1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD 3 * 4 * Copyright (c) 2013-2015 The FreeBSD Foundation 5 * All rights reserved. 6 * 7 * This software was developed by Konstantin Belousov <kib@FreeBSD.org> 8 * under sponsorship from the FreeBSD Foundation. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 20 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 21 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 22 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 23 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 24 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 25 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 26 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 27 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 28 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 29 * SUCH DAMAGE. 30 */ 31 32 #include <sys/cdefs.h> 33 __FBSDID("$FreeBSD$"); 34 35 #include "opt_acpi.h" 36 #if defined(__amd64__) 37 #define DEV_APIC 38 #else 39 #include "opt_apic.h" 40 #endif 41 #include "opt_ddb.h" 42 43 #include <sys/param.h> 44 #include <sys/bus.h> 45 #include <sys/kernel.h> 46 #include <sys/lock.h> 47 #include <sys/malloc.h> 48 #include <sys/memdesc.h> 49 #include <sys/module.h> 50 #include <sys/rman.h> 51 #include <sys/rwlock.h> 52 #include <sys/smp.h> 53 #include <sys/taskqueue.h> 54 #include <sys/tree.h> 55 #include <sys/vmem.h> 56 #include <machine/bus.h> 57 #include <machine/pci_cfgreg.h> 58 #include <contrib/dev/acpica/include/acpi.h> 59 #include <contrib/dev/acpica/include/accommon.h> 60 #include <dev/acpica/acpivar.h> 61 #include <vm/vm.h> 62 #include <vm/vm_extern.h> 63 #include <vm/vm_kern.h> 64 #include <vm/vm_object.h> 65 #include <vm/vm_page.h> 66 #include <vm/vm_pager.h> 67 #include <vm/vm_map.h> 68 #include <x86/include/busdma_impl.h> 69 #include <x86/iommu/intel_reg.h> 70 #include <x86/iommu/busdma_dmar.h> 71 #include <x86/iommu/intel_dmar.h> 72 #include <dev/pci/pcireg.h> 73 #include <dev/pci/pcivar.h> 74 75 #ifdef DEV_APIC 76 #include "pcib_if.h" 77 #include <machine/intr_machdep.h> 78 #include <x86/apicreg.h> 79 #include <x86/apicvar.h> 80 #endif 81 82 #define DMAR_FAULT_IRQ_RID 0 83 #define DMAR_QI_IRQ_RID 1 84 #define DMAR_REG_RID 2 85 86 static devclass_t dmar_devclass; 87 static device_t *dmar_devs; 88 static int dmar_devcnt; 89 90 typedef int (*dmar_iter_t)(ACPI_DMAR_HEADER *, void *); 91 92 static void 93 dmar_iterate_tbl(dmar_iter_t iter, void *arg) 94 { 95 ACPI_TABLE_DMAR *dmartbl; 96 ACPI_DMAR_HEADER *dmarh; 97 char *ptr, *ptrend; 98 ACPI_STATUS status; 99 100 status = AcpiGetTable(ACPI_SIG_DMAR, 1, (ACPI_TABLE_HEADER **)&dmartbl); 101 if (ACPI_FAILURE(status)) 102 return; 103 ptr = (char *)dmartbl + sizeof(*dmartbl); 104 ptrend = (char *)dmartbl + dmartbl->Header.Length; 105 for (;;) { 106 if (ptr >= ptrend) 107 break; 108 dmarh = (ACPI_DMAR_HEADER *)ptr; 109 if (dmarh->Length <= 0) { 110 printf("dmar_identify: corrupted DMAR table, l %d\n", 111 dmarh->Length); 112 break; 113 } 114 ptr += dmarh->Length; 115 if (!iter(dmarh, arg)) 116 break; 117 } 118 AcpiPutTable((ACPI_TABLE_HEADER *)dmartbl); 119 } 120 121 struct find_iter_args { 122 int i; 123 ACPI_DMAR_HARDWARE_UNIT *res; 124 }; 125 126 static int 127 dmar_find_iter(ACPI_DMAR_HEADER *dmarh, void *arg) 128 { 129 struct find_iter_args *fia; 130 131 if (dmarh->Type != ACPI_DMAR_TYPE_HARDWARE_UNIT) 132 return (1); 133 134 fia = arg; 135 if (fia->i == 0) { 136 fia->res = (ACPI_DMAR_HARDWARE_UNIT *)dmarh; 137 return (0); 138 } 139 fia->i--; 140 return (1); 141 } 142 143 static ACPI_DMAR_HARDWARE_UNIT * 144 dmar_find_by_index(int idx) 145 { 146 struct find_iter_args fia; 147 148 fia.i = idx; 149 fia.res = NULL; 150 dmar_iterate_tbl(dmar_find_iter, &fia); 151 return (fia.res); 152 } 153 154 static int 155 dmar_count_iter(ACPI_DMAR_HEADER *dmarh, void *arg) 156 { 157 158 if (dmarh->Type == ACPI_DMAR_TYPE_HARDWARE_UNIT) 159 dmar_devcnt++; 160 return (1); 161 } 162 163 static int dmar_enable = 0; 164 static void 165 dmar_identify(driver_t *driver, device_t parent) 166 { 167 ACPI_TABLE_DMAR *dmartbl; 168 ACPI_DMAR_HARDWARE_UNIT *dmarh; 169 ACPI_STATUS status; 170 int i, error; 171 172 if (acpi_disabled("dmar")) 173 return; 174 TUNABLE_INT_FETCH("hw.dmar.enable", &dmar_enable); 175 if (!dmar_enable) 176 return; 177 #ifdef INVARIANTS 178 TUNABLE_INT_FETCH("hw.dmar.check_free", &dmar_check_free); 179 #endif 180 status = AcpiGetTable(ACPI_SIG_DMAR, 1, (ACPI_TABLE_HEADER **)&dmartbl); 181 if (ACPI_FAILURE(status)) 182 return; 183 haw = dmartbl->Width + 1; 184 if ((1ULL << (haw + 1)) > BUS_SPACE_MAXADDR) 185 dmar_high = BUS_SPACE_MAXADDR; 186 else 187 dmar_high = 1ULL << (haw + 1); 188 if (bootverbose) { 189 printf("DMAR HAW=%d flags=<%b>\n", dmartbl->Width, 190 (unsigned)dmartbl->Flags, 191 "\020\001INTR_REMAP\002X2APIC_OPT_OUT"); 192 } 193 AcpiPutTable((ACPI_TABLE_HEADER *)dmartbl); 194 195 dmar_iterate_tbl(dmar_count_iter, NULL); 196 if (dmar_devcnt == 0) 197 return; 198 dmar_devs = malloc(sizeof(device_t) * dmar_devcnt, M_DEVBUF, 199 M_WAITOK | M_ZERO); 200 for (i = 0; i < dmar_devcnt; i++) { 201 dmarh = dmar_find_by_index(i); 202 if (dmarh == NULL) { 203 printf("dmar_identify: cannot find HWUNIT %d\n", i); 204 continue; 205 } 206 dmar_devs[i] = BUS_ADD_CHILD(parent, 1, "dmar", i); 207 if (dmar_devs[i] == NULL) { 208 printf("dmar_identify: cannot create instance %d\n", i); 209 continue; 210 } 211 error = bus_set_resource(dmar_devs[i], SYS_RES_MEMORY, 212 DMAR_REG_RID, dmarh->Address, PAGE_SIZE); 213 if (error != 0) { 214 printf( 215 "dmar%d: unable to alloc register window at 0x%08jx: error %d\n", 216 i, (uintmax_t)dmarh->Address, error); 217 device_delete_child(parent, dmar_devs[i]); 218 dmar_devs[i] = NULL; 219 } 220 } 221 } 222 223 static int 224 dmar_probe(device_t dev) 225 { 226 227 if (acpi_get_handle(dev) != NULL) 228 return (ENXIO); 229 device_set_desc(dev, "DMA remap"); 230 return (BUS_PROBE_NOWILDCARD); 231 } 232 233 static void 234 dmar_release_intr(device_t dev, struct dmar_unit *unit, int idx) 235 { 236 struct dmar_msi_data *dmd; 237 238 dmd = &unit->intrs[idx]; 239 if (dmd->irq == -1) 240 return; 241 bus_teardown_intr(dev, dmd->irq_res, dmd->intr_handle); 242 bus_release_resource(dev, SYS_RES_IRQ, dmd->irq_rid, dmd->irq_res); 243 bus_delete_resource(dev, SYS_RES_IRQ, dmd->irq_rid); 244 PCIB_RELEASE_MSIX(device_get_parent(device_get_parent(dev)), 245 dev, dmd->irq); 246 dmd->irq = -1; 247 } 248 249 static void 250 dmar_release_resources(device_t dev, struct dmar_unit *unit) 251 { 252 int i; 253 254 dmar_fini_busdma(unit); 255 dmar_fini_irt(unit); 256 dmar_fini_qi(unit); 257 dmar_fini_fault_log(unit); 258 for (i = 0; i < DMAR_INTR_TOTAL; i++) 259 dmar_release_intr(dev, unit, i); 260 if (unit->regs != NULL) { 261 bus_deactivate_resource(dev, SYS_RES_MEMORY, unit->reg_rid, 262 unit->regs); 263 bus_release_resource(dev, SYS_RES_MEMORY, unit->reg_rid, 264 unit->regs); 265 unit->regs = NULL; 266 } 267 if (unit->domids != NULL) { 268 delete_unrhdr(unit->domids); 269 unit->domids = NULL; 270 } 271 if (unit->ctx_obj != NULL) { 272 vm_object_deallocate(unit->ctx_obj); 273 unit->ctx_obj = NULL; 274 } 275 } 276 277 static int 278 dmar_alloc_irq(device_t dev, struct dmar_unit *unit, int idx) 279 { 280 device_t pcib; 281 struct dmar_msi_data *dmd; 282 uint64_t msi_addr; 283 uint32_t msi_data; 284 int error; 285 286 dmd = &unit->intrs[idx]; 287 pcib = device_get_parent(device_get_parent(dev)); /* Really not pcib */ 288 error = PCIB_ALLOC_MSIX(pcib, dev, &dmd->irq); 289 if (error != 0) { 290 device_printf(dev, "cannot allocate %s interrupt, %d\n", 291 dmd->name, error); 292 goto err1; 293 } 294 error = bus_set_resource(dev, SYS_RES_IRQ, dmd->irq_rid, 295 dmd->irq, 1); 296 if (error != 0) { 297 device_printf(dev, "cannot set %s interrupt resource, %d\n", 298 dmd->name, error); 299 goto err2; 300 } 301 dmd->irq_res = bus_alloc_resource_any(dev, SYS_RES_IRQ, 302 &dmd->irq_rid, RF_ACTIVE); 303 if (dmd->irq_res == NULL) { 304 device_printf(dev, 305 "cannot allocate resource for %s interrupt\n", dmd->name); 306 error = ENXIO; 307 goto err3; 308 } 309 error = bus_setup_intr(dev, dmd->irq_res, INTR_TYPE_MISC, 310 dmd->handler, NULL, unit, &dmd->intr_handle); 311 if (error != 0) { 312 device_printf(dev, "cannot setup %s interrupt, %d\n", 313 dmd->name, error); 314 goto err4; 315 } 316 bus_describe_intr(dev, dmd->irq_res, dmd->intr_handle, "%s", dmd->name); 317 error = PCIB_MAP_MSI(pcib, dev, dmd->irq, &msi_addr, &msi_data); 318 if (error != 0) { 319 device_printf(dev, "cannot map %s interrupt, %d\n", 320 dmd->name, error); 321 goto err5; 322 } 323 dmar_write4(unit, dmd->msi_data_reg, msi_data); 324 dmar_write4(unit, dmd->msi_addr_reg, msi_addr); 325 /* Only for xAPIC mode */ 326 dmar_write4(unit, dmd->msi_uaddr_reg, msi_addr >> 32); 327 return (0); 328 329 err5: 330 bus_teardown_intr(dev, dmd->irq_res, dmd->intr_handle); 331 err4: 332 bus_release_resource(dev, SYS_RES_IRQ, dmd->irq_rid, dmd->irq_res); 333 err3: 334 bus_delete_resource(dev, SYS_RES_IRQ, dmd->irq_rid); 335 err2: 336 PCIB_RELEASE_MSIX(pcib, dev, dmd->irq); 337 dmd->irq = -1; 338 err1: 339 return (error); 340 } 341 342 #ifdef DEV_APIC 343 static int 344 dmar_remap_intr(device_t dev, device_t child, u_int irq) 345 { 346 struct dmar_unit *unit; 347 struct dmar_msi_data *dmd; 348 uint64_t msi_addr; 349 uint32_t msi_data; 350 int i, error; 351 352 unit = device_get_softc(dev); 353 for (i = 0; i < DMAR_INTR_TOTAL; i++) { 354 dmd = &unit->intrs[i]; 355 if (irq == dmd->irq) { 356 error = PCIB_MAP_MSI(device_get_parent( 357 device_get_parent(dev)), 358 dev, irq, &msi_addr, &msi_data); 359 if (error != 0) 360 return (error); 361 DMAR_LOCK(unit); 362 (dmd->disable_intr)(unit); 363 dmar_write4(unit, dmd->msi_data_reg, msi_data); 364 dmar_write4(unit, dmd->msi_addr_reg, msi_addr); 365 dmar_write4(unit, dmd->msi_uaddr_reg, msi_addr >> 32); 366 (dmd->enable_intr)(unit); 367 DMAR_UNLOCK(unit); 368 return (0); 369 } 370 } 371 return (ENOENT); 372 } 373 #endif 374 375 static void 376 dmar_print_caps(device_t dev, struct dmar_unit *unit, 377 ACPI_DMAR_HARDWARE_UNIT *dmaru) 378 { 379 uint32_t caphi, ecaphi; 380 381 device_printf(dev, "regs@0x%08jx, ver=%d.%d, seg=%d, flags=<%b>\n", 382 (uintmax_t)dmaru->Address, DMAR_MAJOR_VER(unit->hw_ver), 383 DMAR_MINOR_VER(unit->hw_ver), dmaru->Segment, 384 dmaru->Flags, "\020\001INCLUDE_ALL_PCI"); 385 caphi = unit->hw_cap >> 32; 386 device_printf(dev, "cap=%b,", (u_int)unit->hw_cap, 387 "\020\004AFL\005WBF\006PLMR\007PHMR\010CM\027ZLR\030ISOCH"); 388 printf("%b, ", caphi, "\020\010PSI\027DWD\030DRD\031FL1GP\034PSI"); 389 printf("ndoms=%d, sagaw=%d, mgaw=%d, fro=%d, nfr=%d, superp=%d", 390 DMAR_CAP_ND(unit->hw_cap), DMAR_CAP_SAGAW(unit->hw_cap), 391 DMAR_CAP_MGAW(unit->hw_cap), DMAR_CAP_FRO(unit->hw_cap), 392 DMAR_CAP_NFR(unit->hw_cap), DMAR_CAP_SPS(unit->hw_cap)); 393 if ((unit->hw_cap & DMAR_CAP_PSI) != 0) 394 printf(", mamv=%d", DMAR_CAP_MAMV(unit->hw_cap)); 395 printf("\n"); 396 ecaphi = unit->hw_ecap >> 32; 397 device_printf(dev, "ecap=%b,", (u_int)unit->hw_ecap, 398 "\020\001C\002QI\003DI\004IR\005EIM\007PT\010SC\031ECS\032MTS" 399 "\033NEST\034DIS\035PASID\036PRS\037ERS\040SRS"); 400 printf("%b, ", ecaphi, "\020\002NWFS\003EAFS"); 401 printf("mhmw=%d, iro=%d\n", DMAR_ECAP_MHMV(unit->hw_ecap), 402 DMAR_ECAP_IRO(unit->hw_ecap)); 403 } 404 405 static int 406 dmar_attach(device_t dev) 407 { 408 struct dmar_unit *unit; 409 ACPI_DMAR_HARDWARE_UNIT *dmaru; 410 uint64_t timeout; 411 int i, error; 412 413 unit = device_get_softc(dev); 414 unit->dev = dev; 415 unit->unit = device_get_unit(dev); 416 dmaru = dmar_find_by_index(unit->unit); 417 if (dmaru == NULL) 418 return (EINVAL); 419 unit->segment = dmaru->Segment; 420 unit->base = dmaru->Address; 421 unit->reg_rid = DMAR_REG_RID; 422 unit->regs = bus_alloc_resource_any(dev, SYS_RES_MEMORY, 423 &unit->reg_rid, RF_ACTIVE); 424 if (unit->regs == NULL) { 425 device_printf(dev, "cannot allocate register window\n"); 426 return (ENOMEM); 427 } 428 unit->hw_ver = dmar_read4(unit, DMAR_VER_REG); 429 unit->hw_cap = dmar_read8(unit, DMAR_CAP_REG); 430 unit->hw_ecap = dmar_read8(unit, DMAR_ECAP_REG); 431 if (bootverbose) 432 dmar_print_caps(dev, unit, dmaru); 433 dmar_quirks_post_ident(unit); 434 435 timeout = dmar_get_timeout(); 436 TUNABLE_UINT64_FETCH("hw.dmar.timeout", &timeout); 437 dmar_update_timeout(timeout); 438 439 for (i = 0; i < DMAR_INTR_TOTAL; i++) 440 unit->intrs[i].irq = -1; 441 442 unit->intrs[DMAR_INTR_FAULT].name = "fault"; 443 unit->intrs[DMAR_INTR_FAULT].irq_rid = DMAR_FAULT_IRQ_RID; 444 unit->intrs[DMAR_INTR_FAULT].handler = dmar_fault_intr; 445 unit->intrs[DMAR_INTR_FAULT].msi_data_reg = DMAR_FEDATA_REG; 446 unit->intrs[DMAR_INTR_FAULT].msi_addr_reg = DMAR_FEADDR_REG; 447 unit->intrs[DMAR_INTR_FAULT].msi_uaddr_reg = DMAR_FEUADDR_REG; 448 unit->intrs[DMAR_INTR_FAULT].enable_intr = dmar_enable_fault_intr; 449 unit->intrs[DMAR_INTR_FAULT].disable_intr = dmar_disable_fault_intr; 450 error = dmar_alloc_irq(dev, unit, DMAR_INTR_FAULT); 451 if (error != 0) { 452 dmar_release_resources(dev, unit); 453 return (error); 454 } 455 if (DMAR_HAS_QI(unit)) { 456 unit->intrs[DMAR_INTR_QI].name = "qi"; 457 unit->intrs[DMAR_INTR_QI].irq_rid = DMAR_QI_IRQ_RID; 458 unit->intrs[DMAR_INTR_QI].handler = dmar_qi_intr; 459 unit->intrs[DMAR_INTR_QI].msi_data_reg = DMAR_IEDATA_REG; 460 unit->intrs[DMAR_INTR_QI].msi_addr_reg = DMAR_IEADDR_REG; 461 unit->intrs[DMAR_INTR_QI].msi_uaddr_reg = DMAR_IEUADDR_REG; 462 unit->intrs[DMAR_INTR_QI].enable_intr = dmar_enable_qi_intr; 463 unit->intrs[DMAR_INTR_QI].disable_intr = dmar_disable_qi_intr; 464 error = dmar_alloc_irq(dev, unit, DMAR_INTR_QI); 465 if (error != 0) { 466 dmar_release_resources(dev, unit); 467 return (error); 468 } 469 } 470 471 mtx_init(&unit->lock, "dmarhw", NULL, MTX_DEF); 472 unit->domids = new_unrhdr(0, dmar_nd2mask(DMAR_CAP_ND(unit->hw_cap)), 473 &unit->lock); 474 LIST_INIT(&unit->domains); 475 476 /* 477 * 9.2 "Context Entry": 478 * When Caching Mode (CM) field is reported as Set, the 479 * domain-id value of zero is architecturally reserved. 480 * Software must not use domain-id value of zero 481 * when CM is Set. 482 */ 483 if ((unit->hw_cap & DMAR_CAP_CM) != 0) 484 alloc_unr_specific(unit->domids, 0); 485 486 unit->ctx_obj = vm_pager_allocate(OBJT_PHYS, NULL, IDX_TO_OFF(1 + 487 DMAR_CTX_CNT), 0, 0, NULL); 488 489 /* 490 * Allocate and load the root entry table pointer. Enable the 491 * address translation after the required invalidations are 492 * done. 493 */ 494 dmar_pgalloc(unit->ctx_obj, 0, DMAR_PGF_WAITOK | DMAR_PGF_ZERO); 495 DMAR_LOCK(unit); 496 error = dmar_load_root_entry_ptr(unit); 497 if (error != 0) { 498 DMAR_UNLOCK(unit); 499 dmar_release_resources(dev, unit); 500 return (error); 501 } 502 error = dmar_inv_ctx_glob(unit); 503 if (error != 0) { 504 DMAR_UNLOCK(unit); 505 dmar_release_resources(dev, unit); 506 return (error); 507 } 508 if ((unit->hw_ecap & DMAR_ECAP_DI) != 0) { 509 error = dmar_inv_iotlb_glob(unit); 510 if (error != 0) { 511 DMAR_UNLOCK(unit); 512 dmar_release_resources(dev, unit); 513 return (error); 514 } 515 } 516 517 DMAR_UNLOCK(unit); 518 error = dmar_init_fault_log(unit); 519 if (error != 0) { 520 dmar_release_resources(dev, unit); 521 return (error); 522 } 523 error = dmar_init_qi(unit); 524 if (error != 0) { 525 dmar_release_resources(dev, unit); 526 return (error); 527 } 528 error = dmar_init_irt(unit); 529 if (error != 0) { 530 dmar_release_resources(dev, unit); 531 return (error); 532 } 533 error = dmar_init_busdma(unit); 534 if (error != 0) { 535 dmar_release_resources(dev, unit); 536 return (error); 537 } 538 539 #ifdef NOTYET 540 DMAR_LOCK(unit); 541 error = dmar_enable_translation(unit); 542 if (error != 0) { 543 DMAR_UNLOCK(unit); 544 dmar_release_resources(dev, unit); 545 return (error); 546 } 547 DMAR_UNLOCK(unit); 548 #endif 549 550 return (0); 551 } 552 553 static int 554 dmar_detach(device_t dev) 555 { 556 557 return (EBUSY); 558 } 559 560 static int 561 dmar_suspend(device_t dev) 562 { 563 564 return (0); 565 } 566 567 static int 568 dmar_resume(device_t dev) 569 { 570 571 /* XXXKIB */ 572 return (0); 573 } 574 575 static device_method_t dmar_methods[] = { 576 DEVMETHOD(device_identify, dmar_identify), 577 DEVMETHOD(device_probe, dmar_probe), 578 DEVMETHOD(device_attach, dmar_attach), 579 DEVMETHOD(device_detach, dmar_detach), 580 DEVMETHOD(device_suspend, dmar_suspend), 581 DEVMETHOD(device_resume, dmar_resume), 582 #ifdef DEV_APIC 583 DEVMETHOD(bus_remap_intr, dmar_remap_intr), 584 #endif 585 DEVMETHOD_END 586 }; 587 588 static driver_t dmar_driver = { 589 "dmar", 590 dmar_methods, 591 sizeof(struct dmar_unit), 592 }; 593 594 DRIVER_MODULE(dmar, acpi, dmar_driver, dmar_devclass, 0, 0); 595 MODULE_DEPEND(dmar, acpi, 1, 1, 1); 596 597 static void 598 dmar_print_path(int busno, int depth, const ACPI_DMAR_PCI_PATH *path) 599 { 600 int i; 601 602 printf("[%d, ", busno); 603 for (i = 0; i < depth; i++) { 604 if (i != 0) 605 printf(", "); 606 printf("(%d, %d)", path[i].Device, path[i].Function); 607 } 608 printf("]"); 609 } 610 611 int 612 dmar_dev_depth(device_t child) 613 { 614 devclass_t pci_class; 615 device_t bus, pcib; 616 int depth; 617 618 pci_class = devclass_find("pci"); 619 for (depth = 1; ; depth++) { 620 bus = device_get_parent(child); 621 pcib = device_get_parent(bus); 622 if (device_get_devclass(device_get_parent(pcib)) != 623 pci_class) 624 return (depth); 625 child = pcib; 626 } 627 } 628 629 void 630 dmar_dev_path(device_t child, int *busno, void *path1, int depth) 631 { 632 devclass_t pci_class; 633 device_t bus, pcib; 634 ACPI_DMAR_PCI_PATH *path; 635 636 pci_class = devclass_find("pci"); 637 path = path1; 638 for (depth--; depth != -1; depth--) { 639 path[depth].Device = pci_get_slot(child); 640 path[depth].Function = pci_get_function(child); 641 bus = device_get_parent(child); 642 pcib = device_get_parent(bus); 643 if (device_get_devclass(device_get_parent(pcib)) != 644 pci_class) { 645 /* reached a host bridge */ 646 *busno = pcib_get_bus(bus); 647 return; 648 } 649 child = pcib; 650 } 651 panic("wrong depth"); 652 } 653 654 static int 655 dmar_match_pathes(int busno1, const ACPI_DMAR_PCI_PATH *path1, int depth1, 656 int busno2, const ACPI_DMAR_PCI_PATH *path2, int depth2, 657 enum AcpiDmarScopeType scope_type) 658 { 659 int i, depth; 660 661 if (busno1 != busno2) 662 return (0); 663 if (scope_type == ACPI_DMAR_SCOPE_TYPE_ENDPOINT && depth1 != depth2) 664 return (0); 665 depth = depth1; 666 if (depth2 < depth) 667 depth = depth2; 668 for (i = 0; i < depth; i++) { 669 if (path1[i].Device != path2[i].Device || 670 path1[i].Function != path2[i].Function) 671 return (0); 672 } 673 return (1); 674 } 675 676 static int 677 dmar_match_devscope(ACPI_DMAR_DEVICE_SCOPE *devscope, int dev_busno, 678 const ACPI_DMAR_PCI_PATH *dev_path, int dev_path_len) 679 { 680 ACPI_DMAR_PCI_PATH *path; 681 int path_len; 682 683 if (devscope->Length < sizeof(*devscope)) { 684 printf("dmar_match_devscope: corrupted DMAR table, dl %d\n", 685 devscope->Length); 686 return (-1); 687 } 688 if (devscope->EntryType != ACPI_DMAR_SCOPE_TYPE_ENDPOINT && 689 devscope->EntryType != ACPI_DMAR_SCOPE_TYPE_BRIDGE) 690 return (0); 691 path_len = devscope->Length - sizeof(*devscope); 692 if (path_len % 2 != 0) { 693 printf("dmar_match_devscope: corrupted DMAR table, dl %d\n", 694 devscope->Length); 695 return (-1); 696 } 697 path_len /= 2; 698 path = (ACPI_DMAR_PCI_PATH *)(devscope + 1); 699 if (path_len == 0) { 700 printf("dmar_match_devscope: corrupted DMAR table, dl %d\n", 701 devscope->Length); 702 return (-1); 703 } 704 705 return (dmar_match_pathes(devscope->Bus, path, path_len, dev_busno, 706 dev_path, dev_path_len, devscope->EntryType)); 707 } 708 709 static bool 710 dmar_match_by_path(struct dmar_unit *unit, int dev_domain, int dev_busno, 711 const ACPI_DMAR_PCI_PATH *dev_path, int dev_path_len, const char **banner) 712 { 713 ACPI_DMAR_HARDWARE_UNIT *dmarh; 714 ACPI_DMAR_DEVICE_SCOPE *devscope; 715 char *ptr, *ptrend; 716 int match; 717 718 dmarh = dmar_find_by_index(unit->unit); 719 if (dmarh == NULL) 720 return (false); 721 if (dmarh->Segment != dev_domain) 722 return (false); 723 if ((dmarh->Flags & ACPI_DMAR_INCLUDE_ALL) != 0) { 724 if (banner != NULL) 725 *banner = "INCLUDE_ALL"; 726 return (true); 727 } 728 ptr = (char *)dmarh + sizeof(*dmarh); 729 ptrend = (char *)dmarh + dmarh->Header.Length; 730 while (ptr < ptrend) { 731 devscope = (ACPI_DMAR_DEVICE_SCOPE *)ptr; 732 ptr += devscope->Length; 733 match = dmar_match_devscope(devscope, dev_busno, dev_path, 734 dev_path_len); 735 if (match == -1) 736 return (false); 737 if (match == 1) { 738 if (banner != NULL) 739 *banner = "specific match"; 740 return (true); 741 } 742 } 743 return (false); 744 } 745 746 static struct dmar_unit * 747 dmar_find_by_scope(int dev_domain, int dev_busno, 748 const ACPI_DMAR_PCI_PATH *dev_path, int dev_path_len) 749 { 750 struct dmar_unit *unit; 751 int i; 752 753 for (i = 0; i < dmar_devcnt; i++) { 754 if (dmar_devs[i] == NULL) 755 continue; 756 unit = device_get_softc(dmar_devs[i]); 757 if (dmar_match_by_path(unit, dev_domain, dev_busno, dev_path, 758 dev_path_len, NULL)) 759 return (unit); 760 } 761 return (NULL); 762 } 763 764 struct dmar_unit * 765 dmar_find(device_t dev, bool verbose) 766 { 767 device_t dmar_dev; 768 struct dmar_unit *unit; 769 const char *banner; 770 int i, dev_domain, dev_busno, dev_path_len; 771 772 dmar_dev = NULL; 773 dev_domain = pci_get_domain(dev); 774 dev_path_len = dmar_dev_depth(dev); 775 ACPI_DMAR_PCI_PATH dev_path[dev_path_len]; 776 dmar_dev_path(dev, &dev_busno, dev_path, dev_path_len); 777 banner = ""; 778 779 for (i = 0; i < dmar_devcnt; i++) { 780 if (dmar_devs[i] == NULL) 781 continue; 782 unit = device_get_softc(dmar_devs[i]); 783 if (dmar_match_by_path(unit, dev_domain, dev_busno, 784 dev_path, dev_path_len, &banner)) 785 break; 786 } 787 if (i == dmar_devcnt) 788 return (NULL); 789 790 if (verbose) { 791 device_printf(dev, "pci%d:%d:%d:%d matched dmar%d by %s", 792 dev_domain, pci_get_bus(dev), pci_get_slot(dev), 793 pci_get_function(dev), unit->unit, banner); 794 printf(" scope path "); 795 dmar_print_path(dev_busno, dev_path_len, dev_path); 796 printf("\n"); 797 } 798 return (unit); 799 } 800 801 static struct dmar_unit * 802 dmar_find_nonpci(u_int id, u_int entry_type, uint16_t *rid) 803 { 804 device_t dmar_dev; 805 struct dmar_unit *unit; 806 ACPI_DMAR_HARDWARE_UNIT *dmarh; 807 ACPI_DMAR_DEVICE_SCOPE *devscope; 808 ACPI_DMAR_PCI_PATH *path; 809 char *ptr, *ptrend; 810 #ifdef DEV_APIC 811 int error; 812 #endif 813 int i; 814 815 for (i = 0; i < dmar_devcnt; i++) { 816 dmar_dev = dmar_devs[i]; 817 if (dmar_dev == NULL) 818 continue; 819 unit = (struct dmar_unit *)device_get_softc(dmar_dev); 820 dmarh = dmar_find_by_index(i); 821 if (dmarh == NULL) 822 continue; 823 ptr = (char *)dmarh + sizeof(*dmarh); 824 ptrend = (char *)dmarh + dmarh->Header.Length; 825 for (;;) { 826 if (ptr >= ptrend) 827 break; 828 devscope = (ACPI_DMAR_DEVICE_SCOPE *)ptr; 829 ptr += devscope->Length; 830 if (devscope->EntryType != entry_type) 831 continue; 832 if (devscope->EnumerationId != id) 833 continue; 834 #ifdef DEV_APIC 835 if (entry_type == ACPI_DMAR_SCOPE_TYPE_IOAPIC) { 836 error = ioapic_get_rid(id, rid); 837 /* 838 * If our IOAPIC has PCI bindings then 839 * use the PCI device rid. 840 */ 841 if (error == 0) 842 return (unit); 843 } 844 #endif 845 if (devscope->Length - sizeof(ACPI_DMAR_DEVICE_SCOPE) 846 == 2) { 847 if (rid != NULL) { 848 path = (ACPI_DMAR_PCI_PATH *) 849 (devscope + 1); 850 *rid = PCI_RID(devscope->Bus, 851 path->Device, path->Function); 852 } 853 return (unit); 854 } 855 printf( 856 "dmar_find_nonpci: id %d type %d path length != 2\n", 857 id, entry_type); 858 break; 859 } 860 } 861 return (NULL); 862 } 863 864 865 struct dmar_unit * 866 dmar_find_hpet(device_t dev, uint16_t *rid) 867 { 868 869 return (dmar_find_nonpci(hpet_get_uid(dev), ACPI_DMAR_SCOPE_TYPE_HPET, 870 rid)); 871 } 872 873 struct dmar_unit * 874 dmar_find_ioapic(u_int apic_id, uint16_t *rid) 875 { 876 877 return (dmar_find_nonpci(apic_id, ACPI_DMAR_SCOPE_TYPE_IOAPIC, rid)); 878 } 879 880 struct rmrr_iter_args { 881 struct dmar_domain *domain; 882 int dev_domain; 883 int dev_busno; 884 const ACPI_DMAR_PCI_PATH *dev_path; 885 int dev_path_len; 886 struct dmar_map_entries_tailq *rmrr_entries; 887 }; 888 889 static int 890 dmar_rmrr_iter(ACPI_DMAR_HEADER *dmarh, void *arg) 891 { 892 struct rmrr_iter_args *ria; 893 ACPI_DMAR_RESERVED_MEMORY *resmem; 894 ACPI_DMAR_DEVICE_SCOPE *devscope; 895 struct dmar_map_entry *entry; 896 char *ptr, *ptrend; 897 int match; 898 899 if (dmarh->Type != ACPI_DMAR_TYPE_RESERVED_MEMORY) 900 return (1); 901 902 ria = arg; 903 resmem = (ACPI_DMAR_RESERVED_MEMORY *)dmarh; 904 if (resmem->Segment != ria->dev_domain) 905 return (1); 906 907 ptr = (char *)resmem + sizeof(*resmem); 908 ptrend = (char *)resmem + resmem->Header.Length; 909 for (;;) { 910 if (ptr >= ptrend) 911 break; 912 devscope = (ACPI_DMAR_DEVICE_SCOPE *)ptr; 913 ptr += devscope->Length; 914 match = dmar_match_devscope(devscope, ria->dev_busno, 915 ria->dev_path, ria->dev_path_len); 916 if (match == 1) { 917 entry = dmar_gas_alloc_entry(ria->domain, 918 DMAR_PGF_WAITOK); 919 entry->start = resmem->BaseAddress; 920 /* The RMRR entry end address is inclusive. */ 921 entry->end = resmem->EndAddress; 922 TAILQ_INSERT_TAIL(ria->rmrr_entries, entry, 923 unroll_link); 924 } 925 } 926 927 return (1); 928 } 929 930 void 931 dmar_dev_parse_rmrr(struct dmar_domain *domain, int dev_domain, int dev_busno, 932 const void *dev_path, int dev_path_len, 933 struct dmar_map_entries_tailq *rmrr_entries) 934 { 935 struct rmrr_iter_args ria; 936 937 ria.domain = domain; 938 ria.dev_domain = dev_domain; 939 ria.dev_busno = dev_busno; 940 ria.dev_path = (const ACPI_DMAR_PCI_PATH *)dev_path; 941 ria.dev_path_len = dev_path_len; 942 ria.rmrr_entries = rmrr_entries; 943 dmar_iterate_tbl(dmar_rmrr_iter, &ria); 944 } 945 946 struct inst_rmrr_iter_args { 947 struct dmar_unit *dmar; 948 }; 949 950 static device_t 951 dmar_path_dev(int segment, int path_len, int busno, 952 const ACPI_DMAR_PCI_PATH *path, uint16_t *rid) 953 { 954 device_t dev; 955 int i; 956 957 dev = NULL; 958 for (i = 0; i < path_len; i++) { 959 dev = pci_find_dbsf(segment, busno, path->Device, 960 path->Function); 961 if (i != path_len - 1) { 962 busno = pci_cfgregread(busno, path->Device, 963 path->Function, PCIR_SECBUS_1, 1); 964 path++; 965 } 966 } 967 *rid = PCI_RID(busno, path->Device, path->Function); 968 return (dev); 969 } 970 971 static int 972 dmar_inst_rmrr_iter(ACPI_DMAR_HEADER *dmarh, void *arg) 973 { 974 const ACPI_DMAR_RESERVED_MEMORY *resmem; 975 const ACPI_DMAR_DEVICE_SCOPE *devscope; 976 struct inst_rmrr_iter_args *iria; 977 const char *ptr, *ptrend; 978 device_t dev; 979 struct dmar_unit *unit; 980 int dev_path_len; 981 uint16_t rid; 982 983 iria = arg; 984 985 if (dmarh->Type != ACPI_DMAR_TYPE_RESERVED_MEMORY) 986 return (1); 987 988 resmem = (ACPI_DMAR_RESERVED_MEMORY *)dmarh; 989 if (resmem->Segment != iria->dmar->segment) 990 return (1); 991 992 ptr = (const char *)resmem + sizeof(*resmem); 993 ptrend = (const char *)resmem + resmem->Header.Length; 994 for (;;) { 995 if (ptr >= ptrend) 996 break; 997 devscope = (const ACPI_DMAR_DEVICE_SCOPE *)ptr; 998 ptr += devscope->Length; 999 /* XXXKIB bridge */ 1000 if (devscope->EntryType != ACPI_DMAR_SCOPE_TYPE_ENDPOINT) 1001 continue; 1002 rid = 0; 1003 dev_path_len = (devscope->Length - 1004 sizeof(ACPI_DMAR_DEVICE_SCOPE)) / 2; 1005 dev = dmar_path_dev(resmem->Segment, dev_path_len, 1006 devscope->Bus, 1007 (const ACPI_DMAR_PCI_PATH *)(devscope + 1), &rid); 1008 if (dev == NULL) { 1009 if (bootverbose) { 1010 printf("dmar%d no dev found for RMRR " 1011 "[%#jx, %#jx] rid %#x scope path ", 1012 iria->dmar->unit, 1013 (uintmax_t)resmem->BaseAddress, 1014 (uintmax_t)resmem->EndAddress, 1015 rid); 1016 dmar_print_path(devscope->Bus, dev_path_len, 1017 (const ACPI_DMAR_PCI_PATH *)(devscope + 1)); 1018 printf("\n"); 1019 } 1020 unit = dmar_find_by_scope(resmem->Segment, 1021 devscope->Bus, 1022 (const ACPI_DMAR_PCI_PATH *)(devscope + 1), 1023 dev_path_len); 1024 if (iria->dmar != unit) 1025 continue; 1026 dmar_get_ctx_for_devpath(iria->dmar, rid, 1027 resmem->Segment, devscope->Bus, 1028 (const ACPI_DMAR_PCI_PATH *)(devscope + 1), 1029 dev_path_len, false, true); 1030 } else { 1031 unit = dmar_find(dev, false); 1032 if (iria->dmar != unit) 1033 continue; 1034 dmar_instantiate_ctx(iria->dmar, dev, true); 1035 } 1036 } 1037 1038 return (1); 1039 1040 } 1041 1042 /* 1043 * Pre-create all contexts for the DMAR which have RMRR entries. 1044 */ 1045 int 1046 dmar_instantiate_rmrr_ctxs(struct dmar_unit *dmar) 1047 { 1048 struct inst_rmrr_iter_args iria; 1049 int error; 1050 1051 if (!dmar_barrier_enter(dmar, DMAR_BARRIER_RMRR)) 1052 return (0); 1053 1054 error = 0; 1055 iria.dmar = dmar; 1056 dmar_iterate_tbl(dmar_inst_rmrr_iter, &iria); 1057 DMAR_LOCK(dmar); 1058 if (!LIST_EMPTY(&dmar->domains)) { 1059 KASSERT((dmar->hw_gcmd & DMAR_GCMD_TE) == 0, 1060 ("dmar%d: RMRR not handled but translation is already enabled", 1061 dmar->unit)); 1062 error = dmar_enable_translation(dmar); 1063 if (bootverbose) { 1064 if (error == 0) { 1065 printf("dmar%d: enabled translation\n", 1066 dmar->unit); 1067 } else { 1068 printf("dmar%d: enabling translation failed, " 1069 "error %d\n", dmar->unit, error); 1070 } 1071 } 1072 } 1073 dmar_barrier_exit(dmar, DMAR_BARRIER_RMRR); 1074 return (error); 1075 } 1076 1077 #ifdef DDB 1078 #include <ddb/ddb.h> 1079 #include <ddb/db_lex.h> 1080 1081 static void 1082 dmar_print_domain_entry(const struct dmar_map_entry *entry) 1083 { 1084 struct dmar_map_entry *l, *r; 1085 1086 db_printf( 1087 " start %jx end %jx free_after %jx free_down %jx flags %x ", 1088 entry->start, entry->end, entry->free_after, entry->free_down, 1089 entry->flags); 1090 db_printf("left "); 1091 l = RB_LEFT(entry, rb_entry); 1092 if (l == NULL) 1093 db_printf("NULL "); 1094 else 1095 db_printf("%jx ", l->start); 1096 db_printf("right "); 1097 r = RB_RIGHT(entry, rb_entry); 1098 if (r == NULL) 1099 db_printf("NULL"); 1100 else 1101 db_printf("%jx", r->start); 1102 db_printf("\n"); 1103 } 1104 1105 static void 1106 dmar_print_ctx(struct dmar_ctx *ctx) 1107 { 1108 1109 db_printf( 1110 " @%p pci%d:%d:%d refs %d flags %x loads %lu unloads %lu\n", 1111 ctx, pci_get_bus(ctx->ctx_tag.owner), 1112 pci_get_slot(ctx->ctx_tag.owner), 1113 pci_get_function(ctx->ctx_tag.owner), ctx->refs, ctx->flags, 1114 ctx->loads, ctx->unloads); 1115 } 1116 1117 static void 1118 dmar_print_domain(struct dmar_domain *domain, bool show_mappings) 1119 { 1120 struct dmar_map_entry *entry; 1121 struct dmar_ctx *ctx; 1122 1123 db_printf( 1124 " @%p dom %d mgaw %d agaw %d pglvl %d end %jx refs %d\n" 1125 " ctx_cnt %d flags %x pgobj %p map_ents %u\n", 1126 domain, domain->domain, domain->mgaw, domain->agaw, domain->pglvl, 1127 (uintmax_t)domain->end, domain->refs, domain->ctx_cnt, 1128 domain->flags, domain->pgtbl_obj, domain->entries_cnt); 1129 if (!LIST_EMPTY(&domain->contexts)) { 1130 db_printf(" Contexts:\n"); 1131 LIST_FOREACH(ctx, &domain->contexts, link) 1132 dmar_print_ctx(ctx); 1133 } 1134 if (!show_mappings) 1135 return; 1136 db_printf(" mapped:\n"); 1137 RB_FOREACH(entry, dmar_gas_entries_tree, &domain->rb_root) { 1138 dmar_print_domain_entry(entry); 1139 if (db_pager_quit) 1140 break; 1141 } 1142 if (db_pager_quit) 1143 return; 1144 db_printf(" unloading:\n"); 1145 TAILQ_FOREACH(entry, &domain->unload_entries, dmamap_link) { 1146 dmar_print_domain_entry(entry); 1147 if (db_pager_quit) 1148 break; 1149 } 1150 } 1151 1152 DB_FUNC(dmar_domain, db_dmar_print_domain, db_show_table, CS_OWN, NULL) 1153 { 1154 struct dmar_unit *unit; 1155 struct dmar_domain *domain; 1156 struct dmar_ctx *ctx; 1157 bool show_mappings, valid; 1158 int pci_domain, bus, device, function, i, t; 1159 db_expr_t radix; 1160 1161 valid = false; 1162 radix = db_radix; 1163 db_radix = 10; 1164 t = db_read_token(); 1165 if (t == tSLASH) { 1166 t = db_read_token(); 1167 if (t != tIDENT) { 1168 db_printf("Bad modifier\n"); 1169 db_radix = radix; 1170 db_skip_to_eol(); 1171 return; 1172 } 1173 show_mappings = strchr(db_tok_string, 'm') != NULL; 1174 t = db_read_token(); 1175 } else { 1176 show_mappings = false; 1177 } 1178 if (t == tNUMBER) { 1179 pci_domain = db_tok_number; 1180 t = db_read_token(); 1181 if (t == tNUMBER) { 1182 bus = db_tok_number; 1183 t = db_read_token(); 1184 if (t == tNUMBER) { 1185 device = db_tok_number; 1186 t = db_read_token(); 1187 if (t == tNUMBER) { 1188 function = db_tok_number; 1189 valid = true; 1190 } 1191 } 1192 } 1193 } 1194 db_radix = radix; 1195 db_skip_to_eol(); 1196 if (!valid) { 1197 db_printf("usage: show dmar_domain [/m] " 1198 "<domain> <bus> <device> <func>\n"); 1199 return; 1200 } 1201 for (i = 0; i < dmar_devcnt; i++) { 1202 unit = device_get_softc(dmar_devs[i]); 1203 LIST_FOREACH(domain, &unit->domains, link) { 1204 LIST_FOREACH(ctx, &domain->contexts, link) { 1205 if (pci_domain == unit->segment && 1206 bus == pci_get_bus(ctx->ctx_tag.owner) && 1207 device == 1208 pci_get_slot(ctx->ctx_tag.owner) && 1209 function == 1210 pci_get_function(ctx->ctx_tag.owner)) { 1211 dmar_print_domain(domain, 1212 show_mappings); 1213 goto out; 1214 } 1215 } 1216 } 1217 } 1218 out:; 1219 } 1220 1221 static void 1222 dmar_print_one(int idx, bool show_domains, bool show_mappings) 1223 { 1224 struct dmar_unit *unit; 1225 struct dmar_domain *domain; 1226 int i, frir; 1227 1228 unit = device_get_softc(dmar_devs[idx]); 1229 db_printf("dmar%d at %p, root at 0x%jx, ver 0x%x\n", unit->unit, unit, 1230 dmar_read8(unit, DMAR_RTADDR_REG), dmar_read4(unit, DMAR_VER_REG)); 1231 db_printf("cap 0x%jx ecap 0x%jx gsts 0x%x fsts 0x%x fectl 0x%x\n", 1232 (uintmax_t)dmar_read8(unit, DMAR_CAP_REG), 1233 (uintmax_t)dmar_read8(unit, DMAR_ECAP_REG), 1234 dmar_read4(unit, DMAR_GSTS_REG), 1235 dmar_read4(unit, DMAR_FSTS_REG), 1236 dmar_read4(unit, DMAR_FECTL_REG)); 1237 if (unit->ir_enabled) { 1238 db_printf("ir is enabled; IRT @%p phys 0x%jx maxcnt %d\n", 1239 unit->irt, (uintmax_t)unit->irt_phys, unit->irte_cnt); 1240 } 1241 db_printf("fed 0x%x fea 0x%x feua 0x%x\n", 1242 dmar_read4(unit, DMAR_FEDATA_REG), 1243 dmar_read4(unit, DMAR_FEADDR_REG), 1244 dmar_read4(unit, DMAR_FEUADDR_REG)); 1245 db_printf("primary fault log:\n"); 1246 for (i = 0; i < DMAR_CAP_NFR(unit->hw_cap); i++) { 1247 frir = (DMAR_CAP_FRO(unit->hw_cap) + i) * 16; 1248 db_printf(" %d at 0x%x: %jx %jx\n", i, frir, 1249 (uintmax_t)dmar_read8(unit, frir), 1250 (uintmax_t)dmar_read8(unit, frir + 8)); 1251 } 1252 if (DMAR_HAS_QI(unit)) { 1253 db_printf("ied 0x%x iea 0x%x ieua 0x%x\n", 1254 dmar_read4(unit, DMAR_IEDATA_REG), 1255 dmar_read4(unit, DMAR_IEADDR_REG), 1256 dmar_read4(unit, DMAR_IEUADDR_REG)); 1257 if (unit->qi_enabled) { 1258 db_printf("qi is enabled: queue @0x%jx (IQA 0x%jx) " 1259 "size 0x%jx\n" 1260 " head 0x%x tail 0x%x avail 0x%x status 0x%x ctrl 0x%x\n" 1261 " hw compl 0x%x@%p/phys@%jx next seq 0x%x gen 0x%x\n", 1262 (uintmax_t)unit->inv_queue, 1263 (uintmax_t)dmar_read8(unit, DMAR_IQA_REG), 1264 (uintmax_t)unit->inv_queue_size, 1265 dmar_read4(unit, DMAR_IQH_REG), 1266 dmar_read4(unit, DMAR_IQT_REG), 1267 unit->inv_queue_avail, 1268 dmar_read4(unit, DMAR_ICS_REG), 1269 dmar_read4(unit, DMAR_IECTL_REG), 1270 unit->inv_waitd_seq_hw, 1271 &unit->inv_waitd_seq_hw, 1272 (uintmax_t)unit->inv_waitd_seq_hw_phys, 1273 unit->inv_waitd_seq, 1274 unit->inv_waitd_gen); 1275 } else { 1276 db_printf("qi is disabled\n"); 1277 } 1278 } 1279 if (show_domains) { 1280 db_printf("domains:\n"); 1281 LIST_FOREACH(domain, &unit->domains, link) { 1282 dmar_print_domain(domain, show_mappings); 1283 if (db_pager_quit) 1284 break; 1285 } 1286 } 1287 } 1288 1289 DB_SHOW_COMMAND(dmar, db_dmar_print) 1290 { 1291 bool show_domains, show_mappings; 1292 1293 show_domains = strchr(modif, 'd') != NULL; 1294 show_mappings = strchr(modif, 'm') != NULL; 1295 if (!have_addr) { 1296 db_printf("usage: show dmar [/d] [/m] index\n"); 1297 return; 1298 } 1299 dmar_print_one((int)addr, show_domains, show_mappings); 1300 } 1301 1302 DB_SHOW_ALL_COMMAND(dmars, db_show_all_dmars) 1303 { 1304 int i; 1305 bool show_domains, show_mappings; 1306 1307 show_domains = strchr(modif, 'd') != NULL; 1308 show_mappings = strchr(modif, 'm') != NULL; 1309 1310 for (i = 0; i < dmar_devcnt; i++) { 1311 dmar_print_one(i, show_domains, show_mappings); 1312 if (db_pager_quit) 1313 break; 1314 } 1315 } 1316 #endif 1317