1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD 3 * 4 * Copyright (c) 2013-2015 The FreeBSD Foundation 5 * All rights reserved. 6 * 7 * This software was developed by Konstantin Belousov <kib@FreeBSD.org> 8 * under sponsorship from the FreeBSD Foundation. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 20 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 21 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 22 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 23 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 24 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 25 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 26 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 27 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 28 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 29 * SUCH DAMAGE. 30 */ 31 32 #include <sys/cdefs.h> 33 __FBSDID("$FreeBSD$"); 34 35 #include "opt_acpi.h" 36 #if defined(__amd64__) 37 #define DEV_APIC 38 #else 39 #include "opt_apic.h" 40 #endif 41 #include "opt_ddb.h" 42 43 #include <sys/param.h> 44 #include <sys/bus.h> 45 #include <sys/kernel.h> 46 #include <sys/lock.h> 47 #include <sys/malloc.h> 48 #include <sys/memdesc.h> 49 #include <sys/module.h> 50 #include <sys/mutex.h> 51 #include <sys/rman.h> 52 #include <sys/rwlock.h> 53 #include <sys/smp.h> 54 #include <sys/taskqueue.h> 55 #include <sys/tree.h> 56 #include <sys/vmem.h> 57 #include <machine/bus.h> 58 #include <machine/pci_cfgreg.h> 59 #include <contrib/dev/acpica/include/acpi.h> 60 #include <contrib/dev/acpica/include/accommon.h> 61 #include <dev/acpica/acpivar.h> 62 #include <vm/vm.h> 63 #include <vm/vm_extern.h> 64 #include <vm/vm_kern.h> 65 #include <vm/vm_object.h> 66 #include <vm/vm_page.h> 67 #include <vm/vm_pager.h> 68 #include <vm/vm_map.h> 69 #include <x86/include/busdma_impl.h> 70 #include <x86/iommu/intel_reg.h> 71 #include <x86/iommu/busdma_dmar.h> 72 #include <dev/pci/pcireg.h> 73 #include <dev/pci/pcivar.h> 74 #include <x86/iommu/intel_dmar.h> 75 76 #ifdef DEV_APIC 77 #include "pcib_if.h" 78 #include <machine/intr_machdep.h> 79 #include <x86/apicreg.h> 80 #include <x86/apicvar.h> 81 #endif 82 83 #define DMAR_FAULT_IRQ_RID 0 84 #define DMAR_QI_IRQ_RID 1 85 #define DMAR_REG_RID 2 86 87 static devclass_t dmar_devclass; 88 static device_t *dmar_devs; 89 static int dmar_devcnt; 90 91 typedef int (*dmar_iter_t)(ACPI_DMAR_HEADER *, void *); 92 93 static void 94 dmar_iterate_tbl(dmar_iter_t iter, void *arg) 95 { 96 ACPI_TABLE_DMAR *dmartbl; 97 ACPI_DMAR_HEADER *dmarh; 98 char *ptr, *ptrend; 99 ACPI_STATUS status; 100 101 status = AcpiGetTable(ACPI_SIG_DMAR, 1, (ACPI_TABLE_HEADER **)&dmartbl); 102 if (ACPI_FAILURE(status)) 103 return; 104 ptr = (char *)dmartbl + sizeof(*dmartbl); 105 ptrend = (char *)dmartbl + dmartbl->Header.Length; 106 for (;;) { 107 if (ptr >= ptrend) 108 break; 109 dmarh = (ACPI_DMAR_HEADER *)ptr; 110 if (dmarh->Length <= 0) { 111 printf("dmar_identify: corrupted DMAR table, l %d\n", 112 dmarh->Length); 113 break; 114 } 115 ptr += dmarh->Length; 116 if (!iter(dmarh, arg)) 117 break; 118 } 119 AcpiPutTable((ACPI_TABLE_HEADER *)dmartbl); 120 } 121 122 struct find_iter_args { 123 int i; 124 ACPI_DMAR_HARDWARE_UNIT *res; 125 }; 126 127 static int 128 dmar_find_iter(ACPI_DMAR_HEADER *dmarh, void *arg) 129 { 130 struct find_iter_args *fia; 131 132 if (dmarh->Type != ACPI_DMAR_TYPE_HARDWARE_UNIT) 133 return (1); 134 135 fia = arg; 136 if (fia->i == 0) { 137 fia->res = (ACPI_DMAR_HARDWARE_UNIT *)dmarh; 138 return (0); 139 } 140 fia->i--; 141 return (1); 142 } 143 144 static ACPI_DMAR_HARDWARE_UNIT * 145 dmar_find_by_index(int idx) 146 { 147 struct find_iter_args fia; 148 149 fia.i = idx; 150 fia.res = NULL; 151 dmar_iterate_tbl(dmar_find_iter, &fia); 152 return (fia.res); 153 } 154 155 static int 156 dmar_count_iter(ACPI_DMAR_HEADER *dmarh, void *arg) 157 { 158 159 if (dmarh->Type == ACPI_DMAR_TYPE_HARDWARE_UNIT) 160 dmar_devcnt++; 161 return (1); 162 } 163 164 static int dmar_enable = 0; 165 static void 166 dmar_identify(driver_t *driver, device_t parent) 167 { 168 ACPI_TABLE_DMAR *dmartbl; 169 ACPI_DMAR_HARDWARE_UNIT *dmarh; 170 ACPI_STATUS status; 171 int i, error; 172 173 if (acpi_disabled("dmar")) 174 return; 175 TUNABLE_INT_FETCH("hw.dmar.enable", &dmar_enable); 176 if (!dmar_enable) 177 return; 178 #ifdef INVARIANTS 179 TUNABLE_INT_FETCH("hw.dmar.check_free", &dmar_check_free); 180 #endif 181 status = AcpiGetTable(ACPI_SIG_DMAR, 1, (ACPI_TABLE_HEADER **)&dmartbl); 182 if (ACPI_FAILURE(status)) 183 return; 184 haw = dmartbl->Width + 1; 185 if ((1ULL << (haw + 1)) > BUS_SPACE_MAXADDR) 186 dmar_high = BUS_SPACE_MAXADDR; 187 else 188 dmar_high = 1ULL << (haw + 1); 189 if (bootverbose) { 190 printf("DMAR HAW=%d flags=<%b>\n", dmartbl->Width, 191 (unsigned)dmartbl->Flags, 192 "\020\001INTR_REMAP\002X2APIC_OPT_OUT"); 193 } 194 AcpiPutTable((ACPI_TABLE_HEADER *)dmartbl); 195 196 dmar_iterate_tbl(dmar_count_iter, NULL); 197 if (dmar_devcnt == 0) 198 return; 199 dmar_devs = malloc(sizeof(device_t) * dmar_devcnt, M_DEVBUF, 200 M_WAITOK | M_ZERO); 201 for (i = 0; i < dmar_devcnt; i++) { 202 dmarh = dmar_find_by_index(i); 203 if (dmarh == NULL) { 204 printf("dmar_identify: cannot find HWUNIT %d\n", i); 205 continue; 206 } 207 dmar_devs[i] = BUS_ADD_CHILD(parent, 1, "dmar", i); 208 if (dmar_devs[i] == NULL) { 209 printf("dmar_identify: cannot create instance %d\n", i); 210 continue; 211 } 212 error = bus_set_resource(dmar_devs[i], SYS_RES_MEMORY, 213 DMAR_REG_RID, dmarh->Address, PAGE_SIZE); 214 if (error != 0) { 215 printf( 216 "dmar%d: unable to alloc register window at 0x%08jx: error %d\n", 217 i, (uintmax_t)dmarh->Address, error); 218 device_delete_child(parent, dmar_devs[i]); 219 dmar_devs[i] = NULL; 220 } 221 } 222 } 223 224 static int 225 dmar_probe(device_t dev) 226 { 227 228 if (acpi_get_handle(dev) != NULL) 229 return (ENXIO); 230 device_set_desc(dev, "DMA remap"); 231 return (BUS_PROBE_NOWILDCARD); 232 } 233 234 static void 235 dmar_release_intr(device_t dev, struct dmar_unit *unit, int idx) 236 { 237 struct dmar_msi_data *dmd; 238 239 dmd = &unit->intrs[idx]; 240 if (dmd->irq == -1) 241 return; 242 bus_teardown_intr(dev, dmd->irq_res, dmd->intr_handle); 243 bus_release_resource(dev, SYS_RES_IRQ, dmd->irq_rid, dmd->irq_res); 244 bus_delete_resource(dev, SYS_RES_IRQ, dmd->irq_rid); 245 PCIB_RELEASE_MSIX(device_get_parent(device_get_parent(dev)), 246 dev, dmd->irq); 247 dmd->irq = -1; 248 } 249 250 static void 251 dmar_release_resources(device_t dev, struct dmar_unit *unit) 252 { 253 int i; 254 255 iommu_fini_busdma(&unit->iommu); 256 dmar_fini_irt(unit); 257 dmar_fini_qi(unit); 258 dmar_fini_fault_log(unit); 259 for (i = 0; i < DMAR_INTR_TOTAL; i++) 260 dmar_release_intr(dev, unit, i); 261 if (unit->regs != NULL) { 262 bus_deactivate_resource(dev, SYS_RES_MEMORY, unit->reg_rid, 263 unit->regs); 264 bus_release_resource(dev, SYS_RES_MEMORY, unit->reg_rid, 265 unit->regs); 266 unit->regs = NULL; 267 } 268 if (unit->domids != NULL) { 269 delete_unrhdr(unit->domids); 270 unit->domids = NULL; 271 } 272 if (unit->ctx_obj != NULL) { 273 vm_object_deallocate(unit->ctx_obj); 274 unit->ctx_obj = NULL; 275 } 276 } 277 278 static int 279 dmar_alloc_irq(device_t dev, struct dmar_unit *unit, int idx) 280 { 281 device_t pcib; 282 struct dmar_msi_data *dmd; 283 uint64_t msi_addr; 284 uint32_t msi_data; 285 int error; 286 287 dmd = &unit->intrs[idx]; 288 pcib = device_get_parent(device_get_parent(dev)); /* Really not pcib */ 289 error = PCIB_ALLOC_MSIX(pcib, dev, &dmd->irq); 290 if (error != 0) { 291 device_printf(dev, "cannot allocate %s interrupt, %d\n", 292 dmd->name, error); 293 goto err1; 294 } 295 error = bus_set_resource(dev, SYS_RES_IRQ, dmd->irq_rid, 296 dmd->irq, 1); 297 if (error != 0) { 298 device_printf(dev, "cannot set %s interrupt resource, %d\n", 299 dmd->name, error); 300 goto err2; 301 } 302 dmd->irq_res = bus_alloc_resource_any(dev, SYS_RES_IRQ, 303 &dmd->irq_rid, RF_ACTIVE); 304 if (dmd->irq_res == NULL) { 305 device_printf(dev, 306 "cannot allocate resource for %s interrupt\n", dmd->name); 307 error = ENXIO; 308 goto err3; 309 } 310 error = bus_setup_intr(dev, dmd->irq_res, INTR_TYPE_MISC, 311 dmd->handler, NULL, unit, &dmd->intr_handle); 312 if (error != 0) { 313 device_printf(dev, "cannot setup %s interrupt, %d\n", 314 dmd->name, error); 315 goto err4; 316 } 317 bus_describe_intr(dev, dmd->irq_res, dmd->intr_handle, "%s", dmd->name); 318 error = PCIB_MAP_MSI(pcib, dev, dmd->irq, &msi_addr, &msi_data); 319 if (error != 0) { 320 device_printf(dev, "cannot map %s interrupt, %d\n", 321 dmd->name, error); 322 goto err5; 323 } 324 dmar_write4(unit, dmd->msi_data_reg, msi_data); 325 dmar_write4(unit, dmd->msi_addr_reg, msi_addr); 326 /* Only for xAPIC mode */ 327 dmar_write4(unit, dmd->msi_uaddr_reg, msi_addr >> 32); 328 return (0); 329 330 err5: 331 bus_teardown_intr(dev, dmd->irq_res, dmd->intr_handle); 332 err4: 333 bus_release_resource(dev, SYS_RES_IRQ, dmd->irq_rid, dmd->irq_res); 334 err3: 335 bus_delete_resource(dev, SYS_RES_IRQ, dmd->irq_rid); 336 err2: 337 PCIB_RELEASE_MSIX(pcib, dev, dmd->irq); 338 dmd->irq = -1; 339 err1: 340 return (error); 341 } 342 343 #ifdef DEV_APIC 344 static int 345 dmar_remap_intr(device_t dev, device_t child, u_int irq) 346 { 347 struct dmar_unit *unit; 348 struct dmar_msi_data *dmd; 349 uint64_t msi_addr; 350 uint32_t msi_data; 351 int i, error; 352 353 unit = device_get_softc(dev); 354 for (i = 0; i < DMAR_INTR_TOTAL; i++) { 355 dmd = &unit->intrs[i]; 356 if (irq == dmd->irq) { 357 error = PCIB_MAP_MSI(device_get_parent( 358 device_get_parent(dev)), 359 dev, irq, &msi_addr, &msi_data); 360 if (error != 0) 361 return (error); 362 DMAR_LOCK(unit); 363 (dmd->disable_intr)(unit); 364 dmar_write4(unit, dmd->msi_data_reg, msi_data); 365 dmar_write4(unit, dmd->msi_addr_reg, msi_addr); 366 dmar_write4(unit, dmd->msi_uaddr_reg, msi_addr >> 32); 367 (dmd->enable_intr)(unit); 368 DMAR_UNLOCK(unit); 369 return (0); 370 } 371 } 372 return (ENOENT); 373 } 374 #endif 375 376 static void 377 dmar_print_caps(device_t dev, struct dmar_unit *unit, 378 ACPI_DMAR_HARDWARE_UNIT *dmaru) 379 { 380 uint32_t caphi, ecaphi; 381 382 device_printf(dev, "regs@0x%08jx, ver=%d.%d, seg=%d, flags=<%b>\n", 383 (uintmax_t)dmaru->Address, DMAR_MAJOR_VER(unit->hw_ver), 384 DMAR_MINOR_VER(unit->hw_ver), dmaru->Segment, 385 dmaru->Flags, "\020\001INCLUDE_ALL_PCI"); 386 caphi = unit->hw_cap >> 32; 387 device_printf(dev, "cap=%b,", (u_int)unit->hw_cap, 388 "\020\004AFL\005WBF\006PLMR\007PHMR\010CM\027ZLR\030ISOCH"); 389 printf("%b, ", caphi, "\020\010PSI\027DWD\030DRD\031FL1GP\034PSI"); 390 printf("ndoms=%d, sagaw=%d, mgaw=%d, fro=%d, nfr=%d, superp=%d", 391 DMAR_CAP_ND(unit->hw_cap), DMAR_CAP_SAGAW(unit->hw_cap), 392 DMAR_CAP_MGAW(unit->hw_cap), DMAR_CAP_FRO(unit->hw_cap), 393 DMAR_CAP_NFR(unit->hw_cap), DMAR_CAP_SPS(unit->hw_cap)); 394 if ((unit->hw_cap & DMAR_CAP_PSI) != 0) 395 printf(", mamv=%d", DMAR_CAP_MAMV(unit->hw_cap)); 396 printf("\n"); 397 ecaphi = unit->hw_ecap >> 32; 398 device_printf(dev, "ecap=%b,", (u_int)unit->hw_ecap, 399 "\020\001C\002QI\003DI\004IR\005EIM\007PT\010SC\031ECS\032MTS" 400 "\033NEST\034DIS\035PASID\036PRS\037ERS\040SRS"); 401 printf("%b, ", ecaphi, "\020\002NWFS\003EAFS"); 402 printf("mhmw=%d, iro=%d\n", DMAR_ECAP_MHMV(unit->hw_ecap), 403 DMAR_ECAP_IRO(unit->hw_ecap)); 404 } 405 406 static int 407 dmar_attach(device_t dev) 408 { 409 struct dmar_unit *unit; 410 ACPI_DMAR_HARDWARE_UNIT *dmaru; 411 uint64_t timeout; 412 int i, error; 413 414 unit = device_get_softc(dev); 415 unit->dev = dev; 416 unit->iommu.unit = device_get_unit(dev); 417 dmaru = dmar_find_by_index(unit->iommu.unit); 418 if (dmaru == NULL) 419 return (EINVAL); 420 unit->segment = dmaru->Segment; 421 unit->base = dmaru->Address; 422 unit->reg_rid = DMAR_REG_RID; 423 unit->regs = bus_alloc_resource_any(dev, SYS_RES_MEMORY, 424 &unit->reg_rid, RF_ACTIVE); 425 if (unit->regs == NULL) { 426 device_printf(dev, "cannot allocate register window\n"); 427 return (ENOMEM); 428 } 429 unit->hw_ver = dmar_read4(unit, DMAR_VER_REG); 430 unit->hw_cap = dmar_read8(unit, DMAR_CAP_REG); 431 unit->hw_ecap = dmar_read8(unit, DMAR_ECAP_REG); 432 if (bootverbose) 433 dmar_print_caps(dev, unit, dmaru); 434 dmar_quirks_post_ident(unit); 435 436 timeout = dmar_get_timeout(); 437 TUNABLE_UINT64_FETCH("hw.dmar.timeout", &timeout); 438 dmar_update_timeout(timeout); 439 440 for (i = 0; i < DMAR_INTR_TOTAL; i++) 441 unit->intrs[i].irq = -1; 442 443 unit->intrs[DMAR_INTR_FAULT].name = "fault"; 444 unit->intrs[DMAR_INTR_FAULT].irq_rid = DMAR_FAULT_IRQ_RID; 445 unit->intrs[DMAR_INTR_FAULT].handler = dmar_fault_intr; 446 unit->intrs[DMAR_INTR_FAULT].msi_data_reg = DMAR_FEDATA_REG; 447 unit->intrs[DMAR_INTR_FAULT].msi_addr_reg = DMAR_FEADDR_REG; 448 unit->intrs[DMAR_INTR_FAULT].msi_uaddr_reg = DMAR_FEUADDR_REG; 449 unit->intrs[DMAR_INTR_FAULT].enable_intr = dmar_enable_fault_intr; 450 unit->intrs[DMAR_INTR_FAULT].disable_intr = dmar_disable_fault_intr; 451 error = dmar_alloc_irq(dev, unit, DMAR_INTR_FAULT); 452 if (error != 0) { 453 dmar_release_resources(dev, unit); 454 return (error); 455 } 456 if (DMAR_HAS_QI(unit)) { 457 unit->intrs[DMAR_INTR_QI].name = "qi"; 458 unit->intrs[DMAR_INTR_QI].irq_rid = DMAR_QI_IRQ_RID; 459 unit->intrs[DMAR_INTR_QI].handler = dmar_qi_intr; 460 unit->intrs[DMAR_INTR_QI].msi_data_reg = DMAR_IEDATA_REG; 461 unit->intrs[DMAR_INTR_QI].msi_addr_reg = DMAR_IEADDR_REG; 462 unit->intrs[DMAR_INTR_QI].msi_uaddr_reg = DMAR_IEUADDR_REG; 463 unit->intrs[DMAR_INTR_QI].enable_intr = dmar_enable_qi_intr; 464 unit->intrs[DMAR_INTR_QI].disable_intr = dmar_disable_qi_intr; 465 error = dmar_alloc_irq(dev, unit, DMAR_INTR_QI); 466 if (error != 0) { 467 dmar_release_resources(dev, unit); 468 return (error); 469 } 470 } 471 472 mtx_init(&unit->iommu.lock, "dmarhw", NULL, MTX_DEF); 473 unit->domids = new_unrhdr(0, dmar_nd2mask(DMAR_CAP_ND(unit->hw_cap)), 474 &unit->iommu.lock); 475 LIST_INIT(&unit->domains); 476 477 /* 478 * 9.2 "Context Entry": 479 * When Caching Mode (CM) field is reported as Set, the 480 * domain-id value of zero is architecturally reserved. 481 * Software must not use domain-id value of zero 482 * when CM is Set. 483 */ 484 if ((unit->hw_cap & DMAR_CAP_CM) != 0) 485 alloc_unr_specific(unit->domids, 0); 486 487 unit->ctx_obj = vm_pager_allocate(OBJT_PHYS, NULL, IDX_TO_OFF(1 + 488 DMAR_CTX_CNT), 0, 0, NULL); 489 490 /* 491 * Allocate and load the root entry table pointer. Enable the 492 * address translation after the required invalidations are 493 * done. 494 */ 495 dmar_pgalloc(unit->ctx_obj, 0, DMAR_PGF_WAITOK | DMAR_PGF_ZERO); 496 DMAR_LOCK(unit); 497 error = dmar_load_root_entry_ptr(unit); 498 if (error != 0) { 499 DMAR_UNLOCK(unit); 500 dmar_release_resources(dev, unit); 501 return (error); 502 } 503 error = dmar_inv_ctx_glob(unit); 504 if (error != 0) { 505 DMAR_UNLOCK(unit); 506 dmar_release_resources(dev, unit); 507 return (error); 508 } 509 if ((unit->hw_ecap & DMAR_ECAP_DI) != 0) { 510 error = dmar_inv_iotlb_glob(unit); 511 if (error != 0) { 512 DMAR_UNLOCK(unit); 513 dmar_release_resources(dev, unit); 514 return (error); 515 } 516 } 517 518 DMAR_UNLOCK(unit); 519 error = dmar_init_fault_log(unit); 520 if (error != 0) { 521 dmar_release_resources(dev, unit); 522 return (error); 523 } 524 error = dmar_init_qi(unit); 525 if (error != 0) { 526 dmar_release_resources(dev, unit); 527 return (error); 528 } 529 error = dmar_init_irt(unit); 530 if (error != 0) { 531 dmar_release_resources(dev, unit); 532 return (error); 533 } 534 error = iommu_init_busdma(&unit->iommu); 535 if (error != 0) { 536 dmar_release_resources(dev, unit); 537 return (error); 538 } 539 540 #ifdef NOTYET 541 DMAR_LOCK(unit); 542 error = dmar_enable_translation(unit); 543 if (error != 0) { 544 DMAR_UNLOCK(unit); 545 dmar_release_resources(dev, unit); 546 return (error); 547 } 548 DMAR_UNLOCK(unit); 549 #endif 550 551 return (0); 552 } 553 554 static int 555 dmar_detach(device_t dev) 556 { 557 558 return (EBUSY); 559 } 560 561 static int 562 dmar_suspend(device_t dev) 563 { 564 565 return (0); 566 } 567 568 static int 569 dmar_resume(device_t dev) 570 { 571 572 /* XXXKIB */ 573 return (0); 574 } 575 576 static device_method_t dmar_methods[] = { 577 DEVMETHOD(device_identify, dmar_identify), 578 DEVMETHOD(device_probe, dmar_probe), 579 DEVMETHOD(device_attach, dmar_attach), 580 DEVMETHOD(device_detach, dmar_detach), 581 DEVMETHOD(device_suspend, dmar_suspend), 582 DEVMETHOD(device_resume, dmar_resume), 583 #ifdef DEV_APIC 584 DEVMETHOD(bus_remap_intr, dmar_remap_intr), 585 #endif 586 DEVMETHOD_END 587 }; 588 589 static driver_t dmar_driver = { 590 "dmar", 591 dmar_methods, 592 sizeof(struct dmar_unit), 593 }; 594 595 DRIVER_MODULE(dmar, acpi, dmar_driver, dmar_devclass, 0, 0); 596 MODULE_DEPEND(dmar, acpi, 1, 1, 1); 597 598 void 599 dmar_set_buswide_ctx(struct iommu_unit *unit, u_int busno) 600 { 601 struct dmar_unit *dmar; 602 603 dmar = (struct dmar_unit *)unit; 604 605 MPASS(busno <= PCI_BUSMAX); 606 DMAR_LOCK(dmar); 607 dmar->buswide_ctxs[busno / NBBY / sizeof(uint32_t)] |= 608 1 << (busno % (NBBY * sizeof(uint32_t))); 609 DMAR_UNLOCK(dmar); 610 } 611 612 bool 613 dmar_is_buswide_ctx(struct dmar_unit *unit, u_int busno) 614 { 615 616 MPASS(busno <= PCI_BUSMAX); 617 return ((unit->buswide_ctxs[busno / NBBY / sizeof(uint32_t)] & 618 (1U << (busno % (NBBY * sizeof(uint32_t))))) != 0); 619 } 620 621 static void 622 dmar_print_path(int busno, int depth, const ACPI_DMAR_PCI_PATH *path) 623 { 624 int i; 625 626 printf("[%d, ", busno); 627 for (i = 0; i < depth; i++) { 628 if (i != 0) 629 printf(", "); 630 printf("(%d, %d)", path[i].Device, path[i].Function); 631 } 632 printf("]"); 633 } 634 635 int 636 dmar_dev_depth(device_t child) 637 { 638 devclass_t pci_class; 639 device_t bus, pcib; 640 int depth; 641 642 pci_class = devclass_find("pci"); 643 for (depth = 1; ; depth++) { 644 bus = device_get_parent(child); 645 pcib = device_get_parent(bus); 646 if (device_get_devclass(device_get_parent(pcib)) != 647 pci_class) 648 return (depth); 649 child = pcib; 650 } 651 } 652 653 void 654 dmar_dev_path(device_t child, int *busno, void *path1, int depth) 655 { 656 devclass_t pci_class; 657 device_t bus, pcib; 658 ACPI_DMAR_PCI_PATH *path; 659 660 pci_class = devclass_find("pci"); 661 path = path1; 662 for (depth--; depth != -1; depth--) { 663 path[depth].Device = pci_get_slot(child); 664 path[depth].Function = pci_get_function(child); 665 bus = device_get_parent(child); 666 pcib = device_get_parent(bus); 667 if (device_get_devclass(device_get_parent(pcib)) != 668 pci_class) { 669 /* reached a host bridge */ 670 *busno = pcib_get_bus(bus); 671 return; 672 } 673 child = pcib; 674 } 675 panic("wrong depth"); 676 } 677 678 static int 679 dmar_match_pathes(int busno1, const ACPI_DMAR_PCI_PATH *path1, int depth1, 680 int busno2, const ACPI_DMAR_PCI_PATH *path2, int depth2, 681 enum AcpiDmarScopeType scope_type) 682 { 683 int i, depth; 684 685 if (busno1 != busno2) 686 return (0); 687 if (scope_type == ACPI_DMAR_SCOPE_TYPE_ENDPOINT && depth1 != depth2) 688 return (0); 689 depth = depth1; 690 if (depth2 < depth) 691 depth = depth2; 692 for (i = 0; i < depth; i++) { 693 if (path1[i].Device != path2[i].Device || 694 path1[i].Function != path2[i].Function) 695 return (0); 696 } 697 return (1); 698 } 699 700 static int 701 dmar_match_devscope(ACPI_DMAR_DEVICE_SCOPE *devscope, int dev_busno, 702 const ACPI_DMAR_PCI_PATH *dev_path, int dev_path_len) 703 { 704 ACPI_DMAR_PCI_PATH *path; 705 int path_len; 706 707 if (devscope->Length < sizeof(*devscope)) { 708 printf("dmar_match_devscope: corrupted DMAR table, dl %d\n", 709 devscope->Length); 710 return (-1); 711 } 712 if (devscope->EntryType != ACPI_DMAR_SCOPE_TYPE_ENDPOINT && 713 devscope->EntryType != ACPI_DMAR_SCOPE_TYPE_BRIDGE) 714 return (0); 715 path_len = devscope->Length - sizeof(*devscope); 716 if (path_len % 2 != 0) { 717 printf("dmar_match_devscope: corrupted DMAR table, dl %d\n", 718 devscope->Length); 719 return (-1); 720 } 721 path_len /= 2; 722 path = (ACPI_DMAR_PCI_PATH *)(devscope + 1); 723 if (path_len == 0) { 724 printf("dmar_match_devscope: corrupted DMAR table, dl %d\n", 725 devscope->Length); 726 return (-1); 727 } 728 729 return (dmar_match_pathes(devscope->Bus, path, path_len, dev_busno, 730 dev_path, dev_path_len, devscope->EntryType)); 731 } 732 733 static bool 734 dmar_match_by_path(struct dmar_unit *unit, int dev_domain, int dev_busno, 735 const ACPI_DMAR_PCI_PATH *dev_path, int dev_path_len, const char **banner) 736 { 737 ACPI_DMAR_HARDWARE_UNIT *dmarh; 738 ACPI_DMAR_DEVICE_SCOPE *devscope; 739 char *ptr, *ptrend; 740 int match; 741 742 dmarh = dmar_find_by_index(unit->iommu.unit); 743 if (dmarh == NULL) 744 return (false); 745 if (dmarh->Segment != dev_domain) 746 return (false); 747 if ((dmarh->Flags & ACPI_DMAR_INCLUDE_ALL) != 0) { 748 if (banner != NULL) 749 *banner = "INCLUDE_ALL"; 750 return (true); 751 } 752 ptr = (char *)dmarh + sizeof(*dmarh); 753 ptrend = (char *)dmarh + dmarh->Header.Length; 754 while (ptr < ptrend) { 755 devscope = (ACPI_DMAR_DEVICE_SCOPE *)ptr; 756 ptr += devscope->Length; 757 match = dmar_match_devscope(devscope, dev_busno, dev_path, 758 dev_path_len); 759 if (match == -1) 760 return (false); 761 if (match == 1) { 762 if (banner != NULL) 763 *banner = "specific match"; 764 return (true); 765 } 766 } 767 return (false); 768 } 769 770 static struct dmar_unit * 771 dmar_find_by_scope(int dev_domain, int dev_busno, 772 const ACPI_DMAR_PCI_PATH *dev_path, int dev_path_len) 773 { 774 struct dmar_unit *unit; 775 int i; 776 777 for (i = 0; i < dmar_devcnt; i++) { 778 if (dmar_devs[i] == NULL) 779 continue; 780 unit = device_get_softc(dmar_devs[i]); 781 if (dmar_match_by_path(unit, dev_domain, dev_busno, dev_path, 782 dev_path_len, NULL)) 783 return (unit); 784 } 785 return (NULL); 786 } 787 788 struct dmar_unit * 789 dmar_find(device_t dev, bool verbose) 790 { 791 device_t dmar_dev; 792 struct dmar_unit *unit; 793 const char *banner; 794 int i, dev_domain, dev_busno, dev_path_len; 795 796 /* 797 * This function can only handle PCI(e) devices. 798 */ 799 if (device_get_devclass(device_get_parent(dev)) != 800 devclass_find("pci")) 801 return (NULL); 802 803 dmar_dev = NULL; 804 dev_domain = pci_get_domain(dev); 805 dev_path_len = dmar_dev_depth(dev); 806 ACPI_DMAR_PCI_PATH dev_path[dev_path_len]; 807 dmar_dev_path(dev, &dev_busno, dev_path, dev_path_len); 808 banner = ""; 809 810 for (i = 0; i < dmar_devcnt; i++) { 811 if (dmar_devs[i] == NULL) 812 continue; 813 unit = device_get_softc(dmar_devs[i]); 814 if (dmar_match_by_path(unit, dev_domain, dev_busno, 815 dev_path, dev_path_len, &banner)) 816 break; 817 } 818 if (i == dmar_devcnt) 819 return (NULL); 820 821 if (verbose) { 822 device_printf(dev, "pci%d:%d:%d:%d matched dmar%d by %s", 823 dev_domain, pci_get_bus(dev), pci_get_slot(dev), 824 pci_get_function(dev), unit->iommu.unit, banner); 825 printf(" scope path "); 826 dmar_print_path(dev_busno, dev_path_len, dev_path); 827 printf("\n"); 828 } 829 return (unit); 830 } 831 832 static struct dmar_unit * 833 dmar_find_nonpci(u_int id, u_int entry_type, uint16_t *rid) 834 { 835 device_t dmar_dev; 836 struct dmar_unit *unit; 837 ACPI_DMAR_HARDWARE_UNIT *dmarh; 838 ACPI_DMAR_DEVICE_SCOPE *devscope; 839 ACPI_DMAR_PCI_PATH *path; 840 char *ptr, *ptrend; 841 #ifdef DEV_APIC 842 int error; 843 #endif 844 int i; 845 846 for (i = 0; i < dmar_devcnt; i++) { 847 dmar_dev = dmar_devs[i]; 848 if (dmar_dev == NULL) 849 continue; 850 unit = (struct dmar_unit *)device_get_softc(dmar_dev); 851 dmarh = dmar_find_by_index(i); 852 if (dmarh == NULL) 853 continue; 854 ptr = (char *)dmarh + sizeof(*dmarh); 855 ptrend = (char *)dmarh + dmarh->Header.Length; 856 for (;;) { 857 if (ptr >= ptrend) 858 break; 859 devscope = (ACPI_DMAR_DEVICE_SCOPE *)ptr; 860 ptr += devscope->Length; 861 if (devscope->EntryType != entry_type) 862 continue; 863 if (devscope->EnumerationId != id) 864 continue; 865 #ifdef DEV_APIC 866 if (entry_type == ACPI_DMAR_SCOPE_TYPE_IOAPIC) { 867 error = ioapic_get_rid(id, rid); 868 /* 869 * If our IOAPIC has PCI bindings then 870 * use the PCI device rid. 871 */ 872 if (error == 0) 873 return (unit); 874 } 875 #endif 876 if (devscope->Length - sizeof(ACPI_DMAR_DEVICE_SCOPE) 877 == 2) { 878 if (rid != NULL) { 879 path = (ACPI_DMAR_PCI_PATH *) 880 (devscope + 1); 881 *rid = PCI_RID(devscope->Bus, 882 path->Device, path->Function); 883 } 884 return (unit); 885 } 886 printf( 887 "dmar_find_nonpci: id %d type %d path length != 2\n", 888 id, entry_type); 889 break; 890 } 891 } 892 return (NULL); 893 } 894 895 896 struct dmar_unit * 897 dmar_find_hpet(device_t dev, uint16_t *rid) 898 { 899 900 return (dmar_find_nonpci(hpet_get_uid(dev), ACPI_DMAR_SCOPE_TYPE_HPET, 901 rid)); 902 } 903 904 struct dmar_unit * 905 dmar_find_ioapic(u_int apic_id, uint16_t *rid) 906 { 907 908 return (dmar_find_nonpci(apic_id, ACPI_DMAR_SCOPE_TYPE_IOAPIC, rid)); 909 } 910 911 struct rmrr_iter_args { 912 struct dmar_domain *domain; 913 int dev_domain; 914 int dev_busno; 915 const ACPI_DMAR_PCI_PATH *dev_path; 916 int dev_path_len; 917 struct iommu_map_entries_tailq *rmrr_entries; 918 }; 919 920 static int 921 dmar_rmrr_iter(ACPI_DMAR_HEADER *dmarh, void *arg) 922 { 923 struct rmrr_iter_args *ria; 924 ACPI_DMAR_RESERVED_MEMORY *resmem; 925 ACPI_DMAR_DEVICE_SCOPE *devscope; 926 struct iommu_map_entry *entry; 927 char *ptr, *ptrend; 928 int match; 929 930 if (dmarh->Type != ACPI_DMAR_TYPE_RESERVED_MEMORY) 931 return (1); 932 933 ria = arg; 934 resmem = (ACPI_DMAR_RESERVED_MEMORY *)dmarh; 935 if (resmem->Segment != ria->dev_domain) 936 return (1); 937 938 ptr = (char *)resmem + sizeof(*resmem); 939 ptrend = (char *)resmem + resmem->Header.Length; 940 for (;;) { 941 if (ptr >= ptrend) 942 break; 943 devscope = (ACPI_DMAR_DEVICE_SCOPE *)ptr; 944 ptr += devscope->Length; 945 match = dmar_match_devscope(devscope, ria->dev_busno, 946 ria->dev_path, ria->dev_path_len); 947 if (match == 1) { 948 entry = dmar_gas_alloc_entry(ria->domain, 949 DMAR_PGF_WAITOK); 950 entry->start = resmem->BaseAddress; 951 /* The RMRR entry end address is inclusive. */ 952 entry->end = resmem->EndAddress; 953 TAILQ_INSERT_TAIL(ria->rmrr_entries, entry, 954 unroll_link); 955 } 956 } 957 958 return (1); 959 } 960 961 void 962 dmar_dev_parse_rmrr(struct dmar_domain *domain, int dev_domain, int dev_busno, 963 const void *dev_path, int dev_path_len, 964 struct iommu_map_entries_tailq *rmrr_entries) 965 { 966 struct rmrr_iter_args ria; 967 968 ria.domain = domain; 969 ria.dev_domain = dev_domain; 970 ria.dev_busno = dev_busno; 971 ria.dev_path = (const ACPI_DMAR_PCI_PATH *)dev_path; 972 ria.dev_path_len = dev_path_len; 973 ria.rmrr_entries = rmrr_entries; 974 dmar_iterate_tbl(dmar_rmrr_iter, &ria); 975 } 976 977 struct inst_rmrr_iter_args { 978 struct dmar_unit *dmar; 979 }; 980 981 static device_t 982 dmar_path_dev(int segment, int path_len, int busno, 983 const ACPI_DMAR_PCI_PATH *path, uint16_t *rid) 984 { 985 device_t dev; 986 int i; 987 988 dev = NULL; 989 for (i = 0; i < path_len; i++) { 990 dev = pci_find_dbsf(segment, busno, path->Device, 991 path->Function); 992 if (i != path_len - 1) { 993 busno = pci_cfgregread(busno, path->Device, 994 path->Function, PCIR_SECBUS_1, 1); 995 path++; 996 } 997 } 998 *rid = PCI_RID(busno, path->Device, path->Function); 999 return (dev); 1000 } 1001 1002 static int 1003 dmar_inst_rmrr_iter(ACPI_DMAR_HEADER *dmarh, void *arg) 1004 { 1005 const ACPI_DMAR_RESERVED_MEMORY *resmem; 1006 const ACPI_DMAR_DEVICE_SCOPE *devscope; 1007 struct inst_rmrr_iter_args *iria; 1008 const char *ptr, *ptrend; 1009 device_t dev; 1010 struct dmar_unit *unit; 1011 int dev_path_len; 1012 uint16_t rid; 1013 1014 iria = arg; 1015 1016 if (dmarh->Type != ACPI_DMAR_TYPE_RESERVED_MEMORY) 1017 return (1); 1018 1019 resmem = (ACPI_DMAR_RESERVED_MEMORY *)dmarh; 1020 if (resmem->Segment != iria->dmar->segment) 1021 return (1); 1022 1023 ptr = (const char *)resmem + sizeof(*resmem); 1024 ptrend = (const char *)resmem + resmem->Header.Length; 1025 for (;;) { 1026 if (ptr >= ptrend) 1027 break; 1028 devscope = (const ACPI_DMAR_DEVICE_SCOPE *)ptr; 1029 ptr += devscope->Length; 1030 /* XXXKIB bridge */ 1031 if (devscope->EntryType != ACPI_DMAR_SCOPE_TYPE_ENDPOINT) 1032 continue; 1033 rid = 0; 1034 dev_path_len = (devscope->Length - 1035 sizeof(ACPI_DMAR_DEVICE_SCOPE)) / 2; 1036 dev = dmar_path_dev(resmem->Segment, dev_path_len, 1037 devscope->Bus, 1038 (const ACPI_DMAR_PCI_PATH *)(devscope + 1), &rid); 1039 if (dev == NULL) { 1040 if (bootverbose) { 1041 printf("dmar%d no dev found for RMRR " 1042 "[%#jx, %#jx] rid %#x scope path ", 1043 iria->dmar->iommu.unit, 1044 (uintmax_t)resmem->BaseAddress, 1045 (uintmax_t)resmem->EndAddress, 1046 rid); 1047 dmar_print_path(devscope->Bus, dev_path_len, 1048 (const ACPI_DMAR_PCI_PATH *)(devscope + 1)); 1049 printf("\n"); 1050 } 1051 unit = dmar_find_by_scope(resmem->Segment, 1052 devscope->Bus, 1053 (const ACPI_DMAR_PCI_PATH *)(devscope + 1), 1054 dev_path_len); 1055 if (iria->dmar != unit) 1056 continue; 1057 dmar_get_ctx_for_devpath(iria->dmar, rid, 1058 resmem->Segment, devscope->Bus, 1059 (const ACPI_DMAR_PCI_PATH *)(devscope + 1), 1060 dev_path_len, false, true); 1061 } else { 1062 unit = dmar_find(dev, false); 1063 if (iria->dmar != unit) 1064 continue; 1065 iommu_instantiate_ctx(&(iria)->dmar->iommu, 1066 dev, true); 1067 } 1068 } 1069 1070 return (1); 1071 1072 } 1073 1074 /* 1075 * Pre-create all contexts for the DMAR which have RMRR entries. 1076 */ 1077 int 1078 dmar_instantiate_rmrr_ctxs(struct iommu_unit *unit) 1079 { 1080 struct dmar_unit *dmar; 1081 struct inst_rmrr_iter_args iria; 1082 int error; 1083 1084 dmar = (struct dmar_unit *)unit; 1085 1086 if (!dmar_barrier_enter(dmar, DMAR_BARRIER_RMRR)) 1087 return (0); 1088 1089 error = 0; 1090 iria.dmar = dmar; 1091 dmar_iterate_tbl(dmar_inst_rmrr_iter, &iria); 1092 DMAR_LOCK(dmar); 1093 if (!LIST_EMPTY(&dmar->domains)) { 1094 KASSERT((dmar->hw_gcmd & DMAR_GCMD_TE) == 0, 1095 ("dmar%d: RMRR not handled but translation is already enabled", 1096 dmar->iommu.unit)); 1097 error = dmar_enable_translation(dmar); 1098 if (bootverbose) { 1099 if (error == 0) { 1100 printf("dmar%d: enabled translation\n", 1101 dmar->iommu.unit); 1102 } else { 1103 printf("dmar%d: enabling translation failed, " 1104 "error %d\n", dmar->iommu.unit, error); 1105 } 1106 } 1107 } 1108 dmar_barrier_exit(dmar, DMAR_BARRIER_RMRR); 1109 return (error); 1110 } 1111 1112 #ifdef DDB 1113 #include <ddb/ddb.h> 1114 #include <ddb/db_lex.h> 1115 1116 static void 1117 dmar_print_domain_entry(const struct iommu_map_entry *entry) 1118 { 1119 struct iommu_map_entry *l, *r; 1120 1121 db_printf( 1122 " start %jx end %jx first %jx last %jx free_down %jx flags %x ", 1123 entry->start, entry->end, entry->first, entry->last, 1124 entry->free_down, entry->flags); 1125 db_printf("left "); 1126 l = RB_LEFT(entry, rb_entry); 1127 if (l == NULL) 1128 db_printf("NULL "); 1129 else 1130 db_printf("%jx ", l->start); 1131 db_printf("right "); 1132 r = RB_RIGHT(entry, rb_entry); 1133 if (r == NULL) 1134 db_printf("NULL"); 1135 else 1136 db_printf("%jx", r->start); 1137 db_printf("\n"); 1138 } 1139 1140 static void 1141 dmar_print_ctx(struct dmar_ctx *ctx) 1142 { 1143 1144 db_printf( 1145 " @%p pci%d:%d:%d refs %d flags %x loads %lu unloads %lu\n", 1146 ctx, pci_get_bus(ctx->context.tag->owner), 1147 pci_get_slot(ctx->context.tag->owner), 1148 pci_get_function(ctx->context.tag->owner), ctx->refs, 1149 ctx->context.flags, ctx->context.loads, ctx->context.unloads); 1150 } 1151 1152 static void 1153 dmar_print_domain(struct dmar_domain *domain, bool show_mappings) 1154 { 1155 struct iommu_map_entry *entry; 1156 struct dmar_ctx *ctx; 1157 1158 db_printf( 1159 " @%p dom %d mgaw %d agaw %d pglvl %d end %jx refs %d\n" 1160 " ctx_cnt %d flags %x pgobj %p map_ents %u\n", 1161 domain, domain->domain, domain->mgaw, domain->agaw, domain->pglvl, 1162 (uintmax_t)domain->end, domain->refs, domain->ctx_cnt, 1163 domain->flags, domain->pgtbl_obj, domain->iodom.entries_cnt); 1164 if (!LIST_EMPTY(&domain->contexts)) { 1165 db_printf(" Contexts:\n"); 1166 LIST_FOREACH(ctx, &domain->contexts, link) 1167 dmar_print_ctx(ctx); 1168 } 1169 if (!show_mappings) 1170 return; 1171 db_printf(" mapped:\n"); 1172 RB_FOREACH(entry, dmar_gas_entries_tree, &domain->rb_root) { 1173 dmar_print_domain_entry(entry); 1174 if (db_pager_quit) 1175 break; 1176 } 1177 if (db_pager_quit) 1178 return; 1179 db_printf(" unloading:\n"); 1180 TAILQ_FOREACH(entry, &domain->iodom.unload_entries, dmamap_link) { 1181 dmar_print_domain_entry(entry); 1182 if (db_pager_quit) 1183 break; 1184 } 1185 } 1186 1187 DB_FUNC(dmar_domain, db_dmar_print_domain, db_show_table, CS_OWN, NULL) 1188 { 1189 struct dmar_unit *unit; 1190 struct dmar_domain *domain; 1191 struct dmar_ctx *ctx; 1192 bool show_mappings, valid; 1193 int pci_domain, bus, device, function, i, t; 1194 db_expr_t radix; 1195 1196 valid = false; 1197 radix = db_radix; 1198 db_radix = 10; 1199 t = db_read_token(); 1200 if (t == tSLASH) { 1201 t = db_read_token(); 1202 if (t != tIDENT) { 1203 db_printf("Bad modifier\n"); 1204 db_radix = radix; 1205 db_skip_to_eol(); 1206 return; 1207 } 1208 show_mappings = strchr(db_tok_string, 'm') != NULL; 1209 t = db_read_token(); 1210 } else { 1211 show_mappings = false; 1212 } 1213 if (t == tNUMBER) { 1214 pci_domain = db_tok_number; 1215 t = db_read_token(); 1216 if (t == tNUMBER) { 1217 bus = db_tok_number; 1218 t = db_read_token(); 1219 if (t == tNUMBER) { 1220 device = db_tok_number; 1221 t = db_read_token(); 1222 if (t == tNUMBER) { 1223 function = db_tok_number; 1224 valid = true; 1225 } 1226 } 1227 } 1228 } 1229 db_radix = radix; 1230 db_skip_to_eol(); 1231 if (!valid) { 1232 db_printf("usage: show dmar_domain [/m] " 1233 "<domain> <bus> <device> <func>\n"); 1234 return; 1235 } 1236 for (i = 0; i < dmar_devcnt; i++) { 1237 unit = device_get_softc(dmar_devs[i]); 1238 LIST_FOREACH(domain, &unit->domains, link) { 1239 LIST_FOREACH(ctx, &domain->contexts, link) { 1240 if (pci_domain == unit->segment && 1241 bus == pci_get_bus(ctx->context.tag->owner) && 1242 device == 1243 pci_get_slot(ctx->context.tag->owner) && 1244 function == 1245 pci_get_function(ctx->context.tag->owner)) { 1246 dmar_print_domain(domain, 1247 show_mappings); 1248 goto out; 1249 } 1250 } 1251 } 1252 } 1253 out:; 1254 } 1255 1256 static void 1257 dmar_print_one(int idx, bool show_domains, bool show_mappings) 1258 { 1259 struct dmar_unit *unit; 1260 struct dmar_domain *domain; 1261 int i, frir; 1262 1263 unit = device_get_softc(dmar_devs[idx]); 1264 db_printf("dmar%d at %p, root at 0x%jx, ver 0x%x\n", unit->iommu.unit, 1265 unit, dmar_read8(unit, DMAR_RTADDR_REG), 1266 dmar_read4(unit, DMAR_VER_REG)); 1267 db_printf("cap 0x%jx ecap 0x%jx gsts 0x%x fsts 0x%x fectl 0x%x\n", 1268 (uintmax_t)dmar_read8(unit, DMAR_CAP_REG), 1269 (uintmax_t)dmar_read8(unit, DMAR_ECAP_REG), 1270 dmar_read4(unit, DMAR_GSTS_REG), 1271 dmar_read4(unit, DMAR_FSTS_REG), 1272 dmar_read4(unit, DMAR_FECTL_REG)); 1273 if (unit->ir_enabled) { 1274 db_printf("ir is enabled; IRT @%p phys 0x%jx maxcnt %d\n", 1275 unit->irt, (uintmax_t)unit->irt_phys, unit->irte_cnt); 1276 } 1277 db_printf("fed 0x%x fea 0x%x feua 0x%x\n", 1278 dmar_read4(unit, DMAR_FEDATA_REG), 1279 dmar_read4(unit, DMAR_FEADDR_REG), 1280 dmar_read4(unit, DMAR_FEUADDR_REG)); 1281 db_printf("primary fault log:\n"); 1282 for (i = 0; i < DMAR_CAP_NFR(unit->hw_cap); i++) { 1283 frir = (DMAR_CAP_FRO(unit->hw_cap) + i) * 16; 1284 db_printf(" %d at 0x%x: %jx %jx\n", i, frir, 1285 (uintmax_t)dmar_read8(unit, frir), 1286 (uintmax_t)dmar_read8(unit, frir + 8)); 1287 } 1288 if (DMAR_HAS_QI(unit)) { 1289 db_printf("ied 0x%x iea 0x%x ieua 0x%x\n", 1290 dmar_read4(unit, DMAR_IEDATA_REG), 1291 dmar_read4(unit, DMAR_IEADDR_REG), 1292 dmar_read4(unit, DMAR_IEUADDR_REG)); 1293 if (unit->qi_enabled) { 1294 db_printf("qi is enabled: queue @0x%jx (IQA 0x%jx) " 1295 "size 0x%jx\n" 1296 " head 0x%x tail 0x%x avail 0x%x status 0x%x ctrl 0x%x\n" 1297 " hw compl 0x%x@%p/phys@%jx next seq 0x%x gen 0x%x\n", 1298 (uintmax_t)unit->inv_queue, 1299 (uintmax_t)dmar_read8(unit, DMAR_IQA_REG), 1300 (uintmax_t)unit->inv_queue_size, 1301 dmar_read4(unit, DMAR_IQH_REG), 1302 dmar_read4(unit, DMAR_IQT_REG), 1303 unit->inv_queue_avail, 1304 dmar_read4(unit, DMAR_ICS_REG), 1305 dmar_read4(unit, DMAR_IECTL_REG), 1306 unit->inv_waitd_seq_hw, 1307 &unit->inv_waitd_seq_hw, 1308 (uintmax_t)unit->inv_waitd_seq_hw_phys, 1309 unit->inv_waitd_seq, 1310 unit->inv_waitd_gen); 1311 } else { 1312 db_printf("qi is disabled\n"); 1313 } 1314 } 1315 if (show_domains) { 1316 db_printf("domains:\n"); 1317 LIST_FOREACH(domain, &unit->domains, link) { 1318 dmar_print_domain(domain, show_mappings); 1319 if (db_pager_quit) 1320 break; 1321 } 1322 } 1323 } 1324 1325 DB_SHOW_COMMAND(dmar, db_dmar_print) 1326 { 1327 bool show_domains, show_mappings; 1328 1329 show_domains = strchr(modif, 'd') != NULL; 1330 show_mappings = strchr(modif, 'm') != NULL; 1331 if (!have_addr) { 1332 db_printf("usage: show dmar [/d] [/m] index\n"); 1333 return; 1334 } 1335 dmar_print_one((int)addr, show_domains, show_mappings); 1336 } 1337 1338 DB_SHOW_ALL_COMMAND(dmars, db_show_all_dmars) 1339 { 1340 int i; 1341 bool show_domains, show_mappings; 1342 1343 show_domains = strchr(modif, 'd') != NULL; 1344 show_mappings = strchr(modif, 'm') != NULL; 1345 1346 for (i = 0; i < dmar_devcnt; i++) { 1347 dmar_print_one(i, show_domains, show_mappings); 1348 if (db_pager_quit) 1349 break; 1350 } 1351 } 1352 #endif 1353 1354 struct iommu_unit * 1355 iommu_find(device_t dev, bool verbose) 1356 { 1357 struct dmar_unit *dmar; 1358 1359 dmar = dmar_find(dev, verbose); 1360 1361 return (&dmar->iommu); 1362 } 1363