1 /*- 2 * Copyright (c) 1992 Terrence R. Lambert. 3 * Copyright (c) 1982, 1987, 1990 The Regents of the University of California. 4 * Copyright (c) 1997 KATO Takenori. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to Berkeley by 8 * William Jolitz. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by the University of 21 * California, Berkeley and its contributors. 22 * 4. Neither the name of the University nor the names of its contributors 23 * may be used to endorse or promote products derived from this software 24 * without specific prior written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 27 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 28 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 29 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 30 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 31 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 32 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 33 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 34 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 35 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 36 * SUCH DAMAGE. 37 * 38 * from: Id: machdep.c,v 1.193 1996/06/18 01:22:04 bde Exp 39 */ 40 41 #include <sys/cdefs.h> 42 __FBSDID("$FreeBSD$"); 43 44 #include "opt_cpu.h" 45 46 #include <sys/param.h> 47 #include <sys/bus.h> 48 #include <sys/cpu.h> 49 #include <sys/eventhandler.h> 50 #include <sys/limits.h> 51 #include <sys/systm.h> 52 #include <sys/kernel.h> 53 #include <sys/sysctl.h> 54 #include <sys/power.h> 55 56 #include <vm/vm.h> 57 #include <vm/pmap.h> 58 59 #include <machine/asmacros.h> 60 #include <machine/clock.h> 61 #include <machine/cputypes.h> 62 #include <machine/frame.h> 63 #include <machine/intr_machdep.h> 64 #include <machine/md_var.h> 65 #include <machine/segments.h> 66 #include <machine/specialreg.h> 67 68 #include <amd64/vmm/intel/vmx_controls.h> 69 #include <x86/isa/icu.h> 70 #include <x86/vmware.h> 71 72 #ifdef __i386__ 73 #define IDENTBLUE_CYRIX486 0 74 #define IDENTBLUE_IBMCPU 1 75 #define IDENTBLUE_CYRIXM2 2 76 77 static void identifycyrix(void); 78 static void print_transmeta_info(void); 79 #endif 80 static u_int find_cpu_vendor_id(void); 81 static void print_AMD_info(void); 82 static void print_INTEL_info(void); 83 static void print_INTEL_TLB(u_int data); 84 static void print_hypervisor_info(void); 85 static void print_svm_info(void); 86 static void print_via_padlock_info(void); 87 static void print_vmx_info(void); 88 89 #ifdef __i386__ 90 int cpu; /* Are we 386, 386sx, 486, etc? */ 91 int cpu_class; 92 #endif 93 u_int cpu_feature; /* Feature flags */ 94 u_int cpu_feature2; /* Feature flags */ 95 u_int amd_feature; /* AMD feature flags */ 96 u_int amd_feature2; /* AMD feature flags */ 97 u_int amd_rascap; /* AMD RAS capabilities */ 98 u_int amd_pminfo; /* AMD advanced power management info */ 99 u_int amd_extended_feature_extensions; 100 u_int via_feature_rng; /* VIA RNG features */ 101 u_int via_feature_xcrypt; /* VIA ACE features */ 102 u_int cpu_high; /* Highest arg to CPUID */ 103 u_int cpu_exthigh; /* Highest arg to extended CPUID */ 104 u_int cpu_id; /* Stepping ID */ 105 u_int cpu_procinfo; /* HyperThreading Info / Brand Index / CLFUSH */ 106 u_int cpu_procinfo2; /* Multicore info */ 107 char cpu_vendor[20]; /* CPU Origin code */ 108 u_int cpu_vendor_id; /* CPU vendor ID */ 109 u_int cpu_fxsr; /* SSE enabled */ 110 u_int cpu_mxcsr_mask; /* Valid bits in mxcsr */ 111 u_int cpu_clflush_line_size = 32; 112 u_int cpu_stdext_feature; /* %ebx */ 113 u_int cpu_stdext_feature2; /* %ecx */ 114 u_int cpu_stdext_feature3; /* %edx */ 115 uint64_t cpu_ia32_arch_caps; 116 u_int cpu_max_ext_state_size; 117 u_int cpu_mon_mwait_flags; /* MONITOR/MWAIT flags (CPUID.05H.ECX) */ 118 u_int cpu_mon_min_size; /* MONITOR minimum range size, bytes */ 119 u_int cpu_mon_max_size; /* MONITOR minimum range size, bytes */ 120 u_int cpu_maxphyaddr; /* Max phys addr width in bits */ 121 char machine[] = MACHINE; 122 123 SYSCTL_UINT(_hw, OID_AUTO, via_feature_rng, CTLFLAG_RD, 124 &via_feature_rng, 0, 125 "VIA RNG feature available in CPU"); 126 SYSCTL_UINT(_hw, OID_AUTO, via_feature_xcrypt, CTLFLAG_RD, 127 &via_feature_xcrypt, 0, 128 "VIA xcrypt feature available in CPU"); 129 130 #ifdef __amd64__ 131 #ifdef SCTL_MASK32 132 extern int adaptive_machine_arch; 133 #endif 134 135 static int 136 sysctl_hw_machine(SYSCTL_HANDLER_ARGS) 137 { 138 #ifdef SCTL_MASK32 139 static const char machine32[] = "i386"; 140 #endif 141 int error; 142 143 #ifdef SCTL_MASK32 144 if ((req->flags & SCTL_MASK32) != 0 && adaptive_machine_arch) 145 error = SYSCTL_OUT(req, machine32, sizeof(machine32)); 146 else 147 #endif 148 error = SYSCTL_OUT(req, machine, sizeof(machine)); 149 return (error); 150 151 } 152 SYSCTL_PROC(_hw, HW_MACHINE, machine, CTLTYPE_STRING | CTLFLAG_RD | 153 CTLFLAG_MPSAFE, NULL, 0, sysctl_hw_machine, "A", "Machine class"); 154 #else 155 SYSCTL_STRING(_hw, HW_MACHINE, machine, CTLFLAG_RD, 156 machine, 0, "Machine class"); 157 #endif 158 159 static char cpu_model[128]; 160 SYSCTL_STRING(_hw, HW_MODEL, model, CTLFLAG_RD | CTLFLAG_MPSAFE, 161 cpu_model, 0, "Machine model"); 162 163 static int hw_clockrate; 164 SYSCTL_INT(_hw, OID_AUTO, clockrate, CTLFLAG_RD, 165 &hw_clockrate, 0, "CPU instruction clock rate"); 166 167 u_int hv_high; 168 char hv_vendor[16]; 169 SYSCTL_STRING(_hw, OID_AUTO, hv_vendor, CTLFLAG_RD | CTLFLAG_MPSAFE, hv_vendor, 170 0, "Hypervisor vendor"); 171 172 static eventhandler_tag tsc_post_tag; 173 174 static char cpu_brand[48]; 175 176 #ifdef __i386__ 177 #define MAX_BRAND_INDEX 8 178 179 static const char *cpu_brandtable[MAX_BRAND_INDEX + 1] = { 180 NULL, /* No brand */ 181 "Intel Celeron", 182 "Intel Pentium III", 183 "Intel Pentium III Xeon", 184 NULL, 185 NULL, 186 NULL, 187 NULL, 188 "Intel Pentium 4" 189 }; 190 191 static struct { 192 char *cpu_name; 193 int cpu_class; 194 } cpus[] = { 195 { "Intel 80286", CPUCLASS_286 }, /* CPU_286 */ 196 { "i386SX", CPUCLASS_386 }, /* CPU_386SX */ 197 { "i386DX", CPUCLASS_386 }, /* CPU_386 */ 198 { "i486SX", CPUCLASS_486 }, /* CPU_486SX */ 199 { "i486DX", CPUCLASS_486 }, /* CPU_486 */ 200 { "Pentium", CPUCLASS_586 }, /* CPU_586 */ 201 { "Cyrix 486", CPUCLASS_486 }, /* CPU_486DLC */ 202 { "Pentium Pro", CPUCLASS_686 }, /* CPU_686 */ 203 { "Cyrix 5x86", CPUCLASS_486 }, /* CPU_M1SC */ 204 { "Cyrix 6x86", CPUCLASS_486 }, /* CPU_M1 */ 205 { "Blue Lightning", CPUCLASS_486 }, /* CPU_BLUE */ 206 { "Cyrix 6x86MX", CPUCLASS_686 }, /* CPU_M2 */ 207 { "NexGen 586", CPUCLASS_386 }, /* CPU_NX586 (XXX) */ 208 { "Cyrix 486S/DX", CPUCLASS_486 }, /* CPU_CY486DX */ 209 { "Pentium II", CPUCLASS_686 }, /* CPU_PII */ 210 { "Pentium III", CPUCLASS_686 }, /* CPU_PIII */ 211 { "Pentium 4", CPUCLASS_686 }, /* CPU_P4 */ 212 }; 213 #endif 214 215 static struct { 216 char *vendor; 217 u_int vendor_id; 218 } cpu_vendors[] = { 219 { INTEL_VENDOR_ID, CPU_VENDOR_INTEL }, /* GenuineIntel */ 220 { AMD_VENDOR_ID, CPU_VENDOR_AMD }, /* AuthenticAMD */ 221 { CENTAUR_VENDOR_ID, CPU_VENDOR_CENTAUR }, /* CentaurHauls */ 222 #ifdef __i386__ 223 { NSC_VENDOR_ID, CPU_VENDOR_NSC }, /* Geode by NSC */ 224 { CYRIX_VENDOR_ID, CPU_VENDOR_CYRIX }, /* CyrixInstead */ 225 { TRANSMETA_VENDOR_ID, CPU_VENDOR_TRANSMETA }, /* GenuineTMx86 */ 226 { SIS_VENDOR_ID, CPU_VENDOR_SIS }, /* SiS SiS SiS */ 227 { UMC_VENDOR_ID, CPU_VENDOR_UMC }, /* UMC UMC UMC */ 228 { NEXGEN_VENDOR_ID, CPU_VENDOR_NEXGEN }, /* NexGenDriven */ 229 { RISE_VENDOR_ID, CPU_VENDOR_RISE }, /* RiseRiseRise */ 230 #if 0 231 /* XXX CPUID 8000_0000h and 8086_0000h, not 0000_0000h */ 232 { "TransmetaCPU", CPU_VENDOR_TRANSMETA }, 233 #endif 234 #endif 235 }; 236 237 void 238 printcpuinfo(void) 239 { 240 u_int regs[4], i; 241 char *brand; 242 243 printf("CPU: "); 244 #ifdef __i386__ 245 cpu_class = cpus[cpu].cpu_class; 246 strncpy(cpu_model, cpus[cpu].cpu_name, sizeof (cpu_model)); 247 #else 248 strncpy(cpu_model, "Hammer", sizeof (cpu_model)); 249 #endif 250 251 /* Check for extended CPUID information and a processor name. */ 252 if (cpu_exthigh >= 0x80000004) { 253 brand = cpu_brand; 254 for (i = 0x80000002; i < 0x80000005; i++) { 255 do_cpuid(i, regs); 256 memcpy(brand, regs, sizeof(regs)); 257 brand += sizeof(regs); 258 } 259 } 260 261 switch (cpu_vendor_id) { 262 case CPU_VENDOR_INTEL: 263 #ifdef __i386__ 264 if ((cpu_id & 0xf00) > 0x300) { 265 u_int brand_index; 266 267 cpu_model[0] = '\0'; 268 269 switch (cpu_id & 0x3000) { 270 case 0x1000: 271 strcpy(cpu_model, "Overdrive "); 272 break; 273 case 0x2000: 274 strcpy(cpu_model, "Dual "); 275 break; 276 } 277 278 switch (cpu_id & 0xf00) { 279 case 0x400: 280 strcat(cpu_model, "i486 "); 281 /* Check the particular flavor of 486 */ 282 switch (cpu_id & 0xf0) { 283 case 0x00: 284 case 0x10: 285 strcat(cpu_model, "DX"); 286 break; 287 case 0x20: 288 strcat(cpu_model, "SX"); 289 break; 290 case 0x30: 291 strcat(cpu_model, "DX2"); 292 break; 293 case 0x40: 294 strcat(cpu_model, "SL"); 295 break; 296 case 0x50: 297 strcat(cpu_model, "SX2"); 298 break; 299 case 0x70: 300 strcat(cpu_model, 301 "DX2 Write-Back Enhanced"); 302 break; 303 case 0x80: 304 strcat(cpu_model, "DX4"); 305 break; 306 } 307 break; 308 case 0x500: 309 /* Check the particular flavor of 586 */ 310 strcat(cpu_model, "Pentium"); 311 switch (cpu_id & 0xf0) { 312 case 0x00: 313 strcat(cpu_model, " A-step"); 314 break; 315 case 0x10: 316 strcat(cpu_model, "/P5"); 317 break; 318 case 0x20: 319 strcat(cpu_model, "/P54C"); 320 break; 321 case 0x30: 322 strcat(cpu_model, "/P24T"); 323 break; 324 case 0x40: 325 strcat(cpu_model, "/P55C"); 326 break; 327 case 0x70: 328 strcat(cpu_model, "/P54C"); 329 break; 330 case 0x80: 331 strcat(cpu_model, "/P55C (quarter-micron)"); 332 break; 333 default: 334 /* nothing */ 335 break; 336 } 337 #if defined(I586_CPU) && !defined(NO_F00F_HACK) 338 /* 339 * XXX - If/when Intel fixes the bug, this 340 * should also check the version of the 341 * CPU, not just that it's a Pentium. 342 */ 343 has_f00f_bug = 1; 344 #endif 345 break; 346 case 0x600: 347 /* Check the particular flavor of 686 */ 348 switch (cpu_id & 0xf0) { 349 case 0x00: 350 strcat(cpu_model, "Pentium Pro A-step"); 351 break; 352 case 0x10: 353 strcat(cpu_model, "Pentium Pro"); 354 break; 355 case 0x30: 356 case 0x50: 357 case 0x60: 358 strcat(cpu_model, 359 "Pentium II/Pentium II Xeon/Celeron"); 360 cpu = CPU_PII; 361 break; 362 case 0x70: 363 case 0x80: 364 case 0xa0: 365 case 0xb0: 366 strcat(cpu_model, 367 "Pentium III/Pentium III Xeon/Celeron"); 368 cpu = CPU_PIII; 369 break; 370 default: 371 strcat(cpu_model, "Unknown 80686"); 372 break; 373 } 374 break; 375 case 0xf00: 376 strcat(cpu_model, "Pentium 4"); 377 cpu = CPU_P4; 378 break; 379 default: 380 strcat(cpu_model, "unknown"); 381 break; 382 } 383 384 /* 385 * If we didn't get a brand name from the extended 386 * CPUID, try to look it up in the brand table. 387 */ 388 if (cpu_high > 0 && *cpu_brand == '\0') { 389 brand_index = cpu_procinfo & CPUID_BRAND_INDEX; 390 if (brand_index <= MAX_BRAND_INDEX && 391 cpu_brandtable[brand_index] != NULL) 392 strcpy(cpu_brand, 393 cpu_brandtable[brand_index]); 394 } 395 } 396 #else 397 /* Please make up your mind folks! */ 398 strcat(cpu_model, "EM64T"); 399 #endif 400 break; 401 case CPU_VENDOR_AMD: 402 /* 403 * Values taken from AMD Processor Recognition 404 * http://www.amd.com/K6/k6docs/pdf/20734g.pdf 405 * (also describes ``Features'' encodings. 406 */ 407 strcpy(cpu_model, "AMD "); 408 #ifdef __i386__ 409 switch (cpu_id & 0xFF0) { 410 case 0x410: 411 strcat(cpu_model, "Standard Am486DX"); 412 break; 413 case 0x430: 414 strcat(cpu_model, "Enhanced Am486DX2 Write-Through"); 415 break; 416 case 0x470: 417 strcat(cpu_model, "Enhanced Am486DX2 Write-Back"); 418 break; 419 case 0x480: 420 strcat(cpu_model, "Enhanced Am486DX4/Am5x86 Write-Through"); 421 break; 422 case 0x490: 423 strcat(cpu_model, "Enhanced Am486DX4/Am5x86 Write-Back"); 424 break; 425 case 0x4E0: 426 strcat(cpu_model, "Am5x86 Write-Through"); 427 break; 428 case 0x4F0: 429 strcat(cpu_model, "Am5x86 Write-Back"); 430 break; 431 case 0x500: 432 strcat(cpu_model, "K5 model 0"); 433 break; 434 case 0x510: 435 strcat(cpu_model, "K5 model 1"); 436 break; 437 case 0x520: 438 strcat(cpu_model, "K5 PR166 (model 2)"); 439 break; 440 case 0x530: 441 strcat(cpu_model, "K5 PR200 (model 3)"); 442 break; 443 case 0x560: 444 strcat(cpu_model, "K6"); 445 break; 446 case 0x570: 447 strcat(cpu_model, "K6 266 (model 1)"); 448 break; 449 case 0x580: 450 strcat(cpu_model, "K6-2"); 451 break; 452 case 0x590: 453 strcat(cpu_model, "K6-III"); 454 break; 455 case 0x5a0: 456 strcat(cpu_model, "Geode LX"); 457 break; 458 default: 459 strcat(cpu_model, "Unknown"); 460 break; 461 } 462 #else 463 if ((cpu_id & 0xf00) == 0xf00) 464 strcat(cpu_model, "AMD64 Processor"); 465 else 466 strcat(cpu_model, "Unknown"); 467 #endif 468 break; 469 #ifdef __i386__ 470 case CPU_VENDOR_CYRIX: 471 strcpy(cpu_model, "Cyrix "); 472 switch (cpu_id & 0xff0) { 473 case 0x440: 474 strcat(cpu_model, "MediaGX"); 475 break; 476 case 0x520: 477 strcat(cpu_model, "6x86"); 478 break; 479 case 0x540: 480 cpu_class = CPUCLASS_586; 481 strcat(cpu_model, "GXm"); 482 break; 483 case 0x600: 484 strcat(cpu_model, "6x86MX"); 485 break; 486 default: 487 /* 488 * Even though CPU supports the cpuid 489 * instruction, it can be disabled. 490 * Therefore, this routine supports all Cyrix 491 * CPUs. 492 */ 493 switch (cyrix_did & 0xf0) { 494 case 0x00: 495 switch (cyrix_did & 0x0f) { 496 case 0x00: 497 strcat(cpu_model, "486SLC"); 498 break; 499 case 0x01: 500 strcat(cpu_model, "486DLC"); 501 break; 502 case 0x02: 503 strcat(cpu_model, "486SLC2"); 504 break; 505 case 0x03: 506 strcat(cpu_model, "486DLC2"); 507 break; 508 case 0x04: 509 strcat(cpu_model, "486SRx"); 510 break; 511 case 0x05: 512 strcat(cpu_model, "486DRx"); 513 break; 514 case 0x06: 515 strcat(cpu_model, "486SRx2"); 516 break; 517 case 0x07: 518 strcat(cpu_model, "486DRx2"); 519 break; 520 case 0x08: 521 strcat(cpu_model, "486SRu"); 522 break; 523 case 0x09: 524 strcat(cpu_model, "486DRu"); 525 break; 526 case 0x0a: 527 strcat(cpu_model, "486SRu2"); 528 break; 529 case 0x0b: 530 strcat(cpu_model, "486DRu2"); 531 break; 532 default: 533 strcat(cpu_model, "Unknown"); 534 break; 535 } 536 break; 537 case 0x10: 538 switch (cyrix_did & 0x0f) { 539 case 0x00: 540 strcat(cpu_model, "486S"); 541 break; 542 case 0x01: 543 strcat(cpu_model, "486S2"); 544 break; 545 case 0x02: 546 strcat(cpu_model, "486Se"); 547 break; 548 case 0x03: 549 strcat(cpu_model, "486S2e"); 550 break; 551 case 0x0a: 552 strcat(cpu_model, "486DX"); 553 break; 554 case 0x0b: 555 strcat(cpu_model, "486DX2"); 556 break; 557 case 0x0f: 558 strcat(cpu_model, "486DX4"); 559 break; 560 default: 561 strcat(cpu_model, "Unknown"); 562 break; 563 } 564 break; 565 case 0x20: 566 if ((cyrix_did & 0x0f) < 8) 567 strcat(cpu_model, "6x86"); /* Where did you get it? */ 568 else 569 strcat(cpu_model, "5x86"); 570 break; 571 case 0x30: 572 strcat(cpu_model, "6x86"); 573 break; 574 case 0x40: 575 if ((cyrix_did & 0xf000) == 0x3000) { 576 cpu_class = CPUCLASS_586; 577 strcat(cpu_model, "GXm"); 578 } else 579 strcat(cpu_model, "MediaGX"); 580 break; 581 case 0x50: 582 strcat(cpu_model, "6x86MX"); 583 break; 584 case 0xf0: 585 switch (cyrix_did & 0x0f) { 586 case 0x0d: 587 strcat(cpu_model, "Overdrive CPU"); 588 break; 589 case 0x0e: 590 strcpy(cpu_model, "Texas Instruments 486SXL"); 591 break; 592 case 0x0f: 593 strcat(cpu_model, "486SLC/DLC"); 594 break; 595 default: 596 strcat(cpu_model, "Unknown"); 597 break; 598 } 599 break; 600 default: 601 strcat(cpu_model, "Unknown"); 602 break; 603 } 604 break; 605 } 606 break; 607 case CPU_VENDOR_RISE: 608 strcpy(cpu_model, "Rise "); 609 switch (cpu_id & 0xff0) { 610 case 0x500: /* 6401 and 6441 (Kirin) */ 611 case 0x520: /* 6510 (Lynx) */ 612 strcat(cpu_model, "mP6"); 613 break; 614 default: 615 strcat(cpu_model, "Unknown"); 616 } 617 break; 618 #endif 619 case CPU_VENDOR_CENTAUR: 620 #ifdef __i386__ 621 switch (cpu_id & 0xff0) { 622 case 0x540: 623 strcpy(cpu_model, "IDT WinChip C6"); 624 break; 625 case 0x580: 626 strcpy(cpu_model, "IDT WinChip 2"); 627 break; 628 case 0x590: 629 strcpy(cpu_model, "IDT WinChip 3"); 630 break; 631 case 0x660: 632 strcpy(cpu_model, "VIA C3 Samuel"); 633 break; 634 case 0x670: 635 if (cpu_id & 0x8) 636 strcpy(cpu_model, "VIA C3 Ezra"); 637 else 638 strcpy(cpu_model, "VIA C3 Samuel 2"); 639 break; 640 case 0x680: 641 strcpy(cpu_model, "VIA C3 Ezra-T"); 642 break; 643 case 0x690: 644 strcpy(cpu_model, "VIA C3 Nehemiah"); 645 break; 646 case 0x6a0: 647 case 0x6d0: 648 strcpy(cpu_model, "VIA C7 Esther"); 649 break; 650 case 0x6f0: 651 strcpy(cpu_model, "VIA Nano"); 652 break; 653 default: 654 strcpy(cpu_model, "VIA/IDT Unknown"); 655 } 656 #else 657 strcpy(cpu_model, "VIA "); 658 if ((cpu_id & 0xff0) == 0x6f0) 659 strcat(cpu_model, "Nano Processor"); 660 else 661 strcat(cpu_model, "Unknown"); 662 #endif 663 break; 664 #ifdef __i386__ 665 case CPU_VENDOR_IBM: 666 strcpy(cpu_model, "Blue Lightning CPU"); 667 break; 668 case CPU_VENDOR_NSC: 669 switch (cpu_id & 0xff0) { 670 case 0x540: 671 strcpy(cpu_model, "Geode SC1100"); 672 cpu = CPU_GEODE1100; 673 break; 674 default: 675 strcpy(cpu_model, "Geode/NSC unknown"); 676 break; 677 } 678 break; 679 #endif 680 default: 681 strcat(cpu_model, "Unknown"); 682 break; 683 } 684 685 /* 686 * Replace cpu_model with cpu_brand minus leading spaces if 687 * we have one. 688 */ 689 brand = cpu_brand; 690 while (*brand == ' ') 691 ++brand; 692 if (*brand != '\0') 693 strcpy(cpu_model, brand); 694 695 printf("%s (", cpu_model); 696 if (tsc_freq != 0) { 697 hw_clockrate = (tsc_freq + 5000) / 1000000; 698 printf("%jd.%02d-MHz ", 699 (intmax_t)(tsc_freq + 4999) / 1000000, 700 (u_int)((tsc_freq + 4999) / 10000) % 100); 701 } 702 #ifdef __i386__ 703 switch(cpu_class) { 704 case CPUCLASS_286: 705 printf("286"); 706 break; 707 case CPUCLASS_386: 708 printf("386"); 709 break; 710 #if defined(I486_CPU) 711 case CPUCLASS_486: 712 printf("486"); 713 break; 714 #endif 715 #if defined(I586_CPU) 716 case CPUCLASS_586: 717 printf("586"); 718 break; 719 #endif 720 #if defined(I686_CPU) 721 case CPUCLASS_686: 722 printf("686"); 723 break; 724 #endif 725 default: 726 printf("Unknown"); /* will panic below... */ 727 } 728 #else 729 printf("K8"); 730 #endif 731 printf("-class CPU)\n"); 732 if (*cpu_vendor) 733 printf(" Origin=\"%s\"", cpu_vendor); 734 if (cpu_id) 735 printf(" Id=0x%x", cpu_id); 736 737 if (cpu_vendor_id == CPU_VENDOR_INTEL || 738 cpu_vendor_id == CPU_VENDOR_AMD || 739 cpu_vendor_id == CPU_VENDOR_CENTAUR || 740 #ifdef __i386__ 741 cpu_vendor_id == CPU_VENDOR_TRANSMETA || 742 cpu_vendor_id == CPU_VENDOR_RISE || 743 cpu_vendor_id == CPU_VENDOR_NSC || 744 (cpu_vendor_id == CPU_VENDOR_CYRIX && ((cpu_id & 0xf00) > 0x500)) || 745 #endif 746 0) { 747 printf(" Family=0x%x", CPUID_TO_FAMILY(cpu_id)); 748 printf(" Model=0x%x", CPUID_TO_MODEL(cpu_id)); 749 printf(" Stepping=%u", cpu_id & CPUID_STEPPING); 750 #ifdef __i386__ 751 if (cpu_vendor_id == CPU_VENDOR_CYRIX) 752 printf("\n DIR=0x%04x", cyrix_did); 753 #endif 754 755 /* 756 * AMD CPUID Specification 757 * http://support.amd.com/us/Embedded_TechDocs/25481.pdf 758 * 759 * Intel Processor Identification and CPUID Instruction 760 * http://www.intel.com/assets/pdf/appnote/241618.pdf 761 */ 762 if (cpu_high > 0) { 763 764 /* 765 * Here we should probably set up flags indicating 766 * whether or not various features are available. 767 * The interesting ones are probably VME, PSE, PAE, 768 * and PGE. The code already assumes without bothering 769 * to check that all CPUs >= Pentium have a TSC and 770 * MSRs. 771 */ 772 printf("\n Features=0x%b", cpu_feature, 773 "\020" 774 "\001FPU" /* Integral FPU */ 775 "\002VME" /* Extended VM86 mode support */ 776 "\003DE" /* Debugging Extensions (CR4.DE) */ 777 "\004PSE" /* 4MByte page tables */ 778 "\005TSC" /* Timestamp counter */ 779 "\006MSR" /* Machine specific registers */ 780 "\007PAE" /* Physical address extension */ 781 "\010MCE" /* Machine Check support */ 782 "\011CX8" /* CMPEXCH8 instruction */ 783 "\012APIC" /* SMP local APIC */ 784 "\013oldMTRR" /* Previous implementation of MTRR */ 785 "\014SEP" /* Fast System Call */ 786 "\015MTRR" /* Memory Type Range Registers */ 787 "\016PGE" /* PG_G (global bit) support */ 788 "\017MCA" /* Machine Check Architecture */ 789 "\020CMOV" /* CMOV instruction */ 790 "\021PAT" /* Page attributes table */ 791 "\022PSE36" /* 36 bit address space support */ 792 "\023PN" /* Processor Serial number */ 793 "\024CLFLUSH" /* Has the CLFLUSH instruction */ 794 "\025<b20>" 795 "\026DTS" /* Debug Trace Store */ 796 "\027ACPI" /* ACPI support */ 797 "\030MMX" /* MMX instructions */ 798 "\031FXSR" /* FXSAVE/FXRSTOR */ 799 "\032SSE" /* Streaming SIMD Extensions */ 800 "\033SSE2" /* Streaming SIMD Extensions #2 */ 801 "\034SS" /* Self snoop */ 802 "\035HTT" /* Hyperthreading (see EBX bit 16-23) */ 803 "\036TM" /* Thermal Monitor clock slowdown */ 804 "\037IA64" /* CPU can execute IA64 instructions */ 805 "\040PBE" /* Pending Break Enable */ 806 ); 807 808 if (cpu_feature2 != 0) { 809 printf("\n Features2=0x%b", cpu_feature2, 810 "\020" 811 "\001SSE3" /* SSE3 */ 812 "\002PCLMULQDQ" /* Carry-Less Mul Quadword */ 813 "\003DTES64" /* 64-bit Debug Trace */ 814 "\004MON" /* MONITOR/MWAIT Instructions */ 815 "\005DS_CPL" /* CPL Qualified Debug Store */ 816 "\006VMX" /* Virtual Machine Extensions */ 817 "\007SMX" /* Safer Mode Extensions */ 818 "\010EST" /* Enhanced SpeedStep */ 819 "\011TM2" /* Thermal Monitor 2 */ 820 "\012SSSE3" /* SSSE3 */ 821 "\013CNXT-ID" /* L1 context ID available */ 822 "\014SDBG" /* IA32 silicon debug */ 823 "\015FMA" /* Fused Multiply Add */ 824 "\016CX16" /* CMPXCHG16B Instruction */ 825 "\017xTPR" /* Send Task Priority Messages*/ 826 "\020PDCM" /* Perf/Debug Capability MSR */ 827 "\021<b16>" 828 "\022PCID" /* Process-context Identifiers*/ 829 "\023DCA" /* Direct Cache Access */ 830 "\024SSE4.1" /* SSE 4.1 */ 831 "\025SSE4.2" /* SSE 4.2 */ 832 "\026x2APIC" /* xAPIC Extensions */ 833 "\027MOVBE" /* MOVBE Instruction */ 834 "\030POPCNT" /* POPCNT Instruction */ 835 "\031TSCDLT" /* TSC-Deadline Timer */ 836 "\032AESNI" /* AES Crypto */ 837 "\033XSAVE" /* XSAVE/XRSTOR States */ 838 "\034OSXSAVE" /* OS-Enabled State Management*/ 839 "\035AVX" /* Advanced Vector Extensions */ 840 "\036F16C" /* Half-precision conversions */ 841 "\037RDRAND" /* RDRAND Instruction */ 842 "\040HV" /* Hypervisor */ 843 ); 844 } 845 846 if (amd_feature != 0) { 847 printf("\n AMD Features=0x%b", amd_feature, 848 "\020" /* in hex */ 849 "\001<s0>" /* Same */ 850 "\002<s1>" /* Same */ 851 "\003<s2>" /* Same */ 852 "\004<s3>" /* Same */ 853 "\005<s4>" /* Same */ 854 "\006<s5>" /* Same */ 855 "\007<s6>" /* Same */ 856 "\010<s7>" /* Same */ 857 "\011<s8>" /* Same */ 858 "\012<s9>" /* Same */ 859 "\013<b10>" /* Undefined */ 860 "\014SYSCALL" /* Have SYSCALL/SYSRET */ 861 "\015<s12>" /* Same */ 862 "\016<s13>" /* Same */ 863 "\017<s14>" /* Same */ 864 "\020<s15>" /* Same */ 865 "\021<s16>" /* Same */ 866 "\022<s17>" /* Same */ 867 "\023<b18>" /* Reserved, unknown */ 868 "\024MP" /* Multiprocessor Capable */ 869 "\025NX" /* Has EFER.NXE, NX */ 870 "\026<b21>" /* Undefined */ 871 "\027MMX+" /* AMD MMX Extensions */ 872 "\030<s23>" /* Same */ 873 "\031<s24>" /* Same */ 874 "\032FFXSR" /* Fast FXSAVE/FXRSTOR */ 875 "\033Page1GB" /* 1-GB large page support */ 876 "\034RDTSCP" /* RDTSCP */ 877 "\035<b28>" /* Undefined */ 878 "\036LM" /* 64 bit long mode */ 879 "\0373DNow!+" /* AMD 3DNow! Extensions */ 880 "\0403DNow!" /* AMD 3DNow! */ 881 ); 882 } 883 884 if (amd_feature2 != 0) { 885 printf("\n AMD Features2=0x%b", amd_feature2, 886 "\020" 887 "\001LAHF" /* LAHF/SAHF in long mode */ 888 "\002CMP" /* CMP legacy */ 889 "\003SVM" /* Secure Virtual Mode */ 890 "\004ExtAPIC" /* Extended APIC register */ 891 "\005CR8" /* CR8 in legacy mode */ 892 "\006ABM" /* LZCNT instruction */ 893 "\007SSE4A" /* SSE4A */ 894 "\010MAS" /* Misaligned SSE mode */ 895 "\011Prefetch" /* 3DNow! Prefetch/PrefetchW */ 896 "\012OSVW" /* OS visible workaround */ 897 "\013IBS" /* Instruction based sampling */ 898 "\014XOP" /* XOP extended instructions */ 899 "\015SKINIT" /* SKINIT/STGI */ 900 "\016WDT" /* Watchdog timer */ 901 "\017<b14>" 902 "\020LWP" /* Lightweight Profiling */ 903 "\021FMA4" /* 4-operand FMA instructions */ 904 "\022TCE" /* Translation Cache Extension */ 905 "\023<b18>" 906 "\024NodeId" /* NodeId MSR support */ 907 "\025<b20>" 908 "\026TBM" /* Trailing Bit Manipulation */ 909 "\027Topology" /* Topology Extensions */ 910 "\030PCXC" /* Core perf count */ 911 "\031PNXC" /* NB perf count */ 912 "\032<b25>" 913 "\033DBE" /* Data Breakpoint extension */ 914 "\034PTSC" /* Performance TSC */ 915 "\035PL2I" /* L2I perf count */ 916 "\036MWAITX" /* MONITORX/MWAITX instructions */ 917 "\037<b30>" 918 "\040<b31>" 919 ); 920 } 921 922 if (cpu_stdext_feature != 0) { 923 printf("\n Structured Extended Features=0x%b", 924 cpu_stdext_feature, 925 "\020" 926 /* RDFSBASE/RDGSBASE/WRFSBASE/WRGSBASE */ 927 "\001FSGSBASE" 928 "\002TSCADJ" 929 "\003SGX" 930 /* Bit Manipulation Instructions */ 931 "\004BMI1" 932 /* Hardware Lock Elision */ 933 "\005HLE" 934 /* Advanced Vector Instructions 2 */ 935 "\006AVX2" 936 /* FDP_EXCPTN_ONLY */ 937 "\007FDPEXC" 938 /* Supervisor Mode Execution Prot. */ 939 "\010SMEP" 940 /* Bit Manipulation Instructions */ 941 "\011BMI2" 942 "\012ERMS" 943 /* Invalidate Processor Context ID */ 944 "\013INVPCID" 945 /* Restricted Transactional Memory */ 946 "\014RTM" 947 "\015PQM" 948 "\016NFPUSG" 949 /* Intel Memory Protection Extensions */ 950 "\017MPX" 951 "\020PQE" 952 /* AVX512 Foundation */ 953 "\021AVX512F" 954 "\022AVX512DQ" 955 /* Enhanced NRBG */ 956 "\023RDSEED" 957 /* ADCX + ADOX */ 958 "\024ADX" 959 /* Supervisor Mode Access Prevention */ 960 "\025SMAP" 961 "\026AVX512IFMA" 962 "\027PCOMMIT" 963 "\030CLFLUSHOPT" 964 "\031CLWB" 965 "\032PROCTRACE" 966 "\033AVX512PF" 967 "\034AVX512ER" 968 "\035AVX512CD" 969 "\036SHA" 970 "\037AVX512BW" 971 "\040AVX512VL" 972 ); 973 } 974 975 if (cpu_stdext_feature2 != 0) { 976 printf("\n Structured Extended Features2=0x%b", 977 cpu_stdext_feature2, 978 "\020" 979 "\001PREFETCHWT1" 980 "\002AVX512VBMI" 981 "\003UMIP" 982 "\004PKU" 983 "\005OSPKE" 984 "\006WAITPKG" 985 "\011GFNI" 986 "\027RDPID" 987 "\032CLDEMOTE" 988 "\034MOVDIRI" 989 "\035MOVDIRI64B" 990 "\037SGXLC" 991 ); 992 } 993 994 if (cpu_stdext_feature3 != 0) { 995 printf("\n Structured Extended Features3=0x%b", 996 cpu_stdext_feature3, 997 "\020" 998 "\033IBPB" 999 "\034STIBP" 1000 "\035L1DFL" 1001 "\036ARCH_CAP" 1002 "\037CORE_CAP" 1003 "\040SSBD" 1004 ); 1005 } 1006 1007 if ((cpu_feature2 & CPUID2_XSAVE) != 0) { 1008 cpuid_count(0xd, 0x1, regs); 1009 if (regs[0] != 0) { 1010 printf("\n XSAVE Features=0x%b", 1011 regs[0], 1012 "\020" 1013 "\001XSAVEOPT" 1014 "\002XSAVEC" 1015 "\003XINUSE" 1016 "\004XSAVES"); 1017 } 1018 } 1019 1020 if (cpu_ia32_arch_caps != 0) { 1021 printf("\n IA32_ARCH_CAPS=0x%b", 1022 (u_int)cpu_ia32_arch_caps, 1023 "\020" 1024 "\001RDCL_NO" 1025 "\002IBRS_ALL" 1026 "\003RSBA" 1027 "\004SKIP_L1DFL_VME" 1028 "\005SSB_NO" 1029 ); 1030 } 1031 1032 if (amd_extended_feature_extensions != 0) { 1033 u_int amd_fe_masked; 1034 1035 amd_fe_masked = amd_extended_feature_extensions; 1036 if ((amd_fe_masked & AMDFEID_IBRS) == 0) 1037 amd_fe_masked &= 1038 ~(AMDFEID_IBRS_ALWAYSON | 1039 AMDFEID_PREFER_IBRS); 1040 if ((amd_fe_masked & AMDFEID_STIBP) == 0) 1041 amd_fe_masked &= 1042 ~AMDFEID_STIBP_ALWAYSON; 1043 1044 printf("\n " 1045 "AMD Extended Feature Extensions ID EBX=" 1046 "0x%b", amd_fe_masked, 1047 "\020" 1048 "\001CLZERO" 1049 "\002IRPerf" 1050 "\003XSaveErPtr" 1051 "\015IBPB" 1052 "\017IBRS" 1053 "\020STIBP" 1054 "\021IBRS_ALWAYSON" 1055 "\022STIBP_ALWAYSON" 1056 "\023PREFER_IBRS" 1057 "\031SSBD" 1058 "\032VIRT_SSBD" 1059 "\033SSB_NO" 1060 ); 1061 } 1062 1063 if (via_feature_rng != 0 || via_feature_xcrypt != 0) 1064 print_via_padlock_info(); 1065 1066 if (cpu_feature2 & CPUID2_VMX) 1067 print_vmx_info(); 1068 1069 if (amd_feature2 & AMDID2_SVM) 1070 print_svm_info(); 1071 1072 if ((cpu_feature & CPUID_HTT) && 1073 cpu_vendor_id == CPU_VENDOR_AMD) 1074 cpu_feature &= ~CPUID_HTT; 1075 1076 /* 1077 * If this CPU supports P-state invariant TSC then 1078 * mention the capability. 1079 */ 1080 if (tsc_is_invariant) { 1081 printf("\n TSC: P-state invariant"); 1082 if (tsc_perf_stat) 1083 printf(", performance statistics"); 1084 } 1085 } 1086 #ifdef __i386__ 1087 } else if (cpu_vendor_id == CPU_VENDOR_CYRIX) { 1088 printf(" DIR=0x%04x", cyrix_did); 1089 printf(" Stepping=%u", (cyrix_did & 0xf000) >> 12); 1090 printf(" Revision=%u", (cyrix_did & 0x0f00) >> 8); 1091 #ifndef CYRIX_CACHE_REALLY_WORKS 1092 if (cpu == CPU_M1 && (cyrix_did & 0xff00) < 0x1700) 1093 printf("\n CPU cache: write-through mode"); 1094 #endif 1095 #endif 1096 } 1097 1098 /* Avoid ugly blank lines: only print newline when we have to. */ 1099 if (*cpu_vendor || cpu_id) 1100 printf("\n"); 1101 1102 if (bootverbose) { 1103 if (cpu_vendor_id == CPU_VENDOR_AMD) 1104 print_AMD_info(); 1105 else if (cpu_vendor_id == CPU_VENDOR_INTEL) 1106 print_INTEL_info(); 1107 #ifdef __i386__ 1108 else if (cpu_vendor_id == CPU_VENDOR_TRANSMETA) 1109 print_transmeta_info(); 1110 #endif 1111 } 1112 1113 print_hypervisor_info(); 1114 } 1115 1116 #ifdef __i386__ 1117 void 1118 panicifcpuunsupported(void) 1119 { 1120 1121 #if !defined(lint) 1122 #if !defined(I486_CPU) && !defined(I586_CPU) && !defined(I686_CPU) 1123 #error This kernel is not configured for one of the supported CPUs 1124 #endif 1125 #else /* lint */ 1126 #endif /* lint */ 1127 /* 1128 * Now that we have told the user what they have, 1129 * let them know if that machine type isn't configured. 1130 */ 1131 switch (cpu_class) { 1132 case CPUCLASS_286: /* a 286 should not make it this far, anyway */ 1133 case CPUCLASS_386: 1134 #if !defined(I486_CPU) 1135 case CPUCLASS_486: 1136 #endif 1137 #if !defined(I586_CPU) 1138 case CPUCLASS_586: 1139 #endif 1140 #if !defined(I686_CPU) 1141 case CPUCLASS_686: 1142 #endif 1143 panic("CPU class not configured"); 1144 default: 1145 break; 1146 } 1147 } 1148 1149 static volatile u_int trap_by_rdmsr; 1150 1151 /* 1152 * Special exception 6 handler. 1153 * The rdmsr instruction generates invalid opcodes fault on 486-class 1154 * Cyrix CPU. Stacked eip register points the rdmsr instruction in the 1155 * function identblue() when this handler is called. Stacked eip should 1156 * be advanced. 1157 */ 1158 inthand_t bluetrap6; 1159 #ifdef __GNUCLIKE_ASM 1160 __asm 1161 (" \n\ 1162 .text \n\ 1163 .p2align 2,0x90 \n\ 1164 .type " __XSTRING(CNAME(bluetrap6)) ",@function \n\ 1165 " __XSTRING(CNAME(bluetrap6)) ": \n\ 1166 ss \n\ 1167 movl $0xa8c1d," __XSTRING(CNAME(trap_by_rdmsr)) " \n\ 1168 addl $2, (%esp) /* rdmsr is a 2-byte instruction */ \n\ 1169 iret \n\ 1170 "); 1171 #endif 1172 1173 /* 1174 * Special exception 13 handler. 1175 * Accessing non-existent MSR generates general protection fault. 1176 */ 1177 inthand_t bluetrap13; 1178 #ifdef __GNUCLIKE_ASM 1179 __asm 1180 (" \n\ 1181 .text \n\ 1182 .p2align 2,0x90 \n\ 1183 .type " __XSTRING(CNAME(bluetrap13)) ",@function \n\ 1184 " __XSTRING(CNAME(bluetrap13)) ": \n\ 1185 ss \n\ 1186 movl $0xa89c4," __XSTRING(CNAME(trap_by_rdmsr)) " \n\ 1187 popl %eax /* discard error code */ \n\ 1188 addl $2, (%esp) /* rdmsr is a 2-byte instruction */ \n\ 1189 iret \n\ 1190 "); 1191 #endif 1192 1193 /* 1194 * Distinguish IBM Blue Lightning CPU from Cyrix CPUs that does not 1195 * support cpuid instruction. This function should be called after 1196 * loading interrupt descriptor table register. 1197 * 1198 * I don't like this method that handles fault, but I couldn't get 1199 * information for any other methods. Does blue giant know? 1200 */ 1201 static int 1202 identblue(void) 1203 { 1204 1205 trap_by_rdmsr = 0; 1206 1207 /* 1208 * Cyrix 486-class CPU does not support rdmsr instruction. 1209 * The rdmsr instruction generates invalid opcode fault, and exception 1210 * will be trapped by bluetrap6() on Cyrix 486-class CPU. The 1211 * bluetrap6() set the magic number to trap_by_rdmsr. 1212 */ 1213 setidt(IDT_UD, bluetrap6, SDT_SYS386TGT, SEL_KPL, 1214 GSEL(GCODE_SEL, SEL_KPL)); 1215 1216 /* 1217 * Certain BIOS disables cpuid instruction of Cyrix 6x86MX CPU. 1218 * In this case, rdmsr generates general protection fault, and 1219 * exception will be trapped by bluetrap13(). 1220 */ 1221 setidt(IDT_GP, bluetrap13, SDT_SYS386TGT, SEL_KPL, 1222 GSEL(GCODE_SEL, SEL_KPL)); 1223 1224 rdmsr(0x1002); /* Cyrix CPU generates fault. */ 1225 1226 if (trap_by_rdmsr == 0xa8c1d) 1227 return IDENTBLUE_CYRIX486; 1228 else if (trap_by_rdmsr == 0xa89c4) 1229 return IDENTBLUE_CYRIXM2; 1230 return IDENTBLUE_IBMCPU; 1231 } 1232 1233 1234 /* 1235 * identifycyrix() set lower 16 bits of cyrix_did as follows: 1236 * 1237 * F E D C B A 9 8 7 6 5 4 3 2 1 0 1238 * +-------+-------+---------------+ 1239 * | SID | RID | Device ID | 1240 * | (DIR 1) | (DIR 0) | 1241 * +-------+-------+---------------+ 1242 */ 1243 static void 1244 identifycyrix(void) 1245 { 1246 register_t saveintr; 1247 int ccr2_test = 0, dir_test = 0; 1248 u_char ccr2, ccr3; 1249 1250 saveintr = intr_disable(); 1251 1252 ccr2 = read_cyrix_reg(CCR2); 1253 write_cyrix_reg(CCR2, ccr2 ^ CCR2_LOCK_NW); 1254 read_cyrix_reg(CCR2); 1255 if (read_cyrix_reg(CCR2) != ccr2) 1256 ccr2_test = 1; 1257 write_cyrix_reg(CCR2, ccr2); 1258 1259 ccr3 = read_cyrix_reg(CCR3); 1260 write_cyrix_reg(CCR3, ccr3 ^ CCR3_MAPEN3); 1261 read_cyrix_reg(CCR3); 1262 if (read_cyrix_reg(CCR3) != ccr3) 1263 dir_test = 1; /* CPU supports DIRs. */ 1264 write_cyrix_reg(CCR3, ccr3); 1265 1266 if (dir_test) { 1267 /* Device ID registers are available. */ 1268 cyrix_did = read_cyrix_reg(DIR1) << 8; 1269 cyrix_did += read_cyrix_reg(DIR0); 1270 } else if (ccr2_test) 1271 cyrix_did = 0x0010; /* 486S A-step */ 1272 else 1273 cyrix_did = 0x00ff; /* Old 486SLC/DLC and TI486SXLC/SXL */ 1274 1275 intr_restore(saveintr); 1276 } 1277 #endif 1278 1279 /* Update TSC freq with the value indicated by the caller. */ 1280 static void 1281 tsc_freq_changed(void *arg __unused, const struct cf_level *level, int status) 1282 { 1283 1284 /* If there was an error during the transition, don't do anything. */ 1285 if (status != 0) 1286 return; 1287 1288 /* Total setting for this level gives the new frequency in MHz. */ 1289 hw_clockrate = level->total_set.freq; 1290 } 1291 1292 static void 1293 hook_tsc_freq(void *arg __unused) 1294 { 1295 1296 if (tsc_is_invariant) 1297 return; 1298 1299 tsc_post_tag = EVENTHANDLER_REGISTER(cpufreq_post_change, 1300 tsc_freq_changed, NULL, EVENTHANDLER_PRI_ANY); 1301 } 1302 1303 SYSINIT(hook_tsc_freq, SI_SUB_CONFIGURE, SI_ORDER_ANY, hook_tsc_freq, NULL); 1304 1305 static const char *const vm_bnames[] = { 1306 "QEMU", /* QEMU */ 1307 "Plex86", /* Plex86 */ 1308 "Bochs", /* Bochs */ 1309 "Xen", /* Xen */ 1310 "BHYVE", /* bhyve */ 1311 "Seabios", /* KVM */ 1312 NULL 1313 }; 1314 1315 static const char *const vm_pnames[] = { 1316 "VMware Virtual Platform", /* VMWare VM */ 1317 "Virtual Machine", /* Microsoft VirtualPC */ 1318 "VirtualBox", /* Sun xVM VirtualBox */ 1319 "Parallels Virtual Platform", /* Parallels VM */ 1320 "KVM", /* KVM */ 1321 NULL 1322 }; 1323 1324 void 1325 identify_hypervisor(void) 1326 { 1327 u_int regs[4]; 1328 char *p; 1329 int i; 1330 1331 /* 1332 * [RFC] CPUID usage for interaction between Hypervisors and Linux. 1333 * http://lkml.org/lkml/2008/10/1/246 1334 * 1335 * KB1009458: Mechanisms to determine if software is running in 1336 * a VMware virtual machine 1337 * http://kb.vmware.com/kb/1009458 1338 */ 1339 if (cpu_feature2 & CPUID2_HV) { 1340 vm_guest = VM_GUEST_VM; 1341 do_cpuid(0x40000000, regs); 1342 1343 /* 1344 * KVM from Linux kernels prior to commit 1345 * 57c22e5f35aa4b9b2fe11f73f3e62bbf9ef36190 set %eax 1346 * to 0 rather than a valid hv_high value. Check for 1347 * the KVM signature bytes and fixup %eax to the 1348 * highest supported leaf in that case. 1349 */ 1350 if (regs[0] == 0 && regs[1] == 0x4b4d564b && 1351 regs[2] == 0x564b4d56 && regs[3] == 0x0000004d) 1352 regs[0] = 0x40000001; 1353 1354 if (regs[0] >= 0x40000000) { 1355 hv_high = regs[0]; 1356 ((u_int *)&hv_vendor)[0] = regs[1]; 1357 ((u_int *)&hv_vendor)[1] = regs[2]; 1358 ((u_int *)&hv_vendor)[2] = regs[3]; 1359 hv_vendor[12] = '\0'; 1360 if (strcmp(hv_vendor, "VMwareVMware") == 0) 1361 vm_guest = VM_GUEST_VMWARE; 1362 else if (strcmp(hv_vendor, "Microsoft Hv") == 0) 1363 vm_guest = VM_GUEST_HV; 1364 else if (strcmp(hv_vendor, "KVMKVMKVM") == 0) 1365 vm_guest = VM_GUEST_KVM; 1366 else if (strcmp(hv_vendor, "bhyve bhyve") == 0) 1367 vm_guest = VM_GUEST_BHYVE; 1368 } 1369 return; 1370 } 1371 1372 /* 1373 * Examine SMBIOS strings for older hypervisors. 1374 */ 1375 p = kern_getenv("smbios.system.serial"); 1376 if (p != NULL) { 1377 if (strncmp(p, "VMware-", 7) == 0 || strncmp(p, "VMW", 3) == 0) { 1378 vmware_hvcall(VMW_HVCMD_GETVERSION, regs); 1379 if (regs[1] == VMW_HVMAGIC) { 1380 vm_guest = VM_GUEST_VMWARE; 1381 freeenv(p); 1382 return; 1383 } 1384 } 1385 freeenv(p); 1386 } 1387 1388 /* 1389 * XXX: Some of these entries may not be needed since they were 1390 * added to FreeBSD before the checks above. 1391 */ 1392 p = kern_getenv("smbios.bios.vendor"); 1393 if (p != NULL) { 1394 for (i = 0; vm_bnames[i] != NULL; i++) 1395 if (strcmp(p, vm_bnames[i]) == 0) { 1396 vm_guest = VM_GUEST_VM; 1397 freeenv(p); 1398 return; 1399 } 1400 freeenv(p); 1401 } 1402 p = kern_getenv("smbios.system.product"); 1403 if (p != NULL) { 1404 for (i = 0; vm_pnames[i] != NULL; i++) 1405 if (strcmp(p, vm_pnames[i]) == 0) { 1406 vm_guest = VM_GUEST_VM; 1407 freeenv(p); 1408 return; 1409 } 1410 freeenv(p); 1411 } 1412 } 1413 1414 bool 1415 fix_cpuid(void) 1416 { 1417 uint64_t msr; 1418 1419 /* 1420 * Clear "Limit CPUID Maxval" bit and return true if the caller should 1421 * get the largest standard CPUID function number again if it is set 1422 * from BIOS. It is necessary for probing correct CPU topology later 1423 * and for the correct operation of the AVX-aware userspace. 1424 */ 1425 if (cpu_vendor_id == CPU_VENDOR_INTEL && 1426 ((CPUID_TO_FAMILY(cpu_id) == 0xf && 1427 CPUID_TO_MODEL(cpu_id) >= 0x3) || 1428 (CPUID_TO_FAMILY(cpu_id) == 0x6 && 1429 CPUID_TO_MODEL(cpu_id) >= 0xe))) { 1430 msr = rdmsr(MSR_IA32_MISC_ENABLE); 1431 if ((msr & IA32_MISC_EN_LIMCPUID) != 0) { 1432 msr &= ~IA32_MISC_EN_LIMCPUID; 1433 wrmsr(MSR_IA32_MISC_ENABLE, msr); 1434 return (true); 1435 } 1436 } 1437 1438 /* 1439 * Re-enable AMD Topology Extension that could be disabled by BIOS 1440 * on some notebook processors. Without the extension it's really 1441 * hard to determine the correct CPU cache topology. 1442 * See BIOS and Kernel Developer’s Guide (BKDG) for AMD Family 15h 1443 * Models 60h-6Fh Processors, Publication # 50742. 1444 */ 1445 if (vm_guest == VM_GUEST_NO && cpu_vendor_id == CPU_VENDOR_AMD && 1446 CPUID_TO_FAMILY(cpu_id) == 0x15) { 1447 msr = rdmsr(MSR_EXTFEATURES); 1448 if ((msr & ((uint64_t)1 << 54)) == 0) { 1449 msr |= (uint64_t)1 << 54; 1450 wrmsr(MSR_EXTFEATURES, msr); 1451 return (true); 1452 } 1453 } 1454 return (false); 1455 } 1456 1457 void 1458 identify_cpu1(void) 1459 { 1460 u_int regs[4]; 1461 1462 do_cpuid(0, regs); 1463 cpu_high = regs[0]; 1464 ((u_int *)&cpu_vendor)[0] = regs[1]; 1465 ((u_int *)&cpu_vendor)[1] = regs[3]; 1466 ((u_int *)&cpu_vendor)[2] = regs[2]; 1467 cpu_vendor[12] = '\0'; 1468 1469 do_cpuid(1, regs); 1470 cpu_id = regs[0]; 1471 cpu_procinfo = regs[1]; 1472 cpu_feature = regs[3]; 1473 cpu_feature2 = regs[2]; 1474 } 1475 1476 void 1477 identify_cpu2(void) 1478 { 1479 u_int regs[4], cpu_stdext_disable; 1480 1481 if (cpu_high >= 7) { 1482 cpuid_count(7, 0, regs); 1483 cpu_stdext_feature = regs[1]; 1484 1485 /* 1486 * Some hypervisors failed to filter out unsupported 1487 * extended features. Allow to disable the 1488 * extensions, activation of which requires setting a 1489 * bit in CR4, and which VM monitors do not support. 1490 */ 1491 cpu_stdext_disable = 0; 1492 TUNABLE_INT_FETCH("hw.cpu_stdext_disable", &cpu_stdext_disable); 1493 cpu_stdext_feature &= ~cpu_stdext_disable; 1494 1495 cpu_stdext_feature2 = regs[2]; 1496 cpu_stdext_feature3 = regs[3]; 1497 1498 if ((cpu_stdext_feature3 & CPUID_STDEXT3_ARCH_CAP) != 0) 1499 cpu_ia32_arch_caps = rdmsr(MSR_IA32_ARCH_CAP); 1500 } 1501 } 1502 1503 void 1504 identify_cpu_fixup_bsp(void) 1505 { 1506 u_int regs[4]; 1507 1508 cpu_vendor_id = find_cpu_vendor_id(); 1509 1510 if (fix_cpuid()) { 1511 do_cpuid(0, regs); 1512 cpu_high = regs[0]; 1513 } 1514 } 1515 1516 /* 1517 * Final stage of CPU identification. 1518 */ 1519 void 1520 finishidentcpu(void) 1521 { 1522 u_int regs[4]; 1523 #ifdef __i386__ 1524 u_char ccr3; 1525 #endif 1526 1527 identify_cpu_fixup_bsp(); 1528 1529 if (cpu_high >= 5 && (cpu_feature2 & CPUID2_MON) != 0) { 1530 do_cpuid(5, regs); 1531 cpu_mon_mwait_flags = regs[2]; 1532 cpu_mon_min_size = regs[0] & CPUID5_MON_MIN_SIZE; 1533 cpu_mon_max_size = regs[1] & CPUID5_MON_MAX_SIZE; 1534 } 1535 1536 identify_cpu2(); 1537 1538 #ifdef __i386__ 1539 if (cpu_high > 0 && 1540 (cpu_vendor_id == CPU_VENDOR_INTEL || 1541 cpu_vendor_id == CPU_VENDOR_AMD || 1542 cpu_vendor_id == CPU_VENDOR_TRANSMETA || 1543 cpu_vendor_id == CPU_VENDOR_CENTAUR || 1544 cpu_vendor_id == CPU_VENDOR_NSC)) { 1545 do_cpuid(0x80000000, regs); 1546 if (regs[0] >= 0x80000000) 1547 cpu_exthigh = regs[0]; 1548 } 1549 #else 1550 if (cpu_vendor_id == CPU_VENDOR_INTEL || 1551 cpu_vendor_id == CPU_VENDOR_AMD || 1552 cpu_vendor_id == CPU_VENDOR_CENTAUR) { 1553 do_cpuid(0x80000000, regs); 1554 cpu_exthigh = regs[0]; 1555 } 1556 #endif 1557 if (cpu_exthigh >= 0x80000001) { 1558 do_cpuid(0x80000001, regs); 1559 amd_feature = regs[3] & ~(cpu_feature & 0x0183f3ff); 1560 amd_feature2 = regs[2]; 1561 } 1562 if (cpu_exthigh >= 0x80000007) { 1563 do_cpuid(0x80000007, regs); 1564 amd_rascap = regs[1]; 1565 amd_pminfo = regs[3]; 1566 } 1567 if (cpu_exthigh >= 0x80000008) { 1568 do_cpuid(0x80000008, regs); 1569 cpu_maxphyaddr = regs[0] & 0xff; 1570 amd_extended_feature_extensions = regs[1]; 1571 cpu_procinfo2 = regs[2]; 1572 } else { 1573 cpu_maxphyaddr = (cpu_feature & CPUID_PAE) != 0 ? 36 : 32; 1574 } 1575 1576 #ifdef __i386__ 1577 if (cpu_vendor_id == CPU_VENDOR_CYRIX) { 1578 if (cpu == CPU_486) { 1579 /* 1580 * These conditions are equivalent to: 1581 * - CPU does not support cpuid instruction. 1582 * - Cyrix/IBM CPU is detected. 1583 */ 1584 if (identblue() == IDENTBLUE_IBMCPU) { 1585 strcpy(cpu_vendor, "IBM"); 1586 cpu_vendor_id = CPU_VENDOR_IBM; 1587 cpu = CPU_BLUE; 1588 return; 1589 } 1590 } 1591 switch (cpu_id & 0xf00) { 1592 case 0x600: 1593 /* 1594 * Cyrix's datasheet does not describe DIRs. 1595 * Therefor, I assume it does not have them 1596 * and use the result of the cpuid instruction. 1597 * XXX they seem to have it for now at least. -Peter 1598 */ 1599 identifycyrix(); 1600 cpu = CPU_M2; 1601 break; 1602 default: 1603 identifycyrix(); 1604 /* 1605 * This routine contains a trick. 1606 * Don't check (cpu_id & 0x00f0) == 0x50 to detect M2, now. 1607 */ 1608 switch (cyrix_did & 0x00f0) { 1609 case 0x00: 1610 case 0xf0: 1611 cpu = CPU_486DLC; 1612 break; 1613 case 0x10: 1614 cpu = CPU_CY486DX; 1615 break; 1616 case 0x20: 1617 if ((cyrix_did & 0x000f) < 8) 1618 cpu = CPU_M1; 1619 else 1620 cpu = CPU_M1SC; 1621 break; 1622 case 0x30: 1623 cpu = CPU_M1; 1624 break; 1625 case 0x40: 1626 /* MediaGX CPU */ 1627 cpu = CPU_M1SC; 1628 break; 1629 default: 1630 /* M2 and later CPUs are treated as M2. */ 1631 cpu = CPU_M2; 1632 1633 /* 1634 * enable cpuid instruction. 1635 */ 1636 ccr3 = read_cyrix_reg(CCR3); 1637 write_cyrix_reg(CCR3, CCR3_MAPEN0); 1638 write_cyrix_reg(CCR4, read_cyrix_reg(CCR4) | CCR4_CPUID); 1639 write_cyrix_reg(CCR3, ccr3); 1640 1641 do_cpuid(0, regs); 1642 cpu_high = regs[0]; /* eax */ 1643 do_cpuid(1, regs); 1644 cpu_id = regs[0]; /* eax */ 1645 cpu_feature = regs[3]; /* edx */ 1646 break; 1647 } 1648 } 1649 } else if (cpu == CPU_486 && *cpu_vendor == '\0') { 1650 /* 1651 * There are BlueLightning CPUs that do not change 1652 * undefined flags by dividing 5 by 2. In this case, 1653 * the CPU identification routine in locore.s leaves 1654 * cpu_vendor null string and puts CPU_486 into the 1655 * cpu. 1656 */ 1657 if (identblue() == IDENTBLUE_IBMCPU) { 1658 strcpy(cpu_vendor, "IBM"); 1659 cpu_vendor_id = CPU_VENDOR_IBM; 1660 cpu = CPU_BLUE; 1661 return; 1662 } 1663 } 1664 #endif 1665 } 1666 1667 int 1668 pti_get_default(void) 1669 { 1670 1671 if (strcmp(cpu_vendor, AMD_VENDOR_ID) == 0) 1672 return (0); 1673 if ((cpu_ia32_arch_caps & IA32_ARCH_CAP_RDCL_NO) != 0) 1674 return (0); 1675 return (1); 1676 } 1677 1678 static u_int 1679 find_cpu_vendor_id(void) 1680 { 1681 int i; 1682 1683 for (i = 0; i < nitems(cpu_vendors); i++) 1684 if (strcmp(cpu_vendor, cpu_vendors[i].vendor) == 0) 1685 return (cpu_vendors[i].vendor_id); 1686 return (0); 1687 } 1688 1689 static void 1690 print_AMD_assoc(int i) 1691 { 1692 if (i == 255) 1693 printf(", fully associative\n"); 1694 else 1695 printf(", %d-way associative\n", i); 1696 } 1697 1698 static void 1699 print_AMD_l2_assoc(int i) 1700 { 1701 switch (i & 0x0f) { 1702 case 0: printf(", disabled/not present\n"); break; 1703 case 1: printf(", direct mapped\n"); break; 1704 case 2: printf(", 2-way associative\n"); break; 1705 case 4: printf(", 4-way associative\n"); break; 1706 case 6: printf(", 8-way associative\n"); break; 1707 case 8: printf(", 16-way associative\n"); break; 1708 case 15: printf(", fully associative\n"); break; 1709 default: printf(", reserved configuration\n"); break; 1710 } 1711 } 1712 1713 static void 1714 print_AMD_info(void) 1715 { 1716 #ifdef __i386__ 1717 uint64_t amd_whcr; 1718 #endif 1719 u_int regs[4]; 1720 1721 if (cpu_exthigh >= 0x80000005) { 1722 do_cpuid(0x80000005, regs); 1723 printf("L1 2MB data TLB: %d entries", (regs[0] >> 16) & 0xff); 1724 print_AMD_assoc(regs[0] >> 24); 1725 1726 printf("L1 2MB instruction TLB: %d entries", regs[0] & 0xff); 1727 print_AMD_assoc((regs[0] >> 8) & 0xff); 1728 1729 printf("L1 4KB data TLB: %d entries", (regs[1] >> 16) & 0xff); 1730 print_AMD_assoc(regs[1] >> 24); 1731 1732 printf("L1 4KB instruction TLB: %d entries", regs[1] & 0xff); 1733 print_AMD_assoc((regs[1] >> 8) & 0xff); 1734 1735 printf("L1 data cache: %d kbytes", regs[2] >> 24); 1736 printf(", %d bytes/line", regs[2] & 0xff); 1737 printf(", %d lines/tag", (regs[2] >> 8) & 0xff); 1738 print_AMD_assoc((regs[2] >> 16) & 0xff); 1739 1740 printf("L1 instruction cache: %d kbytes", regs[3] >> 24); 1741 printf(", %d bytes/line", regs[3] & 0xff); 1742 printf(", %d lines/tag", (regs[3] >> 8) & 0xff); 1743 print_AMD_assoc((regs[3] >> 16) & 0xff); 1744 } 1745 1746 if (cpu_exthigh >= 0x80000006) { 1747 do_cpuid(0x80000006, regs); 1748 if ((regs[0] >> 16) != 0) { 1749 printf("L2 2MB data TLB: %d entries", 1750 (regs[0] >> 16) & 0xfff); 1751 print_AMD_l2_assoc(regs[0] >> 28); 1752 printf("L2 2MB instruction TLB: %d entries", 1753 regs[0] & 0xfff); 1754 print_AMD_l2_assoc((regs[0] >> 28) & 0xf); 1755 } else { 1756 printf("L2 2MB unified TLB: %d entries", 1757 regs[0] & 0xfff); 1758 print_AMD_l2_assoc((regs[0] >> 28) & 0xf); 1759 } 1760 if ((regs[1] >> 16) != 0) { 1761 printf("L2 4KB data TLB: %d entries", 1762 (regs[1] >> 16) & 0xfff); 1763 print_AMD_l2_assoc(regs[1] >> 28); 1764 1765 printf("L2 4KB instruction TLB: %d entries", 1766 (regs[1] >> 16) & 0xfff); 1767 print_AMD_l2_assoc((regs[1] >> 28) & 0xf); 1768 } else { 1769 printf("L2 4KB unified TLB: %d entries", 1770 (regs[1] >> 16) & 0xfff); 1771 print_AMD_l2_assoc((regs[1] >> 28) & 0xf); 1772 } 1773 printf("L2 unified cache: %d kbytes", regs[2] >> 16); 1774 printf(", %d bytes/line", regs[2] & 0xff); 1775 printf(", %d lines/tag", (regs[2] >> 8) & 0x0f); 1776 print_AMD_l2_assoc((regs[2] >> 12) & 0x0f); 1777 } 1778 1779 #ifdef __i386__ 1780 if (((cpu_id & 0xf00) == 0x500) 1781 && (((cpu_id & 0x0f0) > 0x80) 1782 || (((cpu_id & 0x0f0) == 0x80) 1783 && (cpu_id & 0x00f) > 0x07))) { 1784 /* K6-2(new core [Stepping 8-F]), K6-III or later */ 1785 amd_whcr = rdmsr(0xc0000082); 1786 if (!(amd_whcr & (0x3ff << 22))) { 1787 printf("Write Allocate Disable\n"); 1788 } else { 1789 printf("Write Allocate Enable Limit: %dM bytes\n", 1790 (u_int32_t)((amd_whcr & (0x3ff << 22)) >> 22) * 4); 1791 printf("Write Allocate 15-16M bytes: %s\n", 1792 (amd_whcr & (1 << 16)) ? "Enable" : "Disable"); 1793 } 1794 } else if (((cpu_id & 0xf00) == 0x500) 1795 && ((cpu_id & 0x0f0) > 0x50)) { 1796 /* K6, K6-2(old core) */ 1797 amd_whcr = rdmsr(0xc0000082); 1798 if (!(amd_whcr & (0x7f << 1))) { 1799 printf("Write Allocate Disable\n"); 1800 } else { 1801 printf("Write Allocate Enable Limit: %dM bytes\n", 1802 (u_int32_t)((amd_whcr & (0x7f << 1)) >> 1) * 4); 1803 printf("Write Allocate 15-16M bytes: %s\n", 1804 (amd_whcr & 0x0001) ? "Enable" : "Disable"); 1805 printf("Hardware Write Allocate Control: %s\n", 1806 (amd_whcr & 0x0100) ? "Enable" : "Disable"); 1807 } 1808 } 1809 #endif 1810 /* 1811 * Opteron Rev E shows a bug as in very rare occasions a read memory 1812 * barrier is not performed as expected if it is followed by a 1813 * non-atomic read-modify-write instruction. 1814 * As long as that bug pops up very rarely (intensive machine usage 1815 * on other operating systems generally generates one unexplainable 1816 * crash any 2 months) and as long as a model specific fix would be 1817 * impractical at this stage, print out a warning string if the broken 1818 * model and family are identified. 1819 */ 1820 if (CPUID_TO_FAMILY(cpu_id) == 0xf && CPUID_TO_MODEL(cpu_id) >= 0x20 && 1821 CPUID_TO_MODEL(cpu_id) <= 0x3f) 1822 printf("WARNING: This architecture revision has known SMP " 1823 "hardware bugs which may cause random instability\n"); 1824 } 1825 1826 static void 1827 print_INTEL_info(void) 1828 { 1829 u_int regs[4]; 1830 u_int rounds, regnum; 1831 u_int nwaycode, nway; 1832 1833 if (cpu_high >= 2) { 1834 rounds = 0; 1835 do { 1836 do_cpuid(0x2, regs); 1837 if (rounds == 0 && (rounds = (regs[0] & 0xff)) == 0) 1838 break; /* we have a buggy CPU */ 1839 1840 for (regnum = 0; regnum <= 3; ++regnum) { 1841 if (regs[regnum] & (1<<31)) 1842 continue; 1843 if (regnum != 0) 1844 print_INTEL_TLB(regs[regnum] & 0xff); 1845 print_INTEL_TLB((regs[regnum] >> 8) & 0xff); 1846 print_INTEL_TLB((regs[regnum] >> 16) & 0xff); 1847 print_INTEL_TLB((regs[regnum] >> 24) & 0xff); 1848 } 1849 } while (--rounds > 0); 1850 } 1851 1852 if (cpu_exthigh >= 0x80000006) { 1853 do_cpuid(0x80000006, regs); 1854 nwaycode = (regs[2] >> 12) & 0x0f; 1855 if (nwaycode >= 0x02 && nwaycode <= 0x08) 1856 nway = 1 << (nwaycode / 2); 1857 else 1858 nway = 0; 1859 printf("L2 cache: %u kbytes, %u-way associative, %u bytes/line\n", 1860 (regs[2] >> 16) & 0xffff, nway, regs[2] & 0xff); 1861 } 1862 } 1863 1864 static void 1865 print_INTEL_TLB(u_int data) 1866 { 1867 switch (data) { 1868 case 0x0: 1869 case 0x40: 1870 default: 1871 break; 1872 case 0x1: 1873 printf("Instruction TLB: 4 KB pages, 4-way set associative, 32 entries\n"); 1874 break; 1875 case 0x2: 1876 printf("Instruction TLB: 4 MB pages, fully associative, 2 entries\n"); 1877 break; 1878 case 0x3: 1879 printf("Data TLB: 4 KB pages, 4-way set associative, 64 entries\n"); 1880 break; 1881 case 0x4: 1882 printf("Data TLB: 4 MB Pages, 4-way set associative, 8 entries\n"); 1883 break; 1884 case 0x6: 1885 printf("1st-level instruction cache: 8 KB, 4-way set associative, 32 byte line size\n"); 1886 break; 1887 case 0x8: 1888 printf("1st-level instruction cache: 16 KB, 4-way set associative, 32 byte line size\n"); 1889 break; 1890 case 0x9: 1891 printf("1st-level instruction cache: 32 KB, 4-way set associative, 64 byte line size\n"); 1892 break; 1893 case 0xa: 1894 printf("1st-level data cache: 8 KB, 2-way set associative, 32 byte line size\n"); 1895 break; 1896 case 0xb: 1897 printf("Instruction TLB: 4 MByte pages, 4-way set associative, 4 entries\n"); 1898 break; 1899 case 0xc: 1900 printf("1st-level data cache: 16 KB, 4-way set associative, 32 byte line size\n"); 1901 break; 1902 case 0xd: 1903 printf("1st-level data cache: 16 KBytes, 4-way set associative, 64 byte line size"); 1904 break; 1905 case 0xe: 1906 printf("1st-level data cache: 24 KBytes, 6-way set associative, 64 byte line size\n"); 1907 break; 1908 case 0x1d: 1909 printf("2nd-level cache: 128 KBytes, 2-way set associative, 64 byte line size\n"); 1910 break; 1911 case 0x21: 1912 printf("2nd-level cache: 256 KBytes, 8-way set associative, 64 byte line size\n"); 1913 break; 1914 case 0x22: 1915 printf("3rd-level cache: 512 KB, 4-way set associative, sectored cache, 64 byte line size\n"); 1916 break; 1917 case 0x23: 1918 printf("3rd-level cache: 1 MB, 8-way set associative, sectored cache, 64 byte line size\n"); 1919 break; 1920 case 0x24: 1921 printf("2nd-level cache: 1 MBytes, 16-way set associative, 64 byte line size\n"); 1922 break; 1923 case 0x25: 1924 printf("3rd-level cache: 2 MB, 8-way set associative, sectored cache, 64 byte line size\n"); 1925 break; 1926 case 0x29: 1927 printf("3rd-level cache: 4 MB, 8-way set associative, sectored cache, 64 byte line size\n"); 1928 break; 1929 case 0x2c: 1930 printf("1st-level data cache: 32 KB, 8-way set associative, 64 byte line size\n"); 1931 break; 1932 case 0x30: 1933 printf("1st-level instruction cache: 32 KB, 8-way set associative, 64 byte line size\n"); 1934 break; 1935 case 0x39: /* De-listed in SDM rev. 54 */ 1936 printf("2nd-level cache: 128 KB, 4-way set associative, sectored cache, 64 byte line size\n"); 1937 break; 1938 case 0x3b: /* De-listed in SDM rev. 54 */ 1939 printf("2nd-level cache: 128 KB, 2-way set associative, sectored cache, 64 byte line size\n"); 1940 break; 1941 case 0x3c: /* De-listed in SDM rev. 54 */ 1942 printf("2nd-level cache: 256 KB, 4-way set associative, sectored cache, 64 byte line size\n"); 1943 break; 1944 case 0x41: 1945 printf("2nd-level cache: 128 KB, 4-way set associative, 32 byte line size\n"); 1946 break; 1947 case 0x42: 1948 printf("2nd-level cache: 256 KB, 4-way set associative, 32 byte line size\n"); 1949 break; 1950 case 0x43: 1951 printf("2nd-level cache: 512 KB, 4-way set associative, 32 byte line size\n"); 1952 break; 1953 case 0x44: 1954 printf("2nd-level cache: 1 MB, 4-way set associative, 32 byte line size\n"); 1955 break; 1956 case 0x45: 1957 printf("2nd-level cache: 2 MB, 4-way set associative, 32 byte line size\n"); 1958 break; 1959 case 0x46: 1960 printf("3rd-level cache: 4 MB, 4-way set associative, 64 byte line size\n"); 1961 break; 1962 case 0x47: 1963 printf("3rd-level cache: 8 MB, 8-way set associative, 64 byte line size\n"); 1964 break; 1965 case 0x48: 1966 printf("2nd-level cache: 3MByte, 12-way set associative, 64 byte line size\n"); 1967 break; 1968 case 0x49: 1969 if (CPUID_TO_FAMILY(cpu_id) == 0xf && 1970 CPUID_TO_MODEL(cpu_id) == 0x6) 1971 printf("3rd-level cache: 4MB, 16-way set associative, 64-byte line size\n"); 1972 else 1973 printf("2nd-level cache: 4 MByte, 16-way set associative, 64 byte line size"); 1974 break; 1975 case 0x4a: 1976 printf("3rd-level cache: 6MByte, 12-way set associative, 64 byte line size\n"); 1977 break; 1978 case 0x4b: 1979 printf("3rd-level cache: 8MByte, 16-way set associative, 64 byte line size\n"); 1980 break; 1981 case 0x4c: 1982 printf("3rd-level cache: 12MByte, 12-way set associative, 64 byte line size\n"); 1983 break; 1984 case 0x4d: 1985 printf("3rd-level cache: 16MByte, 16-way set associative, 64 byte line size\n"); 1986 break; 1987 case 0x4e: 1988 printf("2nd-level cache: 6MByte, 24-way set associative, 64 byte line size\n"); 1989 break; 1990 case 0x4f: 1991 printf("Instruction TLB: 4 KByte pages, 32 entries\n"); 1992 break; 1993 case 0x50: 1994 printf("Instruction TLB: 4 KB, 2 MB or 4 MB pages, fully associative, 64 entries\n"); 1995 break; 1996 case 0x51: 1997 printf("Instruction TLB: 4 KB, 2 MB or 4 MB pages, fully associative, 128 entries\n"); 1998 break; 1999 case 0x52: 2000 printf("Instruction TLB: 4 KB, 2 MB or 4 MB pages, fully associative, 256 entries\n"); 2001 break; 2002 case 0x55: 2003 printf("Instruction TLB: 2-MByte or 4-MByte pages, fully associative, 7 entries\n"); 2004 break; 2005 case 0x56: 2006 printf("Data TLB0: 4 MByte pages, 4-way set associative, 16 entries\n"); 2007 break; 2008 case 0x57: 2009 printf("Data TLB0: 4 KByte pages, 4-way associative, 16 entries\n"); 2010 break; 2011 case 0x59: 2012 printf("Data TLB0: 4 KByte pages, fully associative, 16 entries\n"); 2013 break; 2014 case 0x5a: 2015 printf("Data TLB0: 2-MByte or 4 MByte pages, 4-way set associative, 32 entries\n"); 2016 break; 2017 case 0x5b: 2018 printf("Data TLB: 4 KB or 4 MB pages, fully associative, 64 entries\n"); 2019 break; 2020 case 0x5c: 2021 printf("Data TLB: 4 KB or 4 MB pages, fully associative, 128 entries\n"); 2022 break; 2023 case 0x5d: 2024 printf("Data TLB: 4 KB or 4 MB pages, fully associative, 256 entries\n"); 2025 break; 2026 case 0x60: 2027 printf("1st-level data cache: 16 KB, 8-way set associative, sectored cache, 64 byte line size\n"); 2028 break; 2029 case 0x61: 2030 printf("Instruction TLB: 4 KByte pages, fully associative, 48 entries\n"); 2031 break; 2032 case 0x63: 2033 printf("Data TLB: 2 MByte or 4 MByte pages, 4-way set associative, 32 entries and a separate array with 1 GByte pages, 4-way set associative, 4 entries\n"); 2034 break; 2035 case 0x64: 2036 printf("Data TLB: 4 KBytes pages, 4-way set associative, 512 entries\n"); 2037 break; 2038 case 0x66: 2039 printf("1st-level data cache: 8 KB, 4-way set associative, sectored cache, 64 byte line size\n"); 2040 break; 2041 case 0x67: 2042 printf("1st-level data cache: 16 KB, 4-way set associative, sectored cache, 64 byte line size\n"); 2043 break; 2044 case 0x68: 2045 printf("1st-level data cache: 32 KB, 4 way set associative, sectored cache, 64 byte line size\n"); 2046 break; 2047 case 0x6a: 2048 printf("uTLB: 4KByte pages, 8-way set associative, 64 entries\n"); 2049 break; 2050 case 0x6b: 2051 printf("DTLB: 4KByte pages, 8-way set associative, 256 entries\n"); 2052 break; 2053 case 0x6c: 2054 printf("DTLB: 2M/4M pages, 8-way set associative, 128 entries\n"); 2055 break; 2056 case 0x6d: 2057 printf("DTLB: 1 GByte pages, fully associative, 16 entries\n"); 2058 break; 2059 case 0x70: 2060 printf("Trace cache: 12K-uops, 8-way set associative\n"); 2061 break; 2062 case 0x71: 2063 printf("Trace cache: 16K-uops, 8-way set associative\n"); 2064 break; 2065 case 0x72: 2066 printf("Trace cache: 32K-uops, 8-way set associative\n"); 2067 break; 2068 case 0x76: 2069 printf("Instruction TLB: 2M/4M pages, fully associative, 8 entries\n"); 2070 break; 2071 case 0x78: 2072 printf("2nd-level cache: 1 MB, 4-way set associative, 64-byte line size\n"); 2073 break; 2074 case 0x79: 2075 printf("2nd-level cache: 128 KB, 8-way set associative, sectored cache, 64 byte line size\n"); 2076 break; 2077 case 0x7a: 2078 printf("2nd-level cache: 256 KB, 8-way set associative, sectored cache, 64 byte line size\n"); 2079 break; 2080 case 0x7b: 2081 printf("2nd-level cache: 512 KB, 8-way set associative, sectored cache, 64 byte line size\n"); 2082 break; 2083 case 0x7c: 2084 printf("2nd-level cache: 1 MB, 8-way set associative, sectored cache, 64 byte line size\n"); 2085 break; 2086 case 0x7d: 2087 printf("2nd-level cache: 2-MB, 8-way set associative, 64-byte line size\n"); 2088 break; 2089 case 0x7f: 2090 printf("2nd-level cache: 512-KB, 2-way set associative, 64-byte line size\n"); 2091 break; 2092 case 0x80: 2093 printf("2nd-level cache: 512 KByte, 8-way set associative, 64-byte line size\n"); 2094 break; 2095 case 0x82: 2096 printf("2nd-level cache: 256 KB, 8-way set associative, 32 byte line size\n"); 2097 break; 2098 case 0x83: 2099 printf("2nd-level cache: 512 KB, 8-way set associative, 32 byte line size\n"); 2100 break; 2101 case 0x84: 2102 printf("2nd-level cache: 1 MB, 8-way set associative, 32 byte line size\n"); 2103 break; 2104 case 0x85: 2105 printf("2nd-level cache: 2 MB, 8-way set associative, 32 byte line size\n"); 2106 break; 2107 case 0x86: 2108 printf("2nd-level cache: 512 KB, 4-way set associative, 64 byte line size\n"); 2109 break; 2110 case 0x87: 2111 printf("2nd-level cache: 1 MB, 8-way set associative, 64 byte line size\n"); 2112 break; 2113 case 0xa0: 2114 printf("DTLB: 4k pages, fully associative, 32 entries\n"); 2115 break; 2116 case 0xb0: 2117 printf("Instruction TLB: 4 KB Pages, 4-way set associative, 128 entries\n"); 2118 break; 2119 case 0xb1: 2120 printf("Instruction TLB: 2M pages, 4-way, 8 entries or 4M pages, 4-way, 4 entries\n"); 2121 break; 2122 case 0xb2: 2123 printf("Instruction TLB: 4KByte pages, 4-way set associative, 64 entries\n"); 2124 break; 2125 case 0xb3: 2126 printf("Data TLB: 4 KB Pages, 4-way set associative, 128 entries\n"); 2127 break; 2128 case 0xb4: 2129 printf("Data TLB1: 4 KByte pages, 4-way associative, 256 entries\n"); 2130 break; 2131 case 0xb5: 2132 printf("Instruction TLB: 4KByte pages, 8-way set associative, 64 entries\n"); 2133 break; 2134 case 0xb6: 2135 printf("Instruction TLB: 4KByte pages, 8-way set associative, 128 entries\n"); 2136 break; 2137 case 0xba: 2138 printf("Data TLB1: 4 KByte pages, 4-way associative, 64 entries\n"); 2139 break; 2140 case 0xc0: 2141 printf("Data TLB: 4 KByte and 4 MByte pages, 4-way associative, 8 entries\n"); 2142 break; 2143 case 0xc1: 2144 printf("Shared 2nd-Level TLB: 4 KByte/2MByte pages, 8-way associative, 1024 entries\n"); 2145 break; 2146 case 0xc2: 2147 printf("DTLB: 4 KByte/2 MByte pages, 4-way associative, 16 entries\n"); 2148 break; 2149 case 0xc3: 2150 printf("Shared 2nd-Level TLB: 4 KByte /2 MByte pages, 6-way associative, 1536 entries. Also 1GBbyte pages, 4-way, 16 entries\n"); 2151 break; 2152 case 0xc4: 2153 printf("DTLB: 2M/4M Byte pages, 4-way associative, 32 entries\n"); 2154 break; 2155 case 0xca: 2156 printf("Shared 2nd-Level TLB: 4 KByte pages, 4-way associative, 512 entries\n"); 2157 break; 2158 case 0xd0: 2159 printf("3rd-level cache: 512 KByte, 4-way set associative, 64 byte line size\n"); 2160 break; 2161 case 0xd1: 2162 printf("3rd-level cache: 1 MByte, 4-way set associative, 64 byte line size\n"); 2163 break; 2164 case 0xd2: 2165 printf("3rd-level cache: 2 MByte, 4-way set associative, 64 byte line size\n"); 2166 break; 2167 case 0xd6: 2168 printf("3rd-level cache: 1 MByte, 8-way set associative, 64 byte line size\n"); 2169 break; 2170 case 0xd7: 2171 printf("3rd-level cache: 2 MByte, 8-way set associative, 64 byte line size\n"); 2172 break; 2173 case 0xd8: 2174 printf("3rd-level cache: 4 MByte, 8-way set associative, 64 byte line size\n"); 2175 break; 2176 case 0xdc: 2177 printf("3rd-level cache: 1.5 MByte, 12-way set associative, 64 byte line size\n"); 2178 break; 2179 case 0xdd: 2180 printf("3rd-level cache: 3 MByte, 12-way set associative, 64 byte line size\n"); 2181 break; 2182 case 0xde: 2183 printf("3rd-level cache: 6 MByte, 12-way set associative, 64 byte line size\n"); 2184 break; 2185 case 0xe2: 2186 printf("3rd-level cache: 2 MByte, 16-way set associative, 64 byte line size\n"); 2187 break; 2188 case 0xe3: 2189 printf("3rd-level cache: 4 MByte, 16-way set associative, 64 byte line size\n"); 2190 break; 2191 case 0xe4: 2192 printf("3rd-level cache: 8 MByte, 16-way set associative, 64 byte line size\n"); 2193 break; 2194 case 0xea: 2195 printf("3rd-level cache: 12MByte, 24-way set associative, 64 byte line size\n"); 2196 break; 2197 case 0xeb: 2198 printf("3rd-level cache: 18MByte, 24-way set associative, 64 byte line size\n"); 2199 break; 2200 case 0xec: 2201 printf("3rd-level cache: 24MByte, 24-way set associative, 64 byte line size\n"); 2202 break; 2203 case 0xf0: 2204 printf("64-Byte prefetching\n"); 2205 break; 2206 case 0xf1: 2207 printf("128-Byte prefetching\n"); 2208 break; 2209 } 2210 } 2211 2212 static void 2213 print_svm_info(void) 2214 { 2215 u_int features, regs[4]; 2216 uint64_t msr; 2217 int comma; 2218 2219 printf("\n SVM: "); 2220 do_cpuid(0x8000000A, regs); 2221 features = regs[3]; 2222 2223 msr = rdmsr(MSR_VM_CR); 2224 if ((msr & VM_CR_SVMDIS) == VM_CR_SVMDIS) 2225 printf("(disabled in BIOS) "); 2226 2227 if (!bootverbose) { 2228 comma = 0; 2229 if (features & (1 << 0)) { 2230 printf("%sNP", comma ? "," : ""); 2231 comma = 1; 2232 } 2233 if (features & (1 << 3)) { 2234 printf("%sNRIP", comma ? "," : ""); 2235 comma = 1; 2236 } 2237 if (features & (1 << 5)) { 2238 printf("%sVClean", comma ? "," : ""); 2239 comma = 1; 2240 } 2241 if (features & (1 << 6)) { 2242 printf("%sAFlush", comma ? "," : ""); 2243 comma = 1; 2244 } 2245 if (features & (1 << 7)) { 2246 printf("%sDAssist", comma ? "," : ""); 2247 comma = 1; 2248 } 2249 printf("%sNAsids=%d", comma ? "," : "", regs[1]); 2250 return; 2251 } 2252 2253 printf("Features=0x%b", features, 2254 "\020" 2255 "\001NP" /* Nested paging */ 2256 "\002LbrVirt" /* LBR virtualization */ 2257 "\003SVML" /* SVM lock */ 2258 "\004NRIPS" /* NRIP save */ 2259 "\005TscRateMsr" /* MSR based TSC rate control */ 2260 "\006VmcbClean" /* VMCB clean bits */ 2261 "\007FlushByAsid" /* Flush by ASID */ 2262 "\010DecodeAssist" /* Decode assist */ 2263 "\011<b8>" 2264 "\012<b9>" 2265 "\013PauseFilter" /* PAUSE intercept filter */ 2266 "\014EncryptedMcodePatch" 2267 "\015PauseFilterThreshold" /* PAUSE filter threshold */ 2268 "\016AVIC" /* virtual interrupt controller */ 2269 "\017<b14>" 2270 "\020V_VMSAVE_VMLOAD" 2271 "\021vGIF" 2272 "\022<b17>" 2273 "\023<b18>" 2274 "\024<b19>" 2275 "\025<b20>" 2276 "\026<b21>" 2277 "\027<b22>" 2278 "\030<b23>" 2279 "\031<b24>" 2280 "\032<b25>" 2281 "\033<b26>" 2282 "\034<b27>" 2283 "\035<b28>" 2284 "\036<b29>" 2285 "\037<b30>" 2286 "\040<b31>" 2287 ); 2288 printf("\nRevision=%d, ASIDs=%d", regs[0] & 0xff, regs[1]); 2289 } 2290 2291 #ifdef __i386__ 2292 static void 2293 print_transmeta_info(void) 2294 { 2295 u_int regs[4], nreg = 0; 2296 2297 do_cpuid(0x80860000, regs); 2298 nreg = regs[0]; 2299 if (nreg >= 0x80860001) { 2300 do_cpuid(0x80860001, regs); 2301 printf(" Processor revision %u.%u.%u.%u\n", 2302 (regs[1] >> 24) & 0xff, 2303 (regs[1] >> 16) & 0xff, 2304 (regs[1] >> 8) & 0xff, 2305 regs[1] & 0xff); 2306 } 2307 if (nreg >= 0x80860002) { 2308 do_cpuid(0x80860002, regs); 2309 printf(" Code Morphing Software revision %u.%u.%u-%u-%u\n", 2310 (regs[1] >> 24) & 0xff, 2311 (regs[1] >> 16) & 0xff, 2312 (regs[1] >> 8) & 0xff, 2313 regs[1] & 0xff, 2314 regs[2]); 2315 } 2316 if (nreg >= 0x80860006) { 2317 char info[65]; 2318 do_cpuid(0x80860003, (u_int*) &info[0]); 2319 do_cpuid(0x80860004, (u_int*) &info[16]); 2320 do_cpuid(0x80860005, (u_int*) &info[32]); 2321 do_cpuid(0x80860006, (u_int*) &info[48]); 2322 info[64] = 0; 2323 printf(" %s\n", info); 2324 } 2325 } 2326 #endif 2327 2328 static void 2329 print_via_padlock_info(void) 2330 { 2331 u_int regs[4]; 2332 2333 do_cpuid(0xc0000001, regs); 2334 printf("\n VIA Padlock Features=0x%b", regs[3], 2335 "\020" 2336 "\003RNG" /* RNG */ 2337 "\007AES" /* ACE */ 2338 "\011AES-CTR" /* ACE2 */ 2339 "\013SHA1,SHA256" /* PHE */ 2340 "\015RSA" /* PMM */ 2341 ); 2342 } 2343 2344 static uint32_t 2345 vmx_settable(uint64_t basic, int msr, int true_msr) 2346 { 2347 uint64_t val; 2348 2349 if (basic & (1ULL << 55)) 2350 val = rdmsr(true_msr); 2351 else 2352 val = rdmsr(msr); 2353 2354 /* Just report the controls that can be set to 1. */ 2355 return (val >> 32); 2356 } 2357 2358 static void 2359 print_vmx_info(void) 2360 { 2361 uint64_t basic, msr; 2362 uint32_t entry, exit, mask, pin, proc, proc2; 2363 int comma; 2364 2365 printf("\n VT-x: "); 2366 msr = rdmsr(MSR_IA32_FEATURE_CONTROL); 2367 if (!(msr & IA32_FEATURE_CONTROL_VMX_EN)) 2368 printf("(disabled in BIOS) "); 2369 basic = rdmsr(MSR_VMX_BASIC); 2370 pin = vmx_settable(basic, MSR_VMX_PINBASED_CTLS, 2371 MSR_VMX_TRUE_PINBASED_CTLS); 2372 proc = vmx_settable(basic, MSR_VMX_PROCBASED_CTLS, 2373 MSR_VMX_TRUE_PROCBASED_CTLS); 2374 if (proc & PROCBASED_SECONDARY_CONTROLS) 2375 proc2 = vmx_settable(basic, MSR_VMX_PROCBASED_CTLS2, 2376 MSR_VMX_PROCBASED_CTLS2); 2377 else 2378 proc2 = 0; 2379 exit = vmx_settable(basic, MSR_VMX_EXIT_CTLS, MSR_VMX_TRUE_EXIT_CTLS); 2380 entry = vmx_settable(basic, MSR_VMX_ENTRY_CTLS, MSR_VMX_TRUE_ENTRY_CTLS); 2381 2382 if (!bootverbose) { 2383 comma = 0; 2384 if (exit & VM_EXIT_SAVE_PAT && exit & VM_EXIT_LOAD_PAT && 2385 entry & VM_ENTRY_LOAD_PAT) { 2386 printf("%sPAT", comma ? "," : ""); 2387 comma = 1; 2388 } 2389 if (proc & PROCBASED_HLT_EXITING) { 2390 printf("%sHLT", comma ? "," : ""); 2391 comma = 1; 2392 } 2393 if (proc & PROCBASED_MTF) { 2394 printf("%sMTF", comma ? "," : ""); 2395 comma = 1; 2396 } 2397 if (proc & PROCBASED_PAUSE_EXITING) { 2398 printf("%sPAUSE", comma ? "," : ""); 2399 comma = 1; 2400 } 2401 if (proc2 & PROCBASED2_ENABLE_EPT) { 2402 printf("%sEPT", comma ? "," : ""); 2403 comma = 1; 2404 } 2405 if (proc2 & PROCBASED2_UNRESTRICTED_GUEST) { 2406 printf("%sUG", comma ? "," : ""); 2407 comma = 1; 2408 } 2409 if (proc2 & PROCBASED2_ENABLE_VPID) { 2410 printf("%sVPID", comma ? "," : ""); 2411 comma = 1; 2412 } 2413 if (proc & PROCBASED_USE_TPR_SHADOW && 2414 proc2 & PROCBASED2_VIRTUALIZE_APIC_ACCESSES && 2415 proc2 & PROCBASED2_VIRTUALIZE_X2APIC_MODE && 2416 proc2 & PROCBASED2_APIC_REGISTER_VIRTUALIZATION && 2417 proc2 & PROCBASED2_VIRTUAL_INTERRUPT_DELIVERY) { 2418 printf("%sVID", comma ? "," : ""); 2419 comma = 1; 2420 if (pin & PINBASED_POSTED_INTERRUPT) 2421 printf(",PostIntr"); 2422 } 2423 return; 2424 } 2425 2426 mask = basic >> 32; 2427 printf("Basic Features=0x%b", mask, 2428 "\020" 2429 "\02132PA" /* 32-bit physical addresses */ 2430 "\022SMM" /* SMM dual-monitor */ 2431 "\027INS/OUTS" /* VM-exit info for INS and OUTS */ 2432 "\030TRUE" /* TRUE_CTLS MSRs */ 2433 ); 2434 printf("\n Pin-Based Controls=0x%b", pin, 2435 "\020" 2436 "\001ExtINT" /* External-interrupt exiting */ 2437 "\004NMI" /* NMI exiting */ 2438 "\006VNMI" /* Virtual NMIs */ 2439 "\007PreTmr" /* Activate VMX-preemption timer */ 2440 "\010PostIntr" /* Process posted interrupts */ 2441 ); 2442 printf("\n Primary Processor Controls=0x%b", proc, 2443 "\020" 2444 "\003INTWIN" /* Interrupt-window exiting */ 2445 "\004TSCOff" /* Use TSC offsetting */ 2446 "\010HLT" /* HLT exiting */ 2447 "\012INVLPG" /* INVLPG exiting */ 2448 "\013MWAIT" /* MWAIT exiting */ 2449 "\014RDPMC" /* RDPMC exiting */ 2450 "\015RDTSC" /* RDTSC exiting */ 2451 "\020CR3-LD" /* CR3-load exiting */ 2452 "\021CR3-ST" /* CR3-store exiting */ 2453 "\024CR8-LD" /* CR8-load exiting */ 2454 "\025CR8-ST" /* CR8-store exiting */ 2455 "\026TPR" /* Use TPR shadow */ 2456 "\027NMIWIN" /* NMI-window exiting */ 2457 "\030MOV-DR" /* MOV-DR exiting */ 2458 "\031IO" /* Unconditional I/O exiting */ 2459 "\032IOmap" /* Use I/O bitmaps */ 2460 "\034MTF" /* Monitor trap flag */ 2461 "\035MSRmap" /* Use MSR bitmaps */ 2462 "\036MONITOR" /* MONITOR exiting */ 2463 "\037PAUSE" /* PAUSE exiting */ 2464 ); 2465 if (proc & PROCBASED_SECONDARY_CONTROLS) 2466 printf("\n Secondary Processor Controls=0x%b", proc2, 2467 "\020" 2468 "\001APIC" /* Virtualize APIC accesses */ 2469 "\002EPT" /* Enable EPT */ 2470 "\003DT" /* Descriptor-table exiting */ 2471 "\004RDTSCP" /* Enable RDTSCP */ 2472 "\005x2APIC" /* Virtualize x2APIC mode */ 2473 "\006VPID" /* Enable VPID */ 2474 "\007WBINVD" /* WBINVD exiting */ 2475 "\010UG" /* Unrestricted guest */ 2476 "\011APIC-reg" /* APIC-register virtualization */ 2477 "\012VID" /* Virtual-interrupt delivery */ 2478 "\013PAUSE-loop" /* PAUSE-loop exiting */ 2479 "\014RDRAND" /* RDRAND exiting */ 2480 "\015INVPCID" /* Enable INVPCID */ 2481 "\016VMFUNC" /* Enable VM functions */ 2482 "\017VMCS" /* VMCS shadowing */ 2483 "\020EPT#VE" /* EPT-violation #VE */ 2484 "\021XSAVES" /* Enable XSAVES/XRSTORS */ 2485 ); 2486 printf("\n Exit Controls=0x%b", mask, 2487 "\020" 2488 "\003DR" /* Save debug controls */ 2489 /* Ignore Host address-space size */ 2490 "\015PERF" /* Load MSR_PERF_GLOBAL_CTRL */ 2491 "\020AckInt" /* Acknowledge interrupt on exit */ 2492 "\023PAT-SV" /* Save MSR_PAT */ 2493 "\024PAT-LD" /* Load MSR_PAT */ 2494 "\025EFER-SV" /* Save MSR_EFER */ 2495 "\026EFER-LD" /* Load MSR_EFER */ 2496 "\027PTMR-SV" /* Save VMX-preemption timer value */ 2497 ); 2498 printf("\n Entry Controls=0x%b", mask, 2499 "\020" 2500 "\003DR" /* Save debug controls */ 2501 /* Ignore IA-32e mode guest */ 2502 /* Ignore Entry to SMM */ 2503 /* Ignore Deactivate dual-monitor treatment */ 2504 "\016PERF" /* Load MSR_PERF_GLOBAL_CTRL */ 2505 "\017PAT" /* Load MSR_PAT */ 2506 "\020EFER" /* Load MSR_EFER */ 2507 ); 2508 if (proc & PROCBASED_SECONDARY_CONTROLS && 2509 (proc2 & (PROCBASED2_ENABLE_EPT | PROCBASED2_ENABLE_VPID)) != 0) { 2510 msr = rdmsr(MSR_VMX_EPT_VPID_CAP); 2511 mask = msr; 2512 printf("\n EPT Features=0x%b", mask, 2513 "\020" 2514 "\001XO" /* Execute-only translations */ 2515 "\007PW4" /* Page-walk length of 4 */ 2516 "\011UC" /* EPT paging-structure mem can be UC */ 2517 "\017WB" /* EPT paging-structure mem can be WB */ 2518 "\0212M" /* EPT PDE can map a 2-Mbyte page */ 2519 "\0221G" /* EPT PDPTE can map a 1-Gbyte page */ 2520 "\025INVEPT" /* INVEPT is supported */ 2521 "\026AD" /* Accessed and dirty flags for EPT */ 2522 "\032single" /* INVEPT single-context type */ 2523 "\033all" /* INVEPT all-context type */ 2524 ); 2525 mask = msr >> 32; 2526 printf("\n VPID Features=0x%b", mask, 2527 "\020" 2528 "\001INVVPID" /* INVVPID is supported */ 2529 "\011individual" /* INVVPID individual-address type */ 2530 "\012single" /* INVVPID single-context type */ 2531 "\013all" /* INVVPID all-context type */ 2532 /* INVVPID single-context-retaining-globals type */ 2533 "\014single-globals" 2534 ); 2535 } 2536 } 2537 2538 static void 2539 print_hypervisor_info(void) 2540 { 2541 2542 if (*hv_vendor) 2543 printf("Hypervisor: Origin = \"%s\"\n", hv_vendor); 2544 } 2545 2546 /* 2547 * Returns the maximum physical address that can be used with the 2548 * current system. 2549 */ 2550 vm_paddr_t 2551 cpu_getmaxphyaddr(void) 2552 { 2553 2554 #if defined(__i386__) 2555 if (!pae_mode) 2556 return (0xffffffff); 2557 #endif 2558 return ((1ULL << cpu_maxphyaddr) - 1); 2559 } 2560