1 /*- 2 * Copyright (c) 1992 Terrence R. Lambert. 3 * Copyright (c) 1982, 1987, 1990 The Regents of the University of California. 4 * Copyright (c) 1997 KATO Takenori. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to Berkeley by 8 * William Jolitz. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by the University of 21 * California, Berkeley and its contributors. 22 * 4. Neither the name of the University nor the names of its contributors 23 * may be used to endorse or promote products derived from this software 24 * without specific prior written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 27 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 28 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 29 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 30 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 31 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 32 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 33 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 34 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 35 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 36 * SUCH DAMAGE. 37 * 38 * from: Id: machdep.c,v 1.193 1996/06/18 01:22:04 bde Exp 39 */ 40 41 #include <sys/cdefs.h> 42 #include "opt_cpu.h" 43 44 #include <sys/param.h> 45 #include <sys/bus.h> 46 #include <sys/cpu.h> 47 #include <sys/eventhandler.h> 48 #include <sys/limits.h> 49 #include <sys/systm.h> 50 #include <sys/kernel.h> 51 #include <sys/sysctl.h> 52 #include <sys/power.h> 53 54 #include <vm/vm.h> 55 #include <vm/pmap.h> 56 57 #include <machine/asmacros.h> 58 #include <machine/clock.h> 59 #include <machine/cputypes.h> 60 #include <machine/frame.h> 61 #include <machine/intr_machdep.h> 62 #include <machine/md_var.h> 63 #include <machine/segments.h> 64 #include <machine/specialreg.h> 65 66 #include <amd64/vmm/intel/vmx_controls.h> 67 #include <x86/isa/icu.h> 68 #include <x86/vmware.h> 69 70 #ifdef XENHVM 71 #include <xen/xen-os.h> 72 #endif 73 74 #ifdef __i386__ 75 #define IDENTBLUE_CYRIX486 0 76 #define IDENTBLUE_IBMCPU 1 77 #define IDENTBLUE_CYRIXM2 2 78 79 static void identifycyrix(void); 80 static void print_transmeta_info(void); 81 #endif 82 static u_int find_cpu_vendor_id(void); 83 static void print_AMD_info(void); 84 static void print_INTEL_info(void); 85 static void print_INTEL_TLB(u_int data); 86 static void print_hypervisor_info(void); 87 static void print_svm_info(void); 88 static void print_via_padlock_info(void); 89 static void print_vmx_info(void); 90 91 #ifdef __i386__ 92 int cpu; /* Are we 386, 386sx, 486, etc? */ 93 int cpu_class; 94 #endif 95 u_int cpu_feature; /* Feature flags */ 96 u_int cpu_feature2; /* Feature flags */ 97 u_int amd_feature; /* AMD feature flags */ 98 u_int amd_feature2; /* AMD feature flags */ 99 u_int amd_rascap; /* AMD RAS capabilities */ 100 u_int amd_pminfo; /* AMD advanced power management info */ 101 u_int amd_extended_feature_extensions; 102 u_int via_feature_rng; /* VIA RNG features */ 103 u_int via_feature_xcrypt; /* VIA ACE features */ 104 u_int cpu_high; /* Highest arg to CPUID */ 105 u_int cpu_exthigh; /* Highest arg to extended CPUID */ 106 u_int cpu_id; /* Stepping ID */ 107 u_int cpu_procinfo; /* HyperThreading Info / Brand Index / CLFUSH */ 108 u_int cpu_procinfo2; /* Multicore info */ 109 char cpu_vendor[20]; /* CPU Origin code */ 110 u_int cpu_vendor_id; /* CPU vendor ID */ 111 u_int cpu_mxcsr_mask; /* Valid bits in mxcsr */ 112 u_int cpu_clflush_line_size = 32; 113 u_int cpu_stdext_feature; /* %ebx */ 114 u_int cpu_stdext_feature2; /* %ecx */ 115 u_int cpu_stdext_feature3; /* %edx */ 116 uint64_t cpu_ia32_arch_caps; 117 u_int cpu_max_ext_state_size; 118 u_int cpu_mon_mwait_flags; /* MONITOR/MWAIT flags (CPUID.05H.ECX) */ 119 u_int cpu_mon_min_size; /* MONITOR minimum range size, bytes */ 120 u_int cpu_mon_max_size; /* MONITOR minimum range size, bytes */ 121 u_int cpu_maxphyaddr; /* Max phys addr width in bits */ 122 u_int cpu_power_eax; /* 06H: Power management leaf, %eax */ 123 u_int cpu_power_ebx; /* 06H: Power management leaf, %ebx */ 124 u_int cpu_power_ecx; /* 06H: Power management leaf, %ecx */ 125 u_int cpu_power_edx; /* 06H: Power management leaf, %edx */ 126 char machine[] = MACHINE; 127 128 SYSCTL_UINT(_hw, OID_AUTO, via_feature_rng, CTLFLAG_RD, 129 &via_feature_rng, 0, 130 "VIA RNG feature available in CPU"); 131 SYSCTL_UINT(_hw, OID_AUTO, via_feature_xcrypt, CTLFLAG_RD, 132 &via_feature_xcrypt, 0, 133 "VIA xcrypt feature available in CPU"); 134 135 #ifdef __amd64__ 136 #ifdef SCTL_MASK32 137 extern int adaptive_machine_arch; 138 #endif 139 140 static int 141 sysctl_hw_machine(SYSCTL_HANDLER_ARGS) 142 { 143 #ifdef SCTL_MASK32 144 static const char machine32[] = "i386"; 145 #endif 146 int error; 147 148 #ifdef SCTL_MASK32 149 if ((req->flags & SCTL_MASK32) != 0 && adaptive_machine_arch) 150 error = SYSCTL_OUT(req, machine32, sizeof(machine32)); 151 else 152 #endif 153 error = SYSCTL_OUT(req, machine, sizeof(machine)); 154 return (error); 155 156 } 157 SYSCTL_PROC(_hw, HW_MACHINE, machine, CTLTYPE_STRING | CTLFLAG_RD | 158 CTLFLAG_CAPRD | CTLFLAG_MPSAFE, NULL, 0, sysctl_hw_machine, "A", "Machine class"); 159 #else 160 SYSCTL_STRING(_hw, HW_MACHINE, machine, CTLFLAG_RD | CTLFLAG_CAPRD, 161 machine, 0, "Machine class"); 162 #endif 163 164 char cpu_model[128]; 165 SYSCTL_STRING(_hw, HW_MODEL, model, CTLFLAG_RD | CTLFLAG_CAPRD, 166 cpu_model, 0, "Machine model"); 167 168 static int hw_clockrate; 169 SYSCTL_INT(_hw, OID_AUTO, clockrate, CTLFLAG_RD, 170 &hw_clockrate, 0, "CPU instruction clock rate"); 171 172 u_int hv_base; 173 u_int hv_high; 174 char hv_vendor[16]; 175 SYSCTL_STRING(_hw, OID_AUTO, hv_vendor, CTLFLAG_RD, hv_vendor, 176 0, "Hypervisor vendor"); 177 178 static eventhandler_tag tsc_post_tag; 179 180 static char cpu_brand[48]; 181 182 #ifdef __i386__ 183 #define MAX_BRAND_INDEX 8 184 185 static const char *cpu_brandtable[MAX_BRAND_INDEX + 1] = { 186 NULL, /* No brand */ 187 "Intel Celeron", 188 "Intel Pentium III", 189 "Intel Pentium III Xeon", 190 NULL, 191 NULL, 192 NULL, 193 NULL, 194 "Intel Pentium 4" 195 }; 196 197 static struct { 198 char *cpu_name; 199 int cpu_class; 200 } cpus[] = { 201 { "Intel 80286", CPUCLASS_286 }, /* CPU_286 */ 202 { "i386SX", CPUCLASS_386 }, /* CPU_386SX */ 203 { "i386DX", CPUCLASS_386 }, /* CPU_386 */ 204 { "i486SX", CPUCLASS_486 }, /* CPU_486SX */ 205 { "i486DX", CPUCLASS_486 }, /* CPU_486 */ 206 { "Pentium", CPUCLASS_586 }, /* CPU_586 */ 207 { "Cyrix 486", CPUCLASS_486 }, /* CPU_486DLC */ 208 { "Pentium Pro", CPUCLASS_686 }, /* CPU_686 */ 209 { "Cyrix 5x86", CPUCLASS_486 }, /* CPU_M1SC */ 210 { "Cyrix 6x86", CPUCLASS_486 }, /* CPU_M1 */ 211 { "Blue Lightning", CPUCLASS_486 }, /* CPU_BLUE */ 212 { "Cyrix 6x86MX", CPUCLASS_686 }, /* CPU_M2 */ 213 { "NexGen 586", CPUCLASS_386 }, /* CPU_NX586 (XXX) */ 214 { "Cyrix 486S/DX", CPUCLASS_486 }, /* CPU_CY486DX */ 215 { "Pentium II", CPUCLASS_686 }, /* CPU_PII */ 216 { "Pentium III", CPUCLASS_686 }, /* CPU_PIII */ 217 { "Pentium 4", CPUCLASS_686 }, /* CPU_P4 */ 218 }; 219 #endif 220 221 static struct { 222 char *vendor; 223 u_int vendor_id; 224 } cpu_vendors[] = { 225 { INTEL_VENDOR_ID, CPU_VENDOR_INTEL }, /* GenuineIntel */ 226 { AMD_VENDOR_ID, CPU_VENDOR_AMD }, /* AuthenticAMD */ 227 { HYGON_VENDOR_ID, CPU_VENDOR_HYGON }, /* HygonGenuine */ 228 { CENTAUR_VENDOR_ID, CPU_VENDOR_CENTAUR }, /* CentaurHauls */ 229 #ifdef __i386__ 230 { NSC_VENDOR_ID, CPU_VENDOR_NSC }, /* Geode by NSC */ 231 { CYRIX_VENDOR_ID, CPU_VENDOR_CYRIX }, /* CyrixInstead */ 232 { TRANSMETA_VENDOR_ID, CPU_VENDOR_TRANSMETA }, /* GenuineTMx86 */ 233 { SIS_VENDOR_ID, CPU_VENDOR_SIS }, /* SiS SiS SiS */ 234 { UMC_VENDOR_ID, CPU_VENDOR_UMC }, /* UMC UMC UMC */ 235 { NEXGEN_VENDOR_ID, CPU_VENDOR_NEXGEN }, /* NexGenDriven */ 236 { RISE_VENDOR_ID, CPU_VENDOR_RISE }, /* RiseRiseRise */ 237 #if 0 238 /* XXX CPUID 8000_0000h and 8086_0000h, not 0000_0000h */ 239 { "TransmetaCPU", CPU_VENDOR_TRANSMETA }, 240 #endif 241 #endif 242 }; 243 244 void 245 printcpuinfo(void) 246 { 247 u_int regs[4], i; 248 char *brand; 249 250 printf("CPU: "); 251 #ifdef __i386__ 252 cpu_class = cpus[cpu].cpu_class; 253 strncpy(cpu_model, cpus[cpu].cpu_name, sizeof (cpu_model)); 254 #else 255 strncpy(cpu_model, "Hammer", sizeof (cpu_model)); 256 #endif 257 258 /* Check for extended CPUID information and a processor name. */ 259 if (cpu_exthigh >= 0x80000004) { 260 brand = cpu_brand; 261 for (i = 0x80000002; i < 0x80000005; i++) { 262 do_cpuid(i, regs); 263 memcpy(brand, regs, sizeof(regs)); 264 brand += sizeof(regs); 265 } 266 } 267 268 switch (cpu_vendor_id) { 269 case CPU_VENDOR_INTEL: 270 #ifdef __i386__ 271 if ((cpu_id & 0xf00) > 0x300) { 272 u_int brand_index; 273 274 cpu_model[0] = '\0'; 275 276 switch (cpu_id & 0x3000) { 277 case 0x1000: 278 strcpy(cpu_model, "Overdrive "); 279 break; 280 case 0x2000: 281 strcpy(cpu_model, "Dual "); 282 break; 283 } 284 285 switch (cpu_id & 0xf00) { 286 case 0x400: 287 strcat(cpu_model, "i486 "); 288 /* Check the particular flavor of 486 */ 289 switch (cpu_id & 0xf0) { 290 case 0x00: 291 case 0x10: 292 strcat(cpu_model, "DX"); 293 break; 294 case 0x20: 295 strcat(cpu_model, "SX"); 296 break; 297 case 0x30: 298 strcat(cpu_model, "DX2"); 299 break; 300 case 0x40: 301 strcat(cpu_model, "SL"); 302 break; 303 case 0x50: 304 strcat(cpu_model, "SX2"); 305 break; 306 case 0x70: 307 strcat(cpu_model, 308 "DX2 Write-Back Enhanced"); 309 break; 310 case 0x80: 311 strcat(cpu_model, "DX4"); 312 break; 313 } 314 break; 315 case 0x500: 316 /* Check the particular flavor of 586 */ 317 strcat(cpu_model, "Pentium"); 318 switch (cpu_id & 0xf0) { 319 case 0x00: 320 strcat(cpu_model, " A-step"); 321 break; 322 case 0x10: 323 strcat(cpu_model, "/P5"); 324 break; 325 case 0x20: 326 strcat(cpu_model, "/P54C"); 327 break; 328 case 0x30: 329 strcat(cpu_model, "/P24T"); 330 break; 331 case 0x40: 332 strcat(cpu_model, "/P55C"); 333 break; 334 case 0x70: 335 strcat(cpu_model, "/P54C"); 336 break; 337 case 0x80: 338 strcat(cpu_model, "/P55C (quarter-micron)"); 339 break; 340 default: 341 /* nothing */ 342 break; 343 } 344 #if defined(I586_CPU) && !defined(NO_F00F_HACK) 345 /* 346 * XXX - If/when Intel fixes the bug, this 347 * should also check the version of the 348 * CPU, not just that it's a Pentium. 349 */ 350 has_f00f_bug = 1; 351 #endif 352 break; 353 case 0x600: 354 /* Check the particular flavor of 686 */ 355 switch (cpu_id & 0xf0) { 356 case 0x00: 357 strcat(cpu_model, "Pentium Pro A-step"); 358 break; 359 case 0x10: 360 strcat(cpu_model, "Pentium Pro"); 361 break; 362 case 0x30: 363 case 0x50: 364 case 0x60: 365 strcat(cpu_model, 366 "Pentium II/Pentium II Xeon/Celeron"); 367 cpu = CPU_PII; 368 break; 369 case 0x70: 370 case 0x80: 371 case 0xa0: 372 case 0xb0: 373 strcat(cpu_model, 374 "Pentium III/Pentium III Xeon/Celeron"); 375 cpu = CPU_PIII; 376 break; 377 default: 378 strcat(cpu_model, "Unknown 80686"); 379 break; 380 } 381 break; 382 case 0xf00: 383 strcat(cpu_model, "Pentium 4"); 384 cpu = CPU_P4; 385 break; 386 default: 387 strcat(cpu_model, "unknown"); 388 break; 389 } 390 391 /* 392 * If we didn't get a brand name from the extended 393 * CPUID, try to look it up in the brand table. 394 */ 395 if (cpu_high > 0 && *cpu_brand == '\0') { 396 brand_index = cpu_procinfo & CPUID_BRAND_INDEX; 397 if (brand_index <= MAX_BRAND_INDEX && 398 cpu_brandtable[brand_index] != NULL) 399 strcpy(cpu_brand, 400 cpu_brandtable[brand_index]); 401 } 402 } 403 #else 404 /* Please make up your mind folks! */ 405 strcat(cpu_model, "EM64T"); 406 #endif 407 break; 408 case CPU_VENDOR_AMD: 409 /* 410 * Values taken from AMD Processor Recognition 411 * http://www.amd.com/K6/k6docs/pdf/20734g.pdf 412 * (also describes ``Features'' encodings. 413 */ 414 strcpy(cpu_model, "AMD "); 415 #ifdef __i386__ 416 switch (cpu_id & 0xFF0) { 417 case 0x410: 418 strcat(cpu_model, "Standard Am486DX"); 419 break; 420 case 0x430: 421 strcat(cpu_model, "Enhanced Am486DX2 Write-Through"); 422 break; 423 case 0x470: 424 strcat(cpu_model, "Enhanced Am486DX2 Write-Back"); 425 break; 426 case 0x480: 427 strcat(cpu_model, "Enhanced Am486DX4/Am5x86 Write-Through"); 428 break; 429 case 0x490: 430 strcat(cpu_model, "Enhanced Am486DX4/Am5x86 Write-Back"); 431 break; 432 case 0x4E0: 433 strcat(cpu_model, "Am5x86 Write-Through"); 434 break; 435 case 0x4F0: 436 strcat(cpu_model, "Am5x86 Write-Back"); 437 break; 438 case 0x500: 439 strcat(cpu_model, "K5 model 0"); 440 break; 441 case 0x510: 442 strcat(cpu_model, "K5 model 1"); 443 break; 444 case 0x520: 445 strcat(cpu_model, "K5 PR166 (model 2)"); 446 break; 447 case 0x530: 448 strcat(cpu_model, "K5 PR200 (model 3)"); 449 break; 450 case 0x560: 451 strcat(cpu_model, "K6"); 452 break; 453 case 0x570: 454 strcat(cpu_model, "K6 266 (model 1)"); 455 break; 456 case 0x580: 457 strcat(cpu_model, "K6-2"); 458 break; 459 case 0x590: 460 strcat(cpu_model, "K6-III"); 461 break; 462 case 0x5a0: 463 strcat(cpu_model, "Geode LX"); 464 break; 465 default: 466 strcat(cpu_model, "Unknown"); 467 break; 468 } 469 #else 470 if ((cpu_id & 0xf00) == 0xf00) 471 strcat(cpu_model, "AMD64 Processor"); 472 else 473 strcat(cpu_model, "Unknown"); 474 #endif 475 break; 476 #ifdef __i386__ 477 case CPU_VENDOR_CYRIX: 478 strcpy(cpu_model, "Cyrix "); 479 switch (cpu_id & 0xff0) { 480 case 0x440: 481 strcat(cpu_model, "MediaGX"); 482 break; 483 case 0x520: 484 strcat(cpu_model, "6x86"); 485 break; 486 case 0x540: 487 cpu_class = CPUCLASS_586; 488 strcat(cpu_model, "GXm"); 489 break; 490 case 0x600: 491 strcat(cpu_model, "6x86MX"); 492 break; 493 default: 494 /* 495 * Even though CPU supports the cpuid 496 * instruction, it can be disabled. 497 * Therefore, this routine supports all Cyrix 498 * CPUs. 499 */ 500 switch (cyrix_did & 0xf0) { 501 case 0x00: 502 switch (cyrix_did & 0x0f) { 503 case 0x00: 504 strcat(cpu_model, "486SLC"); 505 break; 506 case 0x01: 507 strcat(cpu_model, "486DLC"); 508 break; 509 case 0x02: 510 strcat(cpu_model, "486SLC2"); 511 break; 512 case 0x03: 513 strcat(cpu_model, "486DLC2"); 514 break; 515 case 0x04: 516 strcat(cpu_model, "486SRx"); 517 break; 518 case 0x05: 519 strcat(cpu_model, "486DRx"); 520 break; 521 case 0x06: 522 strcat(cpu_model, "486SRx2"); 523 break; 524 case 0x07: 525 strcat(cpu_model, "486DRx2"); 526 break; 527 case 0x08: 528 strcat(cpu_model, "486SRu"); 529 break; 530 case 0x09: 531 strcat(cpu_model, "486DRu"); 532 break; 533 case 0x0a: 534 strcat(cpu_model, "486SRu2"); 535 break; 536 case 0x0b: 537 strcat(cpu_model, "486DRu2"); 538 break; 539 default: 540 strcat(cpu_model, "Unknown"); 541 break; 542 } 543 break; 544 case 0x10: 545 switch (cyrix_did & 0x0f) { 546 case 0x00: 547 strcat(cpu_model, "486S"); 548 break; 549 case 0x01: 550 strcat(cpu_model, "486S2"); 551 break; 552 case 0x02: 553 strcat(cpu_model, "486Se"); 554 break; 555 case 0x03: 556 strcat(cpu_model, "486S2e"); 557 break; 558 case 0x0a: 559 strcat(cpu_model, "486DX"); 560 break; 561 case 0x0b: 562 strcat(cpu_model, "486DX2"); 563 break; 564 case 0x0f: 565 strcat(cpu_model, "486DX4"); 566 break; 567 default: 568 strcat(cpu_model, "Unknown"); 569 break; 570 } 571 break; 572 case 0x20: 573 if ((cyrix_did & 0x0f) < 8) 574 strcat(cpu_model, "6x86"); /* Where did you get it? */ 575 else 576 strcat(cpu_model, "5x86"); 577 break; 578 case 0x30: 579 strcat(cpu_model, "6x86"); 580 break; 581 case 0x40: 582 if ((cyrix_did & 0xf000) == 0x3000) { 583 cpu_class = CPUCLASS_586; 584 strcat(cpu_model, "GXm"); 585 } else 586 strcat(cpu_model, "MediaGX"); 587 break; 588 case 0x50: 589 strcat(cpu_model, "6x86MX"); 590 break; 591 case 0xf0: 592 switch (cyrix_did & 0x0f) { 593 case 0x0d: 594 strcat(cpu_model, "Overdrive CPU"); 595 break; 596 case 0x0e: 597 strcpy(cpu_model, "Texas Instruments 486SXL"); 598 break; 599 case 0x0f: 600 strcat(cpu_model, "486SLC/DLC"); 601 break; 602 default: 603 strcat(cpu_model, "Unknown"); 604 break; 605 } 606 break; 607 default: 608 strcat(cpu_model, "Unknown"); 609 break; 610 } 611 break; 612 } 613 break; 614 case CPU_VENDOR_RISE: 615 strcpy(cpu_model, "Rise "); 616 switch (cpu_id & 0xff0) { 617 case 0x500: /* 6401 and 6441 (Kirin) */ 618 case 0x520: /* 6510 (Lynx) */ 619 strcat(cpu_model, "mP6"); 620 break; 621 default: 622 strcat(cpu_model, "Unknown"); 623 } 624 break; 625 #endif 626 case CPU_VENDOR_CENTAUR: 627 #ifdef __i386__ 628 switch (cpu_id & 0xff0) { 629 case 0x540: 630 strcpy(cpu_model, "IDT WinChip C6"); 631 break; 632 case 0x580: 633 strcpy(cpu_model, "IDT WinChip 2"); 634 break; 635 case 0x590: 636 strcpy(cpu_model, "IDT WinChip 3"); 637 break; 638 case 0x660: 639 strcpy(cpu_model, "VIA C3 Samuel"); 640 break; 641 case 0x670: 642 if (cpu_id & 0x8) 643 strcpy(cpu_model, "VIA C3 Ezra"); 644 else 645 strcpy(cpu_model, "VIA C3 Samuel 2"); 646 break; 647 case 0x680: 648 strcpy(cpu_model, "VIA C3 Ezra-T"); 649 break; 650 case 0x690: 651 strcpy(cpu_model, "VIA C3 Nehemiah"); 652 break; 653 case 0x6a0: 654 case 0x6d0: 655 strcpy(cpu_model, "VIA C7 Esther"); 656 break; 657 case 0x6f0: 658 strcpy(cpu_model, "VIA Nano"); 659 break; 660 default: 661 strcpy(cpu_model, "VIA/IDT Unknown"); 662 } 663 #else 664 strcpy(cpu_model, "VIA "); 665 if ((cpu_id & 0xff0) == 0x6f0) 666 strcat(cpu_model, "Nano Processor"); 667 else 668 strcat(cpu_model, "Unknown"); 669 #endif 670 break; 671 #ifdef __i386__ 672 case CPU_VENDOR_IBM: 673 strcpy(cpu_model, "Blue Lightning CPU"); 674 break; 675 case CPU_VENDOR_NSC: 676 switch (cpu_id & 0xff0) { 677 case 0x540: 678 strcpy(cpu_model, "Geode SC1100"); 679 cpu = CPU_GEODE1100; 680 break; 681 default: 682 strcpy(cpu_model, "Geode/NSC unknown"); 683 break; 684 } 685 break; 686 #endif 687 case CPU_VENDOR_HYGON: 688 strcpy(cpu_model, "Hygon "); 689 #ifdef __i386__ 690 strcat(cpu_model, "Unknown"); 691 #else 692 if ((cpu_id & 0xf00) == 0xf00) 693 strcat(cpu_model, "AMD64 Processor"); 694 else 695 strcat(cpu_model, "Unknown"); 696 #endif 697 break; 698 699 default: 700 strcat(cpu_model, "Unknown"); 701 break; 702 } 703 704 /* 705 * Replace cpu_model with cpu_brand minus leading spaces if 706 * we have one. 707 */ 708 brand = cpu_brand; 709 while (*brand == ' ') 710 ++brand; 711 if (*brand != '\0') 712 strcpy(cpu_model, brand); 713 714 printf("%s (", cpu_model); 715 if (tsc_freq != 0) { 716 hw_clockrate = (tsc_freq + 5000) / 1000000; 717 printf("%jd.%02d-MHz ", 718 (intmax_t)(tsc_freq + 4999) / 1000000, 719 (u_int)((tsc_freq + 4999) / 10000) % 100); 720 } 721 #ifdef __i386__ 722 switch(cpu_class) { 723 case CPUCLASS_286: 724 printf("286"); 725 break; 726 case CPUCLASS_386: 727 printf("386"); 728 break; 729 #if defined(I486_CPU) 730 case CPUCLASS_486: 731 printf("486"); 732 break; 733 #endif 734 #if defined(I586_CPU) 735 case CPUCLASS_586: 736 printf("586"); 737 break; 738 #endif 739 #if defined(I686_CPU) 740 case CPUCLASS_686: 741 printf("686"); 742 break; 743 #endif 744 default: 745 printf("Unknown"); /* will panic below... */ 746 } 747 #else 748 printf("K8"); 749 #endif 750 printf("-class CPU)\n"); 751 if (*cpu_vendor) 752 printf(" Origin=\"%s\"", cpu_vendor); 753 if (cpu_id) 754 printf(" Id=0x%x", cpu_id); 755 756 if (cpu_vendor_id == CPU_VENDOR_INTEL || 757 cpu_vendor_id == CPU_VENDOR_AMD || 758 cpu_vendor_id == CPU_VENDOR_HYGON || 759 cpu_vendor_id == CPU_VENDOR_CENTAUR || 760 #ifdef __i386__ 761 cpu_vendor_id == CPU_VENDOR_TRANSMETA || 762 cpu_vendor_id == CPU_VENDOR_RISE || 763 cpu_vendor_id == CPU_VENDOR_NSC || 764 (cpu_vendor_id == CPU_VENDOR_CYRIX && ((cpu_id & 0xf00) > 0x500)) || 765 #endif 766 0) { 767 printf(" Family=0x%x", CPUID_TO_FAMILY(cpu_id)); 768 printf(" Model=0x%x", CPUID_TO_MODEL(cpu_id)); 769 printf(" Stepping=%u", cpu_id & CPUID_STEPPING); 770 #ifdef __i386__ 771 if (cpu_vendor_id == CPU_VENDOR_CYRIX) 772 printf("\n DIR=0x%04x", cyrix_did); 773 #endif 774 775 /* 776 * AMD CPUID Specification 777 * http://support.amd.com/us/Embedded_TechDocs/25481.pdf 778 * 779 * Intel Processor Identification and CPUID Instruction 780 * http://www.intel.com/assets/pdf/appnote/241618.pdf 781 */ 782 if (cpu_high > 0) { 783 /* 784 * Here we should probably set up flags indicating 785 * whether or not various features are available. 786 * The interesting ones are probably VME, PSE, PAE, 787 * and PGE. The code already assumes without bothering 788 * to check that all CPUs >= Pentium have a TSC and 789 * MSRs. 790 */ 791 printf("\n Features=0x%b", cpu_feature, 792 "\020" 793 "\001FPU" /* Integral FPU */ 794 "\002VME" /* Extended VM86 mode support */ 795 "\003DE" /* Debugging Extensions (CR4.DE) */ 796 "\004PSE" /* 4MByte page tables */ 797 "\005TSC" /* Timestamp counter */ 798 "\006MSR" /* Machine specific registers */ 799 "\007PAE" /* Physical address extension */ 800 "\010MCE" /* Machine Check support */ 801 "\011CX8" /* CMPEXCH8 instruction */ 802 "\012APIC" /* SMP local APIC */ 803 "\013oldMTRR" /* Previous implementation of MTRR */ 804 "\014SEP" /* Fast System Call */ 805 "\015MTRR" /* Memory Type Range Registers */ 806 "\016PGE" /* PG_G (global bit) support */ 807 "\017MCA" /* Machine Check Architecture */ 808 "\020CMOV" /* CMOV instruction */ 809 "\021PAT" /* Page attributes table */ 810 "\022PSE36" /* 36 bit address space support */ 811 "\023PN" /* Processor Serial number */ 812 "\024CLFLUSH" /* Has the CLFLUSH instruction */ 813 "\025<b20>" 814 "\026DTS" /* Debug Trace Store */ 815 "\027ACPI" /* ACPI support */ 816 "\030MMX" /* MMX instructions */ 817 "\031FXSR" /* FXSAVE/FXRSTOR */ 818 "\032SSE" /* Streaming SIMD Extensions */ 819 "\033SSE2" /* Streaming SIMD Extensions #2 */ 820 "\034SS" /* Self snoop */ 821 "\035HTT" /* Hyperthreading (see EBX bit 16-23) */ 822 "\036TM" /* Thermal Monitor clock slowdown */ 823 "\037IA64" /* CPU can execute IA64 instructions */ 824 "\040PBE" /* Pending Break Enable */ 825 ); 826 827 if (cpu_feature2 != 0) { 828 printf("\n Features2=0x%b", cpu_feature2, 829 "\020" 830 "\001SSE3" /* SSE3 */ 831 "\002PCLMULQDQ" /* Carry-Less Mul Quadword */ 832 "\003DTES64" /* 64-bit Debug Trace */ 833 "\004MON" /* MONITOR/MWAIT Instructions */ 834 "\005DS_CPL" /* CPL Qualified Debug Store */ 835 "\006VMX" /* Virtual Machine Extensions */ 836 "\007SMX" /* Safer Mode Extensions */ 837 "\010EST" /* Enhanced SpeedStep */ 838 "\011TM2" /* Thermal Monitor 2 */ 839 "\012SSSE3" /* SSSE3 */ 840 "\013CNXT-ID" /* L1 context ID available */ 841 "\014SDBG" /* IA32 silicon debug */ 842 "\015FMA" /* Fused Multiply Add */ 843 "\016CX16" /* CMPXCHG16B Instruction */ 844 "\017xTPR" /* Send Task Priority Messages*/ 845 "\020PDCM" /* Perf/Debug Capability MSR */ 846 "\021<b16>" 847 "\022PCID" /* Process-context Identifiers*/ 848 "\023DCA" /* Direct Cache Access */ 849 "\024SSE4.1" /* SSE 4.1 */ 850 "\025SSE4.2" /* SSE 4.2 */ 851 "\026x2APIC" /* xAPIC Extensions */ 852 "\027MOVBE" /* MOVBE Instruction */ 853 "\030POPCNT" /* POPCNT Instruction */ 854 "\031TSCDLT" /* TSC-Deadline Timer */ 855 "\032AESNI" /* AES Crypto */ 856 "\033XSAVE" /* XSAVE/XRSTOR States */ 857 "\034OSXSAVE" /* OS-Enabled State Management*/ 858 "\035AVX" /* Advanced Vector Extensions */ 859 "\036F16C" /* Half-precision conversions */ 860 "\037RDRAND" /* RDRAND Instruction */ 861 "\040HV" /* Hypervisor */ 862 ); 863 } 864 865 if (amd_feature != 0) { 866 printf("\n AMD Features=0x%b", amd_feature, 867 "\020" /* in hex */ 868 "\001<s0>" /* Same */ 869 "\002<s1>" /* Same */ 870 "\003<s2>" /* Same */ 871 "\004<s3>" /* Same */ 872 "\005<s4>" /* Same */ 873 "\006<s5>" /* Same */ 874 "\007<s6>" /* Same */ 875 "\010<s7>" /* Same */ 876 "\011<s8>" /* Same */ 877 "\012<s9>" /* Same */ 878 "\013<b10>" /* Undefined */ 879 "\014SYSCALL" /* Have SYSCALL/SYSRET */ 880 "\015<s12>" /* Same */ 881 "\016<s13>" /* Same */ 882 "\017<s14>" /* Same */ 883 "\020<s15>" /* Same */ 884 "\021<s16>" /* Same */ 885 "\022<s17>" /* Same */ 886 "\023<b18>" /* Reserved, unknown */ 887 "\024MP" /* Multiprocessor Capable */ 888 "\025NX" /* Has EFER.NXE, NX */ 889 "\026<b21>" /* Undefined */ 890 "\027MMX+" /* AMD MMX Extensions */ 891 "\030<s23>" /* Same */ 892 "\031<s24>" /* Same */ 893 "\032FFXSR" /* Fast FXSAVE/FXRSTOR */ 894 "\033Page1GB" /* 1-GB large page support */ 895 "\034RDTSCP" /* RDTSCP */ 896 "\035<b28>" /* Undefined */ 897 "\036LM" /* 64 bit long mode */ 898 "\0373DNow!+" /* AMD 3DNow! Extensions */ 899 "\0403DNow!" /* AMD 3DNow! */ 900 ); 901 } 902 903 if (amd_feature2 != 0) { 904 printf("\n AMD Features2=0x%b", amd_feature2, 905 "\020" 906 "\001LAHF" /* LAHF/SAHF in long mode */ 907 "\002CMP" /* CMP legacy */ 908 "\003SVM" /* Secure Virtual Mode */ 909 "\004ExtAPIC" /* Extended APIC register */ 910 "\005CR8" /* CR8 in legacy mode */ 911 "\006ABM" /* LZCNT instruction */ 912 "\007SSE4A" /* SSE4A */ 913 "\010MAS" /* Misaligned SSE mode */ 914 "\011Prefetch" /* 3DNow! Prefetch/PrefetchW */ 915 "\012OSVW" /* OS visible workaround */ 916 "\013IBS" /* Instruction based sampling */ 917 "\014XOP" /* XOP extended instructions */ 918 "\015SKINIT" /* SKINIT/STGI */ 919 "\016WDT" /* Watchdog timer */ 920 "\017<b14>" 921 "\020LWP" /* Lightweight Profiling */ 922 "\021FMA4" /* 4-operand FMA instructions */ 923 "\022TCE" /* Translation Cache Extension */ 924 "\023<b18>" 925 "\024NodeId" /* NodeId MSR support */ 926 "\025<b20>" 927 "\026TBM" /* Trailing Bit Manipulation */ 928 "\027Topology" /* Topology Extensions */ 929 "\030PCXC" /* Core perf count */ 930 "\031PNXC" /* NB perf count */ 931 "\032<b25>" 932 "\033DBE" /* Data Breakpoint extension */ 933 "\034PTSC" /* Performance TSC */ 934 "\035PL2I" /* L2I perf count */ 935 "\036MWAITX" /* MONITORX/MWAITX instructions */ 936 "\037ADMSKX" /* Address mask extension */ 937 "\040<b31>" 938 ); 939 } 940 941 if (cpu_stdext_feature != 0) { 942 printf("\n Structured Extended Features=0x%b", 943 cpu_stdext_feature, 944 "\020" 945 /* RDFSBASE/RDGSBASE/WRFSBASE/WRGSBASE */ 946 "\001FSGSBASE" 947 "\002TSCADJ" 948 "\003SGX" 949 /* Bit Manipulation Instructions */ 950 "\004BMI1" 951 /* Hardware Lock Elision */ 952 "\005HLE" 953 /* Advanced Vector Instructions 2 */ 954 "\006AVX2" 955 /* FDP_EXCPTN_ONLY */ 956 "\007FDPEXC" 957 /* Supervisor Mode Execution Prot. */ 958 "\010SMEP" 959 /* Bit Manipulation Instructions */ 960 "\011BMI2" 961 "\012ERMS" 962 /* Invalidate Processor Context ID */ 963 "\013INVPCID" 964 /* Restricted Transactional Memory */ 965 "\014RTM" 966 "\015PQM" 967 "\016NFPUSG" 968 /* Intel Memory Protection Extensions */ 969 "\017MPX" 970 "\020PQE" 971 /* AVX512 Foundation */ 972 "\021AVX512F" 973 "\022AVX512DQ" 974 /* Enhanced NRBG */ 975 "\023RDSEED" 976 /* ADCX + ADOX */ 977 "\024ADX" 978 /* Supervisor Mode Access Prevention */ 979 "\025SMAP" 980 "\026AVX512IFMA" 981 /* Formerly PCOMMIT */ 982 "\027<b22>" 983 "\030CLFLUSHOPT" 984 "\031CLWB" 985 "\032PROCTRACE" 986 "\033AVX512PF" 987 "\034AVX512ER" 988 "\035AVX512CD" 989 "\036SHA" 990 "\037AVX512BW" 991 "\040AVX512VL" 992 ); 993 } 994 995 if (cpu_stdext_feature2 != 0) { 996 printf("\n Structured Extended Features2=0x%b", 997 cpu_stdext_feature2, 998 "\020" 999 "\001PREFETCHWT1" 1000 "\002AVX512VBMI" 1001 "\003UMIP" 1002 "\004PKU" 1003 "\005OSPKE" 1004 "\006WAITPKG" 1005 "\007AVX512VBMI2" 1006 "\011GFNI" 1007 "\012VAES" 1008 "\013VPCLMULQDQ" 1009 "\014AVX512VNNI" 1010 "\015AVX512BITALG" 1011 "\016TME" 1012 "\017AVX512VPOPCNTDQ" 1013 "\021LA57" 1014 "\027RDPID" 1015 "\032CLDEMOTE" 1016 "\034MOVDIRI" 1017 "\035MOVDIR64B" 1018 "\036ENQCMD" 1019 "\037SGXLC" 1020 ); 1021 } 1022 1023 if (cpu_stdext_feature3 != 0) { 1024 printf("\n Structured Extended Features3=0x%b", 1025 cpu_stdext_feature3, 1026 "\020" 1027 "\003AVX512_4VNNIW" 1028 "\004AVX512_4FMAPS" 1029 "\005FSRM" 1030 "\011AVX512VP2INTERSECT" 1031 "\012MCUOPT" 1032 "\013MD_CLEAR" 1033 "\016TSXFA" 1034 "\023PCONFIG" 1035 "\025IBT" 1036 "\033IBPB" 1037 "\034STIBP" 1038 "\035L1DFL" 1039 "\036ARCH_CAP" 1040 "\037CORE_CAP" 1041 "\040SSBD" 1042 ); 1043 } 1044 1045 if ((cpu_feature2 & CPUID2_XSAVE) != 0) { 1046 cpuid_count(0xd, 0x1, regs); 1047 if (regs[0] != 0) { 1048 printf("\n XSAVE Features=0x%b", 1049 regs[0], 1050 "\020" 1051 "\001XSAVEOPT" 1052 "\002XSAVEC" 1053 "\003XINUSE" 1054 "\004XSAVES"); 1055 } 1056 } 1057 1058 if (cpu_ia32_arch_caps != 0) { 1059 printf("\n IA32_ARCH_CAPS=0x%b", 1060 (u_int)cpu_ia32_arch_caps, 1061 "\020" 1062 "\001RDCL_NO" 1063 "\002IBRS_ALL" 1064 "\003RSBA" 1065 "\004SKIP_L1DFL_VME" 1066 "\005SSB_NO" 1067 "\006MDS_NO" 1068 "\010TSX_CTRL" 1069 "\011TAA_NO" 1070 ); 1071 } 1072 1073 if (amd_extended_feature_extensions != 0) { 1074 u_int amd_fe_masked; 1075 1076 amd_fe_masked = amd_extended_feature_extensions; 1077 if ((amd_fe_masked & AMDFEID_IBRS) == 0) 1078 amd_fe_masked &= 1079 ~(AMDFEID_IBRS_ALWAYSON | 1080 AMDFEID_PREFER_IBRS); 1081 if ((amd_fe_masked & AMDFEID_STIBP) == 0) 1082 amd_fe_masked &= 1083 ~AMDFEID_STIBP_ALWAYSON; 1084 1085 printf("\n " 1086 "AMD Extended Feature Extensions ID EBX=" 1087 "0x%b", amd_fe_masked, 1088 "\020" 1089 "\001CLZERO" 1090 "\002IRPerf" 1091 "\003XSaveErPtr" 1092 "\005RDPRU" 1093 "\011MCOMMIT" 1094 "\012WBNOINVD" 1095 "\015IBPB" 1096 "\017IBRS" 1097 "\020STIBP" 1098 "\021IBRS_ALWAYSON" 1099 "\022STIBP_ALWAYSON" 1100 "\023PREFER_IBRS" 1101 "\030PPIN" 1102 "\031SSBD" 1103 "\032VIRT_SSBD" 1104 "\033SSB_NO" 1105 ); 1106 } 1107 1108 if (via_feature_rng != 0 || via_feature_xcrypt != 0) 1109 print_via_padlock_info(); 1110 1111 if (cpu_feature2 & CPUID2_VMX) 1112 print_vmx_info(); 1113 1114 if (amd_feature2 & AMDID2_SVM) 1115 print_svm_info(); 1116 1117 if ((cpu_feature & CPUID_HTT) && 1118 (cpu_vendor_id == CPU_VENDOR_AMD || 1119 cpu_vendor_id == CPU_VENDOR_HYGON)) 1120 cpu_feature &= ~CPUID_HTT; 1121 1122 /* 1123 * If this CPU supports P-state invariant TSC then 1124 * mention the capability. 1125 */ 1126 if (tsc_is_invariant) { 1127 printf("\n TSC: P-state invariant"); 1128 if (tsc_perf_stat) 1129 printf(", performance statistics"); 1130 } 1131 } 1132 #ifdef __i386__ 1133 } else if (cpu_vendor_id == CPU_VENDOR_CYRIX) { 1134 printf(" DIR=0x%04x", cyrix_did); 1135 printf(" Stepping=%u", (cyrix_did & 0xf000) >> 12); 1136 printf(" Revision=%u", (cyrix_did & 0x0f00) >> 8); 1137 #ifndef CYRIX_CACHE_REALLY_WORKS 1138 if (cpu == CPU_M1 && (cyrix_did & 0xff00) < 0x1700) 1139 printf("\n CPU cache: write-through mode"); 1140 #endif 1141 #endif 1142 } 1143 1144 /* Avoid ugly blank lines: only print newline when we have to. */ 1145 if (*cpu_vendor || cpu_id) 1146 printf("\n"); 1147 1148 if (bootverbose) { 1149 if (cpu_vendor_id == CPU_VENDOR_AMD || 1150 cpu_vendor_id == CPU_VENDOR_HYGON) 1151 print_AMD_info(); 1152 else if (cpu_vendor_id == CPU_VENDOR_INTEL) 1153 print_INTEL_info(); 1154 #ifdef __i386__ 1155 else if (cpu_vendor_id == CPU_VENDOR_TRANSMETA) 1156 print_transmeta_info(); 1157 #endif 1158 } 1159 1160 print_hypervisor_info(); 1161 } 1162 1163 #ifdef __i386__ 1164 void 1165 panicifcpuunsupported(void) 1166 { 1167 1168 #if !defined(lint) 1169 #if !defined(I486_CPU) && !defined(I586_CPU) && !defined(I686_CPU) 1170 #error This kernel is not configured for one of the supported CPUs 1171 #endif 1172 #else /* lint */ 1173 #endif /* lint */ 1174 /* 1175 * Now that we have told the user what they have, 1176 * let them know if that machine type isn't configured. 1177 */ 1178 switch (cpu_class) { 1179 case CPUCLASS_286: /* a 286 should not make it this far, anyway */ 1180 case CPUCLASS_386: 1181 #if !defined(I486_CPU) 1182 case CPUCLASS_486: 1183 #endif 1184 #if !defined(I586_CPU) 1185 case CPUCLASS_586: 1186 #endif 1187 #if !defined(I686_CPU) 1188 case CPUCLASS_686: 1189 #endif 1190 panic("CPU class not configured"); 1191 default: 1192 break; 1193 } 1194 } 1195 1196 static volatile u_int trap_by_rdmsr; 1197 1198 /* 1199 * Special exception 6 handler. 1200 * The rdmsr instruction generates invalid opcodes fault on 486-class 1201 * Cyrix CPU. Stacked eip register points the rdmsr instruction in the 1202 * function identblue() when this handler is called. Stacked eip should 1203 * be advanced. 1204 */ 1205 inthand_t bluetrap6; 1206 __asm 1207 (" \n\ 1208 .text \n\ 1209 .p2align 2,0x90 \n\ 1210 .type " __XSTRING(CNAME(bluetrap6)) ",@function \n\ 1211 " __XSTRING(CNAME(bluetrap6)) ": \n\ 1212 ss \n\ 1213 movl $0xa8c1d," __XSTRING(CNAME(trap_by_rdmsr)) " \n\ 1214 addl $2, (%esp) /* rdmsr is a 2-byte instruction */ \n\ 1215 iret \n\ 1216 "); 1217 1218 /* 1219 * Special exception 13 handler. 1220 * Accessing non-existent MSR generates general protection fault. 1221 */ 1222 inthand_t bluetrap13; 1223 __asm 1224 (" \n\ 1225 .text \n\ 1226 .p2align 2,0x90 \n\ 1227 .type " __XSTRING(CNAME(bluetrap13)) ",@function \n\ 1228 " __XSTRING(CNAME(bluetrap13)) ": \n\ 1229 ss \n\ 1230 movl $0xa89c4," __XSTRING(CNAME(trap_by_rdmsr)) " \n\ 1231 popl %eax /* discard error code */ \n\ 1232 addl $2, (%esp) /* rdmsr is a 2-byte instruction */ \n\ 1233 iret \n\ 1234 "); 1235 1236 /* 1237 * Distinguish IBM Blue Lightning CPU from Cyrix CPUs that does not 1238 * support cpuid instruction. This function should be called after 1239 * loading interrupt descriptor table register. 1240 * 1241 * I don't like this method that handles fault, but I couldn't get 1242 * information for any other methods. Does blue giant know? 1243 */ 1244 static int 1245 identblue(void) 1246 { 1247 1248 trap_by_rdmsr = 0; 1249 1250 /* 1251 * Cyrix 486-class CPU does not support rdmsr instruction. 1252 * The rdmsr instruction generates invalid opcode fault, and exception 1253 * will be trapped by bluetrap6() on Cyrix 486-class CPU. The 1254 * bluetrap6() set the magic number to trap_by_rdmsr. 1255 */ 1256 setidt(IDT_UD, bluetrap6, SDT_SYS386TGT, SEL_KPL, 1257 GSEL(GCODE_SEL, SEL_KPL)); 1258 1259 /* 1260 * Certain BIOS disables cpuid instruction of Cyrix 6x86MX CPU. 1261 * In this case, rdmsr generates general protection fault, and 1262 * exception will be trapped by bluetrap13(). 1263 */ 1264 setidt(IDT_GP, bluetrap13, SDT_SYS386TGT, SEL_KPL, 1265 GSEL(GCODE_SEL, SEL_KPL)); 1266 1267 rdmsr(0x1002); /* Cyrix CPU generates fault. */ 1268 1269 if (trap_by_rdmsr == 0xa8c1d) 1270 return IDENTBLUE_CYRIX486; 1271 else if (trap_by_rdmsr == 0xa89c4) 1272 return IDENTBLUE_CYRIXM2; 1273 return IDENTBLUE_IBMCPU; 1274 } 1275 1276 /* 1277 * identifycyrix() set lower 16 bits of cyrix_did as follows: 1278 * 1279 * F E D C B A 9 8 7 6 5 4 3 2 1 0 1280 * +-------+-------+---------------+ 1281 * | SID | RID | Device ID | 1282 * | (DIR 1) | (DIR 0) | 1283 * +-------+-------+---------------+ 1284 */ 1285 static void 1286 identifycyrix(void) 1287 { 1288 register_t saveintr; 1289 int ccr2_test = 0, dir_test = 0; 1290 u_char ccr2, ccr3; 1291 1292 saveintr = intr_disable(); 1293 1294 ccr2 = read_cyrix_reg(CCR2); 1295 write_cyrix_reg(CCR2, ccr2 ^ CCR2_LOCK_NW); 1296 read_cyrix_reg(CCR2); 1297 if (read_cyrix_reg(CCR2) != ccr2) 1298 ccr2_test = 1; 1299 write_cyrix_reg(CCR2, ccr2); 1300 1301 ccr3 = read_cyrix_reg(CCR3); 1302 write_cyrix_reg(CCR3, ccr3 ^ CCR3_MAPEN3); 1303 read_cyrix_reg(CCR3); 1304 if (read_cyrix_reg(CCR3) != ccr3) 1305 dir_test = 1; /* CPU supports DIRs. */ 1306 write_cyrix_reg(CCR3, ccr3); 1307 1308 if (dir_test) { 1309 /* Device ID registers are available. */ 1310 cyrix_did = read_cyrix_reg(DIR1) << 8; 1311 cyrix_did += read_cyrix_reg(DIR0); 1312 } else if (ccr2_test) 1313 cyrix_did = 0x0010; /* 486S A-step */ 1314 else 1315 cyrix_did = 0x00ff; /* Old 486SLC/DLC and TI486SXLC/SXL */ 1316 1317 intr_restore(saveintr); 1318 } 1319 #endif 1320 1321 /* Update TSC freq with the value indicated by the caller. */ 1322 static void 1323 tsc_freq_changed(void *arg __unused, const struct cf_level *level, int status) 1324 { 1325 1326 /* If there was an error during the transition, don't do anything. */ 1327 if (status != 0) 1328 return; 1329 1330 /* Total setting for this level gives the new frequency in MHz. */ 1331 hw_clockrate = level->total_set.freq; 1332 } 1333 1334 static void 1335 hook_tsc_freq(void *arg __unused) 1336 { 1337 1338 if (tsc_is_invariant) 1339 return; 1340 1341 tsc_post_tag = EVENTHANDLER_REGISTER(cpufreq_post_change, 1342 tsc_freq_changed, NULL, EVENTHANDLER_PRI_ANY); 1343 } 1344 1345 SYSINIT(hook_tsc_freq, SI_SUB_CONFIGURE, SI_ORDER_ANY, hook_tsc_freq, NULL); 1346 1347 static struct { 1348 const char *vm_cpuid; 1349 int vm_guest; 1350 void (*init)(void); 1351 } vm_cpuids[] = { 1352 { "XenVMMXenVMM", VM_GUEST_XEN, 1353 #ifdef XENHVM 1354 &xen_early_init, 1355 #endif 1356 }, /* XEN */ 1357 { "Microsoft Hv", VM_GUEST_HV }, /* Microsoft Hyper-V */ 1358 { "VMwareVMware", VM_GUEST_VMWARE }, /* VMware VM */ 1359 { "KVMKVMKVM", VM_GUEST_KVM }, /* KVM */ 1360 { "bhyve bhyve ", VM_GUEST_BHYVE }, /* bhyve */ 1361 { "VBoxVBoxVBox", VM_GUEST_VBOX }, /* VirtualBox */ 1362 }; 1363 1364 static void 1365 identify_hypervisor_cpuid_base(void) 1366 { 1367 void (*init_fn)(void) = NULL; 1368 u_int leaf, regs[4]; 1369 int i; 1370 1371 /* 1372 * [RFC] CPUID usage for interaction between Hypervisors and Linux. 1373 * http://lkml.org/lkml/2008/10/1/246 1374 * 1375 * KB1009458: Mechanisms to determine if software is running in 1376 * a VMware virtual machine 1377 * http://kb.vmware.com/kb/1009458 1378 * 1379 * Search for a hypervisor that we recognize. If we cannot find 1380 * a specific hypervisor, return the first information about the 1381 * hypervisor that we found, as others may be able to use. 1382 */ 1383 for (leaf = 0x40000000; leaf < 0x40010000; leaf += 0x100) { 1384 do_cpuid(leaf, regs); 1385 1386 /* 1387 * KVM from Linux kernels prior to commit 1388 * 57c22e5f35aa4b9b2fe11f73f3e62bbf9ef36190 set %eax 1389 * to 0 rather than a valid hv_high value. Check for 1390 * the KVM signature bytes and fixup %eax to the 1391 * highest supported leaf in that case. 1392 */ 1393 if (regs[0] == 0 && regs[1] == 0x4b4d564b && 1394 regs[2] == 0x564b4d56 && regs[3] == 0x0000004d) 1395 regs[0] = leaf + 1; 1396 1397 if (regs[0] >= leaf) { 1398 enum VM_GUEST prev_vm_guest = vm_guest; 1399 1400 for (i = 0; i < nitems(vm_cpuids); i++) 1401 if (strncmp((const char *)®s[1], 1402 vm_cpuids[i].vm_cpuid, 12) == 0) { 1403 vm_guest = vm_cpuids[i].vm_guest; 1404 init_fn = vm_cpuids[i].init; 1405 break; 1406 } 1407 1408 /* 1409 * If this is the first entry or we found a 1410 * specific hypervisor, record the base, high value, 1411 * and vendor identifier. 1412 */ 1413 if (vm_guest != prev_vm_guest || leaf == 0x40000000) { 1414 hv_base = leaf; 1415 hv_high = regs[0]; 1416 ((u_int *)&hv_vendor)[0] = regs[1]; 1417 ((u_int *)&hv_vendor)[1] = regs[2]; 1418 ((u_int *)&hv_vendor)[2] = regs[3]; 1419 hv_vendor[12] = '\0'; 1420 1421 /* 1422 * If we found a specific hypervisor, then 1423 * we are finished. 1424 */ 1425 if (vm_guest != VM_GUEST_VM && 1426 /* 1427 * Xen and other hypervisors can expose the 1428 * HyperV signature in addition to the 1429 * native one in order to support Viridian 1430 * extensions for Windows guests. 1431 * 1432 * Do the full cpuid scan if HyperV is 1433 * detected, as the native hypervisor is 1434 * preferred. 1435 */ 1436 vm_guest != VM_GUEST_HV) 1437 break; 1438 } 1439 } 1440 } 1441 1442 if (init_fn != NULL) 1443 init_fn(); 1444 } 1445 1446 void 1447 identify_hypervisor(void) 1448 { 1449 u_int regs[4]; 1450 char *p; 1451 1452 TSENTER(); 1453 /* 1454 * If CPUID2_HV is set, we are running in a hypervisor environment. 1455 */ 1456 if (cpu_feature2 & CPUID2_HV) { 1457 vm_guest = VM_GUEST_VM; 1458 identify_hypervisor_cpuid_base(); 1459 1460 /* If we have a definitive vendor, we can return now. */ 1461 if (*hv_vendor != '\0') { 1462 TSEXIT(); 1463 return; 1464 } 1465 } 1466 1467 /* 1468 * Examine SMBIOS strings for older hypervisors. 1469 */ 1470 p = kern_getenv("smbios.system.serial"); 1471 if (p != NULL) { 1472 if (strncmp(p, "VMware-", 7) == 0 || strncmp(p, "VMW", 3) == 0) { 1473 vmware_hvcall(VMW_HVCMD_GETVERSION, regs); 1474 if (regs[1] == VMW_HVMAGIC) { 1475 vm_guest = VM_GUEST_VMWARE; 1476 freeenv(p); 1477 TSEXIT(); 1478 return; 1479 } 1480 } 1481 freeenv(p); 1482 } 1483 TSEXIT(); 1484 } 1485 1486 bool 1487 fix_cpuid(void) 1488 { 1489 uint64_t msr; 1490 1491 /* 1492 * Clear "Limit CPUID Maxval" bit and return true if the caller should 1493 * get the largest standard CPUID function number again if it is set 1494 * from BIOS. It is necessary for probing correct CPU topology later 1495 * and for the correct operation of the AVX-aware userspace. 1496 */ 1497 if (cpu_vendor_id == CPU_VENDOR_INTEL && 1498 ((CPUID_TO_FAMILY(cpu_id) == 0xf && 1499 CPUID_TO_MODEL(cpu_id) >= 0x3) || 1500 (CPUID_TO_FAMILY(cpu_id) == 0x6 && 1501 CPUID_TO_MODEL(cpu_id) >= 0xe))) { 1502 msr = rdmsr(MSR_IA32_MISC_ENABLE); 1503 if ((msr & IA32_MISC_EN_LIMCPUID) != 0) { 1504 msr &= ~IA32_MISC_EN_LIMCPUID; 1505 wrmsr(MSR_IA32_MISC_ENABLE, msr); 1506 return (true); 1507 } 1508 } 1509 1510 /* 1511 * Re-enable AMD Topology Extension that could be disabled by BIOS 1512 * on some notebook processors. Without the extension it's really 1513 * hard to determine the correct CPU cache topology. 1514 * See BIOS and Kernel Developer’s Guide (BKDG) for AMD Family 15h 1515 * Models 60h-6Fh Processors, Publication # 50742. 1516 */ 1517 if (vm_guest == VM_GUEST_NO && cpu_vendor_id == CPU_VENDOR_AMD && 1518 CPUID_TO_FAMILY(cpu_id) == 0x15) { 1519 msr = rdmsr(MSR_EXTFEATURES); 1520 if ((msr & ((uint64_t)1 << 54)) == 0) { 1521 msr |= (uint64_t)1 << 54; 1522 wrmsr(MSR_EXTFEATURES, msr); 1523 return (true); 1524 } 1525 } 1526 return (false); 1527 } 1528 1529 void 1530 identify_cpu1(void) 1531 { 1532 u_int regs[4]; 1533 1534 do_cpuid(0, regs); 1535 cpu_high = regs[0]; 1536 ((u_int *)&cpu_vendor)[0] = regs[1]; 1537 ((u_int *)&cpu_vendor)[1] = regs[3]; 1538 ((u_int *)&cpu_vendor)[2] = regs[2]; 1539 cpu_vendor[12] = '\0'; 1540 1541 do_cpuid(1, regs); 1542 cpu_id = regs[0]; 1543 cpu_procinfo = regs[1]; 1544 cpu_feature = regs[3]; 1545 cpu_feature2 = regs[2]; 1546 } 1547 1548 void 1549 identify_cpu2(void) 1550 { 1551 u_int regs[4], cpu_stdext_disable; 1552 1553 if (cpu_high >= 6) { 1554 cpuid_count(6, 0, regs); 1555 cpu_power_eax = regs[0]; 1556 cpu_power_ebx = regs[1]; 1557 cpu_power_ecx = regs[2]; 1558 cpu_power_edx = regs[3]; 1559 } 1560 1561 if (cpu_high >= 7) { 1562 cpuid_count(7, 0, regs); 1563 cpu_stdext_feature = regs[1]; 1564 1565 /* 1566 * Some hypervisors failed to filter out unsupported 1567 * extended features. Allow to disable the 1568 * extensions, activation of which requires setting a 1569 * bit in CR4, and which VM monitors do not support. 1570 */ 1571 cpu_stdext_disable = 0; 1572 TUNABLE_INT_FETCH("hw.cpu_stdext_disable", &cpu_stdext_disable); 1573 cpu_stdext_feature &= ~cpu_stdext_disable; 1574 1575 cpu_stdext_feature2 = regs[2]; 1576 cpu_stdext_feature3 = regs[3]; 1577 1578 if ((cpu_stdext_feature3 & CPUID_STDEXT3_ARCH_CAP) != 0) 1579 cpu_ia32_arch_caps = rdmsr(MSR_IA32_ARCH_CAP); 1580 } 1581 } 1582 1583 void 1584 identify_cpu_ext_features(void) 1585 { 1586 u_int regs[4]; 1587 1588 if (cpu_high >= 7) { 1589 cpuid_count(7, 0, regs); 1590 cpu_stdext_feature2 = regs[2]; 1591 cpu_stdext_feature3 = regs[3]; 1592 } 1593 } 1594 1595 void 1596 identify_cpu_fixup_bsp(void) 1597 { 1598 u_int regs[4]; 1599 1600 cpu_vendor_id = find_cpu_vendor_id(); 1601 1602 if (fix_cpuid()) { 1603 do_cpuid(0, regs); 1604 cpu_high = regs[0]; 1605 } 1606 } 1607 1608 /* 1609 * Final stage of CPU identification. 1610 */ 1611 void 1612 finishidentcpu(void) 1613 { 1614 u_int regs[4]; 1615 #ifdef __i386__ 1616 u_char ccr3; 1617 #endif 1618 1619 identify_cpu_fixup_bsp(); 1620 1621 if (cpu_high >= 5 && (cpu_feature2 & CPUID2_MON) != 0) { 1622 do_cpuid(5, regs); 1623 cpu_mon_mwait_flags = regs[2]; 1624 cpu_mon_min_size = regs[0] & CPUID5_MON_MIN_SIZE; 1625 cpu_mon_max_size = regs[1] & CPUID5_MON_MAX_SIZE; 1626 } 1627 1628 identify_cpu2(); 1629 1630 #ifdef __i386__ 1631 if (cpu_high > 0 && 1632 (cpu_vendor_id == CPU_VENDOR_INTEL || 1633 cpu_vendor_id == CPU_VENDOR_AMD || 1634 cpu_vendor_id == CPU_VENDOR_HYGON || 1635 cpu_vendor_id == CPU_VENDOR_TRANSMETA || 1636 cpu_vendor_id == CPU_VENDOR_CENTAUR || 1637 cpu_vendor_id == CPU_VENDOR_NSC)) { 1638 do_cpuid(0x80000000, regs); 1639 if (regs[0] >= 0x80000000) 1640 cpu_exthigh = regs[0]; 1641 } 1642 #else 1643 if (cpu_vendor_id == CPU_VENDOR_INTEL || 1644 cpu_vendor_id == CPU_VENDOR_AMD || 1645 cpu_vendor_id == CPU_VENDOR_HYGON || 1646 cpu_vendor_id == CPU_VENDOR_CENTAUR) { 1647 do_cpuid(0x80000000, regs); 1648 cpu_exthigh = regs[0]; 1649 } 1650 #endif 1651 if (cpu_exthigh >= 0x80000001) { 1652 do_cpuid(0x80000001, regs); 1653 amd_feature = regs[3] & ~(cpu_feature & 0x0183f3ff); 1654 amd_feature2 = regs[2]; 1655 } 1656 if (cpu_exthigh >= 0x80000007) { 1657 do_cpuid(0x80000007, regs); 1658 amd_rascap = regs[1]; 1659 amd_pminfo = regs[3]; 1660 } 1661 if (cpu_exthigh >= 0x80000008) { 1662 do_cpuid(0x80000008, regs); 1663 cpu_maxphyaddr = regs[0] & 0xff; 1664 amd_extended_feature_extensions = regs[1]; 1665 cpu_procinfo2 = regs[2]; 1666 } else { 1667 cpu_maxphyaddr = (cpu_feature & CPUID_PAE) != 0 ? 36 : 32; 1668 } 1669 1670 #ifdef __i386__ 1671 if (cpu_vendor_id == CPU_VENDOR_CYRIX) { 1672 if (cpu == CPU_486) { 1673 /* 1674 * These conditions are equivalent to: 1675 * - CPU does not support cpuid instruction. 1676 * - Cyrix/IBM CPU is detected. 1677 */ 1678 if (identblue() == IDENTBLUE_IBMCPU) { 1679 strcpy(cpu_vendor, "IBM"); 1680 cpu_vendor_id = CPU_VENDOR_IBM; 1681 cpu = CPU_BLUE; 1682 return; 1683 } 1684 } 1685 switch (cpu_id & 0xf00) { 1686 case 0x600: 1687 /* 1688 * Cyrix's datasheet does not describe DIRs. 1689 * Therefor, I assume it does not have them 1690 * and use the result of the cpuid instruction. 1691 * XXX they seem to have it for now at least. -Peter 1692 */ 1693 identifycyrix(); 1694 cpu = CPU_M2; 1695 break; 1696 default: 1697 identifycyrix(); 1698 /* 1699 * This routine contains a trick. 1700 * Don't check (cpu_id & 0x00f0) == 0x50 to detect M2, now. 1701 */ 1702 switch (cyrix_did & 0x00f0) { 1703 case 0x00: 1704 case 0xf0: 1705 cpu = CPU_486DLC; 1706 break; 1707 case 0x10: 1708 cpu = CPU_CY486DX; 1709 break; 1710 case 0x20: 1711 if ((cyrix_did & 0x000f) < 8) 1712 cpu = CPU_M1; 1713 else 1714 cpu = CPU_M1SC; 1715 break; 1716 case 0x30: 1717 cpu = CPU_M1; 1718 break; 1719 case 0x40: 1720 /* MediaGX CPU */ 1721 cpu = CPU_M1SC; 1722 break; 1723 default: 1724 /* M2 and later CPUs are treated as M2. */ 1725 cpu = CPU_M2; 1726 1727 /* 1728 * enable cpuid instruction. 1729 */ 1730 ccr3 = read_cyrix_reg(CCR3); 1731 write_cyrix_reg(CCR3, CCR3_MAPEN0); 1732 write_cyrix_reg(CCR4, read_cyrix_reg(CCR4) | CCR4_CPUID); 1733 write_cyrix_reg(CCR3, ccr3); 1734 1735 do_cpuid(0, regs); 1736 cpu_high = regs[0]; /* eax */ 1737 do_cpuid(1, regs); 1738 cpu_id = regs[0]; /* eax */ 1739 cpu_feature = regs[3]; /* edx */ 1740 break; 1741 } 1742 } 1743 } else if (cpu == CPU_486 && *cpu_vendor == '\0') { 1744 /* 1745 * There are BlueLightning CPUs that do not change 1746 * undefined flags by dividing 5 by 2. In this case, 1747 * the CPU identification routine in locore.s leaves 1748 * cpu_vendor null string and puts CPU_486 into the 1749 * cpu. 1750 */ 1751 if (identblue() == IDENTBLUE_IBMCPU) { 1752 strcpy(cpu_vendor, "IBM"); 1753 cpu_vendor_id = CPU_VENDOR_IBM; 1754 cpu = CPU_BLUE; 1755 return; 1756 } 1757 } 1758 #endif 1759 } 1760 1761 int 1762 pti_get_default(void) 1763 { 1764 1765 if (strcmp(cpu_vendor, AMD_VENDOR_ID) == 0 || 1766 strcmp(cpu_vendor, HYGON_VENDOR_ID) == 0) 1767 return (0); 1768 if ((cpu_ia32_arch_caps & IA32_ARCH_CAP_RDCL_NO) != 0) 1769 return (0); 1770 return (1); 1771 } 1772 1773 static u_int 1774 find_cpu_vendor_id(void) 1775 { 1776 int i; 1777 1778 for (i = 0; i < nitems(cpu_vendors); i++) 1779 if (strcmp(cpu_vendor, cpu_vendors[i].vendor) == 0) 1780 return (cpu_vendors[i].vendor_id); 1781 return (0); 1782 } 1783 1784 static void 1785 print_AMD_assoc(int i) 1786 { 1787 if (i == 255) 1788 printf(", fully associative\n"); 1789 else 1790 printf(", %d-way associative\n", i); 1791 } 1792 1793 static void 1794 print_AMD_l2_assoc(int i) 1795 { 1796 switch (i & 0x0f) { 1797 case 0: printf(", disabled/not present\n"); break; 1798 case 1: printf(", direct mapped\n"); break; 1799 case 2: printf(", 2-way associative\n"); break; 1800 case 4: printf(", 4-way associative\n"); break; 1801 case 6: printf(", 8-way associative\n"); break; 1802 case 8: printf(", 16-way associative\n"); break; 1803 case 15: printf(", fully associative\n"); break; 1804 default: printf(", reserved configuration\n"); break; 1805 } 1806 } 1807 1808 static void 1809 print_AMD_info(void) 1810 { 1811 #ifdef __i386__ 1812 uint64_t amd_whcr; 1813 #endif 1814 u_int regs[4]; 1815 1816 if (cpu_exthigh >= 0x80000005) { 1817 do_cpuid(0x80000005, regs); 1818 printf("L1 2MB data TLB: %d entries", (regs[0] >> 16) & 0xff); 1819 print_AMD_assoc(regs[0] >> 24); 1820 1821 printf("L1 2MB instruction TLB: %d entries", regs[0] & 0xff); 1822 print_AMD_assoc((regs[0] >> 8) & 0xff); 1823 1824 printf("L1 4KB data TLB: %d entries", (regs[1] >> 16) & 0xff); 1825 print_AMD_assoc(regs[1] >> 24); 1826 1827 printf("L1 4KB instruction TLB: %d entries", regs[1] & 0xff); 1828 print_AMD_assoc((regs[1] >> 8) & 0xff); 1829 1830 printf("L1 data cache: %d kbytes", regs[2] >> 24); 1831 printf(", %d bytes/line", regs[2] & 0xff); 1832 printf(", %d lines/tag", (regs[2] >> 8) & 0xff); 1833 print_AMD_assoc((regs[2] >> 16) & 0xff); 1834 1835 printf("L1 instruction cache: %d kbytes", regs[3] >> 24); 1836 printf(", %d bytes/line", regs[3] & 0xff); 1837 printf(", %d lines/tag", (regs[3] >> 8) & 0xff); 1838 print_AMD_assoc((regs[3] >> 16) & 0xff); 1839 } 1840 1841 if (cpu_exthigh >= 0x80000006) { 1842 do_cpuid(0x80000006, regs); 1843 if ((regs[0] >> 16) != 0) { 1844 printf("L2 2MB data TLB: %d entries", 1845 (regs[0] >> 16) & 0xfff); 1846 print_AMD_l2_assoc(regs[0] >> 28); 1847 printf("L2 2MB instruction TLB: %d entries", 1848 regs[0] & 0xfff); 1849 print_AMD_l2_assoc((regs[0] >> 28) & 0xf); 1850 } else { 1851 printf("L2 2MB unified TLB: %d entries", 1852 regs[0] & 0xfff); 1853 print_AMD_l2_assoc((regs[0] >> 28) & 0xf); 1854 } 1855 if ((regs[1] >> 16) != 0) { 1856 printf("L2 4KB data TLB: %d entries", 1857 (regs[1] >> 16) & 0xfff); 1858 print_AMD_l2_assoc(regs[1] >> 28); 1859 1860 printf("L2 4KB instruction TLB: %d entries", 1861 (regs[1] >> 16) & 0xfff); 1862 print_AMD_l2_assoc((regs[1] >> 28) & 0xf); 1863 } else { 1864 printf("L2 4KB unified TLB: %d entries", 1865 (regs[1] >> 16) & 0xfff); 1866 print_AMD_l2_assoc((regs[1] >> 28) & 0xf); 1867 } 1868 printf("L2 unified cache: %d kbytes", regs[2] >> 16); 1869 printf(", %d bytes/line", regs[2] & 0xff); 1870 printf(", %d lines/tag", (regs[2] >> 8) & 0x0f); 1871 print_AMD_l2_assoc((regs[2] >> 12) & 0x0f); 1872 } 1873 1874 #ifdef __i386__ 1875 if (((cpu_id & 0xf00) == 0x500) 1876 && (((cpu_id & 0x0f0) > 0x80) 1877 || (((cpu_id & 0x0f0) == 0x80) 1878 && (cpu_id & 0x00f) > 0x07))) { 1879 /* K6-2(new core [Stepping 8-F]), K6-III or later */ 1880 amd_whcr = rdmsr(0xc0000082); 1881 if (!(amd_whcr & (0x3ff << 22))) { 1882 printf("Write Allocate Disable\n"); 1883 } else { 1884 printf("Write Allocate Enable Limit: %dM bytes\n", 1885 (u_int32_t)((amd_whcr & (0x3ff << 22)) >> 22) * 4); 1886 printf("Write Allocate 15-16M bytes: %s\n", 1887 (amd_whcr & (1 << 16)) ? "Enable" : "Disable"); 1888 } 1889 } else if (((cpu_id & 0xf00) == 0x500) 1890 && ((cpu_id & 0x0f0) > 0x50)) { 1891 /* K6, K6-2(old core) */ 1892 amd_whcr = rdmsr(0xc0000082); 1893 if (!(amd_whcr & (0x7f << 1))) { 1894 printf("Write Allocate Disable\n"); 1895 } else { 1896 printf("Write Allocate Enable Limit: %dM bytes\n", 1897 (u_int32_t)((amd_whcr & (0x7f << 1)) >> 1) * 4); 1898 printf("Write Allocate 15-16M bytes: %s\n", 1899 (amd_whcr & 0x0001) ? "Enable" : "Disable"); 1900 printf("Hardware Write Allocate Control: %s\n", 1901 (amd_whcr & 0x0100) ? "Enable" : "Disable"); 1902 } 1903 } 1904 #endif 1905 /* 1906 * Opteron Rev E shows a bug as in very rare occasions a read memory 1907 * barrier is not performed as expected if it is followed by a 1908 * non-atomic read-modify-write instruction. 1909 * As long as that bug pops up very rarely (intensive machine usage 1910 * on other operating systems generally generates one unexplainable 1911 * crash any 2 months) and as long as a model specific fix would be 1912 * impractical at this stage, print out a warning string if the broken 1913 * model and family are identified. 1914 */ 1915 if (CPUID_TO_FAMILY(cpu_id) == 0xf && CPUID_TO_MODEL(cpu_id) >= 0x20 && 1916 CPUID_TO_MODEL(cpu_id) <= 0x3f) 1917 printf("WARNING: This architecture revision has known SMP " 1918 "hardware bugs which may cause random instability\n"); 1919 } 1920 1921 static void 1922 print_INTEL_info(void) 1923 { 1924 u_int regs[4]; 1925 u_int rounds, regnum; 1926 u_int nwaycode, nway; 1927 1928 if (cpu_high >= 2) { 1929 rounds = 0; 1930 do { 1931 do_cpuid(0x2, regs); 1932 if (rounds == 0 && (rounds = (regs[0] & 0xff)) == 0) 1933 break; /* we have a buggy CPU */ 1934 1935 for (regnum = 0; regnum <= 3; ++regnum) { 1936 if (regs[regnum] & (1<<31)) 1937 continue; 1938 if (regnum != 0) 1939 print_INTEL_TLB(regs[regnum] & 0xff); 1940 print_INTEL_TLB((regs[regnum] >> 8) & 0xff); 1941 print_INTEL_TLB((regs[regnum] >> 16) & 0xff); 1942 print_INTEL_TLB((regs[regnum] >> 24) & 0xff); 1943 } 1944 } while (--rounds > 0); 1945 } 1946 1947 if (cpu_exthigh >= 0x80000006) { 1948 do_cpuid(0x80000006, regs); 1949 nwaycode = (regs[2] >> 12) & 0x0f; 1950 if (nwaycode >= 0x02 && nwaycode <= 0x08) 1951 nway = 1 << (nwaycode / 2); 1952 else 1953 nway = 0; 1954 printf("L2 cache: %u kbytes, %u-way associative, %u bytes/line\n", 1955 (regs[2] >> 16) & 0xffff, nway, regs[2] & 0xff); 1956 } 1957 } 1958 1959 static void 1960 print_INTEL_TLB(u_int data) 1961 { 1962 switch (data) { 1963 case 0x0: 1964 case 0x40: 1965 default: 1966 break; 1967 case 0x1: 1968 printf("Instruction TLB: 4 KB pages, 4-way set associative, 32 entries\n"); 1969 break; 1970 case 0x2: 1971 printf("Instruction TLB: 4 MB pages, fully associative, 2 entries\n"); 1972 break; 1973 case 0x3: 1974 printf("Data TLB: 4 KB pages, 4-way set associative, 64 entries\n"); 1975 break; 1976 case 0x4: 1977 printf("Data TLB: 4 MB Pages, 4-way set associative, 8 entries\n"); 1978 break; 1979 case 0x6: 1980 printf("1st-level instruction cache: 8 KB, 4-way set associative, 32 byte line size\n"); 1981 break; 1982 case 0x8: 1983 printf("1st-level instruction cache: 16 KB, 4-way set associative, 32 byte line size\n"); 1984 break; 1985 case 0x9: 1986 printf("1st-level instruction cache: 32 KB, 4-way set associative, 64 byte line size\n"); 1987 break; 1988 case 0xa: 1989 printf("1st-level data cache: 8 KB, 2-way set associative, 32 byte line size\n"); 1990 break; 1991 case 0xb: 1992 printf("Instruction TLB: 4 MByte pages, 4-way set associative, 4 entries\n"); 1993 break; 1994 case 0xc: 1995 printf("1st-level data cache: 16 KB, 4-way set associative, 32 byte line size\n"); 1996 break; 1997 case 0xd: 1998 printf("1st-level data cache: 16 KBytes, 4-way set associative, 64 byte line size"); 1999 break; 2000 case 0xe: 2001 printf("1st-level data cache: 24 KBytes, 6-way set associative, 64 byte line size\n"); 2002 break; 2003 case 0x1d: 2004 printf("2nd-level cache: 128 KBytes, 2-way set associative, 64 byte line size\n"); 2005 break; 2006 case 0x21: 2007 printf("2nd-level cache: 256 KBytes, 8-way set associative, 64 byte line size\n"); 2008 break; 2009 case 0x22: 2010 printf("3rd-level cache: 512 KB, 4-way set associative, sectored cache, 64 byte line size\n"); 2011 break; 2012 case 0x23: 2013 printf("3rd-level cache: 1 MB, 8-way set associative, sectored cache, 64 byte line size\n"); 2014 break; 2015 case 0x24: 2016 printf("2nd-level cache: 1 MBytes, 16-way set associative, 64 byte line size\n"); 2017 break; 2018 case 0x25: 2019 printf("3rd-level cache: 2 MB, 8-way set associative, sectored cache, 64 byte line size\n"); 2020 break; 2021 case 0x29: 2022 printf("3rd-level cache: 4 MB, 8-way set associative, sectored cache, 64 byte line size\n"); 2023 break; 2024 case 0x2c: 2025 printf("1st-level data cache: 32 KB, 8-way set associative, 64 byte line size\n"); 2026 break; 2027 case 0x30: 2028 printf("1st-level instruction cache: 32 KB, 8-way set associative, 64 byte line size\n"); 2029 break; 2030 case 0x39: /* De-listed in SDM rev. 54 */ 2031 printf("2nd-level cache: 128 KB, 4-way set associative, sectored cache, 64 byte line size\n"); 2032 break; 2033 case 0x3b: /* De-listed in SDM rev. 54 */ 2034 printf("2nd-level cache: 128 KB, 2-way set associative, sectored cache, 64 byte line size\n"); 2035 break; 2036 case 0x3c: /* De-listed in SDM rev. 54 */ 2037 printf("2nd-level cache: 256 KB, 4-way set associative, sectored cache, 64 byte line size\n"); 2038 break; 2039 case 0x41: 2040 printf("2nd-level cache: 128 KB, 4-way set associative, 32 byte line size\n"); 2041 break; 2042 case 0x42: 2043 printf("2nd-level cache: 256 KB, 4-way set associative, 32 byte line size\n"); 2044 break; 2045 case 0x43: 2046 printf("2nd-level cache: 512 KB, 4-way set associative, 32 byte line size\n"); 2047 break; 2048 case 0x44: 2049 printf("2nd-level cache: 1 MB, 4-way set associative, 32 byte line size\n"); 2050 break; 2051 case 0x45: 2052 printf("2nd-level cache: 2 MB, 4-way set associative, 32 byte line size\n"); 2053 break; 2054 case 0x46: 2055 printf("3rd-level cache: 4 MB, 4-way set associative, 64 byte line size\n"); 2056 break; 2057 case 0x47: 2058 printf("3rd-level cache: 8 MB, 8-way set associative, 64 byte line size\n"); 2059 break; 2060 case 0x48: 2061 printf("2nd-level cache: 3MByte, 12-way set associative, 64 byte line size\n"); 2062 break; 2063 case 0x49: 2064 if (CPUID_TO_FAMILY(cpu_id) == 0xf && 2065 CPUID_TO_MODEL(cpu_id) == 0x6) 2066 printf("3rd-level cache: 4MB, 16-way set associative, 64-byte line size\n"); 2067 else 2068 printf("2nd-level cache: 4 MByte, 16-way set associative, 64 byte line size"); 2069 break; 2070 case 0x4a: 2071 printf("3rd-level cache: 6MByte, 12-way set associative, 64 byte line size\n"); 2072 break; 2073 case 0x4b: 2074 printf("3rd-level cache: 8MByte, 16-way set associative, 64 byte line size\n"); 2075 break; 2076 case 0x4c: 2077 printf("3rd-level cache: 12MByte, 12-way set associative, 64 byte line size\n"); 2078 break; 2079 case 0x4d: 2080 printf("3rd-level cache: 16MByte, 16-way set associative, 64 byte line size\n"); 2081 break; 2082 case 0x4e: 2083 printf("2nd-level cache: 6MByte, 24-way set associative, 64 byte line size\n"); 2084 break; 2085 case 0x4f: 2086 printf("Instruction TLB: 4 KByte pages, 32 entries\n"); 2087 break; 2088 case 0x50: 2089 printf("Instruction TLB: 4 KB, 2 MB or 4 MB pages, fully associative, 64 entries\n"); 2090 break; 2091 case 0x51: 2092 printf("Instruction TLB: 4 KB, 2 MB or 4 MB pages, fully associative, 128 entries\n"); 2093 break; 2094 case 0x52: 2095 printf("Instruction TLB: 4 KB, 2 MB or 4 MB pages, fully associative, 256 entries\n"); 2096 break; 2097 case 0x55: 2098 printf("Instruction TLB: 2-MByte or 4-MByte pages, fully associative, 7 entries\n"); 2099 break; 2100 case 0x56: 2101 printf("Data TLB0: 4 MByte pages, 4-way set associative, 16 entries\n"); 2102 break; 2103 case 0x57: 2104 printf("Data TLB0: 4 KByte pages, 4-way associative, 16 entries\n"); 2105 break; 2106 case 0x59: 2107 printf("Data TLB0: 4 KByte pages, fully associative, 16 entries\n"); 2108 break; 2109 case 0x5a: 2110 printf("Data TLB0: 2-MByte or 4 MByte pages, 4-way set associative, 32 entries\n"); 2111 break; 2112 case 0x5b: 2113 printf("Data TLB: 4 KB or 4 MB pages, fully associative, 64 entries\n"); 2114 break; 2115 case 0x5c: 2116 printf("Data TLB: 4 KB or 4 MB pages, fully associative, 128 entries\n"); 2117 break; 2118 case 0x5d: 2119 printf("Data TLB: 4 KB or 4 MB pages, fully associative, 256 entries\n"); 2120 break; 2121 case 0x60: 2122 printf("1st-level data cache: 16 KB, 8-way set associative, sectored cache, 64 byte line size\n"); 2123 break; 2124 case 0x61: 2125 printf("Instruction TLB: 4 KByte pages, fully associative, 48 entries\n"); 2126 break; 2127 case 0x63: 2128 printf("Data TLB: 2 MByte or 4 MByte pages, 4-way set associative, 32 entries and a separate array with 1 GByte pages, 4-way set associative, 4 entries\n"); 2129 break; 2130 case 0x64: 2131 printf("Data TLB: 4 KBytes pages, 4-way set associative, 512 entries\n"); 2132 break; 2133 case 0x66: 2134 printf("1st-level data cache: 8 KB, 4-way set associative, sectored cache, 64 byte line size\n"); 2135 break; 2136 case 0x67: 2137 printf("1st-level data cache: 16 KB, 4-way set associative, sectored cache, 64 byte line size\n"); 2138 break; 2139 case 0x68: 2140 printf("1st-level data cache: 32 KB, 4 way set associative, sectored cache, 64 byte line size\n"); 2141 break; 2142 case 0x6a: 2143 printf("uTLB: 4KByte pages, 8-way set associative, 64 entries\n"); 2144 break; 2145 case 0x6b: 2146 printf("DTLB: 4KByte pages, 8-way set associative, 256 entries\n"); 2147 break; 2148 case 0x6c: 2149 printf("DTLB: 2M/4M pages, 8-way set associative, 128 entries\n"); 2150 break; 2151 case 0x6d: 2152 printf("DTLB: 1 GByte pages, fully associative, 16 entries\n"); 2153 break; 2154 case 0x70: 2155 printf("Trace cache: 12K-uops, 8-way set associative\n"); 2156 break; 2157 case 0x71: 2158 printf("Trace cache: 16K-uops, 8-way set associative\n"); 2159 break; 2160 case 0x72: 2161 printf("Trace cache: 32K-uops, 8-way set associative\n"); 2162 break; 2163 case 0x76: 2164 printf("Instruction TLB: 2M/4M pages, fully associative, 8 entries\n"); 2165 break; 2166 case 0x78: 2167 printf("2nd-level cache: 1 MB, 4-way set associative, 64-byte line size\n"); 2168 break; 2169 case 0x79: 2170 printf("2nd-level cache: 128 KB, 8-way set associative, sectored cache, 64 byte line size\n"); 2171 break; 2172 case 0x7a: 2173 printf("2nd-level cache: 256 KB, 8-way set associative, sectored cache, 64 byte line size\n"); 2174 break; 2175 case 0x7b: 2176 printf("2nd-level cache: 512 KB, 8-way set associative, sectored cache, 64 byte line size\n"); 2177 break; 2178 case 0x7c: 2179 printf("2nd-level cache: 1 MB, 8-way set associative, sectored cache, 64 byte line size\n"); 2180 break; 2181 case 0x7d: 2182 printf("2nd-level cache: 2-MB, 8-way set associative, 64-byte line size\n"); 2183 break; 2184 case 0x7f: 2185 printf("2nd-level cache: 512-KB, 2-way set associative, 64-byte line size\n"); 2186 break; 2187 case 0x80: 2188 printf("2nd-level cache: 512 KByte, 8-way set associative, 64-byte line size\n"); 2189 break; 2190 case 0x82: 2191 printf("2nd-level cache: 256 KB, 8-way set associative, 32 byte line size\n"); 2192 break; 2193 case 0x83: 2194 printf("2nd-level cache: 512 KB, 8-way set associative, 32 byte line size\n"); 2195 break; 2196 case 0x84: 2197 printf("2nd-level cache: 1 MB, 8-way set associative, 32 byte line size\n"); 2198 break; 2199 case 0x85: 2200 printf("2nd-level cache: 2 MB, 8-way set associative, 32 byte line size\n"); 2201 break; 2202 case 0x86: 2203 printf("2nd-level cache: 512 KB, 4-way set associative, 64 byte line size\n"); 2204 break; 2205 case 0x87: 2206 printf("2nd-level cache: 1 MB, 8-way set associative, 64 byte line size\n"); 2207 break; 2208 case 0xa0: 2209 printf("DTLB: 4k pages, fully associative, 32 entries\n"); 2210 break; 2211 case 0xb0: 2212 printf("Instruction TLB: 4 KB Pages, 4-way set associative, 128 entries\n"); 2213 break; 2214 case 0xb1: 2215 printf("Instruction TLB: 2M pages, 4-way, 8 entries or 4M pages, 4-way, 4 entries\n"); 2216 break; 2217 case 0xb2: 2218 printf("Instruction TLB: 4KByte pages, 4-way set associative, 64 entries\n"); 2219 break; 2220 case 0xb3: 2221 printf("Data TLB: 4 KB Pages, 4-way set associative, 128 entries\n"); 2222 break; 2223 case 0xb4: 2224 printf("Data TLB1: 4 KByte pages, 4-way associative, 256 entries\n"); 2225 break; 2226 case 0xb5: 2227 printf("Instruction TLB: 4KByte pages, 8-way set associative, 64 entries\n"); 2228 break; 2229 case 0xb6: 2230 printf("Instruction TLB: 4KByte pages, 8-way set associative, 128 entries\n"); 2231 break; 2232 case 0xba: 2233 printf("Data TLB1: 4 KByte pages, 4-way associative, 64 entries\n"); 2234 break; 2235 case 0xc0: 2236 printf("Data TLB: 4 KByte and 4 MByte pages, 4-way associative, 8 entries\n"); 2237 break; 2238 case 0xc1: 2239 printf("Shared 2nd-Level TLB: 4 KByte/2MByte pages, 8-way associative, 1024 entries\n"); 2240 break; 2241 case 0xc2: 2242 printf("DTLB: 4 KByte/2 MByte pages, 4-way associative, 16 entries\n"); 2243 break; 2244 case 0xc3: 2245 printf("Shared 2nd-Level TLB: 4 KByte /2 MByte pages, 6-way associative, 1536 entries. Also 1GBbyte pages, 4-way, 16 entries\n"); 2246 break; 2247 case 0xc4: 2248 printf("DTLB: 2M/4M Byte pages, 4-way associative, 32 entries\n"); 2249 break; 2250 case 0xca: 2251 printf("Shared 2nd-Level TLB: 4 KByte pages, 4-way associative, 512 entries\n"); 2252 break; 2253 case 0xd0: 2254 printf("3rd-level cache: 512 KByte, 4-way set associative, 64 byte line size\n"); 2255 break; 2256 case 0xd1: 2257 printf("3rd-level cache: 1 MByte, 4-way set associative, 64 byte line size\n"); 2258 break; 2259 case 0xd2: 2260 printf("3rd-level cache: 2 MByte, 4-way set associative, 64 byte line size\n"); 2261 break; 2262 case 0xd6: 2263 printf("3rd-level cache: 1 MByte, 8-way set associative, 64 byte line size\n"); 2264 break; 2265 case 0xd7: 2266 printf("3rd-level cache: 2 MByte, 8-way set associative, 64 byte line size\n"); 2267 break; 2268 case 0xd8: 2269 printf("3rd-level cache: 4 MByte, 8-way set associative, 64 byte line size\n"); 2270 break; 2271 case 0xdc: 2272 printf("3rd-level cache: 1.5 MByte, 12-way set associative, 64 byte line size\n"); 2273 break; 2274 case 0xdd: 2275 printf("3rd-level cache: 3 MByte, 12-way set associative, 64 byte line size\n"); 2276 break; 2277 case 0xde: 2278 printf("3rd-level cache: 6 MByte, 12-way set associative, 64 byte line size\n"); 2279 break; 2280 case 0xe2: 2281 printf("3rd-level cache: 2 MByte, 16-way set associative, 64 byte line size\n"); 2282 break; 2283 case 0xe3: 2284 printf("3rd-level cache: 4 MByte, 16-way set associative, 64 byte line size\n"); 2285 break; 2286 case 0xe4: 2287 printf("3rd-level cache: 8 MByte, 16-way set associative, 64 byte line size\n"); 2288 break; 2289 case 0xea: 2290 printf("3rd-level cache: 12MByte, 24-way set associative, 64 byte line size\n"); 2291 break; 2292 case 0xeb: 2293 printf("3rd-level cache: 18MByte, 24-way set associative, 64 byte line size\n"); 2294 break; 2295 case 0xec: 2296 printf("3rd-level cache: 24MByte, 24-way set associative, 64 byte line size\n"); 2297 break; 2298 case 0xf0: 2299 printf("64-Byte prefetching\n"); 2300 break; 2301 case 0xf1: 2302 printf("128-Byte prefetching\n"); 2303 break; 2304 } 2305 } 2306 2307 static void 2308 print_svm_info(void) 2309 { 2310 u_int features, regs[4]; 2311 uint64_t msr; 2312 int comma; 2313 2314 printf("\n SVM: "); 2315 do_cpuid(0x8000000A, regs); 2316 features = regs[3]; 2317 2318 msr = rdmsr(MSR_VM_CR); 2319 if ((msr & VM_CR_SVMDIS) == VM_CR_SVMDIS) 2320 printf("(disabled in BIOS) "); 2321 2322 if (!bootverbose) { 2323 comma = 0; 2324 if (features & (1 << 0)) { 2325 printf("%sNP", comma ? "," : ""); 2326 comma = 1; 2327 } 2328 if (features & (1 << 3)) { 2329 printf("%sNRIP", comma ? "," : ""); 2330 comma = 1; 2331 } 2332 if (features & (1 << 5)) { 2333 printf("%sVClean", comma ? "," : ""); 2334 comma = 1; 2335 } 2336 if (features & (1 << 6)) { 2337 printf("%sAFlush", comma ? "," : ""); 2338 comma = 1; 2339 } 2340 if (features & (1 << 7)) { 2341 printf("%sDAssist", comma ? "," : ""); 2342 comma = 1; 2343 } 2344 printf("%sNAsids=%d", comma ? "," : "", regs[1]); 2345 return; 2346 } 2347 2348 printf("Features=0x%b", features, 2349 "\020" 2350 "\001NP" /* Nested paging */ 2351 "\002LbrVirt" /* LBR virtualization */ 2352 "\003SVML" /* SVM lock */ 2353 "\004NRIPS" /* NRIP save */ 2354 "\005TscRateMsr" /* MSR based TSC rate control */ 2355 "\006VmcbClean" /* VMCB clean bits */ 2356 "\007FlushByAsid" /* Flush by ASID */ 2357 "\010DecodeAssist" /* Decode assist */ 2358 "\011<b8>" 2359 "\012<b9>" 2360 "\013PauseFilter" /* PAUSE intercept filter */ 2361 "\014EncryptedMcodePatch" 2362 "\015PauseFilterThreshold" /* PAUSE filter threshold */ 2363 "\016AVIC" /* virtual interrupt controller */ 2364 "\017<b14>" 2365 "\020V_VMSAVE_VMLOAD" 2366 "\021vGIF" 2367 "\022GMET" /* Guest Mode Execute Trap */ 2368 "\023<b18>" 2369 "\024<b19>" 2370 "\025GuesSpecCtl" /* Guest Spec_ctl */ 2371 "\026<b21>" 2372 "\027<b22>" 2373 "\030<b23>" 2374 "\031<b24>" 2375 "\032<b25>" 2376 "\033<b26>" 2377 "\034<b27>" 2378 "\035<b28>" 2379 "\036<b29>" 2380 "\037<b30>" 2381 "\040<b31>" 2382 ); 2383 printf("\nRevision=%d, ASIDs=%d", regs[0] & 0xff, regs[1]); 2384 } 2385 2386 #ifdef __i386__ 2387 static void 2388 print_transmeta_info(void) 2389 { 2390 u_int regs[4], nreg = 0; 2391 2392 do_cpuid(0x80860000, regs); 2393 nreg = regs[0]; 2394 if (nreg >= 0x80860001) { 2395 do_cpuid(0x80860001, regs); 2396 printf(" Processor revision %u.%u.%u.%u\n", 2397 (regs[1] >> 24) & 0xff, 2398 (regs[1] >> 16) & 0xff, 2399 (regs[1] >> 8) & 0xff, 2400 regs[1] & 0xff); 2401 } 2402 if (nreg >= 0x80860002) { 2403 do_cpuid(0x80860002, regs); 2404 printf(" Code Morphing Software revision %u.%u.%u-%u-%u\n", 2405 (regs[1] >> 24) & 0xff, 2406 (regs[1] >> 16) & 0xff, 2407 (regs[1] >> 8) & 0xff, 2408 regs[1] & 0xff, 2409 regs[2]); 2410 } 2411 if (nreg >= 0x80860006) { 2412 char info[65]; 2413 do_cpuid(0x80860003, (u_int*) &info[0]); 2414 do_cpuid(0x80860004, (u_int*) &info[16]); 2415 do_cpuid(0x80860005, (u_int*) &info[32]); 2416 do_cpuid(0x80860006, (u_int*) &info[48]); 2417 info[64] = 0; 2418 printf(" %s\n", info); 2419 } 2420 } 2421 #endif 2422 2423 static void 2424 print_via_padlock_info(void) 2425 { 2426 u_int regs[4]; 2427 2428 do_cpuid(0xc0000001, regs); 2429 printf("\n VIA Padlock Features=0x%b", regs[3], 2430 "\020" 2431 "\003RNG" /* RNG */ 2432 "\007AES" /* ACE */ 2433 "\011AES-CTR" /* ACE2 */ 2434 "\013SHA1,SHA256" /* PHE */ 2435 "\015RSA" /* PMM */ 2436 ); 2437 } 2438 2439 static uint32_t 2440 vmx_settable(uint64_t basic, int msr, int true_msr) 2441 { 2442 uint64_t val; 2443 2444 if (basic & (1ULL << 55)) 2445 val = rdmsr(true_msr); 2446 else 2447 val = rdmsr(msr); 2448 2449 /* Just report the controls that can be set to 1. */ 2450 return (val >> 32); 2451 } 2452 2453 static void 2454 print_vmx_info(void) 2455 { 2456 uint64_t basic, msr; 2457 uint32_t entry, exit, mask, pin, proc, proc2; 2458 int comma; 2459 2460 printf("\n VT-x: "); 2461 msr = rdmsr(MSR_IA32_FEATURE_CONTROL); 2462 if (!(msr & IA32_FEATURE_CONTROL_VMX_EN)) 2463 printf("(disabled in BIOS) "); 2464 basic = rdmsr(MSR_VMX_BASIC); 2465 pin = vmx_settable(basic, MSR_VMX_PINBASED_CTLS, 2466 MSR_VMX_TRUE_PINBASED_CTLS); 2467 proc = vmx_settable(basic, MSR_VMX_PROCBASED_CTLS, 2468 MSR_VMX_TRUE_PROCBASED_CTLS); 2469 if (proc & PROCBASED_SECONDARY_CONTROLS) 2470 proc2 = vmx_settable(basic, MSR_VMX_PROCBASED_CTLS2, 2471 MSR_VMX_PROCBASED_CTLS2); 2472 else 2473 proc2 = 0; 2474 exit = vmx_settable(basic, MSR_VMX_EXIT_CTLS, MSR_VMX_TRUE_EXIT_CTLS); 2475 entry = vmx_settable(basic, MSR_VMX_ENTRY_CTLS, MSR_VMX_TRUE_ENTRY_CTLS); 2476 2477 if (!bootverbose) { 2478 comma = 0; 2479 if (exit & VM_EXIT_SAVE_PAT && exit & VM_EXIT_LOAD_PAT && 2480 entry & VM_ENTRY_LOAD_PAT) { 2481 printf("%sPAT", comma ? "," : ""); 2482 comma = 1; 2483 } 2484 if (proc & PROCBASED_HLT_EXITING) { 2485 printf("%sHLT", comma ? "," : ""); 2486 comma = 1; 2487 } 2488 if (proc & PROCBASED_MTF) { 2489 printf("%sMTF", comma ? "," : ""); 2490 comma = 1; 2491 } 2492 if (proc & PROCBASED_PAUSE_EXITING) { 2493 printf("%sPAUSE", comma ? "," : ""); 2494 comma = 1; 2495 } 2496 if (proc2 & PROCBASED2_ENABLE_EPT) { 2497 printf("%sEPT", comma ? "," : ""); 2498 comma = 1; 2499 } 2500 if (proc2 & PROCBASED2_UNRESTRICTED_GUEST) { 2501 printf("%sUG", comma ? "," : ""); 2502 comma = 1; 2503 } 2504 if (proc2 & PROCBASED2_ENABLE_VPID) { 2505 printf("%sVPID", comma ? "," : ""); 2506 comma = 1; 2507 } 2508 if (proc & PROCBASED_USE_TPR_SHADOW && 2509 proc2 & PROCBASED2_VIRTUALIZE_APIC_ACCESSES && 2510 proc2 & PROCBASED2_VIRTUALIZE_X2APIC_MODE && 2511 proc2 & PROCBASED2_APIC_REGISTER_VIRTUALIZATION && 2512 proc2 & PROCBASED2_VIRTUAL_INTERRUPT_DELIVERY) { 2513 printf("%sVID", comma ? "," : ""); 2514 comma = 1; 2515 if (pin & PINBASED_POSTED_INTERRUPT) 2516 printf(",PostIntr"); 2517 } 2518 return; 2519 } 2520 2521 mask = basic >> 32; 2522 printf("Basic Features=0x%b", mask, 2523 "\020" 2524 "\02132PA" /* 32-bit physical addresses */ 2525 "\022SMM" /* SMM dual-monitor */ 2526 "\027INS/OUTS" /* VM-exit info for INS and OUTS */ 2527 "\030TRUE" /* TRUE_CTLS MSRs */ 2528 ); 2529 printf("\n Pin-Based Controls=0x%b", pin, 2530 "\020" 2531 "\001ExtINT" /* External-interrupt exiting */ 2532 "\004NMI" /* NMI exiting */ 2533 "\006VNMI" /* Virtual NMIs */ 2534 "\007PreTmr" /* Activate VMX-preemption timer */ 2535 "\010PostIntr" /* Process posted interrupts */ 2536 ); 2537 printf("\n Primary Processor Controls=0x%b", proc, 2538 "\020" 2539 "\003INTWIN" /* Interrupt-window exiting */ 2540 "\004TSCOff" /* Use TSC offsetting */ 2541 "\010HLT" /* HLT exiting */ 2542 "\012INVLPG" /* INVLPG exiting */ 2543 "\013MWAIT" /* MWAIT exiting */ 2544 "\014RDPMC" /* RDPMC exiting */ 2545 "\015RDTSC" /* RDTSC exiting */ 2546 "\020CR3-LD" /* CR3-load exiting */ 2547 "\021CR3-ST" /* CR3-store exiting */ 2548 "\024CR8-LD" /* CR8-load exiting */ 2549 "\025CR8-ST" /* CR8-store exiting */ 2550 "\026TPR" /* Use TPR shadow */ 2551 "\027NMIWIN" /* NMI-window exiting */ 2552 "\030MOV-DR" /* MOV-DR exiting */ 2553 "\031IO" /* Unconditional I/O exiting */ 2554 "\032IOmap" /* Use I/O bitmaps */ 2555 "\034MTF" /* Monitor trap flag */ 2556 "\035MSRmap" /* Use MSR bitmaps */ 2557 "\036MONITOR" /* MONITOR exiting */ 2558 "\037PAUSE" /* PAUSE exiting */ 2559 ); 2560 if (proc & PROCBASED_SECONDARY_CONTROLS) 2561 printf("\n Secondary Processor Controls=0x%b", proc2, 2562 "\020" 2563 "\001APIC" /* Virtualize APIC accesses */ 2564 "\002EPT" /* Enable EPT */ 2565 "\003DT" /* Descriptor-table exiting */ 2566 "\004RDTSCP" /* Enable RDTSCP */ 2567 "\005x2APIC" /* Virtualize x2APIC mode */ 2568 "\006VPID" /* Enable VPID */ 2569 "\007WBINVD" /* WBINVD exiting */ 2570 "\010UG" /* Unrestricted guest */ 2571 "\011APIC-reg" /* APIC-register virtualization */ 2572 "\012VID" /* Virtual-interrupt delivery */ 2573 "\013PAUSE-loop" /* PAUSE-loop exiting */ 2574 "\014RDRAND" /* RDRAND exiting */ 2575 "\015INVPCID" /* Enable INVPCID */ 2576 "\016VMFUNC" /* Enable VM functions */ 2577 "\017VMCS" /* VMCS shadowing */ 2578 "\020EPT#VE" /* EPT-violation #VE */ 2579 "\021XSAVES" /* Enable XSAVES/XRSTORS */ 2580 ); 2581 printf("\n Exit Controls=0x%b", mask, 2582 "\020" 2583 "\003DR" /* Save debug controls */ 2584 /* Ignore Host address-space size */ 2585 "\015PERF" /* Load MSR_PERF_GLOBAL_CTRL */ 2586 "\020AckInt" /* Acknowledge interrupt on exit */ 2587 "\023PAT-SV" /* Save MSR_PAT */ 2588 "\024PAT-LD" /* Load MSR_PAT */ 2589 "\025EFER-SV" /* Save MSR_EFER */ 2590 "\026EFER-LD" /* Load MSR_EFER */ 2591 "\027PTMR-SV" /* Save VMX-preemption timer value */ 2592 ); 2593 printf("\n Entry Controls=0x%b", mask, 2594 "\020" 2595 "\003DR" /* Save debug controls */ 2596 /* Ignore IA-32e mode guest */ 2597 /* Ignore Entry to SMM */ 2598 /* Ignore Deactivate dual-monitor treatment */ 2599 "\016PERF" /* Load MSR_PERF_GLOBAL_CTRL */ 2600 "\017PAT" /* Load MSR_PAT */ 2601 "\020EFER" /* Load MSR_EFER */ 2602 ); 2603 if (proc & PROCBASED_SECONDARY_CONTROLS && 2604 (proc2 & (PROCBASED2_ENABLE_EPT | PROCBASED2_ENABLE_VPID)) != 0) { 2605 msr = rdmsr(MSR_VMX_EPT_VPID_CAP); 2606 mask = msr; 2607 printf("\n EPT Features=0x%b", mask, 2608 "\020" 2609 "\001XO" /* Execute-only translations */ 2610 "\007PW4" /* Page-walk length of 4 */ 2611 "\011UC" /* EPT paging-structure mem can be UC */ 2612 "\017WB" /* EPT paging-structure mem can be WB */ 2613 "\0212M" /* EPT PDE can map a 2-Mbyte page */ 2614 "\0221G" /* EPT PDPTE can map a 1-Gbyte page */ 2615 "\025INVEPT" /* INVEPT is supported */ 2616 "\026AD" /* Accessed and dirty flags for EPT */ 2617 "\032single" /* INVEPT single-context type */ 2618 "\033all" /* INVEPT all-context type */ 2619 ); 2620 mask = msr >> 32; 2621 printf("\n VPID Features=0x%b", mask, 2622 "\020" 2623 "\001INVVPID" /* INVVPID is supported */ 2624 "\011individual" /* INVVPID individual-address type */ 2625 "\012single" /* INVVPID single-context type */ 2626 "\013all" /* INVVPID all-context type */ 2627 /* INVVPID single-context-retaining-globals type */ 2628 "\014single-globals" 2629 ); 2630 } 2631 } 2632 2633 static void 2634 print_hypervisor_info(void) 2635 { 2636 2637 if (*hv_vendor != '\0') 2638 printf("Hypervisor: Origin = \"%s\"\n", hv_vendor); 2639 } 2640 2641 /* 2642 * Returns the maximum physical address that can be used with the 2643 * current system. 2644 */ 2645 vm_paddr_t 2646 cpu_getmaxphyaddr(void) 2647 { 2648 2649 #if defined(__i386__) 2650 if (!pae_mode) 2651 return (0xffffffff); 2652 #endif 2653 return ((1ULL << cpu_maxphyaddr) - 1); 2654 } 2655