1 /*- 2 * Copyright (c) 1992 Terrence R. Lambert. 3 * Copyright (c) 1982, 1987, 1990 The Regents of the University of California. 4 * Copyright (c) 1997 KATO Takenori. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to Berkeley by 8 * William Jolitz. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by the University of 21 * California, Berkeley and its contributors. 22 * 4. Neither the name of the University nor the names of its contributors 23 * may be used to endorse or promote products derived from this software 24 * without specific prior written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 27 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 28 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 29 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 30 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 31 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 32 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 33 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 34 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 35 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 36 * SUCH DAMAGE. 37 * 38 * from: Id: machdep.c,v 1.193 1996/06/18 01:22:04 bde Exp 39 */ 40 41 #include <sys/cdefs.h> 42 __FBSDID("$FreeBSD$"); 43 44 #include "opt_cpu.h" 45 46 #include <sys/param.h> 47 #include <sys/bus.h> 48 #include <sys/cpu.h> 49 #include <sys/eventhandler.h> 50 #include <sys/limits.h> 51 #include <sys/systm.h> 52 #include <sys/kernel.h> 53 #include <sys/sysctl.h> 54 #include <sys/power.h> 55 56 #include <vm/vm.h> 57 #include <vm/pmap.h> 58 59 #include <machine/asmacros.h> 60 #include <machine/clock.h> 61 #include <machine/cputypes.h> 62 #include <machine/frame.h> 63 #include <machine/intr_machdep.h> 64 #include <machine/md_var.h> 65 #include <machine/segments.h> 66 #include <machine/specialreg.h> 67 68 #include <amd64/vmm/intel/vmx_controls.h> 69 #include <x86/isa/icu.h> 70 #include <x86/vmware.h> 71 72 #ifdef __i386__ 73 #define IDENTBLUE_CYRIX486 0 74 #define IDENTBLUE_IBMCPU 1 75 #define IDENTBLUE_CYRIXM2 2 76 77 static void identifycyrix(void); 78 static void print_transmeta_info(void); 79 #endif 80 static u_int find_cpu_vendor_id(void); 81 static void print_AMD_info(void); 82 static void print_INTEL_info(void); 83 static void print_INTEL_TLB(u_int data); 84 static void print_hypervisor_info(void); 85 static void print_svm_info(void); 86 static void print_via_padlock_info(void); 87 static void print_vmx_info(void); 88 89 #ifdef __i386__ 90 int cpu; /* Are we 386, 386sx, 486, etc? */ 91 int cpu_class; 92 #endif 93 u_int cpu_feature; /* Feature flags */ 94 u_int cpu_feature2; /* Feature flags */ 95 u_int amd_feature; /* AMD feature flags */ 96 u_int amd_feature2; /* AMD feature flags */ 97 u_int amd_rascap; /* AMD RAS capabilities */ 98 u_int amd_pminfo; /* AMD advanced power management info */ 99 u_int amd_extended_feature_extensions; 100 u_int via_feature_rng; /* VIA RNG features */ 101 u_int via_feature_xcrypt; /* VIA ACE features */ 102 u_int cpu_high; /* Highest arg to CPUID */ 103 u_int cpu_exthigh; /* Highest arg to extended CPUID */ 104 u_int cpu_id; /* Stepping ID */ 105 u_int cpu_procinfo; /* HyperThreading Info / Brand Index / CLFUSH */ 106 u_int cpu_procinfo2; /* Multicore info */ 107 char cpu_vendor[20]; /* CPU Origin code */ 108 u_int cpu_vendor_id; /* CPU vendor ID */ 109 u_int cpu_mxcsr_mask; /* Valid bits in mxcsr */ 110 u_int cpu_clflush_line_size = 32; 111 u_int cpu_stdext_feature; /* %ebx */ 112 u_int cpu_stdext_feature2; /* %ecx */ 113 u_int cpu_stdext_feature3; /* %edx */ 114 uint64_t cpu_ia32_arch_caps; 115 u_int cpu_max_ext_state_size; 116 u_int cpu_mon_mwait_flags; /* MONITOR/MWAIT flags (CPUID.05H.ECX) */ 117 u_int cpu_mon_min_size; /* MONITOR minimum range size, bytes */ 118 u_int cpu_mon_max_size; /* MONITOR minimum range size, bytes */ 119 u_int cpu_maxphyaddr; /* Max phys addr width in bits */ 120 u_int cpu_power_eax; /* 06H: Power management leaf, %eax */ 121 u_int cpu_power_ebx; /* 06H: Power management leaf, %ebx */ 122 u_int cpu_power_ecx; /* 06H: Power management leaf, %ecx */ 123 u_int cpu_power_edx; /* 06H: Power management leaf, %edx */ 124 char machine[] = MACHINE; 125 126 SYSCTL_UINT(_hw, OID_AUTO, via_feature_rng, CTLFLAG_RD, 127 &via_feature_rng, 0, 128 "VIA RNG feature available in CPU"); 129 SYSCTL_UINT(_hw, OID_AUTO, via_feature_xcrypt, CTLFLAG_RD, 130 &via_feature_xcrypt, 0, 131 "VIA xcrypt feature available in CPU"); 132 133 #ifdef __amd64__ 134 #ifdef SCTL_MASK32 135 extern int adaptive_machine_arch; 136 #endif 137 138 static int 139 sysctl_hw_machine(SYSCTL_HANDLER_ARGS) 140 { 141 #ifdef SCTL_MASK32 142 static const char machine32[] = "i386"; 143 #endif 144 int error; 145 146 #ifdef SCTL_MASK32 147 if ((req->flags & SCTL_MASK32) != 0 && adaptive_machine_arch) 148 error = SYSCTL_OUT(req, machine32, sizeof(machine32)); 149 else 150 #endif 151 error = SYSCTL_OUT(req, machine, sizeof(machine)); 152 return (error); 153 154 } 155 SYSCTL_PROC(_hw, HW_MACHINE, machine, CTLTYPE_STRING | CTLFLAG_RD | 156 CTLFLAG_CAPRD | CTLFLAG_MPSAFE, NULL, 0, sysctl_hw_machine, "A", "Machine class"); 157 #else 158 SYSCTL_STRING(_hw, HW_MACHINE, machine, CTLFLAG_RD | CTLFLAG_CAPRD, 159 machine, 0, "Machine class"); 160 #endif 161 162 static char cpu_model[128]; 163 SYSCTL_STRING(_hw, HW_MODEL, model, CTLFLAG_RD | CTLFLAG_MPSAFE, 164 cpu_model, 0, "Machine model"); 165 166 static int hw_clockrate; 167 SYSCTL_INT(_hw, OID_AUTO, clockrate, CTLFLAG_RD, 168 &hw_clockrate, 0, "CPU instruction clock rate"); 169 170 u_int hv_base; 171 u_int hv_high; 172 char hv_vendor[16]; 173 SYSCTL_STRING(_hw, OID_AUTO, hv_vendor, CTLFLAG_RD | CTLFLAG_MPSAFE, hv_vendor, 174 0, "Hypervisor vendor"); 175 176 static eventhandler_tag tsc_post_tag; 177 178 static char cpu_brand[48]; 179 180 #ifdef __i386__ 181 #define MAX_BRAND_INDEX 8 182 183 static const char *cpu_brandtable[MAX_BRAND_INDEX + 1] = { 184 NULL, /* No brand */ 185 "Intel Celeron", 186 "Intel Pentium III", 187 "Intel Pentium III Xeon", 188 NULL, 189 NULL, 190 NULL, 191 NULL, 192 "Intel Pentium 4" 193 }; 194 195 static struct { 196 char *cpu_name; 197 int cpu_class; 198 } cpus[] = { 199 { "Intel 80286", CPUCLASS_286 }, /* CPU_286 */ 200 { "i386SX", CPUCLASS_386 }, /* CPU_386SX */ 201 { "i386DX", CPUCLASS_386 }, /* CPU_386 */ 202 { "i486SX", CPUCLASS_486 }, /* CPU_486SX */ 203 { "i486DX", CPUCLASS_486 }, /* CPU_486 */ 204 { "Pentium", CPUCLASS_586 }, /* CPU_586 */ 205 { "Cyrix 486", CPUCLASS_486 }, /* CPU_486DLC */ 206 { "Pentium Pro", CPUCLASS_686 }, /* CPU_686 */ 207 { "Cyrix 5x86", CPUCLASS_486 }, /* CPU_M1SC */ 208 { "Cyrix 6x86", CPUCLASS_486 }, /* CPU_M1 */ 209 { "Blue Lightning", CPUCLASS_486 }, /* CPU_BLUE */ 210 { "Cyrix 6x86MX", CPUCLASS_686 }, /* CPU_M2 */ 211 { "NexGen 586", CPUCLASS_386 }, /* CPU_NX586 (XXX) */ 212 { "Cyrix 486S/DX", CPUCLASS_486 }, /* CPU_CY486DX */ 213 { "Pentium II", CPUCLASS_686 }, /* CPU_PII */ 214 { "Pentium III", CPUCLASS_686 }, /* CPU_PIII */ 215 { "Pentium 4", CPUCLASS_686 }, /* CPU_P4 */ 216 }; 217 #endif 218 219 static struct { 220 char *vendor; 221 u_int vendor_id; 222 } cpu_vendors[] = { 223 { INTEL_VENDOR_ID, CPU_VENDOR_INTEL }, /* GenuineIntel */ 224 { AMD_VENDOR_ID, CPU_VENDOR_AMD }, /* AuthenticAMD */ 225 { HYGON_VENDOR_ID, CPU_VENDOR_HYGON }, /* HygonGenuine */ 226 { CENTAUR_VENDOR_ID, CPU_VENDOR_CENTAUR }, /* CentaurHauls */ 227 #ifdef __i386__ 228 { NSC_VENDOR_ID, CPU_VENDOR_NSC }, /* Geode by NSC */ 229 { CYRIX_VENDOR_ID, CPU_VENDOR_CYRIX }, /* CyrixInstead */ 230 { TRANSMETA_VENDOR_ID, CPU_VENDOR_TRANSMETA }, /* GenuineTMx86 */ 231 { SIS_VENDOR_ID, CPU_VENDOR_SIS }, /* SiS SiS SiS */ 232 { UMC_VENDOR_ID, CPU_VENDOR_UMC }, /* UMC UMC UMC */ 233 { NEXGEN_VENDOR_ID, CPU_VENDOR_NEXGEN }, /* NexGenDriven */ 234 { RISE_VENDOR_ID, CPU_VENDOR_RISE }, /* RiseRiseRise */ 235 #if 0 236 /* XXX CPUID 8000_0000h and 8086_0000h, not 0000_0000h */ 237 { "TransmetaCPU", CPU_VENDOR_TRANSMETA }, 238 #endif 239 #endif 240 }; 241 242 void 243 printcpuinfo(void) 244 { 245 u_int regs[4], i; 246 char *brand; 247 248 printf("CPU: "); 249 #ifdef __i386__ 250 cpu_class = cpus[cpu].cpu_class; 251 strncpy(cpu_model, cpus[cpu].cpu_name, sizeof (cpu_model)); 252 #else 253 strncpy(cpu_model, "Hammer", sizeof (cpu_model)); 254 #endif 255 256 /* Check for extended CPUID information and a processor name. */ 257 if (cpu_exthigh >= 0x80000004) { 258 brand = cpu_brand; 259 for (i = 0x80000002; i < 0x80000005; i++) { 260 do_cpuid(i, regs); 261 memcpy(brand, regs, sizeof(regs)); 262 brand += sizeof(regs); 263 } 264 } 265 266 switch (cpu_vendor_id) { 267 case CPU_VENDOR_INTEL: 268 #ifdef __i386__ 269 if ((cpu_id & 0xf00) > 0x300) { 270 u_int brand_index; 271 272 cpu_model[0] = '\0'; 273 274 switch (cpu_id & 0x3000) { 275 case 0x1000: 276 strcpy(cpu_model, "Overdrive "); 277 break; 278 case 0x2000: 279 strcpy(cpu_model, "Dual "); 280 break; 281 } 282 283 switch (cpu_id & 0xf00) { 284 case 0x400: 285 strcat(cpu_model, "i486 "); 286 /* Check the particular flavor of 486 */ 287 switch (cpu_id & 0xf0) { 288 case 0x00: 289 case 0x10: 290 strcat(cpu_model, "DX"); 291 break; 292 case 0x20: 293 strcat(cpu_model, "SX"); 294 break; 295 case 0x30: 296 strcat(cpu_model, "DX2"); 297 break; 298 case 0x40: 299 strcat(cpu_model, "SL"); 300 break; 301 case 0x50: 302 strcat(cpu_model, "SX2"); 303 break; 304 case 0x70: 305 strcat(cpu_model, 306 "DX2 Write-Back Enhanced"); 307 break; 308 case 0x80: 309 strcat(cpu_model, "DX4"); 310 break; 311 } 312 break; 313 case 0x500: 314 /* Check the particular flavor of 586 */ 315 strcat(cpu_model, "Pentium"); 316 switch (cpu_id & 0xf0) { 317 case 0x00: 318 strcat(cpu_model, " A-step"); 319 break; 320 case 0x10: 321 strcat(cpu_model, "/P5"); 322 break; 323 case 0x20: 324 strcat(cpu_model, "/P54C"); 325 break; 326 case 0x30: 327 strcat(cpu_model, "/P24T"); 328 break; 329 case 0x40: 330 strcat(cpu_model, "/P55C"); 331 break; 332 case 0x70: 333 strcat(cpu_model, "/P54C"); 334 break; 335 case 0x80: 336 strcat(cpu_model, "/P55C (quarter-micron)"); 337 break; 338 default: 339 /* nothing */ 340 break; 341 } 342 #if defined(I586_CPU) && !defined(NO_F00F_HACK) 343 /* 344 * XXX - If/when Intel fixes the bug, this 345 * should also check the version of the 346 * CPU, not just that it's a Pentium. 347 */ 348 has_f00f_bug = 1; 349 #endif 350 break; 351 case 0x600: 352 /* Check the particular flavor of 686 */ 353 switch (cpu_id & 0xf0) { 354 case 0x00: 355 strcat(cpu_model, "Pentium Pro A-step"); 356 break; 357 case 0x10: 358 strcat(cpu_model, "Pentium Pro"); 359 break; 360 case 0x30: 361 case 0x50: 362 case 0x60: 363 strcat(cpu_model, 364 "Pentium II/Pentium II Xeon/Celeron"); 365 cpu = CPU_PII; 366 break; 367 case 0x70: 368 case 0x80: 369 case 0xa0: 370 case 0xb0: 371 strcat(cpu_model, 372 "Pentium III/Pentium III Xeon/Celeron"); 373 cpu = CPU_PIII; 374 break; 375 default: 376 strcat(cpu_model, "Unknown 80686"); 377 break; 378 } 379 break; 380 case 0xf00: 381 strcat(cpu_model, "Pentium 4"); 382 cpu = CPU_P4; 383 break; 384 default: 385 strcat(cpu_model, "unknown"); 386 break; 387 } 388 389 /* 390 * If we didn't get a brand name from the extended 391 * CPUID, try to look it up in the brand table. 392 */ 393 if (cpu_high > 0 && *cpu_brand == '\0') { 394 brand_index = cpu_procinfo & CPUID_BRAND_INDEX; 395 if (brand_index <= MAX_BRAND_INDEX && 396 cpu_brandtable[brand_index] != NULL) 397 strcpy(cpu_brand, 398 cpu_brandtable[brand_index]); 399 } 400 } 401 #else 402 /* Please make up your mind folks! */ 403 strcat(cpu_model, "EM64T"); 404 #endif 405 break; 406 case CPU_VENDOR_AMD: 407 /* 408 * Values taken from AMD Processor Recognition 409 * http://www.amd.com/K6/k6docs/pdf/20734g.pdf 410 * (also describes ``Features'' encodings. 411 */ 412 strcpy(cpu_model, "AMD "); 413 #ifdef __i386__ 414 switch (cpu_id & 0xFF0) { 415 case 0x410: 416 strcat(cpu_model, "Standard Am486DX"); 417 break; 418 case 0x430: 419 strcat(cpu_model, "Enhanced Am486DX2 Write-Through"); 420 break; 421 case 0x470: 422 strcat(cpu_model, "Enhanced Am486DX2 Write-Back"); 423 break; 424 case 0x480: 425 strcat(cpu_model, "Enhanced Am486DX4/Am5x86 Write-Through"); 426 break; 427 case 0x490: 428 strcat(cpu_model, "Enhanced Am486DX4/Am5x86 Write-Back"); 429 break; 430 case 0x4E0: 431 strcat(cpu_model, "Am5x86 Write-Through"); 432 break; 433 case 0x4F0: 434 strcat(cpu_model, "Am5x86 Write-Back"); 435 break; 436 case 0x500: 437 strcat(cpu_model, "K5 model 0"); 438 break; 439 case 0x510: 440 strcat(cpu_model, "K5 model 1"); 441 break; 442 case 0x520: 443 strcat(cpu_model, "K5 PR166 (model 2)"); 444 break; 445 case 0x530: 446 strcat(cpu_model, "K5 PR200 (model 3)"); 447 break; 448 case 0x560: 449 strcat(cpu_model, "K6"); 450 break; 451 case 0x570: 452 strcat(cpu_model, "K6 266 (model 1)"); 453 break; 454 case 0x580: 455 strcat(cpu_model, "K6-2"); 456 break; 457 case 0x590: 458 strcat(cpu_model, "K6-III"); 459 break; 460 case 0x5a0: 461 strcat(cpu_model, "Geode LX"); 462 break; 463 default: 464 strcat(cpu_model, "Unknown"); 465 break; 466 } 467 #else 468 if ((cpu_id & 0xf00) == 0xf00) 469 strcat(cpu_model, "AMD64 Processor"); 470 else 471 strcat(cpu_model, "Unknown"); 472 #endif 473 break; 474 #ifdef __i386__ 475 case CPU_VENDOR_CYRIX: 476 strcpy(cpu_model, "Cyrix "); 477 switch (cpu_id & 0xff0) { 478 case 0x440: 479 strcat(cpu_model, "MediaGX"); 480 break; 481 case 0x520: 482 strcat(cpu_model, "6x86"); 483 break; 484 case 0x540: 485 cpu_class = CPUCLASS_586; 486 strcat(cpu_model, "GXm"); 487 break; 488 case 0x600: 489 strcat(cpu_model, "6x86MX"); 490 break; 491 default: 492 /* 493 * Even though CPU supports the cpuid 494 * instruction, it can be disabled. 495 * Therefore, this routine supports all Cyrix 496 * CPUs. 497 */ 498 switch (cyrix_did & 0xf0) { 499 case 0x00: 500 switch (cyrix_did & 0x0f) { 501 case 0x00: 502 strcat(cpu_model, "486SLC"); 503 break; 504 case 0x01: 505 strcat(cpu_model, "486DLC"); 506 break; 507 case 0x02: 508 strcat(cpu_model, "486SLC2"); 509 break; 510 case 0x03: 511 strcat(cpu_model, "486DLC2"); 512 break; 513 case 0x04: 514 strcat(cpu_model, "486SRx"); 515 break; 516 case 0x05: 517 strcat(cpu_model, "486DRx"); 518 break; 519 case 0x06: 520 strcat(cpu_model, "486SRx2"); 521 break; 522 case 0x07: 523 strcat(cpu_model, "486DRx2"); 524 break; 525 case 0x08: 526 strcat(cpu_model, "486SRu"); 527 break; 528 case 0x09: 529 strcat(cpu_model, "486DRu"); 530 break; 531 case 0x0a: 532 strcat(cpu_model, "486SRu2"); 533 break; 534 case 0x0b: 535 strcat(cpu_model, "486DRu2"); 536 break; 537 default: 538 strcat(cpu_model, "Unknown"); 539 break; 540 } 541 break; 542 case 0x10: 543 switch (cyrix_did & 0x0f) { 544 case 0x00: 545 strcat(cpu_model, "486S"); 546 break; 547 case 0x01: 548 strcat(cpu_model, "486S2"); 549 break; 550 case 0x02: 551 strcat(cpu_model, "486Se"); 552 break; 553 case 0x03: 554 strcat(cpu_model, "486S2e"); 555 break; 556 case 0x0a: 557 strcat(cpu_model, "486DX"); 558 break; 559 case 0x0b: 560 strcat(cpu_model, "486DX2"); 561 break; 562 case 0x0f: 563 strcat(cpu_model, "486DX4"); 564 break; 565 default: 566 strcat(cpu_model, "Unknown"); 567 break; 568 } 569 break; 570 case 0x20: 571 if ((cyrix_did & 0x0f) < 8) 572 strcat(cpu_model, "6x86"); /* Where did you get it? */ 573 else 574 strcat(cpu_model, "5x86"); 575 break; 576 case 0x30: 577 strcat(cpu_model, "6x86"); 578 break; 579 case 0x40: 580 if ((cyrix_did & 0xf000) == 0x3000) { 581 cpu_class = CPUCLASS_586; 582 strcat(cpu_model, "GXm"); 583 } else 584 strcat(cpu_model, "MediaGX"); 585 break; 586 case 0x50: 587 strcat(cpu_model, "6x86MX"); 588 break; 589 case 0xf0: 590 switch (cyrix_did & 0x0f) { 591 case 0x0d: 592 strcat(cpu_model, "Overdrive CPU"); 593 break; 594 case 0x0e: 595 strcpy(cpu_model, "Texas Instruments 486SXL"); 596 break; 597 case 0x0f: 598 strcat(cpu_model, "486SLC/DLC"); 599 break; 600 default: 601 strcat(cpu_model, "Unknown"); 602 break; 603 } 604 break; 605 default: 606 strcat(cpu_model, "Unknown"); 607 break; 608 } 609 break; 610 } 611 break; 612 case CPU_VENDOR_RISE: 613 strcpy(cpu_model, "Rise "); 614 switch (cpu_id & 0xff0) { 615 case 0x500: /* 6401 and 6441 (Kirin) */ 616 case 0x520: /* 6510 (Lynx) */ 617 strcat(cpu_model, "mP6"); 618 break; 619 default: 620 strcat(cpu_model, "Unknown"); 621 } 622 break; 623 #endif 624 case CPU_VENDOR_CENTAUR: 625 #ifdef __i386__ 626 switch (cpu_id & 0xff0) { 627 case 0x540: 628 strcpy(cpu_model, "IDT WinChip C6"); 629 break; 630 case 0x580: 631 strcpy(cpu_model, "IDT WinChip 2"); 632 break; 633 case 0x590: 634 strcpy(cpu_model, "IDT WinChip 3"); 635 break; 636 case 0x660: 637 strcpy(cpu_model, "VIA C3 Samuel"); 638 break; 639 case 0x670: 640 if (cpu_id & 0x8) 641 strcpy(cpu_model, "VIA C3 Ezra"); 642 else 643 strcpy(cpu_model, "VIA C3 Samuel 2"); 644 break; 645 case 0x680: 646 strcpy(cpu_model, "VIA C3 Ezra-T"); 647 break; 648 case 0x690: 649 strcpy(cpu_model, "VIA C3 Nehemiah"); 650 break; 651 case 0x6a0: 652 case 0x6d0: 653 strcpy(cpu_model, "VIA C7 Esther"); 654 break; 655 case 0x6f0: 656 strcpy(cpu_model, "VIA Nano"); 657 break; 658 default: 659 strcpy(cpu_model, "VIA/IDT Unknown"); 660 } 661 #else 662 strcpy(cpu_model, "VIA "); 663 if ((cpu_id & 0xff0) == 0x6f0) 664 strcat(cpu_model, "Nano Processor"); 665 else 666 strcat(cpu_model, "Unknown"); 667 #endif 668 break; 669 #ifdef __i386__ 670 case CPU_VENDOR_IBM: 671 strcpy(cpu_model, "Blue Lightning CPU"); 672 break; 673 case CPU_VENDOR_NSC: 674 switch (cpu_id & 0xff0) { 675 case 0x540: 676 strcpy(cpu_model, "Geode SC1100"); 677 cpu = CPU_GEODE1100; 678 break; 679 default: 680 strcpy(cpu_model, "Geode/NSC unknown"); 681 break; 682 } 683 break; 684 #endif 685 case CPU_VENDOR_HYGON: 686 strcpy(cpu_model, "Hygon "); 687 #ifdef __i386__ 688 strcat(cpu_model, "Unknown"); 689 #else 690 if ((cpu_id & 0xf00) == 0xf00) 691 strcat(cpu_model, "AMD64 Processor"); 692 else 693 strcat(cpu_model, "Unknown"); 694 #endif 695 break; 696 697 default: 698 strcat(cpu_model, "Unknown"); 699 break; 700 } 701 702 /* 703 * Replace cpu_model with cpu_brand minus leading spaces if 704 * we have one. 705 */ 706 brand = cpu_brand; 707 while (*brand == ' ') 708 ++brand; 709 if (*brand != '\0') 710 strcpy(cpu_model, brand); 711 712 printf("%s (", cpu_model); 713 if (tsc_freq != 0) { 714 hw_clockrate = (tsc_freq + 5000) / 1000000; 715 printf("%jd.%02d-MHz ", 716 (intmax_t)(tsc_freq + 4999) / 1000000, 717 (u_int)((tsc_freq + 4999) / 10000) % 100); 718 } 719 #ifdef __i386__ 720 switch(cpu_class) { 721 case CPUCLASS_286: 722 printf("286"); 723 break; 724 case CPUCLASS_386: 725 printf("386"); 726 break; 727 #if defined(I486_CPU) 728 case CPUCLASS_486: 729 printf("486"); 730 break; 731 #endif 732 #if defined(I586_CPU) 733 case CPUCLASS_586: 734 printf("586"); 735 break; 736 #endif 737 #if defined(I686_CPU) 738 case CPUCLASS_686: 739 printf("686"); 740 break; 741 #endif 742 default: 743 printf("Unknown"); /* will panic below... */ 744 } 745 #else 746 printf("K8"); 747 #endif 748 printf("-class CPU)\n"); 749 if (*cpu_vendor) 750 printf(" Origin=\"%s\"", cpu_vendor); 751 if (cpu_id) 752 printf(" Id=0x%x", cpu_id); 753 754 if (cpu_vendor_id == CPU_VENDOR_INTEL || 755 cpu_vendor_id == CPU_VENDOR_AMD || 756 cpu_vendor_id == CPU_VENDOR_HYGON || 757 cpu_vendor_id == CPU_VENDOR_CENTAUR || 758 #ifdef __i386__ 759 cpu_vendor_id == CPU_VENDOR_TRANSMETA || 760 cpu_vendor_id == CPU_VENDOR_RISE || 761 cpu_vendor_id == CPU_VENDOR_NSC || 762 (cpu_vendor_id == CPU_VENDOR_CYRIX && ((cpu_id & 0xf00) > 0x500)) || 763 #endif 764 0) { 765 printf(" Family=0x%x", CPUID_TO_FAMILY(cpu_id)); 766 printf(" Model=0x%x", CPUID_TO_MODEL(cpu_id)); 767 printf(" Stepping=%u", cpu_id & CPUID_STEPPING); 768 #ifdef __i386__ 769 if (cpu_vendor_id == CPU_VENDOR_CYRIX) 770 printf("\n DIR=0x%04x", cyrix_did); 771 #endif 772 773 /* 774 * AMD CPUID Specification 775 * http://support.amd.com/us/Embedded_TechDocs/25481.pdf 776 * 777 * Intel Processor Identification and CPUID Instruction 778 * http://www.intel.com/assets/pdf/appnote/241618.pdf 779 */ 780 if (cpu_high > 0) { 781 /* 782 * Here we should probably set up flags indicating 783 * whether or not various features are available. 784 * The interesting ones are probably VME, PSE, PAE, 785 * and PGE. The code already assumes without bothering 786 * to check that all CPUs >= Pentium have a TSC and 787 * MSRs. 788 */ 789 printf("\n Features=0x%b", cpu_feature, 790 "\020" 791 "\001FPU" /* Integral FPU */ 792 "\002VME" /* Extended VM86 mode support */ 793 "\003DE" /* Debugging Extensions (CR4.DE) */ 794 "\004PSE" /* 4MByte page tables */ 795 "\005TSC" /* Timestamp counter */ 796 "\006MSR" /* Machine specific registers */ 797 "\007PAE" /* Physical address extension */ 798 "\010MCE" /* Machine Check support */ 799 "\011CX8" /* CMPEXCH8 instruction */ 800 "\012APIC" /* SMP local APIC */ 801 "\013oldMTRR" /* Previous implementation of MTRR */ 802 "\014SEP" /* Fast System Call */ 803 "\015MTRR" /* Memory Type Range Registers */ 804 "\016PGE" /* PG_G (global bit) support */ 805 "\017MCA" /* Machine Check Architecture */ 806 "\020CMOV" /* CMOV instruction */ 807 "\021PAT" /* Page attributes table */ 808 "\022PSE36" /* 36 bit address space support */ 809 "\023PN" /* Processor Serial number */ 810 "\024CLFLUSH" /* Has the CLFLUSH instruction */ 811 "\025<b20>" 812 "\026DTS" /* Debug Trace Store */ 813 "\027ACPI" /* ACPI support */ 814 "\030MMX" /* MMX instructions */ 815 "\031FXSR" /* FXSAVE/FXRSTOR */ 816 "\032SSE" /* Streaming SIMD Extensions */ 817 "\033SSE2" /* Streaming SIMD Extensions #2 */ 818 "\034SS" /* Self snoop */ 819 "\035HTT" /* Hyperthreading (see EBX bit 16-23) */ 820 "\036TM" /* Thermal Monitor clock slowdown */ 821 "\037IA64" /* CPU can execute IA64 instructions */ 822 "\040PBE" /* Pending Break Enable */ 823 ); 824 825 if (cpu_feature2 != 0) { 826 printf("\n Features2=0x%b", cpu_feature2, 827 "\020" 828 "\001SSE3" /* SSE3 */ 829 "\002PCLMULQDQ" /* Carry-Less Mul Quadword */ 830 "\003DTES64" /* 64-bit Debug Trace */ 831 "\004MON" /* MONITOR/MWAIT Instructions */ 832 "\005DS_CPL" /* CPL Qualified Debug Store */ 833 "\006VMX" /* Virtual Machine Extensions */ 834 "\007SMX" /* Safer Mode Extensions */ 835 "\010EST" /* Enhanced SpeedStep */ 836 "\011TM2" /* Thermal Monitor 2 */ 837 "\012SSSE3" /* SSSE3 */ 838 "\013CNXT-ID" /* L1 context ID available */ 839 "\014SDBG" /* IA32 silicon debug */ 840 "\015FMA" /* Fused Multiply Add */ 841 "\016CX16" /* CMPXCHG16B Instruction */ 842 "\017xTPR" /* Send Task Priority Messages*/ 843 "\020PDCM" /* Perf/Debug Capability MSR */ 844 "\021<b16>" 845 "\022PCID" /* Process-context Identifiers*/ 846 "\023DCA" /* Direct Cache Access */ 847 "\024SSE4.1" /* SSE 4.1 */ 848 "\025SSE4.2" /* SSE 4.2 */ 849 "\026x2APIC" /* xAPIC Extensions */ 850 "\027MOVBE" /* MOVBE Instruction */ 851 "\030POPCNT" /* POPCNT Instruction */ 852 "\031TSCDLT" /* TSC-Deadline Timer */ 853 "\032AESNI" /* AES Crypto */ 854 "\033XSAVE" /* XSAVE/XRSTOR States */ 855 "\034OSXSAVE" /* OS-Enabled State Management*/ 856 "\035AVX" /* Advanced Vector Extensions */ 857 "\036F16C" /* Half-precision conversions */ 858 "\037RDRAND" /* RDRAND Instruction */ 859 "\040HV" /* Hypervisor */ 860 ); 861 } 862 863 if (amd_feature != 0) { 864 printf("\n AMD Features=0x%b", amd_feature, 865 "\020" /* in hex */ 866 "\001<s0>" /* Same */ 867 "\002<s1>" /* Same */ 868 "\003<s2>" /* Same */ 869 "\004<s3>" /* Same */ 870 "\005<s4>" /* Same */ 871 "\006<s5>" /* Same */ 872 "\007<s6>" /* Same */ 873 "\010<s7>" /* Same */ 874 "\011<s8>" /* Same */ 875 "\012<s9>" /* Same */ 876 "\013<b10>" /* Undefined */ 877 "\014SYSCALL" /* Have SYSCALL/SYSRET */ 878 "\015<s12>" /* Same */ 879 "\016<s13>" /* Same */ 880 "\017<s14>" /* Same */ 881 "\020<s15>" /* Same */ 882 "\021<s16>" /* Same */ 883 "\022<s17>" /* Same */ 884 "\023<b18>" /* Reserved, unknown */ 885 "\024MP" /* Multiprocessor Capable */ 886 "\025NX" /* Has EFER.NXE, NX */ 887 "\026<b21>" /* Undefined */ 888 "\027MMX+" /* AMD MMX Extensions */ 889 "\030<s23>" /* Same */ 890 "\031<s24>" /* Same */ 891 "\032FFXSR" /* Fast FXSAVE/FXRSTOR */ 892 "\033Page1GB" /* 1-GB large page support */ 893 "\034RDTSCP" /* RDTSCP */ 894 "\035<b28>" /* Undefined */ 895 "\036LM" /* 64 bit long mode */ 896 "\0373DNow!+" /* AMD 3DNow! Extensions */ 897 "\0403DNow!" /* AMD 3DNow! */ 898 ); 899 } 900 901 if (amd_feature2 != 0) { 902 printf("\n AMD Features2=0x%b", amd_feature2, 903 "\020" 904 "\001LAHF" /* LAHF/SAHF in long mode */ 905 "\002CMP" /* CMP legacy */ 906 "\003SVM" /* Secure Virtual Mode */ 907 "\004ExtAPIC" /* Extended APIC register */ 908 "\005CR8" /* CR8 in legacy mode */ 909 "\006ABM" /* LZCNT instruction */ 910 "\007SSE4A" /* SSE4A */ 911 "\010MAS" /* Misaligned SSE mode */ 912 "\011Prefetch" /* 3DNow! Prefetch/PrefetchW */ 913 "\012OSVW" /* OS visible workaround */ 914 "\013IBS" /* Instruction based sampling */ 915 "\014XOP" /* XOP extended instructions */ 916 "\015SKINIT" /* SKINIT/STGI */ 917 "\016WDT" /* Watchdog timer */ 918 "\017<b14>" 919 "\020LWP" /* Lightweight Profiling */ 920 "\021FMA4" /* 4-operand FMA instructions */ 921 "\022TCE" /* Translation Cache Extension */ 922 "\023<b18>" 923 "\024NodeId" /* NodeId MSR support */ 924 "\025<b20>" 925 "\026TBM" /* Trailing Bit Manipulation */ 926 "\027Topology" /* Topology Extensions */ 927 "\030PCXC" /* Core perf count */ 928 "\031PNXC" /* NB perf count */ 929 "\032<b25>" 930 "\033DBE" /* Data Breakpoint extension */ 931 "\034PTSC" /* Performance TSC */ 932 "\035PL2I" /* L2I perf count */ 933 "\036MWAITX" /* MONITORX/MWAITX instructions */ 934 "\037ADMSKX" /* Address mask extension */ 935 "\040<b31>" 936 ); 937 } 938 939 if (cpu_stdext_feature != 0) { 940 printf("\n Structured Extended Features=0x%b", 941 cpu_stdext_feature, 942 "\020" 943 /* RDFSBASE/RDGSBASE/WRFSBASE/WRGSBASE */ 944 "\001FSGSBASE" 945 "\002TSCADJ" 946 "\003SGX" 947 /* Bit Manipulation Instructions */ 948 "\004BMI1" 949 /* Hardware Lock Elision */ 950 "\005HLE" 951 /* Advanced Vector Instructions 2 */ 952 "\006AVX2" 953 /* FDP_EXCPTN_ONLY */ 954 "\007FDPEXC" 955 /* Supervisor Mode Execution Prot. */ 956 "\010SMEP" 957 /* Bit Manipulation Instructions */ 958 "\011BMI2" 959 "\012ERMS" 960 /* Invalidate Processor Context ID */ 961 "\013INVPCID" 962 /* Restricted Transactional Memory */ 963 "\014RTM" 964 "\015PQM" 965 "\016NFPUSG" 966 /* Intel Memory Protection Extensions */ 967 "\017MPX" 968 "\020PQE" 969 /* AVX512 Foundation */ 970 "\021AVX512F" 971 "\022AVX512DQ" 972 /* Enhanced NRBG */ 973 "\023RDSEED" 974 /* ADCX + ADOX */ 975 "\024ADX" 976 /* Supervisor Mode Access Prevention */ 977 "\025SMAP" 978 "\026AVX512IFMA" 979 /* Formerly PCOMMIT */ 980 "\027<b22>" 981 "\030CLFLUSHOPT" 982 "\031CLWB" 983 "\032PROCTRACE" 984 "\033AVX512PF" 985 "\034AVX512ER" 986 "\035AVX512CD" 987 "\036SHA" 988 "\037AVX512BW" 989 "\040AVX512VL" 990 ); 991 } 992 993 if (cpu_stdext_feature2 != 0) { 994 printf("\n Structured Extended Features2=0x%b", 995 cpu_stdext_feature2, 996 "\020" 997 "\001PREFETCHWT1" 998 "\002AVX512VBMI" 999 "\003UMIP" 1000 "\004PKU" 1001 "\005OSPKE" 1002 "\006WAITPKG" 1003 "\007AVX512VBMI2" 1004 "\011GFNI" 1005 "\012VAES" 1006 "\013VPCLMULQDQ" 1007 "\014AVX512VNNI" 1008 "\015AVX512BITALG" 1009 "\016TME" 1010 "\017AVX512VPOPCNTDQ" 1011 "\021LA57" 1012 "\027RDPID" 1013 "\032CLDEMOTE" 1014 "\034MOVDIRI" 1015 "\035MOVDIR64B" 1016 "\036ENQCMD" 1017 "\037SGXLC" 1018 ); 1019 } 1020 1021 if (cpu_stdext_feature3 != 0) { 1022 printf("\n Structured Extended Features3=0x%b", 1023 cpu_stdext_feature3, 1024 "\020" 1025 "\003AVX512_4VNNIW" 1026 "\004AVX512_4FMAPS" 1027 "\005FSRM" 1028 "\011AVX512VP2INTERSECT" 1029 "\012MCUOPT" 1030 "\013MD_CLEAR" 1031 "\016TSXFA" 1032 "\023PCONFIG" 1033 "\025IBT" 1034 "\033IBPB" 1035 "\034STIBP" 1036 "\035L1DFL" 1037 "\036ARCH_CAP" 1038 "\037CORE_CAP" 1039 "\040SSBD" 1040 ); 1041 } 1042 1043 if ((cpu_feature2 & CPUID2_XSAVE) != 0) { 1044 cpuid_count(0xd, 0x1, regs); 1045 if (regs[0] != 0) { 1046 printf("\n XSAVE Features=0x%b", 1047 regs[0], 1048 "\020" 1049 "\001XSAVEOPT" 1050 "\002XSAVEC" 1051 "\003XINUSE" 1052 "\004XSAVES"); 1053 } 1054 } 1055 1056 if (cpu_ia32_arch_caps != 0) { 1057 printf("\n IA32_ARCH_CAPS=0x%b", 1058 (u_int)cpu_ia32_arch_caps, 1059 "\020" 1060 "\001RDCL_NO" 1061 "\002IBRS_ALL" 1062 "\003RSBA" 1063 "\004SKIP_L1DFL_VME" 1064 "\005SSB_NO" 1065 "\006MDS_NO" 1066 "\010TSX_CTRL" 1067 "\011TAA_NO" 1068 ); 1069 } 1070 1071 if (amd_extended_feature_extensions != 0) { 1072 u_int amd_fe_masked; 1073 1074 amd_fe_masked = amd_extended_feature_extensions; 1075 if ((amd_fe_masked & AMDFEID_IBRS) == 0) 1076 amd_fe_masked &= 1077 ~(AMDFEID_IBRS_ALWAYSON | 1078 AMDFEID_PREFER_IBRS); 1079 if ((amd_fe_masked & AMDFEID_STIBP) == 0) 1080 amd_fe_masked &= 1081 ~AMDFEID_STIBP_ALWAYSON; 1082 1083 printf("\n " 1084 "AMD Extended Feature Extensions ID EBX=" 1085 "0x%b", amd_fe_masked, 1086 "\020" 1087 "\001CLZERO" 1088 "\002IRPerf" 1089 "\003XSaveErPtr" 1090 "\005RDPRU" 1091 "\011MCOMMIT" 1092 "\012WBNOINVD" 1093 "\015IBPB" 1094 "\017IBRS" 1095 "\020STIBP" 1096 "\021IBRS_ALWAYSON" 1097 "\022STIBP_ALWAYSON" 1098 "\023PREFER_IBRS" 1099 "\030PPIN" 1100 "\031SSBD" 1101 "\032VIRT_SSBD" 1102 "\033SSB_NO" 1103 ); 1104 } 1105 1106 if (via_feature_rng != 0 || via_feature_xcrypt != 0) 1107 print_via_padlock_info(); 1108 1109 if (cpu_feature2 & CPUID2_VMX) 1110 print_vmx_info(); 1111 1112 if (amd_feature2 & AMDID2_SVM) 1113 print_svm_info(); 1114 1115 if ((cpu_feature & CPUID_HTT) && 1116 (cpu_vendor_id == CPU_VENDOR_AMD || 1117 cpu_vendor_id == CPU_VENDOR_HYGON)) 1118 cpu_feature &= ~CPUID_HTT; 1119 1120 /* 1121 * If this CPU supports P-state invariant TSC then 1122 * mention the capability. 1123 */ 1124 if (tsc_is_invariant) { 1125 printf("\n TSC: P-state invariant"); 1126 if (tsc_perf_stat) 1127 printf(", performance statistics"); 1128 } 1129 } 1130 #ifdef __i386__ 1131 } else if (cpu_vendor_id == CPU_VENDOR_CYRIX) { 1132 printf(" DIR=0x%04x", cyrix_did); 1133 printf(" Stepping=%u", (cyrix_did & 0xf000) >> 12); 1134 printf(" Revision=%u", (cyrix_did & 0x0f00) >> 8); 1135 #ifndef CYRIX_CACHE_REALLY_WORKS 1136 if (cpu == CPU_M1 && (cyrix_did & 0xff00) < 0x1700) 1137 printf("\n CPU cache: write-through mode"); 1138 #endif 1139 #endif 1140 } 1141 1142 /* Avoid ugly blank lines: only print newline when we have to. */ 1143 if (*cpu_vendor || cpu_id) 1144 printf("\n"); 1145 1146 if (bootverbose) { 1147 if (cpu_vendor_id == CPU_VENDOR_AMD || 1148 cpu_vendor_id == CPU_VENDOR_HYGON) 1149 print_AMD_info(); 1150 else if (cpu_vendor_id == CPU_VENDOR_INTEL) 1151 print_INTEL_info(); 1152 #ifdef __i386__ 1153 else if (cpu_vendor_id == CPU_VENDOR_TRANSMETA) 1154 print_transmeta_info(); 1155 #endif 1156 } 1157 1158 print_hypervisor_info(); 1159 } 1160 1161 #ifdef __i386__ 1162 void 1163 panicifcpuunsupported(void) 1164 { 1165 1166 #if !defined(lint) 1167 #if !defined(I486_CPU) && !defined(I586_CPU) && !defined(I686_CPU) 1168 #error This kernel is not configured for one of the supported CPUs 1169 #endif 1170 #else /* lint */ 1171 #endif /* lint */ 1172 /* 1173 * Now that we have told the user what they have, 1174 * let them know if that machine type isn't configured. 1175 */ 1176 switch (cpu_class) { 1177 case CPUCLASS_286: /* a 286 should not make it this far, anyway */ 1178 case CPUCLASS_386: 1179 #if !defined(I486_CPU) 1180 case CPUCLASS_486: 1181 #endif 1182 #if !defined(I586_CPU) 1183 case CPUCLASS_586: 1184 #endif 1185 #if !defined(I686_CPU) 1186 case CPUCLASS_686: 1187 #endif 1188 panic("CPU class not configured"); 1189 default: 1190 break; 1191 } 1192 } 1193 1194 static volatile u_int trap_by_rdmsr; 1195 1196 /* 1197 * Special exception 6 handler. 1198 * The rdmsr instruction generates invalid opcodes fault on 486-class 1199 * Cyrix CPU. Stacked eip register points the rdmsr instruction in the 1200 * function identblue() when this handler is called. Stacked eip should 1201 * be advanced. 1202 */ 1203 inthand_t bluetrap6; 1204 __asm 1205 (" \n\ 1206 .text \n\ 1207 .p2align 2,0x90 \n\ 1208 .type " __XSTRING(CNAME(bluetrap6)) ",@function \n\ 1209 " __XSTRING(CNAME(bluetrap6)) ": \n\ 1210 ss \n\ 1211 movl $0xa8c1d," __XSTRING(CNAME(trap_by_rdmsr)) " \n\ 1212 addl $2, (%esp) /* rdmsr is a 2-byte instruction */ \n\ 1213 iret \n\ 1214 "); 1215 1216 /* 1217 * Special exception 13 handler. 1218 * Accessing non-existent MSR generates general protection fault. 1219 */ 1220 inthand_t bluetrap13; 1221 __asm 1222 (" \n\ 1223 .text \n\ 1224 .p2align 2,0x90 \n\ 1225 .type " __XSTRING(CNAME(bluetrap13)) ",@function \n\ 1226 " __XSTRING(CNAME(bluetrap13)) ": \n\ 1227 ss \n\ 1228 movl $0xa89c4," __XSTRING(CNAME(trap_by_rdmsr)) " \n\ 1229 popl %eax /* discard error code */ \n\ 1230 addl $2, (%esp) /* rdmsr is a 2-byte instruction */ \n\ 1231 iret \n\ 1232 "); 1233 1234 /* 1235 * Distinguish IBM Blue Lightning CPU from Cyrix CPUs that does not 1236 * support cpuid instruction. This function should be called after 1237 * loading interrupt descriptor table register. 1238 * 1239 * I don't like this method that handles fault, but I couldn't get 1240 * information for any other methods. Does blue giant know? 1241 */ 1242 static int 1243 identblue(void) 1244 { 1245 1246 trap_by_rdmsr = 0; 1247 1248 /* 1249 * Cyrix 486-class CPU does not support rdmsr instruction. 1250 * The rdmsr instruction generates invalid opcode fault, and exception 1251 * will be trapped by bluetrap6() on Cyrix 486-class CPU. The 1252 * bluetrap6() set the magic number to trap_by_rdmsr. 1253 */ 1254 setidt(IDT_UD, bluetrap6, SDT_SYS386TGT, SEL_KPL, 1255 GSEL(GCODE_SEL, SEL_KPL)); 1256 1257 /* 1258 * Certain BIOS disables cpuid instruction of Cyrix 6x86MX CPU. 1259 * In this case, rdmsr generates general protection fault, and 1260 * exception will be trapped by bluetrap13(). 1261 */ 1262 setidt(IDT_GP, bluetrap13, SDT_SYS386TGT, SEL_KPL, 1263 GSEL(GCODE_SEL, SEL_KPL)); 1264 1265 rdmsr(0x1002); /* Cyrix CPU generates fault. */ 1266 1267 if (trap_by_rdmsr == 0xa8c1d) 1268 return IDENTBLUE_CYRIX486; 1269 else if (trap_by_rdmsr == 0xa89c4) 1270 return IDENTBLUE_CYRIXM2; 1271 return IDENTBLUE_IBMCPU; 1272 } 1273 1274 /* 1275 * identifycyrix() set lower 16 bits of cyrix_did as follows: 1276 * 1277 * F E D C B A 9 8 7 6 5 4 3 2 1 0 1278 * +-------+-------+---------------+ 1279 * | SID | RID | Device ID | 1280 * | (DIR 1) | (DIR 0) | 1281 * +-------+-------+---------------+ 1282 */ 1283 static void 1284 identifycyrix(void) 1285 { 1286 register_t saveintr; 1287 int ccr2_test = 0, dir_test = 0; 1288 u_char ccr2, ccr3; 1289 1290 saveintr = intr_disable(); 1291 1292 ccr2 = read_cyrix_reg(CCR2); 1293 write_cyrix_reg(CCR2, ccr2 ^ CCR2_LOCK_NW); 1294 read_cyrix_reg(CCR2); 1295 if (read_cyrix_reg(CCR2) != ccr2) 1296 ccr2_test = 1; 1297 write_cyrix_reg(CCR2, ccr2); 1298 1299 ccr3 = read_cyrix_reg(CCR3); 1300 write_cyrix_reg(CCR3, ccr3 ^ CCR3_MAPEN3); 1301 read_cyrix_reg(CCR3); 1302 if (read_cyrix_reg(CCR3) != ccr3) 1303 dir_test = 1; /* CPU supports DIRs. */ 1304 write_cyrix_reg(CCR3, ccr3); 1305 1306 if (dir_test) { 1307 /* Device ID registers are available. */ 1308 cyrix_did = read_cyrix_reg(DIR1) << 8; 1309 cyrix_did += read_cyrix_reg(DIR0); 1310 } else if (ccr2_test) 1311 cyrix_did = 0x0010; /* 486S A-step */ 1312 else 1313 cyrix_did = 0x00ff; /* Old 486SLC/DLC and TI486SXLC/SXL */ 1314 1315 intr_restore(saveintr); 1316 } 1317 #endif 1318 1319 /* Update TSC freq with the value indicated by the caller. */ 1320 static void 1321 tsc_freq_changed(void *arg __unused, const struct cf_level *level, int status) 1322 { 1323 1324 /* If there was an error during the transition, don't do anything. */ 1325 if (status != 0) 1326 return; 1327 1328 /* Total setting for this level gives the new frequency in MHz. */ 1329 hw_clockrate = level->total_set.freq; 1330 } 1331 1332 static void 1333 hook_tsc_freq(void *arg __unused) 1334 { 1335 1336 if (tsc_is_invariant) 1337 return; 1338 1339 tsc_post_tag = EVENTHANDLER_REGISTER(cpufreq_post_change, 1340 tsc_freq_changed, NULL, EVENTHANDLER_PRI_ANY); 1341 } 1342 1343 SYSINIT(hook_tsc_freq, SI_SUB_CONFIGURE, SI_ORDER_ANY, hook_tsc_freq, NULL); 1344 1345 static struct { 1346 const char *vm_cpuid; 1347 int vm_guest; 1348 } vm_cpuids[] = { 1349 { "XenVMMXenVMM", VM_GUEST_XEN }, /* XEN */ 1350 { "Microsoft Hv", VM_GUEST_HV }, /* Microsoft Hyper-V */ 1351 { "VMwareVMware", VM_GUEST_VMWARE }, /* VMware VM */ 1352 { "KVMKVMKVM", VM_GUEST_KVM }, /* KVM */ 1353 { "bhyve bhyve ", VM_GUEST_BHYVE }, /* bhyve */ 1354 { "VBoxVBoxVBox", VM_GUEST_VBOX }, /* VirtualBox */ 1355 }; 1356 1357 static void 1358 identify_hypervisor_cpuid_base(void) 1359 { 1360 u_int leaf, regs[4]; 1361 int i; 1362 1363 /* 1364 * [RFC] CPUID usage for interaction between Hypervisors and Linux. 1365 * http://lkml.org/lkml/2008/10/1/246 1366 * 1367 * KB1009458: Mechanisms to determine if software is running in 1368 * a VMware virtual machine 1369 * http://kb.vmware.com/kb/1009458 1370 * 1371 * Search for a hypervisor that we recognize. If we cannot find 1372 * a specific hypervisor, return the first information about the 1373 * hypervisor that we found, as others may be able to use. 1374 */ 1375 for (leaf = 0x40000000; leaf < 0x40010000; leaf += 0x100) { 1376 do_cpuid(leaf, regs); 1377 1378 /* 1379 * KVM from Linux kernels prior to commit 1380 * 57c22e5f35aa4b9b2fe11f73f3e62bbf9ef36190 set %eax 1381 * to 0 rather than a valid hv_high value. Check for 1382 * the KVM signature bytes and fixup %eax to the 1383 * highest supported leaf in that case. 1384 */ 1385 if (regs[0] == 0 && regs[1] == 0x4b4d564b && 1386 regs[2] == 0x564b4d56 && regs[3] == 0x0000004d) 1387 regs[0] = leaf + 1; 1388 1389 if (regs[0] >= leaf) { 1390 for (i = 0; i < nitems(vm_cpuids); i++) 1391 if (strncmp((const char *)®s[1], 1392 vm_cpuids[i].vm_cpuid, 12) == 0) { 1393 vm_guest = vm_cpuids[i].vm_guest; 1394 break; 1395 } 1396 1397 /* 1398 * If this is the first entry or we found a 1399 * specific hypervisor, record the base, high value, 1400 * and vendor identifier. 1401 */ 1402 if (vm_guest != VM_GUEST_VM || leaf == 0x40000000) { 1403 hv_base = leaf; 1404 hv_high = regs[0]; 1405 ((u_int *)&hv_vendor)[0] = regs[1]; 1406 ((u_int *)&hv_vendor)[1] = regs[2]; 1407 ((u_int *)&hv_vendor)[2] = regs[3]; 1408 hv_vendor[12] = '\0'; 1409 1410 /* 1411 * If we found a specific hypervisor, then 1412 * we are finished. 1413 */ 1414 if (vm_guest != VM_GUEST_VM) 1415 return; 1416 } 1417 } 1418 } 1419 } 1420 1421 void 1422 identify_hypervisor(void) 1423 { 1424 u_int regs[4]; 1425 char *p; 1426 1427 /* 1428 * If CPUID2_HV is set, we are running in a hypervisor environment. 1429 */ 1430 if (cpu_feature2 & CPUID2_HV) { 1431 vm_guest = VM_GUEST_VM; 1432 identify_hypervisor_cpuid_base(); 1433 1434 /* If we have a definitive vendor, we can return now. */ 1435 if (*hv_vendor != '\0') 1436 return; 1437 } 1438 1439 /* 1440 * Examine SMBIOS strings for older hypervisors. 1441 */ 1442 p = kern_getenv("smbios.system.serial"); 1443 if (p != NULL) { 1444 if (strncmp(p, "VMware-", 7) == 0 || strncmp(p, "VMW", 3) == 0) { 1445 vmware_hvcall(VMW_HVCMD_GETVERSION, regs); 1446 if (regs[1] == VMW_HVMAGIC) { 1447 vm_guest = VM_GUEST_VMWARE; 1448 freeenv(p); 1449 return; 1450 } 1451 } 1452 freeenv(p); 1453 } 1454 } 1455 1456 bool 1457 fix_cpuid(void) 1458 { 1459 uint64_t msr; 1460 1461 /* 1462 * Clear "Limit CPUID Maxval" bit and return true if the caller should 1463 * get the largest standard CPUID function number again if it is set 1464 * from BIOS. It is necessary for probing correct CPU topology later 1465 * and for the correct operation of the AVX-aware userspace. 1466 */ 1467 if (cpu_vendor_id == CPU_VENDOR_INTEL && 1468 ((CPUID_TO_FAMILY(cpu_id) == 0xf && 1469 CPUID_TO_MODEL(cpu_id) >= 0x3) || 1470 (CPUID_TO_FAMILY(cpu_id) == 0x6 && 1471 CPUID_TO_MODEL(cpu_id) >= 0xe))) { 1472 msr = rdmsr(MSR_IA32_MISC_ENABLE); 1473 if ((msr & IA32_MISC_EN_LIMCPUID) != 0) { 1474 msr &= ~IA32_MISC_EN_LIMCPUID; 1475 wrmsr(MSR_IA32_MISC_ENABLE, msr); 1476 return (true); 1477 } 1478 } 1479 1480 /* 1481 * Re-enable AMD Topology Extension that could be disabled by BIOS 1482 * on some notebook processors. Without the extension it's really 1483 * hard to determine the correct CPU cache topology. 1484 * See BIOS and Kernel Developer’s Guide (BKDG) for AMD Family 15h 1485 * Models 60h-6Fh Processors, Publication # 50742. 1486 */ 1487 if (vm_guest == VM_GUEST_NO && cpu_vendor_id == CPU_VENDOR_AMD && 1488 CPUID_TO_FAMILY(cpu_id) == 0x15) { 1489 msr = rdmsr(MSR_EXTFEATURES); 1490 if ((msr & ((uint64_t)1 << 54)) == 0) { 1491 msr |= (uint64_t)1 << 54; 1492 wrmsr(MSR_EXTFEATURES, msr); 1493 return (true); 1494 } 1495 } 1496 return (false); 1497 } 1498 1499 void 1500 identify_cpu1(void) 1501 { 1502 u_int regs[4]; 1503 1504 do_cpuid(0, regs); 1505 cpu_high = regs[0]; 1506 ((u_int *)&cpu_vendor)[0] = regs[1]; 1507 ((u_int *)&cpu_vendor)[1] = regs[3]; 1508 ((u_int *)&cpu_vendor)[2] = regs[2]; 1509 cpu_vendor[12] = '\0'; 1510 1511 do_cpuid(1, regs); 1512 cpu_id = regs[0]; 1513 cpu_procinfo = regs[1]; 1514 cpu_feature = regs[3]; 1515 cpu_feature2 = regs[2]; 1516 } 1517 1518 void 1519 identify_cpu2(void) 1520 { 1521 u_int regs[4], cpu_stdext_disable; 1522 1523 if (cpu_high >= 6) { 1524 cpuid_count(6, 0, regs); 1525 cpu_power_eax = regs[0]; 1526 cpu_power_ebx = regs[1]; 1527 cpu_power_ecx = regs[2]; 1528 cpu_power_edx = regs[3]; 1529 } 1530 1531 if (cpu_high >= 7) { 1532 cpuid_count(7, 0, regs); 1533 cpu_stdext_feature = regs[1]; 1534 1535 /* 1536 * Some hypervisors failed to filter out unsupported 1537 * extended features. Allow to disable the 1538 * extensions, activation of which requires setting a 1539 * bit in CR4, and which VM monitors do not support. 1540 */ 1541 cpu_stdext_disable = 0; 1542 TUNABLE_INT_FETCH("hw.cpu_stdext_disable", &cpu_stdext_disable); 1543 cpu_stdext_feature &= ~cpu_stdext_disable; 1544 1545 cpu_stdext_feature2 = regs[2]; 1546 cpu_stdext_feature3 = regs[3]; 1547 1548 if ((cpu_stdext_feature3 & CPUID_STDEXT3_ARCH_CAP) != 0) 1549 cpu_ia32_arch_caps = rdmsr(MSR_IA32_ARCH_CAP); 1550 } 1551 } 1552 1553 void 1554 identify_cpu_ext_features(void) 1555 { 1556 u_int regs[4]; 1557 1558 if (cpu_high >= 7) { 1559 cpuid_count(7, 0, regs); 1560 cpu_stdext_feature2 = regs[2]; 1561 cpu_stdext_feature3 = regs[3]; 1562 } 1563 } 1564 1565 void 1566 identify_cpu_fixup_bsp(void) 1567 { 1568 u_int regs[4]; 1569 1570 cpu_vendor_id = find_cpu_vendor_id(); 1571 1572 if (fix_cpuid()) { 1573 do_cpuid(0, regs); 1574 cpu_high = regs[0]; 1575 } 1576 } 1577 1578 /* 1579 * Final stage of CPU identification. 1580 */ 1581 void 1582 finishidentcpu(void) 1583 { 1584 u_int regs[4]; 1585 #ifdef __i386__ 1586 u_char ccr3; 1587 #endif 1588 1589 identify_cpu_fixup_bsp(); 1590 1591 if (cpu_high >= 5 && (cpu_feature2 & CPUID2_MON) != 0) { 1592 do_cpuid(5, regs); 1593 cpu_mon_mwait_flags = regs[2]; 1594 cpu_mon_min_size = regs[0] & CPUID5_MON_MIN_SIZE; 1595 cpu_mon_max_size = regs[1] & CPUID5_MON_MAX_SIZE; 1596 } 1597 1598 identify_cpu2(); 1599 1600 #ifdef __i386__ 1601 if (cpu_high > 0 && 1602 (cpu_vendor_id == CPU_VENDOR_INTEL || 1603 cpu_vendor_id == CPU_VENDOR_AMD || 1604 cpu_vendor_id == CPU_VENDOR_HYGON || 1605 cpu_vendor_id == CPU_VENDOR_TRANSMETA || 1606 cpu_vendor_id == CPU_VENDOR_CENTAUR || 1607 cpu_vendor_id == CPU_VENDOR_NSC)) { 1608 do_cpuid(0x80000000, regs); 1609 if (regs[0] >= 0x80000000) 1610 cpu_exthigh = regs[0]; 1611 } 1612 #else 1613 if (cpu_vendor_id == CPU_VENDOR_INTEL || 1614 cpu_vendor_id == CPU_VENDOR_AMD || 1615 cpu_vendor_id == CPU_VENDOR_HYGON || 1616 cpu_vendor_id == CPU_VENDOR_CENTAUR) { 1617 do_cpuid(0x80000000, regs); 1618 cpu_exthigh = regs[0]; 1619 } 1620 #endif 1621 if (cpu_exthigh >= 0x80000001) { 1622 do_cpuid(0x80000001, regs); 1623 amd_feature = regs[3] & ~(cpu_feature & 0x0183f3ff); 1624 amd_feature2 = regs[2]; 1625 } 1626 if (cpu_exthigh >= 0x80000007) { 1627 do_cpuid(0x80000007, regs); 1628 amd_rascap = regs[1]; 1629 amd_pminfo = regs[3]; 1630 } 1631 if (cpu_exthigh >= 0x80000008) { 1632 do_cpuid(0x80000008, regs); 1633 cpu_maxphyaddr = regs[0] & 0xff; 1634 amd_extended_feature_extensions = regs[1]; 1635 cpu_procinfo2 = regs[2]; 1636 } else { 1637 cpu_maxphyaddr = (cpu_feature & CPUID_PAE) != 0 ? 36 : 32; 1638 } 1639 1640 #ifdef __i386__ 1641 if (cpu_vendor_id == CPU_VENDOR_CYRIX) { 1642 if (cpu == CPU_486) { 1643 /* 1644 * These conditions are equivalent to: 1645 * - CPU does not support cpuid instruction. 1646 * - Cyrix/IBM CPU is detected. 1647 */ 1648 if (identblue() == IDENTBLUE_IBMCPU) { 1649 strcpy(cpu_vendor, "IBM"); 1650 cpu_vendor_id = CPU_VENDOR_IBM; 1651 cpu = CPU_BLUE; 1652 return; 1653 } 1654 } 1655 switch (cpu_id & 0xf00) { 1656 case 0x600: 1657 /* 1658 * Cyrix's datasheet does not describe DIRs. 1659 * Therefor, I assume it does not have them 1660 * and use the result of the cpuid instruction. 1661 * XXX they seem to have it for now at least. -Peter 1662 */ 1663 identifycyrix(); 1664 cpu = CPU_M2; 1665 break; 1666 default: 1667 identifycyrix(); 1668 /* 1669 * This routine contains a trick. 1670 * Don't check (cpu_id & 0x00f0) == 0x50 to detect M2, now. 1671 */ 1672 switch (cyrix_did & 0x00f0) { 1673 case 0x00: 1674 case 0xf0: 1675 cpu = CPU_486DLC; 1676 break; 1677 case 0x10: 1678 cpu = CPU_CY486DX; 1679 break; 1680 case 0x20: 1681 if ((cyrix_did & 0x000f) < 8) 1682 cpu = CPU_M1; 1683 else 1684 cpu = CPU_M1SC; 1685 break; 1686 case 0x30: 1687 cpu = CPU_M1; 1688 break; 1689 case 0x40: 1690 /* MediaGX CPU */ 1691 cpu = CPU_M1SC; 1692 break; 1693 default: 1694 /* M2 and later CPUs are treated as M2. */ 1695 cpu = CPU_M2; 1696 1697 /* 1698 * enable cpuid instruction. 1699 */ 1700 ccr3 = read_cyrix_reg(CCR3); 1701 write_cyrix_reg(CCR3, CCR3_MAPEN0); 1702 write_cyrix_reg(CCR4, read_cyrix_reg(CCR4) | CCR4_CPUID); 1703 write_cyrix_reg(CCR3, ccr3); 1704 1705 do_cpuid(0, regs); 1706 cpu_high = regs[0]; /* eax */ 1707 do_cpuid(1, regs); 1708 cpu_id = regs[0]; /* eax */ 1709 cpu_feature = regs[3]; /* edx */ 1710 break; 1711 } 1712 } 1713 } else if (cpu == CPU_486 && *cpu_vendor == '\0') { 1714 /* 1715 * There are BlueLightning CPUs that do not change 1716 * undefined flags by dividing 5 by 2. In this case, 1717 * the CPU identification routine in locore.s leaves 1718 * cpu_vendor null string and puts CPU_486 into the 1719 * cpu. 1720 */ 1721 if (identblue() == IDENTBLUE_IBMCPU) { 1722 strcpy(cpu_vendor, "IBM"); 1723 cpu_vendor_id = CPU_VENDOR_IBM; 1724 cpu = CPU_BLUE; 1725 return; 1726 } 1727 } 1728 #endif 1729 } 1730 1731 int 1732 pti_get_default(void) 1733 { 1734 1735 if (strcmp(cpu_vendor, AMD_VENDOR_ID) == 0 || 1736 strcmp(cpu_vendor, HYGON_VENDOR_ID) == 0) 1737 return (0); 1738 if ((cpu_ia32_arch_caps & IA32_ARCH_CAP_RDCL_NO) != 0) 1739 return (0); 1740 return (1); 1741 } 1742 1743 static u_int 1744 find_cpu_vendor_id(void) 1745 { 1746 int i; 1747 1748 for (i = 0; i < nitems(cpu_vendors); i++) 1749 if (strcmp(cpu_vendor, cpu_vendors[i].vendor) == 0) 1750 return (cpu_vendors[i].vendor_id); 1751 return (0); 1752 } 1753 1754 static void 1755 print_AMD_assoc(int i) 1756 { 1757 if (i == 255) 1758 printf(", fully associative\n"); 1759 else 1760 printf(", %d-way associative\n", i); 1761 } 1762 1763 static void 1764 print_AMD_l2_assoc(int i) 1765 { 1766 switch (i & 0x0f) { 1767 case 0: printf(", disabled/not present\n"); break; 1768 case 1: printf(", direct mapped\n"); break; 1769 case 2: printf(", 2-way associative\n"); break; 1770 case 4: printf(", 4-way associative\n"); break; 1771 case 6: printf(", 8-way associative\n"); break; 1772 case 8: printf(", 16-way associative\n"); break; 1773 case 15: printf(", fully associative\n"); break; 1774 default: printf(", reserved configuration\n"); break; 1775 } 1776 } 1777 1778 static void 1779 print_AMD_info(void) 1780 { 1781 #ifdef __i386__ 1782 uint64_t amd_whcr; 1783 #endif 1784 u_int regs[4]; 1785 1786 if (cpu_exthigh >= 0x80000005) { 1787 do_cpuid(0x80000005, regs); 1788 printf("L1 2MB data TLB: %d entries", (regs[0] >> 16) & 0xff); 1789 print_AMD_assoc(regs[0] >> 24); 1790 1791 printf("L1 2MB instruction TLB: %d entries", regs[0] & 0xff); 1792 print_AMD_assoc((regs[0] >> 8) & 0xff); 1793 1794 printf("L1 4KB data TLB: %d entries", (regs[1] >> 16) & 0xff); 1795 print_AMD_assoc(regs[1] >> 24); 1796 1797 printf("L1 4KB instruction TLB: %d entries", regs[1] & 0xff); 1798 print_AMD_assoc((regs[1] >> 8) & 0xff); 1799 1800 printf("L1 data cache: %d kbytes", regs[2] >> 24); 1801 printf(", %d bytes/line", regs[2] & 0xff); 1802 printf(", %d lines/tag", (regs[2] >> 8) & 0xff); 1803 print_AMD_assoc((regs[2] >> 16) & 0xff); 1804 1805 printf("L1 instruction cache: %d kbytes", regs[3] >> 24); 1806 printf(", %d bytes/line", regs[3] & 0xff); 1807 printf(", %d lines/tag", (regs[3] >> 8) & 0xff); 1808 print_AMD_assoc((regs[3] >> 16) & 0xff); 1809 } 1810 1811 if (cpu_exthigh >= 0x80000006) { 1812 do_cpuid(0x80000006, regs); 1813 if ((regs[0] >> 16) != 0) { 1814 printf("L2 2MB data TLB: %d entries", 1815 (regs[0] >> 16) & 0xfff); 1816 print_AMD_l2_assoc(regs[0] >> 28); 1817 printf("L2 2MB instruction TLB: %d entries", 1818 regs[0] & 0xfff); 1819 print_AMD_l2_assoc((regs[0] >> 28) & 0xf); 1820 } else { 1821 printf("L2 2MB unified TLB: %d entries", 1822 regs[0] & 0xfff); 1823 print_AMD_l2_assoc((regs[0] >> 28) & 0xf); 1824 } 1825 if ((regs[1] >> 16) != 0) { 1826 printf("L2 4KB data TLB: %d entries", 1827 (regs[1] >> 16) & 0xfff); 1828 print_AMD_l2_assoc(regs[1] >> 28); 1829 1830 printf("L2 4KB instruction TLB: %d entries", 1831 (regs[1] >> 16) & 0xfff); 1832 print_AMD_l2_assoc((regs[1] >> 28) & 0xf); 1833 } else { 1834 printf("L2 4KB unified TLB: %d entries", 1835 (regs[1] >> 16) & 0xfff); 1836 print_AMD_l2_assoc((regs[1] >> 28) & 0xf); 1837 } 1838 printf("L2 unified cache: %d kbytes", regs[2] >> 16); 1839 printf(", %d bytes/line", regs[2] & 0xff); 1840 printf(", %d lines/tag", (regs[2] >> 8) & 0x0f); 1841 print_AMD_l2_assoc((regs[2] >> 12) & 0x0f); 1842 } 1843 1844 #ifdef __i386__ 1845 if (((cpu_id & 0xf00) == 0x500) 1846 && (((cpu_id & 0x0f0) > 0x80) 1847 || (((cpu_id & 0x0f0) == 0x80) 1848 && (cpu_id & 0x00f) > 0x07))) { 1849 /* K6-2(new core [Stepping 8-F]), K6-III or later */ 1850 amd_whcr = rdmsr(0xc0000082); 1851 if (!(amd_whcr & (0x3ff << 22))) { 1852 printf("Write Allocate Disable\n"); 1853 } else { 1854 printf("Write Allocate Enable Limit: %dM bytes\n", 1855 (u_int32_t)((amd_whcr & (0x3ff << 22)) >> 22) * 4); 1856 printf("Write Allocate 15-16M bytes: %s\n", 1857 (amd_whcr & (1 << 16)) ? "Enable" : "Disable"); 1858 } 1859 } else if (((cpu_id & 0xf00) == 0x500) 1860 && ((cpu_id & 0x0f0) > 0x50)) { 1861 /* K6, K6-2(old core) */ 1862 amd_whcr = rdmsr(0xc0000082); 1863 if (!(amd_whcr & (0x7f << 1))) { 1864 printf("Write Allocate Disable\n"); 1865 } else { 1866 printf("Write Allocate Enable Limit: %dM bytes\n", 1867 (u_int32_t)((amd_whcr & (0x7f << 1)) >> 1) * 4); 1868 printf("Write Allocate 15-16M bytes: %s\n", 1869 (amd_whcr & 0x0001) ? "Enable" : "Disable"); 1870 printf("Hardware Write Allocate Control: %s\n", 1871 (amd_whcr & 0x0100) ? "Enable" : "Disable"); 1872 } 1873 } 1874 #endif 1875 /* 1876 * Opteron Rev E shows a bug as in very rare occasions a read memory 1877 * barrier is not performed as expected if it is followed by a 1878 * non-atomic read-modify-write instruction. 1879 * As long as that bug pops up very rarely (intensive machine usage 1880 * on other operating systems generally generates one unexplainable 1881 * crash any 2 months) and as long as a model specific fix would be 1882 * impractical at this stage, print out a warning string if the broken 1883 * model and family are identified. 1884 */ 1885 if (CPUID_TO_FAMILY(cpu_id) == 0xf && CPUID_TO_MODEL(cpu_id) >= 0x20 && 1886 CPUID_TO_MODEL(cpu_id) <= 0x3f) 1887 printf("WARNING: This architecture revision has known SMP " 1888 "hardware bugs which may cause random instability\n"); 1889 } 1890 1891 static void 1892 print_INTEL_info(void) 1893 { 1894 u_int regs[4]; 1895 u_int rounds, regnum; 1896 u_int nwaycode, nway; 1897 1898 if (cpu_high >= 2) { 1899 rounds = 0; 1900 do { 1901 do_cpuid(0x2, regs); 1902 if (rounds == 0 && (rounds = (regs[0] & 0xff)) == 0) 1903 break; /* we have a buggy CPU */ 1904 1905 for (regnum = 0; regnum <= 3; ++regnum) { 1906 if (regs[regnum] & (1<<31)) 1907 continue; 1908 if (regnum != 0) 1909 print_INTEL_TLB(regs[regnum] & 0xff); 1910 print_INTEL_TLB((regs[regnum] >> 8) & 0xff); 1911 print_INTEL_TLB((regs[regnum] >> 16) & 0xff); 1912 print_INTEL_TLB((regs[regnum] >> 24) & 0xff); 1913 } 1914 } while (--rounds > 0); 1915 } 1916 1917 if (cpu_exthigh >= 0x80000006) { 1918 do_cpuid(0x80000006, regs); 1919 nwaycode = (regs[2] >> 12) & 0x0f; 1920 if (nwaycode >= 0x02 && nwaycode <= 0x08) 1921 nway = 1 << (nwaycode / 2); 1922 else 1923 nway = 0; 1924 printf("L2 cache: %u kbytes, %u-way associative, %u bytes/line\n", 1925 (regs[2] >> 16) & 0xffff, nway, regs[2] & 0xff); 1926 } 1927 } 1928 1929 static void 1930 print_INTEL_TLB(u_int data) 1931 { 1932 switch (data) { 1933 case 0x0: 1934 case 0x40: 1935 default: 1936 break; 1937 case 0x1: 1938 printf("Instruction TLB: 4 KB pages, 4-way set associative, 32 entries\n"); 1939 break; 1940 case 0x2: 1941 printf("Instruction TLB: 4 MB pages, fully associative, 2 entries\n"); 1942 break; 1943 case 0x3: 1944 printf("Data TLB: 4 KB pages, 4-way set associative, 64 entries\n"); 1945 break; 1946 case 0x4: 1947 printf("Data TLB: 4 MB Pages, 4-way set associative, 8 entries\n"); 1948 break; 1949 case 0x6: 1950 printf("1st-level instruction cache: 8 KB, 4-way set associative, 32 byte line size\n"); 1951 break; 1952 case 0x8: 1953 printf("1st-level instruction cache: 16 KB, 4-way set associative, 32 byte line size\n"); 1954 break; 1955 case 0x9: 1956 printf("1st-level instruction cache: 32 KB, 4-way set associative, 64 byte line size\n"); 1957 break; 1958 case 0xa: 1959 printf("1st-level data cache: 8 KB, 2-way set associative, 32 byte line size\n"); 1960 break; 1961 case 0xb: 1962 printf("Instruction TLB: 4 MByte pages, 4-way set associative, 4 entries\n"); 1963 break; 1964 case 0xc: 1965 printf("1st-level data cache: 16 KB, 4-way set associative, 32 byte line size\n"); 1966 break; 1967 case 0xd: 1968 printf("1st-level data cache: 16 KBytes, 4-way set associative, 64 byte line size"); 1969 break; 1970 case 0xe: 1971 printf("1st-level data cache: 24 KBytes, 6-way set associative, 64 byte line size\n"); 1972 break; 1973 case 0x1d: 1974 printf("2nd-level cache: 128 KBytes, 2-way set associative, 64 byte line size\n"); 1975 break; 1976 case 0x21: 1977 printf("2nd-level cache: 256 KBytes, 8-way set associative, 64 byte line size\n"); 1978 break; 1979 case 0x22: 1980 printf("3rd-level cache: 512 KB, 4-way set associative, sectored cache, 64 byte line size\n"); 1981 break; 1982 case 0x23: 1983 printf("3rd-level cache: 1 MB, 8-way set associative, sectored cache, 64 byte line size\n"); 1984 break; 1985 case 0x24: 1986 printf("2nd-level cache: 1 MBytes, 16-way set associative, 64 byte line size\n"); 1987 break; 1988 case 0x25: 1989 printf("3rd-level cache: 2 MB, 8-way set associative, sectored cache, 64 byte line size\n"); 1990 break; 1991 case 0x29: 1992 printf("3rd-level cache: 4 MB, 8-way set associative, sectored cache, 64 byte line size\n"); 1993 break; 1994 case 0x2c: 1995 printf("1st-level data cache: 32 KB, 8-way set associative, 64 byte line size\n"); 1996 break; 1997 case 0x30: 1998 printf("1st-level instruction cache: 32 KB, 8-way set associative, 64 byte line size\n"); 1999 break; 2000 case 0x39: /* De-listed in SDM rev. 54 */ 2001 printf("2nd-level cache: 128 KB, 4-way set associative, sectored cache, 64 byte line size\n"); 2002 break; 2003 case 0x3b: /* De-listed in SDM rev. 54 */ 2004 printf("2nd-level cache: 128 KB, 2-way set associative, sectored cache, 64 byte line size\n"); 2005 break; 2006 case 0x3c: /* De-listed in SDM rev. 54 */ 2007 printf("2nd-level cache: 256 KB, 4-way set associative, sectored cache, 64 byte line size\n"); 2008 break; 2009 case 0x41: 2010 printf("2nd-level cache: 128 KB, 4-way set associative, 32 byte line size\n"); 2011 break; 2012 case 0x42: 2013 printf("2nd-level cache: 256 KB, 4-way set associative, 32 byte line size\n"); 2014 break; 2015 case 0x43: 2016 printf("2nd-level cache: 512 KB, 4-way set associative, 32 byte line size\n"); 2017 break; 2018 case 0x44: 2019 printf("2nd-level cache: 1 MB, 4-way set associative, 32 byte line size\n"); 2020 break; 2021 case 0x45: 2022 printf("2nd-level cache: 2 MB, 4-way set associative, 32 byte line size\n"); 2023 break; 2024 case 0x46: 2025 printf("3rd-level cache: 4 MB, 4-way set associative, 64 byte line size\n"); 2026 break; 2027 case 0x47: 2028 printf("3rd-level cache: 8 MB, 8-way set associative, 64 byte line size\n"); 2029 break; 2030 case 0x48: 2031 printf("2nd-level cache: 3MByte, 12-way set associative, 64 byte line size\n"); 2032 break; 2033 case 0x49: 2034 if (CPUID_TO_FAMILY(cpu_id) == 0xf && 2035 CPUID_TO_MODEL(cpu_id) == 0x6) 2036 printf("3rd-level cache: 4MB, 16-way set associative, 64-byte line size\n"); 2037 else 2038 printf("2nd-level cache: 4 MByte, 16-way set associative, 64 byte line size"); 2039 break; 2040 case 0x4a: 2041 printf("3rd-level cache: 6MByte, 12-way set associative, 64 byte line size\n"); 2042 break; 2043 case 0x4b: 2044 printf("3rd-level cache: 8MByte, 16-way set associative, 64 byte line size\n"); 2045 break; 2046 case 0x4c: 2047 printf("3rd-level cache: 12MByte, 12-way set associative, 64 byte line size\n"); 2048 break; 2049 case 0x4d: 2050 printf("3rd-level cache: 16MByte, 16-way set associative, 64 byte line size\n"); 2051 break; 2052 case 0x4e: 2053 printf("2nd-level cache: 6MByte, 24-way set associative, 64 byte line size\n"); 2054 break; 2055 case 0x4f: 2056 printf("Instruction TLB: 4 KByte pages, 32 entries\n"); 2057 break; 2058 case 0x50: 2059 printf("Instruction TLB: 4 KB, 2 MB or 4 MB pages, fully associative, 64 entries\n"); 2060 break; 2061 case 0x51: 2062 printf("Instruction TLB: 4 KB, 2 MB or 4 MB pages, fully associative, 128 entries\n"); 2063 break; 2064 case 0x52: 2065 printf("Instruction TLB: 4 KB, 2 MB or 4 MB pages, fully associative, 256 entries\n"); 2066 break; 2067 case 0x55: 2068 printf("Instruction TLB: 2-MByte or 4-MByte pages, fully associative, 7 entries\n"); 2069 break; 2070 case 0x56: 2071 printf("Data TLB0: 4 MByte pages, 4-way set associative, 16 entries\n"); 2072 break; 2073 case 0x57: 2074 printf("Data TLB0: 4 KByte pages, 4-way associative, 16 entries\n"); 2075 break; 2076 case 0x59: 2077 printf("Data TLB0: 4 KByte pages, fully associative, 16 entries\n"); 2078 break; 2079 case 0x5a: 2080 printf("Data TLB0: 2-MByte or 4 MByte pages, 4-way set associative, 32 entries\n"); 2081 break; 2082 case 0x5b: 2083 printf("Data TLB: 4 KB or 4 MB pages, fully associative, 64 entries\n"); 2084 break; 2085 case 0x5c: 2086 printf("Data TLB: 4 KB or 4 MB pages, fully associative, 128 entries\n"); 2087 break; 2088 case 0x5d: 2089 printf("Data TLB: 4 KB or 4 MB pages, fully associative, 256 entries\n"); 2090 break; 2091 case 0x60: 2092 printf("1st-level data cache: 16 KB, 8-way set associative, sectored cache, 64 byte line size\n"); 2093 break; 2094 case 0x61: 2095 printf("Instruction TLB: 4 KByte pages, fully associative, 48 entries\n"); 2096 break; 2097 case 0x63: 2098 printf("Data TLB: 2 MByte or 4 MByte pages, 4-way set associative, 32 entries and a separate array with 1 GByte pages, 4-way set associative, 4 entries\n"); 2099 break; 2100 case 0x64: 2101 printf("Data TLB: 4 KBytes pages, 4-way set associative, 512 entries\n"); 2102 break; 2103 case 0x66: 2104 printf("1st-level data cache: 8 KB, 4-way set associative, sectored cache, 64 byte line size\n"); 2105 break; 2106 case 0x67: 2107 printf("1st-level data cache: 16 KB, 4-way set associative, sectored cache, 64 byte line size\n"); 2108 break; 2109 case 0x68: 2110 printf("1st-level data cache: 32 KB, 4 way set associative, sectored cache, 64 byte line size\n"); 2111 break; 2112 case 0x6a: 2113 printf("uTLB: 4KByte pages, 8-way set associative, 64 entries\n"); 2114 break; 2115 case 0x6b: 2116 printf("DTLB: 4KByte pages, 8-way set associative, 256 entries\n"); 2117 break; 2118 case 0x6c: 2119 printf("DTLB: 2M/4M pages, 8-way set associative, 128 entries\n"); 2120 break; 2121 case 0x6d: 2122 printf("DTLB: 1 GByte pages, fully associative, 16 entries\n"); 2123 break; 2124 case 0x70: 2125 printf("Trace cache: 12K-uops, 8-way set associative\n"); 2126 break; 2127 case 0x71: 2128 printf("Trace cache: 16K-uops, 8-way set associative\n"); 2129 break; 2130 case 0x72: 2131 printf("Trace cache: 32K-uops, 8-way set associative\n"); 2132 break; 2133 case 0x76: 2134 printf("Instruction TLB: 2M/4M pages, fully associative, 8 entries\n"); 2135 break; 2136 case 0x78: 2137 printf("2nd-level cache: 1 MB, 4-way set associative, 64-byte line size\n"); 2138 break; 2139 case 0x79: 2140 printf("2nd-level cache: 128 KB, 8-way set associative, sectored cache, 64 byte line size\n"); 2141 break; 2142 case 0x7a: 2143 printf("2nd-level cache: 256 KB, 8-way set associative, sectored cache, 64 byte line size\n"); 2144 break; 2145 case 0x7b: 2146 printf("2nd-level cache: 512 KB, 8-way set associative, sectored cache, 64 byte line size\n"); 2147 break; 2148 case 0x7c: 2149 printf("2nd-level cache: 1 MB, 8-way set associative, sectored cache, 64 byte line size\n"); 2150 break; 2151 case 0x7d: 2152 printf("2nd-level cache: 2-MB, 8-way set associative, 64-byte line size\n"); 2153 break; 2154 case 0x7f: 2155 printf("2nd-level cache: 512-KB, 2-way set associative, 64-byte line size\n"); 2156 break; 2157 case 0x80: 2158 printf("2nd-level cache: 512 KByte, 8-way set associative, 64-byte line size\n"); 2159 break; 2160 case 0x82: 2161 printf("2nd-level cache: 256 KB, 8-way set associative, 32 byte line size\n"); 2162 break; 2163 case 0x83: 2164 printf("2nd-level cache: 512 KB, 8-way set associative, 32 byte line size\n"); 2165 break; 2166 case 0x84: 2167 printf("2nd-level cache: 1 MB, 8-way set associative, 32 byte line size\n"); 2168 break; 2169 case 0x85: 2170 printf("2nd-level cache: 2 MB, 8-way set associative, 32 byte line size\n"); 2171 break; 2172 case 0x86: 2173 printf("2nd-level cache: 512 KB, 4-way set associative, 64 byte line size\n"); 2174 break; 2175 case 0x87: 2176 printf("2nd-level cache: 1 MB, 8-way set associative, 64 byte line size\n"); 2177 break; 2178 case 0xa0: 2179 printf("DTLB: 4k pages, fully associative, 32 entries\n"); 2180 break; 2181 case 0xb0: 2182 printf("Instruction TLB: 4 KB Pages, 4-way set associative, 128 entries\n"); 2183 break; 2184 case 0xb1: 2185 printf("Instruction TLB: 2M pages, 4-way, 8 entries or 4M pages, 4-way, 4 entries\n"); 2186 break; 2187 case 0xb2: 2188 printf("Instruction TLB: 4KByte pages, 4-way set associative, 64 entries\n"); 2189 break; 2190 case 0xb3: 2191 printf("Data TLB: 4 KB Pages, 4-way set associative, 128 entries\n"); 2192 break; 2193 case 0xb4: 2194 printf("Data TLB1: 4 KByte pages, 4-way associative, 256 entries\n"); 2195 break; 2196 case 0xb5: 2197 printf("Instruction TLB: 4KByte pages, 8-way set associative, 64 entries\n"); 2198 break; 2199 case 0xb6: 2200 printf("Instruction TLB: 4KByte pages, 8-way set associative, 128 entries\n"); 2201 break; 2202 case 0xba: 2203 printf("Data TLB1: 4 KByte pages, 4-way associative, 64 entries\n"); 2204 break; 2205 case 0xc0: 2206 printf("Data TLB: 4 KByte and 4 MByte pages, 4-way associative, 8 entries\n"); 2207 break; 2208 case 0xc1: 2209 printf("Shared 2nd-Level TLB: 4 KByte/2MByte pages, 8-way associative, 1024 entries\n"); 2210 break; 2211 case 0xc2: 2212 printf("DTLB: 4 KByte/2 MByte pages, 4-way associative, 16 entries\n"); 2213 break; 2214 case 0xc3: 2215 printf("Shared 2nd-Level TLB: 4 KByte /2 MByte pages, 6-way associative, 1536 entries. Also 1GBbyte pages, 4-way, 16 entries\n"); 2216 break; 2217 case 0xc4: 2218 printf("DTLB: 2M/4M Byte pages, 4-way associative, 32 entries\n"); 2219 break; 2220 case 0xca: 2221 printf("Shared 2nd-Level TLB: 4 KByte pages, 4-way associative, 512 entries\n"); 2222 break; 2223 case 0xd0: 2224 printf("3rd-level cache: 512 KByte, 4-way set associative, 64 byte line size\n"); 2225 break; 2226 case 0xd1: 2227 printf("3rd-level cache: 1 MByte, 4-way set associative, 64 byte line size\n"); 2228 break; 2229 case 0xd2: 2230 printf("3rd-level cache: 2 MByte, 4-way set associative, 64 byte line size\n"); 2231 break; 2232 case 0xd6: 2233 printf("3rd-level cache: 1 MByte, 8-way set associative, 64 byte line size\n"); 2234 break; 2235 case 0xd7: 2236 printf("3rd-level cache: 2 MByte, 8-way set associative, 64 byte line size\n"); 2237 break; 2238 case 0xd8: 2239 printf("3rd-level cache: 4 MByte, 8-way set associative, 64 byte line size\n"); 2240 break; 2241 case 0xdc: 2242 printf("3rd-level cache: 1.5 MByte, 12-way set associative, 64 byte line size\n"); 2243 break; 2244 case 0xdd: 2245 printf("3rd-level cache: 3 MByte, 12-way set associative, 64 byte line size\n"); 2246 break; 2247 case 0xde: 2248 printf("3rd-level cache: 6 MByte, 12-way set associative, 64 byte line size\n"); 2249 break; 2250 case 0xe2: 2251 printf("3rd-level cache: 2 MByte, 16-way set associative, 64 byte line size\n"); 2252 break; 2253 case 0xe3: 2254 printf("3rd-level cache: 4 MByte, 16-way set associative, 64 byte line size\n"); 2255 break; 2256 case 0xe4: 2257 printf("3rd-level cache: 8 MByte, 16-way set associative, 64 byte line size\n"); 2258 break; 2259 case 0xea: 2260 printf("3rd-level cache: 12MByte, 24-way set associative, 64 byte line size\n"); 2261 break; 2262 case 0xeb: 2263 printf("3rd-level cache: 18MByte, 24-way set associative, 64 byte line size\n"); 2264 break; 2265 case 0xec: 2266 printf("3rd-level cache: 24MByte, 24-way set associative, 64 byte line size\n"); 2267 break; 2268 case 0xf0: 2269 printf("64-Byte prefetching\n"); 2270 break; 2271 case 0xf1: 2272 printf("128-Byte prefetching\n"); 2273 break; 2274 } 2275 } 2276 2277 static void 2278 print_svm_info(void) 2279 { 2280 u_int features, regs[4]; 2281 uint64_t msr; 2282 int comma; 2283 2284 printf("\n SVM: "); 2285 do_cpuid(0x8000000A, regs); 2286 features = regs[3]; 2287 2288 msr = rdmsr(MSR_VM_CR); 2289 if ((msr & VM_CR_SVMDIS) == VM_CR_SVMDIS) 2290 printf("(disabled in BIOS) "); 2291 2292 if (!bootverbose) { 2293 comma = 0; 2294 if (features & (1 << 0)) { 2295 printf("%sNP", comma ? "," : ""); 2296 comma = 1; 2297 } 2298 if (features & (1 << 3)) { 2299 printf("%sNRIP", comma ? "," : ""); 2300 comma = 1; 2301 } 2302 if (features & (1 << 5)) { 2303 printf("%sVClean", comma ? "," : ""); 2304 comma = 1; 2305 } 2306 if (features & (1 << 6)) { 2307 printf("%sAFlush", comma ? "," : ""); 2308 comma = 1; 2309 } 2310 if (features & (1 << 7)) { 2311 printf("%sDAssist", comma ? "," : ""); 2312 comma = 1; 2313 } 2314 printf("%sNAsids=%d", comma ? "," : "", regs[1]); 2315 return; 2316 } 2317 2318 printf("Features=0x%b", features, 2319 "\020" 2320 "\001NP" /* Nested paging */ 2321 "\002LbrVirt" /* LBR virtualization */ 2322 "\003SVML" /* SVM lock */ 2323 "\004NRIPS" /* NRIP save */ 2324 "\005TscRateMsr" /* MSR based TSC rate control */ 2325 "\006VmcbClean" /* VMCB clean bits */ 2326 "\007FlushByAsid" /* Flush by ASID */ 2327 "\010DecodeAssist" /* Decode assist */ 2328 "\011<b8>" 2329 "\012<b9>" 2330 "\013PauseFilter" /* PAUSE intercept filter */ 2331 "\014EncryptedMcodePatch" 2332 "\015PauseFilterThreshold" /* PAUSE filter threshold */ 2333 "\016AVIC" /* virtual interrupt controller */ 2334 "\017<b14>" 2335 "\020V_VMSAVE_VMLOAD" 2336 "\021vGIF" 2337 "\022GMET" /* Guest Mode Execute Trap */ 2338 "\023<b18>" 2339 "\024<b19>" 2340 "\025GuesSpecCtl" /* Guest Spec_ctl */ 2341 "\026<b21>" 2342 "\027<b22>" 2343 "\030<b23>" 2344 "\031<b24>" 2345 "\032<b25>" 2346 "\033<b26>" 2347 "\034<b27>" 2348 "\035<b28>" 2349 "\036<b29>" 2350 "\037<b30>" 2351 "\040<b31>" 2352 ); 2353 printf("\nRevision=%d, ASIDs=%d", regs[0] & 0xff, regs[1]); 2354 } 2355 2356 #ifdef __i386__ 2357 static void 2358 print_transmeta_info(void) 2359 { 2360 u_int regs[4], nreg = 0; 2361 2362 do_cpuid(0x80860000, regs); 2363 nreg = regs[0]; 2364 if (nreg >= 0x80860001) { 2365 do_cpuid(0x80860001, regs); 2366 printf(" Processor revision %u.%u.%u.%u\n", 2367 (regs[1] >> 24) & 0xff, 2368 (regs[1] >> 16) & 0xff, 2369 (regs[1] >> 8) & 0xff, 2370 regs[1] & 0xff); 2371 } 2372 if (nreg >= 0x80860002) { 2373 do_cpuid(0x80860002, regs); 2374 printf(" Code Morphing Software revision %u.%u.%u-%u-%u\n", 2375 (regs[1] >> 24) & 0xff, 2376 (regs[1] >> 16) & 0xff, 2377 (regs[1] >> 8) & 0xff, 2378 regs[1] & 0xff, 2379 regs[2]); 2380 } 2381 if (nreg >= 0x80860006) { 2382 char info[65]; 2383 do_cpuid(0x80860003, (u_int*) &info[0]); 2384 do_cpuid(0x80860004, (u_int*) &info[16]); 2385 do_cpuid(0x80860005, (u_int*) &info[32]); 2386 do_cpuid(0x80860006, (u_int*) &info[48]); 2387 info[64] = 0; 2388 printf(" %s\n", info); 2389 } 2390 } 2391 #endif 2392 2393 static void 2394 print_via_padlock_info(void) 2395 { 2396 u_int regs[4]; 2397 2398 do_cpuid(0xc0000001, regs); 2399 printf("\n VIA Padlock Features=0x%b", regs[3], 2400 "\020" 2401 "\003RNG" /* RNG */ 2402 "\007AES" /* ACE */ 2403 "\011AES-CTR" /* ACE2 */ 2404 "\013SHA1,SHA256" /* PHE */ 2405 "\015RSA" /* PMM */ 2406 ); 2407 } 2408 2409 static uint32_t 2410 vmx_settable(uint64_t basic, int msr, int true_msr) 2411 { 2412 uint64_t val; 2413 2414 if (basic & (1ULL << 55)) 2415 val = rdmsr(true_msr); 2416 else 2417 val = rdmsr(msr); 2418 2419 /* Just report the controls that can be set to 1. */ 2420 return (val >> 32); 2421 } 2422 2423 static void 2424 print_vmx_info(void) 2425 { 2426 uint64_t basic, msr; 2427 uint32_t entry, exit, mask, pin, proc, proc2; 2428 int comma; 2429 2430 printf("\n VT-x: "); 2431 msr = rdmsr(MSR_IA32_FEATURE_CONTROL); 2432 if (!(msr & IA32_FEATURE_CONTROL_VMX_EN)) 2433 printf("(disabled in BIOS) "); 2434 basic = rdmsr(MSR_VMX_BASIC); 2435 pin = vmx_settable(basic, MSR_VMX_PINBASED_CTLS, 2436 MSR_VMX_TRUE_PINBASED_CTLS); 2437 proc = vmx_settable(basic, MSR_VMX_PROCBASED_CTLS, 2438 MSR_VMX_TRUE_PROCBASED_CTLS); 2439 if (proc & PROCBASED_SECONDARY_CONTROLS) 2440 proc2 = vmx_settable(basic, MSR_VMX_PROCBASED_CTLS2, 2441 MSR_VMX_PROCBASED_CTLS2); 2442 else 2443 proc2 = 0; 2444 exit = vmx_settable(basic, MSR_VMX_EXIT_CTLS, MSR_VMX_TRUE_EXIT_CTLS); 2445 entry = vmx_settable(basic, MSR_VMX_ENTRY_CTLS, MSR_VMX_TRUE_ENTRY_CTLS); 2446 2447 if (!bootverbose) { 2448 comma = 0; 2449 if (exit & VM_EXIT_SAVE_PAT && exit & VM_EXIT_LOAD_PAT && 2450 entry & VM_ENTRY_LOAD_PAT) { 2451 printf("%sPAT", comma ? "," : ""); 2452 comma = 1; 2453 } 2454 if (proc & PROCBASED_HLT_EXITING) { 2455 printf("%sHLT", comma ? "," : ""); 2456 comma = 1; 2457 } 2458 if (proc & PROCBASED_MTF) { 2459 printf("%sMTF", comma ? "," : ""); 2460 comma = 1; 2461 } 2462 if (proc & PROCBASED_PAUSE_EXITING) { 2463 printf("%sPAUSE", comma ? "," : ""); 2464 comma = 1; 2465 } 2466 if (proc2 & PROCBASED2_ENABLE_EPT) { 2467 printf("%sEPT", comma ? "," : ""); 2468 comma = 1; 2469 } 2470 if (proc2 & PROCBASED2_UNRESTRICTED_GUEST) { 2471 printf("%sUG", comma ? "," : ""); 2472 comma = 1; 2473 } 2474 if (proc2 & PROCBASED2_ENABLE_VPID) { 2475 printf("%sVPID", comma ? "," : ""); 2476 comma = 1; 2477 } 2478 if (proc & PROCBASED_USE_TPR_SHADOW && 2479 proc2 & PROCBASED2_VIRTUALIZE_APIC_ACCESSES && 2480 proc2 & PROCBASED2_VIRTUALIZE_X2APIC_MODE && 2481 proc2 & PROCBASED2_APIC_REGISTER_VIRTUALIZATION && 2482 proc2 & PROCBASED2_VIRTUAL_INTERRUPT_DELIVERY) { 2483 printf("%sVID", comma ? "," : ""); 2484 comma = 1; 2485 if (pin & PINBASED_POSTED_INTERRUPT) 2486 printf(",PostIntr"); 2487 } 2488 return; 2489 } 2490 2491 mask = basic >> 32; 2492 printf("Basic Features=0x%b", mask, 2493 "\020" 2494 "\02132PA" /* 32-bit physical addresses */ 2495 "\022SMM" /* SMM dual-monitor */ 2496 "\027INS/OUTS" /* VM-exit info for INS and OUTS */ 2497 "\030TRUE" /* TRUE_CTLS MSRs */ 2498 ); 2499 printf("\n Pin-Based Controls=0x%b", pin, 2500 "\020" 2501 "\001ExtINT" /* External-interrupt exiting */ 2502 "\004NMI" /* NMI exiting */ 2503 "\006VNMI" /* Virtual NMIs */ 2504 "\007PreTmr" /* Activate VMX-preemption timer */ 2505 "\010PostIntr" /* Process posted interrupts */ 2506 ); 2507 printf("\n Primary Processor Controls=0x%b", proc, 2508 "\020" 2509 "\003INTWIN" /* Interrupt-window exiting */ 2510 "\004TSCOff" /* Use TSC offsetting */ 2511 "\010HLT" /* HLT exiting */ 2512 "\012INVLPG" /* INVLPG exiting */ 2513 "\013MWAIT" /* MWAIT exiting */ 2514 "\014RDPMC" /* RDPMC exiting */ 2515 "\015RDTSC" /* RDTSC exiting */ 2516 "\020CR3-LD" /* CR3-load exiting */ 2517 "\021CR3-ST" /* CR3-store exiting */ 2518 "\024CR8-LD" /* CR8-load exiting */ 2519 "\025CR8-ST" /* CR8-store exiting */ 2520 "\026TPR" /* Use TPR shadow */ 2521 "\027NMIWIN" /* NMI-window exiting */ 2522 "\030MOV-DR" /* MOV-DR exiting */ 2523 "\031IO" /* Unconditional I/O exiting */ 2524 "\032IOmap" /* Use I/O bitmaps */ 2525 "\034MTF" /* Monitor trap flag */ 2526 "\035MSRmap" /* Use MSR bitmaps */ 2527 "\036MONITOR" /* MONITOR exiting */ 2528 "\037PAUSE" /* PAUSE exiting */ 2529 ); 2530 if (proc & PROCBASED_SECONDARY_CONTROLS) 2531 printf("\n Secondary Processor Controls=0x%b", proc2, 2532 "\020" 2533 "\001APIC" /* Virtualize APIC accesses */ 2534 "\002EPT" /* Enable EPT */ 2535 "\003DT" /* Descriptor-table exiting */ 2536 "\004RDTSCP" /* Enable RDTSCP */ 2537 "\005x2APIC" /* Virtualize x2APIC mode */ 2538 "\006VPID" /* Enable VPID */ 2539 "\007WBINVD" /* WBINVD exiting */ 2540 "\010UG" /* Unrestricted guest */ 2541 "\011APIC-reg" /* APIC-register virtualization */ 2542 "\012VID" /* Virtual-interrupt delivery */ 2543 "\013PAUSE-loop" /* PAUSE-loop exiting */ 2544 "\014RDRAND" /* RDRAND exiting */ 2545 "\015INVPCID" /* Enable INVPCID */ 2546 "\016VMFUNC" /* Enable VM functions */ 2547 "\017VMCS" /* VMCS shadowing */ 2548 "\020EPT#VE" /* EPT-violation #VE */ 2549 "\021XSAVES" /* Enable XSAVES/XRSTORS */ 2550 ); 2551 printf("\n Exit Controls=0x%b", mask, 2552 "\020" 2553 "\003DR" /* Save debug controls */ 2554 /* Ignore Host address-space size */ 2555 "\015PERF" /* Load MSR_PERF_GLOBAL_CTRL */ 2556 "\020AckInt" /* Acknowledge interrupt on exit */ 2557 "\023PAT-SV" /* Save MSR_PAT */ 2558 "\024PAT-LD" /* Load MSR_PAT */ 2559 "\025EFER-SV" /* Save MSR_EFER */ 2560 "\026EFER-LD" /* Load MSR_EFER */ 2561 "\027PTMR-SV" /* Save VMX-preemption timer value */ 2562 ); 2563 printf("\n Entry Controls=0x%b", mask, 2564 "\020" 2565 "\003DR" /* Save debug controls */ 2566 /* Ignore IA-32e mode guest */ 2567 /* Ignore Entry to SMM */ 2568 /* Ignore Deactivate dual-monitor treatment */ 2569 "\016PERF" /* Load MSR_PERF_GLOBAL_CTRL */ 2570 "\017PAT" /* Load MSR_PAT */ 2571 "\020EFER" /* Load MSR_EFER */ 2572 ); 2573 if (proc & PROCBASED_SECONDARY_CONTROLS && 2574 (proc2 & (PROCBASED2_ENABLE_EPT | PROCBASED2_ENABLE_VPID)) != 0) { 2575 msr = rdmsr(MSR_VMX_EPT_VPID_CAP); 2576 mask = msr; 2577 printf("\n EPT Features=0x%b", mask, 2578 "\020" 2579 "\001XO" /* Execute-only translations */ 2580 "\007PW4" /* Page-walk length of 4 */ 2581 "\011UC" /* EPT paging-structure mem can be UC */ 2582 "\017WB" /* EPT paging-structure mem can be WB */ 2583 "\0212M" /* EPT PDE can map a 2-Mbyte page */ 2584 "\0221G" /* EPT PDPTE can map a 1-Gbyte page */ 2585 "\025INVEPT" /* INVEPT is supported */ 2586 "\026AD" /* Accessed and dirty flags for EPT */ 2587 "\032single" /* INVEPT single-context type */ 2588 "\033all" /* INVEPT all-context type */ 2589 ); 2590 mask = msr >> 32; 2591 printf("\n VPID Features=0x%b", mask, 2592 "\020" 2593 "\001INVVPID" /* INVVPID is supported */ 2594 "\011individual" /* INVVPID individual-address type */ 2595 "\012single" /* INVVPID single-context type */ 2596 "\013all" /* INVVPID all-context type */ 2597 /* INVVPID single-context-retaining-globals type */ 2598 "\014single-globals" 2599 ); 2600 } 2601 } 2602 2603 static void 2604 print_hypervisor_info(void) 2605 { 2606 2607 if (*hv_vendor != '\0') 2608 printf("Hypervisor: Origin = \"%s\"\n", hv_vendor); 2609 } 2610 2611 /* 2612 * Returns the maximum physical address that can be used with the 2613 * current system. 2614 */ 2615 vm_paddr_t 2616 cpu_getmaxphyaddr(void) 2617 { 2618 2619 #if defined(__i386__) 2620 if (!pae_mode) 2621 return (0xffffffff); 2622 #endif 2623 return ((1ULL << cpu_maxphyaddr) - 1); 2624 } 2625