1 /*- 2 * Copyright (c) 1992 Terrence R. Lambert. 3 * Copyright (c) 1982, 1987, 1990 The Regents of the University of California. 4 * Copyright (c) 1997 KATO Takenori. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to Berkeley by 8 * William Jolitz. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by the University of 21 * California, Berkeley and its contributors. 22 * 4. Neither the name of the University nor the names of its contributors 23 * may be used to endorse or promote products derived from this software 24 * without specific prior written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 27 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 28 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 29 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 30 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 31 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 32 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 33 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 34 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 35 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 36 * SUCH DAMAGE. 37 * 38 * from: Id: machdep.c,v 1.193 1996/06/18 01:22:04 bde Exp 39 */ 40 41 #include <sys/cdefs.h> 42 __FBSDID("$FreeBSD$"); 43 44 #include "opt_cpu.h" 45 46 #include <sys/param.h> 47 #include <sys/bus.h> 48 #include <sys/cpu.h> 49 #include <sys/eventhandler.h> 50 #include <sys/limits.h> 51 #include <sys/systm.h> 52 #include <sys/kernel.h> 53 #include <sys/sysctl.h> 54 #include <sys/power.h> 55 56 #include <vm/vm.h> 57 #include <vm/pmap.h> 58 59 #include <machine/asmacros.h> 60 #include <machine/clock.h> 61 #include <machine/cputypes.h> 62 #include <machine/frame.h> 63 #include <machine/intr_machdep.h> 64 #include <machine/md_var.h> 65 #include <machine/segments.h> 66 #include <machine/specialreg.h> 67 68 #include <amd64/vmm/intel/vmx_controls.h> 69 #include <x86/isa/icu.h> 70 #include <x86/vmware.h> 71 72 #ifdef __i386__ 73 #define IDENTBLUE_CYRIX486 0 74 #define IDENTBLUE_IBMCPU 1 75 #define IDENTBLUE_CYRIXM2 2 76 77 static void identifycyrix(void); 78 static void print_transmeta_info(void); 79 #endif 80 static u_int find_cpu_vendor_id(void); 81 static void print_AMD_info(void); 82 static void print_INTEL_info(void); 83 static void print_INTEL_TLB(u_int data); 84 static void print_hypervisor_info(void); 85 static void print_svm_info(void); 86 static void print_via_padlock_info(void); 87 static void print_vmx_info(void); 88 89 #ifdef __i386__ 90 int cpu; /* Are we 386, 386sx, 486, etc? */ 91 int cpu_class; 92 #endif 93 u_int cpu_feature; /* Feature flags */ 94 u_int cpu_feature2; /* Feature flags */ 95 u_int amd_feature; /* AMD feature flags */ 96 u_int amd_feature2; /* AMD feature flags */ 97 u_int amd_rascap; /* AMD RAS capabilities */ 98 u_int amd_pminfo; /* AMD advanced power management info */ 99 u_int amd_extended_feature_extensions; 100 u_int via_feature_rng; /* VIA RNG features */ 101 u_int via_feature_xcrypt; /* VIA ACE features */ 102 u_int cpu_high; /* Highest arg to CPUID */ 103 u_int cpu_exthigh; /* Highest arg to extended CPUID */ 104 u_int cpu_id; /* Stepping ID */ 105 u_int cpu_procinfo; /* HyperThreading Info / Brand Index / CLFUSH */ 106 u_int cpu_procinfo2; /* Multicore info */ 107 char cpu_vendor[20]; /* CPU Origin code */ 108 u_int cpu_vendor_id; /* CPU vendor ID */ 109 u_int cpu_mxcsr_mask; /* Valid bits in mxcsr */ 110 u_int cpu_clflush_line_size = 32; 111 u_int cpu_stdext_feature; /* %ebx */ 112 u_int cpu_stdext_feature2; /* %ecx */ 113 u_int cpu_stdext_feature3; /* %edx */ 114 uint64_t cpu_ia32_arch_caps; 115 u_int cpu_max_ext_state_size; 116 u_int cpu_mon_mwait_flags; /* MONITOR/MWAIT flags (CPUID.05H.ECX) */ 117 u_int cpu_mon_min_size; /* MONITOR minimum range size, bytes */ 118 u_int cpu_mon_max_size; /* MONITOR minimum range size, bytes */ 119 u_int cpu_maxphyaddr; /* Max phys addr width in bits */ 120 u_int cpu_power_eax; /* 06H: Power management leaf, %eax */ 121 u_int cpu_power_ebx; /* 06H: Power management leaf, %ebx */ 122 u_int cpu_power_ecx; /* 06H: Power management leaf, %ecx */ 123 u_int cpu_power_edx; /* 06H: Power management leaf, %edx */ 124 char machine[] = MACHINE; 125 126 SYSCTL_UINT(_hw, OID_AUTO, via_feature_rng, CTLFLAG_RD, 127 &via_feature_rng, 0, 128 "VIA RNG feature available in CPU"); 129 SYSCTL_UINT(_hw, OID_AUTO, via_feature_xcrypt, CTLFLAG_RD, 130 &via_feature_xcrypt, 0, 131 "VIA xcrypt feature available in CPU"); 132 133 #ifdef __amd64__ 134 #ifdef SCTL_MASK32 135 extern int adaptive_machine_arch; 136 #endif 137 138 static int 139 sysctl_hw_machine(SYSCTL_HANDLER_ARGS) 140 { 141 #ifdef SCTL_MASK32 142 static const char machine32[] = "i386"; 143 #endif 144 int error; 145 146 #ifdef SCTL_MASK32 147 if ((req->flags & SCTL_MASK32) != 0 && adaptive_machine_arch) 148 error = SYSCTL_OUT(req, machine32, sizeof(machine32)); 149 else 150 #endif 151 error = SYSCTL_OUT(req, machine, sizeof(machine)); 152 return (error); 153 154 } 155 SYSCTL_PROC(_hw, HW_MACHINE, machine, CTLTYPE_STRING | CTLFLAG_RD | 156 CTLFLAG_CAPRD | CTLFLAG_MPSAFE, NULL, 0, sysctl_hw_machine, "A", "Machine class"); 157 #else 158 SYSCTL_STRING(_hw, HW_MACHINE, machine, CTLFLAG_RD | CTLFLAG_CAPRD, 159 machine, 0, "Machine class"); 160 #endif 161 162 static char cpu_model[128]; 163 SYSCTL_STRING(_hw, HW_MODEL, model, CTLFLAG_RD | CTLFLAG_MPSAFE, 164 cpu_model, 0, "Machine model"); 165 166 static int hw_clockrate; 167 SYSCTL_INT(_hw, OID_AUTO, clockrate, CTLFLAG_RD, 168 &hw_clockrate, 0, "CPU instruction clock rate"); 169 170 u_int hv_base; 171 u_int hv_high; 172 char hv_vendor[16]; 173 SYSCTL_STRING(_hw, OID_AUTO, hv_vendor, CTLFLAG_RD | CTLFLAG_MPSAFE, hv_vendor, 174 0, "Hypervisor vendor"); 175 176 static eventhandler_tag tsc_post_tag; 177 178 static char cpu_brand[48]; 179 180 #ifdef __i386__ 181 #define MAX_BRAND_INDEX 8 182 183 static const char *cpu_brandtable[MAX_BRAND_INDEX + 1] = { 184 NULL, /* No brand */ 185 "Intel Celeron", 186 "Intel Pentium III", 187 "Intel Pentium III Xeon", 188 NULL, 189 NULL, 190 NULL, 191 NULL, 192 "Intel Pentium 4" 193 }; 194 195 static struct { 196 char *cpu_name; 197 int cpu_class; 198 } cpus[] = { 199 { "Intel 80286", CPUCLASS_286 }, /* CPU_286 */ 200 { "i386SX", CPUCLASS_386 }, /* CPU_386SX */ 201 { "i386DX", CPUCLASS_386 }, /* CPU_386 */ 202 { "i486SX", CPUCLASS_486 }, /* CPU_486SX */ 203 { "i486DX", CPUCLASS_486 }, /* CPU_486 */ 204 { "Pentium", CPUCLASS_586 }, /* CPU_586 */ 205 { "Cyrix 486", CPUCLASS_486 }, /* CPU_486DLC */ 206 { "Pentium Pro", CPUCLASS_686 }, /* CPU_686 */ 207 { "Cyrix 5x86", CPUCLASS_486 }, /* CPU_M1SC */ 208 { "Cyrix 6x86", CPUCLASS_486 }, /* CPU_M1 */ 209 { "Blue Lightning", CPUCLASS_486 }, /* CPU_BLUE */ 210 { "Cyrix 6x86MX", CPUCLASS_686 }, /* CPU_M2 */ 211 { "NexGen 586", CPUCLASS_386 }, /* CPU_NX586 (XXX) */ 212 { "Cyrix 486S/DX", CPUCLASS_486 }, /* CPU_CY486DX */ 213 { "Pentium II", CPUCLASS_686 }, /* CPU_PII */ 214 { "Pentium III", CPUCLASS_686 }, /* CPU_PIII */ 215 { "Pentium 4", CPUCLASS_686 }, /* CPU_P4 */ 216 }; 217 #endif 218 219 static struct { 220 char *vendor; 221 u_int vendor_id; 222 } cpu_vendors[] = { 223 { INTEL_VENDOR_ID, CPU_VENDOR_INTEL }, /* GenuineIntel */ 224 { AMD_VENDOR_ID, CPU_VENDOR_AMD }, /* AuthenticAMD */ 225 { HYGON_VENDOR_ID, CPU_VENDOR_HYGON }, /* HygonGenuine */ 226 { CENTAUR_VENDOR_ID, CPU_VENDOR_CENTAUR }, /* CentaurHauls */ 227 #ifdef __i386__ 228 { NSC_VENDOR_ID, CPU_VENDOR_NSC }, /* Geode by NSC */ 229 { CYRIX_VENDOR_ID, CPU_VENDOR_CYRIX }, /* CyrixInstead */ 230 { TRANSMETA_VENDOR_ID, CPU_VENDOR_TRANSMETA }, /* GenuineTMx86 */ 231 { SIS_VENDOR_ID, CPU_VENDOR_SIS }, /* SiS SiS SiS */ 232 { UMC_VENDOR_ID, CPU_VENDOR_UMC }, /* UMC UMC UMC */ 233 { NEXGEN_VENDOR_ID, CPU_VENDOR_NEXGEN }, /* NexGenDriven */ 234 { RISE_VENDOR_ID, CPU_VENDOR_RISE }, /* RiseRiseRise */ 235 #if 0 236 /* XXX CPUID 8000_0000h and 8086_0000h, not 0000_0000h */ 237 { "TransmetaCPU", CPU_VENDOR_TRANSMETA }, 238 #endif 239 #endif 240 }; 241 242 void 243 printcpuinfo(void) 244 { 245 u_int regs[4], i; 246 char *brand; 247 248 printf("CPU: "); 249 #ifdef __i386__ 250 cpu_class = cpus[cpu].cpu_class; 251 strncpy(cpu_model, cpus[cpu].cpu_name, sizeof (cpu_model)); 252 #else 253 strncpy(cpu_model, "Hammer", sizeof (cpu_model)); 254 #endif 255 256 /* Check for extended CPUID information and a processor name. */ 257 if (cpu_exthigh >= 0x80000004) { 258 brand = cpu_brand; 259 for (i = 0x80000002; i < 0x80000005; i++) { 260 do_cpuid(i, regs); 261 memcpy(brand, regs, sizeof(regs)); 262 brand += sizeof(regs); 263 } 264 } 265 266 switch (cpu_vendor_id) { 267 case CPU_VENDOR_INTEL: 268 #ifdef __i386__ 269 if ((cpu_id & 0xf00) > 0x300) { 270 u_int brand_index; 271 272 cpu_model[0] = '\0'; 273 274 switch (cpu_id & 0x3000) { 275 case 0x1000: 276 strcpy(cpu_model, "Overdrive "); 277 break; 278 case 0x2000: 279 strcpy(cpu_model, "Dual "); 280 break; 281 } 282 283 switch (cpu_id & 0xf00) { 284 case 0x400: 285 strcat(cpu_model, "i486 "); 286 /* Check the particular flavor of 486 */ 287 switch (cpu_id & 0xf0) { 288 case 0x00: 289 case 0x10: 290 strcat(cpu_model, "DX"); 291 break; 292 case 0x20: 293 strcat(cpu_model, "SX"); 294 break; 295 case 0x30: 296 strcat(cpu_model, "DX2"); 297 break; 298 case 0x40: 299 strcat(cpu_model, "SL"); 300 break; 301 case 0x50: 302 strcat(cpu_model, "SX2"); 303 break; 304 case 0x70: 305 strcat(cpu_model, 306 "DX2 Write-Back Enhanced"); 307 break; 308 case 0x80: 309 strcat(cpu_model, "DX4"); 310 break; 311 } 312 break; 313 case 0x500: 314 /* Check the particular flavor of 586 */ 315 strcat(cpu_model, "Pentium"); 316 switch (cpu_id & 0xf0) { 317 case 0x00: 318 strcat(cpu_model, " A-step"); 319 break; 320 case 0x10: 321 strcat(cpu_model, "/P5"); 322 break; 323 case 0x20: 324 strcat(cpu_model, "/P54C"); 325 break; 326 case 0x30: 327 strcat(cpu_model, "/P24T"); 328 break; 329 case 0x40: 330 strcat(cpu_model, "/P55C"); 331 break; 332 case 0x70: 333 strcat(cpu_model, "/P54C"); 334 break; 335 case 0x80: 336 strcat(cpu_model, "/P55C (quarter-micron)"); 337 break; 338 default: 339 /* nothing */ 340 break; 341 } 342 #if defined(I586_CPU) && !defined(NO_F00F_HACK) 343 /* 344 * XXX - If/when Intel fixes the bug, this 345 * should also check the version of the 346 * CPU, not just that it's a Pentium. 347 */ 348 has_f00f_bug = 1; 349 #endif 350 break; 351 case 0x600: 352 /* Check the particular flavor of 686 */ 353 switch (cpu_id & 0xf0) { 354 case 0x00: 355 strcat(cpu_model, "Pentium Pro A-step"); 356 break; 357 case 0x10: 358 strcat(cpu_model, "Pentium Pro"); 359 break; 360 case 0x30: 361 case 0x50: 362 case 0x60: 363 strcat(cpu_model, 364 "Pentium II/Pentium II Xeon/Celeron"); 365 cpu = CPU_PII; 366 break; 367 case 0x70: 368 case 0x80: 369 case 0xa0: 370 case 0xb0: 371 strcat(cpu_model, 372 "Pentium III/Pentium III Xeon/Celeron"); 373 cpu = CPU_PIII; 374 break; 375 default: 376 strcat(cpu_model, "Unknown 80686"); 377 break; 378 } 379 break; 380 case 0xf00: 381 strcat(cpu_model, "Pentium 4"); 382 cpu = CPU_P4; 383 break; 384 default: 385 strcat(cpu_model, "unknown"); 386 break; 387 } 388 389 /* 390 * If we didn't get a brand name from the extended 391 * CPUID, try to look it up in the brand table. 392 */ 393 if (cpu_high > 0 && *cpu_brand == '\0') { 394 brand_index = cpu_procinfo & CPUID_BRAND_INDEX; 395 if (brand_index <= MAX_BRAND_INDEX && 396 cpu_brandtable[brand_index] != NULL) 397 strcpy(cpu_brand, 398 cpu_brandtable[brand_index]); 399 } 400 } 401 #else 402 /* Please make up your mind folks! */ 403 strcat(cpu_model, "EM64T"); 404 #endif 405 break; 406 case CPU_VENDOR_AMD: 407 /* 408 * Values taken from AMD Processor Recognition 409 * http://www.amd.com/K6/k6docs/pdf/20734g.pdf 410 * (also describes ``Features'' encodings. 411 */ 412 strcpy(cpu_model, "AMD "); 413 #ifdef __i386__ 414 switch (cpu_id & 0xFF0) { 415 case 0x410: 416 strcat(cpu_model, "Standard Am486DX"); 417 break; 418 case 0x430: 419 strcat(cpu_model, "Enhanced Am486DX2 Write-Through"); 420 break; 421 case 0x470: 422 strcat(cpu_model, "Enhanced Am486DX2 Write-Back"); 423 break; 424 case 0x480: 425 strcat(cpu_model, "Enhanced Am486DX4/Am5x86 Write-Through"); 426 break; 427 case 0x490: 428 strcat(cpu_model, "Enhanced Am486DX4/Am5x86 Write-Back"); 429 break; 430 case 0x4E0: 431 strcat(cpu_model, "Am5x86 Write-Through"); 432 break; 433 case 0x4F0: 434 strcat(cpu_model, "Am5x86 Write-Back"); 435 break; 436 case 0x500: 437 strcat(cpu_model, "K5 model 0"); 438 break; 439 case 0x510: 440 strcat(cpu_model, "K5 model 1"); 441 break; 442 case 0x520: 443 strcat(cpu_model, "K5 PR166 (model 2)"); 444 break; 445 case 0x530: 446 strcat(cpu_model, "K5 PR200 (model 3)"); 447 break; 448 case 0x560: 449 strcat(cpu_model, "K6"); 450 break; 451 case 0x570: 452 strcat(cpu_model, "K6 266 (model 1)"); 453 break; 454 case 0x580: 455 strcat(cpu_model, "K6-2"); 456 break; 457 case 0x590: 458 strcat(cpu_model, "K6-III"); 459 break; 460 case 0x5a0: 461 strcat(cpu_model, "Geode LX"); 462 break; 463 default: 464 strcat(cpu_model, "Unknown"); 465 break; 466 } 467 #else 468 if ((cpu_id & 0xf00) == 0xf00) 469 strcat(cpu_model, "AMD64 Processor"); 470 else 471 strcat(cpu_model, "Unknown"); 472 #endif 473 break; 474 #ifdef __i386__ 475 case CPU_VENDOR_CYRIX: 476 strcpy(cpu_model, "Cyrix "); 477 switch (cpu_id & 0xff0) { 478 case 0x440: 479 strcat(cpu_model, "MediaGX"); 480 break; 481 case 0x520: 482 strcat(cpu_model, "6x86"); 483 break; 484 case 0x540: 485 cpu_class = CPUCLASS_586; 486 strcat(cpu_model, "GXm"); 487 break; 488 case 0x600: 489 strcat(cpu_model, "6x86MX"); 490 break; 491 default: 492 /* 493 * Even though CPU supports the cpuid 494 * instruction, it can be disabled. 495 * Therefore, this routine supports all Cyrix 496 * CPUs. 497 */ 498 switch (cyrix_did & 0xf0) { 499 case 0x00: 500 switch (cyrix_did & 0x0f) { 501 case 0x00: 502 strcat(cpu_model, "486SLC"); 503 break; 504 case 0x01: 505 strcat(cpu_model, "486DLC"); 506 break; 507 case 0x02: 508 strcat(cpu_model, "486SLC2"); 509 break; 510 case 0x03: 511 strcat(cpu_model, "486DLC2"); 512 break; 513 case 0x04: 514 strcat(cpu_model, "486SRx"); 515 break; 516 case 0x05: 517 strcat(cpu_model, "486DRx"); 518 break; 519 case 0x06: 520 strcat(cpu_model, "486SRx2"); 521 break; 522 case 0x07: 523 strcat(cpu_model, "486DRx2"); 524 break; 525 case 0x08: 526 strcat(cpu_model, "486SRu"); 527 break; 528 case 0x09: 529 strcat(cpu_model, "486DRu"); 530 break; 531 case 0x0a: 532 strcat(cpu_model, "486SRu2"); 533 break; 534 case 0x0b: 535 strcat(cpu_model, "486DRu2"); 536 break; 537 default: 538 strcat(cpu_model, "Unknown"); 539 break; 540 } 541 break; 542 case 0x10: 543 switch (cyrix_did & 0x0f) { 544 case 0x00: 545 strcat(cpu_model, "486S"); 546 break; 547 case 0x01: 548 strcat(cpu_model, "486S2"); 549 break; 550 case 0x02: 551 strcat(cpu_model, "486Se"); 552 break; 553 case 0x03: 554 strcat(cpu_model, "486S2e"); 555 break; 556 case 0x0a: 557 strcat(cpu_model, "486DX"); 558 break; 559 case 0x0b: 560 strcat(cpu_model, "486DX2"); 561 break; 562 case 0x0f: 563 strcat(cpu_model, "486DX4"); 564 break; 565 default: 566 strcat(cpu_model, "Unknown"); 567 break; 568 } 569 break; 570 case 0x20: 571 if ((cyrix_did & 0x0f) < 8) 572 strcat(cpu_model, "6x86"); /* Where did you get it? */ 573 else 574 strcat(cpu_model, "5x86"); 575 break; 576 case 0x30: 577 strcat(cpu_model, "6x86"); 578 break; 579 case 0x40: 580 if ((cyrix_did & 0xf000) == 0x3000) { 581 cpu_class = CPUCLASS_586; 582 strcat(cpu_model, "GXm"); 583 } else 584 strcat(cpu_model, "MediaGX"); 585 break; 586 case 0x50: 587 strcat(cpu_model, "6x86MX"); 588 break; 589 case 0xf0: 590 switch (cyrix_did & 0x0f) { 591 case 0x0d: 592 strcat(cpu_model, "Overdrive CPU"); 593 break; 594 case 0x0e: 595 strcpy(cpu_model, "Texas Instruments 486SXL"); 596 break; 597 case 0x0f: 598 strcat(cpu_model, "486SLC/DLC"); 599 break; 600 default: 601 strcat(cpu_model, "Unknown"); 602 break; 603 } 604 break; 605 default: 606 strcat(cpu_model, "Unknown"); 607 break; 608 } 609 break; 610 } 611 break; 612 case CPU_VENDOR_RISE: 613 strcpy(cpu_model, "Rise "); 614 switch (cpu_id & 0xff0) { 615 case 0x500: /* 6401 and 6441 (Kirin) */ 616 case 0x520: /* 6510 (Lynx) */ 617 strcat(cpu_model, "mP6"); 618 break; 619 default: 620 strcat(cpu_model, "Unknown"); 621 } 622 break; 623 #endif 624 case CPU_VENDOR_CENTAUR: 625 #ifdef __i386__ 626 switch (cpu_id & 0xff0) { 627 case 0x540: 628 strcpy(cpu_model, "IDT WinChip C6"); 629 break; 630 case 0x580: 631 strcpy(cpu_model, "IDT WinChip 2"); 632 break; 633 case 0x590: 634 strcpy(cpu_model, "IDT WinChip 3"); 635 break; 636 case 0x660: 637 strcpy(cpu_model, "VIA C3 Samuel"); 638 break; 639 case 0x670: 640 if (cpu_id & 0x8) 641 strcpy(cpu_model, "VIA C3 Ezra"); 642 else 643 strcpy(cpu_model, "VIA C3 Samuel 2"); 644 break; 645 case 0x680: 646 strcpy(cpu_model, "VIA C3 Ezra-T"); 647 break; 648 case 0x690: 649 strcpy(cpu_model, "VIA C3 Nehemiah"); 650 break; 651 case 0x6a0: 652 case 0x6d0: 653 strcpy(cpu_model, "VIA C7 Esther"); 654 break; 655 case 0x6f0: 656 strcpy(cpu_model, "VIA Nano"); 657 break; 658 default: 659 strcpy(cpu_model, "VIA/IDT Unknown"); 660 } 661 #else 662 strcpy(cpu_model, "VIA "); 663 if ((cpu_id & 0xff0) == 0x6f0) 664 strcat(cpu_model, "Nano Processor"); 665 else 666 strcat(cpu_model, "Unknown"); 667 #endif 668 break; 669 #ifdef __i386__ 670 case CPU_VENDOR_IBM: 671 strcpy(cpu_model, "Blue Lightning CPU"); 672 break; 673 case CPU_VENDOR_NSC: 674 switch (cpu_id & 0xff0) { 675 case 0x540: 676 strcpy(cpu_model, "Geode SC1100"); 677 cpu = CPU_GEODE1100; 678 break; 679 default: 680 strcpy(cpu_model, "Geode/NSC unknown"); 681 break; 682 } 683 break; 684 #endif 685 case CPU_VENDOR_HYGON: 686 strcpy(cpu_model, "Hygon "); 687 #ifdef __i386__ 688 strcat(cpu_model, "Unknown"); 689 #else 690 if ((cpu_id & 0xf00) == 0xf00) 691 strcat(cpu_model, "AMD64 Processor"); 692 else 693 strcat(cpu_model, "Unknown"); 694 #endif 695 break; 696 697 default: 698 strcat(cpu_model, "Unknown"); 699 break; 700 } 701 702 /* 703 * Replace cpu_model with cpu_brand minus leading spaces if 704 * we have one. 705 */ 706 brand = cpu_brand; 707 while (*brand == ' ') 708 ++brand; 709 if (*brand != '\0') 710 strcpy(cpu_model, brand); 711 712 printf("%s (", cpu_model); 713 if (tsc_freq != 0) { 714 hw_clockrate = (tsc_freq + 5000) / 1000000; 715 printf("%jd.%02d-MHz ", 716 (intmax_t)(tsc_freq + 4999) / 1000000, 717 (u_int)((tsc_freq + 4999) / 10000) % 100); 718 } 719 #ifdef __i386__ 720 switch(cpu_class) { 721 case CPUCLASS_286: 722 printf("286"); 723 break; 724 case CPUCLASS_386: 725 printf("386"); 726 break; 727 #if defined(I486_CPU) 728 case CPUCLASS_486: 729 printf("486"); 730 break; 731 #endif 732 #if defined(I586_CPU) 733 case CPUCLASS_586: 734 printf("586"); 735 break; 736 #endif 737 #if defined(I686_CPU) 738 case CPUCLASS_686: 739 printf("686"); 740 break; 741 #endif 742 default: 743 printf("Unknown"); /* will panic below... */ 744 } 745 #else 746 printf("K8"); 747 #endif 748 printf("-class CPU)\n"); 749 if (*cpu_vendor) 750 printf(" Origin=\"%s\"", cpu_vendor); 751 if (cpu_id) 752 printf(" Id=0x%x", cpu_id); 753 754 if (cpu_vendor_id == CPU_VENDOR_INTEL || 755 cpu_vendor_id == CPU_VENDOR_AMD || 756 cpu_vendor_id == CPU_VENDOR_HYGON || 757 cpu_vendor_id == CPU_VENDOR_CENTAUR || 758 #ifdef __i386__ 759 cpu_vendor_id == CPU_VENDOR_TRANSMETA || 760 cpu_vendor_id == CPU_VENDOR_RISE || 761 cpu_vendor_id == CPU_VENDOR_NSC || 762 (cpu_vendor_id == CPU_VENDOR_CYRIX && ((cpu_id & 0xf00) > 0x500)) || 763 #endif 764 0) { 765 printf(" Family=0x%x", CPUID_TO_FAMILY(cpu_id)); 766 printf(" Model=0x%x", CPUID_TO_MODEL(cpu_id)); 767 printf(" Stepping=%u", cpu_id & CPUID_STEPPING); 768 #ifdef __i386__ 769 if (cpu_vendor_id == CPU_VENDOR_CYRIX) 770 printf("\n DIR=0x%04x", cyrix_did); 771 #endif 772 773 /* 774 * AMD CPUID Specification 775 * http://support.amd.com/us/Embedded_TechDocs/25481.pdf 776 * 777 * Intel Processor Identification and CPUID Instruction 778 * http://www.intel.com/assets/pdf/appnote/241618.pdf 779 */ 780 if (cpu_high > 0) { 781 /* 782 * Here we should probably set up flags indicating 783 * whether or not various features are available. 784 * The interesting ones are probably VME, PSE, PAE, 785 * and PGE. The code already assumes without bothering 786 * to check that all CPUs >= Pentium have a TSC and 787 * MSRs. 788 */ 789 printf("\n Features=0x%b", cpu_feature, 790 "\020" 791 "\001FPU" /* Integral FPU */ 792 "\002VME" /* Extended VM86 mode support */ 793 "\003DE" /* Debugging Extensions (CR4.DE) */ 794 "\004PSE" /* 4MByte page tables */ 795 "\005TSC" /* Timestamp counter */ 796 "\006MSR" /* Machine specific registers */ 797 "\007PAE" /* Physical address extension */ 798 "\010MCE" /* Machine Check support */ 799 "\011CX8" /* CMPEXCH8 instruction */ 800 "\012APIC" /* SMP local APIC */ 801 "\013oldMTRR" /* Previous implementation of MTRR */ 802 "\014SEP" /* Fast System Call */ 803 "\015MTRR" /* Memory Type Range Registers */ 804 "\016PGE" /* PG_G (global bit) support */ 805 "\017MCA" /* Machine Check Architecture */ 806 "\020CMOV" /* CMOV instruction */ 807 "\021PAT" /* Page attributes table */ 808 "\022PSE36" /* 36 bit address space support */ 809 "\023PN" /* Processor Serial number */ 810 "\024CLFLUSH" /* Has the CLFLUSH instruction */ 811 "\025<b20>" 812 "\026DTS" /* Debug Trace Store */ 813 "\027ACPI" /* ACPI support */ 814 "\030MMX" /* MMX instructions */ 815 "\031FXSR" /* FXSAVE/FXRSTOR */ 816 "\032SSE" /* Streaming SIMD Extensions */ 817 "\033SSE2" /* Streaming SIMD Extensions #2 */ 818 "\034SS" /* Self snoop */ 819 "\035HTT" /* Hyperthreading (see EBX bit 16-23) */ 820 "\036TM" /* Thermal Monitor clock slowdown */ 821 "\037IA64" /* CPU can execute IA64 instructions */ 822 "\040PBE" /* Pending Break Enable */ 823 ); 824 825 if (cpu_feature2 != 0) { 826 printf("\n Features2=0x%b", cpu_feature2, 827 "\020" 828 "\001SSE3" /* SSE3 */ 829 "\002PCLMULQDQ" /* Carry-Less Mul Quadword */ 830 "\003DTES64" /* 64-bit Debug Trace */ 831 "\004MON" /* MONITOR/MWAIT Instructions */ 832 "\005DS_CPL" /* CPL Qualified Debug Store */ 833 "\006VMX" /* Virtual Machine Extensions */ 834 "\007SMX" /* Safer Mode Extensions */ 835 "\010EST" /* Enhanced SpeedStep */ 836 "\011TM2" /* Thermal Monitor 2 */ 837 "\012SSSE3" /* SSSE3 */ 838 "\013CNXT-ID" /* L1 context ID available */ 839 "\014SDBG" /* IA32 silicon debug */ 840 "\015FMA" /* Fused Multiply Add */ 841 "\016CX16" /* CMPXCHG16B Instruction */ 842 "\017xTPR" /* Send Task Priority Messages*/ 843 "\020PDCM" /* Perf/Debug Capability MSR */ 844 "\021<b16>" 845 "\022PCID" /* Process-context Identifiers*/ 846 "\023DCA" /* Direct Cache Access */ 847 "\024SSE4.1" /* SSE 4.1 */ 848 "\025SSE4.2" /* SSE 4.2 */ 849 "\026x2APIC" /* xAPIC Extensions */ 850 "\027MOVBE" /* MOVBE Instruction */ 851 "\030POPCNT" /* POPCNT Instruction */ 852 "\031TSCDLT" /* TSC-Deadline Timer */ 853 "\032AESNI" /* AES Crypto */ 854 "\033XSAVE" /* XSAVE/XRSTOR States */ 855 "\034OSXSAVE" /* OS-Enabled State Management*/ 856 "\035AVX" /* Advanced Vector Extensions */ 857 "\036F16C" /* Half-precision conversions */ 858 "\037RDRAND" /* RDRAND Instruction */ 859 "\040HV" /* Hypervisor */ 860 ); 861 } 862 863 if (amd_feature != 0) { 864 printf("\n AMD Features=0x%b", amd_feature, 865 "\020" /* in hex */ 866 "\001<s0>" /* Same */ 867 "\002<s1>" /* Same */ 868 "\003<s2>" /* Same */ 869 "\004<s3>" /* Same */ 870 "\005<s4>" /* Same */ 871 "\006<s5>" /* Same */ 872 "\007<s6>" /* Same */ 873 "\010<s7>" /* Same */ 874 "\011<s8>" /* Same */ 875 "\012<s9>" /* Same */ 876 "\013<b10>" /* Undefined */ 877 "\014SYSCALL" /* Have SYSCALL/SYSRET */ 878 "\015<s12>" /* Same */ 879 "\016<s13>" /* Same */ 880 "\017<s14>" /* Same */ 881 "\020<s15>" /* Same */ 882 "\021<s16>" /* Same */ 883 "\022<s17>" /* Same */ 884 "\023<b18>" /* Reserved, unknown */ 885 "\024MP" /* Multiprocessor Capable */ 886 "\025NX" /* Has EFER.NXE, NX */ 887 "\026<b21>" /* Undefined */ 888 "\027MMX+" /* AMD MMX Extensions */ 889 "\030<s23>" /* Same */ 890 "\031<s24>" /* Same */ 891 "\032FFXSR" /* Fast FXSAVE/FXRSTOR */ 892 "\033Page1GB" /* 1-GB large page support */ 893 "\034RDTSCP" /* RDTSCP */ 894 "\035<b28>" /* Undefined */ 895 "\036LM" /* 64 bit long mode */ 896 "\0373DNow!+" /* AMD 3DNow! Extensions */ 897 "\0403DNow!" /* AMD 3DNow! */ 898 ); 899 } 900 901 if (amd_feature2 != 0) { 902 printf("\n AMD Features2=0x%b", amd_feature2, 903 "\020" 904 "\001LAHF" /* LAHF/SAHF in long mode */ 905 "\002CMP" /* CMP legacy */ 906 "\003SVM" /* Secure Virtual Mode */ 907 "\004ExtAPIC" /* Extended APIC register */ 908 "\005CR8" /* CR8 in legacy mode */ 909 "\006ABM" /* LZCNT instruction */ 910 "\007SSE4A" /* SSE4A */ 911 "\010MAS" /* Misaligned SSE mode */ 912 "\011Prefetch" /* 3DNow! Prefetch/PrefetchW */ 913 "\012OSVW" /* OS visible workaround */ 914 "\013IBS" /* Instruction based sampling */ 915 "\014XOP" /* XOP extended instructions */ 916 "\015SKINIT" /* SKINIT/STGI */ 917 "\016WDT" /* Watchdog timer */ 918 "\017<b14>" 919 "\020LWP" /* Lightweight Profiling */ 920 "\021FMA4" /* 4-operand FMA instructions */ 921 "\022TCE" /* Translation Cache Extension */ 922 "\023<b18>" 923 "\024NodeId" /* NodeId MSR support */ 924 "\025<b20>" 925 "\026TBM" /* Trailing Bit Manipulation */ 926 "\027Topology" /* Topology Extensions */ 927 "\030PCXC" /* Core perf count */ 928 "\031PNXC" /* NB perf count */ 929 "\032<b25>" 930 "\033DBE" /* Data Breakpoint extension */ 931 "\034PTSC" /* Performance TSC */ 932 "\035PL2I" /* L2I perf count */ 933 "\036MWAITX" /* MONITORX/MWAITX instructions */ 934 "\037ADMSKX" /* Address mask extension */ 935 "\040<b31>" 936 ); 937 } 938 939 if (cpu_stdext_feature != 0) { 940 printf("\n Structured Extended Features=0x%b", 941 cpu_stdext_feature, 942 "\020" 943 /* RDFSBASE/RDGSBASE/WRFSBASE/WRGSBASE */ 944 "\001FSGSBASE" 945 "\002TSCADJ" 946 "\003SGX" 947 /* Bit Manipulation Instructions */ 948 "\004BMI1" 949 /* Hardware Lock Elision */ 950 "\005HLE" 951 /* Advanced Vector Instructions 2 */ 952 "\006AVX2" 953 /* FDP_EXCPTN_ONLY */ 954 "\007FDPEXC" 955 /* Supervisor Mode Execution Prot. */ 956 "\010SMEP" 957 /* Bit Manipulation Instructions */ 958 "\011BMI2" 959 "\012ERMS" 960 /* Invalidate Processor Context ID */ 961 "\013INVPCID" 962 /* Restricted Transactional Memory */ 963 "\014RTM" 964 "\015PQM" 965 "\016NFPUSG" 966 /* Intel Memory Protection Extensions */ 967 "\017MPX" 968 "\020PQE" 969 /* AVX512 Foundation */ 970 "\021AVX512F" 971 "\022AVX512DQ" 972 /* Enhanced NRBG */ 973 "\023RDSEED" 974 /* ADCX + ADOX */ 975 "\024ADX" 976 /* Supervisor Mode Access Prevention */ 977 "\025SMAP" 978 "\026AVX512IFMA" 979 /* Formerly PCOMMIT */ 980 "\027<b22>" 981 "\030CLFLUSHOPT" 982 "\031CLWB" 983 "\032PROCTRACE" 984 "\033AVX512PF" 985 "\034AVX512ER" 986 "\035AVX512CD" 987 "\036SHA" 988 "\037AVX512BW" 989 "\040AVX512VL" 990 ); 991 } 992 993 if (cpu_stdext_feature2 != 0) { 994 printf("\n Structured Extended Features2=0x%b", 995 cpu_stdext_feature2, 996 "\020" 997 "\001PREFETCHWT1" 998 "\002AVX512VBMI" 999 "\003UMIP" 1000 "\004PKU" 1001 "\005OSPKE" 1002 "\006WAITPKG" 1003 "\007AVX512VBMI2" 1004 "\011GFNI" 1005 "\012VAES" 1006 "\013VPCLMULQDQ" 1007 "\014AVX512VNNI" 1008 "\015AVX512BITALG" 1009 "\016TME" 1010 "\017AVX512VPOPCNTDQ" 1011 "\021LA57" 1012 "\027RDPID" 1013 "\032CLDEMOTE" 1014 "\034MOVDIRI" 1015 "\035MOVDIR64B" 1016 "\036ENQCMD" 1017 "\037SGXLC" 1018 ); 1019 } 1020 1021 if (cpu_stdext_feature3 != 0) { 1022 printf("\n Structured Extended Features3=0x%b", 1023 cpu_stdext_feature3, 1024 "\020" 1025 "\003AVX512_4VNNIW" 1026 "\004AVX512_4FMAPS" 1027 "\005FSRM" 1028 "\011AVX512VP2INTERSECT" 1029 "\012MCUOPT" 1030 "\013MD_CLEAR" 1031 "\016TSXFA" 1032 "\023PCONFIG" 1033 "\025IBT" 1034 "\033IBPB" 1035 "\034STIBP" 1036 "\035L1DFL" 1037 "\036ARCH_CAP" 1038 "\037CORE_CAP" 1039 "\040SSBD" 1040 ); 1041 } 1042 1043 if ((cpu_feature2 & CPUID2_XSAVE) != 0) { 1044 cpuid_count(0xd, 0x1, regs); 1045 if (regs[0] != 0) { 1046 printf("\n XSAVE Features=0x%b", 1047 regs[0], 1048 "\020" 1049 "\001XSAVEOPT" 1050 "\002XSAVEC" 1051 "\003XINUSE" 1052 "\004XSAVES"); 1053 } 1054 } 1055 1056 if (cpu_ia32_arch_caps != 0) { 1057 printf("\n IA32_ARCH_CAPS=0x%b", 1058 (u_int)cpu_ia32_arch_caps, 1059 "\020" 1060 "\001RDCL_NO" 1061 "\002IBRS_ALL" 1062 "\003RSBA" 1063 "\004SKIP_L1DFL_VME" 1064 "\005SSB_NO" 1065 "\006MDS_NO" 1066 "\010TSX_CTRL" 1067 "\011TAA_NO" 1068 ); 1069 } 1070 1071 if (amd_extended_feature_extensions != 0) { 1072 u_int amd_fe_masked; 1073 1074 amd_fe_masked = amd_extended_feature_extensions; 1075 if ((amd_fe_masked & AMDFEID_IBRS) == 0) 1076 amd_fe_masked &= 1077 ~(AMDFEID_IBRS_ALWAYSON | 1078 AMDFEID_PREFER_IBRS); 1079 if ((amd_fe_masked & AMDFEID_STIBP) == 0) 1080 amd_fe_masked &= 1081 ~AMDFEID_STIBP_ALWAYSON; 1082 1083 printf("\n " 1084 "AMD Extended Feature Extensions ID EBX=" 1085 "0x%b", amd_fe_masked, 1086 "\020" 1087 "\001CLZERO" 1088 "\002IRPerf" 1089 "\003XSaveErPtr" 1090 "\005RDPRU" 1091 "\011MCOMMIT" 1092 "\012WBNOINVD" 1093 "\015IBPB" 1094 "\017IBRS" 1095 "\020STIBP" 1096 "\021IBRS_ALWAYSON" 1097 "\022STIBP_ALWAYSON" 1098 "\023PREFER_IBRS" 1099 "\030PPIN" 1100 "\031SSBD" 1101 "\032VIRT_SSBD" 1102 "\033SSB_NO" 1103 ); 1104 } 1105 1106 if (via_feature_rng != 0 || via_feature_xcrypt != 0) 1107 print_via_padlock_info(); 1108 1109 if (cpu_feature2 & CPUID2_VMX) 1110 print_vmx_info(); 1111 1112 if (amd_feature2 & AMDID2_SVM) 1113 print_svm_info(); 1114 1115 if ((cpu_feature & CPUID_HTT) && 1116 (cpu_vendor_id == CPU_VENDOR_AMD || 1117 cpu_vendor_id == CPU_VENDOR_HYGON)) 1118 cpu_feature &= ~CPUID_HTT; 1119 1120 /* 1121 * If this CPU supports P-state invariant TSC then 1122 * mention the capability. 1123 */ 1124 if (tsc_is_invariant) { 1125 printf("\n TSC: P-state invariant"); 1126 if (tsc_perf_stat) 1127 printf(", performance statistics"); 1128 } 1129 } 1130 #ifdef __i386__ 1131 } else if (cpu_vendor_id == CPU_VENDOR_CYRIX) { 1132 printf(" DIR=0x%04x", cyrix_did); 1133 printf(" Stepping=%u", (cyrix_did & 0xf000) >> 12); 1134 printf(" Revision=%u", (cyrix_did & 0x0f00) >> 8); 1135 #ifndef CYRIX_CACHE_REALLY_WORKS 1136 if (cpu == CPU_M1 && (cyrix_did & 0xff00) < 0x1700) 1137 printf("\n CPU cache: write-through mode"); 1138 #endif 1139 #endif 1140 } 1141 1142 /* Avoid ugly blank lines: only print newline when we have to. */ 1143 if (*cpu_vendor || cpu_id) 1144 printf("\n"); 1145 1146 if (bootverbose) { 1147 if (cpu_vendor_id == CPU_VENDOR_AMD || 1148 cpu_vendor_id == CPU_VENDOR_HYGON) 1149 print_AMD_info(); 1150 else if (cpu_vendor_id == CPU_VENDOR_INTEL) 1151 print_INTEL_info(); 1152 #ifdef __i386__ 1153 else if (cpu_vendor_id == CPU_VENDOR_TRANSMETA) 1154 print_transmeta_info(); 1155 #endif 1156 } 1157 1158 print_hypervisor_info(); 1159 } 1160 1161 #ifdef __i386__ 1162 void 1163 panicifcpuunsupported(void) 1164 { 1165 1166 #if !defined(lint) 1167 #if !defined(I486_CPU) && !defined(I586_CPU) && !defined(I686_CPU) 1168 #error This kernel is not configured for one of the supported CPUs 1169 #endif 1170 #else /* lint */ 1171 #endif /* lint */ 1172 /* 1173 * Now that we have told the user what they have, 1174 * let them know if that machine type isn't configured. 1175 */ 1176 switch (cpu_class) { 1177 case CPUCLASS_286: /* a 286 should not make it this far, anyway */ 1178 case CPUCLASS_386: 1179 #if !defined(I486_CPU) 1180 case CPUCLASS_486: 1181 #endif 1182 #if !defined(I586_CPU) 1183 case CPUCLASS_586: 1184 #endif 1185 #if !defined(I686_CPU) 1186 case CPUCLASS_686: 1187 #endif 1188 panic("CPU class not configured"); 1189 default: 1190 break; 1191 } 1192 } 1193 1194 static volatile u_int trap_by_rdmsr; 1195 1196 /* 1197 * Special exception 6 handler. 1198 * The rdmsr instruction generates invalid opcodes fault on 486-class 1199 * Cyrix CPU. Stacked eip register points the rdmsr instruction in the 1200 * function identblue() when this handler is called. Stacked eip should 1201 * be advanced. 1202 */ 1203 inthand_t bluetrap6; 1204 __asm 1205 (" \n\ 1206 .text \n\ 1207 .p2align 2,0x90 \n\ 1208 .type " __XSTRING(CNAME(bluetrap6)) ",@function \n\ 1209 " __XSTRING(CNAME(bluetrap6)) ": \n\ 1210 ss \n\ 1211 movl $0xa8c1d," __XSTRING(CNAME(trap_by_rdmsr)) " \n\ 1212 addl $2, (%esp) /* rdmsr is a 2-byte instruction */ \n\ 1213 iret \n\ 1214 "); 1215 1216 /* 1217 * Special exception 13 handler. 1218 * Accessing non-existent MSR generates general protection fault. 1219 */ 1220 inthand_t bluetrap13; 1221 __asm 1222 (" \n\ 1223 .text \n\ 1224 .p2align 2,0x90 \n\ 1225 .type " __XSTRING(CNAME(bluetrap13)) ",@function \n\ 1226 " __XSTRING(CNAME(bluetrap13)) ": \n\ 1227 ss \n\ 1228 movl $0xa89c4," __XSTRING(CNAME(trap_by_rdmsr)) " \n\ 1229 popl %eax /* discard error code */ \n\ 1230 addl $2, (%esp) /* rdmsr is a 2-byte instruction */ \n\ 1231 iret \n\ 1232 "); 1233 1234 /* 1235 * Distinguish IBM Blue Lightning CPU from Cyrix CPUs that does not 1236 * support cpuid instruction. This function should be called after 1237 * loading interrupt descriptor table register. 1238 * 1239 * I don't like this method that handles fault, but I couldn't get 1240 * information for any other methods. Does blue giant know? 1241 */ 1242 static int 1243 identblue(void) 1244 { 1245 1246 trap_by_rdmsr = 0; 1247 1248 /* 1249 * Cyrix 486-class CPU does not support rdmsr instruction. 1250 * The rdmsr instruction generates invalid opcode fault, and exception 1251 * will be trapped by bluetrap6() on Cyrix 486-class CPU. The 1252 * bluetrap6() set the magic number to trap_by_rdmsr. 1253 */ 1254 setidt(IDT_UD, bluetrap6, SDT_SYS386TGT, SEL_KPL, 1255 GSEL(GCODE_SEL, SEL_KPL)); 1256 1257 /* 1258 * Certain BIOS disables cpuid instruction of Cyrix 6x86MX CPU. 1259 * In this case, rdmsr generates general protection fault, and 1260 * exception will be trapped by bluetrap13(). 1261 */ 1262 setidt(IDT_GP, bluetrap13, SDT_SYS386TGT, SEL_KPL, 1263 GSEL(GCODE_SEL, SEL_KPL)); 1264 1265 rdmsr(0x1002); /* Cyrix CPU generates fault. */ 1266 1267 if (trap_by_rdmsr == 0xa8c1d) 1268 return IDENTBLUE_CYRIX486; 1269 else if (trap_by_rdmsr == 0xa89c4) 1270 return IDENTBLUE_CYRIXM2; 1271 return IDENTBLUE_IBMCPU; 1272 } 1273 1274 /* 1275 * identifycyrix() set lower 16 bits of cyrix_did as follows: 1276 * 1277 * F E D C B A 9 8 7 6 5 4 3 2 1 0 1278 * +-------+-------+---------------+ 1279 * | SID | RID | Device ID | 1280 * | (DIR 1) | (DIR 0) | 1281 * +-------+-------+---------------+ 1282 */ 1283 static void 1284 identifycyrix(void) 1285 { 1286 register_t saveintr; 1287 int ccr2_test = 0, dir_test = 0; 1288 u_char ccr2, ccr3; 1289 1290 saveintr = intr_disable(); 1291 1292 ccr2 = read_cyrix_reg(CCR2); 1293 write_cyrix_reg(CCR2, ccr2 ^ CCR2_LOCK_NW); 1294 read_cyrix_reg(CCR2); 1295 if (read_cyrix_reg(CCR2) != ccr2) 1296 ccr2_test = 1; 1297 write_cyrix_reg(CCR2, ccr2); 1298 1299 ccr3 = read_cyrix_reg(CCR3); 1300 write_cyrix_reg(CCR3, ccr3 ^ CCR3_MAPEN3); 1301 read_cyrix_reg(CCR3); 1302 if (read_cyrix_reg(CCR3) != ccr3) 1303 dir_test = 1; /* CPU supports DIRs. */ 1304 write_cyrix_reg(CCR3, ccr3); 1305 1306 if (dir_test) { 1307 /* Device ID registers are available. */ 1308 cyrix_did = read_cyrix_reg(DIR1) << 8; 1309 cyrix_did += read_cyrix_reg(DIR0); 1310 } else if (ccr2_test) 1311 cyrix_did = 0x0010; /* 486S A-step */ 1312 else 1313 cyrix_did = 0x00ff; /* Old 486SLC/DLC and TI486SXLC/SXL */ 1314 1315 intr_restore(saveintr); 1316 } 1317 #endif 1318 1319 /* Update TSC freq with the value indicated by the caller. */ 1320 static void 1321 tsc_freq_changed(void *arg __unused, const struct cf_level *level, int status) 1322 { 1323 1324 /* If there was an error during the transition, don't do anything. */ 1325 if (status != 0) 1326 return; 1327 1328 /* Total setting for this level gives the new frequency in MHz. */ 1329 hw_clockrate = level->total_set.freq; 1330 } 1331 1332 static void 1333 hook_tsc_freq(void *arg __unused) 1334 { 1335 1336 if (tsc_is_invariant) 1337 return; 1338 1339 tsc_post_tag = EVENTHANDLER_REGISTER(cpufreq_post_change, 1340 tsc_freq_changed, NULL, EVENTHANDLER_PRI_ANY); 1341 } 1342 1343 SYSINIT(hook_tsc_freq, SI_SUB_CONFIGURE, SI_ORDER_ANY, hook_tsc_freq, NULL); 1344 1345 static const struct { 1346 const char * vm_bname; 1347 int vm_guest; 1348 } vm_bnames[] = { 1349 { "QEMU", VM_GUEST_VM }, /* QEMU */ 1350 { "Plex86", VM_GUEST_VM }, /* Plex86 */ 1351 { "Bochs", VM_GUEST_VM }, /* Bochs */ 1352 { "Xen", VM_GUEST_XEN }, /* Xen */ 1353 { "BHYVE", VM_GUEST_BHYVE }, /* bhyve */ 1354 { "Seabios", VM_GUEST_KVM }, /* KVM */ 1355 }; 1356 1357 static const struct { 1358 const char * vm_pname; 1359 int vm_guest; 1360 } vm_pnames[] = { 1361 { "VMware Virtual Platform", VM_GUEST_VMWARE }, 1362 { "Virtual Machine", VM_GUEST_VM }, /* Microsoft VirtualPC */ 1363 { "VirtualBox", VM_GUEST_VBOX }, 1364 { "Parallels Virtual Platform", VM_GUEST_PARALLELS }, 1365 { "KVM", VM_GUEST_KVM }, 1366 }; 1367 1368 static struct { 1369 const char *vm_cpuid; 1370 int vm_guest; 1371 } vm_cpuids[] = { 1372 { "XenVMMXenVMM", VM_GUEST_XEN }, /* XEN */ 1373 { "Microsoft Hv", VM_GUEST_HV }, /* Microsoft Hyper-V */ 1374 { "VMwareVMware", VM_GUEST_VMWARE }, /* VMware VM */ 1375 { "KVMKVMKVM", VM_GUEST_KVM }, /* KVM */ 1376 { "bhyve bhyve ", VM_GUEST_BHYVE }, /* bhyve */ 1377 { "VBoxVBoxVBox", VM_GUEST_VBOX }, /* VirtualBox */ 1378 }; 1379 1380 static void 1381 identify_hypervisor_cpuid_base(void) 1382 { 1383 u_int leaf, regs[4]; 1384 int i; 1385 1386 /* 1387 * [RFC] CPUID usage for interaction between Hypervisors and Linux. 1388 * http://lkml.org/lkml/2008/10/1/246 1389 * 1390 * KB1009458: Mechanisms to determine if software is running in 1391 * a VMware virtual machine 1392 * http://kb.vmware.com/kb/1009458 1393 * 1394 * Search for a hypervisor that we recognize. If we cannot find 1395 * a specific hypervisor, return the first information about the 1396 * hypervisor that we found, as others may be able to use. 1397 */ 1398 for (leaf = 0x40000000; leaf < 0x40010000; leaf += 0x100) { 1399 do_cpuid(leaf, regs); 1400 1401 /* 1402 * KVM from Linux kernels prior to commit 1403 * 57c22e5f35aa4b9b2fe11f73f3e62bbf9ef36190 set %eax 1404 * to 0 rather than a valid hv_high value. Check for 1405 * the KVM signature bytes and fixup %eax to the 1406 * highest supported leaf in that case. 1407 */ 1408 if (regs[0] == 0 && regs[1] == 0x4b4d564b && 1409 regs[2] == 0x564b4d56 && regs[3] == 0x0000004d) 1410 regs[0] = leaf + 1; 1411 1412 if (regs[0] >= leaf) { 1413 for (i = 0; i < nitems(vm_cpuids); i++) 1414 if (strncmp((const char *)®s[1], 1415 vm_cpuids[i].vm_cpuid, 12) == 0) { 1416 vm_guest = vm_cpuids[i].vm_guest; 1417 break; 1418 } 1419 1420 /* 1421 * If this is the first entry or we found a 1422 * specific hypervisor, record the base, high value, 1423 * and vendor identifier. 1424 */ 1425 if (vm_guest != VM_GUEST_VM || leaf == 0x40000000) { 1426 hv_base = leaf; 1427 hv_high = regs[0]; 1428 ((u_int *)&hv_vendor)[0] = regs[1]; 1429 ((u_int *)&hv_vendor)[1] = regs[2]; 1430 ((u_int *)&hv_vendor)[2] = regs[3]; 1431 hv_vendor[12] = '\0'; 1432 1433 /* 1434 * If we found a specific hypervisor, then 1435 * we are finished. 1436 */ 1437 if (vm_guest != VM_GUEST_VM) 1438 return; 1439 } 1440 } 1441 } 1442 } 1443 1444 void 1445 identify_hypervisor(void) 1446 { 1447 u_int regs[4]; 1448 char *p; 1449 int i; 1450 1451 /* 1452 * If CPUID2_HV is set, we are running in a hypervisor environment. 1453 */ 1454 if (cpu_feature2 & CPUID2_HV) { 1455 vm_guest = VM_GUEST_VM; 1456 identify_hypervisor_cpuid_base(); 1457 1458 /* If we have a definitive vendor, we can return now. */ 1459 if (*hv_vendor != '\0') 1460 return; 1461 } 1462 1463 /* 1464 * Examine SMBIOS strings for older hypervisors. 1465 */ 1466 p = kern_getenv("smbios.system.serial"); 1467 if (p != NULL) { 1468 if (strncmp(p, "VMware-", 7) == 0 || strncmp(p, "VMW", 3) == 0) { 1469 vmware_hvcall(VMW_HVCMD_GETVERSION, regs); 1470 if (regs[1] == VMW_HVMAGIC) { 1471 vm_guest = VM_GUEST_VMWARE; 1472 freeenv(p); 1473 return; 1474 } 1475 } 1476 freeenv(p); 1477 } 1478 1479 /* 1480 * XXX: Some of these entries may not be needed since they were 1481 * added to FreeBSD before the checks above. 1482 */ 1483 p = kern_getenv("smbios.bios.vendor"); 1484 if (p != NULL) { 1485 for (i = 0; i < nitems(vm_bnames); i++) 1486 if (strcmp(p, vm_bnames[i].vm_bname) == 0) { 1487 vm_guest = vm_bnames[i].vm_guest; 1488 /* If we have a specific match, return */ 1489 if (vm_guest != VM_GUEST_VM) { 1490 freeenv(p); 1491 return; 1492 } 1493 /* 1494 * We are done with bnames, but there might be 1495 * a more specific match in the pnames 1496 */ 1497 break; 1498 } 1499 freeenv(p); 1500 } 1501 p = kern_getenv("smbios.system.product"); 1502 if (p != NULL) { 1503 for (i = 0; i < nitems(vm_pnames); i++) 1504 if (strcmp(p, vm_pnames[i].vm_pname) == 0) { 1505 vm_guest = vm_pnames[i].vm_guest; 1506 freeenv(p); 1507 return; 1508 } 1509 freeenv(p); 1510 } 1511 } 1512 1513 bool 1514 fix_cpuid(void) 1515 { 1516 uint64_t msr; 1517 1518 /* 1519 * Clear "Limit CPUID Maxval" bit and return true if the caller should 1520 * get the largest standard CPUID function number again if it is set 1521 * from BIOS. It is necessary for probing correct CPU topology later 1522 * and for the correct operation of the AVX-aware userspace. 1523 */ 1524 if (cpu_vendor_id == CPU_VENDOR_INTEL && 1525 ((CPUID_TO_FAMILY(cpu_id) == 0xf && 1526 CPUID_TO_MODEL(cpu_id) >= 0x3) || 1527 (CPUID_TO_FAMILY(cpu_id) == 0x6 && 1528 CPUID_TO_MODEL(cpu_id) >= 0xe))) { 1529 msr = rdmsr(MSR_IA32_MISC_ENABLE); 1530 if ((msr & IA32_MISC_EN_LIMCPUID) != 0) { 1531 msr &= ~IA32_MISC_EN_LIMCPUID; 1532 wrmsr(MSR_IA32_MISC_ENABLE, msr); 1533 return (true); 1534 } 1535 } 1536 1537 /* 1538 * Re-enable AMD Topology Extension that could be disabled by BIOS 1539 * on some notebook processors. Without the extension it's really 1540 * hard to determine the correct CPU cache topology. 1541 * See BIOS and Kernel Developer’s Guide (BKDG) for AMD Family 15h 1542 * Models 60h-6Fh Processors, Publication # 50742. 1543 */ 1544 if (vm_guest == VM_GUEST_NO && cpu_vendor_id == CPU_VENDOR_AMD && 1545 CPUID_TO_FAMILY(cpu_id) == 0x15) { 1546 msr = rdmsr(MSR_EXTFEATURES); 1547 if ((msr & ((uint64_t)1 << 54)) == 0) { 1548 msr |= (uint64_t)1 << 54; 1549 wrmsr(MSR_EXTFEATURES, msr); 1550 return (true); 1551 } 1552 } 1553 return (false); 1554 } 1555 1556 void 1557 identify_cpu1(void) 1558 { 1559 u_int regs[4]; 1560 1561 do_cpuid(0, regs); 1562 cpu_high = regs[0]; 1563 ((u_int *)&cpu_vendor)[0] = regs[1]; 1564 ((u_int *)&cpu_vendor)[1] = regs[3]; 1565 ((u_int *)&cpu_vendor)[2] = regs[2]; 1566 cpu_vendor[12] = '\0'; 1567 1568 do_cpuid(1, regs); 1569 cpu_id = regs[0]; 1570 cpu_procinfo = regs[1]; 1571 cpu_feature = regs[3]; 1572 cpu_feature2 = regs[2]; 1573 } 1574 1575 void 1576 identify_cpu2(void) 1577 { 1578 u_int regs[4], cpu_stdext_disable; 1579 1580 if (cpu_high >= 6) { 1581 cpuid_count(6, 0, regs); 1582 cpu_power_eax = regs[0]; 1583 cpu_power_ebx = regs[1]; 1584 cpu_power_ecx = regs[2]; 1585 cpu_power_edx = regs[3]; 1586 } 1587 1588 if (cpu_high >= 7) { 1589 cpuid_count(7, 0, regs); 1590 cpu_stdext_feature = regs[1]; 1591 1592 /* 1593 * Some hypervisors failed to filter out unsupported 1594 * extended features. Allow to disable the 1595 * extensions, activation of which requires setting a 1596 * bit in CR4, and which VM monitors do not support. 1597 */ 1598 cpu_stdext_disable = 0; 1599 TUNABLE_INT_FETCH("hw.cpu_stdext_disable", &cpu_stdext_disable); 1600 cpu_stdext_feature &= ~cpu_stdext_disable; 1601 1602 cpu_stdext_feature2 = regs[2]; 1603 cpu_stdext_feature3 = regs[3]; 1604 1605 if ((cpu_stdext_feature3 & CPUID_STDEXT3_ARCH_CAP) != 0) 1606 cpu_ia32_arch_caps = rdmsr(MSR_IA32_ARCH_CAP); 1607 } 1608 } 1609 1610 void 1611 identify_cpu_ext_features(void) 1612 { 1613 u_int regs[4]; 1614 1615 if (cpu_high >= 7) { 1616 cpuid_count(7, 0, regs); 1617 cpu_stdext_feature2 = regs[2]; 1618 cpu_stdext_feature3 = regs[3]; 1619 } 1620 } 1621 1622 void 1623 identify_cpu_fixup_bsp(void) 1624 { 1625 u_int regs[4]; 1626 1627 cpu_vendor_id = find_cpu_vendor_id(); 1628 1629 if (fix_cpuid()) { 1630 do_cpuid(0, regs); 1631 cpu_high = regs[0]; 1632 } 1633 } 1634 1635 /* 1636 * Final stage of CPU identification. 1637 */ 1638 void 1639 finishidentcpu(void) 1640 { 1641 u_int regs[4]; 1642 #ifdef __i386__ 1643 u_char ccr3; 1644 #endif 1645 1646 identify_cpu_fixup_bsp(); 1647 1648 if (cpu_high >= 5 && (cpu_feature2 & CPUID2_MON) != 0) { 1649 do_cpuid(5, regs); 1650 cpu_mon_mwait_flags = regs[2]; 1651 cpu_mon_min_size = regs[0] & CPUID5_MON_MIN_SIZE; 1652 cpu_mon_max_size = regs[1] & CPUID5_MON_MAX_SIZE; 1653 } 1654 1655 identify_cpu2(); 1656 1657 #ifdef __i386__ 1658 if (cpu_high > 0 && 1659 (cpu_vendor_id == CPU_VENDOR_INTEL || 1660 cpu_vendor_id == CPU_VENDOR_AMD || 1661 cpu_vendor_id == CPU_VENDOR_HYGON || 1662 cpu_vendor_id == CPU_VENDOR_TRANSMETA || 1663 cpu_vendor_id == CPU_VENDOR_CENTAUR || 1664 cpu_vendor_id == CPU_VENDOR_NSC)) { 1665 do_cpuid(0x80000000, regs); 1666 if (regs[0] >= 0x80000000) 1667 cpu_exthigh = regs[0]; 1668 } 1669 #else 1670 if (cpu_vendor_id == CPU_VENDOR_INTEL || 1671 cpu_vendor_id == CPU_VENDOR_AMD || 1672 cpu_vendor_id == CPU_VENDOR_HYGON || 1673 cpu_vendor_id == CPU_VENDOR_CENTAUR) { 1674 do_cpuid(0x80000000, regs); 1675 cpu_exthigh = regs[0]; 1676 } 1677 #endif 1678 if (cpu_exthigh >= 0x80000001) { 1679 do_cpuid(0x80000001, regs); 1680 amd_feature = regs[3] & ~(cpu_feature & 0x0183f3ff); 1681 amd_feature2 = regs[2]; 1682 } 1683 if (cpu_exthigh >= 0x80000007) { 1684 do_cpuid(0x80000007, regs); 1685 amd_rascap = regs[1]; 1686 amd_pminfo = regs[3]; 1687 } 1688 if (cpu_exthigh >= 0x80000008) { 1689 do_cpuid(0x80000008, regs); 1690 cpu_maxphyaddr = regs[0] & 0xff; 1691 amd_extended_feature_extensions = regs[1]; 1692 cpu_procinfo2 = regs[2]; 1693 } else { 1694 cpu_maxphyaddr = (cpu_feature & CPUID_PAE) != 0 ? 36 : 32; 1695 } 1696 1697 #ifdef __i386__ 1698 if (cpu_vendor_id == CPU_VENDOR_CYRIX) { 1699 if (cpu == CPU_486) { 1700 /* 1701 * These conditions are equivalent to: 1702 * - CPU does not support cpuid instruction. 1703 * - Cyrix/IBM CPU is detected. 1704 */ 1705 if (identblue() == IDENTBLUE_IBMCPU) { 1706 strcpy(cpu_vendor, "IBM"); 1707 cpu_vendor_id = CPU_VENDOR_IBM; 1708 cpu = CPU_BLUE; 1709 return; 1710 } 1711 } 1712 switch (cpu_id & 0xf00) { 1713 case 0x600: 1714 /* 1715 * Cyrix's datasheet does not describe DIRs. 1716 * Therefor, I assume it does not have them 1717 * and use the result of the cpuid instruction. 1718 * XXX they seem to have it for now at least. -Peter 1719 */ 1720 identifycyrix(); 1721 cpu = CPU_M2; 1722 break; 1723 default: 1724 identifycyrix(); 1725 /* 1726 * This routine contains a trick. 1727 * Don't check (cpu_id & 0x00f0) == 0x50 to detect M2, now. 1728 */ 1729 switch (cyrix_did & 0x00f0) { 1730 case 0x00: 1731 case 0xf0: 1732 cpu = CPU_486DLC; 1733 break; 1734 case 0x10: 1735 cpu = CPU_CY486DX; 1736 break; 1737 case 0x20: 1738 if ((cyrix_did & 0x000f) < 8) 1739 cpu = CPU_M1; 1740 else 1741 cpu = CPU_M1SC; 1742 break; 1743 case 0x30: 1744 cpu = CPU_M1; 1745 break; 1746 case 0x40: 1747 /* MediaGX CPU */ 1748 cpu = CPU_M1SC; 1749 break; 1750 default: 1751 /* M2 and later CPUs are treated as M2. */ 1752 cpu = CPU_M2; 1753 1754 /* 1755 * enable cpuid instruction. 1756 */ 1757 ccr3 = read_cyrix_reg(CCR3); 1758 write_cyrix_reg(CCR3, CCR3_MAPEN0); 1759 write_cyrix_reg(CCR4, read_cyrix_reg(CCR4) | CCR4_CPUID); 1760 write_cyrix_reg(CCR3, ccr3); 1761 1762 do_cpuid(0, regs); 1763 cpu_high = regs[0]; /* eax */ 1764 do_cpuid(1, regs); 1765 cpu_id = regs[0]; /* eax */ 1766 cpu_feature = regs[3]; /* edx */ 1767 break; 1768 } 1769 } 1770 } else if (cpu == CPU_486 && *cpu_vendor == '\0') { 1771 /* 1772 * There are BlueLightning CPUs that do not change 1773 * undefined flags by dividing 5 by 2. In this case, 1774 * the CPU identification routine in locore.s leaves 1775 * cpu_vendor null string and puts CPU_486 into the 1776 * cpu. 1777 */ 1778 if (identblue() == IDENTBLUE_IBMCPU) { 1779 strcpy(cpu_vendor, "IBM"); 1780 cpu_vendor_id = CPU_VENDOR_IBM; 1781 cpu = CPU_BLUE; 1782 return; 1783 } 1784 } 1785 #endif 1786 } 1787 1788 int 1789 pti_get_default(void) 1790 { 1791 1792 if (strcmp(cpu_vendor, AMD_VENDOR_ID) == 0 || 1793 strcmp(cpu_vendor, HYGON_VENDOR_ID) == 0) 1794 return (0); 1795 if ((cpu_ia32_arch_caps & IA32_ARCH_CAP_RDCL_NO) != 0) 1796 return (0); 1797 return (1); 1798 } 1799 1800 static u_int 1801 find_cpu_vendor_id(void) 1802 { 1803 int i; 1804 1805 for (i = 0; i < nitems(cpu_vendors); i++) 1806 if (strcmp(cpu_vendor, cpu_vendors[i].vendor) == 0) 1807 return (cpu_vendors[i].vendor_id); 1808 return (0); 1809 } 1810 1811 static void 1812 print_AMD_assoc(int i) 1813 { 1814 if (i == 255) 1815 printf(", fully associative\n"); 1816 else 1817 printf(", %d-way associative\n", i); 1818 } 1819 1820 static void 1821 print_AMD_l2_assoc(int i) 1822 { 1823 switch (i & 0x0f) { 1824 case 0: printf(", disabled/not present\n"); break; 1825 case 1: printf(", direct mapped\n"); break; 1826 case 2: printf(", 2-way associative\n"); break; 1827 case 4: printf(", 4-way associative\n"); break; 1828 case 6: printf(", 8-way associative\n"); break; 1829 case 8: printf(", 16-way associative\n"); break; 1830 case 15: printf(", fully associative\n"); break; 1831 default: printf(", reserved configuration\n"); break; 1832 } 1833 } 1834 1835 static void 1836 print_AMD_info(void) 1837 { 1838 #ifdef __i386__ 1839 uint64_t amd_whcr; 1840 #endif 1841 u_int regs[4]; 1842 1843 if (cpu_exthigh >= 0x80000005) { 1844 do_cpuid(0x80000005, regs); 1845 printf("L1 2MB data TLB: %d entries", (regs[0] >> 16) & 0xff); 1846 print_AMD_assoc(regs[0] >> 24); 1847 1848 printf("L1 2MB instruction TLB: %d entries", regs[0] & 0xff); 1849 print_AMD_assoc((regs[0] >> 8) & 0xff); 1850 1851 printf("L1 4KB data TLB: %d entries", (regs[1] >> 16) & 0xff); 1852 print_AMD_assoc(regs[1] >> 24); 1853 1854 printf("L1 4KB instruction TLB: %d entries", regs[1] & 0xff); 1855 print_AMD_assoc((regs[1] >> 8) & 0xff); 1856 1857 printf("L1 data cache: %d kbytes", regs[2] >> 24); 1858 printf(", %d bytes/line", regs[2] & 0xff); 1859 printf(", %d lines/tag", (regs[2] >> 8) & 0xff); 1860 print_AMD_assoc((regs[2] >> 16) & 0xff); 1861 1862 printf("L1 instruction cache: %d kbytes", regs[3] >> 24); 1863 printf(", %d bytes/line", regs[3] & 0xff); 1864 printf(", %d lines/tag", (regs[3] >> 8) & 0xff); 1865 print_AMD_assoc((regs[3] >> 16) & 0xff); 1866 } 1867 1868 if (cpu_exthigh >= 0x80000006) { 1869 do_cpuid(0x80000006, regs); 1870 if ((regs[0] >> 16) != 0) { 1871 printf("L2 2MB data TLB: %d entries", 1872 (regs[0] >> 16) & 0xfff); 1873 print_AMD_l2_assoc(regs[0] >> 28); 1874 printf("L2 2MB instruction TLB: %d entries", 1875 regs[0] & 0xfff); 1876 print_AMD_l2_assoc((regs[0] >> 28) & 0xf); 1877 } else { 1878 printf("L2 2MB unified TLB: %d entries", 1879 regs[0] & 0xfff); 1880 print_AMD_l2_assoc((regs[0] >> 28) & 0xf); 1881 } 1882 if ((regs[1] >> 16) != 0) { 1883 printf("L2 4KB data TLB: %d entries", 1884 (regs[1] >> 16) & 0xfff); 1885 print_AMD_l2_assoc(regs[1] >> 28); 1886 1887 printf("L2 4KB instruction TLB: %d entries", 1888 (regs[1] >> 16) & 0xfff); 1889 print_AMD_l2_assoc((regs[1] >> 28) & 0xf); 1890 } else { 1891 printf("L2 4KB unified TLB: %d entries", 1892 (regs[1] >> 16) & 0xfff); 1893 print_AMD_l2_assoc((regs[1] >> 28) & 0xf); 1894 } 1895 printf("L2 unified cache: %d kbytes", regs[2] >> 16); 1896 printf(", %d bytes/line", regs[2] & 0xff); 1897 printf(", %d lines/tag", (regs[2] >> 8) & 0x0f); 1898 print_AMD_l2_assoc((regs[2] >> 12) & 0x0f); 1899 } 1900 1901 #ifdef __i386__ 1902 if (((cpu_id & 0xf00) == 0x500) 1903 && (((cpu_id & 0x0f0) > 0x80) 1904 || (((cpu_id & 0x0f0) == 0x80) 1905 && (cpu_id & 0x00f) > 0x07))) { 1906 /* K6-2(new core [Stepping 8-F]), K6-III or later */ 1907 amd_whcr = rdmsr(0xc0000082); 1908 if (!(amd_whcr & (0x3ff << 22))) { 1909 printf("Write Allocate Disable\n"); 1910 } else { 1911 printf("Write Allocate Enable Limit: %dM bytes\n", 1912 (u_int32_t)((amd_whcr & (0x3ff << 22)) >> 22) * 4); 1913 printf("Write Allocate 15-16M bytes: %s\n", 1914 (amd_whcr & (1 << 16)) ? "Enable" : "Disable"); 1915 } 1916 } else if (((cpu_id & 0xf00) == 0x500) 1917 && ((cpu_id & 0x0f0) > 0x50)) { 1918 /* K6, K6-2(old core) */ 1919 amd_whcr = rdmsr(0xc0000082); 1920 if (!(amd_whcr & (0x7f << 1))) { 1921 printf("Write Allocate Disable\n"); 1922 } else { 1923 printf("Write Allocate Enable Limit: %dM bytes\n", 1924 (u_int32_t)((amd_whcr & (0x7f << 1)) >> 1) * 4); 1925 printf("Write Allocate 15-16M bytes: %s\n", 1926 (amd_whcr & 0x0001) ? "Enable" : "Disable"); 1927 printf("Hardware Write Allocate Control: %s\n", 1928 (amd_whcr & 0x0100) ? "Enable" : "Disable"); 1929 } 1930 } 1931 #endif 1932 /* 1933 * Opteron Rev E shows a bug as in very rare occasions a read memory 1934 * barrier is not performed as expected if it is followed by a 1935 * non-atomic read-modify-write instruction. 1936 * As long as that bug pops up very rarely (intensive machine usage 1937 * on other operating systems generally generates one unexplainable 1938 * crash any 2 months) and as long as a model specific fix would be 1939 * impractical at this stage, print out a warning string if the broken 1940 * model and family are identified. 1941 */ 1942 if (CPUID_TO_FAMILY(cpu_id) == 0xf && CPUID_TO_MODEL(cpu_id) >= 0x20 && 1943 CPUID_TO_MODEL(cpu_id) <= 0x3f) 1944 printf("WARNING: This architecture revision has known SMP " 1945 "hardware bugs which may cause random instability\n"); 1946 } 1947 1948 static void 1949 print_INTEL_info(void) 1950 { 1951 u_int regs[4]; 1952 u_int rounds, regnum; 1953 u_int nwaycode, nway; 1954 1955 if (cpu_high >= 2) { 1956 rounds = 0; 1957 do { 1958 do_cpuid(0x2, regs); 1959 if (rounds == 0 && (rounds = (regs[0] & 0xff)) == 0) 1960 break; /* we have a buggy CPU */ 1961 1962 for (regnum = 0; regnum <= 3; ++regnum) { 1963 if (regs[regnum] & (1<<31)) 1964 continue; 1965 if (regnum != 0) 1966 print_INTEL_TLB(regs[regnum] & 0xff); 1967 print_INTEL_TLB((regs[regnum] >> 8) & 0xff); 1968 print_INTEL_TLB((regs[regnum] >> 16) & 0xff); 1969 print_INTEL_TLB((regs[regnum] >> 24) & 0xff); 1970 } 1971 } while (--rounds > 0); 1972 } 1973 1974 if (cpu_exthigh >= 0x80000006) { 1975 do_cpuid(0x80000006, regs); 1976 nwaycode = (regs[2] >> 12) & 0x0f; 1977 if (nwaycode >= 0x02 && nwaycode <= 0x08) 1978 nway = 1 << (nwaycode / 2); 1979 else 1980 nway = 0; 1981 printf("L2 cache: %u kbytes, %u-way associative, %u bytes/line\n", 1982 (regs[2] >> 16) & 0xffff, nway, regs[2] & 0xff); 1983 } 1984 } 1985 1986 static void 1987 print_INTEL_TLB(u_int data) 1988 { 1989 switch (data) { 1990 case 0x0: 1991 case 0x40: 1992 default: 1993 break; 1994 case 0x1: 1995 printf("Instruction TLB: 4 KB pages, 4-way set associative, 32 entries\n"); 1996 break; 1997 case 0x2: 1998 printf("Instruction TLB: 4 MB pages, fully associative, 2 entries\n"); 1999 break; 2000 case 0x3: 2001 printf("Data TLB: 4 KB pages, 4-way set associative, 64 entries\n"); 2002 break; 2003 case 0x4: 2004 printf("Data TLB: 4 MB Pages, 4-way set associative, 8 entries\n"); 2005 break; 2006 case 0x6: 2007 printf("1st-level instruction cache: 8 KB, 4-way set associative, 32 byte line size\n"); 2008 break; 2009 case 0x8: 2010 printf("1st-level instruction cache: 16 KB, 4-way set associative, 32 byte line size\n"); 2011 break; 2012 case 0x9: 2013 printf("1st-level instruction cache: 32 KB, 4-way set associative, 64 byte line size\n"); 2014 break; 2015 case 0xa: 2016 printf("1st-level data cache: 8 KB, 2-way set associative, 32 byte line size\n"); 2017 break; 2018 case 0xb: 2019 printf("Instruction TLB: 4 MByte pages, 4-way set associative, 4 entries\n"); 2020 break; 2021 case 0xc: 2022 printf("1st-level data cache: 16 KB, 4-way set associative, 32 byte line size\n"); 2023 break; 2024 case 0xd: 2025 printf("1st-level data cache: 16 KBytes, 4-way set associative, 64 byte line size"); 2026 break; 2027 case 0xe: 2028 printf("1st-level data cache: 24 KBytes, 6-way set associative, 64 byte line size\n"); 2029 break; 2030 case 0x1d: 2031 printf("2nd-level cache: 128 KBytes, 2-way set associative, 64 byte line size\n"); 2032 break; 2033 case 0x21: 2034 printf("2nd-level cache: 256 KBytes, 8-way set associative, 64 byte line size\n"); 2035 break; 2036 case 0x22: 2037 printf("3rd-level cache: 512 KB, 4-way set associative, sectored cache, 64 byte line size\n"); 2038 break; 2039 case 0x23: 2040 printf("3rd-level cache: 1 MB, 8-way set associative, sectored cache, 64 byte line size\n"); 2041 break; 2042 case 0x24: 2043 printf("2nd-level cache: 1 MBytes, 16-way set associative, 64 byte line size\n"); 2044 break; 2045 case 0x25: 2046 printf("3rd-level cache: 2 MB, 8-way set associative, sectored cache, 64 byte line size\n"); 2047 break; 2048 case 0x29: 2049 printf("3rd-level cache: 4 MB, 8-way set associative, sectored cache, 64 byte line size\n"); 2050 break; 2051 case 0x2c: 2052 printf("1st-level data cache: 32 KB, 8-way set associative, 64 byte line size\n"); 2053 break; 2054 case 0x30: 2055 printf("1st-level instruction cache: 32 KB, 8-way set associative, 64 byte line size\n"); 2056 break; 2057 case 0x39: /* De-listed in SDM rev. 54 */ 2058 printf("2nd-level cache: 128 KB, 4-way set associative, sectored cache, 64 byte line size\n"); 2059 break; 2060 case 0x3b: /* De-listed in SDM rev. 54 */ 2061 printf("2nd-level cache: 128 KB, 2-way set associative, sectored cache, 64 byte line size\n"); 2062 break; 2063 case 0x3c: /* De-listed in SDM rev. 54 */ 2064 printf("2nd-level cache: 256 KB, 4-way set associative, sectored cache, 64 byte line size\n"); 2065 break; 2066 case 0x41: 2067 printf("2nd-level cache: 128 KB, 4-way set associative, 32 byte line size\n"); 2068 break; 2069 case 0x42: 2070 printf("2nd-level cache: 256 KB, 4-way set associative, 32 byte line size\n"); 2071 break; 2072 case 0x43: 2073 printf("2nd-level cache: 512 KB, 4-way set associative, 32 byte line size\n"); 2074 break; 2075 case 0x44: 2076 printf("2nd-level cache: 1 MB, 4-way set associative, 32 byte line size\n"); 2077 break; 2078 case 0x45: 2079 printf("2nd-level cache: 2 MB, 4-way set associative, 32 byte line size\n"); 2080 break; 2081 case 0x46: 2082 printf("3rd-level cache: 4 MB, 4-way set associative, 64 byte line size\n"); 2083 break; 2084 case 0x47: 2085 printf("3rd-level cache: 8 MB, 8-way set associative, 64 byte line size\n"); 2086 break; 2087 case 0x48: 2088 printf("2nd-level cache: 3MByte, 12-way set associative, 64 byte line size\n"); 2089 break; 2090 case 0x49: 2091 if (CPUID_TO_FAMILY(cpu_id) == 0xf && 2092 CPUID_TO_MODEL(cpu_id) == 0x6) 2093 printf("3rd-level cache: 4MB, 16-way set associative, 64-byte line size\n"); 2094 else 2095 printf("2nd-level cache: 4 MByte, 16-way set associative, 64 byte line size"); 2096 break; 2097 case 0x4a: 2098 printf("3rd-level cache: 6MByte, 12-way set associative, 64 byte line size\n"); 2099 break; 2100 case 0x4b: 2101 printf("3rd-level cache: 8MByte, 16-way set associative, 64 byte line size\n"); 2102 break; 2103 case 0x4c: 2104 printf("3rd-level cache: 12MByte, 12-way set associative, 64 byte line size\n"); 2105 break; 2106 case 0x4d: 2107 printf("3rd-level cache: 16MByte, 16-way set associative, 64 byte line size\n"); 2108 break; 2109 case 0x4e: 2110 printf("2nd-level cache: 6MByte, 24-way set associative, 64 byte line size\n"); 2111 break; 2112 case 0x4f: 2113 printf("Instruction TLB: 4 KByte pages, 32 entries\n"); 2114 break; 2115 case 0x50: 2116 printf("Instruction TLB: 4 KB, 2 MB or 4 MB pages, fully associative, 64 entries\n"); 2117 break; 2118 case 0x51: 2119 printf("Instruction TLB: 4 KB, 2 MB or 4 MB pages, fully associative, 128 entries\n"); 2120 break; 2121 case 0x52: 2122 printf("Instruction TLB: 4 KB, 2 MB or 4 MB pages, fully associative, 256 entries\n"); 2123 break; 2124 case 0x55: 2125 printf("Instruction TLB: 2-MByte or 4-MByte pages, fully associative, 7 entries\n"); 2126 break; 2127 case 0x56: 2128 printf("Data TLB0: 4 MByte pages, 4-way set associative, 16 entries\n"); 2129 break; 2130 case 0x57: 2131 printf("Data TLB0: 4 KByte pages, 4-way associative, 16 entries\n"); 2132 break; 2133 case 0x59: 2134 printf("Data TLB0: 4 KByte pages, fully associative, 16 entries\n"); 2135 break; 2136 case 0x5a: 2137 printf("Data TLB0: 2-MByte or 4 MByte pages, 4-way set associative, 32 entries\n"); 2138 break; 2139 case 0x5b: 2140 printf("Data TLB: 4 KB or 4 MB pages, fully associative, 64 entries\n"); 2141 break; 2142 case 0x5c: 2143 printf("Data TLB: 4 KB or 4 MB pages, fully associative, 128 entries\n"); 2144 break; 2145 case 0x5d: 2146 printf("Data TLB: 4 KB or 4 MB pages, fully associative, 256 entries\n"); 2147 break; 2148 case 0x60: 2149 printf("1st-level data cache: 16 KB, 8-way set associative, sectored cache, 64 byte line size\n"); 2150 break; 2151 case 0x61: 2152 printf("Instruction TLB: 4 KByte pages, fully associative, 48 entries\n"); 2153 break; 2154 case 0x63: 2155 printf("Data TLB: 2 MByte or 4 MByte pages, 4-way set associative, 32 entries and a separate array with 1 GByte pages, 4-way set associative, 4 entries\n"); 2156 break; 2157 case 0x64: 2158 printf("Data TLB: 4 KBytes pages, 4-way set associative, 512 entries\n"); 2159 break; 2160 case 0x66: 2161 printf("1st-level data cache: 8 KB, 4-way set associative, sectored cache, 64 byte line size\n"); 2162 break; 2163 case 0x67: 2164 printf("1st-level data cache: 16 KB, 4-way set associative, sectored cache, 64 byte line size\n"); 2165 break; 2166 case 0x68: 2167 printf("1st-level data cache: 32 KB, 4 way set associative, sectored cache, 64 byte line size\n"); 2168 break; 2169 case 0x6a: 2170 printf("uTLB: 4KByte pages, 8-way set associative, 64 entries\n"); 2171 break; 2172 case 0x6b: 2173 printf("DTLB: 4KByte pages, 8-way set associative, 256 entries\n"); 2174 break; 2175 case 0x6c: 2176 printf("DTLB: 2M/4M pages, 8-way set associative, 128 entries\n"); 2177 break; 2178 case 0x6d: 2179 printf("DTLB: 1 GByte pages, fully associative, 16 entries\n"); 2180 break; 2181 case 0x70: 2182 printf("Trace cache: 12K-uops, 8-way set associative\n"); 2183 break; 2184 case 0x71: 2185 printf("Trace cache: 16K-uops, 8-way set associative\n"); 2186 break; 2187 case 0x72: 2188 printf("Trace cache: 32K-uops, 8-way set associative\n"); 2189 break; 2190 case 0x76: 2191 printf("Instruction TLB: 2M/4M pages, fully associative, 8 entries\n"); 2192 break; 2193 case 0x78: 2194 printf("2nd-level cache: 1 MB, 4-way set associative, 64-byte line size\n"); 2195 break; 2196 case 0x79: 2197 printf("2nd-level cache: 128 KB, 8-way set associative, sectored cache, 64 byte line size\n"); 2198 break; 2199 case 0x7a: 2200 printf("2nd-level cache: 256 KB, 8-way set associative, sectored cache, 64 byte line size\n"); 2201 break; 2202 case 0x7b: 2203 printf("2nd-level cache: 512 KB, 8-way set associative, sectored cache, 64 byte line size\n"); 2204 break; 2205 case 0x7c: 2206 printf("2nd-level cache: 1 MB, 8-way set associative, sectored cache, 64 byte line size\n"); 2207 break; 2208 case 0x7d: 2209 printf("2nd-level cache: 2-MB, 8-way set associative, 64-byte line size\n"); 2210 break; 2211 case 0x7f: 2212 printf("2nd-level cache: 512-KB, 2-way set associative, 64-byte line size\n"); 2213 break; 2214 case 0x80: 2215 printf("2nd-level cache: 512 KByte, 8-way set associative, 64-byte line size\n"); 2216 break; 2217 case 0x82: 2218 printf("2nd-level cache: 256 KB, 8-way set associative, 32 byte line size\n"); 2219 break; 2220 case 0x83: 2221 printf("2nd-level cache: 512 KB, 8-way set associative, 32 byte line size\n"); 2222 break; 2223 case 0x84: 2224 printf("2nd-level cache: 1 MB, 8-way set associative, 32 byte line size\n"); 2225 break; 2226 case 0x85: 2227 printf("2nd-level cache: 2 MB, 8-way set associative, 32 byte line size\n"); 2228 break; 2229 case 0x86: 2230 printf("2nd-level cache: 512 KB, 4-way set associative, 64 byte line size\n"); 2231 break; 2232 case 0x87: 2233 printf("2nd-level cache: 1 MB, 8-way set associative, 64 byte line size\n"); 2234 break; 2235 case 0xa0: 2236 printf("DTLB: 4k pages, fully associative, 32 entries\n"); 2237 break; 2238 case 0xb0: 2239 printf("Instruction TLB: 4 KB Pages, 4-way set associative, 128 entries\n"); 2240 break; 2241 case 0xb1: 2242 printf("Instruction TLB: 2M pages, 4-way, 8 entries or 4M pages, 4-way, 4 entries\n"); 2243 break; 2244 case 0xb2: 2245 printf("Instruction TLB: 4KByte pages, 4-way set associative, 64 entries\n"); 2246 break; 2247 case 0xb3: 2248 printf("Data TLB: 4 KB Pages, 4-way set associative, 128 entries\n"); 2249 break; 2250 case 0xb4: 2251 printf("Data TLB1: 4 KByte pages, 4-way associative, 256 entries\n"); 2252 break; 2253 case 0xb5: 2254 printf("Instruction TLB: 4KByte pages, 8-way set associative, 64 entries\n"); 2255 break; 2256 case 0xb6: 2257 printf("Instruction TLB: 4KByte pages, 8-way set associative, 128 entries\n"); 2258 break; 2259 case 0xba: 2260 printf("Data TLB1: 4 KByte pages, 4-way associative, 64 entries\n"); 2261 break; 2262 case 0xc0: 2263 printf("Data TLB: 4 KByte and 4 MByte pages, 4-way associative, 8 entries\n"); 2264 break; 2265 case 0xc1: 2266 printf("Shared 2nd-Level TLB: 4 KByte/2MByte pages, 8-way associative, 1024 entries\n"); 2267 break; 2268 case 0xc2: 2269 printf("DTLB: 4 KByte/2 MByte pages, 4-way associative, 16 entries\n"); 2270 break; 2271 case 0xc3: 2272 printf("Shared 2nd-Level TLB: 4 KByte /2 MByte pages, 6-way associative, 1536 entries. Also 1GBbyte pages, 4-way, 16 entries\n"); 2273 break; 2274 case 0xc4: 2275 printf("DTLB: 2M/4M Byte pages, 4-way associative, 32 entries\n"); 2276 break; 2277 case 0xca: 2278 printf("Shared 2nd-Level TLB: 4 KByte pages, 4-way associative, 512 entries\n"); 2279 break; 2280 case 0xd0: 2281 printf("3rd-level cache: 512 KByte, 4-way set associative, 64 byte line size\n"); 2282 break; 2283 case 0xd1: 2284 printf("3rd-level cache: 1 MByte, 4-way set associative, 64 byte line size\n"); 2285 break; 2286 case 0xd2: 2287 printf("3rd-level cache: 2 MByte, 4-way set associative, 64 byte line size\n"); 2288 break; 2289 case 0xd6: 2290 printf("3rd-level cache: 1 MByte, 8-way set associative, 64 byte line size\n"); 2291 break; 2292 case 0xd7: 2293 printf("3rd-level cache: 2 MByte, 8-way set associative, 64 byte line size\n"); 2294 break; 2295 case 0xd8: 2296 printf("3rd-level cache: 4 MByte, 8-way set associative, 64 byte line size\n"); 2297 break; 2298 case 0xdc: 2299 printf("3rd-level cache: 1.5 MByte, 12-way set associative, 64 byte line size\n"); 2300 break; 2301 case 0xdd: 2302 printf("3rd-level cache: 3 MByte, 12-way set associative, 64 byte line size\n"); 2303 break; 2304 case 0xde: 2305 printf("3rd-level cache: 6 MByte, 12-way set associative, 64 byte line size\n"); 2306 break; 2307 case 0xe2: 2308 printf("3rd-level cache: 2 MByte, 16-way set associative, 64 byte line size\n"); 2309 break; 2310 case 0xe3: 2311 printf("3rd-level cache: 4 MByte, 16-way set associative, 64 byte line size\n"); 2312 break; 2313 case 0xe4: 2314 printf("3rd-level cache: 8 MByte, 16-way set associative, 64 byte line size\n"); 2315 break; 2316 case 0xea: 2317 printf("3rd-level cache: 12MByte, 24-way set associative, 64 byte line size\n"); 2318 break; 2319 case 0xeb: 2320 printf("3rd-level cache: 18MByte, 24-way set associative, 64 byte line size\n"); 2321 break; 2322 case 0xec: 2323 printf("3rd-level cache: 24MByte, 24-way set associative, 64 byte line size\n"); 2324 break; 2325 case 0xf0: 2326 printf("64-Byte prefetching\n"); 2327 break; 2328 case 0xf1: 2329 printf("128-Byte prefetching\n"); 2330 break; 2331 } 2332 } 2333 2334 static void 2335 print_svm_info(void) 2336 { 2337 u_int features, regs[4]; 2338 uint64_t msr; 2339 int comma; 2340 2341 printf("\n SVM: "); 2342 do_cpuid(0x8000000A, regs); 2343 features = regs[3]; 2344 2345 msr = rdmsr(MSR_VM_CR); 2346 if ((msr & VM_CR_SVMDIS) == VM_CR_SVMDIS) 2347 printf("(disabled in BIOS) "); 2348 2349 if (!bootverbose) { 2350 comma = 0; 2351 if (features & (1 << 0)) { 2352 printf("%sNP", comma ? "," : ""); 2353 comma = 1; 2354 } 2355 if (features & (1 << 3)) { 2356 printf("%sNRIP", comma ? "," : ""); 2357 comma = 1; 2358 } 2359 if (features & (1 << 5)) { 2360 printf("%sVClean", comma ? "," : ""); 2361 comma = 1; 2362 } 2363 if (features & (1 << 6)) { 2364 printf("%sAFlush", comma ? "," : ""); 2365 comma = 1; 2366 } 2367 if (features & (1 << 7)) { 2368 printf("%sDAssist", comma ? "," : ""); 2369 comma = 1; 2370 } 2371 printf("%sNAsids=%d", comma ? "," : "", regs[1]); 2372 return; 2373 } 2374 2375 printf("Features=0x%b", features, 2376 "\020" 2377 "\001NP" /* Nested paging */ 2378 "\002LbrVirt" /* LBR virtualization */ 2379 "\003SVML" /* SVM lock */ 2380 "\004NRIPS" /* NRIP save */ 2381 "\005TscRateMsr" /* MSR based TSC rate control */ 2382 "\006VmcbClean" /* VMCB clean bits */ 2383 "\007FlushByAsid" /* Flush by ASID */ 2384 "\010DecodeAssist" /* Decode assist */ 2385 "\011<b8>" 2386 "\012<b9>" 2387 "\013PauseFilter" /* PAUSE intercept filter */ 2388 "\014EncryptedMcodePatch" 2389 "\015PauseFilterThreshold" /* PAUSE filter threshold */ 2390 "\016AVIC" /* virtual interrupt controller */ 2391 "\017<b14>" 2392 "\020V_VMSAVE_VMLOAD" 2393 "\021vGIF" 2394 "\022GMET" /* Guest Mode Execute Trap */ 2395 "\023<b18>" 2396 "\024<b19>" 2397 "\025GuesSpecCtl" /* Guest Spec_ctl */ 2398 "\026<b21>" 2399 "\027<b22>" 2400 "\030<b23>" 2401 "\031<b24>" 2402 "\032<b25>" 2403 "\033<b26>" 2404 "\034<b27>" 2405 "\035<b28>" 2406 "\036<b29>" 2407 "\037<b30>" 2408 "\040<b31>" 2409 ); 2410 printf("\nRevision=%d, ASIDs=%d", regs[0] & 0xff, regs[1]); 2411 } 2412 2413 #ifdef __i386__ 2414 static void 2415 print_transmeta_info(void) 2416 { 2417 u_int regs[4], nreg = 0; 2418 2419 do_cpuid(0x80860000, regs); 2420 nreg = regs[0]; 2421 if (nreg >= 0x80860001) { 2422 do_cpuid(0x80860001, regs); 2423 printf(" Processor revision %u.%u.%u.%u\n", 2424 (regs[1] >> 24) & 0xff, 2425 (regs[1] >> 16) & 0xff, 2426 (regs[1] >> 8) & 0xff, 2427 regs[1] & 0xff); 2428 } 2429 if (nreg >= 0x80860002) { 2430 do_cpuid(0x80860002, regs); 2431 printf(" Code Morphing Software revision %u.%u.%u-%u-%u\n", 2432 (regs[1] >> 24) & 0xff, 2433 (regs[1] >> 16) & 0xff, 2434 (regs[1] >> 8) & 0xff, 2435 regs[1] & 0xff, 2436 regs[2]); 2437 } 2438 if (nreg >= 0x80860006) { 2439 char info[65]; 2440 do_cpuid(0x80860003, (u_int*) &info[0]); 2441 do_cpuid(0x80860004, (u_int*) &info[16]); 2442 do_cpuid(0x80860005, (u_int*) &info[32]); 2443 do_cpuid(0x80860006, (u_int*) &info[48]); 2444 info[64] = 0; 2445 printf(" %s\n", info); 2446 } 2447 } 2448 #endif 2449 2450 static void 2451 print_via_padlock_info(void) 2452 { 2453 u_int regs[4]; 2454 2455 do_cpuid(0xc0000001, regs); 2456 printf("\n VIA Padlock Features=0x%b", regs[3], 2457 "\020" 2458 "\003RNG" /* RNG */ 2459 "\007AES" /* ACE */ 2460 "\011AES-CTR" /* ACE2 */ 2461 "\013SHA1,SHA256" /* PHE */ 2462 "\015RSA" /* PMM */ 2463 ); 2464 } 2465 2466 static uint32_t 2467 vmx_settable(uint64_t basic, int msr, int true_msr) 2468 { 2469 uint64_t val; 2470 2471 if (basic & (1ULL << 55)) 2472 val = rdmsr(true_msr); 2473 else 2474 val = rdmsr(msr); 2475 2476 /* Just report the controls that can be set to 1. */ 2477 return (val >> 32); 2478 } 2479 2480 static void 2481 print_vmx_info(void) 2482 { 2483 uint64_t basic, msr; 2484 uint32_t entry, exit, mask, pin, proc, proc2; 2485 int comma; 2486 2487 printf("\n VT-x: "); 2488 msr = rdmsr(MSR_IA32_FEATURE_CONTROL); 2489 if (!(msr & IA32_FEATURE_CONTROL_VMX_EN)) 2490 printf("(disabled in BIOS) "); 2491 basic = rdmsr(MSR_VMX_BASIC); 2492 pin = vmx_settable(basic, MSR_VMX_PINBASED_CTLS, 2493 MSR_VMX_TRUE_PINBASED_CTLS); 2494 proc = vmx_settable(basic, MSR_VMX_PROCBASED_CTLS, 2495 MSR_VMX_TRUE_PROCBASED_CTLS); 2496 if (proc & PROCBASED_SECONDARY_CONTROLS) 2497 proc2 = vmx_settable(basic, MSR_VMX_PROCBASED_CTLS2, 2498 MSR_VMX_PROCBASED_CTLS2); 2499 else 2500 proc2 = 0; 2501 exit = vmx_settable(basic, MSR_VMX_EXIT_CTLS, MSR_VMX_TRUE_EXIT_CTLS); 2502 entry = vmx_settable(basic, MSR_VMX_ENTRY_CTLS, MSR_VMX_TRUE_ENTRY_CTLS); 2503 2504 if (!bootverbose) { 2505 comma = 0; 2506 if (exit & VM_EXIT_SAVE_PAT && exit & VM_EXIT_LOAD_PAT && 2507 entry & VM_ENTRY_LOAD_PAT) { 2508 printf("%sPAT", comma ? "," : ""); 2509 comma = 1; 2510 } 2511 if (proc & PROCBASED_HLT_EXITING) { 2512 printf("%sHLT", comma ? "," : ""); 2513 comma = 1; 2514 } 2515 if (proc & PROCBASED_MTF) { 2516 printf("%sMTF", comma ? "," : ""); 2517 comma = 1; 2518 } 2519 if (proc & PROCBASED_PAUSE_EXITING) { 2520 printf("%sPAUSE", comma ? "," : ""); 2521 comma = 1; 2522 } 2523 if (proc2 & PROCBASED2_ENABLE_EPT) { 2524 printf("%sEPT", comma ? "," : ""); 2525 comma = 1; 2526 } 2527 if (proc2 & PROCBASED2_UNRESTRICTED_GUEST) { 2528 printf("%sUG", comma ? "," : ""); 2529 comma = 1; 2530 } 2531 if (proc2 & PROCBASED2_ENABLE_VPID) { 2532 printf("%sVPID", comma ? "," : ""); 2533 comma = 1; 2534 } 2535 if (proc & PROCBASED_USE_TPR_SHADOW && 2536 proc2 & PROCBASED2_VIRTUALIZE_APIC_ACCESSES && 2537 proc2 & PROCBASED2_VIRTUALIZE_X2APIC_MODE && 2538 proc2 & PROCBASED2_APIC_REGISTER_VIRTUALIZATION && 2539 proc2 & PROCBASED2_VIRTUAL_INTERRUPT_DELIVERY) { 2540 printf("%sVID", comma ? "," : ""); 2541 comma = 1; 2542 if (pin & PINBASED_POSTED_INTERRUPT) 2543 printf(",PostIntr"); 2544 } 2545 return; 2546 } 2547 2548 mask = basic >> 32; 2549 printf("Basic Features=0x%b", mask, 2550 "\020" 2551 "\02132PA" /* 32-bit physical addresses */ 2552 "\022SMM" /* SMM dual-monitor */ 2553 "\027INS/OUTS" /* VM-exit info for INS and OUTS */ 2554 "\030TRUE" /* TRUE_CTLS MSRs */ 2555 ); 2556 printf("\n Pin-Based Controls=0x%b", pin, 2557 "\020" 2558 "\001ExtINT" /* External-interrupt exiting */ 2559 "\004NMI" /* NMI exiting */ 2560 "\006VNMI" /* Virtual NMIs */ 2561 "\007PreTmr" /* Activate VMX-preemption timer */ 2562 "\010PostIntr" /* Process posted interrupts */ 2563 ); 2564 printf("\n Primary Processor Controls=0x%b", proc, 2565 "\020" 2566 "\003INTWIN" /* Interrupt-window exiting */ 2567 "\004TSCOff" /* Use TSC offsetting */ 2568 "\010HLT" /* HLT exiting */ 2569 "\012INVLPG" /* INVLPG exiting */ 2570 "\013MWAIT" /* MWAIT exiting */ 2571 "\014RDPMC" /* RDPMC exiting */ 2572 "\015RDTSC" /* RDTSC exiting */ 2573 "\020CR3-LD" /* CR3-load exiting */ 2574 "\021CR3-ST" /* CR3-store exiting */ 2575 "\024CR8-LD" /* CR8-load exiting */ 2576 "\025CR8-ST" /* CR8-store exiting */ 2577 "\026TPR" /* Use TPR shadow */ 2578 "\027NMIWIN" /* NMI-window exiting */ 2579 "\030MOV-DR" /* MOV-DR exiting */ 2580 "\031IO" /* Unconditional I/O exiting */ 2581 "\032IOmap" /* Use I/O bitmaps */ 2582 "\034MTF" /* Monitor trap flag */ 2583 "\035MSRmap" /* Use MSR bitmaps */ 2584 "\036MONITOR" /* MONITOR exiting */ 2585 "\037PAUSE" /* PAUSE exiting */ 2586 ); 2587 if (proc & PROCBASED_SECONDARY_CONTROLS) 2588 printf("\n Secondary Processor Controls=0x%b", proc2, 2589 "\020" 2590 "\001APIC" /* Virtualize APIC accesses */ 2591 "\002EPT" /* Enable EPT */ 2592 "\003DT" /* Descriptor-table exiting */ 2593 "\004RDTSCP" /* Enable RDTSCP */ 2594 "\005x2APIC" /* Virtualize x2APIC mode */ 2595 "\006VPID" /* Enable VPID */ 2596 "\007WBINVD" /* WBINVD exiting */ 2597 "\010UG" /* Unrestricted guest */ 2598 "\011APIC-reg" /* APIC-register virtualization */ 2599 "\012VID" /* Virtual-interrupt delivery */ 2600 "\013PAUSE-loop" /* PAUSE-loop exiting */ 2601 "\014RDRAND" /* RDRAND exiting */ 2602 "\015INVPCID" /* Enable INVPCID */ 2603 "\016VMFUNC" /* Enable VM functions */ 2604 "\017VMCS" /* VMCS shadowing */ 2605 "\020EPT#VE" /* EPT-violation #VE */ 2606 "\021XSAVES" /* Enable XSAVES/XRSTORS */ 2607 ); 2608 printf("\n Exit Controls=0x%b", mask, 2609 "\020" 2610 "\003DR" /* Save debug controls */ 2611 /* Ignore Host address-space size */ 2612 "\015PERF" /* Load MSR_PERF_GLOBAL_CTRL */ 2613 "\020AckInt" /* Acknowledge interrupt on exit */ 2614 "\023PAT-SV" /* Save MSR_PAT */ 2615 "\024PAT-LD" /* Load MSR_PAT */ 2616 "\025EFER-SV" /* Save MSR_EFER */ 2617 "\026EFER-LD" /* Load MSR_EFER */ 2618 "\027PTMR-SV" /* Save VMX-preemption timer value */ 2619 ); 2620 printf("\n Entry Controls=0x%b", mask, 2621 "\020" 2622 "\003DR" /* Save debug controls */ 2623 /* Ignore IA-32e mode guest */ 2624 /* Ignore Entry to SMM */ 2625 /* Ignore Deactivate dual-monitor treatment */ 2626 "\016PERF" /* Load MSR_PERF_GLOBAL_CTRL */ 2627 "\017PAT" /* Load MSR_PAT */ 2628 "\020EFER" /* Load MSR_EFER */ 2629 ); 2630 if (proc & PROCBASED_SECONDARY_CONTROLS && 2631 (proc2 & (PROCBASED2_ENABLE_EPT | PROCBASED2_ENABLE_VPID)) != 0) { 2632 msr = rdmsr(MSR_VMX_EPT_VPID_CAP); 2633 mask = msr; 2634 printf("\n EPT Features=0x%b", mask, 2635 "\020" 2636 "\001XO" /* Execute-only translations */ 2637 "\007PW4" /* Page-walk length of 4 */ 2638 "\011UC" /* EPT paging-structure mem can be UC */ 2639 "\017WB" /* EPT paging-structure mem can be WB */ 2640 "\0212M" /* EPT PDE can map a 2-Mbyte page */ 2641 "\0221G" /* EPT PDPTE can map a 1-Gbyte page */ 2642 "\025INVEPT" /* INVEPT is supported */ 2643 "\026AD" /* Accessed and dirty flags for EPT */ 2644 "\032single" /* INVEPT single-context type */ 2645 "\033all" /* INVEPT all-context type */ 2646 ); 2647 mask = msr >> 32; 2648 printf("\n VPID Features=0x%b", mask, 2649 "\020" 2650 "\001INVVPID" /* INVVPID is supported */ 2651 "\011individual" /* INVVPID individual-address type */ 2652 "\012single" /* INVVPID single-context type */ 2653 "\013all" /* INVVPID all-context type */ 2654 /* INVVPID single-context-retaining-globals type */ 2655 "\014single-globals" 2656 ); 2657 } 2658 } 2659 2660 static void 2661 print_hypervisor_info(void) 2662 { 2663 2664 if (*hv_vendor != '\0') 2665 printf("Hypervisor: Origin = \"%s\"\n", hv_vendor); 2666 } 2667 2668 /* 2669 * Returns the maximum physical address that can be used with the 2670 * current system. 2671 */ 2672 vm_paddr_t 2673 cpu_getmaxphyaddr(void) 2674 { 2675 2676 #if defined(__i386__) 2677 if (!pae_mode) 2678 return (0xffffffff); 2679 #endif 2680 return ((1ULL << cpu_maxphyaddr) - 1); 2681 } 2682