1 /*- 2 * Copyright (c) 1992 Terrence R. Lambert. 3 * Copyright (c) 1982, 1987, 1990 The Regents of the University of California. 4 * Copyright (c) 1997 KATO Takenori. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to Berkeley by 8 * William Jolitz. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by the University of 21 * California, Berkeley and its contributors. 22 * 4. Neither the name of the University nor the names of its contributors 23 * may be used to endorse or promote products derived from this software 24 * without specific prior written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 27 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 28 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 29 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 30 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 31 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 32 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 33 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 34 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 35 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 36 * SUCH DAMAGE. 37 * 38 * from: Id: machdep.c,v 1.193 1996/06/18 01:22:04 bde Exp 39 */ 40 41 #include <sys/cdefs.h> 42 __FBSDID("$FreeBSD$"); 43 44 #include "opt_cpu.h" 45 46 #include <sys/param.h> 47 #include <sys/bus.h> 48 #include <sys/cpu.h> 49 #include <sys/eventhandler.h> 50 #include <sys/limits.h> 51 #include <sys/systm.h> 52 #include <sys/kernel.h> 53 #include <sys/sysctl.h> 54 #include <sys/power.h> 55 56 #include <machine/asmacros.h> 57 #include <machine/clock.h> 58 #include <machine/cputypes.h> 59 #include <machine/frame.h> 60 #include <machine/intr_machdep.h> 61 #include <machine/md_var.h> 62 #include <machine/segments.h> 63 #include <machine/specialreg.h> 64 65 #include <amd64/vmm/intel/vmx_controls.h> 66 #include <x86/isa/icu.h> 67 #include <x86/vmware.h> 68 69 #ifdef __i386__ 70 #define IDENTBLUE_CYRIX486 0 71 #define IDENTBLUE_IBMCPU 1 72 #define IDENTBLUE_CYRIXM2 2 73 74 static void identifycyrix(void); 75 static void print_transmeta_info(void); 76 #endif 77 static u_int find_cpu_vendor_id(void); 78 static void print_AMD_info(void); 79 static void print_INTEL_info(void); 80 static void print_INTEL_TLB(u_int data); 81 static void print_hypervisor_info(void); 82 static void print_svm_info(void); 83 static void print_via_padlock_info(void); 84 static void print_vmx_info(void); 85 86 #ifdef __i386__ 87 int cpu; /* Are we 386, 386sx, 486, etc? */ 88 int cpu_class; 89 #endif 90 u_int cpu_feature; /* Feature flags */ 91 u_int cpu_feature2; /* Feature flags */ 92 u_int amd_feature; /* AMD feature flags */ 93 u_int amd_feature2; /* AMD feature flags */ 94 u_int amd_rascap; /* AMD RAS capabilities */ 95 u_int amd_pminfo; /* AMD advanced power management info */ 96 u_int amd_extended_feature_extensions; 97 u_int via_feature_rng; /* VIA RNG features */ 98 u_int via_feature_xcrypt; /* VIA ACE features */ 99 u_int cpu_high; /* Highest arg to CPUID */ 100 u_int cpu_exthigh; /* Highest arg to extended CPUID */ 101 u_int cpu_id; /* Stepping ID */ 102 u_int cpu_procinfo; /* HyperThreading Info / Brand Index / CLFUSH */ 103 u_int cpu_procinfo2; /* Multicore info */ 104 char cpu_vendor[20]; /* CPU Origin code */ 105 u_int cpu_vendor_id; /* CPU vendor ID */ 106 u_int cpu_fxsr; /* SSE enabled */ 107 u_int cpu_mxcsr_mask; /* Valid bits in mxcsr */ 108 u_int cpu_clflush_line_size = 32; 109 u_int cpu_stdext_feature; /* %ebx */ 110 u_int cpu_stdext_feature2; /* %ecx */ 111 u_int cpu_stdext_feature3; /* %edx */ 112 uint64_t cpu_ia32_arch_caps; 113 u_int cpu_max_ext_state_size; 114 u_int cpu_mon_mwait_flags; /* MONITOR/MWAIT flags (CPUID.05H.ECX) */ 115 u_int cpu_mon_min_size; /* MONITOR minimum range size, bytes */ 116 u_int cpu_mon_max_size; /* MONITOR minimum range size, bytes */ 117 u_int cpu_maxphyaddr; /* Max phys addr width in bits */ 118 char machine[] = MACHINE; 119 120 SYSCTL_UINT(_hw, OID_AUTO, via_feature_rng, CTLFLAG_RD, 121 &via_feature_rng, 0, 122 "VIA RNG feature available in CPU"); 123 SYSCTL_UINT(_hw, OID_AUTO, via_feature_xcrypt, CTLFLAG_RD, 124 &via_feature_xcrypt, 0, 125 "VIA xcrypt feature available in CPU"); 126 127 #ifdef __amd64__ 128 #ifdef SCTL_MASK32 129 extern int adaptive_machine_arch; 130 #endif 131 132 static int 133 sysctl_hw_machine(SYSCTL_HANDLER_ARGS) 134 { 135 #ifdef SCTL_MASK32 136 static const char machine32[] = "i386"; 137 #endif 138 int error; 139 140 #ifdef SCTL_MASK32 141 if ((req->flags & SCTL_MASK32) != 0 && adaptive_machine_arch) 142 error = SYSCTL_OUT(req, machine32, sizeof(machine32)); 143 else 144 #endif 145 error = SYSCTL_OUT(req, machine, sizeof(machine)); 146 return (error); 147 148 } 149 SYSCTL_PROC(_hw, HW_MACHINE, machine, CTLTYPE_STRING | CTLFLAG_RD | 150 CTLFLAG_MPSAFE, NULL, 0, sysctl_hw_machine, "A", "Machine class"); 151 #else 152 SYSCTL_STRING(_hw, HW_MACHINE, machine, CTLFLAG_RD, 153 machine, 0, "Machine class"); 154 #endif 155 156 static char cpu_model[128]; 157 SYSCTL_STRING(_hw, HW_MODEL, model, CTLFLAG_RD | CTLFLAG_MPSAFE, 158 cpu_model, 0, "Machine model"); 159 160 static int hw_clockrate; 161 SYSCTL_INT(_hw, OID_AUTO, clockrate, CTLFLAG_RD, 162 &hw_clockrate, 0, "CPU instruction clock rate"); 163 164 u_int hv_high; 165 char hv_vendor[16]; 166 SYSCTL_STRING(_hw, OID_AUTO, hv_vendor, CTLFLAG_RD | CTLFLAG_MPSAFE, hv_vendor, 167 0, "Hypervisor vendor"); 168 169 static eventhandler_tag tsc_post_tag; 170 171 static char cpu_brand[48]; 172 173 #ifdef __i386__ 174 #define MAX_BRAND_INDEX 8 175 176 static const char *cpu_brandtable[MAX_BRAND_INDEX + 1] = { 177 NULL, /* No brand */ 178 "Intel Celeron", 179 "Intel Pentium III", 180 "Intel Pentium III Xeon", 181 NULL, 182 NULL, 183 NULL, 184 NULL, 185 "Intel Pentium 4" 186 }; 187 188 static struct { 189 char *cpu_name; 190 int cpu_class; 191 } cpus[] = { 192 { "Intel 80286", CPUCLASS_286 }, /* CPU_286 */ 193 { "i386SX", CPUCLASS_386 }, /* CPU_386SX */ 194 { "i386DX", CPUCLASS_386 }, /* CPU_386 */ 195 { "i486SX", CPUCLASS_486 }, /* CPU_486SX */ 196 { "i486DX", CPUCLASS_486 }, /* CPU_486 */ 197 { "Pentium", CPUCLASS_586 }, /* CPU_586 */ 198 { "Cyrix 486", CPUCLASS_486 }, /* CPU_486DLC */ 199 { "Pentium Pro", CPUCLASS_686 }, /* CPU_686 */ 200 { "Cyrix 5x86", CPUCLASS_486 }, /* CPU_M1SC */ 201 { "Cyrix 6x86", CPUCLASS_486 }, /* CPU_M1 */ 202 { "Blue Lightning", CPUCLASS_486 }, /* CPU_BLUE */ 203 { "Cyrix 6x86MX", CPUCLASS_686 }, /* CPU_M2 */ 204 { "NexGen 586", CPUCLASS_386 }, /* CPU_NX586 (XXX) */ 205 { "Cyrix 486S/DX", CPUCLASS_486 }, /* CPU_CY486DX */ 206 { "Pentium II", CPUCLASS_686 }, /* CPU_PII */ 207 { "Pentium III", CPUCLASS_686 }, /* CPU_PIII */ 208 { "Pentium 4", CPUCLASS_686 }, /* CPU_P4 */ 209 }; 210 #endif 211 212 static struct { 213 char *vendor; 214 u_int vendor_id; 215 } cpu_vendors[] = { 216 { INTEL_VENDOR_ID, CPU_VENDOR_INTEL }, /* GenuineIntel */ 217 { AMD_VENDOR_ID, CPU_VENDOR_AMD }, /* AuthenticAMD */ 218 { CENTAUR_VENDOR_ID, CPU_VENDOR_CENTAUR }, /* CentaurHauls */ 219 #ifdef __i386__ 220 { NSC_VENDOR_ID, CPU_VENDOR_NSC }, /* Geode by NSC */ 221 { CYRIX_VENDOR_ID, CPU_VENDOR_CYRIX }, /* CyrixInstead */ 222 { TRANSMETA_VENDOR_ID, CPU_VENDOR_TRANSMETA }, /* GenuineTMx86 */ 223 { SIS_VENDOR_ID, CPU_VENDOR_SIS }, /* SiS SiS SiS */ 224 { UMC_VENDOR_ID, CPU_VENDOR_UMC }, /* UMC UMC UMC */ 225 { NEXGEN_VENDOR_ID, CPU_VENDOR_NEXGEN }, /* NexGenDriven */ 226 { RISE_VENDOR_ID, CPU_VENDOR_RISE }, /* RiseRiseRise */ 227 #if 0 228 /* XXX CPUID 8000_0000h and 8086_0000h, not 0000_0000h */ 229 { "TransmetaCPU", CPU_VENDOR_TRANSMETA }, 230 #endif 231 #endif 232 }; 233 234 void 235 printcpuinfo(void) 236 { 237 u_int regs[4], i; 238 char *brand; 239 240 printf("CPU: "); 241 #ifdef __i386__ 242 cpu_class = cpus[cpu].cpu_class; 243 strncpy(cpu_model, cpus[cpu].cpu_name, sizeof (cpu_model)); 244 #else 245 strncpy(cpu_model, "Hammer", sizeof (cpu_model)); 246 #endif 247 248 /* Check for extended CPUID information and a processor name. */ 249 if (cpu_exthigh >= 0x80000004) { 250 brand = cpu_brand; 251 for (i = 0x80000002; i < 0x80000005; i++) { 252 do_cpuid(i, regs); 253 memcpy(brand, regs, sizeof(regs)); 254 brand += sizeof(regs); 255 } 256 } 257 258 switch (cpu_vendor_id) { 259 case CPU_VENDOR_INTEL: 260 #ifdef __i386__ 261 if ((cpu_id & 0xf00) > 0x300) { 262 u_int brand_index; 263 264 cpu_model[0] = '\0'; 265 266 switch (cpu_id & 0x3000) { 267 case 0x1000: 268 strcpy(cpu_model, "Overdrive "); 269 break; 270 case 0x2000: 271 strcpy(cpu_model, "Dual "); 272 break; 273 } 274 275 switch (cpu_id & 0xf00) { 276 case 0x400: 277 strcat(cpu_model, "i486 "); 278 /* Check the particular flavor of 486 */ 279 switch (cpu_id & 0xf0) { 280 case 0x00: 281 case 0x10: 282 strcat(cpu_model, "DX"); 283 break; 284 case 0x20: 285 strcat(cpu_model, "SX"); 286 break; 287 case 0x30: 288 strcat(cpu_model, "DX2"); 289 break; 290 case 0x40: 291 strcat(cpu_model, "SL"); 292 break; 293 case 0x50: 294 strcat(cpu_model, "SX2"); 295 break; 296 case 0x70: 297 strcat(cpu_model, 298 "DX2 Write-Back Enhanced"); 299 break; 300 case 0x80: 301 strcat(cpu_model, "DX4"); 302 break; 303 } 304 break; 305 case 0x500: 306 /* Check the particular flavor of 586 */ 307 strcat(cpu_model, "Pentium"); 308 switch (cpu_id & 0xf0) { 309 case 0x00: 310 strcat(cpu_model, " A-step"); 311 break; 312 case 0x10: 313 strcat(cpu_model, "/P5"); 314 break; 315 case 0x20: 316 strcat(cpu_model, "/P54C"); 317 break; 318 case 0x30: 319 strcat(cpu_model, "/P24T"); 320 break; 321 case 0x40: 322 strcat(cpu_model, "/P55C"); 323 break; 324 case 0x70: 325 strcat(cpu_model, "/P54C"); 326 break; 327 case 0x80: 328 strcat(cpu_model, "/P55C (quarter-micron)"); 329 break; 330 default: 331 /* nothing */ 332 break; 333 } 334 #if defined(I586_CPU) && !defined(NO_F00F_HACK) 335 /* 336 * XXX - If/when Intel fixes the bug, this 337 * should also check the version of the 338 * CPU, not just that it's a Pentium. 339 */ 340 has_f00f_bug = 1; 341 #endif 342 break; 343 case 0x600: 344 /* Check the particular flavor of 686 */ 345 switch (cpu_id & 0xf0) { 346 case 0x00: 347 strcat(cpu_model, "Pentium Pro A-step"); 348 break; 349 case 0x10: 350 strcat(cpu_model, "Pentium Pro"); 351 break; 352 case 0x30: 353 case 0x50: 354 case 0x60: 355 strcat(cpu_model, 356 "Pentium II/Pentium II Xeon/Celeron"); 357 cpu = CPU_PII; 358 break; 359 case 0x70: 360 case 0x80: 361 case 0xa0: 362 case 0xb0: 363 strcat(cpu_model, 364 "Pentium III/Pentium III Xeon/Celeron"); 365 cpu = CPU_PIII; 366 break; 367 default: 368 strcat(cpu_model, "Unknown 80686"); 369 break; 370 } 371 break; 372 case 0xf00: 373 strcat(cpu_model, "Pentium 4"); 374 cpu = CPU_P4; 375 break; 376 default: 377 strcat(cpu_model, "unknown"); 378 break; 379 } 380 381 /* 382 * If we didn't get a brand name from the extended 383 * CPUID, try to look it up in the brand table. 384 */ 385 if (cpu_high > 0 && *cpu_brand == '\0') { 386 brand_index = cpu_procinfo & CPUID_BRAND_INDEX; 387 if (brand_index <= MAX_BRAND_INDEX && 388 cpu_brandtable[brand_index] != NULL) 389 strcpy(cpu_brand, 390 cpu_brandtable[brand_index]); 391 } 392 } 393 #else 394 /* Please make up your mind folks! */ 395 strcat(cpu_model, "EM64T"); 396 #endif 397 break; 398 case CPU_VENDOR_AMD: 399 /* 400 * Values taken from AMD Processor Recognition 401 * http://www.amd.com/K6/k6docs/pdf/20734g.pdf 402 * (also describes ``Features'' encodings. 403 */ 404 strcpy(cpu_model, "AMD "); 405 #ifdef __i386__ 406 switch (cpu_id & 0xFF0) { 407 case 0x410: 408 strcat(cpu_model, "Standard Am486DX"); 409 break; 410 case 0x430: 411 strcat(cpu_model, "Enhanced Am486DX2 Write-Through"); 412 break; 413 case 0x470: 414 strcat(cpu_model, "Enhanced Am486DX2 Write-Back"); 415 break; 416 case 0x480: 417 strcat(cpu_model, "Enhanced Am486DX4/Am5x86 Write-Through"); 418 break; 419 case 0x490: 420 strcat(cpu_model, "Enhanced Am486DX4/Am5x86 Write-Back"); 421 break; 422 case 0x4E0: 423 strcat(cpu_model, "Am5x86 Write-Through"); 424 break; 425 case 0x4F0: 426 strcat(cpu_model, "Am5x86 Write-Back"); 427 break; 428 case 0x500: 429 strcat(cpu_model, "K5 model 0"); 430 break; 431 case 0x510: 432 strcat(cpu_model, "K5 model 1"); 433 break; 434 case 0x520: 435 strcat(cpu_model, "K5 PR166 (model 2)"); 436 break; 437 case 0x530: 438 strcat(cpu_model, "K5 PR200 (model 3)"); 439 break; 440 case 0x560: 441 strcat(cpu_model, "K6"); 442 break; 443 case 0x570: 444 strcat(cpu_model, "K6 266 (model 1)"); 445 break; 446 case 0x580: 447 strcat(cpu_model, "K6-2"); 448 break; 449 case 0x590: 450 strcat(cpu_model, "K6-III"); 451 break; 452 case 0x5a0: 453 strcat(cpu_model, "Geode LX"); 454 break; 455 default: 456 strcat(cpu_model, "Unknown"); 457 break; 458 } 459 #else 460 if ((cpu_id & 0xf00) == 0xf00) 461 strcat(cpu_model, "AMD64 Processor"); 462 else 463 strcat(cpu_model, "Unknown"); 464 #endif 465 break; 466 #ifdef __i386__ 467 case CPU_VENDOR_CYRIX: 468 strcpy(cpu_model, "Cyrix "); 469 switch (cpu_id & 0xff0) { 470 case 0x440: 471 strcat(cpu_model, "MediaGX"); 472 break; 473 case 0x520: 474 strcat(cpu_model, "6x86"); 475 break; 476 case 0x540: 477 cpu_class = CPUCLASS_586; 478 strcat(cpu_model, "GXm"); 479 break; 480 case 0x600: 481 strcat(cpu_model, "6x86MX"); 482 break; 483 default: 484 /* 485 * Even though CPU supports the cpuid 486 * instruction, it can be disabled. 487 * Therefore, this routine supports all Cyrix 488 * CPUs. 489 */ 490 switch (cyrix_did & 0xf0) { 491 case 0x00: 492 switch (cyrix_did & 0x0f) { 493 case 0x00: 494 strcat(cpu_model, "486SLC"); 495 break; 496 case 0x01: 497 strcat(cpu_model, "486DLC"); 498 break; 499 case 0x02: 500 strcat(cpu_model, "486SLC2"); 501 break; 502 case 0x03: 503 strcat(cpu_model, "486DLC2"); 504 break; 505 case 0x04: 506 strcat(cpu_model, "486SRx"); 507 break; 508 case 0x05: 509 strcat(cpu_model, "486DRx"); 510 break; 511 case 0x06: 512 strcat(cpu_model, "486SRx2"); 513 break; 514 case 0x07: 515 strcat(cpu_model, "486DRx2"); 516 break; 517 case 0x08: 518 strcat(cpu_model, "486SRu"); 519 break; 520 case 0x09: 521 strcat(cpu_model, "486DRu"); 522 break; 523 case 0x0a: 524 strcat(cpu_model, "486SRu2"); 525 break; 526 case 0x0b: 527 strcat(cpu_model, "486DRu2"); 528 break; 529 default: 530 strcat(cpu_model, "Unknown"); 531 break; 532 } 533 break; 534 case 0x10: 535 switch (cyrix_did & 0x0f) { 536 case 0x00: 537 strcat(cpu_model, "486S"); 538 break; 539 case 0x01: 540 strcat(cpu_model, "486S2"); 541 break; 542 case 0x02: 543 strcat(cpu_model, "486Se"); 544 break; 545 case 0x03: 546 strcat(cpu_model, "486S2e"); 547 break; 548 case 0x0a: 549 strcat(cpu_model, "486DX"); 550 break; 551 case 0x0b: 552 strcat(cpu_model, "486DX2"); 553 break; 554 case 0x0f: 555 strcat(cpu_model, "486DX4"); 556 break; 557 default: 558 strcat(cpu_model, "Unknown"); 559 break; 560 } 561 break; 562 case 0x20: 563 if ((cyrix_did & 0x0f) < 8) 564 strcat(cpu_model, "6x86"); /* Where did you get it? */ 565 else 566 strcat(cpu_model, "5x86"); 567 break; 568 case 0x30: 569 strcat(cpu_model, "6x86"); 570 break; 571 case 0x40: 572 if ((cyrix_did & 0xf000) == 0x3000) { 573 cpu_class = CPUCLASS_586; 574 strcat(cpu_model, "GXm"); 575 } else 576 strcat(cpu_model, "MediaGX"); 577 break; 578 case 0x50: 579 strcat(cpu_model, "6x86MX"); 580 break; 581 case 0xf0: 582 switch (cyrix_did & 0x0f) { 583 case 0x0d: 584 strcat(cpu_model, "Overdrive CPU"); 585 break; 586 case 0x0e: 587 strcpy(cpu_model, "Texas Instruments 486SXL"); 588 break; 589 case 0x0f: 590 strcat(cpu_model, "486SLC/DLC"); 591 break; 592 default: 593 strcat(cpu_model, "Unknown"); 594 break; 595 } 596 break; 597 default: 598 strcat(cpu_model, "Unknown"); 599 break; 600 } 601 break; 602 } 603 break; 604 case CPU_VENDOR_RISE: 605 strcpy(cpu_model, "Rise "); 606 switch (cpu_id & 0xff0) { 607 case 0x500: /* 6401 and 6441 (Kirin) */ 608 case 0x520: /* 6510 (Lynx) */ 609 strcat(cpu_model, "mP6"); 610 break; 611 default: 612 strcat(cpu_model, "Unknown"); 613 } 614 break; 615 #endif 616 case CPU_VENDOR_CENTAUR: 617 #ifdef __i386__ 618 switch (cpu_id & 0xff0) { 619 case 0x540: 620 strcpy(cpu_model, "IDT WinChip C6"); 621 break; 622 case 0x580: 623 strcpy(cpu_model, "IDT WinChip 2"); 624 break; 625 case 0x590: 626 strcpy(cpu_model, "IDT WinChip 3"); 627 break; 628 case 0x660: 629 strcpy(cpu_model, "VIA C3 Samuel"); 630 break; 631 case 0x670: 632 if (cpu_id & 0x8) 633 strcpy(cpu_model, "VIA C3 Ezra"); 634 else 635 strcpy(cpu_model, "VIA C3 Samuel 2"); 636 break; 637 case 0x680: 638 strcpy(cpu_model, "VIA C3 Ezra-T"); 639 break; 640 case 0x690: 641 strcpy(cpu_model, "VIA C3 Nehemiah"); 642 break; 643 case 0x6a0: 644 case 0x6d0: 645 strcpy(cpu_model, "VIA C7 Esther"); 646 break; 647 case 0x6f0: 648 strcpy(cpu_model, "VIA Nano"); 649 break; 650 default: 651 strcpy(cpu_model, "VIA/IDT Unknown"); 652 } 653 #else 654 strcpy(cpu_model, "VIA "); 655 if ((cpu_id & 0xff0) == 0x6f0) 656 strcat(cpu_model, "Nano Processor"); 657 else 658 strcat(cpu_model, "Unknown"); 659 #endif 660 break; 661 #ifdef __i386__ 662 case CPU_VENDOR_IBM: 663 strcpy(cpu_model, "Blue Lightning CPU"); 664 break; 665 case CPU_VENDOR_NSC: 666 switch (cpu_id & 0xff0) { 667 case 0x540: 668 strcpy(cpu_model, "Geode SC1100"); 669 cpu = CPU_GEODE1100; 670 break; 671 default: 672 strcpy(cpu_model, "Geode/NSC unknown"); 673 break; 674 } 675 break; 676 #endif 677 default: 678 strcat(cpu_model, "Unknown"); 679 break; 680 } 681 682 /* 683 * Replace cpu_model with cpu_brand minus leading spaces if 684 * we have one. 685 */ 686 brand = cpu_brand; 687 while (*brand == ' ') 688 ++brand; 689 if (*brand != '\0') 690 strcpy(cpu_model, brand); 691 692 printf("%s (", cpu_model); 693 if (tsc_freq != 0) { 694 hw_clockrate = (tsc_freq + 5000) / 1000000; 695 printf("%jd.%02d-MHz ", 696 (intmax_t)(tsc_freq + 4999) / 1000000, 697 (u_int)((tsc_freq + 4999) / 10000) % 100); 698 } 699 #ifdef __i386__ 700 switch(cpu_class) { 701 case CPUCLASS_286: 702 printf("286"); 703 break; 704 case CPUCLASS_386: 705 printf("386"); 706 break; 707 #if defined(I486_CPU) 708 case CPUCLASS_486: 709 printf("486"); 710 break; 711 #endif 712 #if defined(I586_CPU) 713 case CPUCLASS_586: 714 printf("586"); 715 break; 716 #endif 717 #if defined(I686_CPU) 718 case CPUCLASS_686: 719 printf("686"); 720 break; 721 #endif 722 default: 723 printf("Unknown"); /* will panic below... */ 724 } 725 #else 726 printf("K8"); 727 #endif 728 printf("-class CPU)\n"); 729 if (*cpu_vendor) 730 printf(" Origin=\"%s\"", cpu_vendor); 731 if (cpu_id) 732 printf(" Id=0x%x", cpu_id); 733 734 if (cpu_vendor_id == CPU_VENDOR_INTEL || 735 cpu_vendor_id == CPU_VENDOR_AMD || 736 cpu_vendor_id == CPU_VENDOR_CENTAUR || 737 #ifdef __i386__ 738 cpu_vendor_id == CPU_VENDOR_TRANSMETA || 739 cpu_vendor_id == CPU_VENDOR_RISE || 740 cpu_vendor_id == CPU_VENDOR_NSC || 741 (cpu_vendor_id == CPU_VENDOR_CYRIX && ((cpu_id & 0xf00) > 0x500)) || 742 #endif 743 0) { 744 printf(" Family=0x%x", CPUID_TO_FAMILY(cpu_id)); 745 printf(" Model=0x%x", CPUID_TO_MODEL(cpu_id)); 746 printf(" Stepping=%u", cpu_id & CPUID_STEPPING); 747 #ifdef __i386__ 748 if (cpu_vendor_id == CPU_VENDOR_CYRIX) 749 printf("\n DIR=0x%04x", cyrix_did); 750 #endif 751 752 /* 753 * AMD CPUID Specification 754 * http://support.amd.com/us/Embedded_TechDocs/25481.pdf 755 * 756 * Intel Processor Identification and CPUID Instruction 757 * http://www.intel.com/assets/pdf/appnote/241618.pdf 758 */ 759 if (cpu_high > 0) { 760 761 /* 762 * Here we should probably set up flags indicating 763 * whether or not various features are available. 764 * The interesting ones are probably VME, PSE, PAE, 765 * and PGE. The code already assumes without bothering 766 * to check that all CPUs >= Pentium have a TSC and 767 * MSRs. 768 */ 769 printf("\n Features=0x%b", cpu_feature, 770 "\020" 771 "\001FPU" /* Integral FPU */ 772 "\002VME" /* Extended VM86 mode support */ 773 "\003DE" /* Debugging Extensions (CR4.DE) */ 774 "\004PSE" /* 4MByte page tables */ 775 "\005TSC" /* Timestamp counter */ 776 "\006MSR" /* Machine specific registers */ 777 "\007PAE" /* Physical address extension */ 778 "\010MCE" /* Machine Check support */ 779 "\011CX8" /* CMPEXCH8 instruction */ 780 "\012APIC" /* SMP local APIC */ 781 "\013oldMTRR" /* Previous implementation of MTRR */ 782 "\014SEP" /* Fast System Call */ 783 "\015MTRR" /* Memory Type Range Registers */ 784 "\016PGE" /* PG_G (global bit) support */ 785 "\017MCA" /* Machine Check Architecture */ 786 "\020CMOV" /* CMOV instruction */ 787 "\021PAT" /* Page attributes table */ 788 "\022PSE36" /* 36 bit address space support */ 789 "\023PN" /* Processor Serial number */ 790 "\024CLFLUSH" /* Has the CLFLUSH instruction */ 791 "\025<b20>" 792 "\026DTS" /* Debug Trace Store */ 793 "\027ACPI" /* ACPI support */ 794 "\030MMX" /* MMX instructions */ 795 "\031FXSR" /* FXSAVE/FXRSTOR */ 796 "\032SSE" /* Streaming SIMD Extensions */ 797 "\033SSE2" /* Streaming SIMD Extensions #2 */ 798 "\034SS" /* Self snoop */ 799 "\035HTT" /* Hyperthreading (see EBX bit 16-23) */ 800 "\036TM" /* Thermal Monitor clock slowdown */ 801 "\037IA64" /* CPU can execute IA64 instructions */ 802 "\040PBE" /* Pending Break Enable */ 803 ); 804 805 if (cpu_feature2 != 0) { 806 printf("\n Features2=0x%b", cpu_feature2, 807 "\020" 808 "\001SSE3" /* SSE3 */ 809 "\002PCLMULQDQ" /* Carry-Less Mul Quadword */ 810 "\003DTES64" /* 64-bit Debug Trace */ 811 "\004MON" /* MONITOR/MWAIT Instructions */ 812 "\005DS_CPL" /* CPL Qualified Debug Store */ 813 "\006VMX" /* Virtual Machine Extensions */ 814 "\007SMX" /* Safer Mode Extensions */ 815 "\010EST" /* Enhanced SpeedStep */ 816 "\011TM2" /* Thermal Monitor 2 */ 817 "\012SSSE3" /* SSSE3 */ 818 "\013CNXT-ID" /* L1 context ID available */ 819 "\014SDBG" /* IA32 silicon debug */ 820 "\015FMA" /* Fused Multiply Add */ 821 "\016CX16" /* CMPXCHG16B Instruction */ 822 "\017xTPR" /* Send Task Priority Messages*/ 823 "\020PDCM" /* Perf/Debug Capability MSR */ 824 "\021<b16>" 825 "\022PCID" /* Process-context Identifiers*/ 826 "\023DCA" /* Direct Cache Access */ 827 "\024SSE4.1" /* SSE 4.1 */ 828 "\025SSE4.2" /* SSE 4.2 */ 829 "\026x2APIC" /* xAPIC Extensions */ 830 "\027MOVBE" /* MOVBE Instruction */ 831 "\030POPCNT" /* POPCNT Instruction */ 832 "\031TSCDLT" /* TSC-Deadline Timer */ 833 "\032AESNI" /* AES Crypto */ 834 "\033XSAVE" /* XSAVE/XRSTOR States */ 835 "\034OSXSAVE" /* OS-Enabled State Management*/ 836 "\035AVX" /* Advanced Vector Extensions */ 837 "\036F16C" /* Half-precision conversions */ 838 "\037RDRAND" /* RDRAND Instruction */ 839 "\040HV" /* Hypervisor */ 840 ); 841 } 842 843 if (amd_feature != 0) { 844 printf("\n AMD Features=0x%b", amd_feature, 845 "\020" /* in hex */ 846 "\001<s0>" /* Same */ 847 "\002<s1>" /* Same */ 848 "\003<s2>" /* Same */ 849 "\004<s3>" /* Same */ 850 "\005<s4>" /* Same */ 851 "\006<s5>" /* Same */ 852 "\007<s6>" /* Same */ 853 "\010<s7>" /* Same */ 854 "\011<s8>" /* Same */ 855 "\012<s9>" /* Same */ 856 "\013<b10>" /* Undefined */ 857 "\014SYSCALL" /* Have SYSCALL/SYSRET */ 858 "\015<s12>" /* Same */ 859 "\016<s13>" /* Same */ 860 "\017<s14>" /* Same */ 861 "\020<s15>" /* Same */ 862 "\021<s16>" /* Same */ 863 "\022<s17>" /* Same */ 864 "\023<b18>" /* Reserved, unknown */ 865 "\024MP" /* Multiprocessor Capable */ 866 "\025NX" /* Has EFER.NXE, NX */ 867 "\026<b21>" /* Undefined */ 868 "\027MMX+" /* AMD MMX Extensions */ 869 "\030<s23>" /* Same */ 870 "\031<s24>" /* Same */ 871 "\032FFXSR" /* Fast FXSAVE/FXRSTOR */ 872 "\033Page1GB" /* 1-GB large page support */ 873 "\034RDTSCP" /* RDTSCP */ 874 "\035<b28>" /* Undefined */ 875 "\036LM" /* 64 bit long mode */ 876 "\0373DNow!+" /* AMD 3DNow! Extensions */ 877 "\0403DNow!" /* AMD 3DNow! */ 878 ); 879 } 880 881 if (amd_feature2 != 0) { 882 printf("\n AMD Features2=0x%b", amd_feature2, 883 "\020" 884 "\001LAHF" /* LAHF/SAHF in long mode */ 885 "\002CMP" /* CMP legacy */ 886 "\003SVM" /* Secure Virtual Mode */ 887 "\004ExtAPIC" /* Extended APIC register */ 888 "\005CR8" /* CR8 in legacy mode */ 889 "\006ABM" /* LZCNT instruction */ 890 "\007SSE4A" /* SSE4A */ 891 "\010MAS" /* Misaligned SSE mode */ 892 "\011Prefetch" /* 3DNow! Prefetch/PrefetchW */ 893 "\012OSVW" /* OS visible workaround */ 894 "\013IBS" /* Instruction based sampling */ 895 "\014XOP" /* XOP extended instructions */ 896 "\015SKINIT" /* SKINIT/STGI */ 897 "\016WDT" /* Watchdog timer */ 898 "\017<b14>" 899 "\020LWP" /* Lightweight Profiling */ 900 "\021FMA4" /* 4-operand FMA instructions */ 901 "\022TCE" /* Translation Cache Extension */ 902 "\023<b18>" 903 "\024NodeId" /* NodeId MSR support */ 904 "\025<b20>" 905 "\026TBM" /* Trailing Bit Manipulation */ 906 "\027Topology" /* Topology Extensions */ 907 "\030PCXC" /* Core perf count */ 908 "\031PNXC" /* NB perf count */ 909 "\032<b25>" 910 "\033DBE" /* Data Breakpoint extension */ 911 "\034PTSC" /* Performance TSC */ 912 "\035PL2I" /* L2I perf count */ 913 "\036MWAITX" /* MONITORX/MWAITX instructions */ 914 "\037<b30>" 915 "\040<b31>" 916 ); 917 } 918 919 if (cpu_stdext_feature != 0) { 920 printf("\n Structured Extended Features=0x%b", 921 cpu_stdext_feature, 922 "\020" 923 /* RDFSBASE/RDGSBASE/WRFSBASE/WRGSBASE */ 924 "\001FSGSBASE" 925 "\002TSCADJ" 926 "\003SGX" 927 /* Bit Manipulation Instructions */ 928 "\004BMI1" 929 /* Hardware Lock Elision */ 930 "\005HLE" 931 /* Advanced Vector Instructions 2 */ 932 "\006AVX2" 933 /* FDP_EXCPTN_ONLY */ 934 "\007FDPEXC" 935 /* Supervisor Mode Execution Prot. */ 936 "\010SMEP" 937 /* Bit Manipulation Instructions */ 938 "\011BMI2" 939 "\012ERMS" 940 /* Invalidate Processor Context ID */ 941 "\013INVPCID" 942 /* Restricted Transactional Memory */ 943 "\014RTM" 944 "\015PQM" 945 "\016NFPUSG" 946 /* Intel Memory Protection Extensions */ 947 "\017MPX" 948 "\020PQE" 949 /* AVX512 Foundation */ 950 "\021AVX512F" 951 "\022AVX512DQ" 952 /* Enhanced NRBG */ 953 "\023RDSEED" 954 /* ADCX + ADOX */ 955 "\024ADX" 956 /* Supervisor Mode Access Prevention */ 957 "\025SMAP" 958 "\026AVX512IFMA" 959 "\027PCOMMIT" 960 "\030CLFLUSHOPT" 961 "\031CLWB" 962 "\032PROCTRACE" 963 "\033AVX512PF" 964 "\034AVX512ER" 965 "\035AVX512CD" 966 "\036SHA" 967 "\037AVX512BW" 968 "\040AVX512VL" 969 ); 970 } 971 972 if (cpu_stdext_feature2 != 0) { 973 printf("\n Structured Extended Features2=0x%b", 974 cpu_stdext_feature2, 975 "\020" 976 "\001PREFETCHWT1" 977 "\002AVX512VBMI" 978 "\003UMIP" 979 "\004PKU" 980 "\005OSPKE" 981 "\027RDPID" 982 "\037SGXLC" 983 ); 984 } 985 986 if (cpu_stdext_feature3 != 0) { 987 printf("\n Structured Extended Features3=0x%b", 988 cpu_stdext_feature3, 989 "\020" 990 "\033IBPB" 991 "\034STIBP" 992 "\036ARCH_CAP" 993 "\040SSBD" 994 ); 995 } 996 997 if ((cpu_feature2 & CPUID2_XSAVE) != 0) { 998 cpuid_count(0xd, 0x1, regs); 999 if (regs[0] != 0) { 1000 printf("\n XSAVE Features=0x%b", 1001 regs[0], 1002 "\020" 1003 "\001XSAVEOPT" 1004 "\002XSAVEC" 1005 "\003XINUSE" 1006 "\004XSAVES"); 1007 } 1008 } 1009 1010 if (cpu_ia32_arch_caps != 0) { 1011 printf("\n IA32_ARCH_CAPS=0x%b", 1012 (u_int)cpu_ia32_arch_caps, 1013 "\020" 1014 "\001RDCL_NO" 1015 "\002IBRS_ALL" 1016 ); 1017 } 1018 1019 if (amd_extended_feature_extensions != 0) { 1020 printf("\n " 1021 "AMD Extended Feature Extensions ID EBX=" 1022 "0x%b", amd_extended_feature_extensions, 1023 "\020" 1024 "\001CLZERO" 1025 "\002IRPerf" 1026 "\003XSaveErPtr"); 1027 } 1028 1029 if (via_feature_rng != 0 || via_feature_xcrypt != 0) 1030 print_via_padlock_info(); 1031 1032 if (cpu_feature2 & CPUID2_VMX) 1033 print_vmx_info(); 1034 1035 if (amd_feature2 & AMDID2_SVM) 1036 print_svm_info(); 1037 1038 if ((cpu_feature & CPUID_HTT) && 1039 cpu_vendor_id == CPU_VENDOR_AMD) 1040 cpu_feature &= ~CPUID_HTT; 1041 1042 /* 1043 * If this CPU supports P-state invariant TSC then 1044 * mention the capability. 1045 */ 1046 if (tsc_is_invariant) { 1047 printf("\n TSC: P-state invariant"); 1048 if (tsc_perf_stat) 1049 printf(", performance statistics"); 1050 } 1051 } 1052 #ifdef __i386__ 1053 } else if (cpu_vendor_id == CPU_VENDOR_CYRIX) { 1054 printf(" DIR=0x%04x", cyrix_did); 1055 printf(" Stepping=%u", (cyrix_did & 0xf000) >> 12); 1056 printf(" Revision=%u", (cyrix_did & 0x0f00) >> 8); 1057 #ifndef CYRIX_CACHE_REALLY_WORKS 1058 if (cpu == CPU_M1 && (cyrix_did & 0xff00) < 0x1700) 1059 printf("\n CPU cache: write-through mode"); 1060 #endif 1061 #endif 1062 } 1063 1064 /* Avoid ugly blank lines: only print newline when we have to. */ 1065 if (*cpu_vendor || cpu_id) 1066 printf("\n"); 1067 1068 if (bootverbose) { 1069 if (cpu_vendor_id == CPU_VENDOR_AMD) 1070 print_AMD_info(); 1071 else if (cpu_vendor_id == CPU_VENDOR_INTEL) 1072 print_INTEL_info(); 1073 #ifdef __i386__ 1074 else if (cpu_vendor_id == CPU_VENDOR_TRANSMETA) 1075 print_transmeta_info(); 1076 #endif 1077 } 1078 1079 print_hypervisor_info(); 1080 } 1081 1082 #ifdef __i386__ 1083 void 1084 panicifcpuunsupported(void) 1085 { 1086 1087 #if !defined(lint) 1088 #if !defined(I486_CPU) && !defined(I586_CPU) && !defined(I686_CPU) 1089 #error This kernel is not configured for one of the supported CPUs 1090 #endif 1091 #else /* lint */ 1092 #endif /* lint */ 1093 /* 1094 * Now that we have told the user what they have, 1095 * let them know if that machine type isn't configured. 1096 */ 1097 switch (cpu_class) { 1098 case CPUCLASS_286: /* a 286 should not make it this far, anyway */ 1099 case CPUCLASS_386: 1100 #if !defined(I486_CPU) 1101 case CPUCLASS_486: 1102 #endif 1103 #if !defined(I586_CPU) 1104 case CPUCLASS_586: 1105 #endif 1106 #if !defined(I686_CPU) 1107 case CPUCLASS_686: 1108 #endif 1109 panic("CPU class not configured"); 1110 default: 1111 break; 1112 } 1113 } 1114 1115 static volatile u_int trap_by_rdmsr; 1116 1117 /* 1118 * Special exception 6 handler. 1119 * The rdmsr instruction generates invalid opcodes fault on 486-class 1120 * Cyrix CPU. Stacked eip register points the rdmsr instruction in the 1121 * function identblue() when this handler is called. Stacked eip should 1122 * be advanced. 1123 */ 1124 inthand_t bluetrap6; 1125 #ifdef __GNUCLIKE_ASM 1126 __asm 1127 (" \n\ 1128 .text \n\ 1129 .p2align 2,0x90 \n\ 1130 .type " __XSTRING(CNAME(bluetrap6)) ",@function \n\ 1131 " __XSTRING(CNAME(bluetrap6)) ": \n\ 1132 ss \n\ 1133 movl $0xa8c1d," __XSTRING(CNAME(trap_by_rdmsr)) " \n\ 1134 addl $2, (%esp) /* rdmsr is a 2-byte instruction */ \n\ 1135 iret \n\ 1136 "); 1137 #endif 1138 1139 /* 1140 * Special exception 13 handler. 1141 * Accessing non-existent MSR generates general protection fault. 1142 */ 1143 inthand_t bluetrap13; 1144 #ifdef __GNUCLIKE_ASM 1145 __asm 1146 (" \n\ 1147 .text \n\ 1148 .p2align 2,0x90 \n\ 1149 .type " __XSTRING(CNAME(bluetrap13)) ",@function \n\ 1150 " __XSTRING(CNAME(bluetrap13)) ": \n\ 1151 ss \n\ 1152 movl $0xa89c4," __XSTRING(CNAME(trap_by_rdmsr)) " \n\ 1153 popl %eax /* discard error code */ \n\ 1154 addl $2, (%esp) /* rdmsr is a 2-byte instruction */ \n\ 1155 iret \n\ 1156 "); 1157 #endif 1158 1159 /* 1160 * Distinguish IBM Blue Lightning CPU from Cyrix CPUs that does not 1161 * support cpuid instruction. This function should be called after 1162 * loading interrupt descriptor table register. 1163 * 1164 * I don't like this method that handles fault, but I couldn't get 1165 * information for any other methods. Does blue giant know? 1166 */ 1167 static int 1168 identblue(void) 1169 { 1170 1171 trap_by_rdmsr = 0; 1172 1173 /* 1174 * Cyrix 486-class CPU does not support rdmsr instruction. 1175 * The rdmsr instruction generates invalid opcode fault, and exception 1176 * will be trapped by bluetrap6() on Cyrix 486-class CPU. The 1177 * bluetrap6() set the magic number to trap_by_rdmsr. 1178 */ 1179 setidt(IDT_UD, bluetrap6, SDT_SYS386TGT, SEL_KPL, 1180 GSEL(GCODE_SEL, SEL_KPL)); 1181 1182 /* 1183 * Certain BIOS disables cpuid instruction of Cyrix 6x86MX CPU. 1184 * In this case, rdmsr generates general protection fault, and 1185 * exception will be trapped by bluetrap13(). 1186 */ 1187 setidt(IDT_GP, bluetrap13, SDT_SYS386TGT, SEL_KPL, 1188 GSEL(GCODE_SEL, SEL_KPL)); 1189 1190 rdmsr(0x1002); /* Cyrix CPU generates fault. */ 1191 1192 if (trap_by_rdmsr == 0xa8c1d) 1193 return IDENTBLUE_CYRIX486; 1194 else if (trap_by_rdmsr == 0xa89c4) 1195 return IDENTBLUE_CYRIXM2; 1196 return IDENTBLUE_IBMCPU; 1197 } 1198 1199 1200 /* 1201 * identifycyrix() set lower 16 bits of cyrix_did as follows: 1202 * 1203 * F E D C B A 9 8 7 6 5 4 3 2 1 0 1204 * +-------+-------+---------------+ 1205 * | SID | RID | Device ID | 1206 * | (DIR 1) | (DIR 0) | 1207 * +-------+-------+---------------+ 1208 */ 1209 static void 1210 identifycyrix(void) 1211 { 1212 register_t saveintr; 1213 int ccr2_test = 0, dir_test = 0; 1214 u_char ccr2, ccr3; 1215 1216 saveintr = intr_disable(); 1217 1218 ccr2 = read_cyrix_reg(CCR2); 1219 write_cyrix_reg(CCR2, ccr2 ^ CCR2_LOCK_NW); 1220 read_cyrix_reg(CCR2); 1221 if (read_cyrix_reg(CCR2) != ccr2) 1222 ccr2_test = 1; 1223 write_cyrix_reg(CCR2, ccr2); 1224 1225 ccr3 = read_cyrix_reg(CCR3); 1226 write_cyrix_reg(CCR3, ccr3 ^ CCR3_MAPEN3); 1227 read_cyrix_reg(CCR3); 1228 if (read_cyrix_reg(CCR3) != ccr3) 1229 dir_test = 1; /* CPU supports DIRs. */ 1230 write_cyrix_reg(CCR3, ccr3); 1231 1232 if (dir_test) { 1233 /* Device ID registers are available. */ 1234 cyrix_did = read_cyrix_reg(DIR1) << 8; 1235 cyrix_did += read_cyrix_reg(DIR0); 1236 } else if (ccr2_test) 1237 cyrix_did = 0x0010; /* 486S A-step */ 1238 else 1239 cyrix_did = 0x00ff; /* Old 486SLC/DLC and TI486SXLC/SXL */ 1240 1241 intr_restore(saveintr); 1242 } 1243 #endif 1244 1245 /* Update TSC freq with the value indicated by the caller. */ 1246 static void 1247 tsc_freq_changed(void *arg __unused, const struct cf_level *level, int status) 1248 { 1249 1250 /* If there was an error during the transition, don't do anything. */ 1251 if (status != 0) 1252 return; 1253 1254 /* Total setting for this level gives the new frequency in MHz. */ 1255 hw_clockrate = level->total_set.freq; 1256 } 1257 1258 static void 1259 hook_tsc_freq(void *arg __unused) 1260 { 1261 1262 if (tsc_is_invariant) 1263 return; 1264 1265 tsc_post_tag = EVENTHANDLER_REGISTER(cpufreq_post_change, 1266 tsc_freq_changed, NULL, EVENTHANDLER_PRI_ANY); 1267 } 1268 1269 SYSINIT(hook_tsc_freq, SI_SUB_CONFIGURE, SI_ORDER_ANY, hook_tsc_freq, NULL); 1270 1271 static const char *const vm_bnames[] = { 1272 "QEMU", /* QEMU */ 1273 "Plex86", /* Plex86 */ 1274 "Bochs", /* Bochs */ 1275 "Xen", /* Xen */ 1276 "BHYVE", /* bhyve */ 1277 "Seabios", /* KVM */ 1278 NULL 1279 }; 1280 1281 static const char *const vm_pnames[] = { 1282 "VMware Virtual Platform", /* VMWare VM */ 1283 "Virtual Machine", /* Microsoft VirtualPC */ 1284 "VirtualBox", /* Sun xVM VirtualBox */ 1285 "Parallels Virtual Platform", /* Parallels VM */ 1286 "KVM", /* KVM */ 1287 NULL 1288 }; 1289 1290 void 1291 identify_hypervisor(void) 1292 { 1293 u_int regs[4]; 1294 char *p; 1295 int i; 1296 1297 /* 1298 * [RFC] CPUID usage for interaction between Hypervisors and Linux. 1299 * http://lkml.org/lkml/2008/10/1/246 1300 * 1301 * KB1009458: Mechanisms to determine if software is running in 1302 * a VMware virtual machine 1303 * http://kb.vmware.com/kb/1009458 1304 */ 1305 if (cpu_feature2 & CPUID2_HV) { 1306 vm_guest = VM_GUEST_VM; 1307 do_cpuid(0x40000000, regs); 1308 1309 /* 1310 * KVM from Linux kernels prior to commit 1311 * 57c22e5f35aa4b9b2fe11f73f3e62bbf9ef36190 set %eax 1312 * to 0 rather than a valid hv_high value. Check for 1313 * the KVM signature bytes and fixup %eax to the 1314 * highest supported leaf in that case. 1315 */ 1316 if (regs[0] == 0 && regs[1] == 0x4b4d564b && 1317 regs[2] == 0x564b4d56 && regs[3] == 0x0000004d) 1318 regs[0] = 0x40000001; 1319 1320 if (regs[0] >= 0x40000000) { 1321 hv_high = regs[0]; 1322 ((u_int *)&hv_vendor)[0] = regs[1]; 1323 ((u_int *)&hv_vendor)[1] = regs[2]; 1324 ((u_int *)&hv_vendor)[2] = regs[3]; 1325 hv_vendor[12] = '\0'; 1326 if (strcmp(hv_vendor, "VMwareVMware") == 0) 1327 vm_guest = VM_GUEST_VMWARE; 1328 else if (strcmp(hv_vendor, "Microsoft Hv") == 0) 1329 vm_guest = VM_GUEST_HV; 1330 else if (strcmp(hv_vendor, "KVMKVMKVM") == 0) 1331 vm_guest = VM_GUEST_KVM; 1332 else if (strcmp(hv_vendor, "bhyve bhyve") == 0) 1333 vm_guest = VM_GUEST_BHYVE; 1334 } 1335 return; 1336 } 1337 1338 /* 1339 * Examine SMBIOS strings for older hypervisors. 1340 */ 1341 p = kern_getenv("smbios.system.serial"); 1342 if (p != NULL) { 1343 if (strncmp(p, "VMware-", 7) == 0 || strncmp(p, "VMW", 3) == 0) { 1344 vmware_hvcall(VMW_HVCMD_GETVERSION, regs); 1345 if (regs[1] == VMW_HVMAGIC) { 1346 vm_guest = VM_GUEST_VMWARE; 1347 freeenv(p); 1348 return; 1349 } 1350 } 1351 freeenv(p); 1352 } 1353 1354 /* 1355 * XXX: Some of these entries may not be needed since they were 1356 * added to FreeBSD before the checks above. 1357 */ 1358 p = kern_getenv("smbios.bios.vendor"); 1359 if (p != NULL) { 1360 for (i = 0; vm_bnames[i] != NULL; i++) 1361 if (strcmp(p, vm_bnames[i]) == 0) { 1362 vm_guest = VM_GUEST_VM; 1363 freeenv(p); 1364 return; 1365 } 1366 freeenv(p); 1367 } 1368 p = kern_getenv("smbios.system.product"); 1369 if (p != NULL) { 1370 for (i = 0; vm_pnames[i] != NULL; i++) 1371 if (strcmp(p, vm_pnames[i]) == 0) { 1372 vm_guest = VM_GUEST_VM; 1373 freeenv(p); 1374 return; 1375 } 1376 freeenv(p); 1377 } 1378 } 1379 1380 bool 1381 fix_cpuid(void) 1382 { 1383 uint64_t msr; 1384 1385 /* 1386 * Clear "Limit CPUID Maxval" bit and return true if the caller should 1387 * get the largest standard CPUID function number again if it is set 1388 * from BIOS. It is necessary for probing correct CPU topology later 1389 * and for the correct operation of the AVX-aware userspace. 1390 */ 1391 if (cpu_vendor_id == CPU_VENDOR_INTEL && 1392 ((CPUID_TO_FAMILY(cpu_id) == 0xf && 1393 CPUID_TO_MODEL(cpu_id) >= 0x3) || 1394 (CPUID_TO_FAMILY(cpu_id) == 0x6 && 1395 CPUID_TO_MODEL(cpu_id) >= 0xe))) { 1396 msr = rdmsr(MSR_IA32_MISC_ENABLE); 1397 if ((msr & IA32_MISC_EN_LIMCPUID) != 0) { 1398 msr &= ~IA32_MISC_EN_LIMCPUID; 1399 wrmsr(MSR_IA32_MISC_ENABLE, msr); 1400 return (true); 1401 } 1402 } 1403 1404 /* 1405 * Re-enable AMD Topology Extension that could be disabled by BIOS 1406 * on some notebook processors. Without the extension it's really 1407 * hard to determine the correct CPU cache topology. 1408 * See BIOS and Kernel Developer’s Guide (BKDG) for AMD Family 15h 1409 * Models 60h-6Fh Processors, Publication # 50742. 1410 */ 1411 if (vm_guest == VM_GUEST_NO && cpu_vendor_id == CPU_VENDOR_AMD && 1412 CPUID_TO_FAMILY(cpu_id) == 0x15) { 1413 msr = rdmsr(MSR_EXTFEATURES); 1414 if ((msr & ((uint64_t)1 << 54)) == 0) { 1415 msr |= (uint64_t)1 << 54; 1416 wrmsr(MSR_EXTFEATURES, msr); 1417 return (true); 1418 } 1419 } 1420 return (false); 1421 } 1422 1423 void 1424 identify_cpu1(void) 1425 { 1426 u_int regs[4]; 1427 1428 do_cpuid(0, regs); 1429 cpu_high = regs[0]; 1430 ((u_int *)&cpu_vendor)[0] = regs[1]; 1431 ((u_int *)&cpu_vendor)[1] = regs[3]; 1432 ((u_int *)&cpu_vendor)[2] = regs[2]; 1433 cpu_vendor[12] = '\0'; 1434 1435 do_cpuid(1, regs); 1436 cpu_id = regs[0]; 1437 cpu_procinfo = regs[1]; 1438 cpu_feature = regs[3]; 1439 cpu_feature2 = regs[2]; 1440 } 1441 1442 void 1443 identify_cpu2(void) 1444 { 1445 u_int regs[4], cpu_stdext_disable; 1446 1447 if (cpu_high >= 7) { 1448 cpuid_count(7, 0, regs); 1449 cpu_stdext_feature = regs[1]; 1450 1451 /* 1452 * Some hypervisors failed to filter out unsupported 1453 * extended features. Allow to disable the 1454 * extensions, activation of which requires setting a 1455 * bit in CR4, and which VM monitors do not support. 1456 */ 1457 cpu_stdext_disable = 0; 1458 TUNABLE_INT_FETCH("hw.cpu_stdext_disable", &cpu_stdext_disable); 1459 cpu_stdext_feature &= ~cpu_stdext_disable; 1460 1461 cpu_stdext_feature2 = regs[2]; 1462 cpu_stdext_feature3 = regs[3]; 1463 1464 if ((cpu_stdext_feature3 & CPUID_STDEXT3_ARCH_CAP) != 0) 1465 cpu_ia32_arch_caps = rdmsr(MSR_IA32_ARCH_CAP); 1466 } 1467 } 1468 1469 /* 1470 * Final stage of CPU identification. 1471 */ 1472 void 1473 finishidentcpu(void) 1474 { 1475 u_int regs[4]; 1476 #ifdef __i386__ 1477 u_char ccr3; 1478 #endif 1479 1480 cpu_vendor_id = find_cpu_vendor_id(); 1481 1482 if (fix_cpuid()) { 1483 do_cpuid(0, regs); 1484 cpu_high = regs[0]; 1485 } 1486 1487 if (cpu_high >= 5 && (cpu_feature2 & CPUID2_MON) != 0) { 1488 do_cpuid(5, regs); 1489 cpu_mon_mwait_flags = regs[2]; 1490 cpu_mon_min_size = regs[0] & CPUID5_MON_MIN_SIZE; 1491 cpu_mon_max_size = regs[1] & CPUID5_MON_MAX_SIZE; 1492 } 1493 1494 identify_cpu2(); 1495 1496 #ifdef __i386__ 1497 if (cpu_high > 0 && 1498 (cpu_vendor_id == CPU_VENDOR_INTEL || 1499 cpu_vendor_id == CPU_VENDOR_AMD || 1500 cpu_vendor_id == CPU_VENDOR_TRANSMETA || 1501 cpu_vendor_id == CPU_VENDOR_CENTAUR || 1502 cpu_vendor_id == CPU_VENDOR_NSC)) { 1503 do_cpuid(0x80000000, regs); 1504 if (regs[0] >= 0x80000000) 1505 cpu_exthigh = regs[0]; 1506 } 1507 #else 1508 if (cpu_vendor_id == CPU_VENDOR_INTEL || 1509 cpu_vendor_id == CPU_VENDOR_AMD || 1510 cpu_vendor_id == CPU_VENDOR_CENTAUR) { 1511 do_cpuid(0x80000000, regs); 1512 cpu_exthigh = regs[0]; 1513 } 1514 #endif 1515 if (cpu_exthigh >= 0x80000001) { 1516 do_cpuid(0x80000001, regs); 1517 amd_feature = regs[3] & ~(cpu_feature & 0x0183f3ff); 1518 amd_feature2 = regs[2]; 1519 } 1520 if (cpu_exthigh >= 0x80000007) { 1521 do_cpuid(0x80000007, regs); 1522 amd_rascap = regs[1]; 1523 amd_pminfo = regs[3]; 1524 } 1525 if (cpu_exthigh >= 0x80000008) { 1526 do_cpuid(0x80000008, regs); 1527 cpu_maxphyaddr = regs[0] & 0xff; 1528 amd_extended_feature_extensions = regs[1]; 1529 cpu_procinfo2 = regs[2]; 1530 } else { 1531 cpu_maxphyaddr = (cpu_feature & CPUID_PAE) != 0 ? 36 : 32; 1532 } 1533 1534 #ifdef __i386__ 1535 if (cpu_vendor_id == CPU_VENDOR_CYRIX) { 1536 if (cpu == CPU_486) { 1537 /* 1538 * These conditions are equivalent to: 1539 * - CPU does not support cpuid instruction. 1540 * - Cyrix/IBM CPU is detected. 1541 */ 1542 if (identblue() == IDENTBLUE_IBMCPU) { 1543 strcpy(cpu_vendor, "IBM"); 1544 cpu_vendor_id = CPU_VENDOR_IBM; 1545 cpu = CPU_BLUE; 1546 return; 1547 } 1548 } 1549 switch (cpu_id & 0xf00) { 1550 case 0x600: 1551 /* 1552 * Cyrix's datasheet does not describe DIRs. 1553 * Therefor, I assume it does not have them 1554 * and use the result of the cpuid instruction. 1555 * XXX they seem to have it for now at least. -Peter 1556 */ 1557 identifycyrix(); 1558 cpu = CPU_M2; 1559 break; 1560 default: 1561 identifycyrix(); 1562 /* 1563 * This routine contains a trick. 1564 * Don't check (cpu_id & 0x00f0) == 0x50 to detect M2, now. 1565 */ 1566 switch (cyrix_did & 0x00f0) { 1567 case 0x00: 1568 case 0xf0: 1569 cpu = CPU_486DLC; 1570 break; 1571 case 0x10: 1572 cpu = CPU_CY486DX; 1573 break; 1574 case 0x20: 1575 if ((cyrix_did & 0x000f) < 8) 1576 cpu = CPU_M1; 1577 else 1578 cpu = CPU_M1SC; 1579 break; 1580 case 0x30: 1581 cpu = CPU_M1; 1582 break; 1583 case 0x40: 1584 /* MediaGX CPU */ 1585 cpu = CPU_M1SC; 1586 break; 1587 default: 1588 /* M2 and later CPUs are treated as M2. */ 1589 cpu = CPU_M2; 1590 1591 /* 1592 * enable cpuid instruction. 1593 */ 1594 ccr3 = read_cyrix_reg(CCR3); 1595 write_cyrix_reg(CCR3, CCR3_MAPEN0); 1596 write_cyrix_reg(CCR4, read_cyrix_reg(CCR4) | CCR4_CPUID); 1597 write_cyrix_reg(CCR3, ccr3); 1598 1599 do_cpuid(0, regs); 1600 cpu_high = regs[0]; /* eax */ 1601 do_cpuid(1, regs); 1602 cpu_id = regs[0]; /* eax */ 1603 cpu_feature = regs[3]; /* edx */ 1604 break; 1605 } 1606 } 1607 } else if (cpu == CPU_486 && *cpu_vendor == '\0') { 1608 /* 1609 * There are BlueLightning CPUs that do not change 1610 * undefined flags by dividing 5 by 2. In this case, 1611 * the CPU identification routine in locore.s leaves 1612 * cpu_vendor null string and puts CPU_486 into the 1613 * cpu. 1614 */ 1615 if (identblue() == IDENTBLUE_IBMCPU) { 1616 strcpy(cpu_vendor, "IBM"); 1617 cpu_vendor_id = CPU_VENDOR_IBM; 1618 cpu = CPU_BLUE; 1619 return; 1620 } 1621 } 1622 #endif 1623 } 1624 1625 int 1626 pti_get_default(void) 1627 { 1628 1629 if (strcmp(cpu_vendor, AMD_VENDOR_ID) == 0) 1630 return (0); 1631 if ((cpu_ia32_arch_caps & IA32_ARCH_CAP_RDCL_NO) != 0) 1632 return (0); 1633 return (1); 1634 } 1635 1636 static u_int 1637 find_cpu_vendor_id(void) 1638 { 1639 int i; 1640 1641 for (i = 0; i < nitems(cpu_vendors); i++) 1642 if (strcmp(cpu_vendor, cpu_vendors[i].vendor) == 0) 1643 return (cpu_vendors[i].vendor_id); 1644 return (0); 1645 } 1646 1647 static void 1648 print_AMD_assoc(int i) 1649 { 1650 if (i == 255) 1651 printf(", fully associative\n"); 1652 else 1653 printf(", %d-way associative\n", i); 1654 } 1655 1656 static void 1657 print_AMD_l2_assoc(int i) 1658 { 1659 switch (i & 0x0f) { 1660 case 0: printf(", disabled/not present\n"); break; 1661 case 1: printf(", direct mapped\n"); break; 1662 case 2: printf(", 2-way associative\n"); break; 1663 case 4: printf(", 4-way associative\n"); break; 1664 case 6: printf(", 8-way associative\n"); break; 1665 case 8: printf(", 16-way associative\n"); break; 1666 case 15: printf(", fully associative\n"); break; 1667 default: printf(", reserved configuration\n"); break; 1668 } 1669 } 1670 1671 static void 1672 print_AMD_info(void) 1673 { 1674 #ifdef __i386__ 1675 uint64_t amd_whcr; 1676 #endif 1677 u_int regs[4]; 1678 1679 if (cpu_exthigh >= 0x80000005) { 1680 do_cpuid(0x80000005, regs); 1681 printf("L1 2MB data TLB: %d entries", (regs[0] >> 16) & 0xff); 1682 print_AMD_assoc(regs[0] >> 24); 1683 1684 printf("L1 2MB instruction TLB: %d entries", regs[0] & 0xff); 1685 print_AMD_assoc((regs[0] >> 8) & 0xff); 1686 1687 printf("L1 4KB data TLB: %d entries", (regs[1] >> 16) & 0xff); 1688 print_AMD_assoc(regs[1] >> 24); 1689 1690 printf("L1 4KB instruction TLB: %d entries", regs[1] & 0xff); 1691 print_AMD_assoc((regs[1] >> 8) & 0xff); 1692 1693 printf("L1 data cache: %d kbytes", regs[2] >> 24); 1694 printf(", %d bytes/line", regs[2] & 0xff); 1695 printf(", %d lines/tag", (regs[2] >> 8) & 0xff); 1696 print_AMD_assoc((regs[2] >> 16) & 0xff); 1697 1698 printf("L1 instruction cache: %d kbytes", regs[3] >> 24); 1699 printf(", %d bytes/line", regs[3] & 0xff); 1700 printf(", %d lines/tag", (regs[3] >> 8) & 0xff); 1701 print_AMD_assoc((regs[3] >> 16) & 0xff); 1702 } 1703 1704 if (cpu_exthigh >= 0x80000006) { 1705 do_cpuid(0x80000006, regs); 1706 if ((regs[0] >> 16) != 0) { 1707 printf("L2 2MB data TLB: %d entries", 1708 (regs[0] >> 16) & 0xfff); 1709 print_AMD_l2_assoc(regs[0] >> 28); 1710 printf("L2 2MB instruction TLB: %d entries", 1711 regs[0] & 0xfff); 1712 print_AMD_l2_assoc((regs[0] >> 28) & 0xf); 1713 } else { 1714 printf("L2 2MB unified TLB: %d entries", 1715 regs[0] & 0xfff); 1716 print_AMD_l2_assoc((regs[0] >> 28) & 0xf); 1717 } 1718 if ((regs[1] >> 16) != 0) { 1719 printf("L2 4KB data TLB: %d entries", 1720 (regs[1] >> 16) & 0xfff); 1721 print_AMD_l2_assoc(regs[1] >> 28); 1722 1723 printf("L2 4KB instruction TLB: %d entries", 1724 (regs[1] >> 16) & 0xfff); 1725 print_AMD_l2_assoc((regs[1] >> 28) & 0xf); 1726 } else { 1727 printf("L2 4KB unified TLB: %d entries", 1728 (regs[1] >> 16) & 0xfff); 1729 print_AMD_l2_assoc((regs[1] >> 28) & 0xf); 1730 } 1731 printf("L2 unified cache: %d kbytes", regs[2] >> 16); 1732 printf(", %d bytes/line", regs[2] & 0xff); 1733 printf(", %d lines/tag", (regs[2] >> 8) & 0x0f); 1734 print_AMD_l2_assoc((regs[2] >> 12) & 0x0f); 1735 } 1736 1737 #ifdef __i386__ 1738 if (((cpu_id & 0xf00) == 0x500) 1739 && (((cpu_id & 0x0f0) > 0x80) 1740 || (((cpu_id & 0x0f0) == 0x80) 1741 && (cpu_id & 0x00f) > 0x07))) { 1742 /* K6-2(new core [Stepping 8-F]), K6-III or later */ 1743 amd_whcr = rdmsr(0xc0000082); 1744 if (!(amd_whcr & (0x3ff << 22))) { 1745 printf("Write Allocate Disable\n"); 1746 } else { 1747 printf("Write Allocate Enable Limit: %dM bytes\n", 1748 (u_int32_t)((amd_whcr & (0x3ff << 22)) >> 22) * 4); 1749 printf("Write Allocate 15-16M bytes: %s\n", 1750 (amd_whcr & (1 << 16)) ? "Enable" : "Disable"); 1751 } 1752 } else if (((cpu_id & 0xf00) == 0x500) 1753 && ((cpu_id & 0x0f0) > 0x50)) { 1754 /* K6, K6-2(old core) */ 1755 amd_whcr = rdmsr(0xc0000082); 1756 if (!(amd_whcr & (0x7f << 1))) { 1757 printf("Write Allocate Disable\n"); 1758 } else { 1759 printf("Write Allocate Enable Limit: %dM bytes\n", 1760 (u_int32_t)((amd_whcr & (0x7f << 1)) >> 1) * 4); 1761 printf("Write Allocate 15-16M bytes: %s\n", 1762 (amd_whcr & 0x0001) ? "Enable" : "Disable"); 1763 printf("Hardware Write Allocate Control: %s\n", 1764 (amd_whcr & 0x0100) ? "Enable" : "Disable"); 1765 } 1766 } 1767 #endif 1768 /* 1769 * Opteron Rev E shows a bug as in very rare occasions a read memory 1770 * barrier is not performed as expected if it is followed by a 1771 * non-atomic read-modify-write instruction. 1772 * As long as that bug pops up very rarely (intensive machine usage 1773 * on other operating systems generally generates one unexplainable 1774 * crash any 2 months) and as long as a model specific fix would be 1775 * impractical at this stage, print out a warning string if the broken 1776 * model and family are identified. 1777 */ 1778 if (CPUID_TO_FAMILY(cpu_id) == 0xf && CPUID_TO_MODEL(cpu_id) >= 0x20 && 1779 CPUID_TO_MODEL(cpu_id) <= 0x3f) 1780 printf("WARNING: This architecture revision has known SMP " 1781 "hardware bugs which may cause random instability\n"); 1782 } 1783 1784 static void 1785 print_INTEL_info(void) 1786 { 1787 u_int regs[4]; 1788 u_int rounds, regnum; 1789 u_int nwaycode, nway; 1790 1791 if (cpu_high >= 2) { 1792 rounds = 0; 1793 do { 1794 do_cpuid(0x2, regs); 1795 if (rounds == 0 && (rounds = (regs[0] & 0xff)) == 0) 1796 break; /* we have a buggy CPU */ 1797 1798 for (regnum = 0; regnum <= 3; ++regnum) { 1799 if (regs[regnum] & (1<<31)) 1800 continue; 1801 if (regnum != 0) 1802 print_INTEL_TLB(regs[regnum] & 0xff); 1803 print_INTEL_TLB((regs[regnum] >> 8) & 0xff); 1804 print_INTEL_TLB((regs[regnum] >> 16) & 0xff); 1805 print_INTEL_TLB((regs[regnum] >> 24) & 0xff); 1806 } 1807 } while (--rounds > 0); 1808 } 1809 1810 if (cpu_exthigh >= 0x80000006) { 1811 do_cpuid(0x80000006, regs); 1812 nwaycode = (regs[2] >> 12) & 0x0f; 1813 if (nwaycode >= 0x02 && nwaycode <= 0x08) 1814 nway = 1 << (nwaycode / 2); 1815 else 1816 nway = 0; 1817 printf("L2 cache: %u kbytes, %u-way associative, %u bytes/line\n", 1818 (regs[2] >> 16) & 0xffff, nway, regs[2] & 0xff); 1819 } 1820 } 1821 1822 static void 1823 print_INTEL_TLB(u_int data) 1824 { 1825 switch (data) { 1826 case 0x0: 1827 case 0x40: 1828 default: 1829 break; 1830 case 0x1: 1831 printf("Instruction TLB: 4 KB pages, 4-way set associative, 32 entries\n"); 1832 break; 1833 case 0x2: 1834 printf("Instruction TLB: 4 MB pages, fully associative, 2 entries\n"); 1835 break; 1836 case 0x3: 1837 printf("Data TLB: 4 KB pages, 4-way set associative, 64 entries\n"); 1838 break; 1839 case 0x4: 1840 printf("Data TLB: 4 MB Pages, 4-way set associative, 8 entries\n"); 1841 break; 1842 case 0x6: 1843 printf("1st-level instruction cache: 8 KB, 4-way set associative, 32 byte line size\n"); 1844 break; 1845 case 0x8: 1846 printf("1st-level instruction cache: 16 KB, 4-way set associative, 32 byte line size\n"); 1847 break; 1848 case 0x9: 1849 printf("1st-level instruction cache: 32 KB, 4-way set associative, 64 byte line size\n"); 1850 break; 1851 case 0xa: 1852 printf("1st-level data cache: 8 KB, 2-way set associative, 32 byte line size\n"); 1853 break; 1854 case 0xb: 1855 printf("Instruction TLB: 4 MByte pages, 4-way set associative, 4 entries\n"); 1856 break; 1857 case 0xc: 1858 printf("1st-level data cache: 16 KB, 4-way set associative, 32 byte line size\n"); 1859 break; 1860 case 0xd: 1861 printf("1st-level data cache: 16 KBytes, 4-way set associative, 64 byte line size"); 1862 break; 1863 case 0xe: 1864 printf("1st-level data cache: 24 KBytes, 6-way set associative, 64 byte line size\n"); 1865 break; 1866 case 0x1d: 1867 printf("2nd-level cache: 128 KBytes, 2-way set associative, 64 byte line size\n"); 1868 break; 1869 case 0x21: 1870 printf("2nd-level cache: 256 KBytes, 8-way set associative, 64 byte line size\n"); 1871 break; 1872 case 0x22: 1873 printf("3rd-level cache: 512 KB, 4-way set associative, sectored cache, 64 byte line size\n"); 1874 break; 1875 case 0x23: 1876 printf("3rd-level cache: 1 MB, 8-way set associative, sectored cache, 64 byte line size\n"); 1877 break; 1878 case 0x24: 1879 printf("2nd-level cache: 1 MBytes, 16-way set associative, 64 byte line size\n"); 1880 break; 1881 case 0x25: 1882 printf("3rd-level cache: 2 MB, 8-way set associative, sectored cache, 64 byte line size\n"); 1883 break; 1884 case 0x29: 1885 printf("3rd-level cache: 4 MB, 8-way set associative, sectored cache, 64 byte line size\n"); 1886 break; 1887 case 0x2c: 1888 printf("1st-level data cache: 32 KB, 8-way set associative, 64 byte line size\n"); 1889 break; 1890 case 0x30: 1891 printf("1st-level instruction cache: 32 KB, 8-way set associative, 64 byte line size\n"); 1892 break; 1893 case 0x39: /* De-listed in SDM rev. 54 */ 1894 printf("2nd-level cache: 128 KB, 4-way set associative, sectored cache, 64 byte line size\n"); 1895 break; 1896 case 0x3b: /* De-listed in SDM rev. 54 */ 1897 printf("2nd-level cache: 128 KB, 2-way set associative, sectored cache, 64 byte line size\n"); 1898 break; 1899 case 0x3c: /* De-listed in SDM rev. 54 */ 1900 printf("2nd-level cache: 256 KB, 4-way set associative, sectored cache, 64 byte line size\n"); 1901 break; 1902 case 0x41: 1903 printf("2nd-level cache: 128 KB, 4-way set associative, 32 byte line size\n"); 1904 break; 1905 case 0x42: 1906 printf("2nd-level cache: 256 KB, 4-way set associative, 32 byte line size\n"); 1907 break; 1908 case 0x43: 1909 printf("2nd-level cache: 512 KB, 4-way set associative, 32 byte line size\n"); 1910 break; 1911 case 0x44: 1912 printf("2nd-level cache: 1 MB, 4-way set associative, 32 byte line size\n"); 1913 break; 1914 case 0x45: 1915 printf("2nd-level cache: 2 MB, 4-way set associative, 32 byte line size\n"); 1916 break; 1917 case 0x46: 1918 printf("3rd-level cache: 4 MB, 4-way set associative, 64 byte line size\n"); 1919 break; 1920 case 0x47: 1921 printf("3rd-level cache: 8 MB, 8-way set associative, 64 byte line size\n"); 1922 break; 1923 case 0x48: 1924 printf("2nd-level cache: 3MByte, 12-way set associative, 64 byte line size\n"); 1925 break; 1926 case 0x49: 1927 if (CPUID_TO_FAMILY(cpu_id) == 0xf && 1928 CPUID_TO_MODEL(cpu_id) == 0x6) 1929 printf("3rd-level cache: 4MB, 16-way set associative, 64-byte line size\n"); 1930 else 1931 printf("2nd-level cache: 4 MByte, 16-way set associative, 64 byte line size"); 1932 break; 1933 case 0x4a: 1934 printf("3rd-level cache: 6MByte, 12-way set associative, 64 byte line size\n"); 1935 break; 1936 case 0x4b: 1937 printf("3rd-level cache: 8MByte, 16-way set associative, 64 byte line size\n"); 1938 break; 1939 case 0x4c: 1940 printf("3rd-level cache: 12MByte, 12-way set associative, 64 byte line size\n"); 1941 break; 1942 case 0x4d: 1943 printf("3rd-level cache: 16MByte, 16-way set associative, 64 byte line size\n"); 1944 break; 1945 case 0x4e: 1946 printf("2nd-level cache: 6MByte, 24-way set associative, 64 byte line size\n"); 1947 break; 1948 case 0x4f: 1949 printf("Instruction TLB: 4 KByte pages, 32 entries\n"); 1950 break; 1951 case 0x50: 1952 printf("Instruction TLB: 4 KB, 2 MB or 4 MB pages, fully associative, 64 entries\n"); 1953 break; 1954 case 0x51: 1955 printf("Instruction TLB: 4 KB, 2 MB or 4 MB pages, fully associative, 128 entries\n"); 1956 break; 1957 case 0x52: 1958 printf("Instruction TLB: 4 KB, 2 MB or 4 MB pages, fully associative, 256 entries\n"); 1959 break; 1960 case 0x55: 1961 printf("Instruction TLB: 2-MByte or 4-MByte pages, fully associative, 7 entries\n"); 1962 break; 1963 case 0x56: 1964 printf("Data TLB0: 4 MByte pages, 4-way set associative, 16 entries\n"); 1965 break; 1966 case 0x57: 1967 printf("Data TLB0: 4 KByte pages, 4-way associative, 16 entries\n"); 1968 break; 1969 case 0x59: 1970 printf("Data TLB0: 4 KByte pages, fully associative, 16 entries\n"); 1971 break; 1972 case 0x5a: 1973 printf("Data TLB0: 2-MByte or 4 MByte pages, 4-way set associative, 32 entries\n"); 1974 break; 1975 case 0x5b: 1976 printf("Data TLB: 4 KB or 4 MB pages, fully associative, 64 entries\n"); 1977 break; 1978 case 0x5c: 1979 printf("Data TLB: 4 KB or 4 MB pages, fully associative, 128 entries\n"); 1980 break; 1981 case 0x5d: 1982 printf("Data TLB: 4 KB or 4 MB pages, fully associative, 256 entries\n"); 1983 break; 1984 case 0x60: 1985 printf("1st-level data cache: 16 KB, 8-way set associative, sectored cache, 64 byte line size\n"); 1986 break; 1987 case 0x61: 1988 printf("Instruction TLB: 4 KByte pages, fully associative, 48 entries\n"); 1989 break; 1990 case 0x63: 1991 printf("Data TLB: 2 MByte or 4 MByte pages, 4-way set associative, 32 entries and a separate array with 1 GByte pages, 4-way set associative, 4 entries\n"); 1992 break; 1993 case 0x64: 1994 printf("Data TLB: 4 KBytes pages, 4-way set associative, 512 entries\n"); 1995 break; 1996 case 0x66: 1997 printf("1st-level data cache: 8 KB, 4-way set associative, sectored cache, 64 byte line size\n"); 1998 break; 1999 case 0x67: 2000 printf("1st-level data cache: 16 KB, 4-way set associative, sectored cache, 64 byte line size\n"); 2001 break; 2002 case 0x68: 2003 printf("1st-level data cache: 32 KB, 4 way set associative, sectored cache, 64 byte line size\n"); 2004 break; 2005 case 0x6a: 2006 printf("uTLB: 4KByte pages, 8-way set associative, 64 entries\n"); 2007 break; 2008 case 0x6b: 2009 printf("DTLB: 4KByte pages, 8-way set associative, 256 entries\n"); 2010 break; 2011 case 0x6c: 2012 printf("DTLB: 2M/4M pages, 8-way set associative, 128 entries\n"); 2013 break; 2014 case 0x6d: 2015 printf("DTLB: 1 GByte pages, fully associative, 16 entries\n"); 2016 break; 2017 case 0x70: 2018 printf("Trace cache: 12K-uops, 8-way set associative\n"); 2019 break; 2020 case 0x71: 2021 printf("Trace cache: 16K-uops, 8-way set associative\n"); 2022 break; 2023 case 0x72: 2024 printf("Trace cache: 32K-uops, 8-way set associative\n"); 2025 break; 2026 case 0x76: 2027 printf("Instruction TLB: 2M/4M pages, fully associative, 8 entries\n"); 2028 break; 2029 case 0x78: 2030 printf("2nd-level cache: 1 MB, 4-way set associative, 64-byte line size\n"); 2031 break; 2032 case 0x79: 2033 printf("2nd-level cache: 128 KB, 8-way set associative, sectored cache, 64 byte line size\n"); 2034 break; 2035 case 0x7a: 2036 printf("2nd-level cache: 256 KB, 8-way set associative, sectored cache, 64 byte line size\n"); 2037 break; 2038 case 0x7b: 2039 printf("2nd-level cache: 512 KB, 8-way set associative, sectored cache, 64 byte line size\n"); 2040 break; 2041 case 0x7c: 2042 printf("2nd-level cache: 1 MB, 8-way set associative, sectored cache, 64 byte line size\n"); 2043 break; 2044 case 0x7d: 2045 printf("2nd-level cache: 2-MB, 8-way set associative, 64-byte line size\n"); 2046 break; 2047 case 0x7f: 2048 printf("2nd-level cache: 512-KB, 2-way set associative, 64-byte line size\n"); 2049 break; 2050 case 0x80: 2051 printf("2nd-level cache: 512 KByte, 8-way set associative, 64-byte line size\n"); 2052 break; 2053 case 0x82: 2054 printf("2nd-level cache: 256 KB, 8-way set associative, 32 byte line size\n"); 2055 break; 2056 case 0x83: 2057 printf("2nd-level cache: 512 KB, 8-way set associative, 32 byte line size\n"); 2058 break; 2059 case 0x84: 2060 printf("2nd-level cache: 1 MB, 8-way set associative, 32 byte line size\n"); 2061 break; 2062 case 0x85: 2063 printf("2nd-level cache: 2 MB, 8-way set associative, 32 byte line size\n"); 2064 break; 2065 case 0x86: 2066 printf("2nd-level cache: 512 KB, 4-way set associative, 64 byte line size\n"); 2067 break; 2068 case 0x87: 2069 printf("2nd-level cache: 1 MB, 8-way set associative, 64 byte line size\n"); 2070 break; 2071 case 0xa0: 2072 printf("DTLB: 4k pages, fully associative, 32 entries\n"); 2073 break; 2074 case 0xb0: 2075 printf("Instruction TLB: 4 KB Pages, 4-way set associative, 128 entries\n"); 2076 break; 2077 case 0xb1: 2078 printf("Instruction TLB: 2M pages, 4-way, 8 entries or 4M pages, 4-way, 4 entries\n"); 2079 break; 2080 case 0xb2: 2081 printf("Instruction TLB: 4KByte pages, 4-way set associative, 64 entries\n"); 2082 break; 2083 case 0xb3: 2084 printf("Data TLB: 4 KB Pages, 4-way set associative, 128 entries\n"); 2085 break; 2086 case 0xb4: 2087 printf("Data TLB1: 4 KByte pages, 4-way associative, 256 entries\n"); 2088 break; 2089 case 0xb5: 2090 printf("Instruction TLB: 4KByte pages, 8-way set associative, 64 entries\n"); 2091 break; 2092 case 0xb6: 2093 printf("Instruction TLB: 4KByte pages, 8-way set associative, 128 entries\n"); 2094 break; 2095 case 0xba: 2096 printf("Data TLB1: 4 KByte pages, 4-way associative, 64 entries\n"); 2097 break; 2098 case 0xc0: 2099 printf("Data TLB: 4 KByte and 4 MByte pages, 4-way associative, 8 entries\n"); 2100 break; 2101 case 0xc1: 2102 printf("Shared 2nd-Level TLB: 4 KByte/2MByte pages, 8-way associative, 1024 entries\n"); 2103 break; 2104 case 0xc2: 2105 printf("DTLB: 4 KByte/2 MByte pages, 4-way associative, 16 entries\n"); 2106 break; 2107 case 0xc3: 2108 printf("Shared 2nd-Level TLB: 4 KByte /2 MByte pages, 6-way associative, 1536 entries. Also 1GBbyte pages, 4-way, 16 entries\n"); 2109 break; 2110 case 0xc4: 2111 printf("DTLB: 2M/4M Byte pages, 4-way associative, 32 entries\n"); 2112 break; 2113 case 0xca: 2114 printf("Shared 2nd-Level TLB: 4 KByte pages, 4-way associative, 512 entries\n"); 2115 break; 2116 case 0xd0: 2117 printf("3rd-level cache: 512 KByte, 4-way set associative, 64 byte line size\n"); 2118 break; 2119 case 0xd1: 2120 printf("3rd-level cache: 1 MByte, 4-way set associative, 64 byte line size\n"); 2121 break; 2122 case 0xd2: 2123 printf("3rd-level cache: 2 MByte, 4-way set associative, 64 byte line size\n"); 2124 break; 2125 case 0xd6: 2126 printf("3rd-level cache: 1 MByte, 8-way set associative, 64 byte line size\n"); 2127 break; 2128 case 0xd7: 2129 printf("3rd-level cache: 2 MByte, 8-way set associative, 64 byte line size\n"); 2130 break; 2131 case 0xd8: 2132 printf("3rd-level cache: 4 MByte, 8-way set associative, 64 byte line size\n"); 2133 break; 2134 case 0xdc: 2135 printf("3rd-level cache: 1.5 MByte, 12-way set associative, 64 byte line size\n"); 2136 break; 2137 case 0xdd: 2138 printf("3rd-level cache: 3 MByte, 12-way set associative, 64 byte line size\n"); 2139 break; 2140 case 0xde: 2141 printf("3rd-level cache: 6 MByte, 12-way set associative, 64 byte line size\n"); 2142 break; 2143 case 0xe2: 2144 printf("3rd-level cache: 2 MByte, 16-way set associative, 64 byte line size\n"); 2145 break; 2146 case 0xe3: 2147 printf("3rd-level cache: 4 MByte, 16-way set associative, 64 byte line size\n"); 2148 break; 2149 case 0xe4: 2150 printf("3rd-level cache: 8 MByte, 16-way set associative, 64 byte line size\n"); 2151 break; 2152 case 0xea: 2153 printf("3rd-level cache: 12MByte, 24-way set associative, 64 byte line size\n"); 2154 break; 2155 case 0xeb: 2156 printf("3rd-level cache: 18MByte, 24-way set associative, 64 byte line size\n"); 2157 break; 2158 case 0xec: 2159 printf("3rd-level cache: 24MByte, 24-way set associative, 64 byte line size\n"); 2160 break; 2161 case 0xf0: 2162 printf("64-Byte prefetching\n"); 2163 break; 2164 case 0xf1: 2165 printf("128-Byte prefetching\n"); 2166 break; 2167 } 2168 } 2169 2170 static void 2171 print_svm_info(void) 2172 { 2173 u_int features, regs[4]; 2174 uint64_t msr; 2175 int comma; 2176 2177 printf("\n SVM: "); 2178 do_cpuid(0x8000000A, regs); 2179 features = regs[3]; 2180 2181 msr = rdmsr(MSR_VM_CR); 2182 if ((msr & VM_CR_SVMDIS) == VM_CR_SVMDIS) 2183 printf("(disabled in BIOS) "); 2184 2185 if (!bootverbose) { 2186 comma = 0; 2187 if (features & (1 << 0)) { 2188 printf("%sNP", comma ? "," : ""); 2189 comma = 1; 2190 } 2191 if (features & (1 << 3)) { 2192 printf("%sNRIP", comma ? "," : ""); 2193 comma = 1; 2194 } 2195 if (features & (1 << 5)) { 2196 printf("%sVClean", comma ? "," : ""); 2197 comma = 1; 2198 } 2199 if (features & (1 << 6)) { 2200 printf("%sAFlush", comma ? "," : ""); 2201 comma = 1; 2202 } 2203 if (features & (1 << 7)) { 2204 printf("%sDAssist", comma ? "," : ""); 2205 comma = 1; 2206 } 2207 printf("%sNAsids=%d", comma ? "," : "", regs[1]); 2208 return; 2209 } 2210 2211 printf("Features=0x%b", features, 2212 "\020" 2213 "\001NP" /* Nested paging */ 2214 "\002LbrVirt" /* LBR virtualization */ 2215 "\003SVML" /* SVM lock */ 2216 "\004NRIPS" /* NRIP save */ 2217 "\005TscRateMsr" /* MSR based TSC rate control */ 2218 "\006VmcbClean" /* VMCB clean bits */ 2219 "\007FlushByAsid" /* Flush by ASID */ 2220 "\010DecodeAssist" /* Decode assist */ 2221 "\011<b8>" 2222 "\012<b9>" 2223 "\013PauseFilter" /* PAUSE intercept filter */ 2224 "\014EncryptedMcodePatch" 2225 "\015PauseFilterThreshold" /* PAUSE filter threshold */ 2226 "\016AVIC" /* virtual interrupt controller */ 2227 "\017<b14>" 2228 "\020V_VMSAVE_VMLOAD" 2229 "\021vGIF" 2230 "\022<b17>" 2231 "\023<b18>" 2232 "\024<b19>" 2233 "\025<b20>" 2234 "\026<b21>" 2235 "\027<b22>" 2236 "\030<b23>" 2237 "\031<b24>" 2238 "\032<b25>" 2239 "\033<b26>" 2240 "\034<b27>" 2241 "\035<b28>" 2242 "\036<b29>" 2243 "\037<b30>" 2244 "\040<b31>" 2245 ); 2246 printf("\nRevision=%d, ASIDs=%d", regs[0] & 0xff, regs[1]); 2247 } 2248 2249 #ifdef __i386__ 2250 static void 2251 print_transmeta_info(void) 2252 { 2253 u_int regs[4], nreg = 0; 2254 2255 do_cpuid(0x80860000, regs); 2256 nreg = regs[0]; 2257 if (nreg >= 0x80860001) { 2258 do_cpuid(0x80860001, regs); 2259 printf(" Processor revision %u.%u.%u.%u\n", 2260 (regs[1] >> 24) & 0xff, 2261 (regs[1] >> 16) & 0xff, 2262 (regs[1] >> 8) & 0xff, 2263 regs[1] & 0xff); 2264 } 2265 if (nreg >= 0x80860002) { 2266 do_cpuid(0x80860002, regs); 2267 printf(" Code Morphing Software revision %u.%u.%u-%u-%u\n", 2268 (regs[1] >> 24) & 0xff, 2269 (regs[1] >> 16) & 0xff, 2270 (regs[1] >> 8) & 0xff, 2271 regs[1] & 0xff, 2272 regs[2]); 2273 } 2274 if (nreg >= 0x80860006) { 2275 char info[65]; 2276 do_cpuid(0x80860003, (u_int*) &info[0]); 2277 do_cpuid(0x80860004, (u_int*) &info[16]); 2278 do_cpuid(0x80860005, (u_int*) &info[32]); 2279 do_cpuid(0x80860006, (u_int*) &info[48]); 2280 info[64] = 0; 2281 printf(" %s\n", info); 2282 } 2283 } 2284 #endif 2285 2286 static void 2287 print_via_padlock_info(void) 2288 { 2289 u_int regs[4]; 2290 2291 do_cpuid(0xc0000001, regs); 2292 printf("\n VIA Padlock Features=0x%b", regs[3], 2293 "\020" 2294 "\003RNG" /* RNG */ 2295 "\007AES" /* ACE */ 2296 "\011AES-CTR" /* ACE2 */ 2297 "\013SHA1,SHA256" /* PHE */ 2298 "\015RSA" /* PMM */ 2299 ); 2300 } 2301 2302 static uint32_t 2303 vmx_settable(uint64_t basic, int msr, int true_msr) 2304 { 2305 uint64_t val; 2306 2307 if (basic & (1ULL << 55)) 2308 val = rdmsr(true_msr); 2309 else 2310 val = rdmsr(msr); 2311 2312 /* Just report the controls that can be set to 1. */ 2313 return (val >> 32); 2314 } 2315 2316 static void 2317 print_vmx_info(void) 2318 { 2319 uint64_t basic, msr; 2320 uint32_t entry, exit, mask, pin, proc, proc2; 2321 int comma; 2322 2323 printf("\n VT-x: "); 2324 msr = rdmsr(MSR_IA32_FEATURE_CONTROL); 2325 if (!(msr & IA32_FEATURE_CONTROL_VMX_EN)) 2326 printf("(disabled in BIOS) "); 2327 basic = rdmsr(MSR_VMX_BASIC); 2328 pin = vmx_settable(basic, MSR_VMX_PINBASED_CTLS, 2329 MSR_VMX_TRUE_PINBASED_CTLS); 2330 proc = vmx_settable(basic, MSR_VMX_PROCBASED_CTLS, 2331 MSR_VMX_TRUE_PROCBASED_CTLS); 2332 if (proc & PROCBASED_SECONDARY_CONTROLS) 2333 proc2 = vmx_settable(basic, MSR_VMX_PROCBASED_CTLS2, 2334 MSR_VMX_PROCBASED_CTLS2); 2335 else 2336 proc2 = 0; 2337 exit = vmx_settable(basic, MSR_VMX_EXIT_CTLS, MSR_VMX_TRUE_EXIT_CTLS); 2338 entry = vmx_settable(basic, MSR_VMX_ENTRY_CTLS, MSR_VMX_TRUE_ENTRY_CTLS); 2339 2340 if (!bootverbose) { 2341 comma = 0; 2342 if (exit & VM_EXIT_SAVE_PAT && exit & VM_EXIT_LOAD_PAT && 2343 entry & VM_ENTRY_LOAD_PAT) { 2344 printf("%sPAT", comma ? "," : ""); 2345 comma = 1; 2346 } 2347 if (proc & PROCBASED_HLT_EXITING) { 2348 printf("%sHLT", comma ? "," : ""); 2349 comma = 1; 2350 } 2351 if (proc & PROCBASED_MTF) { 2352 printf("%sMTF", comma ? "," : ""); 2353 comma = 1; 2354 } 2355 if (proc & PROCBASED_PAUSE_EXITING) { 2356 printf("%sPAUSE", comma ? "," : ""); 2357 comma = 1; 2358 } 2359 if (proc2 & PROCBASED2_ENABLE_EPT) { 2360 printf("%sEPT", comma ? "," : ""); 2361 comma = 1; 2362 } 2363 if (proc2 & PROCBASED2_UNRESTRICTED_GUEST) { 2364 printf("%sUG", comma ? "," : ""); 2365 comma = 1; 2366 } 2367 if (proc2 & PROCBASED2_ENABLE_VPID) { 2368 printf("%sVPID", comma ? "," : ""); 2369 comma = 1; 2370 } 2371 if (proc & PROCBASED_USE_TPR_SHADOW && 2372 proc2 & PROCBASED2_VIRTUALIZE_APIC_ACCESSES && 2373 proc2 & PROCBASED2_VIRTUALIZE_X2APIC_MODE && 2374 proc2 & PROCBASED2_APIC_REGISTER_VIRTUALIZATION && 2375 proc2 & PROCBASED2_VIRTUAL_INTERRUPT_DELIVERY) { 2376 printf("%sVID", comma ? "," : ""); 2377 comma = 1; 2378 if (pin & PINBASED_POSTED_INTERRUPT) 2379 printf(",PostIntr"); 2380 } 2381 return; 2382 } 2383 2384 mask = basic >> 32; 2385 printf("Basic Features=0x%b", mask, 2386 "\020" 2387 "\02132PA" /* 32-bit physical addresses */ 2388 "\022SMM" /* SMM dual-monitor */ 2389 "\027INS/OUTS" /* VM-exit info for INS and OUTS */ 2390 "\030TRUE" /* TRUE_CTLS MSRs */ 2391 ); 2392 printf("\n Pin-Based Controls=0x%b", pin, 2393 "\020" 2394 "\001ExtINT" /* External-interrupt exiting */ 2395 "\004NMI" /* NMI exiting */ 2396 "\006VNMI" /* Virtual NMIs */ 2397 "\007PreTmr" /* Activate VMX-preemption timer */ 2398 "\010PostIntr" /* Process posted interrupts */ 2399 ); 2400 printf("\n Primary Processor Controls=0x%b", proc, 2401 "\020" 2402 "\003INTWIN" /* Interrupt-window exiting */ 2403 "\004TSCOff" /* Use TSC offsetting */ 2404 "\010HLT" /* HLT exiting */ 2405 "\012INVLPG" /* INVLPG exiting */ 2406 "\013MWAIT" /* MWAIT exiting */ 2407 "\014RDPMC" /* RDPMC exiting */ 2408 "\015RDTSC" /* RDTSC exiting */ 2409 "\020CR3-LD" /* CR3-load exiting */ 2410 "\021CR3-ST" /* CR3-store exiting */ 2411 "\024CR8-LD" /* CR8-load exiting */ 2412 "\025CR8-ST" /* CR8-store exiting */ 2413 "\026TPR" /* Use TPR shadow */ 2414 "\027NMIWIN" /* NMI-window exiting */ 2415 "\030MOV-DR" /* MOV-DR exiting */ 2416 "\031IO" /* Unconditional I/O exiting */ 2417 "\032IOmap" /* Use I/O bitmaps */ 2418 "\034MTF" /* Monitor trap flag */ 2419 "\035MSRmap" /* Use MSR bitmaps */ 2420 "\036MONITOR" /* MONITOR exiting */ 2421 "\037PAUSE" /* PAUSE exiting */ 2422 ); 2423 if (proc & PROCBASED_SECONDARY_CONTROLS) 2424 printf("\n Secondary Processor Controls=0x%b", proc2, 2425 "\020" 2426 "\001APIC" /* Virtualize APIC accesses */ 2427 "\002EPT" /* Enable EPT */ 2428 "\003DT" /* Descriptor-table exiting */ 2429 "\004RDTSCP" /* Enable RDTSCP */ 2430 "\005x2APIC" /* Virtualize x2APIC mode */ 2431 "\006VPID" /* Enable VPID */ 2432 "\007WBINVD" /* WBINVD exiting */ 2433 "\010UG" /* Unrestricted guest */ 2434 "\011APIC-reg" /* APIC-register virtualization */ 2435 "\012VID" /* Virtual-interrupt delivery */ 2436 "\013PAUSE-loop" /* PAUSE-loop exiting */ 2437 "\014RDRAND" /* RDRAND exiting */ 2438 "\015INVPCID" /* Enable INVPCID */ 2439 "\016VMFUNC" /* Enable VM functions */ 2440 "\017VMCS" /* VMCS shadowing */ 2441 "\020EPT#VE" /* EPT-violation #VE */ 2442 "\021XSAVES" /* Enable XSAVES/XRSTORS */ 2443 ); 2444 printf("\n Exit Controls=0x%b", mask, 2445 "\020" 2446 "\003DR" /* Save debug controls */ 2447 /* Ignore Host address-space size */ 2448 "\015PERF" /* Load MSR_PERF_GLOBAL_CTRL */ 2449 "\020AckInt" /* Acknowledge interrupt on exit */ 2450 "\023PAT-SV" /* Save MSR_PAT */ 2451 "\024PAT-LD" /* Load MSR_PAT */ 2452 "\025EFER-SV" /* Save MSR_EFER */ 2453 "\026EFER-LD" /* Load MSR_EFER */ 2454 "\027PTMR-SV" /* Save VMX-preemption timer value */ 2455 ); 2456 printf("\n Entry Controls=0x%b", mask, 2457 "\020" 2458 "\003DR" /* Save debug controls */ 2459 /* Ignore IA-32e mode guest */ 2460 /* Ignore Entry to SMM */ 2461 /* Ignore Deactivate dual-monitor treatment */ 2462 "\016PERF" /* Load MSR_PERF_GLOBAL_CTRL */ 2463 "\017PAT" /* Load MSR_PAT */ 2464 "\020EFER" /* Load MSR_EFER */ 2465 ); 2466 if (proc & PROCBASED_SECONDARY_CONTROLS && 2467 (proc2 & (PROCBASED2_ENABLE_EPT | PROCBASED2_ENABLE_VPID)) != 0) { 2468 msr = rdmsr(MSR_VMX_EPT_VPID_CAP); 2469 mask = msr; 2470 printf("\n EPT Features=0x%b", mask, 2471 "\020" 2472 "\001XO" /* Execute-only translations */ 2473 "\007PW4" /* Page-walk length of 4 */ 2474 "\011UC" /* EPT paging-structure mem can be UC */ 2475 "\017WB" /* EPT paging-structure mem can be WB */ 2476 "\0212M" /* EPT PDE can map a 2-Mbyte page */ 2477 "\0221G" /* EPT PDPTE can map a 1-Gbyte page */ 2478 "\025INVEPT" /* INVEPT is supported */ 2479 "\026AD" /* Accessed and dirty flags for EPT */ 2480 "\032single" /* INVEPT single-context type */ 2481 "\033all" /* INVEPT all-context type */ 2482 ); 2483 mask = msr >> 32; 2484 printf("\n VPID Features=0x%b", mask, 2485 "\020" 2486 "\001INVVPID" /* INVVPID is supported */ 2487 "\011individual" /* INVVPID individual-address type */ 2488 "\012single" /* INVVPID single-context type */ 2489 "\013all" /* INVVPID all-context type */ 2490 /* INVVPID single-context-retaining-globals type */ 2491 "\014single-globals" 2492 ); 2493 } 2494 } 2495 2496 static void 2497 print_hypervisor_info(void) 2498 { 2499 2500 if (*hv_vendor) 2501 printf("Hypervisor: Origin = \"%s\"\n", hv_vendor); 2502 } 2503