1 /*- 2 * Copyright (c) 1992 Terrence R. Lambert. 3 * Copyright (c) 1982, 1987, 1990 The Regents of the University of California. 4 * Copyright (c) 1997 KATO Takenori. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to Berkeley by 8 * William Jolitz. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by the University of 21 * California, Berkeley and its contributors. 22 * 4. Neither the name of the University nor the names of its contributors 23 * may be used to endorse or promote products derived from this software 24 * without specific prior written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 27 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 28 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 29 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 30 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 31 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 32 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 33 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 34 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 35 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 36 * SUCH DAMAGE. 37 * 38 * from: Id: machdep.c,v 1.193 1996/06/18 01:22:04 bde Exp 39 */ 40 41 #include <sys/cdefs.h> 42 #include "opt_cpu.h" 43 44 #include <sys/param.h> 45 #include <sys/bus.h> 46 #include <sys/cpu.h> 47 #include <sys/eventhandler.h> 48 #include <sys/limits.h> 49 #include <sys/systm.h> 50 #include <sys/kernel.h> 51 #include <sys/sysctl.h> 52 #include <sys/power.h> 53 54 #include <vm/vm.h> 55 #include <vm/pmap.h> 56 57 #include <machine/asmacros.h> 58 #include <machine/clock.h> 59 #include <machine/cputypes.h> 60 #include <machine/frame.h> 61 #include <machine/intr_machdep.h> 62 #include <machine/md_var.h> 63 #include <machine/segments.h> 64 #include <machine/specialreg.h> 65 66 #include <amd64/vmm/intel/vmx_controls.h> 67 #include <x86/isa/icu.h> 68 #include <x86/vmware.h> 69 70 #ifdef __i386__ 71 #define IDENTBLUE_CYRIX486 0 72 #define IDENTBLUE_IBMCPU 1 73 #define IDENTBLUE_CYRIXM2 2 74 75 static void identifycyrix(void); 76 static void print_transmeta_info(void); 77 #endif 78 static u_int find_cpu_vendor_id(void); 79 static void print_AMD_info(void); 80 static void print_INTEL_info(void); 81 static void print_INTEL_TLB(u_int data); 82 static void print_hypervisor_info(void); 83 static void print_svm_info(void); 84 static void print_via_padlock_info(void); 85 static void print_vmx_info(void); 86 87 #ifdef __i386__ 88 int cpu; /* Are we 386, 386sx, 486, etc? */ 89 int cpu_class; 90 #endif 91 u_int cpu_feature; /* Feature flags */ 92 u_int cpu_feature2; /* Feature flags */ 93 u_int amd_feature; /* AMD feature flags */ 94 u_int amd_feature2; /* AMD feature flags */ 95 u_int amd_rascap; /* AMD RAS capabilities */ 96 u_int amd_pminfo; /* AMD advanced power management info */ 97 u_int amd_extended_feature_extensions; 98 u_int via_feature_rng; /* VIA RNG features */ 99 u_int via_feature_xcrypt; /* VIA ACE features */ 100 u_int cpu_high; /* Highest arg to CPUID */ 101 u_int cpu_exthigh; /* Highest arg to extended CPUID */ 102 u_int cpu_id; /* Stepping ID */ 103 u_int cpu_procinfo; /* HyperThreading Info / Brand Index / CLFUSH */ 104 u_int cpu_procinfo2; /* Multicore info */ 105 char cpu_vendor[20]; /* CPU Origin code */ 106 u_int cpu_vendor_id; /* CPU vendor ID */ 107 u_int cpu_mxcsr_mask; /* Valid bits in mxcsr */ 108 u_int cpu_clflush_line_size = 32; 109 u_int cpu_stdext_feature; /* %ebx */ 110 u_int cpu_stdext_feature2; /* %ecx */ 111 u_int cpu_stdext_feature3; /* %edx */ 112 uint64_t cpu_ia32_arch_caps; 113 u_int cpu_max_ext_state_size; 114 u_int cpu_mon_mwait_flags; /* MONITOR/MWAIT flags (CPUID.05H.ECX) */ 115 u_int cpu_mon_min_size; /* MONITOR minimum range size, bytes */ 116 u_int cpu_mon_max_size; /* MONITOR minimum range size, bytes */ 117 u_int cpu_maxphyaddr; /* Max phys addr width in bits */ 118 u_int cpu_power_eax; /* 06H: Power management leaf, %eax */ 119 u_int cpu_power_ebx; /* 06H: Power management leaf, %ebx */ 120 u_int cpu_power_ecx; /* 06H: Power management leaf, %ecx */ 121 u_int cpu_power_edx; /* 06H: Power management leaf, %edx */ 122 char machine[] = MACHINE; 123 124 SYSCTL_UINT(_hw, OID_AUTO, via_feature_rng, CTLFLAG_RD, 125 &via_feature_rng, 0, 126 "VIA RNG feature available in CPU"); 127 SYSCTL_UINT(_hw, OID_AUTO, via_feature_xcrypt, CTLFLAG_RD, 128 &via_feature_xcrypt, 0, 129 "VIA xcrypt feature available in CPU"); 130 131 #ifdef __amd64__ 132 #ifdef SCTL_MASK32 133 extern int adaptive_machine_arch; 134 #endif 135 136 static int 137 sysctl_hw_machine(SYSCTL_HANDLER_ARGS) 138 { 139 #ifdef SCTL_MASK32 140 static const char machine32[] = "i386"; 141 #endif 142 int error; 143 144 #ifdef SCTL_MASK32 145 if ((req->flags & SCTL_MASK32) != 0 && adaptive_machine_arch) 146 error = SYSCTL_OUT(req, machine32, sizeof(machine32)); 147 else 148 #endif 149 error = SYSCTL_OUT(req, machine, sizeof(machine)); 150 return (error); 151 152 } 153 SYSCTL_PROC(_hw, HW_MACHINE, machine, CTLTYPE_STRING | CTLFLAG_RD | 154 CTLFLAG_CAPRD | CTLFLAG_MPSAFE, NULL, 0, sysctl_hw_machine, "A", "Machine class"); 155 #else 156 SYSCTL_STRING(_hw, HW_MACHINE, machine, CTLFLAG_RD | CTLFLAG_CAPRD, 157 machine, 0, "Machine class"); 158 #endif 159 160 static char cpu_model[128]; 161 SYSCTL_STRING(_hw, HW_MODEL, model, CTLFLAG_RD | CTLFLAG_MPSAFE, 162 cpu_model, 0, "Machine model"); 163 164 static int hw_clockrate; 165 SYSCTL_INT(_hw, OID_AUTO, clockrate, CTLFLAG_RD, 166 &hw_clockrate, 0, "CPU instruction clock rate"); 167 168 u_int hv_base; 169 u_int hv_high; 170 char hv_vendor[16]; 171 SYSCTL_STRING(_hw, OID_AUTO, hv_vendor, CTLFLAG_RD | CTLFLAG_MPSAFE, hv_vendor, 172 0, "Hypervisor vendor"); 173 174 static eventhandler_tag tsc_post_tag; 175 176 static char cpu_brand[48]; 177 178 #ifdef __i386__ 179 #define MAX_BRAND_INDEX 8 180 181 static const char *cpu_brandtable[MAX_BRAND_INDEX + 1] = { 182 NULL, /* No brand */ 183 "Intel Celeron", 184 "Intel Pentium III", 185 "Intel Pentium III Xeon", 186 NULL, 187 NULL, 188 NULL, 189 NULL, 190 "Intel Pentium 4" 191 }; 192 193 static struct { 194 char *cpu_name; 195 int cpu_class; 196 } cpus[] = { 197 { "Intel 80286", CPUCLASS_286 }, /* CPU_286 */ 198 { "i386SX", CPUCLASS_386 }, /* CPU_386SX */ 199 { "i386DX", CPUCLASS_386 }, /* CPU_386 */ 200 { "i486SX", CPUCLASS_486 }, /* CPU_486SX */ 201 { "i486DX", CPUCLASS_486 }, /* CPU_486 */ 202 { "Pentium", CPUCLASS_586 }, /* CPU_586 */ 203 { "Cyrix 486", CPUCLASS_486 }, /* CPU_486DLC */ 204 { "Pentium Pro", CPUCLASS_686 }, /* CPU_686 */ 205 { "Cyrix 5x86", CPUCLASS_486 }, /* CPU_M1SC */ 206 { "Cyrix 6x86", CPUCLASS_486 }, /* CPU_M1 */ 207 { "Blue Lightning", CPUCLASS_486 }, /* CPU_BLUE */ 208 { "Cyrix 6x86MX", CPUCLASS_686 }, /* CPU_M2 */ 209 { "NexGen 586", CPUCLASS_386 }, /* CPU_NX586 (XXX) */ 210 { "Cyrix 486S/DX", CPUCLASS_486 }, /* CPU_CY486DX */ 211 { "Pentium II", CPUCLASS_686 }, /* CPU_PII */ 212 { "Pentium III", CPUCLASS_686 }, /* CPU_PIII */ 213 { "Pentium 4", CPUCLASS_686 }, /* CPU_P4 */ 214 }; 215 #endif 216 217 static struct { 218 char *vendor; 219 u_int vendor_id; 220 } cpu_vendors[] = { 221 { INTEL_VENDOR_ID, CPU_VENDOR_INTEL }, /* GenuineIntel */ 222 { AMD_VENDOR_ID, CPU_VENDOR_AMD }, /* AuthenticAMD */ 223 { HYGON_VENDOR_ID, CPU_VENDOR_HYGON }, /* HygonGenuine */ 224 { CENTAUR_VENDOR_ID, CPU_VENDOR_CENTAUR }, /* CentaurHauls */ 225 #ifdef __i386__ 226 { NSC_VENDOR_ID, CPU_VENDOR_NSC }, /* Geode by NSC */ 227 { CYRIX_VENDOR_ID, CPU_VENDOR_CYRIX }, /* CyrixInstead */ 228 { TRANSMETA_VENDOR_ID, CPU_VENDOR_TRANSMETA }, /* GenuineTMx86 */ 229 { SIS_VENDOR_ID, CPU_VENDOR_SIS }, /* SiS SiS SiS */ 230 { UMC_VENDOR_ID, CPU_VENDOR_UMC }, /* UMC UMC UMC */ 231 { NEXGEN_VENDOR_ID, CPU_VENDOR_NEXGEN }, /* NexGenDriven */ 232 { RISE_VENDOR_ID, CPU_VENDOR_RISE }, /* RiseRiseRise */ 233 #if 0 234 /* XXX CPUID 8000_0000h and 8086_0000h, not 0000_0000h */ 235 { "TransmetaCPU", CPU_VENDOR_TRANSMETA }, 236 #endif 237 #endif 238 }; 239 240 void 241 printcpuinfo(void) 242 { 243 u_int regs[4], i; 244 char *brand; 245 246 printf("CPU: "); 247 #ifdef __i386__ 248 cpu_class = cpus[cpu].cpu_class; 249 strncpy(cpu_model, cpus[cpu].cpu_name, sizeof (cpu_model)); 250 #else 251 strncpy(cpu_model, "Hammer", sizeof (cpu_model)); 252 #endif 253 254 /* Check for extended CPUID information and a processor name. */ 255 if (cpu_exthigh >= 0x80000004) { 256 brand = cpu_brand; 257 for (i = 0x80000002; i < 0x80000005; i++) { 258 do_cpuid(i, regs); 259 memcpy(brand, regs, sizeof(regs)); 260 brand += sizeof(regs); 261 } 262 } 263 264 switch (cpu_vendor_id) { 265 case CPU_VENDOR_INTEL: 266 #ifdef __i386__ 267 if ((cpu_id & 0xf00) > 0x300) { 268 u_int brand_index; 269 270 cpu_model[0] = '\0'; 271 272 switch (cpu_id & 0x3000) { 273 case 0x1000: 274 strcpy(cpu_model, "Overdrive "); 275 break; 276 case 0x2000: 277 strcpy(cpu_model, "Dual "); 278 break; 279 } 280 281 switch (cpu_id & 0xf00) { 282 case 0x400: 283 strcat(cpu_model, "i486 "); 284 /* Check the particular flavor of 486 */ 285 switch (cpu_id & 0xf0) { 286 case 0x00: 287 case 0x10: 288 strcat(cpu_model, "DX"); 289 break; 290 case 0x20: 291 strcat(cpu_model, "SX"); 292 break; 293 case 0x30: 294 strcat(cpu_model, "DX2"); 295 break; 296 case 0x40: 297 strcat(cpu_model, "SL"); 298 break; 299 case 0x50: 300 strcat(cpu_model, "SX2"); 301 break; 302 case 0x70: 303 strcat(cpu_model, 304 "DX2 Write-Back Enhanced"); 305 break; 306 case 0x80: 307 strcat(cpu_model, "DX4"); 308 break; 309 } 310 break; 311 case 0x500: 312 /* Check the particular flavor of 586 */ 313 strcat(cpu_model, "Pentium"); 314 switch (cpu_id & 0xf0) { 315 case 0x00: 316 strcat(cpu_model, " A-step"); 317 break; 318 case 0x10: 319 strcat(cpu_model, "/P5"); 320 break; 321 case 0x20: 322 strcat(cpu_model, "/P54C"); 323 break; 324 case 0x30: 325 strcat(cpu_model, "/P24T"); 326 break; 327 case 0x40: 328 strcat(cpu_model, "/P55C"); 329 break; 330 case 0x70: 331 strcat(cpu_model, "/P54C"); 332 break; 333 case 0x80: 334 strcat(cpu_model, "/P55C (quarter-micron)"); 335 break; 336 default: 337 /* nothing */ 338 break; 339 } 340 #if defined(I586_CPU) && !defined(NO_F00F_HACK) 341 /* 342 * XXX - If/when Intel fixes the bug, this 343 * should also check the version of the 344 * CPU, not just that it's a Pentium. 345 */ 346 has_f00f_bug = 1; 347 #endif 348 break; 349 case 0x600: 350 /* Check the particular flavor of 686 */ 351 switch (cpu_id & 0xf0) { 352 case 0x00: 353 strcat(cpu_model, "Pentium Pro A-step"); 354 break; 355 case 0x10: 356 strcat(cpu_model, "Pentium Pro"); 357 break; 358 case 0x30: 359 case 0x50: 360 case 0x60: 361 strcat(cpu_model, 362 "Pentium II/Pentium II Xeon/Celeron"); 363 cpu = CPU_PII; 364 break; 365 case 0x70: 366 case 0x80: 367 case 0xa0: 368 case 0xb0: 369 strcat(cpu_model, 370 "Pentium III/Pentium III Xeon/Celeron"); 371 cpu = CPU_PIII; 372 break; 373 default: 374 strcat(cpu_model, "Unknown 80686"); 375 break; 376 } 377 break; 378 case 0xf00: 379 strcat(cpu_model, "Pentium 4"); 380 cpu = CPU_P4; 381 break; 382 default: 383 strcat(cpu_model, "unknown"); 384 break; 385 } 386 387 /* 388 * If we didn't get a brand name from the extended 389 * CPUID, try to look it up in the brand table. 390 */ 391 if (cpu_high > 0 && *cpu_brand == '\0') { 392 brand_index = cpu_procinfo & CPUID_BRAND_INDEX; 393 if (brand_index <= MAX_BRAND_INDEX && 394 cpu_brandtable[brand_index] != NULL) 395 strcpy(cpu_brand, 396 cpu_brandtable[brand_index]); 397 } 398 } 399 #else 400 /* Please make up your mind folks! */ 401 strcat(cpu_model, "EM64T"); 402 #endif 403 break; 404 case CPU_VENDOR_AMD: 405 /* 406 * Values taken from AMD Processor Recognition 407 * http://www.amd.com/K6/k6docs/pdf/20734g.pdf 408 * (also describes ``Features'' encodings. 409 */ 410 strcpy(cpu_model, "AMD "); 411 #ifdef __i386__ 412 switch (cpu_id & 0xFF0) { 413 case 0x410: 414 strcat(cpu_model, "Standard Am486DX"); 415 break; 416 case 0x430: 417 strcat(cpu_model, "Enhanced Am486DX2 Write-Through"); 418 break; 419 case 0x470: 420 strcat(cpu_model, "Enhanced Am486DX2 Write-Back"); 421 break; 422 case 0x480: 423 strcat(cpu_model, "Enhanced Am486DX4/Am5x86 Write-Through"); 424 break; 425 case 0x490: 426 strcat(cpu_model, "Enhanced Am486DX4/Am5x86 Write-Back"); 427 break; 428 case 0x4E0: 429 strcat(cpu_model, "Am5x86 Write-Through"); 430 break; 431 case 0x4F0: 432 strcat(cpu_model, "Am5x86 Write-Back"); 433 break; 434 case 0x500: 435 strcat(cpu_model, "K5 model 0"); 436 break; 437 case 0x510: 438 strcat(cpu_model, "K5 model 1"); 439 break; 440 case 0x520: 441 strcat(cpu_model, "K5 PR166 (model 2)"); 442 break; 443 case 0x530: 444 strcat(cpu_model, "K5 PR200 (model 3)"); 445 break; 446 case 0x560: 447 strcat(cpu_model, "K6"); 448 break; 449 case 0x570: 450 strcat(cpu_model, "K6 266 (model 1)"); 451 break; 452 case 0x580: 453 strcat(cpu_model, "K6-2"); 454 break; 455 case 0x590: 456 strcat(cpu_model, "K6-III"); 457 break; 458 case 0x5a0: 459 strcat(cpu_model, "Geode LX"); 460 break; 461 default: 462 strcat(cpu_model, "Unknown"); 463 break; 464 } 465 #else 466 if ((cpu_id & 0xf00) == 0xf00) 467 strcat(cpu_model, "AMD64 Processor"); 468 else 469 strcat(cpu_model, "Unknown"); 470 #endif 471 break; 472 #ifdef __i386__ 473 case CPU_VENDOR_CYRIX: 474 strcpy(cpu_model, "Cyrix "); 475 switch (cpu_id & 0xff0) { 476 case 0x440: 477 strcat(cpu_model, "MediaGX"); 478 break; 479 case 0x520: 480 strcat(cpu_model, "6x86"); 481 break; 482 case 0x540: 483 cpu_class = CPUCLASS_586; 484 strcat(cpu_model, "GXm"); 485 break; 486 case 0x600: 487 strcat(cpu_model, "6x86MX"); 488 break; 489 default: 490 /* 491 * Even though CPU supports the cpuid 492 * instruction, it can be disabled. 493 * Therefore, this routine supports all Cyrix 494 * CPUs. 495 */ 496 switch (cyrix_did & 0xf0) { 497 case 0x00: 498 switch (cyrix_did & 0x0f) { 499 case 0x00: 500 strcat(cpu_model, "486SLC"); 501 break; 502 case 0x01: 503 strcat(cpu_model, "486DLC"); 504 break; 505 case 0x02: 506 strcat(cpu_model, "486SLC2"); 507 break; 508 case 0x03: 509 strcat(cpu_model, "486DLC2"); 510 break; 511 case 0x04: 512 strcat(cpu_model, "486SRx"); 513 break; 514 case 0x05: 515 strcat(cpu_model, "486DRx"); 516 break; 517 case 0x06: 518 strcat(cpu_model, "486SRx2"); 519 break; 520 case 0x07: 521 strcat(cpu_model, "486DRx2"); 522 break; 523 case 0x08: 524 strcat(cpu_model, "486SRu"); 525 break; 526 case 0x09: 527 strcat(cpu_model, "486DRu"); 528 break; 529 case 0x0a: 530 strcat(cpu_model, "486SRu2"); 531 break; 532 case 0x0b: 533 strcat(cpu_model, "486DRu2"); 534 break; 535 default: 536 strcat(cpu_model, "Unknown"); 537 break; 538 } 539 break; 540 case 0x10: 541 switch (cyrix_did & 0x0f) { 542 case 0x00: 543 strcat(cpu_model, "486S"); 544 break; 545 case 0x01: 546 strcat(cpu_model, "486S2"); 547 break; 548 case 0x02: 549 strcat(cpu_model, "486Se"); 550 break; 551 case 0x03: 552 strcat(cpu_model, "486S2e"); 553 break; 554 case 0x0a: 555 strcat(cpu_model, "486DX"); 556 break; 557 case 0x0b: 558 strcat(cpu_model, "486DX2"); 559 break; 560 case 0x0f: 561 strcat(cpu_model, "486DX4"); 562 break; 563 default: 564 strcat(cpu_model, "Unknown"); 565 break; 566 } 567 break; 568 case 0x20: 569 if ((cyrix_did & 0x0f) < 8) 570 strcat(cpu_model, "6x86"); /* Where did you get it? */ 571 else 572 strcat(cpu_model, "5x86"); 573 break; 574 case 0x30: 575 strcat(cpu_model, "6x86"); 576 break; 577 case 0x40: 578 if ((cyrix_did & 0xf000) == 0x3000) { 579 cpu_class = CPUCLASS_586; 580 strcat(cpu_model, "GXm"); 581 } else 582 strcat(cpu_model, "MediaGX"); 583 break; 584 case 0x50: 585 strcat(cpu_model, "6x86MX"); 586 break; 587 case 0xf0: 588 switch (cyrix_did & 0x0f) { 589 case 0x0d: 590 strcat(cpu_model, "Overdrive CPU"); 591 break; 592 case 0x0e: 593 strcpy(cpu_model, "Texas Instruments 486SXL"); 594 break; 595 case 0x0f: 596 strcat(cpu_model, "486SLC/DLC"); 597 break; 598 default: 599 strcat(cpu_model, "Unknown"); 600 break; 601 } 602 break; 603 default: 604 strcat(cpu_model, "Unknown"); 605 break; 606 } 607 break; 608 } 609 break; 610 case CPU_VENDOR_RISE: 611 strcpy(cpu_model, "Rise "); 612 switch (cpu_id & 0xff0) { 613 case 0x500: /* 6401 and 6441 (Kirin) */ 614 case 0x520: /* 6510 (Lynx) */ 615 strcat(cpu_model, "mP6"); 616 break; 617 default: 618 strcat(cpu_model, "Unknown"); 619 } 620 break; 621 #endif 622 case CPU_VENDOR_CENTAUR: 623 #ifdef __i386__ 624 switch (cpu_id & 0xff0) { 625 case 0x540: 626 strcpy(cpu_model, "IDT WinChip C6"); 627 break; 628 case 0x580: 629 strcpy(cpu_model, "IDT WinChip 2"); 630 break; 631 case 0x590: 632 strcpy(cpu_model, "IDT WinChip 3"); 633 break; 634 case 0x660: 635 strcpy(cpu_model, "VIA C3 Samuel"); 636 break; 637 case 0x670: 638 if (cpu_id & 0x8) 639 strcpy(cpu_model, "VIA C3 Ezra"); 640 else 641 strcpy(cpu_model, "VIA C3 Samuel 2"); 642 break; 643 case 0x680: 644 strcpy(cpu_model, "VIA C3 Ezra-T"); 645 break; 646 case 0x690: 647 strcpy(cpu_model, "VIA C3 Nehemiah"); 648 break; 649 case 0x6a0: 650 case 0x6d0: 651 strcpy(cpu_model, "VIA C7 Esther"); 652 break; 653 case 0x6f0: 654 strcpy(cpu_model, "VIA Nano"); 655 break; 656 default: 657 strcpy(cpu_model, "VIA/IDT Unknown"); 658 } 659 #else 660 strcpy(cpu_model, "VIA "); 661 if ((cpu_id & 0xff0) == 0x6f0) 662 strcat(cpu_model, "Nano Processor"); 663 else 664 strcat(cpu_model, "Unknown"); 665 #endif 666 break; 667 #ifdef __i386__ 668 case CPU_VENDOR_IBM: 669 strcpy(cpu_model, "Blue Lightning CPU"); 670 break; 671 case CPU_VENDOR_NSC: 672 switch (cpu_id & 0xff0) { 673 case 0x540: 674 strcpy(cpu_model, "Geode SC1100"); 675 cpu = CPU_GEODE1100; 676 break; 677 default: 678 strcpy(cpu_model, "Geode/NSC unknown"); 679 break; 680 } 681 break; 682 #endif 683 case CPU_VENDOR_HYGON: 684 strcpy(cpu_model, "Hygon "); 685 #ifdef __i386__ 686 strcat(cpu_model, "Unknown"); 687 #else 688 if ((cpu_id & 0xf00) == 0xf00) 689 strcat(cpu_model, "AMD64 Processor"); 690 else 691 strcat(cpu_model, "Unknown"); 692 #endif 693 break; 694 695 default: 696 strcat(cpu_model, "Unknown"); 697 break; 698 } 699 700 /* 701 * Replace cpu_model with cpu_brand minus leading spaces if 702 * we have one. 703 */ 704 brand = cpu_brand; 705 while (*brand == ' ') 706 ++brand; 707 if (*brand != '\0') 708 strcpy(cpu_model, brand); 709 710 printf("%s (", cpu_model); 711 if (tsc_freq != 0) { 712 hw_clockrate = (tsc_freq + 5000) / 1000000; 713 printf("%jd.%02d-MHz ", 714 (intmax_t)(tsc_freq + 4999) / 1000000, 715 (u_int)((tsc_freq + 4999) / 10000) % 100); 716 } 717 #ifdef __i386__ 718 switch(cpu_class) { 719 case CPUCLASS_286: 720 printf("286"); 721 break; 722 case CPUCLASS_386: 723 printf("386"); 724 break; 725 #if defined(I486_CPU) 726 case CPUCLASS_486: 727 printf("486"); 728 break; 729 #endif 730 #if defined(I586_CPU) 731 case CPUCLASS_586: 732 printf("586"); 733 break; 734 #endif 735 #if defined(I686_CPU) 736 case CPUCLASS_686: 737 printf("686"); 738 break; 739 #endif 740 default: 741 printf("Unknown"); /* will panic below... */ 742 } 743 #else 744 printf("K8"); 745 #endif 746 printf("-class CPU)\n"); 747 if (*cpu_vendor) 748 printf(" Origin=\"%s\"", cpu_vendor); 749 if (cpu_id) 750 printf(" Id=0x%x", cpu_id); 751 752 if (cpu_vendor_id == CPU_VENDOR_INTEL || 753 cpu_vendor_id == CPU_VENDOR_AMD || 754 cpu_vendor_id == CPU_VENDOR_HYGON || 755 cpu_vendor_id == CPU_VENDOR_CENTAUR || 756 #ifdef __i386__ 757 cpu_vendor_id == CPU_VENDOR_TRANSMETA || 758 cpu_vendor_id == CPU_VENDOR_RISE || 759 cpu_vendor_id == CPU_VENDOR_NSC || 760 (cpu_vendor_id == CPU_VENDOR_CYRIX && ((cpu_id & 0xf00) > 0x500)) || 761 #endif 762 0) { 763 printf(" Family=0x%x", CPUID_TO_FAMILY(cpu_id)); 764 printf(" Model=0x%x", CPUID_TO_MODEL(cpu_id)); 765 printf(" Stepping=%u", cpu_id & CPUID_STEPPING); 766 #ifdef __i386__ 767 if (cpu_vendor_id == CPU_VENDOR_CYRIX) 768 printf("\n DIR=0x%04x", cyrix_did); 769 #endif 770 771 /* 772 * AMD CPUID Specification 773 * http://support.amd.com/us/Embedded_TechDocs/25481.pdf 774 * 775 * Intel Processor Identification and CPUID Instruction 776 * http://www.intel.com/assets/pdf/appnote/241618.pdf 777 */ 778 if (cpu_high > 0) { 779 /* 780 * Here we should probably set up flags indicating 781 * whether or not various features are available. 782 * The interesting ones are probably VME, PSE, PAE, 783 * and PGE. The code already assumes without bothering 784 * to check that all CPUs >= Pentium have a TSC and 785 * MSRs. 786 */ 787 printf("\n Features=0x%b", cpu_feature, 788 "\020" 789 "\001FPU" /* Integral FPU */ 790 "\002VME" /* Extended VM86 mode support */ 791 "\003DE" /* Debugging Extensions (CR4.DE) */ 792 "\004PSE" /* 4MByte page tables */ 793 "\005TSC" /* Timestamp counter */ 794 "\006MSR" /* Machine specific registers */ 795 "\007PAE" /* Physical address extension */ 796 "\010MCE" /* Machine Check support */ 797 "\011CX8" /* CMPEXCH8 instruction */ 798 "\012APIC" /* SMP local APIC */ 799 "\013oldMTRR" /* Previous implementation of MTRR */ 800 "\014SEP" /* Fast System Call */ 801 "\015MTRR" /* Memory Type Range Registers */ 802 "\016PGE" /* PG_G (global bit) support */ 803 "\017MCA" /* Machine Check Architecture */ 804 "\020CMOV" /* CMOV instruction */ 805 "\021PAT" /* Page attributes table */ 806 "\022PSE36" /* 36 bit address space support */ 807 "\023PN" /* Processor Serial number */ 808 "\024CLFLUSH" /* Has the CLFLUSH instruction */ 809 "\025<b20>" 810 "\026DTS" /* Debug Trace Store */ 811 "\027ACPI" /* ACPI support */ 812 "\030MMX" /* MMX instructions */ 813 "\031FXSR" /* FXSAVE/FXRSTOR */ 814 "\032SSE" /* Streaming SIMD Extensions */ 815 "\033SSE2" /* Streaming SIMD Extensions #2 */ 816 "\034SS" /* Self snoop */ 817 "\035HTT" /* Hyperthreading (see EBX bit 16-23) */ 818 "\036TM" /* Thermal Monitor clock slowdown */ 819 "\037IA64" /* CPU can execute IA64 instructions */ 820 "\040PBE" /* Pending Break Enable */ 821 ); 822 823 if (cpu_feature2 != 0) { 824 printf("\n Features2=0x%b", cpu_feature2, 825 "\020" 826 "\001SSE3" /* SSE3 */ 827 "\002PCLMULQDQ" /* Carry-Less Mul Quadword */ 828 "\003DTES64" /* 64-bit Debug Trace */ 829 "\004MON" /* MONITOR/MWAIT Instructions */ 830 "\005DS_CPL" /* CPL Qualified Debug Store */ 831 "\006VMX" /* Virtual Machine Extensions */ 832 "\007SMX" /* Safer Mode Extensions */ 833 "\010EST" /* Enhanced SpeedStep */ 834 "\011TM2" /* Thermal Monitor 2 */ 835 "\012SSSE3" /* SSSE3 */ 836 "\013CNXT-ID" /* L1 context ID available */ 837 "\014SDBG" /* IA32 silicon debug */ 838 "\015FMA" /* Fused Multiply Add */ 839 "\016CX16" /* CMPXCHG16B Instruction */ 840 "\017xTPR" /* Send Task Priority Messages*/ 841 "\020PDCM" /* Perf/Debug Capability MSR */ 842 "\021<b16>" 843 "\022PCID" /* Process-context Identifiers*/ 844 "\023DCA" /* Direct Cache Access */ 845 "\024SSE4.1" /* SSE 4.1 */ 846 "\025SSE4.2" /* SSE 4.2 */ 847 "\026x2APIC" /* xAPIC Extensions */ 848 "\027MOVBE" /* MOVBE Instruction */ 849 "\030POPCNT" /* POPCNT Instruction */ 850 "\031TSCDLT" /* TSC-Deadline Timer */ 851 "\032AESNI" /* AES Crypto */ 852 "\033XSAVE" /* XSAVE/XRSTOR States */ 853 "\034OSXSAVE" /* OS-Enabled State Management*/ 854 "\035AVX" /* Advanced Vector Extensions */ 855 "\036F16C" /* Half-precision conversions */ 856 "\037RDRAND" /* RDRAND Instruction */ 857 "\040HV" /* Hypervisor */ 858 ); 859 } 860 861 if (amd_feature != 0) { 862 printf("\n AMD Features=0x%b", amd_feature, 863 "\020" /* in hex */ 864 "\001<s0>" /* Same */ 865 "\002<s1>" /* Same */ 866 "\003<s2>" /* Same */ 867 "\004<s3>" /* Same */ 868 "\005<s4>" /* Same */ 869 "\006<s5>" /* Same */ 870 "\007<s6>" /* Same */ 871 "\010<s7>" /* Same */ 872 "\011<s8>" /* Same */ 873 "\012<s9>" /* Same */ 874 "\013<b10>" /* Undefined */ 875 "\014SYSCALL" /* Have SYSCALL/SYSRET */ 876 "\015<s12>" /* Same */ 877 "\016<s13>" /* Same */ 878 "\017<s14>" /* Same */ 879 "\020<s15>" /* Same */ 880 "\021<s16>" /* Same */ 881 "\022<s17>" /* Same */ 882 "\023<b18>" /* Reserved, unknown */ 883 "\024MP" /* Multiprocessor Capable */ 884 "\025NX" /* Has EFER.NXE, NX */ 885 "\026<b21>" /* Undefined */ 886 "\027MMX+" /* AMD MMX Extensions */ 887 "\030<s23>" /* Same */ 888 "\031<s24>" /* Same */ 889 "\032FFXSR" /* Fast FXSAVE/FXRSTOR */ 890 "\033Page1GB" /* 1-GB large page support */ 891 "\034RDTSCP" /* RDTSCP */ 892 "\035<b28>" /* Undefined */ 893 "\036LM" /* 64 bit long mode */ 894 "\0373DNow!+" /* AMD 3DNow! Extensions */ 895 "\0403DNow!" /* AMD 3DNow! */ 896 ); 897 } 898 899 if (amd_feature2 != 0) { 900 printf("\n AMD Features2=0x%b", amd_feature2, 901 "\020" 902 "\001LAHF" /* LAHF/SAHF in long mode */ 903 "\002CMP" /* CMP legacy */ 904 "\003SVM" /* Secure Virtual Mode */ 905 "\004ExtAPIC" /* Extended APIC register */ 906 "\005CR8" /* CR8 in legacy mode */ 907 "\006ABM" /* LZCNT instruction */ 908 "\007SSE4A" /* SSE4A */ 909 "\010MAS" /* Misaligned SSE mode */ 910 "\011Prefetch" /* 3DNow! Prefetch/PrefetchW */ 911 "\012OSVW" /* OS visible workaround */ 912 "\013IBS" /* Instruction based sampling */ 913 "\014XOP" /* XOP extended instructions */ 914 "\015SKINIT" /* SKINIT/STGI */ 915 "\016WDT" /* Watchdog timer */ 916 "\017<b14>" 917 "\020LWP" /* Lightweight Profiling */ 918 "\021FMA4" /* 4-operand FMA instructions */ 919 "\022TCE" /* Translation Cache Extension */ 920 "\023<b18>" 921 "\024NodeId" /* NodeId MSR support */ 922 "\025<b20>" 923 "\026TBM" /* Trailing Bit Manipulation */ 924 "\027Topology" /* Topology Extensions */ 925 "\030PCXC" /* Core perf count */ 926 "\031PNXC" /* NB perf count */ 927 "\032<b25>" 928 "\033DBE" /* Data Breakpoint extension */ 929 "\034PTSC" /* Performance TSC */ 930 "\035PL2I" /* L2I perf count */ 931 "\036MWAITX" /* MONITORX/MWAITX instructions */ 932 "\037ADMSKX" /* Address mask extension */ 933 "\040<b31>" 934 ); 935 } 936 937 if (cpu_stdext_feature != 0) { 938 printf("\n Structured Extended Features=0x%b", 939 cpu_stdext_feature, 940 "\020" 941 /* RDFSBASE/RDGSBASE/WRFSBASE/WRGSBASE */ 942 "\001FSGSBASE" 943 "\002TSCADJ" 944 "\003SGX" 945 /* Bit Manipulation Instructions */ 946 "\004BMI1" 947 /* Hardware Lock Elision */ 948 "\005HLE" 949 /* Advanced Vector Instructions 2 */ 950 "\006AVX2" 951 /* FDP_EXCPTN_ONLY */ 952 "\007FDPEXC" 953 /* Supervisor Mode Execution Prot. */ 954 "\010SMEP" 955 /* Bit Manipulation Instructions */ 956 "\011BMI2" 957 "\012ERMS" 958 /* Invalidate Processor Context ID */ 959 "\013INVPCID" 960 /* Restricted Transactional Memory */ 961 "\014RTM" 962 "\015PQM" 963 "\016NFPUSG" 964 /* Intel Memory Protection Extensions */ 965 "\017MPX" 966 "\020PQE" 967 /* AVX512 Foundation */ 968 "\021AVX512F" 969 "\022AVX512DQ" 970 /* Enhanced NRBG */ 971 "\023RDSEED" 972 /* ADCX + ADOX */ 973 "\024ADX" 974 /* Supervisor Mode Access Prevention */ 975 "\025SMAP" 976 "\026AVX512IFMA" 977 /* Formerly PCOMMIT */ 978 "\027<b22>" 979 "\030CLFLUSHOPT" 980 "\031CLWB" 981 "\032PROCTRACE" 982 "\033AVX512PF" 983 "\034AVX512ER" 984 "\035AVX512CD" 985 "\036SHA" 986 "\037AVX512BW" 987 "\040AVX512VL" 988 ); 989 } 990 991 if (cpu_stdext_feature2 != 0) { 992 printf("\n Structured Extended Features2=0x%b", 993 cpu_stdext_feature2, 994 "\020" 995 "\001PREFETCHWT1" 996 "\002AVX512VBMI" 997 "\003UMIP" 998 "\004PKU" 999 "\005OSPKE" 1000 "\006WAITPKG" 1001 "\007AVX512VBMI2" 1002 "\011GFNI" 1003 "\012VAES" 1004 "\013VPCLMULQDQ" 1005 "\014AVX512VNNI" 1006 "\015AVX512BITALG" 1007 "\016TME" 1008 "\017AVX512VPOPCNTDQ" 1009 "\021LA57" 1010 "\027RDPID" 1011 "\032CLDEMOTE" 1012 "\034MOVDIRI" 1013 "\035MOVDIR64B" 1014 "\036ENQCMD" 1015 "\037SGXLC" 1016 ); 1017 } 1018 1019 if (cpu_stdext_feature3 != 0) { 1020 printf("\n Structured Extended Features3=0x%b", 1021 cpu_stdext_feature3, 1022 "\020" 1023 "\003AVX512_4VNNIW" 1024 "\004AVX512_4FMAPS" 1025 "\005FSRM" 1026 "\011AVX512VP2INTERSECT" 1027 "\012MCUOPT" 1028 "\013MD_CLEAR" 1029 "\016TSXFA" 1030 "\023PCONFIG" 1031 "\025IBT" 1032 "\033IBPB" 1033 "\034STIBP" 1034 "\035L1DFL" 1035 "\036ARCH_CAP" 1036 "\037CORE_CAP" 1037 "\040SSBD" 1038 ); 1039 } 1040 1041 if ((cpu_feature2 & CPUID2_XSAVE) != 0) { 1042 cpuid_count(0xd, 0x1, regs); 1043 if (regs[0] != 0) { 1044 printf("\n XSAVE Features=0x%b", 1045 regs[0], 1046 "\020" 1047 "\001XSAVEOPT" 1048 "\002XSAVEC" 1049 "\003XINUSE" 1050 "\004XSAVES"); 1051 } 1052 } 1053 1054 if (cpu_ia32_arch_caps != 0) { 1055 printf("\n IA32_ARCH_CAPS=0x%b", 1056 (u_int)cpu_ia32_arch_caps, 1057 "\020" 1058 "\001RDCL_NO" 1059 "\002IBRS_ALL" 1060 "\003RSBA" 1061 "\004SKIP_L1DFL_VME" 1062 "\005SSB_NO" 1063 "\006MDS_NO" 1064 "\010TSX_CTRL" 1065 "\011TAA_NO" 1066 ); 1067 } 1068 1069 if (amd_extended_feature_extensions != 0) { 1070 u_int amd_fe_masked; 1071 1072 amd_fe_masked = amd_extended_feature_extensions; 1073 if ((amd_fe_masked & AMDFEID_IBRS) == 0) 1074 amd_fe_masked &= 1075 ~(AMDFEID_IBRS_ALWAYSON | 1076 AMDFEID_PREFER_IBRS); 1077 if ((amd_fe_masked & AMDFEID_STIBP) == 0) 1078 amd_fe_masked &= 1079 ~AMDFEID_STIBP_ALWAYSON; 1080 1081 printf("\n " 1082 "AMD Extended Feature Extensions ID EBX=" 1083 "0x%b", amd_fe_masked, 1084 "\020" 1085 "\001CLZERO" 1086 "\002IRPerf" 1087 "\003XSaveErPtr" 1088 "\005RDPRU" 1089 "\011MCOMMIT" 1090 "\012WBNOINVD" 1091 "\015IBPB" 1092 "\017IBRS" 1093 "\020STIBP" 1094 "\021IBRS_ALWAYSON" 1095 "\022STIBP_ALWAYSON" 1096 "\023PREFER_IBRS" 1097 "\030PPIN" 1098 "\031SSBD" 1099 "\032VIRT_SSBD" 1100 "\033SSB_NO" 1101 ); 1102 } 1103 1104 if (via_feature_rng != 0 || via_feature_xcrypt != 0) 1105 print_via_padlock_info(); 1106 1107 if (cpu_feature2 & CPUID2_VMX) 1108 print_vmx_info(); 1109 1110 if (amd_feature2 & AMDID2_SVM) 1111 print_svm_info(); 1112 1113 if ((cpu_feature & CPUID_HTT) && 1114 (cpu_vendor_id == CPU_VENDOR_AMD || 1115 cpu_vendor_id == CPU_VENDOR_HYGON)) 1116 cpu_feature &= ~CPUID_HTT; 1117 1118 /* 1119 * If this CPU supports P-state invariant TSC then 1120 * mention the capability. 1121 */ 1122 if (tsc_is_invariant) { 1123 printf("\n TSC: P-state invariant"); 1124 if (tsc_perf_stat) 1125 printf(", performance statistics"); 1126 } 1127 } 1128 #ifdef __i386__ 1129 } else if (cpu_vendor_id == CPU_VENDOR_CYRIX) { 1130 printf(" DIR=0x%04x", cyrix_did); 1131 printf(" Stepping=%u", (cyrix_did & 0xf000) >> 12); 1132 printf(" Revision=%u", (cyrix_did & 0x0f00) >> 8); 1133 #ifndef CYRIX_CACHE_REALLY_WORKS 1134 if (cpu == CPU_M1 && (cyrix_did & 0xff00) < 0x1700) 1135 printf("\n CPU cache: write-through mode"); 1136 #endif 1137 #endif 1138 } 1139 1140 /* Avoid ugly blank lines: only print newline when we have to. */ 1141 if (*cpu_vendor || cpu_id) 1142 printf("\n"); 1143 1144 if (bootverbose) { 1145 if (cpu_vendor_id == CPU_VENDOR_AMD || 1146 cpu_vendor_id == CPU_VENDOR_HYGON) 1147 print_AMD_info(); 1148 else if (cpu_vendor_id == CPU_VENDOR_INTEL) 1149 print_INTEL_info(); 1150 #ifdef __i386__ 1151 else if (cpu_vendor_id == CPU_VENDOR_TRANSMETA) 1152 print_transmeta_info(); 1153 #endif 1154 } 1155 1156 print_hypervisor_info(); 1157 } 1158 1159 #ifdef __i386__ 1160 void 1161 panicifcpuunsupported(void) 1162 { 1163 1164 #if !defined(lint) 1165 #if !defined(I486_CPU) && !defined(I586_CPU) && !defined(I686_CPU) 1166 #error This kernel is not configured for one of the supported CPUs 1167 #endif 1168 #else /* lint */ 1169 #endif /* lint */ 1170 /* 1171 * Now that we have told the user what they have, 1172 * let them know if that machine type isn't configured. 1173 */ 1174 switch (cpu_class) { 1175 case CPUCLASS_286: /* a 286 should not make it this far, anyway */ 1176 case CPUCLASS_386: 1177 #if !defined(I486_CPU) 1178 case CPUCLASS_486: 1179 #endif 1180 #if !defined(I586_CPU) 1181 case CPUCLASS_586: 1182 #endif 1183 #if !defined(I686_CPU) 1184 case CPUCLASS_686: 1185 #endif 1186 panic("CPU class not configured"); 1187 default: 1188 break; 1189 } 1190 } 1191 1192 static volatile u_int trap_by_rdmsr; 1193 1194 /* 1195 * Special exception 6 handler. 1196 * The rdmsr instruction generates invalid opcodes fault on 486-class 1197 * Cyrix CPU. Stacked eip register points the rdmsr instruction in the 1198 * function identblue() when this handler is called. Stacked eip should 1199 * be advanced. 1200 */ 1201 inthand_t bluetrap6; 1202 __asm 1203 (" \n\ 1204 .text \n\ 1205 .p2align 2,0x90 \n\ 1206 .type " __XSTRING(CNAME(bluetrap6)) ",@function \n\ 1207 " __XSTRING(CNAME(bluetrap6)) ": \n\ 1208 ss \n\ 1209 movl $0xa8c1d," __XSTRING(CNAME(trap_by_rdmsr)) " \n\ 1210 addl $2, (%esp) /* rdmsr is a 2-byte instruction */ \n\ 1211 iret \n\ 1212 "); 1213 1214 /* 1215 * Special exception 13 handler. 1216 * Accessing non-existent MSR generates general protection fault. 1217 */ 1218 inthand_t bluetrap13; 1219 __asm 1220 (" \n\ 1221 .text \n\ 1222 .p2align 2,0x90 \n\ 1223 .type " __XSTRING(CNAME(bluetrap13)) ",@function \n\ 1224 " __XSTRING(CNAME(bluetrap13)) ": \n\ 1225 ss \n\ 1226 movl $0xa89c4," __XSTRING(CNAME(trap_by_rdmsr)) " \n\ 1227 popl %eax /* discard error code */ \n\ 1228 addl $2, (%esp) /* rdmsr is a 2-byte instruction */ \n\ 1229 iret \n\ 1230 "); 1231 1232 /* 1233 * Distinguish IBM Blue Lightning CPU from Cyrix CPUs that does not 1234 * support cpuid instruction. This function should be called after 1235 * loading interrupt descriptor table register. 1236 * 1237 * I don't like this method that handles fault, but I couldn't get 1238 * information for any other methods. Does blue giant know? 1239 */ 1240 static int 1241 identblue(void) 1242 { 1243 1244 trap_by_rdmsr = 0; 1245 1246 /* 1247 * Cyrix 486-class CPU does not support rdmsr instruction. 1248 * The rdmsr instruction generates invalid opcode fault, and exception 1249 * will be trapped by bluetrap6() on Cyrix 486-class CPU. The 1250 * bluetrap6() set the magic number to trap_by_rdmsr. 1251 */ 1252 setidt(IDT_UD, bluetrap6, SDT_SYS386TGT, SEL_KPL, 1253 GSEL(GCODE_SEL, SEL_KPL)); 1254 1255 /* 1256 * Certain BIOS disables cpuid instruction of Cyrix 6x86MX CPU. 1257 * In this case, rdmsr generates general protection fault, and 1258 * exception will be trapped by bluetrap13(). 1259 */ 1260 setidt(IDT_GP, bluetrap13, SDT_SYS386TGT, SEL_KPL, 1261 GSEL(GCODE_SEL, SEL_KPL)); 1262 1263 rdmsr(0x1002); /* Cyrix CPU generates fault. */ 1264 1265 if (trap_by_rdmsr == 0xa8c1d) 1266 return IDENTBLUE_CYRIX486; 1267 else if (trap_by_rdmsr == 0xa89c4) 1268 return IDENTBLUE_CYRIXM2; 1269 return IDENTBLUE_IBMCPU; 1270 } 1271 1272 /* 1273 * identifycyrix() set lower 16 bits of cyrix_did as follows: 1274 * 1275 * F E D C B A 9 8 7 6 5 4 3 2 1 0 1276 * +-------+-------+---------------+ 1277 * | SID | RID | Device ID | 1278 * | (DIR 1) | (DIR 0) | 1279 * +-------+-------+---------------+ 1280 */ 1281 static void 1282 identifycyrix(void) 1283 { 1284 register_t saveintr; 1285 int ccr2_test = 0, dir_test = 0; 1286 u_char ccr2, ccr3; 1287 1288 saveintr = intr_disable(); 1289 1290 ccr2 = read_cyrix_reg(CCR2); 1291 write_cyrix_reg(CCR2, ccr2 ^ CCR2_LOCK_NW); 1292 read_cyrix_reg(CCR2); 1293 if (read_cyrix_reg(CCR2) != ccr2) 1294 ccr2_test = 1; 1295 write_cyrix_reg(CCR2, ccr2); 1296 1297 ccr3 = read_cyrix_reg(CCR3); 1298 write_cyrix_reg(CCR3, ccr3 ^ CCR3_MAPEN3); 1299 read_cyrix_reg(CCR3); 1300 if (read_cyrix_reg(CCR3) != ccr3) 1301 dir_test = 1; /* CPU supports DIRs. */ 1302 write_cyrix_reg(CCR3, ccr3); 1303 1304 if (dir_test) { 1305 /* Device ID registers are available. */ 1306 cyrix_did = read_cyrix_reg(DIR1) << 8; 1307 cyrix_did += read_cyrix_reg(DIR0); 1308 } else if (ccr2_test) 1309 cyrix_did = 0x0010; /* 486S A-step */ 1310 else 1311 cyrix_did = 0x00ff; /* Old 486SLC/DLC and TI486SXLC/SXL */ 1312 1313 intr_restore(saveintr); 1314 } 1315 #endif 1316 1317 /* Update TSC freq with the value indicated by the caller. */ 1318 static void 1319 tsc_freq_changed(void *arg __unused, const struct cf_level *level, int status) 1320 { 1321 1322 /* If there was an error during the transition, don't do anything. */ 1323 if (status != 0) 1324 return; 1325 1326 /* Total setting for this level gives the new frequency in MHz. */ 1327 hw_clockrate = level->total_set.freq; 1328 } 1329 1330 static void 1331 hook_tsc_freq(void *arg __unused) 1332 { 1333 1334 if (tsc_is_invariant) 1335 return; 1336 1337 tsc_post_tag = EVENTHANDLER_REGISTER(cpufreq_post_change, 1338 tsc_freq_changed, NULL, EVENTHANDLER_PRI_ANY); 1339 } 1340 1341 SYSINIT(hook_tsc_freq, SI_SUB_CONFIGURE, SI_ORDER_ANY, hook_tsc_freq, NULL); 1342 1343 static struct { 1344 const char *vm_cpuid; 1345 int vm_guest; 1346 } vm_cpuids[] = { 1347 { "XenVMMXenVMM", VM_GUEST_XEN }, /* XEN */ 1348 { "Microsoft Hv", VM_GUEST_HV }, /* Microsoft Hyper-V */ 1349 { "VMwareVMware", VM_GUEST_VMWARE }, /* VMware VM */ 1350 { "KVMKVMKVM", VM_GUEST_KVM }, /* KVM */ 1351 { "bhyve bhyve ", VM_GUEST_BHYVE }, /* bhyve */ 1352 { "VBoxVBoxVBox", VM_GUEST_VBOX }, /* VirtualBox */ 1353 }; 1354 1355 static void 1356 identify_hypervisor_cpuid_base(void) 1357 { 1358 u_int leaf, regs[4]; 1359 int i; 1360 1361 /* 1362 * [RFC] CPUID usage for interaction between Hypervisors and Linux. 1363 * http://lkml.org/lkml/2008/10/1/246 1364 * 1365 * KB1009458: Mechanisms to determine if software is running in 1366 * a VMware virtual machine 1367 * http://kb.vmware.com/kb/1009458 1368 * 1369 * Search for a hypervisor that we recognize. If we cannot find 1370 * a specific hypervisor, return the first information about the 1371 * hypervisor that we found, as others may be able to use. 1372 */ 1373 for (leaf = 0x40000000; leaf < 0x40010000; leaf += 0x100) { 1374 do_cpuid(leaf, regs); 1375 1376 /* 1377 * KVM from Linux kernels prior to commit 1378 * 57c22e5f35aa4b9b2fe11f73f3e62bbf9ef36190 set %eax 1379 * to 0 rather than a valid hv_high value. Check for 1380 * the KVM signature bytes and fixup %eax to the 1381 * highest supported leaf in that case. 1382 */ 1383 if (regs[0] == 0 && regs[1] == 0x4b4d564b && 1384 regs[2] == 0x564b4d56 && regs[3] == 0x0000004d) 1385 regs[0] = leaf + 1; 1386 1387 if (regs[0] >= leaf) { 1388 for (i = 0; i < nitems(vm_cpuids); i++) 1389 if (strncmp((const char *)®s[1], 1390 vm_cpuids[i].vm_cpuid, 12) == 0) { 1391 vm_guest = vm_cpuids[i].vm_guest; 1392 break; 1393 } 1394 1395 /* 1396 * If this is the first entry or we found a 1397 * specific hypervisor, record the base, high value, 1398 * and vendor identifier. 1399 */ 1400 if (vm_guest != VM_GUEST_VM || leaf == 0x40000000) { 1401 hv_base = leaf; 1402 hv_high = regs[0]; 1403 ((u_int *)&hv_vendor)[0] = regs[1]; 1404 ((u_int *)&hv_vendor)[1] = regs[2]; 1405 ((u_int *)&hv_vendor)[2] = regs[3]; 1406 hv_vendor[12] = '\0'; 1407 1408 /* 1409 * If we found a specific hypervisor, then 1410 * we are finished. 1411 */ 1412 if (vm_guest != VM_GUEST_VM) 1413 return; 1414 } 1415 } 1416 } 1417 } 1418 1419 void 1420 identify_hypervisor(void) 1421 { 1422 u_int regs[4]; 1423 char *p; 1424 1425 TSENTER(); 1426 /* 1427 * If CPUID2_HV is set, we are running in a hypervisor environment. 1428 */ 1429 if (cpu_feature2 & CPUID2_HV) { 1430 vm_guest = VM_GUEST_VM; 1431 identify_hypervisor_cpuid_base(); 1432 1433 /* If we have a definitive vendor, we can return now. */ 1434 if (*hv_vendor != '\0') { 1435 TSEXIT(); 1436 return; 1437 } 1438 } 1439 1440 /* 1441 * Examine SMBIOS strings for older hypervisors. 1442 */ 1443 p = kern_getenv("smbios.system.serial"); 1444 if (p != NULL) { 1445 if (strncmp(p, "VMware-", 7) == 0 || strncmp(p, "VMW", 3) == 0) { 1446 vmware_hvcall(VMW_HVCMD_GETVERSION, regs); 1447 if (regs[1] == VMW_HVMAGIC) { 1448 vm_guest = VM_GUEST_VMWARE; 1449 freeenv(p); 1450 TSEXIT(); 1451 return; 1452 } 1453 } 1454 freeenv(p); 1455 } 1456 TSEXIT(); 1457 } 1458 1459 bool 1460 fix_cpuid(void) 1461 { 1462 uint64_t msr; 1463 1464 /* 1465 * Clear "Limit CPUID Maxval" bit and return true if the caller should 1466 * get the largest standard CPUID function number again if it is set 1467 * from BIOS. It is necessary for probing correct CPU topology later 1468 * and for the correct operation of the AVX-aware userspace. 1469 */ 1470 if (cpu_vendor_id == CPU_VENDOR_INTEL && 1471 ((CPUID_TO_FAMILY(cpu_id) == 0xf && 1472 CPUID_TO_MODEL(cpu_id) >= 0x3) || 1473 (CPUID_TO_FAMILY(cpu_id) == 0x6 && 1474 CPUID_TO_MODEL(cpu_id) >= 0xe))) { 1475 msr = rdmsr(MSR_IA32_MISC_ENABLE); 1476 if ((msr & IA32_MISC_EN_LIMCPUID) != 0) { 1477 msr &= ~IA32_MISC_EN_LIMCPUID; 1478 wrmsr(MSR_IA32_MISC_ENABLE, msr); 1479 return (true); 1480 } 1481 } 1482 1483 /* 1484 * Re-enable AMD Topology Extension that could be disabled by BIOS 1485 * on some notebook processors. Without the extension it's really 1486 * hard to determine the correct CPU cache topology. 1487 * See BIOS and Kernel Developer’s Guide (BKDG) for AMD Family 15h 1488 * Models 60h-6Fh Processors, Publication # 50742. 1489 */ 1490 if (vm_guest == VM_GUEST_NO && cpu_vendor_id == CPU_VENDOR_AMD && 1491 CPUID_TO_FAMILY(cpu_id) == 0x15) { 1492 msr = rdmsr(MSR_EXTFEATURES); 1493 if ((msr & ((uint64_t)1 << 54)) == 0) { 1494 msr |= (uint64_t)1 << 54; 1495 wrmsr(MSR_EXTFEATURES, msr); 1496 return (true); 1497 } 1498 } 1499 return (false); 1500 } 1501 1502 void 1503 identify_cpu1(void) 1504 { 1505 u_int regs[4]; 1506 1507 do_cpuid(0, regs); 1508 cpu_high = regs[0]; 1509 ((u_int *)&cpu_vendor)[0] = regs[1]; 1510 ((u_int *)&cpu_vendor)[1] = regs[3]; 1511 ((u_int *)&cpu_vendor)[2] = regs[2]; 1512 cpu_vendor[12] = '\0'; 1513 1514 do_cpuid(1, regs); 1515 cpu_id = regs[0]; 1516 cpu_procinfo = regs[1]; 1517 cpu_feature = regs[3]; 1518 cpu_feature2 = regs[2]; 1519 } 1520 1521 void 1522 identify_cpu2(void) 1523 { 1524 u_int regs[4], cpu_stdext_disable; 1525 1526 if (cpu_high >= 6) { 1527 cpuid_count(6, 0, regs); 1528 cpu_power_eax = regs[0]; 1529 cpu_power_ebx = regs[1]; 1530 cpu_power_ecx = regs[2]; 1531 cpu_power_edx = regs[3]; 1532 } 1533 1534 if (cpu_high >= 7) { 1535 cpuid_count(7, 0, regs); 1536 cpu_stdext_feature = regs[1]; 1537 1538 /* 1539 * Some hypervisors failed to filter out unsupported 1540 * extended features. Allow to disable the 1541 * extensions, activation of which requires setting a 1542 * bit in CR4, and which VM monitors do not support. 1543 */ 1544 cpu_stdext_disable = 0; 1545 TUNABLE_INT_FETCH("hw.cpu_stdext_disable", &cpu_stdext_disable); 1546 cpu_stdext_feature &= ~cpu_stdext_disable; 1547 1548 cpu_stdext_feature2 = regs[2]; 1549 cpu_stdext_feature3 = regs[3]; 1550 1551 if ((cpu_stdext_feature3 & CPUID_STDEXT3_ARCH_CAP) != 0) 1552 cpu_ia32_arch_caps = rdmsr(MSR_IA32_ARCH_CAP); 1553 } 1554 } 1555 1556 void 1557 identify_cpu_ext_features(void) 1558 { 1559 u_int regs[4]; 1560 1561 if (cpu_high >= 7) { 1562 cpuid_count(7, 0, regs); 1563 cpu_stdext_feature2 = regs[2]; 1564 cpu_stdext_feature3 = regs[3]; 1565 } 1566 } 1567 1568 void 1569 identify_cpu_fixup_bsp(void) 1570 { 1571 u_int regs[4]; 1572 1573 cpu_vendor_id = find_cpu_vendor_id(); 1574 1575 if (fix_cpuid()) { 1576 do_cpuid(0, regs); 1577 cpu_high = regs[0]; 1578 } 1579 } 1580 1581 /* 1582 * Final stage of CPU identification. 1583 */ 1584 void 1585 finishidentcpu(void) 1586 { 1587 u_int regs[4]; 1588 #ifdef __i386__ 1589 u_char ccr3; 1590 #endif 1591 1592 identify_cpu_fixup_bsp(); 1593 1594 if (cpu_high >= 5 && (cpu_feature2 & CPUID2_MON) != 0) { 1595 do_cpuid(5, regs); 1596 cpu_mon_mwait_flags = regs[2]; 1597 cpu_mon_min_size = regs[0] & CPUID5_MON_MIN_SIZE; 1598 cpu_mon_max_size = regs[1] & CPUID5_MON_MAX_SIZE; 1599 } 1600 1601 identify_cpu2(); 1602 1603 #ifdef __i386__ 1604 if (cpu_high > 0 && 1605 (cpu_vendor_id == CPU_VENDOR_INTEL || 1606 cpu_vendor_id == CPU_VENDOR_AMD || 1607 cpu_vendor_id == CPU_VENDOR_HYGON || 1608 cpu_vendor_id == CPU_VENDOR_TRANSMETA || 1609 cpu_vendor_id == CPU_VENDOR_CENTAUR || 1610 cpu_vendor_id == CPU_VENDOR_NSC)) { 1611 do_cpuid(0x80000000, regs); 1612 if (regs[0] >= 0x80000000) 1613 cpu_exthigh = regs[0]; 1614 } 1615 #else 1616 if (cpu_vendor_id == CPU_VENDOR_INTEL || 1617 cpu_vendor_id == CPU_VENDOR_AMD || 1618 cpu_vendor_id == CPU_VENDOR_HYGON || 1619 cpu_vendor_id == CPU_VENDOR_CENTAUR) { 1620 do_cpuid(0x80000000, regs); 1621 cpu_exthigh = regs[0]; 1622 } 1623 #endif 1624 if (cpu_exthigh >= 0x80000001) { 1625 do_cpuid(0x80000001, regs); 1626 amd_feature = regs[3] & ~(cpu_feature & 0x0183f3ff); 1627 amd_feature2 = regs[2]; 1628 } 1629 if (cpu_exthigh >= 0x80000007) { 1630 do_cpuid(0x80000007, regs); 1631 amd_rascap = regs[1]; 1632 amd_pminfo = regs[3]; 1633 } 1634 if (cpu_exthigh >= 0x80000008) { 1635 do_cpuid(0x80000008, regs); 1636 cpu_maxphyaddr = regs[0] & 0xff; 1637 amd_extended_feature_extensions = regs[1]; 1638 cpu_procinfo2 = regs[2]; 1639 } else { 1640 cpu_maxphyaddr = (cpu_feature & CPUID_PAE) != 0 ? 36 : 32; 1641 } 1642 1643 #ifdef __i386__ 1644 if (cpu_vendor_id == CPU_VENDOR_CYRIX) { 1645 if (cpu == CPU_486) { 1646 /* 1647 * These conditions are equivalent to: 1648 * - CPU does not support cpuid instruction. 1649 * - Cyrix/IBM CPU is detected. 1650 */ 1651 if (identblue() == IDENTBLUE_IBMCPU) { 1652 strcpy(cpu_vendor, "IBM"); 1653 cpu_vendor_id = CPU_VENDOR_IBM; 1654 cpu = CPU_BLUE; 1655 return; 1656 } 1657 } 1658 switch (cpu_id & 0xf00) { 1659 case 0x600: 1660 /* 1661 * Cyrix's datasheet does not describe DIRs. 1662 * Therefor, I assume it does not have them 1663 * and use the result of the cpuid instruction. 1664 * XXX they seem to have it for now at least. -Peter 1665 */ 1666 identifycyrix(); 1667 cpu = CPU_M2; 1668 break; 1669 default: 1670 identifycyrix(); 1671 /* 1672 * This routine contains a trick. 1673 * Don't check (cpu_id & 0x00f0) == 0x50 to detect M2, now. 1674 */ 1675 switch (cyrix_did & 0x00f0) { 1676 case 0x00: 1677 case 0xf0: 1678 cpu = CPU_486DLC; 1679 break; 1680 case 0x10: 1681 cpu = CPU_CY486DX; 1682 break; 1683 case 0x20: 1684 if ((cyrix_did & 0x000f) < 8) 1685 cpu = CPU_M1; 1686 else 1687 cpu = CPU_M1SC; 1688 break; 1689 case 0x30: 1690 cpu = CPU_M1; 1691 break; 1692 case 0x40: 1693 /* MediaGX CPU */ 1694 cpu = CPU_M1SC; 1695 break; 1696 default: 1697 /* M2 and later CPUs are treated as M2. */ 1698 cpu = CPU_M2; 1699 1700 /* 1701 * enable cpuid instruction. 1702 */ 1703 ccr3 = read_cyrix_reg(CCR3); 1704 write_cyrix_reg(CCR3, CCR3_MAPEN0); 1705 write_cyrix_reg(CCR4, read_cyrix_reg(CCR4) | CCR4_CPUID); 1706 write_cyrix_reg(CCR3, ccr3); 1707 1708 do_cpuid(0, regs); 1709 cpu_high = regs[0]; /* eax */ 1710 do_cpuid(1, regs); 1711 cpu_id = regs[0]; /* eax */ 1712 cpu_feature = regs[3]; /* edx */ 1713 break; 1714 } 1715 } 1716 } else if (cpu == CPU_486 && *cpu_vendor == '\0') { 1717 /* 1718 * There are BlueLightning CPUs that do not change 1719 * undefined flags by dividing 5 by 2. In this case, 1720 * the CPU identification routine in locore.s leaves 1721 * cpu_vendor null string and puts CPU_486 into the 1722 * cpu. 1723 */ 1724 if (identblue() == IDENTBLUE_IBMCPU) { 1725 strcpy(cpu_vendor, "IBM"); 1726 cpu_vendor_id = CPU_VENDOR_IBM; 1727 cpu = CPU_BLUE; 1728 return; 1729 } 1730 } 1731 #endif 1732 } 1733 1734 int 1735 pti_get_default(void) 1736 { 1737 1738 if (strcmp(cpu_vendor, AMD_VENDOR_ID) == 0 || 1739 strcmp(cpu_vendor, HYGON_VENDOR_ID) == 0) 1740 return (0); 1741 if ((cpu_ia32_arch_caps & IA32_ARCH_CAP_RDCL_NO) != 0) 1742 return (0); 1743 return (1); 1744 } 1745 1746 static u_int 1747 find_cpu_vendor_id(void) 1748 { 1749 int i; 1750 1751 for (i = 0; i < nitems(cpu_vendors); i++) 1752 if (strcmp(cpu_vendor, cpu_vendors[i].vendor) == 0) 1753 return (cpu_vendors[i].vendor_id); 1754 return (0); 1755 } 1756 1757 static void 1758 print_AMD_assoc(int i) 1759 { 1760 if (i == 255) 1761 printf(", fully associative\n"); 1762 else 1763 printf(", %d-way associative\n", i); 1764 } 1765 1766 static void 1767 print_AMD_l2_assoc(int i) 1768 { 1769 switch (i & 0x0f) { 1770 case 0: printf(", disabled/not present\n"); break; 1771 case 1: printf(", direct mapped\n"); break; 1772 case 2: printf(", 2-way associative\n"); break; 1773 case 4: printf(", 4-way associative\n"); break; 1774 case 6: printf(", 8-way associative\n"); break; 1775 case 8: printf(", 16-way associative\n"); break; 1776 case 15: printf(", fully associative\n"); break; 1777 default: printf(", reserved configuration\n"); break; 1778 } 1779 } 1780 1781 static void 1782 print_AMD_info(void) 1783 { 1784 #ifdef __i386__ 1785 uint64_t amd_whcr; 1786 #endif 1787 u_int regs[4]; 1788 1789 if (cpu_exthigh >= 0x80000005) { 1790 do_cpuid(0x80000005, regs); 1791 printf("L1 2MB data TLB: %d entries", (regs[0] >> 16) & 0xff); 1792 print_AMD_assoc(regs[0] >> 24); 1793 1794 printf("L1 2MB instruction TLB: %d entries", regs[0] & 0xff); 1795 print_AMD_assoc((regs[0] >> 8) & 0xff); 1796 1797 printf("L1 4KB data TLB: %d entries", (regs[1] >> 16) & 0xff); 1798 print_AMD_assoc(regs[1] >> 24); 1799 1800 printf("L1 4KB instruction TLB: %d entries", regs[1] & 0xff); 1801 print_AMD_assoc((regs[1] >> 8) & 0xff); 1802 1803 printf("L1 data cache: %d kbytes", regs[2] >> 24); 1804 printf(", %d bytes/line", regs[2] & 0xff); 1805 printf(", %d lines/tag", (regs[2] >> 8) & 0xff); 1806 print_AMD_assoc((regs[2] >> 16) & 0xff); 1807 1808 printf("L1 instruction cache: %d kbytes", regs[3] >> 24); 1809 printf(", %d bytes/line", regs[3] & 0xff); 1810 printf(", %d lines/tag", (regs[3] >> 8) & 0xff); 1811 print_AMD_assoc((regs[3] >> 16) & 0xff); 1812 } 1813 1814 if (cpu_exthigh >= 0x80000006) { 1815 do_cpuid(0x80000006, regs); 1816 if ((regs[0] >> 16) != 0) { 1817 printf("L2 2MB data TLB: %d entries", 1818 (regs[0] >> 16) & 0xfff); 1819 print_AMD_l2_assoc(regs[0] >> 28); 1820 printf("L2 2MB instruction TLB: %d entries", 1821 regs[0] & 0xfff); 1822 print_AMD_l2_assoc((regs[0] >> 28) & 0xf); 1823 } else { 1824 printf("L2 2MB unified TLB: %d entries", 1825 regs[0] & 0xfff); 1826 print_AMD_l2_assoc((regs[0] >> 28) & 0xf); 1827 } 1828 if ((regs[1] >> 16) != 0) { 1829 printf("L2 4KB data TLB: %d entries", 1830 (regs[1] >> 16) & 0xfff); 1831 print_AMD_l2_assoc(regs[1] >> 28); 1832 1833 printf("L2 4KB instruction TLB: %d entries", 1834 (regs[1] >> 16) & 0xfff); 1835 print_AMD_l2_assoc((regs[1] >> 28) & 0xf); 1836 } else { 1837 printf("L2 4KB unified TLB: %d entries", 1838 (regs[1] >> 16) & 0xfff); 1839 print_AMD_l2_assoc((regs[1] >> 28) & 0xf); 1840 } 1841 printf("L2 unified cache: %d kbytes", regs[2] >> 16); 1842 printf(", %d bytes/line", regs[2] & 0xff); 1843 printf(", %d lines/tag", (regs[2] >> 8) & 0x0f); 1844 print_AMD_l2_assoc((regs[2] >> 12) & 0x0f); 1845 } 1846 1847 #ifdef __i386__ 1848 if (((cpu_id & 0xf00) == 0x500) 1849 && (((cpu_id & 0x0f0) > 0x80) 1850 || (((cpu_id & 0x0f0) == 0x80) 1851 && (cpu_id & 0x00f) > 0x07))) { 1852 /* K6-2(new core [Stepping 8-F]), K6-III or later */ 1853 amd_whcr = rdmsr(0xc0000082); 1854 if (!(amd_whcr & (0x3ff << 22))) { 1855 printf("Write Allocate Disable\n"); 1856 } else { 1857 printf("Write Allocate Enable Limit: %dM bytes\n", 1858 (u_int32_t)((amd_whcr & (0x3ff << 22)) >> 22) * 4); 1859 printf("Write Allocate 15-16M bytes: %s\n", 1860 (amd_whcr & (1 << 16)) ? "Enable" : "Disable"); 1861 } 1862 } else if (((cpu_id & 0xf00) == 0x500) 1863 && ((cpu_id & 0x0f0) > 0x50)) { 1864 /* K6, K6-2(old core) */ 1865 amd_whcr = rdmsr(0xc0000082); 1866 if (!(amd_whcr & (0x7f << 1))) { 1867 printf("Write Allocate Disable\n"); 1868 } else { 1869 printf("Write Allocate Enable Limit: %dM bytes\n", 1870 (u_int32_t)((amd_whcr & (0x7f << 1)) >> 1) * 4); 1871 printf("Write Allocate 15-16M bytes: %s\n", 1872 (amd_whcr & 0x0001) ? "Enable" : "Disable"); 1873 printf("Hardware Write Allocate Control: %s\n", 1874 (amd_whcr & 0x0100) ? "Enable" : "Disable"); 1875 } 1876 } 1877 #endif 1878 /* 1879 * Opteron Rev E shows a bug as in very rare occasions a read memory 1880 * barrier is not performed as expected if it is followed by a 1881 * non-atomic read-modify-write instruction. 1882 * As long as that bug pops up very rarely (intensive machine usage 1883 * on other operating systems generally generates one unexplainable 1884 * crash any 2 months) and as long as a model specific fix would be 1885 * impractical at this stage, print out a warning string if the broken 1886 * model and family are identified. 1887 */ 1888 if (CPUID_TO_FAMILY(cpu_id) == 0xf && CPUID_TO_MODEL(cpu_id) >= 0x20 && 1889 CPUID_TO_MODEL(cpu_id) <= 0x3f) 1890 printf("WARNING: This architecture revision has known SMP " 1891 "hardware bugs which may cause random instability\n"); 1892 } 1893 1894 static void 1895 print_INTEL_info(void) 1896 { 1897 u_int regs[4]; 1898 u_int rounds, regnum; 1899 u_int nwaycode, nway; 1900 1901 if (cpu_high >= 2) { 1902 rounds = 0; 1903 do { 1904 do_cpuid(0x2, regs); 1905 if (rounds == 0 && (rounds = (regs[0] & 0xff)) == 0) 1906 break; /* we have a buggy CPU */ 1907 1908 for (regnum = 0; regnum <= 3; ++regnum) { 1909 if (regs[regnum] & (1<<31)) 1910 continue; 1911 if (regnum != 0) 1912 print_INTEL_TLB(regs[regnum] & 0xff); 1913 print_INTEL_TLB((regs[regnum] >> 8) & 0xff); 1914 print_INTEL_TLB((regs[regnum] >> 16) & 0xff); 1915 print_INTEL_TLB((regs[regnum] >> 24) & 0xff); 1916 } 1917 } while (--rounds > 0); 1918 } 1919 1920 if (cpu_exthigh >= 0x80000006) { 1921 do_cpuid(0x80000006, regs); 1922 nwaycode = (regs[2] >> 12) & 0x0f; 1923 if (nwaycode >= 0x02 && nwaycode <= 0x08) 1924 nway = 1 << (nwaycode / 2); 1925 else 1926 nway = 0; 1927 printf("L2 cache: %u kbytes, %u-way associative, %u bytes/line\n", 1928 (regs[2] >> 16) & 0xffff, nway, regs[2] & 0xff); 1929 } 1930 } 1931 1932 static void 1933 print_INTEL_TLB(u_int data) 1934 { 1935 switch (data) { 1936 case 0x0: 1937 case 0x40: 1938 default: 1939 break; 1940 case 0x1: 1941 printf("Instruction TLB: 4 KB pages, 4-way set associative, 32 entries\n"); 1942 break; 1943 case 0x2: 1944 printf("Instruction TLB: 4 MB pages, fully associative, 2 entries\n"); 1945 break; 1946 case 0x3: 1947 printf("Data TLB: 4 KB pages, 4-way set associative, 64 entries\n"); 1948 break; 1949 case 0x4: 1950 printf("Data TLB: 4 MB Pages, 4-way set associative, 8 entries\n"); 1951 break; 1952 case 0x6: 1953 printf("1st-level instruction cache: 8 KB, 4-way set associative, 32 byte line size\n"); 1954 break; 1955 case 0x8: 1956 printf("1st-level instruction cache: 16 KB, 4-way set associative, 32 byte line size\n"); 1957 break; 1958 case 0x9: 1959 printf("1st-level instruction cache: 32 KB, 4-way set associative, 64 byte line size\n"); 1960 break; 1961 case 0xa: 1962 printf("1st-level data cache: 8 KB, 2-way set associative, 32 byte line size\n"); 1963 break; 1964 case 0xb: 1965 printf("Instruction TLB: 4 MByte pages, 4-way set associative, 4 entries\n"); 1966 break; 1967 case 0xc: 1968 printf("1st-level data cache: 16 KB, 4-way set associative, 32 byte line size\n"); 1969 break; 1970 case 0xd: 1971 printf("1st-level data cache: 16 KBytes, 4-way set associative, 64 byte line size"); 1972 break; 1973 case 0xe: 1974 printf("1st-level data cache: 24 KBytes, 6-way set associative, 64 byte line size\n"); 1975 break; 1976 case 0x1d: 1977 printf("2nd-level cache: 128 KBytes, 2-way set associative, 64 byte line size\n"); 1978 break; 1979 case 0x21: 1980 printf("2nd-level cache: 256 KBytes, 8-way set associative, 64 byte line size\n"); 1981 break; 1982 case 0x22: 1983 printf("3rd-level cache: 512 KB, 4-way set associative, sectored cache, 64 byte line size\n"); 1984 break; 1985 case 0x23: 1986 printf("3rd-level cache: 1 MB, 8-way set associative, sectored cache, 64 byte line size\n"); 1987 break; 1988 case 0x24: 1989 printf("2nd-level cache: 1 MBytes, 16-way set associative, 64 byte line size\n"); 1990 break; 1991 case 0x25: 1992 printf("3rd-level cache: 2 MB, 8-way set associative, sectored cache, 64 byte line size\n"); 1993 break; 1994 case 0x29: 1995 printf("3rd-level cache: 4 MB, 8-way set associative, sectored cache, 64 byte line size\n"); 1996 break; 1997 case 0x2c: 1998 printf("1st-level data cache: 32 KB, 8-way set associative, 64 byte line size\n"); 1999 break; 2000 case 0x30: 2001 printf("1st-level instruction cache: 32 KB, 8-way set associative, 64 byte line size\n"); 2002 break; 2003 case 0x39: /* De-listed in SDM rev. 54 */ 2004 printf("2nd-level cache: 128 KB, 4-way set associative, sectored cache, 64 byte line size\n"); 2005 break; 2006 case 0x3b: /* De-listed in SDM rev. 54 */ 2007 printf("2nd-level cache: 128 KB, 2-way set associative, sectored cache, 64 byte line size\n"); 2008 break; 2009 case 0x3c: /* De-listed in SDM rev. 54 */ 2010 printf("2nd-level cache: 256 KB, 4-way set associative, sectored cache, 64 byte line size\n"); 2011 break; 2012 case 0x41: 2013 printf("2nd-level cache: 128 KB, 4-way set associative, 32 byte line size\n"); 2014 break; 2015 case 0x42: 2016 printf("2nd-level cache: 256 KB, 4-way set associative, 32 byte line size\n"); 2017 break; 2018 case 0x43: 2019 printf("2nd-level cache: 512 KB, 4-way set associative, 32 byte line size\n"); 2020 break; 2021 case 0x44: 2022 printf("2nd-level cache: 1 MB, 4-way set associative, 32 byte line size\n"); 2023 break; 2024 case 0x45: 2025 printf("2nd-level cache: 2 MB, 4-way set associative, 32 byte line size\n"); 2026 break; 2027 case 0x46: 2028 printf("3rd-level cache: 4 MB, 4-way set associative, 64 byte line size\n"); 2029 break; 2030 case 0x47: 2031 printf("3rd-level cache: 8 MB, 8-way set associative, 64 byte line size\n"); 2032 break; 2033 case 0x48: 2034 printf("2nd-level cache: 3MByte, 12-way set associative, 64 byte line size\n"); 2035 break; 2036 case 0x49: 2037 if (CPUID_TO_FAMILY(cpu_id) == 0xf && 2038 CPUID_TO_MODEL(cpu_id) == 0x6) 2039 printf("3rd-level cache: 4MB, 16-way set associative, 64-byte line size\n"); 2040 else 2041 printf("2nd-level cache: 4 MByte, 16-way set associative, 64 byte line size"); 2042 break; 2043 case 0x4a: 2044 printf("3rd-level cache: 6MByte, 12-way set associative, 64 byte line size\n"); 2045 break; 2046 case 0x4b: 2047 printf("3rd-level cache: 8MByte, 16-way set associative, 64 byte line size\n"); 2048 break; 2049 case 0x4c: 2050 printf("3rd-level cache: 12MByte, 12-way set associative, 64 byte line size\n"); 2051 break; 2052 case 0x4d: 2053 printf("3rd-level cache: 16MByte, 16-way set associative, 64 byte line size\n"); 2054 break; 2055 case 0x4e: 2056 printf("2nd-level cache: 6MByte, 24-way set associative, 64 byte line size\n"); 2057 break; 2058 case 0x4f: 2059 printf("Instruction TLB: 4 KByte pages, 32 entries\n"); 2060 break; 2061 case 0x50: 2062 printf("Instruction TLB: 4 KB, 2 MB or 4 MB pages, fully associative, 64 entries\n"); 2063 break; 2064 case 0x51: 2065 printf("Instruction TLB: 4 KB, 2 MB or 4 MB pages, fully associative, 128 entries\n"); 2066 break; 2067 case 0x52: 2068 printf("Instruction TLB: 4 KB, 2 MB or 4 MB pages, fully associative, 256 entries\n"); 2069 break; 2070 case 0x55: 2071 printf("Instruction TLB: 2-MByte or 4-MByte pages, fully associative, 7 entries\n"); 2072 break; 2073 case 0x56: 2074 printf("Data TLB0: 4 MByte pages, 4-way set associative, 16 entries\n"); 2075 break; 2076 case 0x57: 2077 printf("Data TLB0: 4 KByte pages, 4-way associative, 16 entries\n"); 2078 break; 2079 case 0x59: 2080 printf("Data TLB0: 4 KByte pages, fully associative, 16 entries\n"); 2081 break; 2082 case 0x5a: 2083 printf("Data TLB0: 2-MByte or 4 MByte pages, 4-way set associative, 32 entries\n"); 2084 break; 2085 case 0x5b: 2086 printf("Data TLB: 4 KB or 4 MB pages, fully associative, 64 entries\n"); 2087 break; 2088 case 0x5c: 2089 printf("Data TLB: 4 KB or 4 MB pages, fully associative, 128 entries\n"); 2090 break; 2091 case 0x5d: 2092 printf("Data TLB: 4 KB or 4 MB pages, fully associative, 256 entries\n"); 2093 break; 2094 case 0x60: 2095 printf("1st-level data cache: 16 KB, 8-way set associative, sectored cache, 64 byte line size\n"); 2096 break; 2097 case 0x61: 2098 printf("Instruction TLB: 4 KByte pages, fully associative, 48 entries\n"); 2099 break; 2100 case 0x63: 2101 printf("Data TLB: 2 MByte or 4 MByte pages, 4-way set associative, 32 entries and a separate array with 1 GByte pages, 4-way set associative, 4 entries\n"); 2102 break; 2103 case 0x64: 2104 printf("Data TLB: 4 KBytes pages, 4-way set associative, 512 entries\n"); 2105 break; 2106 case 0x66: 2107 printf("1st-level data cache: 8 KB, 4-way set associative, sectored cache, 64 byte line size\n"); 2108 break; 2109 case 0x67: 2110 printf("1st-level data cache: 16 KB, 4-way set associative, sectored cache, 64 byte line size\n"); 2111 break; 2112 case 0x68: 2113 printf("1st-level data cache: 32 KB, 4 way set associative, sectored cache, 64 byte line size\n"); 2114 break; 2115 case 0x6a: 2116 printf("uTLB: 4KByte pages, 8-way set associative, 64 entries\n"); 2117 break; 2118 case 0x6b: 2119 printf("DTLB: 4KByte pages, 8-way set associative, 256 entries\n"); 2120 break; 2121 case 0x6c: 2122 printf("DTLB: 2M/4M pages, 8-way set associative, 128 entries\n"); 2123 break; 2124 case 0x6d: 2125 printf("DTLB: 1 GByte pages, fully associative, 16 entries\n"); 2126 break; 2127 case 0x70: 2128 printf("Trace cache: 12K-uops, 8-way set associative\n"); 2129 break; 2130 case 0x71: 2131 printf("Trace cache: 16K-uops, 8-way set associative\n"); 2132 break; 2133 case 0x72: 2134 printf("Trace cache: 32K-uops, 8-way set associative\n"); 2135 break; 2136 case 0x76: 2137 printf("Instruction TLB: 2M/4M pages, fully associative, 8 entries\n"); 2138 break; 2139 case 0x78: 2140 printf("2nd-level cache: 1 MB, 4-way set associative, 64-byte line size\n"); 2141 break; 2142 case 0x79: 2143 printf("2nd-level cache: 128 KB, 8-way set associative, sectored cache, 64 byte line size\n"); 2144 break; 2145 case 0x7a: 2146 printf("2nd-level cache: 256 KB, 8-way set associative, sectored cache, 64 byte line size\n"); 2147 break; 2148 case 0x7b: 2149 printf("2nd-level cache: 512 KB, 8-way set associative, sectored cache, 64 byte line size\n"); 2150 break; 2151 case 0x7c: 2152 printf("2nd-level cache: 1 MB, 8-way set associative, sectored cache, 64 byte line size\n"); 2153 break; 2154 case 0x7d: 2155 printf("2nd-level cache: 2-MB, 8-way set associative, 64-byte line size\n"); 2156 break; 2157 case 0x7f: 2158 printf("2nd-level cache: 512-KB, 2-way set associative, 64-byte line size\n"); 2159 break; 2160 case 0x80: 2161 printf("2nd-level cache: 512 KByte, 8-way set associative, 64-byte line size\n"); 2162 break; 2163 case 0x82: 2164 printf("2nd-level cache: 256 KB, 8-way set associative, 32 byte line size\n"); 2165 break; 2166 case 0x83: 2167 printf("2nd-level cache: 512 KB, 8-way set associative, 32 byte line size\n"); 2168 break; 2169 case 0x84: 2170 printf("2nd-level cache: 1 MB, 8-way set associative, 32 byte line size\n"); 2171 break; 2172 case 0x85: 2173 printf("2nd-level cache: 2 MB, 8-way set associative, 32 byte line size\n"); 2174 break; 2175 case 0x86: 2176 printf("2nd-level cache: 512 KB, 4-way set associative, 64 byte line size\n"); 2177 break; 2178 case 0x87: 2179 printf("2nd-level cache: 1 MB, 8-way set associative, 64 byte line size\n"); 2180 break; 2181 case 0xa0: 2182 printf("DTLB: 4k pages, fully associative, 32 entries\n"); 2183 break; 2184 case 0xb0: 2185 printf("Instruction TLB: 4 KB Pages, 4-way set associative, 128 entries\n"); 2186 break; 2187 case 0xb1: 2188 printf("Instruction TLB: 2M pages, 4-way, 8 entries or 4M pages, 4-way, 4 entries\n"); 2189 break; 2190 case 0xb2: 2191 printf("Instruction TLB: 4KByte pages, 4-way set associative, 64 entries\n"); 2192 break; 2193 case 0xb3: 2194 printf("Data TLB: 4 KB Pages, 4-way set associative, 128 entries\n"); 2195 break; 2196 case 0xb4: 2197 printf("Data TLB1: 4 KByte pages, 4-way associative, 256 entries\n"); 2198 break; 2199 case 0xb5: 2200 printf("Instruction TLB: 4KByte pages, 8-way set associative, 64 entries\n"); 2201 break; 2202 case 0xb6: 2203 printf("Instruction TLB: 4KByte pages, 8-way set associative, 128 entries\n"); 2204 break; 2205 case 0xba: 2206 printf("Data TLB1: 4 KByte pages, 4-way associative, 64 entries\n"); 2207 break; 2208 case 0xc0: 2209 printf("Data TLB: 4 KByte and 4 MByte pages, 4-way associative, 8 entries\n"); 2210 break; 2211 case 0xc1: 2212 printf("Shared 2nd-Level TLB: 4 KByte/2MByte pages, 8-way associative, 1024 entries\n"); 2213 break; 2214 case 0xc2: 2215 printf("DTLB: 4 KByte/2 MByte pages, 4-way associative, 16 entries\n"); 2216 break; 2217 case 0xc3: 2218 printf("Shared 2nd-Level TLB: 4 KByte /2 MByte pages, 6-way associative, 1536 entries. Also 1GBbyte pages, 4-way, 16 entries\n"); 2219 break; 2220 case 0xc4: 2221 printf("DTLB: 2M/4M Byte pages, 4-way associative, 32 entries\n"); 2222 break; 2223 case 0xca: 2224 printf("Shared 2nd-Level TLB: 4 KByte pages, 4-way associative, 512 entries\n"); 2225 break; 2226 case 0xd0: 2227 printf("3rd-level cache: 512 KByte, 4-way set associative, 64 byte line size\n"); 2228 break; 2229 case 0xd1: 2230 printf("3rd-level cache: 1 MByte, 4-way set associative, 64 byte line size\n"); 2231 break; 2232 case 0xd2: 2233 printf("3rd-level cache: 2 MByte, 4-way set associative, 64 byte line size\n"); 2234 break; 2235 case 0xd6: 2236 printf("3rd-level cache: 1 MByte, 8-way set associative, 64 byte line size\n"); 2237 break; 2238 case 0xd7: 2239 printf("3rd-level cache: 2 MByte, 8-way set associative, 64 byte line size\n"); 2240 break; 2241 case 0xd8: 2242 printf("3rd-level cache: 4 MByte, 8-way set associative, 64 byte line size\n"); 2243 break; 2244 case 0xdc: 2245 printf("3rd-level cache: 1.5 MByte, 12-way set associative, 64 byte line size\n"); 2246 break; 2247 case 0xdd: 2248 printf("3rd-level cache: 3 MByte, 12-way set associative, 64 byte line size\n"); 2249 break; 2250 case 0xde: 2251 printf("3rd-level cache: 6 MByte, 12-way set associative, 64 byte line size\n"); 2252 break; 2253 case 0xe2: 2254 printf("3rd-level cache: 2 MByte, 16-way set associative, 64 byte line size\n"); 2255 break; 2256 case 0xe3: 2257 printf("3rd-level cache: 4 MByte, 16-way set associative, 64 byte line size\n"); 2258 break; 2259 case 0xe4: 2260 printf("3rd-level cache: 8 MByte, 16-way set associative, 64 byte line size\n"); 2261 break; 2262 case 0xea: 2263 printf("3rd-level cache: 12MByte, 24-way set associative, 64 byte line size\n"); 2264 break; 2265 case 0xeb: 2266 printf("3rd-level cache: 18MByte, 24-way set associative, 64 byte line size\n"); 2267 break; 2268 case 0xec: 2269 printf("3rd-level cache: 24MByte, 24-way set associative, 64 byte line size\n"); 2270 break; 2271 case 0xf0: 2272 printf("64-Byte prefetching\n"); 2273 break; 2274 case 0xf1: 2275 printf("128-Byte prefetching\n"); 2276 break; 2277 } 2278 } 2279 2280 static void 2281 print_svm_info(void) 2282 { 2283 u_int features, regs[4]; 2284 uint64_t msr; 2285 int comma; 2286 2287 printf("\n SVM: "); 2288 do_cpuid(0x8000000A, regs); 2289 features = regs[3]; 2290 2291 msr = rdmsr(MSR_VM_CR); 2292 if ((msr & VM_CR_SVMDIS) == VM_CR_SVMDIS) 2293 printf("(disabled in BIOS) "); 2294 2295 if (!bootverbose) { 2296 comma = 0; 2297 if (features & (1 << 0)) { 2298 printf("%sNP", comma ? "," : ""); 2299 comma = 1; 2300 } 2301 if (features & (1 << 3)) { 2302 printf("%sNRIP", comma ? "," : ""); 2303 comma = 1; 2304 } 2305 if (features & (1 << 5)) { 2306 printf("%sVClean", comma ? "," : ""); 2307 comma = 1; 2308 } 2309 if (features & (1 << 6)) { 2310 printf("%sAFlush", comma ? "," : ""); 2311 comma = 1; 2312 } 2313 if (features & (1 << 7)) { 2314 printf("%sDAssist", comma ? "," : ""); 2315 comma = 1; 2316 } 2317 printf("%sNAsids=%d", comma ? "," : "", regs[1]); 2318 return; 2319 } 2320 2321 printf("Features=0x%b", features, 2322 "\020" 2323 "\001NP" /* Nested paging */ 2324 "\002LbrVirt" /* LBR virtualization */ 2325 "\003SVML" /* SVM lock */ 2326 "\004NRIPS" /* NRIP save */ 2327 "\005TscRateMsr" /* MSR based TSC rate control */ 2328 "\006VmcbClean" /* VMCB clean bits */ 2329 "\007FlushByAsid" /* Flush by ASID */ 2330 "\010DecodeAssist" /* Decode assist */ 2331 "\011<b8>" 2332 "\012<b9>" 2333 "\013PauseFilter" /* PAUSE intercept filter */ 2334 "\014EncryptedMcodePatch" 2335 "\015PauseFilterThreshold" /* PAUSE filter threshold */ 2336 "\016AVIC" /* virtual interrupt controller */ 2337 "\017<b14>" 2338 "\020V_VMSAVE_VMLOAD" 2339 "\021vGIF" 2340 "\022GMET" /* Guest Mode Execute Trap */ 2341 "\023<b18>" 2342 "\024<b19>" 2343 "\025GuesSpecCtl" /* Guest Spec_ctl */ 2344 "\026<b21>" 2345 "\027<b22>" 2346 "\030<b23>" 2347 "\031<b24>" 2348 "\032<b25>" 2349 "\033<b26>" 2350 "\034<b27>" 2351 "\035<b28>" 2352 "\036<b29>" 2353 "\037<b30>" 2354 "\040<b31>" 2355 ); 2356 printf("\nRevision=%d, ASIDs=%d", regs[0] & 0xff, regs[1]); 2357 } 2358 2359 #ifdef __i386__ 2360 static void 2361 print_transmeta_info(void) 2362 { 2363 u_int regs[4], nreg = 0; 2364 2365 do_cpuid(0x80860000, regs); 2366 nreg = regs[0]; 2367 if (nreg >= 0x80860001) { 2368 do_cpuid(0x80860001, regs); 2369 printf(" Processor revision %u.%u.%u.%u\n", 2370 (regs[1] >> 24) & 0xff, 2371 (regs[1] >> 16) & 0xff, 2372 (regs[1] >> 8) & 0xff, 2373 regs[1] & 0xff); 2374 } 2375 if (nreg >= 0x80860002) { 2376 do_cpuid(0x80860002, regs); 2377 printf(" Code Morphing Software revision %u.%u.%u-%u-%u\n", 2378 (regs[1] >> 24) & 0xff, 2379 (regs[1] >> 16) & 0xff, 2380 (regs[1] >> 8) & 0xff, 2381 regs[1] & 0xff, 2382 regs[2]); 2383 } 2384 if (nreg >= 0x80860006) { 2385 char info[65]; 2386 do_cpuid(0x80860003, (u_int*) &info[0]); 2387 do_cpuid(0x80860004, (u_int*) &info[16]); 2388 do_cpuid(0x80860005, (u_int*) &info[32]); 2389 do_cpuid(0x80860006, (u_int*) &info[48]); 2390 info[64] = 0; 2391 printf(" %s\n", info); 2392 } 2393 } 2394 #endif 2395 2396 static void 2397 print_via_padlock_info(void) 2398 { 2399 u_int regs[4]; 2400 2401 do_cpuid(0xc0000001, regs); 2402 printf("\n VIA Padlock Features=0x%b", regs[3], 2403 "\020" 2404 "\003RNG" /* RNG */ 2405 "\007AES" /* ACE */ 2406 "\011AES-CTR" /* ACE2 */ 2407 "\013SHA1,SHA256" /* PHE */ 2408 "\015RSA" /* PMM */ 2409 ); 2410 } 2411 2412 static uint32_t 2413 vmx_settable(uint64_t basic, int msr, int true_msr) 2414 { 2415 uint64_t val; 2416 2417 if (basic & (1ULL << 55)) 2418 val = rdmsr(true_msr); 2419 else 2420 val = rdmsr(msr); 2421 2422 /* Just report the controls that can be set to 1. */ 2423 return (val >> 32); 2424 } 2425 2426 static void 2427 print_vmx_info(void) 2428 { 2429 uint64_t basic, msr; 2430 uint32_t entry, exit, mask, pin, proc, proc2; 2431 int comma; 2432 2433 printf("\n VT-x: "); 2434 msr = rdmsr(MSR_IA32_FEATURE_CONTROL); 2435 if (!(msr & IA32_FEATURE_CONTROL_VMX_EN)) 2436 printf("(disabled in BIOS) "); 2437 basic = rdmsr(MSR_VMX_BASIC); 2438 pin = vmx_settable(basic, MSR_VMX_PINBASED_CTLS, 2439 MSR_VMX_TRUE_PINBASED_CTLS); 2440 proc = vmx_settable(basic, MSR_VMX_PROCBASED_CTLS, 2441 MSR_VMX_TRUE_PROCBASED_CTLS); 2442 if (proc & PROCBASED_SECONDARY_CONTROLS) 2443 proc2 = vmx_settable(basic, MSR_VMX_PROCBASED_CTLS2, 2444 MSR_VMX_PROCBASED_CTLS2); 2445 else 2446 proc2 = 0; 2447 exit = vmx_settable(basic, MSR_VMX_EXIT_CTLS, MSR_VMX_TRUE_EXIT_CTLS); 2448 entry = vmx_settable(basic, MSR_VMX_ENTRY_CTLS, MSR_VMX_TRUE_ENTRY_CTLS); 2449 2450 if (!bootverbose) { 2451 comma = 0; 2452 if (exit & VM_EXIT_SAVE_PAT && exit & VM_EXIT_LOAD_PAT && 2453 entry & VM_ENTRY_LOAD_PAT) { 2454 printf("%sPAT", comma ? "," : ""); 2455 comma = 1; 2456 } 2457 if (proc & PROCBASED_HLT_EXITING) { 2458 printf("%sHLT", comma ? "," : ""); 2459 comma = 1; 2460 } 2461 if (proc & PROCBASED_MTF) { 2462 printf("%sMTF", comma ? "," : ""); 2463 comma = 1; 2464 } 2465 if (proc & PROCBASED_PAUSE_EXITING) { 2466 printf("%sPAUSE", comma ? "," : ""); 2467 comma = 1; 2468 } 2469 if (proc2 & PROCBASED2_ENABLE_EPT) { 2470 printf("%sEPT", comma ? "," : ""); 2471 comma = 1; 2472 } 2473 if (proc2 & PROCBASED2_UNRESTRICTED_GUEST) { 2474 printf("%sUG", comma ? "," : ""); 2475 comma = 1; 2476 } 2477 if (proc2 & PROCBASED2_ENABLE_VPID) { 2478 printf("%sVPID", comma ? "," : ""); 2479 comma = 1; 2480 } 2481 if (proc & PROCBASED_USE_TPR_SHADOW && 2482 proc2 & PROCBASED2_VIRTUALIZE_APIC_ACCESSES && 2483 proc2 & PROCBASED2_VIRTUALIZE_X2APIC_MODE && 2484 proc2 & PROCBASED2_APIC_REGISTER_VIRTUALIZATION && 2485 proc2 & PROCBASED2_VIRTUAL_INTERRUPT_DELIVERY) { 2486 printf("%sVID", comma ? "," : ""); 2487 comma = 1; 2488 if (pin & PINBASED_POSTED_INTERRUPT) 2489 printf(",PostIntr"); 2490 } 2491 return; 2492 } 2493 2494 mask = basic >> 32; 2495 printf("Basic Features=0x%b", mask, 2496 "\020" 2497 "\02132PA" /* 32-bit physical addresses */ 2498 "\022SMM" /* SMM dual-monitor */ 2499 "\027INS/OUTS" /* VM-exit info for INS and OUTS */ 2500 "\030TRUE" /* TRUE_CTLS MSRs */ 2501 ); 2502 printf("\n Pin-Based Controls=0x%b", pin, 2503 "\020" 2504 "\001ExtINT" /* External-interrupt exiting */ 2505 "\004NMI" /* NMI exiting */ 2506 "\006VNMI" /* Virtual NMIs */ 2507 "\007PreTmr" /* Activate VMX-preemption timer */ 2508 "\010PostIntr" /* Process posted interrupts */ 2509 ); 2510 printf("\n Primary Processor Controls=0x%b", proc, 2511 "\020" 2512 "\003INTWIN" /* Interrupt-window exiting */ 2513 "\004TSCOff" /* Use TSC offsetting */ 2514 "\010HLT" /* HLT exiting */ 2515 "\012INVLPG" /* INVLPG exiting */ 2516 "\013MWAIT" /* MWAIT exiting */ 2517 "\014RDPMC" /* RDPMC exiting */ 2518 "\015RDTSC" /* RDTSC exiting */ 2519 "\020CR3-LD" /* CR3-load exiting */ 2520 "\021CR3-ST" /* CR3-store exiting */ 2521 "\024CR8-LD" /* CR8-load exiting */ 2522 "\025CR8-ST" /* CR8-store exiting */ 2523 "\026TPR" /* Use TPR shadow */ 2524 "\027NMIWIN" /* NMI-window exiting */ 2525 "\030MOV-DR" /* MOV-DR exiting */ 2526 "\031IO" /* Unconditional I/O exiting */ 2527 "\032IOmap" /* Use I/O bitmaps */ 2528 "\034MTF" /* Monitor trap flag */ 2529 "\035MSRmap" /* Use MSR bitmaps */ 2530 "\036MONITOR" /* MONITOR exiting */ 2531 "\037PAUSE" /* PAUSE exiting */ 2532 ); 2533 if (proc & PROCBASED_SECONDARY_CONTROLS) 2534 printf("\n Secondary Processor Controls=0x%b", proc2, 2535 "\020" 2536 "\001APIC" /* Virtualize APIC accesses */ 2537 "\002EPT" /* Enable EPT */ 2538 "\003DT" /* Descriptor-table exiting */ 2539 "\004RDTSCP" /* Enable RDTSCP */ 2540 "\005x2APIC" /* Virtualize x2APIC mode */ 2541 "\006VPID" /* Enable VPID */ 2542 "\007WBINVD" /* WBINVD exiting */ 2543 "\010UG" /* Unrestricted guest */ 2544 "\011APIC-reg" /* APIC-register virtualization */ 2545 "\012VID" /* Virtual-interrupt delivery */ 2546 "\013PAUSE-loop" /* PAUSE-loop exiting */ 2547 "\014RDRAND" /* RDRAND exiting */ 2548 "\015INVPCID" /* Enable INVPCID */ 2549 "\016VMFUNC" /* Enable VM functions */ 2550 "\017VMCS" /* VMCS shadowing */ 2551 "\020EPT#VE" /* EPT-violation #VE */ 2552 "\021XSAVES" /* Enable XSAVES/XRSTORS */ 2553 ); 2554 printf("\n Exit Controls=0x%b", mask, 2555 "\020" 2556 "\003DR" /* Save debug controls */ 2557 /* Ignore Host address-space size */ 2558 "\015PERF" /* Load MSR_PERF_GLOBAL_CTRL */ 2559 "\020AckInt" /* Acknowledge interrupt on exit */ 2560 "\023PAT-SV" /* Save MSR_PAT */ 2561 "\024PAT-LD" /* Load MSR_PAT */ 2562 "\025EFER-SV" /* Save MSR_EFER */ 2563 "\026EFER-LD" /* Load MSR_EFER */ 2564 "\027PTMR-SV" /* Save VMX-preemption timer value */ 2565 ); 2566 printf("\n Entry Controls=0x%b", mask, 2567 "\020" 2568 "\003DR" /* Save debug controls */ 2569 /* Ignore IA-32e mode guest */ 2570 /* Ignore Entry to SMM */ 2571 /* Ignore Deactivate dual-monitor treatment */ 2572 "\016PERF" /* Load MSR_PERF_GLOBAL_CTRL */ 2573 "\017PAT" /* Load MSR_PAT */ 2574 "\020EFER" /* Load MSR_EFER */ 2575 ); 2576 if (proc & PROCBASED_SECONDARY_CONTROLS && 2577 (proc2 & (PROCBASED2_ENABLE_EPT | PROCBASED2_ENABLE_VPID)) != 0) { 2578 msr = rdmsr(MSR_VMX_EPT_VPID_CAP); 2579 mask = msr; 2580 printf("\n EPT Features=0x%b", mask, 2581 "\020" 2582 "\001XO" /* Execute-only translations */ 2583 "\007PW4" /* Page-walk length of 4 */ 2584 "\011UC" /* EPT paging-structure mem can be UC */ 2585 "\017WB" /* EPT paging-structure mem can be WB */ 2586 "\0212M" /* EPT PDE can map a 2-Mbyte page */ 2587 "\0221G" /* EPT PDPTE can map a 1-Gbyte page */ 2588 "\025INVEPT" /* INVEPT is supported */ 2589 "\026AD" /* Accessed and dirty flags for EPT */ 2590 "\032single" /* INVEPT single-context type */ 2591 "\033all" /* INVEPT all-context type */ 2592 ); 2593 mask = msr >> 32; 2594 printf("\n VPID Features=0x%b", mask, 2595 "\020" 2596 "\001INVVPID" /* INVVPID is supported */ 2597 "\011individual" /* INVVPID individual-address type */ 2598 "\012single" /* INVVPID single-context type */ 2599 "\013all" /* INVVPID all-context type */ 2600 /* INVVPID single-context-retaining-globals type */ 2601 "\014single-globals" 2602 ); 2603 } 2604 } 2605 2606 static void 2607 print_hypervisor_info(void) 2608 { 2609 2610 if (*hv_vendor != '\0') 2611 printf("Hypervisor: Origin = \"%s\"\n", hv_vendor); 2612 } 2613 2614 /* 2615 * Returns the maximum physical address that can be used with the 2616 * current system. 2617 */ 2618 vm_paddr_t 2619 cpu_getmaxphyaddr(void) 2620 { 2621 2622 #if defined(__i386__) 2623 if (!pae_mode) 2624 return (0xffffffff); 2625 #endif 2626 return ((1ULL << cpu_maxphyaddr) - 1); 2627 } 2628