1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD 3 * 4 * Copyright (c) 2003 John Baldwin <jhb@FreeBSD.org> 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 25 * SUCH DAMAGE. 26 */ 27 28 #include <sys/cdefs.h> 29 __FBSDID("$FreeBSD$"); 30 31 #include "opt_acpi.h" 32 #include "opt_isa.h" 33 34 #include <sys/param.h> 35 #include <sys/systm.h> 36 #include <sys/bus.h> 37 #include <sys/kernel.h> 38 #include <sys/lock.h> 39 #include <sys/malloc.h> 40 #include <sys/module.h> 41 #include <sys/mutex.h> 42 #include <sys/rman.h> 43 #include <sys/sysctl.h> 44 45 #include <dev/pci/pcireg.h> 46 #include <dev/pci/pcivar.h> 47 48 #include <vm/vm.h> 49 #include <vm/pmap.h> 50 51 #include <x86/apicreg.h> 52 #include <machine/frame.h> 53 #include <machine/intr_machdep.h> 54 #include <x86/apicvar.h> 55 #include <machine/resource.h> 56 #include <machine/segments.h> 57 #include <x86/iommu/iommu_intrmap.h> 58 59 #define IOAPIC_ISA_INTS 16 60 #define IOAPIC_MEM_REGION 32 61 #define IOAPIC_REDTBL_LO(i) (IOAPIC_REDTBL + (i) * 2) 62 #define IOAPIC_REDTBL_HI(i) (IOAPIC_REDTBL_LO(i) + 1) 63 64 static MALLOC_DEFINE(M_IOAPIC, "io_apic", "I/O APIC structures"); 65 66 /* 67 * I/O APIC interrupt source driver. Each pin is assigned an IRQ cookie 68 * as laid out in the ACPI System Interrupt number model where each I/O 69 * APIC has a contiguous chunk of the System Interrupt address space. 70 * We assume that IRQs 1 - 15 behave like ISA IRQs and that all other 71 * IRQs behave as PCI IRQs by default. We also assume that the pin for 72 * IRQ 0 is actually an ExtINT pin. The apic enumerators override the 73 * configuration of individual pins as indicated by their tables. 74 * 75 * Documentation for the I/O APIC: "82093AA I/O Advanced Programmable 76 * Interrupt Controller (IOAPIC)", May 1996, Intel Corp. 77 * ftp://download.intel.com/design/chipsets/datashts/29056601.pdf 78 */ 79 80 struct ioapic_intsrc { 81 struct intsrc io_intsrc; 82 int io_irq; 83 u_int io_intpin:8; 84 u_int io_vector:8; 85 u_int io_cpu; 86 u_int io_activehi:1; 87 u_int io_edgetrigger:1; 88 u_int io_masked:1; 89 int io_bus:4; 90 uint32_t io_lowreg; 91 u_int io_remap_cookie; 92 }; 93 94 struct ioapic { 95 struct pic io_pic; 96 u_int io_id:8; /* logical ID */ 97 u_int io_apic_id:4; 98 u_int io_intbase:8; /* System Interrupt base */ 99 u_int io_numintr:8; 100 u_int io_haseoi:1; 101 volatile ioapic_t *io_addr; /* XXX: should use bus_space */ 102 vm_paddr_t io_paddr; 103 STAILQ_ENTRY(ioapic) io_next; 104 device_t pci_dev; /* matched pci device, if found */ 105 struct resource *pci_wnd; /* BAR 0, should be same or alias to 106 io_paddr */ 107 struct ioapic_intsrc io_pins[0]; 108 }; 109 110 static u_int ioapic_read(volatile ioapic_t *apic, int reg); 111 static void ioapic_write(volatile ioapic_t *apic, int reg, u_int val); 112 static const char *ioapic_bus_string(int bus_type); 113 static void ioapic_print_irq(struct ioapic_intsrc *intpin); 114 static void ioapic_register_sources(struct pic *pic); 115 static void ioapic_enable_source(struct intsrc *isrc); 116 static void ioapic_disable_source(struct intsrc *isrc, int eoi); 117 static void ioapic_eoi_source(struct intsrc *isrc); 118 static void ioapic_enable_intr(struct intsrc *isrc); 119 static void ioapic_disable_intr(struct intsrc *isrc); 120 static int ioapic_vector(struct intsrc *isrc); 121 static int ioapic_source_pending(struct intsrc *isrc); 122 static int ioapic_config_intr(struct intsrc *isrc, enum intr_trigger trig, 123 enum intr_polarity pol); 124 static void ioapic_resume(struct pic *pic, bool suspend_cancelled); 125 static int ioapic_assign_cpu(struct intsrc *isrc, u_int apic_id); 126 static void ioapic_program_intpin(struct ioapic_intsrc *intpin); 127 static void ioapic_reprogram_intpin(struct intsrc *isrc); 128 129 static STAILQ_HEAD(,ioapic) ioapic_list = STAILQ_HEAD_INITIALIZER(ioapic_list); 130 struct pic ioapic_template = { 131 .pic_register_sources = ioapic_register_sources, 132 .pic_enable_source = ioapic_enable_source, 133 .pic_disable_source = ioapic_disable_source, 134 .pic_eoi_source = ioapic_eoi_source, 135 .pic_enable_intr = ioapic_enable_intr, 136 .pic_disable_intr = ioapic_disable_intr, 137 .pic_vector = ioapic_vector, 138 .pic_source_pending = ioapic_source_pending, 139 .pic_suspend = NULL, 140 .pic_resume = ioapic_resume, 141 .pic_config_intr = ioapic_config_intr, 142 .pic_assign_cpu = ioapic_assign_cpu, 143 .pic_reprogram_pin = ioapic_reprogram_intpin, 144 }; 145 146 static u_int next_ioapic_base; 147 static u_int next_id; 148 149 static int enable_extint; 150 SYSCTL_INT(_hw_apic, OID_AUTO, enable_extint, CTLFLAG_RDTUN, &enable_extint, 0, 151 "Enable the ExtINT pin in the first I/O APIC"); 152 153 static void 154 _ioapic_eoi_source(struct intsrc *isrc, int locked) 155 { 156 struct ioapic_intsrc *src; 157 struct ioapic *io; 158 volatile uint32_t *apic_eoi; 159 uint32_t low1; 160 161 lapic_eoi(); 162 if (!lapic_eoi_suppression) 163 return; 164 src = (struct ioapic_intsrc *)isrc; 165 if (src->io_edgetrigger) 166 return; 167 io = (struct ioapic *)isrc->is_pic; 168 169 /* 170 * Handle targeted EOI for level-triggered pins, if broadcast 171 * EOI suppression is supported by LAPICs. 172 */ 173 if (io->io_haseoi) { 174 /* 175 * If IOAPIC has EOI Register, simply write vector 176 * number into the reg. 177 */ 178 apic_eoi = (volatile uint32_t *)((volatile char *) 179 io->io_addr + IOAPIC_EOIR); 180 *apic_eoi = src->io_vector; 181 } else { 182 /* 183 * Otherwise, if IO-APIC is too old to provide EOIR, 184 * do what Intel did for the Linux kernel. Temporary 185 * switch the pin to edge-trigger and back, masking 186 * the pin during the trick. 187 */ 188 if (!locked) 189 mtx_lock_spin(&icu_lock); 190 low1 = src->io_lowreg; 191 low1 &= ~IOART_TRGRLVL; 192 low1 |= IOART_TRGREDG | IOART_INTMSET; 193 ioapic_write(io->io_addr, IOAPIC_REDTBL_LO(src->io_intpin), 194 low1); 195 ioapic_write(io->io_addr, IOAPIC_REDTBL_LO(src->io_intpin), 196 src->io_lowreg); 197 if (!locked) 198 mtx_unlock_spin(&icu_lock); 199 } 200 } 201 202 static u_int 203 ioapic_read(volatile ioapic_t *apic, int reg) 204 { 205 206 mtx_assert(&icu_lock, MA_OWNED); 207 apic->ioregsel = reg; 208 return (apic->iowin); 209 } 210 211 static void 212 ioapic_write(volatile ioapic_t *apic, int reg, u_int val) 213 { 214 215 mtx_assert(&icu_lock, MA_OWNED); 216 apic->ioregsel = reg; 217 apic->iowin = val; 218 } 219 220 static const char * 221 ioapic_bus_string(int bus_type) 222 { 223 224 switch (bus_type) { 225 case APIC_BUS_ISA: 226 return ("ISA"); 227 case APIC_BUS_EISA: 228 return ("EISA"); 229 case APIC_BUS_PCI: 230 return ("PCI"); 231 default: 232 return ("unknown"); 233 } 234 } 235 236 static void 237 ioapic_print_irq(struct ioapic_intsrc *intpin) 238 { 239 240 switch (intpin->io_irq) { 241 case IRQ_DISABLED: 242 printf("disabled"); 243 break; 244 case IRQ_EXTINT: 245 printf("ExtINT"); 246 break; 247 case IRQ_NMI: 248 printf("NMI"); 249 break; 250 case IRQ_SMI: 251 printf("SMI"); 252 break; 253 default: 254 printf("%s IRQ %d", ioapic_bus_string(intpin->io_bus), 255 intpin->io_irq); 256 } 257 } 258 259 static void 260 ioapic_enable_source(struct intsrc *isrc) 261 { 262 struct ioapic_intsrc *intpin = (struct ioapic_intsrc *)isrc; 263 struct ioapic *io = (struct ioapic *)isrc->is_pic; 264 uint32_t flags; 265 266 mtx_lock_spin(&icu_lock); 267 if (intpin->io_masked) { 268 flags = intpin->io_lowreg & ~IOART_INTMASK; 269 ioapic_write(io->io_addr, IOAPIC_REDTBL_LO(intpin->io_intpin), 270 flags); 271 intpin->io_masked = 0; 272 } 273 mtx_unlock_spin(&icu_lock); 274 } 275 276 static void 277 ioapic_disable_source(struct intsrc *isrc, int eoi) 278 { 279 struct ioapic_intsrc *intpin = (struct ioapic_intsrc *)isrc; 280 struct ioapic *io = (struct ioapic *)isrc->is_pic; 281 uint32_t flags; 282 283 mtx_lock_spin(&icu_lock); 284 if (!intpin->io_masked && !intpin->io_edgetrigger) { 285 flags = intpin->io_lowreg | IOART_INTMSET; 286 ioapic_write(io->io_addr, IOAPIC_REDTBL_LO(intpin->io_intpin), 287 flags); 288 intpin->io_masked = 1; 289 } 290 291 if (eoi == PIC_EOI) 292 _ioapic_eoi_source(isrc, 1); 293 294 mtx_unlock_spin(&icu_lock); 295 } 296 297 static void 298 ioapic_eoi_source(struct intsrc *isrc) 299 { 300 301 _ioapic_eoi_source(isrc, 0); 302 } 303 304 /* 305 * Completely program an intpin based on the data in its interrupt source 306 * structure. 307 */ 308 static void 309 ioapic_program_intpin(struct ioapic_intsrc *intpin) 310 { 311 struct ioapic *io = (struct ioapic *)intpin->io_intsrc.is_pic; 312 uint32_t low, high; 313 #ifdef ACPI_DMAR 314 int error; 315 #endif 316 317 /* 318 * If a pin is completely invalid or if it is valid but hasn't 319 * been enabled yet, just ensure that the pin is masked. 320 */ 321 mtx_assert(&icu_lock, MA_OWNED); 322 if (intpin->io_irq == IRQ_DISABLED || (intpin->io_irq >= 0 && 323 intpin->io_vector == 0)) { 324 low = ioapic_read(io->io_addr, 325 IOAPIC_REDTBL_LO(intpin->io_intpin)); 326 if ((low & IOART_INTMASK) == IOART_INTMCLR) 327 ioapic_write(io->io_addr, 328 IOAPIC_REDTBL_LO(intpin->io_intpin), 329 low | IOART_INTMSET); 330 #ifdef ACPI_DMAR 331 mtx_unlock_spin(&icu_lock); 332 iommu_unmap_ioapic_intr(io->io_apic_id, 333 &intpin->io_remap_cookie); 334 mtx_lock_spin(&icu_lock); 335 #endif 336 return; 337 } 338 339 #ifdef ACPI_DMAR 340 mtx_unlock_spin(&icu_lock); 341 error = iommu_map_ioapic_intr(io->io_apic_id, 342 intpin->io_cpu, intpin->io_vector, intpin->io_edgetrigger, 343 intpin->io_activehi, intpin->io_irq, &intpin->io_remap_cookie, 344 &high, &low); 345 mtx_lock_spin(&icu_lock); 346 if (error == 0) { 347 ioapic_write(io->io_addr, IOAPIC_REDTBL_HI(intpin->io_intpin), 348 high); 349 intpin->io_lowreg = low; 350 ioapic_write(io->io_addr, IOAPIC_REDTBL_LO(intpin->io_intpin), 351 low); 352 return; 353 } else if (error != EOPNOTSUPP) { 354 return; 355 } 356 #endif 357 358 /* 359 * Set the destination. Note that with Intel interrupt remapping, 360 * the previously reserved bits 55:48 now have a purpose so ensure 361 * these are zero. 362 */ 363 low = IOART_DESTPHY; 364 high = intpin->io_cpu << APIC_ID_SHIFT; 365 366 /* Program the rest of the low word. */ 367 if (intpin->io_edgetrigger) 368 low |= IOART_TRGREDG; 369 else 370 low |= IOART_TRGRLVL; 371 if (intpin->io_activehi) 372 low |= IOART_INTAHI; 373 else 374 low |= IOART_INTALO; 375 if (intpin->io_masked) 376 low |= IOART_INTMSET; 377 switch (intpin->io_irq) { 378 case IRQ_EXTINT: 379 KASSERT(intpin->io_edgetrigger, 380 ("ExtINT not edge triggered")); 381 low |= IOART_DELEXINT; 382 break; 383 case IRQ_NMI: 384 KASSERT(intpin->io_edgetrigger, 385 ("NMI not edge triggered")); 386 low |= IOART_DELNMI; 387 break; 388 case IRQ_SMI: 389 KASSERT(intpin->io_edgetrigger, 390 ("SMI not edge triggered")); 391 low |= IOART_DELSMI; 392 break; 393 default: 394 KASSERT(intpin->io_vector != 0, ("No vector for IRQ %u", 395 intpin->io_irq)); 396 low |= IOART_DELFIXED | intpin->io_vector; 397 } 398 399 /* Write the values to the APIC. */ 400 ioapic_write(io->io_addr, IOAPIC_REDTBL_HI(intpin->io_intpin), high); 401 intpin->io_lowreg = low; 402 ioapic_write(io->io_addr, IOAPIC_REDTBL_LO(intpin->io_intpin), low); 403 } 404 405 static void 406 ioapic_reprogram_intpin(struct intsrc *isrc) 407 { 408 409 mtx_lock_spin(&icu_lock); 410 ioapic_program_intpin((struct ioapic_intsrc *)isrc); 411 mtx_unlock_spin(&icu_lock); 412 } 413 414 static int 415 ioapic_assign_cpu(struct intsrc *isrc, u_int apic_id) 416 { 417 struct ioapic_intsrc *intpin = (struct ioapic_intsrc *)isrc; 418 struct ioapic *io = (struct ioapic *)isrc->is_pic; 419 u_int old_vector, new_vector; 420 u_int old_id; 421 422 /* 423 * On Hyper-V: 424 * - Stick to the first cpu for all I/O APIC pins. 425 * - And don't allow destination cpu changes. 426 */ 427 if (vm_guest == VM_GUEST_HV) { 428 if (intpin->io_vector) 429 return (EINVAL); 430 else 431 apic_id = 0; 432 } 433 434 /* 435 * keep 1st core as the destination for NMI 436 */ 437 if (intpin->io_irq == IRQ_NMI) 438 apic_id = 0; 439 440 /* 441 * Set us up to free the old irq. 442 */ 443 old_vector = intpin->io_vector; 444 old_id = intpin->io_cpu; 445 if (old_vector && apic_id == old_id) 446 return (0); 447 448 /* 449 * Allocate an APIC vector for this interrupt pin. Once 450 * we have a vector we program the interrupt pin. 451 */ 452 new_vector = apic_alloc_vector(apic_id, intpin->io_irq); 453 if (new_vector == 0) 454 return (ENOSPC); 455 456 /* 457 * Mask the old intpin if it is enabled while it is migrated. 458 * 459 * At least some level-triggered interrupts seem to need the 460 * extra DELAY() to avoid being stuck in a non-EOI'd state. 461 */ 462 mtx_lock_spin(&icu_lock); 463 if (!intpin->io_masked && !intpin->io_edgetrigger) { 464 ioapic_write(io->io_addr, IOAPIC_REDTBL_LO(intpin->io_intpin), 465 intpin->io_lowreg | IOART_INTMSET); 466 mtx_unlock_spin(&icu_lock); 467 DELAY(100); 468 mtx_lock_spin(&icu_lock); 469 } 470 471 intpin->io_cpu = apic_id; 472 intpin->io_vector = new_vector; 473 if (isrc->is_handlers > 0) 474 apic_enable_vector(intpin->io_cpu, intpin->io_vector); 475 if (bootverbose) { 476 printf("ioapic%u: routing intpin %u (", io->io_id, 477 intpin->io_intpin); 478 ioapic_print_irq(intpin); 479 printf(") to lapic %u vector %u\n", intpin->io_cpu, 480 intpin->io_vector); 481 } 482 ioapic_program_intpin(intpin); 483 mtx_unlock_spin(&icu_lock); 484 485 /* 486 * Free the old vector after the new one is established. This is done 487 * to prevent races where we could miss an interrupt. 488 */ 489 if (old_vector) { 490 if (isrc->is_handlers > 0) 491 apic_disable_vector(old_id, old_vector); 492 apic_free_vector(old_id, old_vector, intpin->io_irq); 493 } 494 return (0); 495 } 496 497 static void 498 ioapic_enable_intr(struct intsrc *isrc) 499 { 500 struct ioapic_intsrc *intpin = (struct ioapic_intsrc *)isrc; 501 502 if (intpin->io_vector == 0) 503 if (ioapic_assign_cpu(isrc, intr_next_cpu(isrc->is_domain)) != 0) 504 panic("Couldn't find an APIC vector for IRQ %d", 505 intpin->io_irq); 506 apic_enable_vector(intpin->io_cpu, intpin->io_vector); 507 } 508 509 510 static void 511 ioapic_disable_intr(struct intsrc *isrc) 512 { 513 struct ioapic_intsrc *intpin = (struct ioapic_intsrc *)isrc; 514 u_int vector; 515 516 if (intpin->io_vector != 0) { 517 /* Mask this interrupt pin and free its APIC vector. */ 518 vector = intpin->io_vector; 519 apic_disable_vector(intpin->io_cpu, vector); 520 mtx_lock_spin(&icu_lock); 521 intpin->io_masked = 1; 522 intpin->io_vector = 0; 523 ioapic_program_intpin(intpin); 524 mtx_unlock_spin(&icu_lock); 525 apic_free_vector(intpin->io_cpu, vector, intpin->io_irq); 526 } 527 } 528 529 static int 530 ioapic_vector(struct intsrc *isrc) 531 { 532 struct ioapic_intsrc *pin; 533 534 pin = (struct ioapic_intsrc *)isrc; 535 return (pin->io_irq); 536 } 537 538 static int 539 ioapic_source_pending(struct intsrc *isrc) 540 { 541 struct ioapic_intsrc *intpin = (struct ioapic_intsrc *)isrc; 542 543 if (intpin->io_vector == 0) 544 return 0; 545 return (lapic_intr_pending(intpin->io_vector)); 546 } 547 548 static int 549 ioapic_config_intr(struct intsrc *isrc, enum intr_trigger trig, 550 enum intr_polarity pol) 551 { 552 struct ioapic_intsrc *intpin = (struct ioapic_intsrc *)isrc; 553 struct ioapic *io = (struct ioapic *)isrc->is_pic; 554 int changed; 555 556 KASSERT(!(trig == INTR_TRIGGER_CONFORM || pol == INTR_POLARITY_CONFORM), 557 ("%s: Conforming trigger or polarity\n", __func__)); 558 559 /* 560 * EISA interrupts always use active high polarity, so don't allow 561 * them to be set to active low. 562 * 563 * XXX: Should we write to the ELCR if the trigger mode changes for 564 * an EISA IRQ or an ISA IRQ with the ELCR present? 565 */ 566 mtx_lock_spin(&icu_lock); 567 if (intpin->io_bus == APIC_BUS_EISA) 568 pol = INTR_POLARITY_HIGH; 569 changed = 0; 570 if (intpin->io_edgetrigger != (trig == INTR_TRIGGER_EDGE)) { 571 if (bootverbose) 572 printf("ioapic%u: Changing trigger for pin %u to %s\n", 573 io->io_id, intpin->io_intpin, 574 trig == INTR_TRIGGER_EDGE ? "edge" : "level"); 575 intpin->io_edgetrigger = (trig == INTR_TRIGGER_EDGE); 576 changed++; 577 } 578 if (intpin->io_activehi != (pol == INTR_POLARITY_HIGH)) { 579 if (bootverbose) 580 printf("ioapic%u: Changing polarity for pin %u to %s\n", 581 io->io_id, intpin->io_intpin, 582 pol == INTR_POLARITY_HIGH ? "high" : "low"); 583 intpin->io_activehi = (pol == INTR_POLARITY_HIGH); 584 changed++; 585 } 586 if (changed) 587 ioapic_program_intpin(intpin); 588 mtx_unlock_spin(&icu_lock); 589 return (0); 590 } 591 592 static void 593 ioapic_resume(struct pic *pic, bool suspend_cancelled) 594 { 595 struct ioapic *io = (struct ioapic *)pic; 596 int i; 597 598 mtx_lock_spin(&icu_lock); 599 for (i = 0; i < io->io_numintr; i++) 600 ioapic_program_intpin(&io->io_pins[i]); 601 mtx_unlock_spin(&icu_lock); 602 } 603 604 /* 605 * Create a plain I/O APIC object. 606 */ 607 void * 608 ioapic_create(vm_paddr_t addr, int32_t apic_id, int intbase) 609 { 610 struct ioapic *io; 611 struct ioapic_intsrc *intpin; 612 volatile ioapic_t *apic; 613 u_int numintr, i; 614 uint32_t value; 615 616 /* Map the register window so we can access the device. */ 617 apic = pmap_mapdev(addr, IOAPIC_MEM_REGION); 618 mtx_lock_spin(&icu_lock); 619 value = ioapic_read(apic, IOAPIC_VER); 620 mtx_unlock_spin(&icu_lock); 621 622 /* If it's version register doesn't seem to work, punt. */ 623 if (value == 0xffffffff) { 624 pmap_unmapdev((vm_offset_t)apic, IOAPIC_MEM_REGION); 625 return (NULL); 626 } 627 628 /* Determine the number of vectors and set the APIC ID. */ 629 numintr = ((value & IOART_VER_MAXREDIR) >> MAXREDIRSHIFT) + 1; 630 io = malloc(sizeof(struct ioapic) + 631 numintr * sizeof(struct ioapic_intsrc), M_IOAPIC, M_WAITOK); 632 io->io_pic = ioapic_template; 633 io->pci_dev = NULL; 634 io->pci_wnd = NULL; 635 mtx_lock_spin(&icu_lock); 636 io->io_id = next_id++; 637 io->io_apic_id = ioapic_read(apic, IOAPIC_ID) >> APIC_ID_SHIFT; 638 if (apic_id != -1 && io->io_apic_id != apic_id) { 639 ioapic_write(apic, IOAPIC_ID, apic_id << APIC_ID_SHIFT); 640 mtx_unlock_spin(&icu_lock); 641 io->io_apic_id = apic_id; 642 printf("ioapic%u: Changing APIC ID to %d\n", io->io_id, 643 apic_id); 644 } else 645 mtx_unlock_spin(&icu_lock); 646 if (intbase == -1) { 647 intbase = next_ioapic_base; 648 printf("ioapic%u: Assuming intbase of %d\n", io->io_id, 649 intbase); 650 } else if (intbase != next_ioapic_base && bootverbose) 651 printf("ioapic%u: WARNING: intbase %d != expected base %d\n", 652 io->io_id, intbase, next_ioapic_base); 653 io->io_intbase = intbase; 654 next_ioapic_base = intbase + numintr; 655 if (next_ioapic_base > num_io_irqs) 656 num_io_irqs = next_ioapic_base; 657 io->io_numintr = numintr; 658 io->io_addr = apic; 659 io->io_paddr = addr; 660 661 if (bootverbose) { 662 printf("ioapic%u: ver 0x%02x maxredir 0x%02x\n", io->io_id, 663 (value & IOART_VER_VERSION), (value & IOART_VER_MAXREDIR) 664 >> MAXREDIRSHIFT); 665 } 666 /* 667 * The summary information about IO-APIC versions is taken from 668 * the Linux kernel source: 669 * 0Xh 82489DX 670 * 1Xh I/OAPIC or I/O(x)APIC which are not PCI 2.2 Compliant 671 * 2Xh I/O(x)APIC which is PCI 2.2 Compliant 672 * 30h-FFh Reserved 673 * IO-APICs with version >= 0x20 have working EOIR register. 674 */ 675 io->io_haseoi = (value & IOART_VER_VERSION) >= 0x20; 676 677 /* 678 * Initialize pins. Start off with interrupts disabled. Default 679 * to active-hi and edge-triggered for ISA interrupts and active-lo 680 * and level-triggered for all others. 681 */ 682 bzero(io->io_pins, sizeof(struct ioapic_intsrc) * numintr); 683 mtx_lock_spin(&icu_lock); 684 for (i = 0, intpin = io->io_pins; i < numintr; i++, intpin++) { 685 intpin->io_intsrc.is_pic = (struct pic *)io; 686 intpin->io_intpin = i; 687 intpin->io_irq = intbase + i; 688 689 /* 690 * Assume that pin 0 on the first I/O APIC is an ExtINT pin. 691 * Assume that pins 1-15 are ISA interrupts and that all 692 * other pins are PCI interrupts. 693 */ 694 if (intpin->io_irq == 0) 695 ioapic_set_extint(io, i); 696 else if (intpin->io_irq < IOAPIC_ISA_INTS) { 697 intpin->io_bus = APIC_BUS_ISA; 698 intpin->io_activehi = 1; 699 intpin->io_edgetrigger = 1; 700 intpin->io_masked = 1; 701 } else { 702 intpin->io_bus = APIC_BUS_PCI; 703 intpin->io_activehi = 0; 704 intpin->io_edgetrigger = 0; 705 intpin->io_masked = 1; 706 } 707 708 /* 709 * Route interrupts to the BSP by default. Interrupts may 710 * be routed to other CPUs later after they are enabled. 711 */ 712 intpin->io_cpu = PCPU_GET(apic_id); 713 value = ioapic_read(apic, IOAPIC_REDTBL_LO(i)); 714 ioapic_write(apic, IOAPIC_REDTBL_LO(i), value | IOART_INTMSET); 715 #ifdef ACPI_DMAR 716 /* dummy, but sets cookie */ 717 mtx_unlock_spin(&icu_lock); 718 iommu_map_ioapic_intr(io->io_apic_id, 719 intpin->io_cpu, intpin->io_vector, intpin->io_edgetrigger, 720 intpin->io_activehi, intpin->io_irq, 721 &intpin->io_remap_cookie, NULL, NULL); 722 mtx_lock_spin(&icu_lock); 723 #endif 724 } 725 mtx_unlock_spin(&icu_lock); 726 727 return (io); 728 } 729 730 int 731 ioapic_get_vector(void *cookie, u_int pin) 732 { 733 struct ioapic *io; 734 735 io = (struct ioapic *)cookie; 736 if (pin >= io->io_numintr) 737 return (-1); 738 return (io->io_pins[pin].io_irq); 739 } 740 741 int 742 ioapic_disable_pin(void *cookie, u_int pin) 743 { 744 struct ioapic *io; 745 746 io = (struct ioapic *)cookie; 747 if (pin >= io->io_numintr) 748 return (EINVAL); 749 if (io->io_pins[pin].io_irq == IRQ_DISABLED) 750 return (EINVAL); 751 io->io_pins[pin].io_irq = IRQ_DISABLED; 752 if (bootverbose) 753 printf("ioapic%u: intpin %d disabled\n", io->io_id, pin); 754 return (0); 755 } 756 757 int 758 ioapic_remap_vector(void *cookie, u_int pin, int vector) 759 { 760 struct ioapic *io; 761 762 io = (struct ioapic *)cookie; 763 if (pin >= io->io_numintr || vector < 0) 764 return (EINVAL); 765 if (io->io_pins[pin].io_irq < 0) 766 return (EINVAL); 767 io->io_pins[pin].io_irq = vector; 768 if (bootverbose) 769 printf("ioapic%u: Routing IRQ %d -> intpin %d\n", io->io_id, 770 vector, pin); 771 return (0); 772 } 773 774 int 775 ioapic_set_bus(void *cookie, u_int pin, int bus_type) 776 { 777 struct ioapic *io; 778 779 if (bus_type < 0 || bus_type > APIC_BUS_MAX) 780 return (EINVAL); 781 io = (struct ioapic *)cookie; 782 if (pin >= io->io_numintr) 783 return (EINVAL); 784 if (io->io_pins[pin].io_irq < 0) 785 return (EINVAL); 786 if (io->io_pins[pin].io_bus == bus_type) 787 return (0); 788 io->io_pins[pin].io_bus = bus_type; 789 if (bootverbose) 790 printf("ioapic%u: intpin %d bus %s\n", io->io_id, pin, 791 ioapic_bus_string(bus_type)); 792 return (0); 793 } 794 795 int 796 ioapic_set_nmi(void *cookie, u_int pin) 797 { 798 struct ioapic *io; 799 800 io = (struct ioapic *)cookie; 801 if (pin >= io->io_numintr) 802 return (EINVAL); 803 if (io->io_pins[pin].io_irq == IRQ_NMI) 804 return (0); 805 if (io->io_pins[pin].io_irq < 0) 806 return (EINVAL); 807 io->io_pins[pin].io_bus = APIC_BUS_UNKNOWN; 808 io->io_pins[pin].io_irq = IRQ_NMI; 809 io->io_pins[pin].io_masked = 0; 810 io->io_pins[pin].io_edgetrigger = 1; 811 io->io_pins[pin].io_activehi = 1; 812 if (bootverbose) 813 printf("ioapic%u: Routing NMI -> intpin %d\n", 814 io->io_id, pin); 815 return (0); 816 } 817 818 int 819 ioapic_set_smi(void *cookie, u_int pin) 820 { 821 struct ioapic *io; 822 823 io = (struct ioapic *)cookie; 824 if (pin >= io->io_numintr) 825 return (EINVAL); 826 if (io->io_pins[pin].io_irq == IRQ_SMI) 827 return (0); 828 if (io->io_pins[pin].io_irq < 0) 829 return (EINVAL); 830 io->io_pins[pin].io_bus = APIC_BUS_UNKNOWN; 831 io->io_pins[pin].io_irq = IRQ_SMI; 832 io->io_pins[pin].io_masked = 0; 833 io->io_pins[pin].io_edgetrigger = 1; 834 io->io_pins[pin].io_activehi = 1; 835 if (bootverbose) 836 printf("ioapic%u: Routing SMI -> intpin %d\n", 837 io->io_id, pin); 838 return (0); 839 } 840 841 int 842 ioapic_set_extint(void *cookie, u_int pin) 843 { 844 struct ioapic *io; 845 846 io = (struct ioapic *)cookie; 847 if (pin >= io->io_numintr) 848 return (EINVAL); 849 if (io->io_pins[pin].io_irq == IRQ_EXTINT) 850 return (0); 851 if (io->io_pins[pin].io_irq < 0) 852 return (EINVAL); 853 io->io_pins[pin].io_bus = APIC_BUS_UNKNOWN; 854 io->io_pins[pin].io_irq = IRQ_EXTINT; 855 if (enable_extint) 856 io->io_pins[pin].io_masked = 0; 857 else 858 io->io_pins[pin].io_masked = 1; 859 io->io_pins[pin].io_edgetrigger = 1; 860 io->io_pins[pin].io_activehi = 1; 861 if (bootverbose) 862 printf("ioapic%u: Routing external 8259A's -> intpin %d\n", 863 io->io_id, pin); 864 return (0); 865 } 866 867 int 868 ioapic_set_polarity(void *cookie, u_int pin, enum intr_polarity pol) 869 { 870 struct ioapic *io; 871 int activehi; 872 873 io = (struct ioapic *)cookie; 874 if (pin >= io->io_numintr || pol == INTR_POLARITY_CONFORM) 875 return (EINVAL); 876 if (io->io_pins[pin].io_irq < 0) 877 return (EINVAL); 878 activehi = (pol == INTR_POLARITY_HIGH); 879 if (io->io_pins[pin].io_activehi == activehi) 880 return (0); 881 io->io_pins[pin].io_activehi = activehi; 882 if (bootverbose) 883 printf("ioapic%u: intpin %d polarity: %s\n", io->io_id, pin, 884 pol == INTR_POLARITY_HIGH ? "high" : "low"); 885 return (0); 886 } 887 888 int 889 ioapic_set_triggermode(void *cookie, u_int pin, enum intr_trigger trigger) 890 { 891 struct ioapic *io; 892 int edgetrigger; 893 894 io = (struct ioapic *)cookie; 895 if (pin >= io->io_numintr || trigger == INTR_TRIGGER_CONFORM) 896 return (EINVAL); 897 if (io->io_pins[pin].io_irq < 0) 898 return (EINVAL); 899 edgetrigger = (trigger == INTR_TRIGGER_EDGE); 900 if (io->io_pins[pin].io_edgetrigger == edgetrigger) 901 return (0); 902 io->io_pins[pin].io_edgetrigger = edgetrigger; 903 if (bootverbose) 904 printf("ioapic%u: intpin %d trigger: %s\n", io->io_id, pin, 905 trigger == INTR_TRIGGER_EDGE ? "edge" : "level"); 906 return (0); 907 } 908 909 /* 910 * Register a complete I/O APIC object with the interrupt subsystem. 911 */ 912 void 913 ioapic_register(void *cookie) 914 { 915 struct ioapic_intsrc *pin; 916 struct ioapic *io; 917 volatile ioapic_t *apic; 918 uint32_t flags; 919 int i; 920 921 io = (struct ioapic *)cookie; 922 apic = io->io_addr; 923 mtx_lock_spin(&icu_lock); 924 flags = ioapic_read(apic, IOAPIC_VER) & IOART_VER_VERSION; 925 STAILQ_INSERT_TAIL(&ioapic_list, io, io_next); 926 mtx_unlock_spin(&icu_lock); 927 printf("ioapic%u <Version %u.%u> irqs %u-%u on motherboard\n", 928 io->io_id, flags >> 4, flags & 0xf, io->io_intbase, 929 io->io_intbase + io->io_numintr - 1); 930 931 /* 932 * Reprogram pins to handle special case pins (such as NMI and 933 * SMI) and disable normal pins until a handler is registered. 934 */ 935 intr_register_pic(&io->io_pic); 936 for (i = 0, pin = io->io_pins; i < io->io_numintr; i++, pin++) 937 ioapic_reprogram_intpin(&pin->io_intsrc); 938 } 939 940 /* 941 * Add interrupt sources for I/O APIC interrupt pins. 942 */ 943 static void 944 ioapic_register_sources(struct pic *pic) 945 { 946 struct ioapic_intsrc *pin; 947 struct ioapic *io; 948 int i; 949 950 io = (struct ioapic *)pic; 951 for (i = 0, pin = io->io_pins; i < io->io_numintr; i++, pin++) { 952 if (pin->io_irq >= 0) 953 intr_register_source(&pin->io_intsrc); 954 } 955 } 956 957 /* A simple new-bus driver to consume PCI I/O APIC devices. */ 958 static int 959 ioapic_pci_probe(device_t dev) 960 { 961 962 if (pci_get_class(dev) == PCIC_BASEPERIPH && 963 pci_get_subclass(dev) == PCIS_BASEPERIPH_PIC) { 964 switch (pci_get_progif(dev)) { 965 case PCIP_BASEPERIPH_PIC_IO_APIC: 966 device_set_desc(dev, "IO APIC"); 967 break; 968 case PCIP_BASEPERIPH_PIC_IOX_APIC: 969 device_set_desc(dev, "IO(x) APIC"); 970 break; 971 default: 972 return (ENXIO); 973 } 974 device_quiet(dev); 975 return (-10000); 976 } 977 return (ENXIO); 978 } 979 980 static int 981 ioapic_pci_attach(device_t dev) 982 { 983 struct resource *res; 984 volatile ioapic_t *apic; 985 struct ioapic *io; 986 int rid; 987 u_int apic_id; 988 989 /* 990 * Try to match the enumerated ioapic. Match BAR start 991 * against io_paddr. Due to a fear that PCI window is not the 992 * same as the MADT reported io window, but an alias, read the 993 * APIC ID from the mapped BAR and match against it. 994 */ 995 rid = PCIR_BAR(0); 996 res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid, 997 RF_ACTIVE | RF_SHAREABLE); 998 if (res == NULL) { 999 if (bootverbose) 1000 device_printf(dev, "cannot activate BAR0\n"); 1001 return (ENXIO); 1002 } 1003 apic = (volatile ioapic_t *)rman_get_virtual(res); 1004 if (rman_get_size(res) < IOAPIC_WND_SIZE) { 1005 if (bootverbose) 1006 device_printf(dev, 1007 "BAR0 too small (%jd) for IOAPIC window\n", 1008 (uintmax_t)rman_get_size(res)); 1009 goto fail; 1010 } 1011 mtx_lock_spin(&icu_lock); 1012 apic_id = ioapic_read(apic, IOAPIC_ID) >> APIC_ID_SHIFT; 1013 /* First match by io window address */ 1014 STAILQ_FOREACH(io, &ioapic_list, io_next) { 1015 if (io->io_paddr == (vm_paddr_t)rman_get_start(res)) 1016 goto found; 1017 } 1018 /* Then by apic id */ 1019 STAILQ_FOREACH(io, &ioapic_list, io_next) { 1020 if (io->io_apic_id == apic_id) 1021 goto found; 1022 } 1023 mtx_unlock_spin(&icu_lock); 1024 if (bootverbose) 1025 device_printf(dev, 1026 "cannot match pci bar apic id %d against MADT\n", 1027 apic_id); 1028 fail: 1029 bus_release_resource(dev, SYS_RES_MEMORY, rid, res); 1030 return (ENXIO); 1031 found: 1032 KASSERT(io->pci_dev == NULL, 1033 ("ioapic %d pci_dev not NULL", io->io_id)); 1034 KASSERT(io->pci_wnd == NULL, 1035 ("ioapic %d pci_wnd not NULL", io->io_id)); 1036 1037 io->pci_dev = dev; 1038 io->pci_wnd = res; 1039 if (bootverbose && (io->io_paddr != (vm_paddr_t)rman_get_start(res) || 1040 io->io_apic_id != apic_id)) { 1041 device_printf(dev, "pci%d:%d:%d:%d pci BAR0@%jx id %d " 1042 "MADT id %d paddr@%jx\n", 1043 pci_get_domain(dev), pci_get_bus(dev), 1044 pci_get_slot(dev), pci_get_function(dev), 1045 (uintmax_t)rman_get_start(res), apic_id, 1046 io->io_apic_id, (uintmax_t)io->io_paddr); 1047 } 1048 mtx_unlock_spin(&icu_lock); 1049 return (0); 1050 } 1051 1052 static device_method_t ioapic_pci_methods[] = { 1053 /* Device interface */ 1054 DEVMETHOD(device_probe, ioapic_pci_probe), 1055 DEVMETHOD(device_attach, ioapic_pci_attach), 1056 1057 { 0, 0 } 1058 }; 1059 1060 DEFINE_CLASS_0(ioapic, ioapic_pci_driver, ioapic_pci_methods, 0); 1061 1062 static devclass_t ioapic_devclass; 1063 DRIVER_MODULE(ioapic, pci, ioapic_pci_driver, ioapic_devclass, 0, 0); 1064 1065 int 1066 ioapic_get_rid(u_int apic_id, uint16_t *ridp) 1067 { 1068 struct ioapic *io; 1069 uintptr_t rid; 1070 int error; 1071 1072 mtx_lock_spin(&icu_lock); 1073 STAILQ_FOREACH(io, &ioapic_list, io_next) { 1074 if (io->io_apic_id == apic_id) 1075 break; 1076 } 1077 mtx_unlock_spin(&icu_lock); 1078 if (io == NULL || io->pci_dev == NULL) 1079 return (EINVAL); 1080 error = pci_get_id(io->pci_dev, PCI_ID_RID, &rid); 1081 if (error != 0) 1082 return (error); 1083 *ridp = rid; 1084 return (0); 1085 } 1086 1087 /* 1088 * A new-bus driver to consume the memory resources associated with 1089 * the APICs in the system. On some systems ACPI or PnPBIOS system 1090 * resource devices may already claim these resources. To keep from 1091 * breaking those devices, we attach ourself to the nexus device after 1092 * legacy0 and acpi0 and ignore any allocation failures. 1093 */ 1094 static void 1095 apic_identify(driver_t *driver, device_t parent) 1096 { 1097 1098 /* 1099 * Add at order 12. acpi0 is probed at order 10 and legacy0 1100 * is probed at order 11. 1101 */ 1102 if (lapic_paddr != 0) 1103 BUS_ADD_CHILD(parent, 12, "apic", 0); 1104 } 1105 1106 static int 1107 apic_probe(device_t dev) 1108 { 1109 1110 device_set_desc(dev, "APIC resources"); 1111 device_quiet(dev); 1112 return (0); 1113 } 1114 1115 static void 1116 apic_add_resource(device_t dev, int rid, vm_paddr_t base, size_t length) 1117 { 1118 int error; 1119 1120 error = bus_set_resource(dev, SYS_RES_MEMORY, rid, base, length); 1121 if (error) 1122 panic("apic_add_resource: resource %d failed set with %d", rid, 1123 error); 1124 bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid, RF_SHAREABLE); 1125 } 1126 1127 static int 1128 apic_attach(device_t dev) 1129 { 1130 struct ioapic *io; 1131 int i; 1132 1133 /* Reserve the local APIC. */ 1134 apic_add_resource(dev, 0, lapic_paddr, LAPIC_MEM_REGION); 1135 i = 1; 1136 STAILQ_FOREACH(io, &ioapic_list, io_next) { 1137 apic_add_resource(dev, i, io->io_paddr, IOAPIC_MEM_REGION); 1138 i++; 1139 } 1140 return (0); 1141 } 1142 1143 static device_method_t apic_methods[] = { 1144 /* Device interface */ 1145 DEVMETHOD(device_identify, apic_identify), 1146 DEVMETHOD(device_probe, apic_probe), 1147 DEVMETHOD(device_attach, apic_attach), 1148 1149 { 0, 0 } 1150 }; 1151 1152 DEFINE_CLASS_0(apic, apic_driver, apic_methods, 0); 1153 1154 static devclass_t apic_devclass; 1155 DRIVER_MODULE(apic, nexus, apic_driver, apic_devclass, 0, 0); 1156 1157 #include "opt_ddb.h" 1158 1159 #ifdef DDB 1160 #include <ddb/ddb.h> 1161 1162 static const char * 1163 ioapic_delivery_mode(uint32_t mode) 1164 { 1165 1166 switch (mode) { 1167 case IOART_DELFIXED: 1168 return ("fixed"); 1169 case IOART_DELLOPRI: 1170 return ("lowestpri"); 1171 case IOART_DELSMI: 1172 return ("SMI"); 1173 case IOART_DELRSV1: 1174 return ("rsrvd1"); 1175 case IOART_DELNMI: 1176 return ("NMI"); 1177 case IOART_DELINIT: 1178 return ("INIT"); 1179 case IOART_DELRSV2: 1180 return ("rsrvd2"); 1181 case IOART_DELEXINT: 1182 return ("ExtINT"); 1183 default: 1184 return (""); 1185 } 1186 } 1187 1188 static u_int 1189 db_ioapic_read(volatile ioapic_t *apic, int reg) 1190 { 1191 1192 apic->ioregsel = reg; 1193 return (apic->iowin); 1194 } 1195 1196 static void 1197 db_show_ioapic_one(volatile ioapic_t *io_addr) 1198 { 1199 uint32_t r, lo, hi; 1200 int mre, i; 1201 1202 r = db_ioapic_read(io_addr, IOAPIC_VER); 1203 mre = (r & IOART_VER_MAXREDIR) >> MAXREDIRSHIFT; 1204 db_printf("Id 0x%08x Ver 0x%02x MRE %d\n", 1205 db_ioapic_read(io_addr, IOAPIC_ID), r & IOART_VER_VERSION, mre); 1206 for (i = 0; i < mre; i++) { 1207 lo = db_ioapic_read(io_addr, IOAPIC_REDTBL_LO(i)); 1208 hi = db_ioapic_read(io_addr, IOAPIC_REDTBL_HI(i)); 1209 db_printf(" pin %d Dest %s/%x %smasked Trig %s RemoteIRR %d " 1210 "Polarity %s Status %s DeliveryMode %s Vec %d\n", i, 1211 (lo & IOART_DESTMOD) == IOART_DESTLOG ? "log" : "phy", 1212 (hi & IOART_DEST) >> 24, 1213 (lo & IOART_INTMASK) == IOART_INTMSET ? "" : "not", 1214 (lo & IOART_TRGRMOD) == IOART_TRGRLVL ? "lvl" : "edge", 1215 (lo & IOART_REM_IRR) == IOART_REM_IRR ? 1 : 0, 1216 (lo & IOART_INTPOL) == IOART_INTALO ? "low" : "high", 1217 (lo & IOART_DELIVS) == IOART_DELIVS ? "pend" : "idle", 1218 ioapic_delivery_mode(lo & IOART_DELMOD), 1219 (lo & IOART_INTVEC)); 1220 } 1221 } 1222 1223 DB_SHOW_COMMAND(ioapic, db_show_ioapic) 1224 { 1225 struct ioapic *ioapic; 1226 int idx, i; 1227 1228 if (!have_addr) { 1229 db_printf("usage: show ioapic index\n"); 1230 return; 1231 } 1232 1233 idx = (int)addr; 1234 i = 0; 1235 STAILQ_FOREACH(ioapic, &ioapic_list, io_next) { 1236 if (idx == i) { 1237 db_show_ioapic_one(ioapic->io_addr); 1238 break; 1239 } 1240 i++; 1241 } 1242 } 1243 1244 DB_SHOW_ALL_COMMAND(ioapics, db_show_all_ioapics) 1245 { 1246 struct ioapic *ioapic; 1247 1248 STAILQ_FOREACH(ioapic, &ioapic_list, io_next) 1249 db_show_ioapic_one(ioapic->io_addr); 1250 } 1251 #endif 1252