1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause 3 * 4 * Copyright (c) 2003 John Baldwin <jhb@FreeBSD.org> 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 25 * SUCH DAMAGE. 26 */ 27 28 #include <sys/cdefs.h> 29 #include "opt_acpi.h" 30 #include "opt_iommu.h" 31 #include "opt_isa.h" 32 33 #include <sys/param.h> 34 #include <sys/systm.h> 35 #include <sys/bus.h> 36 #include <sys/kernel.h> 37 #include <sys/lock.h> 38 #include <sys/malloc.h> 39 #include <sys/module.h> 40 #include <sys/mutex.h> 41 #include <sys/rman.h> 42 #include <sys/sysctl.h> 43 44 #include <dev/pci/pcireg.h> 45 #include <dev/pci/pcivar.h> 46 47 #include <vm/vm.h> 48 #include <vm/pmap.h> 49 50 #include <x86/apicreg.h> 51 #include <machine/frame.h> 52 #include <machine/intr_machdep.h> 53 #include <x86/apicvar.h> 54 #include <machine/resource.h> 55 #include <machine/segments.h> 56 #include <x86/iommu/iommu_intrmap.h> 57 58 #define IOAPIC_ISA_INTS 16 59 #define IOAPIC_MEM_REGION 32 60 #define IOAPIC_REDTBL_LO(i) (IOAPIC_REDTBL + (i) * 2) 61 #define IOAPIC_REDTBL_HI(i) (IOAPIC_REDTBL_LO(i) + 1) 62 63 static MALLOC_DEFINE(M_IOAPIC, "io_apic", "I/O APIC structures"); 64 65 /* 66 * I/O APIC interrupt source driver. Each pin is assigned an IRQ cookie 67 * as laid out in the ACPI System Interrupt number model where each I/O 68 * APIC has a contiguous chunk of the System Interrupt address space. 69 * We assume that IRQs 1 - 15 behave like ISA IRQs and that all other 70 * IRQs behave as PCI IRQs by default. We also assume that the pin for 71 * IRQ 0 is actually an ExtINT pin. The apic enumerators override the 72 * configuration of individual pins as indicated by their tables. 73 * 74 * Documentation for the I/O APIC: "82093AA I/O Advanced Programmable 75 * Interrupt Controller (IOAPIC)", May 1996, Intel Corp. 76 * ftp://download.intel.com/design/chipsets/datashts/29056601.pdf 77 */ 78 79 struct ioapic_intsrc { 80 struct intsrc io_intsrc; 81 int io_irq; 82 u_int io_intpin:8; 83 u_int io_vector:8; 84 u_int io_cpu; 85 u_int io_activehi:1; 86 u_int io_edgetrigger:1; 87 u_int io_masked:1; 88 int io_bus:4; 89 uint32_t io_lowreg; 90 u_int io_remap_cookie; 91 }; 92 93 struct ioapic { 94 struct pic io_pic; 95 u_int io_id:8; /* logical ID */ 96 u_int io_apic_id:8; /* Id as enumerated by MADT */ 97 u_int io_hw_apic_id:8; /* Content of APIC ID register */ 98 u_int io_intbase:8; /* System Interrupt base */ 99 u_int io_numintr:8; 100 u_int io_haseoi:1; 101 volatile ioapic_t *io_addr; /* XXX: should use bus_space */ 102 vm_paddr_t io_paddr; 103 STAILQ_ENTRY(ioapic) io_next; 104 device_t pci_dev; /* matched pci device, if found */ 105 struct resource *pci_wnd; /* BAR 0, should be same or alias to 106 io_paddr */ 107 struct ioapic_intsrc io_pins[0]; 108 }; 109 110 static u_int ioapic_read(volatile ioapic_t *apic, int reg); 111 static void ioapic_write(volatile ioapic_t *apic, int reg, u_int val); 112 static const char *ioapic_bus_string(int bus_type); 113 static void ioapic_print_irq(struct ioapic_intsrc *intpin); 114 static void ioapic_register_sources(struct pic *pic); 115 static void ioapic_enable_source(struct intsrc *isrc); 116 static void ioapic_disable_source(struct intsrc *isrc, int eoi); 117 static void ioapic_eoi_source(struct intsrc *isrc); 118 static void ioapic_enable_intr(struct intsrc *isrc); 119 static void ioapic_disable_intr(struct intsrc *isrc); 120 static int ioapic_vector(struct intsrc *isrc); 121 static int ioapic_source_pending(struct intsrc *isrc); 122 static int ioapic_config_intr(struct intsrc *isrc, enum intr_trigger trig, 123 enum intr_polarity pol); 124 static void ioapic_resume(struct pic *pic, bool suspend_cancelled); 125 static int ioapic_assign_cpu(struct intsrc *isrc, u_int apic_id); 126 static void ioapic_program_intpin(struct ioapic_intsrc *intpin); 127 static void ioapic_reprogram_intpin(struct intsrc *isrc); 128 129 static STAILQ_HEAD(,ioapic) ioapic_list = STAILQ_HEAD_INITIALIZER(ioapic_list); 130 struct pic ioapic_template = { 131 .pic_register_sources = ioapic_register_sources, 132 .pic_enable_source = ioapic_enable_source, 133 .pic_disable_source = ioapic_disable_source, 134 .pic_eoi_source = ioapic_eoi_source, 135 .pic_enable_intr = ioapic_enable_intr, 136 .pic_disable_intr = ioapic_disable_intr, 137 .pic_vector = ioapic_vector, 138 .pic_source_pending = ioapic_source_pending, 139 .pic_suspend = NULL, 140 .pic_resume = ioapic_resume, 141 .pic_config_intr = ioapic_config_intr, 142 .pic_assign_cpu = ioapic_assign_cpu, 143 .pic_reprogram_pin = ioapic_reprogram_intpin, 144 }; 145 146 static u_int next_ioapic_base; 147 static u_int next_id; 148 149 static int enable_extint; 150 SYSCTL_INT(_hw_apic, OID_AUTO, enable_extint, CTLFLAG_RDTUN, &enable_extint, 0, 151 "Enable the ExtINT pin in the first I/O APIC"); 152 153 static void 154 _ioapic_eoi_source(struct intsrc *isrc, int locked) 155 { 156 struct ioapic_intsrc *src; 157 struct ioapic *io; 158 volatile uint32_t *apic_eoi; 159 uint32_t low1; 160 161 lapic_eoi(); 162 if (!lapic_eoi_suppression) 163 return; 164 src = (struct ioapic_intsrc *)isrc; 165 if (src->io_edgetrigger) 166 return; 167 io = (struct ioapic *)isrc->is_pic; 168 169 /* 170 * Handle targeted EOI for level-triggered pins, if broadcast 171 * EOI suppression is supported by LAPICs. 172 */ 173 if (io->io_haseoi) { 174 /* 175 * If IOAPIC has EOI Register, simply write vector 176 * number into the reg. 177 */ 178 apic_eoi = (volatile uint32_t *)((volatile char *) 179 io->io_addr + IOAPIC_EOIR); 180 *apic_eoi = src->io_vector; 181 } else { 182 /* 183 * Otherwise, if IO-APIC is too old to provide EOIR, 184 * do what Intel did for the Linux kernel. Temporary 185 * switch the pin to edge-trigger and back, masking 186 * the pin during the trick. 187 */ 188 if (!locked) 189 mtx_lock_spin(&icu_lock); 190 low1 = src->io_lowreg; 191 low1 &= ~IOART_TRGRLVL; 192 low1 |= IOART_TRGREDG | IOART_INTMSET; 193 ioapic_write(io->io_addr, IOAPIC_REDTBL_LO(src->io_intpin), 194 low1); 195 low1 = src->io_lowreg; 196 if (src->io_masked != 0) 197 low1 |= IOART_INTMSET; 198 ioapic_write(io->io_addr, IOAPIC_REDTBL_LO(src->io_intpin), 199 low1); 200 if (!locked) 201 mtx_unlock_spin(&icu_lock); 202 } 203 } 204 205 static u_int 206 ioapic_read(volatile ioapic_t *apic, int reg) 207 { 208 209 mtx_assert(&icu_lock, MA_OWNED); 210 apic->ioregsel = reg; 211 return (apic->iowin); 212 } 213 214 static void 215 ioapic_write(volatile ioapic_t *apic, int reg, u_int val) 216 { 217 218 mtx_assert(&icu_lock, MA_OWNED); 219 apic->ioregsel = reg; 220 apic->iowin = val; 221 } 222 223 static const char * 224 ioapic_bus_string(int bus_type) 225 { 226 227 switch (bus_type) { 228 case APIC_BUS_ISA: 229 return ("ISA"); 230 case APIC_BUS_EISA: 231 return ("EISA"); 232 case APIC_BUS_PCI: 233 return ("PCI"); 234 default: 235 return ("unknown"); 236 } 237 } 238 239 static void 240 ioapic_print_irq(struct ioapic_intsrc *intpin) 241 { 242 243 switch (intpin->io_irq) { 244 case IRQ_DISABLED: 245 printf("disabled"); 246 break; 247 case IRQ_EXTINT: 248 printf("ExtINT"); 249 break; 250 case IRQ_NMI: 251 printf("NMI"); 252 break; 253 case IRQ_SMI: 254 printf("SMI"); 255 break; 256 default: 257 printf("%s IRQ %d", ioapic_bus_string(intpin->io_bus), 258 intpin->io_irq); 259 } 260 } 261 262 static void 263 ioapic_enable_source(struct intsrc *isrc) 264 { 265 struct ioapic_intsrc *intpin = (struct ioapic_intsrc *)isrc; 266 struct ioapic *io = (struct ioapic *)isrc->is_pic; 267 uint32_t flags; 268 269 mtx_lock_spin(&icu_lock); 270 if (intpin->io_masked) { 271 flags = intpin->io_lowreg & ~IOART_INTMASK; 272 ioapic_write(io->io_addr, IOAPIC_REDTBL_LO(intpin->io_intpin), 273 flags); 274 intpin->io_masked = 0; 275 } 276 mtx_unlock_spin(&icu_lock); 277 } 278 279 static void 280 ioapic_disable_source(struct intsrc *isrc, int eoi) 281 { 282 struct ioapic_intsrc *intpin = (struct ioapic_intsrc *)isrc; 283 struct ioapic *io = (struct ioapic *)isrc->is_pic; 284 uint32_t flags; 285 286 mtx_lock_spin(&icu_lock); 287 if (!intpin->io_masked && !intpin->io_edgetrigger) { 288 flags = intpin->io_lowreg | IOART_INTMSET; 289 ioapic_write(io->io_addr, IOAPIC_REDTBL_LO(intpin->io_intpin), 290 flags); 291 intpin->io_masked = 1; 292 } 293 294 if (eoi == PIC_EOI) 295 _ioapic_eoi_source(isrc, 1); 296 297 mtx_unlock_spin(&icu_lock); 298 } 299 300 static void 301 ioapic_eoi_source(struct intsrc *isrc) 302 { 303 304 _ioapic_eoi_source(isrc, 0); 305 } 306 307 /* 308 * Completely program an intpin based on the data in its interrupt source 309 * structure. 310 */ 311 static void 312 ioapic_program_intpin(struct ioapic_intsrc *intpin) 313 { 314 struct ioapic *io = (struct ioapic *)intpin->io_intsrc.is_pic; 315 uint32_t low, high; 316 #ifdef IOMMU 317 int error; 318 #endif 319 320 /* 321 * If a pin is completely invalid or if it is valid but hasn't 322 * been enabled yet, just ensure that the pin is masked. 323 */ 324 mtx_assert(&icu_lock, MA_OWNED); 325 if (intpin->io_irq == IRQ_DISABLED || (intpin->io_irq >= 0 && 326 intpin->io_vector == 0)) { 327 low = ioapic_read(io->io_addr, 328 IOAPIC_REDTBL_LO(intpin->io_intpin)); 329 if ((low & IOART_INTMASK) == IOART_INTMCLR) 330 ioapic_write(io->io_addr, 331 IOAPIC_REDTBL_LO(intpin->io_intpin), 332 low | IOART_INTMSET); 333 #ifdef IOMMU 334 mtx_unlock_spin(&icu_lock); 335 iommu_unmap_ioapic_intr(io->io_apic_id, 336 &intpin->io_remap_cookie); 337 mtx_lock_spin(&icu_lock); 338 #endif 339 return; 340 } 341 342 #ifdef IOMMU 343 mtx_unlock_spin(&icu_lock); 344 error = iommu_map_ioapic_intr(io->io_apic_id, 345 intpin->io_cpu, intpin->io_vector, intpin->io_edgetrigger, 346 intpin->io_activehi, intpin->io_irq, &intpin->io_remap_cookie, 347 &high, &low); 348 mtx_lock_spin(&icu_lock); 349 if (error == 0) { 350 ioapic_write(io->io_addr, IOAPIC_REDTBL_HI(intpin->io_intpin), 351 high); 352 intpin->io_lowreg = low; 353 ioapic_write(io->io_addr, IOAPIC_REDTBL_LO(intpin->io_intpin), 354 low); 355 return; 356 } else if (error != EOPNOTSUPP) { 357 return; 358 } 359 #endif 360 361 /* 362 * Set the destination. Note that with Intel interrupt remapping, 363 * the previously reserved bits 55:48 now have a purpose so ensure 364 * these are zero. 365 */ 366 low = IOART_DESTPHY; 367 high = intpin->io_cpu << APIC_ID_SHIFT; 368 369 /* Program the rest of the low word. */ 370 if (intpin->io_edgetrigger) 371 low |= IOART_TRGREDG; 372 else 373 low |= IOART_TRGRLVL; 374 if (intpin->io_activehi) 375 low |= IOART_INTAHI; 376 else 377 low |= IOART_INTALO; 378 if (intpin->io_masked) 379 low |= IOART_INTMSET; 380 switch (intpin->io_irq) { 381 case IRQ_EXTINT: 382 KASSERT(intpin->io_edgetrigger, 383 ("ExtINT not edge triggered")); 384 low |= IOART_DELEXINT; 385 break; 386 case IRQ_NMI: 387 KASSERT(intpin->io_edgetrigger, 388 ("NMI not edge triggered")); 389 low |= IOART_DELNMI; 390 break; 391 case IRQ_SMI: 392 KASSERT(intpin->io_edgetrigger, 393 ("SMI not edge triggered")); 394 low |= IOART_DELSMI; 395 break; 396 default: 397 KASSERT(intpin->io_vector != 0, ("No vector for IRQ %u", 398 intpin->io_irq)); 399 low |= IOART_DELFIXED | intpin->io_vector; 400 } 401 402 /* Write the values to the APIC. */ 403 ioapic_write(io->io_addr, IOAPIC_REDTBL_HI(intpin->io_intpin), high); 404 intpin->io_lowreg = low; 405 ioapic_write(io->io_addr, IOAPIC_REDTBL_LO(intpin->io_intpin), low); 406 } 407 408 static void 409 ioapic_reprogram_intpin(struct intsrc *isrc) 410 { 411 412 mtx_lock_spin(&icu_lock); 413 ioapic_program_intpin((struct ioapic_intsrc *)isrc); 414 mtx_unlock_spin(&icu_lock); 415 } 416 417 static int 418 ioapic_assign_cpu(struct intsrc *isrc, u_int apic_id) 419 { 420 struct ioapic_intsrc *intpin = (struct ioapic_intsrc *)isrc; 421 struct ioapic *io = (struct ioapic *)isrc->is_pic; 422 u_int old_vector, new_vector; 423 u_int old_id; 424 425 /* 426 * On Hyper-V: 427 * - Stick to the first cpu for all I/O APIC pins. 428 * - And don't allow destination cpu changes. 429 */ 430 if (vm_guest == VM_GUEST_HV) { 431 if (intpin->io_vector) 432 return (EINVAL); 433 else 434 apic_id = 0; 435 } 436 437 /* 438 * keep 1st core as the destination for NMI 439 */ 440 if (intpin->io_irq == IRQ_NMI) 441 apic_id = 0; 442 443 /* 444 * Set us up to free the old irq. 445 */ 446 old_vector = intpin->io_vector; 447 old_id = intpin->io_cpu; 448 if (old_vector && apic_id == old_id) 449 return (0); 450 451 /* 452 * Allocate an APIC vector for this interrupt pin. Once 453 * we have a vector we program the interrupt pin. 454 */ 455 new_vector = apic_alloc_vector(apic_id, intpin->io_irq); 456 if (new_vector == 0) 457 return (ENOSPC); 458 459 /* 460 * Mask the old intpin if it is enabled while it is migrated. 461 * 462 * At least some level-triggered interrupts seem to need the 463 * extra DELAY() to avoid being stuck in a non-EOI'd state. 464 */ 465 mtx_lock_spin(&icu_lock); 466 if (!intpin->io_masked && !intpin->io_edgetrigger) { 467 ioapic_write(io->io_addr, IOAPIC_REDTBL_LO(intpin->io_intpin), 468 intpin->io_lowreg | IOART_INTMSET); 469 mtx_unlock_spin(&icu_lock); 470 DELAY(100); 471 mtx_lock_spin(&icu_lock); 472 } 473 474 intpin->io_cpu = apic_id; 475 intpin->io_vector = new_vector; 476 if (isrc->is_handlers > 0) 477 apic_enable_vector(intpin->io_cpu, intpin->io_vector); 478 if (bootverbose) { 479 printf("ioapic%u: routing intpin %u (", io->io_id, 480 intpin->io_intpin); 481 ioapic_print_irq(intpin); 482 printf(") to lapic %u vector %u\n", intpin->io_cpu, 483 intpin->io_vector); 484 } 485 ioapic_program_intpin(intpin); 486 mtx_unlock_spin(&icu_lock); 487 488 /* 489 * Free the old vector after the new one is established. This is done 490 * to prevent races where we could miss an interrupt. 491 */ 492 if (old_vector) { 493 if (isrc->is_handlers > 0) 494 apic_disable_vector(old_id, old_vector); 495 apic_free_vector(old_id, old_vector, intpin->io_irq); 496 } 497 return (0); 498 } 499 500 static void 501 ioapic_enable_intr(struct intsrc *isrc) 502 { 503 struct ioapic_intsrc *intpin = (struct ioapic_intsrc *)isrc; 504 505 if (intpin->io_vector == 0) 506 if (ioapic_assign_cpu(isrc, intr_next_cpu(isrc->is_domain)) != 0) 507 panic("Couldn't find an APIC vector for IRQ %d", 508 intpin->io_irq); 509 apic_enable_vector(intpin->io_cpu, intpin->io_vector); 510 } 511 512 static void 513 ioapic_disable_intr(struct intsrc *isrc) 514 { 515 struct ioapic_intsrc *intpin = (struct ioapic_intsrc *)isrc; 516 u_int vector; 517 518 if (intpin->io_vector != 0) { 519 /* Mask this interrupt pin and free its APIC vector. */ 520 vector = intpin->io_vector; 521 apic_disable_vector(intpin->io_cpu, vector); 522 mtx_lock_spin(&icu_lock); 523 intpin->io_masked = 1; 524 intpin->io_vector = 0; 525 ioapic_program_intpin(intpin); 526 mtx_unlock_spin(&icu_lock); 527 apic_free_vector(intpin->io_cpu, vector, intpin->io_irq); 528 } 529 } 530 531 static int 532 ioapic_vector(struct intsrc *isrc) 533 { 534 struct ioapic_intsrc *pin; 535 536 pin = (struct ioapic_intsrc *)isrc; 537 return (pin->io_irq); 538 } 539 540 static int 541 ioapic_source_pending(struct intsrc *isrc) 542 { 543 struct ioapic_intsrc *intpin = (struct ioapic_intsrc *)isrc; 544 545 if (intpin->io_vector == 0) 546 return 0; 547 return (lapic_intr_pending(intpin->io_vector)); 548 } 549 550 static int 551 ioapic_config_intr(struct intsrc *isrc, enum intr_trigger trig, 552 enum intr_polarity pol) 553 { 554 struct ioapic_intsrc *intpin = (struct ioapic_intsrc *)isrc; 555 struct ioapic *io = (struct ioapic *)isrc->is_pic; 556 int changed; 557 558 KASSERT(!(trig == INTR_TRIGGER_CONFORM || pol == INTR_POLARITY_CONFORM), 559 ("%s: Conforming trigger or polarity\n", __func__)); 560 561 /* 562 * EISA interrupts always use active high polarity, so don't allow 563 * them to be set to active low. 564 * 565 * XXX: Should we write to the ELCR if the trigger mode changes for 566 * an EISA IRQ or an ISA IRQ with the ELCR present? 567 */ 568 mtx_lock_spin(&icu_lock); 569 if (intpin->io_bus == APIC_BUS_EISA) 570 pol = INTR_POLARITY_HIGH; 571 changed = 0; 572 if (intpin->io_edgetrigger != (trig == INTR_TRIGGER_EDGE)) { 573 if (bootverbose) 574 printf("ioapic%u: Changing trigger for pin %u to %s\n", 575 io->io_id, intpin->io_intpin, 576 trig == INTR_TRIGGER_EDGE ? "edge" : "level"); 577 intpin->io_edgetrigger = (trig == INTR_TRIGGER_EDGE); 578 changed++; 579 } 580 if (intpin->io_activehi != (pol == INTR_POLARITY_HIGH)) { 581 if (bootverbose) 582 printf("ioapic%u: Changing polarity for pin %u to %s\n", 583 io->io_id, intpin->io_intpin, 584 pol == INTR_POLARITY_HIGH ? "high" : "low"); 585 intpin->io_activehi = (pol == INTR_POLARITY_HIGH); 586 changed++; 587 } 588 if (changed) 589 ioapic_program_intpin(intpin); 590 mtx_unlock_spin(&icu_lock); 591 return (0); 592 } 593 594 static void 595 ioapic_resume(struct pic *pic, bool suspend_cancelled) 596 { 597 struct ioapic *io = (struct ioapic *)pic; 598 int i; 599 600 mtx_lock_spin(&icu_lock); 601 for (i = 0; i < io->io_numintr; i++) 602 ioapic_program_intpin(&io->io_pins[i]); 603 mtx_unlock_spin(&icu_lock); 604 } 605 606 /* 607 * Create a plain I/O APIC object. 608 */ 609 void * 610 ioapic_create(vm_paddr_t addr, int32_t apic_id, int intbase) 611 { 612 struct ioapic *io; 613 struct ioapic_intsrc *intpin; 614 ioapic_t *apic; 615 u_int numintr, i; 616 uint32_t value; 617 618 /* Map the register window so we can access the device. */ 619 apic = pmap_mapdev(addr, IOAPIC_MEM_REGION); 620 mtx_lock_spin(&icu_lock); 621 value = ioapic_read(apic, IOAPIC_VER); 622 mtx_unlock_spin(&icu_lock); 623 624 /* If it's version register doesn't seem to work, punt. */ 625 if (value == 0xffffffff) { 626 pmap_unmapdev(apic, IOAPIC_MEM_REGION); 627 return (NULL); 628 } 629 630 /* Determine the number of vectors and set the APIC ID. */ 631 numintr = ((value & IOART_VER_MAXREDIR) >> MAXREDIRSHIFT) + 1; 632 io = malloc(sizeof(struct ioapic) + 633 numintr * sizeof(struct ioapic_intsrc), M_IOAPIC, M_WAITOK); 634 io->io_pic = ioapic_template; 635 io->pci_dev = NULL; 636 io->pci_wnd = NULL; 637 mtx_lock_spin(&icu_lock); 638 io->io_id = next_id++; 639 io->io_hw_apic_id = ioapic_read(apic, IOAPIC_ID) >> APIC_ID_SHIFT; 640 io->io_apic_id = apic_id == -1 ? io->io_hw_apic_id : apic_id; 641 mtx_unlock_spin(&icu_lock); 642 if (io->io_hw_apic_id != apic_id) 643 printf("ioapic%u: MADT APIC ID %d != hw id %d\n", io->io_id, 644 apic_id, io->io_hw_apic_id); 645 if (intbase == -1) { 646 intbase = next_ioapic_base; 647 printf("ioapic%u: Assuming intbase of %d\n", io->io_id, 648 intbase); 649 } else if (intbase != next_ioapic_base && bootverbose) 650 printf("ioapic%u: WARNING: intbase %d != expected base %d\n", 651 io->io_id, intbase, next_ioapic_base); 652 io->io_intbase = intbase; 653 next_ioapic_base = intbase + numintr; 654 if (next_ioapic_base > num_io_irqs) 655 num_io_irqs = next_ioapic_base; 656 io->io_numintr = numintr; 657 io->io_addr = apic; 658 io->io_paddr = addr; 659 660 if (bootverbose) { 661 printf("ioapic%u: ver 0x%02x maxredir 0x%02x\n", io->io_id, 662 (value & IOART_VER_VERSION), (value & IOART_VER_MAXREDIR) 663 >> MAXREDIRSHIFT); 664 } 665 /* 666 * The summary information about IO-APIC versions is taken from 667 * the Linux kernel source: 668 * 0Xh 82489DX 669 * 1Xh I/OAPIC or I/O(x)APIC which are not PCI 2.2 Compliant 670 * 2Xh I/O(x)APIC which is PCI 2.2 Compliant 671 * 30h-FFh Reserved 672 * IO-APICs with version >= 0x20 have working EOIR register. 673 */ 674 io->io_haseoi = (value & IOART_VER_VERSION) >= 0x20; 675 676 /* 677 * Initialize pins. Start off with interrupts disabled. Default 678 * to active-hi and edge-triggered for ISA interrupts and active-lo 679 * and level-triggered for all others. 680 */ 681 bzero(io->io_pins, sizeof(struct ioapic_intsrc) * numintr); 682 mtx_lock_spin(&icu_lock); 683 for (i = 0, intpin = io->io_pins; i < numintr; i++, intpin++) { 684 intpin->io_intsrc.is_pic = (struct pic *)io; 685 intpin->io_intpin = i; 686 intpin->io_irq = intbase + i; 687 688 /* 689 * Assume that pin 0 on the first I/O APIC is an ExtINT pin. 690 * Assume that pins 1-15 are ISA interrupts and that all 691 * other pins are PCI interrupts. 692 */ 693 if (intpin->io_irq == 0) 694 ioapic_set_extint(io, i); 695 else if (intpin->io_irq < IOAPIC_ISA_INTS) { 696 intpin->io_bus = APIC_BUS_ISA; 697 intpin->io_activehi = 1; 698 intpin->io_edgetrigger = 1; 699 intpin->io_masked = 1; 700 } else { 701 intpin->io_bus = APIC_BUS_PCI; 702 intpin->io_activehi = 0; 703 intpin->io_edgetrigger = 0; 704 intpin->io_masked = 1; 705 } 706 707 /* 708 * Route interrupts to the BSP by default. Interrupts may 709 * be routed to other CPUs later after they are enabled. 710 */ 711 intpin->io_cpu = PCPU_GET(apic_id); 712 value = ioapic_read(apic, IOAPIC_REDTBL_LO(i)); 713 ioapic_write(apic, IOAPIC_REDTBL_LO(i), value | IOART_INTMSET); 714 #ifdef IOMMU 715 /* dummy, but sets cookie */ 716 mtx_unlock_spin(&icu_lock); 717 iommu_map_ioapic_intr(io->io_apic_id, 718 intpin->io_cpu, intpin->io_vector, intpin->io_edgetrigger, 719 intpin->io_activehi, intpin->io_irq, 720 &intpin->io_remap_cookie, NULL, NULL); 721 mtx_lock_spin(&icu_lock); 722 #endif 723 } 724 mtx_unlock_spin(&icu_lock); 725 726 return (io); 727 } 728 729 int 730 ioapic_get_vector(void *cookie, u_int pin) 731 { 732 struct ioapic *io; 733 734 io = (struct ioapic *)cookie; 735 if (pin >= io->io_numintr) 736 return (-1); 737 return (io->io_pins[pin].io_irq); 738 } 739 740 int 741 ioapic_disable_pin(void *cookie, u_int pin) 742 { 743 struct ioapic *io; 744 745 io = (struct ioapic *)cookie; 746 if (pin >= io->io_numintr) 747 return (EINVAL); 748 if (io->io_pins[pin].io_irq == IRQ_DISABLED) 749 return (EINVAL); 750 io->io_pins[pin].io_irq = IRQ_DISABLED; 751 if (bootverbose) 752 printf("ioapic%u: intpin %d disabled\n", io->io_id, pin); 753 return (0); 754 } 755 756 int 757 ioapic_remap_vector(void *cookie, u_int pin, int vector) 758 { 759 struct ioapic *io; 760 761 io = (struct ioapic *)cookie; 762 if (pin >= io->io_numintr || vector < 0) 763 return (EINVAL); 764 if (io->io_pins[pin].io_irq < 0) 765 return (EINVAL); 766 io->io_pins[pin].io_irq = vector; 767 if (bootverbose) 768 printf("ioapic%u: Routing IRQ %d -> intpin %d\n", io->io_id, 769 vector, pin); 770 return (0); 771 } 772 773 int 774 ioapic_set_bus(void *cookie, u_int pin, int bus_type) 775 { 776 struct ioapic *io; 777 778 if (bus_type < 0 || bus_type > APIC_BUS_MAX) 779 return (EINVAL); 780 io = (struct ioapic *)cookie; 781 if (pin >= io->io_numintr) 782 return (EINVAL); 783 if (io->io_pins[pin].io_irq < 0) 784 return (EINVAL); 785 if (io->io_pins[pin].io_bus == bus_type) 786 return (0); 787 io->io_pins[pin].io_bus = bus_type; 788 if (bootverbose) 789 printf("ioapic%u: intpin %d bus %s\n", io->io_id, pin, 790 ioapic_bus_string(bus_type)); 791 return (0); 792 } 793 794 int 795 ioapic_set_nmi(void *cookie, u_int pin) 796 { 797 struct ioapic *io; 798 799 io = (struct ioapic *)cookie; 800 if (pin >= io->io_numintr) 801 return (EINVAL); 802 if (io->io_pins[pin].io_irq == IRQ_NMI) 803 return (0); 804 if (io->io_pins[pin].io_irq < 0) 805 return (EINVAL); 806 io->io_pins[pin].io_bus = APIC_BUS_UNKNOWN; 807 io->io_pins[pin].io_irq = IRQ_NMI; 808 io->io_pins[pin].io_masked = 0; 809 io->io_pins[pin].io_edgetrigger = 1; 810 io->io_pins[pin].io_activehi = 1; 811 if (bootverbose) 812 printf("ioapic%u: Routing NMI -> intpin %d\n", 813 io->io_id, pin); 814 return (0); 815 } 816 817 int 818 ioapic_set_smi(void *cookie, u_int pin) 819 { 820 struct ioapic *io; 821 822 io = (struct ioapic *)cookie; 823 if (pin >= io->io_numintr) 824 return (EINVAL); 825 if (io->io_pins[pin].io_irq == IRQ_SMI) 826 return (0); 827 if (io->io_pins[pin].io_irq < 0) 828 return (EINVAL); 829 io->io_pins[pin].io_bus = APIC_BUS_UNKNOWN; 830 io->io_pins[pin].io_irq = IRQ_SMI; 831 io->io_pins[pin].io_masked = 0; 832 io->io_pins[pin].io_edgetrigger = 1; 833 io->io_pins[pin].io_activehi = 1; 834 if (bootverbose) 835 printf("ioapic%u: Routing SMI -> intpin %d\n", 836 io->io_id, pin); 837 return (0); 838 } 839 840 int 841 ioapic_set_extint(void *cookie, u_int pin) 842 { 843 struct ioapic *io; 844 845 io = (struct ioapic *)cookie; 846 if (pin >= io->io_numintr) 847 return (EINVAL); 848 if (io->io_pins[pin].io_irq == IRQ_EXTINT) 849 return (0); 850 if (io->io_pins[pin].io_irq < 0) 851 return (EINVAL); 852 io->io_pins[pin].io_bus = APIC_BUS_UNKNOWN; 853 io->io_pins[pin].io_irq = IRQ_EXTINT; 854 if (enable_extint) 855 io->io_pins[pin].io_masked = 0; 856 else 857 io->io_pins[pin].io_masked = 1; 858 io->io_pins[pin].io_edgetrigger = 1; 859 io->io_pins[pin].io_activehi = 1; 860 if (bootverbose) 861 printf("ioapic%u: Routing external 8259A's -> intpin %d\n", 862 io->io_id, pin); 863 return (0); 864 } 865 866 int 867 ioapic_set_polarity(void *cookie, u_int pin, enum intr_polarity pol) 868 { 869 struct ioapic *io; 870 int activehi; 871 872 io = (struct ioapic *)cookie; 873 if (pin >= io->io_numintr || pol == INTR_POLARITY_CONFORM) 874 return (EINVAL); 875 if (io->io_pins[pin].io_irq < 0) 876 return (EINVAL); 877 activehi = (pol == INTR_POLARITY_HIGH); 878 if (io->io_pins[pin].io_activehi == activehi) 879 return (0); 880 io->io_pins[pin].io_activehi = activehi; 881 if (bootverbose) 882 printf("ioapic%u: intpin %d polarity: %s\n", io->io_id, pin, 883 pol == INTR_POLARITY_HIGH ? "high" : "low"); 884 return (0); 885 } 886 887 int 888 ioapic_set_triggermode(void *cookie, u_int pin, enum intr_trigger trigger) 889 { 890 struct ioapic *io; 891 int edgetrigger; 892 893 io = (struct ioapic *)cookie; 894 if (pin >= io->io_numintr || trigger == INTR_TRIGGER_CONFORM) 895 return (EINVAL); 896 if (io->io_pins[pin].io_irq < 0) 897 return (EINVAL); 898 edgetrigger = (trigger == INTR_TRIGGER_EDGE); 899 if (io->io_pins[pin].io_edgetrigger == edgetrigger) 900 return (0); 901 io->io_pins[pin].io_edgetrigger = edgetrigger; 902 if (bootverbose) 903 printf("ioapic%u: intpin %d trigger: %s\n", io->io_id, pin, 904 trigger == INTR_TRIGGER_EDGE ? "edge" : "level"); 905 return (0); 906 } 907 908 /* 909 * Register a complete I/O APIC object with the interrupt subsystem. 910 */ 911 void 912 ioapic_register(void *cookie) 913 { 914 struct ioapic_intsrc *pin; 915 struct ioapic *io; 916 volatile ioapic_t *apic; 917 uint32_t flags; 918 int i; 919 920 io = (struct ioapic *)cookie; 921 apic = io->io_addr; 922 mtx_lock_spin(&icu_lock); 923 flags = ioapic_read(apic, IOAPIC_VER) & IOART_VER_VERSION; 924 STAILQ_INSERT_TAIL(&ioapic_list, io, io_next); 925 mtx_unlock_spin(&icu_lock); 926 printf("ioapic%u <Version %u.%u> irqs %u-%u\n", 927 io->io_id, flags >> 4, flags & 0xf, io->io_intbase, 928 io->io_intbase + io->io_numintr - 1); 929 930 /* 931 * Reprogram pins to handle special case pins (such as NMI and 932 * SMI) and disable normal pins until a handler is registered. 933 */ 934 intr_register_pic(&io->io_pic); 935 for (i = 0, pin = io->io_pins; i < io->io_numintr; i++, pin++) 936 ioapic_reprogram_intpin(&pin->io_intsrc); 937 } 938 939 /* 940 * Add interrupt sources for I/O APIC interrupt pins. 941 */ 942 static void 943 ioapic_register_sources(struct pic *pic) 944 { 945 struct ioapic_intsrc *pin; 946 struct ioapic *io; 947 int i; 948 949 io = (struct ioapic *)pic; 950 for (i = 0, pin = io->io_pins; i < io->io_numintr; i++, pin++) { 951 if (pin->io_irq >= 0) 952 intr_register_source(&pin->io_intsrc); 953 } 954 } 955 956 /* A simple new-bus driver to consume PCI I/O APIC devices. */ 957 static int 958 ioapic_pci_probe(device_t dev) 959 { 960 961 if (pci_get_class(dev) == PCIC_BASEPERIPH && 962 pci_get_subclass(dev) == PCIS_BASEPERIPH_PIC) { 963 switch (pci_get_progif(dev)) { 964 case PCIP_BASEPERIPH_PIC_IO_APIC: 965 device_set_desc(dev, "IO APIC"); 966 break; 967 case PCIP_BASEPERIPH_PIC_IOX_APIC: 968 device_set_desc(dev, "IO(x) APIC"); 969 break; 970 default: 971 return (ENXIO); 972 } 973 device_quiet(dev); 974 return (-10000); 975 } 976 return (ENXIO); 977 } 978 979 static int 980 ioapic_pci_attach(device_t dev) 981 { 982 struct resource *res; 983 volatile ioapic_t *apic; 984 struct ioapic *io; 985 int rid; 986 u_int apic_id; 987 988 /* 989 * Try to match the enumerated ioapic. Match BAR start 990 * against io_paddr. Due to a fear that PCI window is not the 991 * same as the MADT reported io window, but an alias, read the 992 * APIC ID from the mapped BAR and match against it. 993 */ 994 rid = PCIR_BAR(0); 995 res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid, 996 RF_ACTIVE | RF_SHAREABLE); 997 if (res == NULL) { 998 if (bootverbose) 999 device_printf(dev, "cannot activate BAR0\n"); 1000 return (ENXIO); 1001 } 1002 apic = (volatile ioapic_t *)rman_get_virtual(res); 1003 if (rman_get_size(res) < IOAPIC_WND_SIZE) { 1004 if (bootverbose) 1005 device_printf(dev, 1006 "BAR0 too small (%jd) for IOAPIC window\n", 1007 (uintmax_t)rman_get_size(res)); 1008 goto fail; 1009 } 1010 mtx_lock_spin(&icu_lock); 1011 apic_id = ioapic_read(apic, IOAPIC_ID) >> APIC_ID_SHIFT; 1012 /* First match by io window address */ 1013 STAILQ_FOREACH(io, &ioapic_list, io_next) { 1014 if (io->io_paddr == (vm_paddr_t)rman_get_start(res)) 1015 goto found; 1016 } 1017 /* Then by apic id */ 1018 STAILQ_FOREACH(io, &ioapic_list, io_next) { 1019 if (io->io_hw_apic_id == apic_id) 1020 goto found; 1021 } 1022 mtx_unlock_spin(&icu_lock); 1023 if (bootverbose) 1024 device_printf(dev, 1025 "cannot match pci bar apic id %d against MADT, BAR0 %#jx\n", 1026 apic_id, (uintmax_t)rman_get_start(res)); 1027 fail: 1028 bus_release_resource(dev, SYS_RES_MEMORY, rid, res); 1029 return (ENXIO); 1030 found: 1031 KASSERT(io->pci_dev == NULL, 1032 ("ioapic %d pci_dev not NULL", io->io_id)); 1033 KASSERT(io->pci_wnd == NULL, 1034 ("ioapic %d pci_wnd not NULL", io->io_id)); 1035 1036 io->pci_dev = dev; 1037 io->pci_wnd = res; 1038 if (bootverbose && (io->io_paddr != (vm_paddr_t)rman_get_start(res) || 1039 io->io_hw_apic_id != apic_id)) { 1040 device_printf(dev, "pci%d:%d:%d:%d pci BAR0@%jx id %d " 1041 "MADT id %d hw id %d paddr@%jx\n", 1042 pci_get_domain(dev), pci_get_bus(dev), 1043 pci_get_slot(dev), pci_get_function(dev), 1044 (uintmax_t)rman_get_start(res), apic_id, 1045 io->io_apic_id, io->io_hw_apic_id, (uintmax_t)io->io_paddr); 1046 } 1047 mtx_unlock_spin(&icu_lock); 1048 return (0); 1049 } 1050 1051 static device_method_t ioapic_pci_methods[] = { 1052 /* Device interface */ 1053 DEVMETHOD(device_probe, ioapic_pci_probe), 1054 DEVMETHOD(device_attach, ioapic_pci_attach), 1055 { 0, 0 } 1056 }; 1057 1058 DEFINE_CLASS_0(ioapic, ioapic_pci_driver, ioapic_pci_methods, 0); 1059 1060 DRIVER_MODULE(ioapic, pci, ioapic_pci_driver, 0, 0); 1061 1062 int 1063 ioapic_get_rid(u_int apic_id, uint16_t *ridp) 1064 { 1065 struct ioapic *io; 1066 uintptr_t rid; 1067 int error; 1068 1069 mtx_lock_spin(&icu_lock); 1070 STAILQ_FOREACH(io, &ioapic_list, io_next) { 1071 if (io->io_apic_id == apic_id) 1072 break; 1073 } 1074 mtx_unlock_spin(&icu_lock); 1075 if (io == NULL || io->pci_dev == NULL) 1076 return (EINVAL); 1077 error = pci_get_id(io->pci_dev, PCI_ID_RID, &rid); 1078 if (error != 0) 1079 return (error); 1080 *ridp = rid; 1081 return (0); 1082 } 1083 1084 /* 1085 * A new-bus driver to consume the memory resources associated with 1086 * the APICs in the system. On some systems ACPI or PnPBIOS system 1087 * resource devices may already claim these resources. To keep from 1088 * breaking those devices, we attach ourself to the nexus device after 1089 * legacy0 and acpi0 and ignore any allocation failures. 1090 */ 1091 static void 1092 apic_identify(driver_t *driver, device_t parent) 1093 { 1094 1095 /* 1096 * Add at order 12. acpi0 is probed at order 10 and legacy0 1097 * is probed at order 11. 1098 */ 1099 if (lapic_paddr != 0) 1100 BUS_ADD_CHILD(parent, 12, "apic", 0); 1101 } 1102 1103 static int 1104 apic_probe(device_t dev) 1105 { 1106 1107 device_set_desc(dev, "APIC resources"); 1108 device_quiet(dev); 1109 return (0); 1110 } 1111 1112 static void 1113 apic_add_resource(device_t dev, int rid, vm_paddr_t base, size_t length) 1114 { 1115 int error; 1116 1117 error = bus_set_resource(dev, SYS_RES_MEMORY, rid, base, length); 1118 if (error) 1119 panic("apic_add_resource: resource %d failed set with %d", rid, 1120 error); 1121 bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid, RF_SHAREABLE); 1122 } 1123 1124 static int 1125 apic_attach(device_t dev) 1126 { 1127 struct ioapic *io; 1128 int i; 1129 1130 /* Reserve the local APIC. */ 1131 apic_add_resource(dev, 0, lapic_paddr, LAPIC_MEM_REGION); 1132 i = 1; 1133 STAILQ_FOREACH(io, &ioapic_list, io_next) { 1134 apic_add_resource(dev, i, io->io_paddr, IOAPIC_MEM_REGION); 1135 i++; 1136 } 1137 return (0); 1138 } 1139 1140 static device_method_t apic_methods[] = { 1141 /* Device interface */ 1142 DEVMETHOD(device_identify, apic_identify), 1143 DEVMETHOD(device_probe, apic_probe), 1144 DEVMETHOD(device_attach, apic_attach), 1145 { 0, 0 } 1146 }; 1147 1148 DEFINE_CLASS_0(apic, apic_driver, apic_methods, 0); 1149 1150 DRIVER_MODULE(apic, nexus, apic_driver, 0, 0); 1151 1152 #include "opt_ddb.h" 1153 1154 #ifdef DDB 1155 #include <ddb/ddb.h> 1156 1157 static const char * 1158 ioapic_delivery_mode(uint32_t mode) 1159 { 1160 1161 switch (mode) { 1162 case IOART_DELFIXED: 1163 return ("fixed"); 1164 case IOART_DELLOPRI: 1165 return ("lowestpri"); 1166 case IOART_DELSMI: 1167 return ("SMI"); 1168 case IOART_DELRSV1: 1169 return ("rsrvd1"); 1170 case IOART_DELNMI: 1171 return ("NMI"); 1172 case IOART_DELINIT: 1173 return ("INIT"); 1174 case IOART_DELRSV2: 1175 return ("rsrvd2"); 1176 case IOART_DELEXINT: 1177 return ("ExtINT"); 1178 default: 1179 return (""); 1180 } 1181 } 1182 1183 static u_int 1184 db_ioapic_read(volatile ioapic_t *apic, int reg) 1185 { 1186 1187 apic->ioregsel = reg; 1188 return (apic->iowin); 1189 } 1190 1191 static void 1192 db_show_ioapic_one(volatile ioapic_t *io_addr) 1193 { 1194 uint32_t r, lo, hi; 1195 int mre, i; 1196 1197 r = db_ioapic_read(io_addr, IOAPIC_VER); 1198 mre = (r & IOART_VER_MAXREDIR) >> MAXREDIRSHIFT; 1199 db_printf("Id 0x%08x Ver 0x%02x MRE %d\n", 1200 db_ioapic_read(io_addr, IOAPIC_ID), r & IOART_VER_VERSION, mre); 1201 for (i = 0; i < mre; i++) { 1202 lo = db_ioapic_read(io_addr, IOAPIC_REDTBL_LO(i)); 1203 hi = db_ioapic_read(io_addr, IOAPIC_REDTBL_HI(i)); 1204 db_printf(" pin %d Dest %s/%x %smasked Trig %s RemoteIRR %d " 1205 "Polarity %s Status %s DeliveryMode %s Vec %d\n", i, 1206 (lo & IOART_DESTMOD) == IOART_DESTLOG ? "log" : "phy", 1207 (hi & IOART_DEST) >> 24, 1208 (lo & IOART_INTMASK) == IOART_INTMSET ? "" : "not", 1209 (lo & IOART_TRGRMOD) == IOART_TRGRLVL ? "lvl" : "edge", 1210 (lo & IOART_REM_IRR) == IOART_REM_IRR ? 1 : 0, 1211 (lo & IOART_INTPOL) == IOART_INTALO ? "low" : "high", 1212 (lo & IOART_DELIVS) == IOART_DELIVS ? "pend" : "idle", 1213 ioapic_delivery_mode(lo & IOART_DELMOD), 1214 (lo & IOART_INTVEC)); 1215 } 1216 } 1217 1218 DB_SHOW_COMMAND(ioapic, db_show_ioapic) 1219 { 1220 struct ioapic *ioapic; 1221 int idx, i; 1222 1223 if (!have_addr) { 1224 db_printf("usage: show ioapic index\n"); 1225 return; 1226 } 1227 1228 idx = (int)addr; 1229 i = 0; 1230 STAILQ_FOREACH(ioapic, &ioapic_list, io_next) { 1231 if (idx == i) { 1232 db_show_ioapic_one(ioapic->io_addr); 1233 break; 1234 } 1235 i++; 1236 } 1237 } 1238 1239 DB_SHOW_ALL_COMMAND(ioapics, db_show_all_ioapics) 1240 { 1241 struct ioapic *ioapic; 1242 1243 STAILQ_FOREACH(ioapic, &ioapic_list, io_next) 1244 db_show_ioapic_one(ioapic->io_addr); 1245 } 1246 #endif 1247