1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD 3 * 4 * Copyright (c) 2003 John Baldwin <jhb@FreeBSD.org> 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 25 * SUCH DAMAGE. 26 */ 27 28 #include <sys/cdefs.h> 29 __FBSDID("$FreeBSD$"); 30 31 #include "opt_acpi.h" 32 #include "opt_iommu.h" 33 #include "opt_isa.h" 34 35 #include <sys/param.h> 36 #include <sys/systm.h> 37 #include <sys/bus.h> 38 #include <sys/kernel.h> 39 #include <sys/lock.h> 40 #include <sys/malloc.h> 41 #include <sys/module.h> 42 #include <sys/mutex.h> 43 #include <sys/rman.h> 44 #include <sys/sysctl.h> 45 46 #include <dev/pci/pcireg.h> 47 #include <dev/pci/pcivar.h> 48 49 #include <vm/vm.h> 50 #include <vm/pmap.h> 51 52 #include <x86/apicreg.h> 53 #include <machine/frame.h> 54 #include <machine/intr_machdep.h> 55 #include <x86/apicvar.h> 56 #include <machine/resource.h> 57 #include <machine/segments.h> 58 #include <x86/iommu/iommu_intrmap.h> 59 60 #define IOAPIC_ISA_INTS 16 61 #define IOAPIC_MEM_REGION 32 62 #define IOAPIC_REDTBL_LO(i) (IOAPIC_REDTBL + (i) * 2) 63 #define IOAPIC_REDTBL_HI(i) (IOAPIC_REDTBL_LO(i) + 1) 64 65 static MALLOC_DEFINE(M_IOAPIC, "io_apic", "I/O APIC structures"); 66 67 /* 68 * I/O APIC interrupt source driver. Each pin is assigned an IRQ cookie 69 * as laid out in the ACPI System Interrupt number model where each I/O 70 * APIC has a contiguous chunk of the System Interrupt address space. 71 * We assume that IRQs 1 - 15 behave like ISA IRQs and that all other 72 * IRQs behave as PCI IRQs by default. We also assume that the pin for 73 * IRQ 0 is actually an ExtINT pin. The apic enumerators override the 74 * configuration of individual pins as indicated by their tables. 75 * 76 * Documentation for the I/O APIC: "82093AA I/O Advanced Programmable 77 * Interrupt Controller (IOAPIC)", May 1996, Intel Corp. 78 * ftp://download.intel.com/design/chipsets/datashts/29056601.pdf 79 */ 80 81 struct ioapic_intsrc { 82 struct intsrc io_intsrc; 83 int io_irq; 84 u_int io_intpin:8; 85 u_int io_vector:8; 86 u_int io_cpu; 87 u_int io_activehi:1; 88 u_int io_edgetrigger:1; 89 u_int io_masked:1; 90 int io_bus:4; 91 uint32_t io_lowreg; 92 u_int io_remap_cookie; 93 }; 94 95 struct ioapic { 96 struct pic io_pic; 97 u_int io_id:8; /* logical ID */ 98 u_int io_apic_id:8; /* Id as enumerated by MADT */ 99 u_int io_hw_apic_id:8; /* Content of APIC ID register */ 100 u_int io_intbase:8; /* System Interrupt base */ 101 u_int io_numintr:8; 102 u_int io_haseoi:1; 103 volatile ioapic_t *io_addr; /* XXX: should use bus_space */ 104 vm_paddr_t io_paddr; 105 STAILQ_ENTRY(ioapic) io_next; 106 device_t pci_dev; /* matched pci device, if found */ 107 struct resource *pci_wnd; /* BAR 0, should be same or alias to 108 io_paddr */ 109 struct ioapic_intsrc io_pins[0]; 110 }; 111 112 static u_int ioapic_read(volatile ioapic_t *apic, int reg); 113 static void ioapic_write(volatile ioapic_t *apic, int reg, u_int val); 114 static const char *ioapic_bus_string(int bus_type); 115 static void ioapic_print_irq(struct ioapic_intsrc *intpin); 116 static void ioapic_register_sources(struct pic *pic); 117 static void ioapic_enable_source(struct intsrc *isrc); 118 static void ioapic_disable_source(struct intsrc *isrc, int eoi); 119 static void ioapic_eoi_source(struct intsrc *isrc); 120 static void ioapic_enable_intr(struct intsrc *isrc); 121 static void ioapic_disable_intr(struct intsrc *isrc); 122 static int ioapic_vector(struct intsrc *isrc); 123 static int ioapic_source_pending(struct intsrc *isrc); 124 static int ioapic_config_intr(struct intsrc *isrc, enum intr_trigger trig, 125 enum intr_polarity pol); 126 static void ioapic_resume(struct pic *pic, bool suspend_cancelled); 127 static int ioapic_assign_cpu(struct intsrc *isrc, u_int apic_id); 128 static void ioapic_program_intpin(struct ioapic_intsrc *intpin); 129 static void ioapic_reprogram_intpin(struct intsrc *isrc); 130 131 static STAILQ_HEAD(,ioapic) ioapic_list = STAILQ_HEAD_INITIALIZER(ioapic_list); 132 struct pic ioapic_template = { 133 .pic_register_sources = ioapic_register_sources, 134 .pic_enable_source = ioapic_enable_source, 135 .pic_disable_source = ioapic_disable_source, 136 .pic_eoi_source = ioapic_eoi_source, 137 .pic_enable_intr = ioapic_enable_intr, 138 .pic_disable_intr = ioapic_disable_intr, 139 .pic_vector = ioapic_vector, 140 .pic_source_pending = ioapic_source_pending, 141 .pic_suspend = NULL, 142 .pic_resume = ioapic_resume, 143 .pic_config_intr = ioapic_config_intr, 144 .pic_assign_cpu = ioapic_assign_cpu, 145 .pic_reprogram_pin = ioapic_reprogram_intpin, 146 }; 147 148 static u_int next_ioapic_base; 149 static u_int next_id; 150 151 static int enable_extint; 152 SYSCTL_INT(_hw_apic, OID_AUTO, enable_extint, CTLFLAG_RDTUN, &enable_extint, 0, 153 "Enable the ExtINT pin in the first I/O APIC"); 154 155 static void 156 _ioapic_eoi_source(struct intsrc *isrc, int locked) 157 { 158 struct ioapic_intsrc *src; 159 struct ioapic *io; 160 volatile uint32_t *apic_eoi; 161 uint32_t low1; 162 163 lapic_eoi(); 164 if (!lapic_eoi_suppression) 165 return; 166 src = (struct ioapic_intsrc *)isrc; 167 if (src->io_edgetrigger) 168 return; 169 io = (struct ioapic *)isrc->is_pic; 170 171 /* 172 * Handle targeted EOI for level-triggered pins, if broadcast 173 * EOI suppression is supported by LAPICs. 174 */ 175 if (io->io_haseoi) { 176 /* 177 * If IOAPIC has EOI Register, simply write vector 178 * number into the reg. 179 */ 180 apic_eoi = (volatile uint32_t *)((volatile char *) 181 io->io_addr + IOAPIC_EOIR); 182 *apic_eoi = src->io_vector; 183 } else { 184 /* 185 * Otherwise, if IO-APIC is too old to provide EOIR, 186 * do what Intel did for the Linux kernel. Temporary 187 * switch the pin to edge-trigger and back, masking 188 * the pin during the trick. 189 */ 190 if (!locked) 191 mtx_lock_spin(&icu_lock); 192 low1 = src->io_lowreg; 193 low1 &= ~IOART_TRGRLVL; 194 low1 |= IOART_TRGREDG | IOART_INTMSET; 195 ioapic_write(io->io_addr, IOAPIC_REDTBL_LO(src->io_intpin), 196 low1); 197 low1 = src->io_lowreg; 198 if (src->io_masked != 0) 199 low1 |= IOART_INTMSET; 200 ioapic_write(io->io_addr, IOAPIC_REDTBL_LO(src->io_intpin), 201 low1); 202 if (!locked) 203 mtx_unlock_spin(&icu_lock); 204 } 205 } 206 207 static u_int 208 ioapic_read(volatile ioapic_t *apic, int reg) 209 { 210 211 mtx_assert(&icu_lock, MA_OWNED); 212 apic->ioregsel = reg; 213 return (apic->iowin); 214 } 215 216 static void 217 ioapic_write(volatile ioapic_t *apic, int reg, u_int val) 218 { 219 220 mtx_assert(&icu_lock, MA_OWNED); 221 apic->ioregsel = reg; 222 apic->iowin = val; 223 } 224 225 static const char * 226 ioapic_bus_string(int bus_type) 227 { 228 229 switch (bus_type) { 230 case APIC_BUS_ISA: 231 return ("ISA"); 232 case APIC_BUS_EISA: 233 return ("EISA"); 234 case APIC_BUS_PCI: 235 return ("PCI"); 236 default: 237 return ("unknown"); 238 } 239 } 240 241 static void 242 ioapic_print_irq(struct ioapic_intsrc *intpin) 243 { 244 245 switch (intpin->io_irq) { 246 case IRQ_DISABLED: 247 printf("disabled"); 248 break; 249 case IRQ_EXTINT: 250 printf("ExtINT"); 251 break; 252 case IRQ_NMI: 253 printf("NMI"); 254 break; 255 case IRQ_SMI: 256 printf("SMI"); 257 break; 258 default: 259 printf("%s IRQ %d", ioapic_bus_string(intpin->io_bus), 260 intpin->io_irq); 261 } 262 } 263 264 static void 265 ioapic_enable_source(struct intsrc *isrc) 266 { 267 struct ioapic_intsrc *intpin = (struct ioapic_intsrc *)isrc; 268 struct ioapic *io = (struct ioapic *)isrc->is_pic; 269 uint32_t flags; 270 271 mtx_lock_spin(&icu_lock); 272 if (intpin->io_masked) { 273 flags = intpin->io_lowreg & ~IOART_INTMASK; 274 ioapic_write(io->io_addr, IOAPIC_REDTBL_LO(intpin->io_intpin), 275 flags); 276 intpin->io_masked = 0; 277 } 278 mtx_unlock_spin(&icu_lock); 279 } 280 281 static void 282 ioapic_disable_source(struct intsrc *isrc, int eoi) 283 { 284 struct ioapic_intsrc *intpin = (struct ioapic_intsrc *)isrc; 285 struct ioapic *io = (struct ioapic *)isrc->is_pic; 286 uint32_t flags; 287 288 mtx_lock_spin(&icu_lock); 289 if (!intpin->io_masked && !intpin->io_edgetrigger) { 290 flags = intpin->io_lowreg | IOART_INTMSET; 291 ioapic_write(io->io_addr, IOAPIC_REDTBL_LO(intpin->io_intpin), 292 flags); 293 intpin->io_masked = 1; 294 } 295 296 if (eoi == PIC_EOI) 297 _ioapic_eoi_source(isrc, 1); 298 299 mtx_unlock_spin(&icu_lock); 300 } 301 302 static void 303 ioapic_eoi_source(struct intsrc *isrc) 304 { 305 306 _ioapic_eoi_source(isrc, 0); 307 } 308 309 /* 310 * Completely program an intpin based on the data in its interrupt source 311 * structure. 312 */ 313 static void 314 ioapic_program_intpin(struct ioapic_intsrc *intpin) 315 { 316 struct ioapic *io = (struct ioapic *)intpin->io_intsrc.is_pic; 317 uint32_t low, high; 318 #ifdef IOMMU 319 int error; 320 #endif 321 322 /* 323 * If a pin is completely invalid or if it is valid but hasn't 324 * been enabled yet, just ensure that the pin is masked. 325 */ 326 mtx_assert(&icu_lock, MA_OWNED); 327 if (intpin->io_irq == IRQ_DISABLED || (intpin->io_irq >= 0 && 328 intpin->io_vector == 0)) { 329 low = ioapic_read(io->io_addr, 330 IOAPIC_REDTBL_LO(intpin->io_intpin)); 331 if ((low & IOART_INTMASK) == IOART_INTMCLR) 332 ioapic_write(io->io_addr, 333 IOAPIC_REDTBL_LO(intpin->io_intpin), 334 low | IOART_INTMSET); 335 #ifdef IOMMU 336 mtx_unlock_spin(&icu_lock); 337 iommu_unmap_ioapic_intr(io->io_apic_id, 338 &intpin->io_remap_cookie); 339 mtx_lock_spin(&icu_lock); 340 #endif 341 return; 342 } 343 344 #ifdef IOMMU 345 mtx_unlock_spin(&icu_lock); 346 error = iommu_map_ioapic_intr(io->io_apic_id, 347 intpin->io_cpu, intpin->io_vector, intpin->io_edgetrigger, 348 intpin->io_activehi, intpin->io_irq, &intpin->io_remap_cookie, 349 &high, &low); 350 mtx_lock_spin(&icu_lock); 351 if (error == 0) { 352 ioapic_write(io->io_addr, IOAPIC_REDTBL_HI(intpin->io_intpin), 353 high); 354 intpin->io_lowreg = low; 355 ioapic_write(io->io_addr, IOAPIC_REDTBL_LO(intpin->io_intpin), 356 low); 357 return; 358 } else if (error != EOPNOTSUPP) { 359 return; 360 } 361 #endif 362 363 /* 364 * Set the destination. Note that with Intel interrupt remapping, 365 * the previously reserved bits 55:48 now have a purpose so ensure 366 * these are zero. 367 */ 368 low = IOART_DESTPHY; 369 high = intpin->io_cpu << APIC_ID_SHIFT; 370 371 /* Program the rest of the low word. */ 372 if (intpin->io_edgetrigger) 373 low |= IOART_TRGREDG; 374 else 375 low |= IOART_TRGRLVL; 376 if (intpin->io_activehi) 377 low |= IOART_INTAHI; 378 else 379 low |= IOART_INTALO; 380 if (intpin->io_masked) 381 low |= IOART_INTMSET; 382 switch (intpin->io_irq) { 383 case IRQ_EXTINT: 384 KASSERT(intpin->io_edgetrigger, 385 ("ExtINT not edge triggered")); 386 low |= IOART_DELEXINT; 387 break; 388 case IRQ_NMI: 389 KASSERT(intpin->io_edgetrigger, 390 ("NMI not edge triggered")); 391 low |= IOART_DELNMI; 392 break; 393 case IRQ_SMI: 394 KASSERT(intpin->io_edgetrigger, 395 ("SMI not edge triggered")); 396 low |= IOART_DELSMI; 397 break; 398 default: 399 KASSERT(intpin->io_vector != 0, ("No vector for IRQ %u", 400 intpin->io_irq)); 401 low |= IOART_DELFIXED | intpin->io_vector; 402 } 403 404 /* Write the values to the APIC. */ 405 ioapic_write(io->io_addr, IOAPIC_REDTBL_HI(intpin->io_intpin), high); 406 intpin->io_lowreg = low; 407 ioapic_write(io->io_addr, IOAPIC_REDTBL_LO(intpin->io_intpin), low); 408 } 409 410 static void 411 ioapic_reprogram_intpin(struct intsrc *isrc) 412 { 413 414 mtx_lock_spin(&icu_lock); 415 ioapic_program_intpin((struct ioapic_intsrc *)isrc); 416 mtx_unlock_spin(&icu_lock); 417 } 418 419 static int 420 ioapic_assign_cpu(struct intsrc *isrc, u_int apic_id) 421 { 422 struct ioapic_intsrc *intpin = (struct ioapic_intsrc *)isrc; 423 struct ioapic *io = (struct ioapic *)isrc->is_pic; 424 u_int old_vector, new_vector; 425 u_int old_id; 426 427 /* 428 * On Hyper-V: 429 * - Stick to the first cpu for all I/O APIC pins. 430 * - And don't allow destination cpu changes. 431 */ 432 if (vm_guest == VM_GUEST_HV) { 433 if (intpin->io_vector) 434 return (EINVAL); 435 else 436 apic_id = 0; 437 } 438 439 /* 440 * keep 1st core as the destination for NMI 441 */ 442 if (intpin->io_irq == IRQ_NMI) 443 apic_id = 0; 444 445 /* 446 * Set us up to free the old irq. 447 */ 448 old_vector = intpin->io_vector; 449 old_id = intpin->io_cpu; 450 if (old_vector && apic_id == old_id) 451 return (0); 452 453 /* 454 * Allocate an APIC vector for this interrupt pin. Once 455 * we have a vector we program the interrupt pin. 456 */ 457 new_vector = apic_alloc_vector(apic_id, intpin->io_irq); 458 if (new_vector == 0) 459 return (ENOSPC); 460 461 /* 462 * Mask the old intpin if it is enabled while it is migrated. 463 * 464 * At least some level-triggered interrupts seem to need the 465 * extra DELAY() to avoid being stuck in a non-EOI'd state. 466 */ 467 mtx_lock_spin(&icu_lock); 468 if (!intpin->io_masked && !intpin->io_edgetrigger) { 469 ioapic_write(io->io_addr, IOAPIC_REDTBL_LO(intpin->io_intpin), 470 intpin->io_lowreg | IOART_INTMSET); 471 mtx_unlock_spin(&icu_lock); 472 DELAY(100); 473 mtx_lock_spin(&icu_lock); 474 } 475 476 intpin->io_cpu = apic_id; 477 intpin->io_vector = new_vector; 478 if (isrc->is_handlers > 0) 479 apic_enable_vector(intpin->io_cpu, intpin->io_vector); 480 if (bootverbose) { 481 printf("ioapic%u: routing intpin %u (", io->io_id, 482 intpin->io_intpin); 483 ioapic_print_irq(intpin); 484 printf(") to lapic %u vector %u\n", intpin->io_cpu, 485 intpin->io_vector); 486 } 487 ioapic_program_intpin(intpin); 488 mtx_unlock_spin(&icu_lock); 489 490 /* 491 * Free the old vector after the new one is established. This is done 492 * to prevent races where we could miss an interrupt. 493 */ 494 if (old_vector) { 495 if (isrc->is_handlers > 0) 496 apic_disable_vector(old_id, old_vector); 497 apic_free_vector(old_id, old_vector, intpin->io_irq); 498 } 499 return (0); 500 } 501 502 static void 503 ioapic_enable_intr(struct intsrc *isrc) 504 { 505 struct ioapic_intsrc *intpin = (struct ioapic_intsrc *)isrc; 506 507 if (intpin->io_vector == 0) 508 if (ioapic_assign_cpu(isrc, intr_next_cpu(isrc->is_domain)) != 0) 509 panic("Couldn't find an APIC vector for IRQ %d", 510 intpin->io_irq); 511 apic_enable_vector(intpin->io_cpu, intpin->io_vector); 512 } 513 514 static void 515 ioapic_disable_intr(struct intsrc *isrc) 516 { 517 struct ioapic_intsrc *intpin = (struct ioapic_intsrc *)isrc; 518 u_int vector; 519 520 if (intpin->io_vector != 0) { 521 /* Mask this interrupt pin and free its APIC vector. */ 522 vector = intpin->io_vector; 523 apic_disable_vector(intpin->io_cpu, vector); 524 mtx_lock_spin(&icu_lock); 525 intpin->io_masked = 1; 526 intpin->io_vector = 0; 527 ioapic_program_intpin(intpin); 528 mtx_unlock_spin(&icu_lock); 529 apic_free_vector(intpin->io_cpu, vector, intpin->io_irq); 530 } 531 } 532 533 static int 534 ioapic_vector(struct intsrc *isrc) 535 { 536 struct ioapic_intsrc *pin; 537 538 pin = (struct ioapic_intsrc *)isrc; 539 return (pin->io_irq); 540 } 541 542 static int 543 ioapic_source_pending(struct intsrc *isrc) 544 { 545 struct ioapic_intsrc *intpin = (struct ioapic_intsrc *)isrc; 546 547 if (intpin->io_vector == 0) 548 return 0; 549 return (lapic_intr_pending(intpin->io_vector)); 550 } 551 552 static int 553 ioapic_config_intr(struct intsrc *isrc, enum intr_trigger trig, 554 enum intr_polarity pol) 555 { 556 struct ioapic_intsrc *intpin = (struct ioapic_intsrc *)isrc; 557 struct ioapic *io = (struct ioapic *)isrc->is_pic; 558 int changed; 559 560 KASSERT(!(trig == INTR_TRIGGER_CONFORM || pol == INTR_POLARITY_CONFORM), 561 ("%s: Conforming trigger or polarity\n", __func__)); 562 563 /* 564 * EISA interrupts always use active high polarity, so don't allow 565 * them to be set to active low. 566 * 567 * XXX: Should we write to the ELCR if the trigger mode changes for 568 * an EISA IRQ or an ISA IRQ with the ELCR present? 569 */ 570 mtx_lock_spin(&icu_lock); 571 if (intpin->io_bus == APIC_BUS_EISA) 572 pol = INTR_POLARITY_HIGH; 573 changed = 0; 574 if (intpin->io_edgetrigger != (trig == INTR_TRIGGER_EDGE)) { 575 if (bootverbose) 576 printf("ioapic%u: Changing trigger for pin %u to %s\n", 577 io->io_id, intpin->io_intpin, 578 trig == INTR_TRIGGER_EDGE ? "edge" : "level"); 579 intpin->io_edgetrigger = (trig == INTR_TRIGGER_EDGE); 580 changed++; 581 } 582 if (intpin->io_activehi != (pol == INTR_POLARITY_HIGH)) { 583 if (bootverbose) 584 printf("ioapic%u: Changing polarity for pin %u to %s\n", 585 io->io_id, intpin->io_intpin, 586 pol == INTR_POLARITY_HIGH ? "high" : "low"); 587 intpin->io_activehi = (pol == INTR_POLARITY_HIGH); 588 changed++; 589 } 590 if (changed) 591 ioapic_program_intpin(intpin); 592 mtx_unlock_spin(&icu_lock); 593 return (0); 594 } 595 596 static void 597 ioapic_resume(struct pic *pic, bool suspend_cancelled) 598 { 599 struct ioapic *io = (struct ioapic *)pic; 600 int i; 601 602 mtx_lock_spin(&icu_lock); 603 for (i = 0; i < io->io_numintr; i++) 604 ioapic_program_intpin(&io->io_pins[i]); 605 mtx_unlock_spin(&icu_lock); 606 } 607 608 /* 609 * Create a plain I/O APIC object. 610 */ 611 void * 612 ioapic_create(vm_paddr_t addr, int32_t apic_id, int intbase) 613 { 614 struct ioapic *io; 615 struct ioapic_intsrc *intpin; 616 volatile ioapic_t *apic; 617 u_int numintr, i; 618 uint32_t value; 619 620 /* Map the register window so we can access the device. */ 621 apic = pmap_mapdev(addr, IOAPIC_MEM_REGION); 622 mtx_lock_spin(&icu_lock); 623 value = ioapic_read(apic, IOAPIC_VER); 624 mtx_unlock_spin(&icu_lock); 625 626 /* If it's version register doesn't seem to work, punt. */ 627 if (value == 0xffffffff) { 628 pmap_unmapdev((vm_offset_t)apic, IOAPIC_MEM_REGION); 629 return (NULL); 630 } 631 632 /* Determine the number of vectors and set the APIC ID. */ 633 numintr = ((value & IOART_VER_MAXREDIR) >> MAXREDIRSHIFT) + 1; 634 io = malloc(sizeof(struct ioapic) + 635 numintr * sizeof(struct ioapic_intsrc), M_IOAPIC, M_WAITOK); 636 io->io_pic = ioapic_template; 637 io->pci_dev = NULL; 638 io->pci_wnd = NULL; 639 mtx_lock_spin(&icu_lock); 640 io->io_id = next_id++; 641 io->io_hw_apic_id = ioapic_read(apic, IOAPIC_ID) >> APIC_ID_SHIFT; 642 io->io_apic_id = apic_id == -1 ? io->io_hw_apic_id : apic_id; 643 mtx_unlock_spin(&icu_lock); 644 if (io->io_hw_apic_id != apic_id) 645 printf("ioapic%u: MADT APIC ID %d != hw id %d\n", io->io_id, 646 apic_id, io->io_hw_apic_id); 647 if (intbase == -1) { 648 intbase = next_ioapic_base; 649 printf("ioapic%u: Assuming intbase of %d\n", io->io_id, 650 intbase); 651 } else if (intbase != next_ioapic_base && bootverbose) 652 printf("ioapic%u: WARNING: intbase %d != expected base %d\n", 653 io->io_id, intbase, next_ioapic_base); 654 io->io_intbase = intbase; 655 next_ioapic_base = intbase + numintr; 656 if (next_ioapic_base > num_io_irqs) 657 num_io_irqs = next_ioapic_base; 658 io->io_numintr = numintr; 659 io->io_addr = apic; 660 io->io_paddr = addr; 661 662 if (bootverbose) { 663 printf("ioapic%u: ver 0x%02x maxredir 0x%02x\n", io->io_id, 664 (value & IOART_VER_VERSION), (value & IOART_VER_MAXREDIR) 665 >> MAXREDIRSHIFT); 666 } 667 /* 668 * The summary information about IO-APIC versions is taken from 669 * the Linux kernel source: 670 * 0Xh 82489DX 671 * 1Xh I/OAPIC or I/O(x)APIC which are not PCI 2.2 Compliant 672 * 2Xh I/O(x)APIC which is PCI 2.2 Compliant 673 * 30h-FFh Reserved 674 * IO-APICs with version >= 0x20 have working EOIR register. 675 */ 676 io->io_haseoi = (value & IOART_VER_VERSION) >= 0x20; 677 678 /* 679 * Initialize pins. Start off with interrupts disabled. Default 680 * to active-hi and edge-triggered for ISA interrupts and active-lo 681 * and level-triggered for all others. 682 */ 683 bzero(io->io_pins, sizeof(struct ioapic_intsrc) * numintr); 684 mtx_lock_spin(&icu_lock); 685 for (i = 0, intpin = io->io_pins; i < numintr; i++, intpin++) { 686 intpin->io_intsrc.is_pic = (struct pic *)io; 687 intpin->io_intpin = i; 688 intpin->io_irq = intbase + i; 689 690 /* 691 * Assume that pin 0 on the first I/O APIC is an ExtINT pin. 692 * Assume that pins 1-15 are ISA interrupts and that all 693 * other pins are PCI interrupts. 694 */ 695 if (intpin->io_irq == 0) 696 ioapic_set_extint(io, i); 697 else if (intpin->io_irq < IOAPIC_ISA_INTS) { 698 intpin->io_bus = APIC_BUS_ISA; 699 intpin->io_activehi = 1; 700 intpin->io_edgetrigger = 1; 701 intpin->io_masked = 1; 702 } else { 703 intpin->io_bus = APIC_BUS_PCI; 704 intpin->io_activehi = 0; 705 intpin->io_edgetrigger = 0; 706 intpin->io_masked = 1; 707 } 708 709 /* 710 * Route interrupts to the BSP by default. Interrupts may 711 * be routed to other CPUs later after they are enabled. 712 */ 713 intpin->io_cpu = PCPU_GET(apic_id); 714 value = ioapic_read(apic, IOAPIC_REDTBL_LO(i)); 715 ioapic_write(apic, IOAPIC_REDTBL_LO(i), value | IOART_INTMSET); 716 #ifdef IOMMU 717 /* dummy, but sets cookie */ 718 mtx_unlock_spin(&icu_lock); 719 iommu_map_ioapic_intr(io->io_apic_id, 720 intpin->io_cpu, intpin->io_vector, intpin->io_edgetrigger, 721 intpin->io_activehi, intpin->io_irq, 722 &intpin->io_remap_cookie, NULL, NULL); 723 mtx_lock_spin(&icu_lock); 724 #endif 725 } 726 mtx_unlock_spin(&icu_lock); 727 728 return (io); 729 } 730 731 int 732 ioapic_get_vector(void *cookie, u_int pin) 733 { 734 struct ioapic *io; 735 736 io = (struct ioapic *)cookie; 737 if (pin >= io->io_numintr) 738 return (-1); 739 return (io->io_pins[pin].io_irq); 740 } 741 742 int 743 ioapic_disable_pin(void *cookie, u_int pin) 744 { 745 struct ioapic *io; 746 747 io = (struct ioapic *)cookie; 748 if (pin >= io->io_numintr) 749 return (EINVAL); 750 if (io->io_pins[pin].io_irq == IRQ_DISABLED) 751 return (EINVAL); 752 io->io_pins[pin].io_irq = IRQ_DISABLED; 753 if (bootverbose) 754 printf("ioapic%u: intpin %d disabled\n", io->io_id, pin); 755 return (0); 756 } 757 758 int 759 ioapic_remap_vector(void *cookie, u_int pin, int vector) 760 { 761 struct ioapic *io; 762 763 io = (struct ioapic *)cookie; 764 if (pin >= io->io_numintr || vector < 0) 765 return (EINVAL); 766 if (io->io_pins[pin].io_irq < 0) 767 return (EINVAL); 768 io->io_pins[pin].io_irq = vector; 769 if (bootverbose) 770 printf("ioapic%u: Routing IRQ %d -> intpin %d\n", io->io_id, 771 vector, pin); 772 return (0); 773 } 774 775 int 776 ioapic_set_bus(void *cookie, u_int pin, int bus_type) 777 { 778 struct ioapic *io; 779 780 if (bus_type < 0 || bus_type > APIC_BUS_MAX) 781 return (EINVAL); 782 io = (struct ioapic *)cookie; 783 if (pin >= io->io_numintr) 784 return (EINVAL); 785 if (io->io_pins[pin].io_irq < 0) 786 return (EINVAL); 787 if (io->io_pins[pin].io_bus == bus_type) 788 return (0); 789 io->io_pins[pin].io_bus = bus_type; 790 if (bootverbose) 791 printf("ioapic%u: intpin %d bus %s\n", io->io_id, pin, 792 ioapic_bus_string(bus_type)); 793 return (0); 794 } 795 796 int 797 ioapic_set_nmi(void *cookie, u_int pin) 798 { 799 struct ioapic *io; 800 801 io = (struct ioapic *)cookie; 802 if (pin >= io->io_numintr) 803 return (EINVAL); 804 if (io->io_pins[pin].io_irq == IRQ_NMI) 805 return (0); 806 if (io->io_pins[pin].io_irq < 0) 807 return (EINVAL); 808 io->io_pins[pin].io_bus = APIC_BUS_UNKNOWN; 809 io->io_pins[pin].io_irq = IRQ_NMI; 810 io->io_pins[pin].io_masked = 0; 811 io->io_pins[pin].io_edgetrigger = 1; 812 io->io_pins[pin].io_activehi = 1; 813 if (bootverbose) 814 printf("ioapic%u: Routing NMI -> intpin %d\n", 815 io->io_id, pin); 816 return (0); 817 } 818 819 int 820 ioapic_set_smi(void *cookie, u_int pin) 821 { 822 struct ioapic *io; 823 824 io = (struct ioapic *)cookie; 825 if (pin >= io->io_numintr) 826 return (EINVAL); 827 if (io->io_pins[pin].io_irq == IRQ_SMI) 828 return (0); 829 if (io->io_pins[pin].io_irq < 0) 830 return (EINVAL); 831 io->io_pins[pin].io_bus = APIC_BUS_UNKNOWN; 832 io->io_pins[pin].io_irq = IRQ_SMI; 833 io->io_pins[pin].io_masked = 0; 834 io->io_pins[pin].io_edgetrigger = 1; 835 io->io_pins[pin].io_activehi = 1; 836 if (bootverbose) 837 printf("ioapic%u: Routing SMI -> intpin %d\n", 838 io->io_id, pin); 839 return (0); 840 } 841 842 int 843 ioapic_set_extint(void *cookie, u_int pin) 844 { 845 struct ioapic *io; 846 847 io = (struct ioapic *)cookie; 848 if (pin >= io->io_numintr) 849 return (EINVAL); 850 if (io->io_pins[pin].io_irq == IRQ_EXTINT) 851 return (0); 852 if (io->io_pins[pin].io_irq < 0) 853 return (EINVAL); 854 io->io_pins[pin].io_bus = APIC_BUS_UNKNOWN; 855 io->io_pins[pin].io_irq = IRQ_EXTINT; 856 if (enable_extint) 857 io->io_pins[pin].io_masked = 0; 858 else 859 io->io_pins[pin].io_masked = 1; 860 io->io_pins[pin].io_edgetrigger = 1; 861 io->io_pins[pin].io_activehi = 1; 862 if (bootverbose) 863 printf("ioapic%u: Routing external 8259A's -> intpin %d\n", 864 io->io_id, pin); 865 return (0); 866 } 867 868 int 869 ioapic_set_polarity(void *cookie, u_int pin, enum intr_polarity pol) 870 { 871 struct ioapic *io; 872 int activehi; 873 874 io = (struct ioapic *)cookie; 875 if (pin >= io->io_numintr || pol == INTR_POLARITY_CONFORM) 876 return (EINVAL); 877 if (io->io_pins[pin].io_irq < 0) 878 return (EINVAL); 879 activehi = (pol == INTR_POLARITY_HIGH); 880 if (io->io_pins[pin].io_activehi == activehi) 881 return (0); 882 io->io_pins[pin].io_activehi = activehi; 883 if (bootverbose) 884 printf("ioapic%u: intpin %d polarity: %s\n", io->io_id, pin, 885 pol == INTR_POLARITY_HIGH ? "high" : "low"); 886 return (0); 887 } 888 889 int 890 ioapic_set_triggermode(void *cookie, u_int pin, enum intr_trigger trigger) 891 { 892 struct ioapic *io; 893 int edgetrigger; 894 895 io = (struct ioapic *)cookie; 896 if (pin >= io->io_numintr || trigger == INTR_TRIGGER_CONFORM) 897 return (EINVAL); 898 if (io->io_pins[pin].io_irq < 0) 899 return (EINVAL); 900 edgetrigger = (trigger == INTR_TRIGGER_EDGE); 901 if (io->io_pins[pin].io_edgetrigger == edgetrigger) 902 return (0); 903 io->io_pins[pin].io_edgetrigger = edgetrigger; 904 if (bootverbose) 905 printf("ioapic%u: intpin %d trigger: %s\n", io->io_id, pin, 906 trigger == INTR_TRIGGER_EDGE ? "edge" : "level"); 907 return (0); 908 } 909 910 /* 911 * Register a complete I/O APIC object with the interrupt subsystem. 912 */ 913 void 914 ioapic_register(void *cookie) 915 { 916 struct ioapic_intsrc *pin; 917 struct ioapic *io; 918 volatile ioapic_t *apic; 919 uint32_t flags; 920 int i; 921 922 io = (struct ioapic *)cookie; 923 apic = io->io_addr; 924 mtx_lock_spin(&icu_lock); 925 flags = ioapic_read(apic, IOAPIC_VER) & IOART_VER_VERSION; 926 STAILQ_INSERT_TAIL(&ioapic_list, io, io_next); 927 mtx_unlock_spin(&icu_lock); 928 printf("ioapic%u <Version %u.%u> irqs %u-%u\n", 929 io->io_id, flags >> 4, flags & 0xf, io->io_intbase, 930 io->io_intbase + io->io_numintr - 1); 931 932 /* 933 * Reprogram pins to handle special case pins (such as NMI and 934 * SMI) and disable normal pins until a handler is registered. 935 */ 936 intr_register_pic(&io->io_pic); 937 for (i = 0, pin = io->io_pins; i < io->io_numintr; i++, pin++) 938 ioapic_reprogram_intpin(&pin->io_intsrc); 939 } 940 941 /* 942 * Add interrupt sources for I/O APIC interrupt pins. 943 */ 944 static void 945 ioapic_register_sources(struct pic *pic) 946 { 947 struct ioapic_intsrc *pin; 948 struct ioapic *io; 949 int i; 950 951 io = (struct ioapic *)pic; 952 for (i = 0, pin = io->io_pins; i < io->io_numintr; i++, pin++) { 953 if (pin->io_irq >= 0) 954 intr_register_source(&pin->io_intsrc); 955 } 956 } 957 958 /* A simple new-bus driver to consume PCI I/O APIC devices. */ 959 static int 960 ioapic_pci_probe(device_t dev) 961 { 962 963 if (pci_get_class(dev) == PCIC_BASEPERIPH && 964 pci_get_subclass(dev) == PCIS_BASEPERIPH_PIC) { 965 switch (pci_get_progif(dev)) { 966 case PCIP_BASEPERIPH_PIC_IO_APIC: 967 device_set_desc(dev, "IO APIC"); 968 break; 969 case PCIP_BASEPERIPH_PIC_IOX_APIC: 970 device_set_desc(dev, "IO(x) APIC"); 971 break; 972 default: 973 return (ENXIO); 974 } 975 device_quiet(dev); 976 return (-10000); 977 } 978 return (ENXIO); 979 } 980 981 static int 982 ioapic_pci_attach(device_t dev) 983 { 984 struct resource *res; 985 volatile ioapic_t *apic; 986 struct ioapic *io; 987 int rid; 988 u_int apic_id; 989 990 /* 991 * Try to match the enumerated ioapic. Match BAR start 992 * against io_paddr. Due to a fear that PCI window is not the 993 * same as the MADT reported io window, but an alias, read the 994 * APIC ID from the mapped BAR and match against it. 995 */ 996 rid = PCIR_BAR(0); 997 res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid, 998 RF_ACTIVE | RF_SHAREABLE); 999 if (res == NULL) { 1000 if (bootverbose) 1001 device_printf(dev, "cannot activate BAR0\n"); 1002 return (ENXIO); 1003 } 1004 apic = (volatile ioapic_t *)rman_get_virtual(res); 1005 if (rman_get_size(res) < IOAPIC_WND_SIZE) { 1006 if (bootverbose) 1007 device_printf(dev, 1008 "BAR0 too small (%jd) for IOAPIC window\n", 1009 (uintmax_t)rman_get_size(res)); 1010 goto fail; 1011 } 1012 mtx_lock_spin(&icu_lock); 1013 apic_id = ioapic_read(apic, IOAPIC_ID) >> APIC_ID_SHIFT; 1014 /* First match by io window address */ 1015 STAILQ_FOREACH(io, &ioapic_list, io_next) { 1016 if (io->io_paddr == (vm_paddr_t)rman_get_start(res)) 1017 goto found; 1018 } 1019 /* Then by apic id */ 1020 STAILQ_FOREACH(io, &ioapic_list, io_next) { 1021 if (io->io_hw_apic_id == apic_id) 1022 goto found; 1023 } 1024 mtx_unlock_spin(&icu_lock); 1025 if (bootverbose) 1026 device_printf(dev, 1027 "cannot match pci bar apic id %d against MADT, BAR0 %#jx\n", 1028 apic_id, (uintmax_t)rman_get_start(res)); 1029 fail: 1030 bus_release_resource(dev, SYS_RES_MEMORY, rid, res); 1031 return (ENXIO); 1032 found: 1033 KASSERT(io->pci_dev == NULL, 1034 ("ioapic %d pci_dev not NULL", io->io_id)); 1035 KASSERT(io->pci_wnd == NULL, 1036 ("ioapic %d pci_wnd not NULL", io->io_id)); 1037 1038 io->pci_dev = dev; 1039 io->pci_wnd = res; 1040 if (bootverbose && (io->io_paddr != (vm_paddr_t)rman_get_start(res) || 1041 io->io_hw_apic_id != apic_id)) { 1042 device_printf(dev, "pci%d:%d:%d:%d pci BAR0@%jx id %d " 1043 "MADT id %d hw id %d paddr@%jx\n", 1044 pci_get_domain(dev), pci_get_bus(dev), 1045 pci_get_slot(dev), pci_get_function(dev), 1046 (uintmax_t)rman_get_start(res), apic_id, 1047 io->io_apic_id, io->io_hw_apic_id, (uintmax_t)io->io_paddr); 1048 } 1049 mtx_unlock_spin(&icu_lock); 1050 return (0); 1051 } 1052 1053 static device_method_t ioapic_pci_methods[] = { 1054 /* Device interface */ 1055 DEVMETHOD(device_probe, ioapic_pci_probe), 1056 DEVMETHOD(device_attach, ioapic_pci_attach), 1057 { 0, 0 } 1058 }; 1059 1060 DEFINE_CLASS_0(ioapic, ioapic_pci_driver, ioapic_pci_methods, 0); 1061 1062 DRIVER_MODULE(ioapic, pci, ioapic_pci_driver, 0, 0); 1063 1064 int 1065 ioapic_get_rid(u_int apic_id, uint16_t *ridp) 1066 { 1067 struct ioapic *io; 1068 uintptr_t rid; 1069 int error; 1070 1071 mtx_lock_spin(&icu_lock); 1072 STAILQ_FOREACH(io, &ioapic_list, io_next) { 1073 if (io->io_apic_id == apic_id) 1074 break; 1075 } 1076 mtx_unlock_spin(&icu_lock); 1077 if (io == NULL || io->pci_dev == NULL) 1078 return (EINVAL); 1079 error = pci_get_id(io->pci_dev, PCI_ID_RID, &rid); 1080 if (error != 0) 1081 return (error); 1082 *ridp = rid; 1083 return (0); 1084 } 1085 1086 /* 1087 * A new-bus driver to consume the memory resources associated with 1088 * the APICs in the system. On some systems ACPI or PnPBIOS system 1089 * resource devices may already claim these resources. To keep from 1090 * breaking those devices, we attach ourself to the nexus device after 1091 * legacy0 and acpi0 and ignore any allocation failures. 1092 */ 1093 static void 1094 apic_identify(driver_t *driver, device_t parent) 1095 { 1096 1097 /* 1098 * Add at order 12. acpi0 is probed at order 10 and legacy0 1099 * is probed at order 11. 1100 */ 1101 if (lapic_paddr != 0) 1102 BUS_ADD_CHILD(parent, 12, "apic", 0); 1103 } 1104 1105 static int 1106 apic_probe(device_t dev) 1107 { 1108 1109 device_set_desc(dev, "APIC resources"); 1110 device_quiet(dev); 1111 return (0); 1112 } 1113 1114 static void 1115 apic_add_resource(device_t dev, int rid, vm_paddr_t base, size_t length) 1116 { 1117 int error; 1118 1119 error = bus_set_resource(dev, SYS_RES_MEMORY, rid, base, length); 1120 if (error) 1121 panic("apic_add_resource: resource %d failed set with %d", rid, 1122 error); 1123 bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid, RF_SHAREABLE); 1124 } 1125 1126 static int 1127 apic_attach(device_t dev) 1128 { 1129 struct ioapic *io; 1130 int i; 1131 1132 /* Reserve the local APIC. */ 1133 apic_add_resource(dev, 0, lapic_paddr, LAPIC_MEM_REGION); 1134 i = 1; 1135 STAILQ_FOREACH(io, &ioapic_list, io_next) { 1136 apic_add_resource(dev, i, io->io_paddr, IOAPIC_MEM_REGION); 1137 i++; 1138 } 1139 return (0); 1140 } 1141 1142 static device_method_t apic_methods[] = { 1143 /* Device interface */ 1144 DEVMETHOD(device_identify, apic_identify), 1145 DEVMETHOD(device_probe, apic_probe), 1146 DEVMETHOD(device_attach, apic_attach), 1147 { 0, 0 } 1148 }; 1149 1150 DEFINE_CLASS_0(apic, apic_driver, apic_methods, 0); 1151 1152 DRIVER_MODULE(apic, nexus, apic_driver, 0, 0); 1153 1154 #include "opt_ddb.h" 1155 1156 #ifdef DDB 1157 #include <ddb/ddb.h> 1158 1159 static const char * 1160 ioapic_delivery_mode(uint32_t mode) 1161 { 1162 1163 switch (mode) { 1164 case IOART_DELFIXED: 1165 return ("fixed"); 1166 case IOART_DELLOPRI: 1167 return ("lowestpri"); 1168 case IOART_DELSMI: 1169 return ("SMI"); 1170 case IOART_DELRSV1: 1171 return ("rsrvd1"); 1172 case IOART_DELNMI: 1173 return ("NMI"); 1174 case IOART_DELINIT: 1175 return ("INIT"); 1176 case IOART_DELRSV2: 1177 return ("rsrvd2"); 1178 case IOART_DELEXINT: 1179 return ("ExtINT"); 1180 default: 1181 return (""); 1182 } 1183 } 1184 1185 static u_int 1186 db_ioapic_read(volatile ioapic_t *apic, int reg) 1187 { 1188 1189 apic->ioregsel = reg; 1190 return (apic->iowin); 1191 } 1192 1193 static void 1194 db_show_ioapic_one(volatile ioapic_t *io_addr) 1195 { 1196 uint32_t r, lo, hi; 1197 int mre, i; 1198 1199 r = db_ioapic_read(io_addr, IOAPIC_VER); 1200 mre = (r & IOART_VER_MAXREDIR) >> MAXREDIRSHIFT; 1201 db_printf("Id 0x%08x Ver 0x%02x MRE %d\n", 1202 db_ioapic_read(io_addr, IOAPIC_ID), r & IOART_VER_VERSION, mre); 1203 for (i = 0; i < mre; i++) { 1204 lo = db_ioapic_read(io_addr, IOAPIC_REDTBL_LO(i)); 1205 hi = db_ioapic_read(io_addr, IOAPIC_REDTBL_HI(i)); 1206 db_printf(" pin %d Dest %s/%x %smasked Trig %s RemoteIRR %d " 1207 "Polarity %s Status %s DeliveryMode %s Vec %d\n", i, 1208 (lo & IOART_DESTMOD) == IOART_DESTLOG ? "log" : "phy", 1209 (hi & IOART_DEST) >> 24, 1210 (lo & IOART_INTMASK) == IOART_INTMSET ? "" : "not", 1211 (lo & IOART_TRGRMOD) == IOART_TRGRLVL ? "lvl" : "edge", 1212 (lo & IOART_REM_IRR) == IOART_REM_IRR ? 1 : 0, 1213 (lo & IOART_INTPOL) == IOART_INTALO ? "low" : "high", 1214 (lo & IOART_DELIVS) == IOART_DELIVS ? "pend" : "idle", 1215 ioapic_delivery_mode(lo & IOART_DELMOD), 1216 (lo & IOART_INTVEC)); 1217 } 1218 } 1219 1220 DB_SHOW_COMMAND(ioapic, db_show_ioapic) 1221 { 1222 struct ioapic *ioapic; 1223 int idx, i; 1224 1225 if (!have_addr) { 1226 db_printf("usage: show ioapic index\n"); 1227 return; 1228 } 1229 1230 idx = (int)addr; 1231 i = 0; 1232 STAILQ_FOREACH(ioapic, &ioapic_list, io_next) { 1233 if (idx == i) { 1234 db_show_ioapic_one(ioapic->io_addr); 1235 break; 1236 } 1237 i++; 1238 } 1239 } 1240 1241 DB_SHOW_ALL_COMMAND(ioapics, db_show_all_ioapics) 1242 { 1243 struct ioapic *ioapic; 1244 1245 STAILQ_FOREACH(ioapic, &ioapic_list, io_next) 1246 db_show_ioapic_one(ioapic->io_addr); 1247 } 1248 #endif 1249