1 /*- 2 * Copyright 1998 Massachusetts Institute of Technology 3 * 4 * Permission to use, copy, modify, and distribute this software and 5 * its documentation for any purpose and without fee is hereby 6 * granted, provided that both the above copyright notice and this 7 * permission notice appear in all copies, that both the above 8 * copyright notice and this permission notice appear in all 9 * supporting documentation, and that the name of M.I.T. not be used 10 * in advertising or publicity pertaining to distribution of the 11 * software without specific, written prior permission. M.I.T. makes 12 * no representations about the suitability of this software for any 13 * purpose. It is provided "as is" without express or implied 14 * warranty. 15 * 16 * THIS SOFTWARE IS PROVIDED BY M.I.T. ``AS IS''. M.I.T. DISCLAIMS 17 * ALL EXPRESS OR IMPLIED WARRANTIES WITH REGARD TO THIS SOFTWARE, 18 * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 19 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT 20 * SHALL M.I.T. BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF 23 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND 24 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 25 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT 26 * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 27 * SUCH DAMAGE. 28 */ 29 30 #include <sys/cdefs.h> 31 __FBSDID("$FreeBSD$"); 32 33 /* 34 * This code implements a system driver for legacy systems that do not 35 * support ACPI or when ACPI support is not present in the kernel. 36 */ 37 38 #include <sys/param.h> 39 #include <sys/systm.h> 40 #include <sys/bus.h> 41 #include <sys/cpu.h> 42 #include <sys/kernel.h> 43 #include <sys/malloc.h> 44 #include <sys/module.h> 45 #include <machine/bus.h> 46 #include <sys/pcpu.h> 47 #include <sys/rman.h> 48 #include <sys/smp.h> 49 #include <dev/pci/pcireg.h> 50 51 #include <machine/clock.h> 52 #include <machine/pci_cfgreg.h> 53 #include <machine/resource.h> 54 #include <x86/legacyvar.h> 55 56 static MALLOC_DEFINE(M_LEGACYDEV, "legacydrv", "legacy system device"); 57 struct legacy_device { 58 int lg_pcibus; 59 int lg_pcislot; 60 int lg_pcifunc; 61 }; 62 63 #define DEVTOAT(dev) ((struct legacy_device *)device_get_ivars(dev)) 64 65 static int legacy_probe(device_t); 66 static int legacy_attach(device_t); 67 static int legacy_print_child(device_t, device_t); 68 static device_t legacy_add_child(device_t bus, u_int order, const char *name, 69 int unit); 70 static int legacy_read_ivar(device_t, device_t, int, uintptr_t *); 71 static int legacy_write_ivar(device_t, device_t, int, uintptr_t); 72 73 static device_method_t legacy_methods[] = { 74 /* Device interface */ 75 DEVMETHOD(device_probe, legacy_probe), 76 DEVMETHOD(device_attach, legacy_attach), 77 DEVMETHOD(device_detach, bus_generic_detach), 78 DEVMETHOD(device_shutdown, bus_generic_shutdown), 79 DEVMETHOD(device_suspend, bus_generic_suspend), 80 DEVMETHOD(device_resume, bus_generic_resume), 81 82 /* Bus interface */ 83 DEVMETHOD(bus_print_child, legacy_print_child), 84 DEVMETHOD(bus_add_child, legacy_add_child), 85 DEVMETHOD(bus_read_ivar, legacy_read_ivar), 86 DEVMETHOD(bus_write_ivar, legacy_write_ivar), 87 DEVMETHOD(bus_alloc_resource, bus_generic_alloc_resource), 88 DEVMETHOD(bus_adjust_resource, bus_generic_adjust_resource), 89 DEVMETHOD(bus_release_resource, bus_generic_release_resource), 90 DEVMETHOD(bus_activate_resource, bus_generic_activate_resource), 91 DEVMETHOD(bus_deactivate_resource, bus_generic_deactivate_resource), 92 DEVMETHOD(bus_setup_intr, bus_generic_setup_intr), 93 DEVMETHOD(bus_teardown_intr, bus_generic_teardown_intr), 94 95 { 0, 0 } 96 }; 97 98 static driver_t legacy_driver = { 99 "legacy", 100 legacy_methods, 101 1, /* no softc */ 102 }; 103 static devclass_t legacy_devclass; 104 105 DRIVER_MODULE(legacy, nexus, legacy_driver, legacy_devclass, 0, 0); 106 107 static int 108 legacy_probe(device_t dev) 109 { 110 111 device_set_desc(dev, "legacy system"); 112 device_quiet(dev); 113 return (0); 114 } 115 116 /* 117 * Grope around in the PCI config space to see if this is a chipset 118 * that is capable of doing memory-mapped config cycles. This also 119 * implies that it can do PCIe extended config cycles. 120 */ 121 static void 122 legacy_pci_cfgregopen(device_t dev) 123 { 124 uint64_t pciebar; 125 u_int16_t did, vid; 126 127 if (cfgmech == CFGMECH_NONE || cfgmech == CFGMECH_PCIE) 128 return; 129 130 /* Check for supported chipsets */ 131 vid = pci_cfgregread(0, 0, 0, PCIR_VENDOR, 2); 132 did = pci_cfgregread(0, 0, 0, PCIR_DEVICE, 2); 133 switch (vid) { 134 case 0x8086: 135 switch (did) { 136 case 0x3590: 137 case 0x3592: 138 /* Intel 7520 or 7320 */ 139 pciebar = pci_cfgregread(0, 0, 0, 0xce, 2) << 16; 140 pcie_cfgregopen(pciebar, 0, 255); 141 break; 142 case 0x2580: 143 case 0x2584: 144 case 0x2590: 145 /* Intel 915, 925, or 915GM */ 146 pciebar = pci_cfgregread(0, 0, 0, 0x48, 4); 147 pcie_cfgregopen(pciebar, 0, 255); 148 break; 149 } 150 } 151 152 if (bootverbose && cfgmech == CFGMECH_PCIE) 153 device_printf(dev, "Enabled ECAM PCIe accesses\n"); 154 } 155 156 static int 157 legacy_attach(device_t dev) 158 { 159 device_t child; 160 161 legacy_pci_cfgregopen(dev); 162 163 /* 164 * Let our child drivers identify any child devices that they 165 * can find. Once that is done attach any devices that we 166 * found. 167 */ 168 bus_generic_probe(dev); 169 bus_generic_attach(dev); 170 171 /* 172 * If we didn't see ISA on a PCI bridge, add a top-level bus. 173 */ 174 if (!devclass_get_device(devclass_find("isa"), 0)) { 175 child = BUS_ADD_CHILD(dev, 0, "isa", 0); 176 if (child == NULL) 177 panic("legacy_attach isa"); 178 device_probe_and_attach(child); 179 } 180 181 return 0; 182 } 183 184 static int 185 legacy_print_child(device_t bus, device_t child) 186 { 187 struct legacy_device *atdev = DEVTOAT(child); 188 int retval = 0; 189 190 retval += bus_print_child_header(bus, child); 191 if (atdev->lg_pcibus != -1) 192 retval += printf(" pcibus %d", atdev->lg_pcibus); 193 retval += printf("\n"); 194 195 return (retval); 196 } 197 198 static device_t 199 legacy_add_child(device_t bus, u_int order, const char *name, int unit) 200 { 201 device_t child; 202 struct legacy_device *atdev; 203 204 atdev = malloc(sizeof(struct legacy_device), M_LEGACYDEV, 205 M_NOWAIT | M_ZERO); 206 if (atdev == NULL) 207 return(NULL); 208 atdev->lg_pcibus = -1; 209 atdev->lg_pcislot = -1; 210 atdev->lg_pcifunc = -1; 211 212 child = device_add_child_ordered(bus, order, name, unit); 213 if (child == NULL) 214 free(atdev, M_LEGACYDEV); 215 else 216 /* should we free this in legacy_child_detached? */ 217 device_set_ivars(child, atdev); 218 219 return (child); 220 } 221 222 static int 223 legacy_read_ivar(device_t dev, device_t child, int which, uintptr_t *result) 224 { 225 struct legacy_device *atdev = DEVTOAT(child); 226 227 switch (which) { 228 case LEGACY_IVAR_PCIDOMAIN: 229 *result = 0; 230 break; 231 case LEGACY_IVAR_PCIBUS: 232 *result = atdev->lg_pcibus; 233 break; 234 case LEGACY_IVAR_PCISLOT: 235 *result = atdev->lg_pcislot; 236 break; 237 case LEGACY_IVAR_PCIFUNC: 238 *result = atdev->lg_pcifunc; 239 break; 240 default: 241 return ENOENT; 242 } 243 return 0; 244 } 245 246 247 static int 248 legacy_write_ivar(device_t dev, device_t child, int which, uintptr_t value) 249 { 250 struct legacy_device *atdev = DEVTOAT(child); 251 252 switch (which) { 253 case LEGACY_IVAR_PCIDOMAIN: 254 return EINVAL; 255 case LEGACY_IVAR_PCIBUS: 256 atdev->lg_pcibus = value; 257 break; 258 case LEGACY_IVAR_PCISLOT: 259 atdev->lg_pcislot = value; 260 break; 261 case LEGACY_IVAR_PCIFUNC: 262 atdev->lg_pcifunc = value; 263 break; 264 default: 265 return ENOENT; 266 } 267 return 0; 268 } 269 270 /* 271 * Legacy CPU attachment when ACPI is not available. Drivers like 272 * cpufreq(4) hang off this. 273 */ 274 static void cpu_identify(driver_t *driver, device_t parent); 275 static int cpu_read_ivar(device_t dev, device_t child, int index, 276 uintptr_t *result); 277 static device_t cpu_add_child(device_t bus, u_int order, const char *name, 278 int unit); 279 static struct resource_list *cpu_get_rlist(device_t dev, device_t child); 280 281 struct cpu_device { 282 struct resource_list cd_rl; 283 struct pcpu *cd_pcpu; 284 }; 285 286 static device_method_t cpu_methods[] = { 287 /* Device interface */ 288 DEVMETHOD(device_identify, cpu_identify), 289 DEVMETHOD(device_probe, bus_generic_probe), 290 DEVMETHOD(device_attach, bus_generic_attach), 291 DEVMETHOD(device_detach, bus_generic_detach), 292 DEVMETHOD(device_shutdown, bus_generic_shutdown), 293 DEVMETHOD(device_suspend, bus_generic_suspend), 294 DEVMETHOD(device_resume, bus_generic_resume), 295 296 /* Bus interface */ 297 DEVMETHOD(bus_add_child, cpu_add_child), 298 DEVMETHOD(bus_read_ivar, cpu_read_ivar), 299 DEVMETHOD(bus_get_resource_list, cpu_get_rlist), 300 DEVMETHOD(bus_get_resource, bus_generic_rl_get_resource), 301 DEVMETHOD(bus_set_resource, bus_generic_rl_set_resource), 302 DEVMETHOD(bus_alloc_resource, bus_generic_rl_alloc_resource), 303 DEVMETHOD(bus_release_resource, bus_generic_rl_release_resource), 304 DEVMETHOD(bus_activate_resource, bus_generic_activate_resource), 305 DEVMETHOD(bus_deactivate_resource, bus_generic_deactivate_resource), 306 DEVMETHOD(bus_setup_intr, bus_generic_setup_intr), 307 DEVMETHOD(bus_teardown_intr, bus_generic_teardown_intr), 308 309 DEVMETHOD_END 310 }; 311 312 static driver_t cpu_driver = { 313 "cpu", 314 cpu_methods, 315 1, /* no softc */ 316 }; 317 static devclass_t cpu_devclass; 318 DRIVER_MODULE(cpu, legacy, cpu_driver, cpu_devclass, 0, 0); 319 320 static void 321 cpu_identify(driver_t *driver, device_t parent) 322 { 323 device_t child; 324 int i; 325 326 /* 327 * Attach a cpuX device for each CPU. We use an order of 150 328 * so that these devices are attached after the Host-PCI 329 * bridges (which are added at order 100). 330 */ 331 CPU_FOREACH(i) { 332 child = BUS_ADD_CHILD(parent, 150, "cpu", i); 333 if (child == NULL) 334 panic("legacy_attach cpu"); 335 } 336 } 337 338 static device_t 339 cpu_add_child(device_t bus, u_int order, const char *name, int unit) 340 { 341 struct cpu_device *cd; 342 device_t child; 343 struct pcpu *pc; 344 345 if ((cd = malloc(sizeof(*cd), M_DEVBUF, M_NOWAIT | M_ZERO)) == NULL) 346 return (NULL); 347 348 resource_list_init(&cd->cd_rl); 349 pc = pcpu_find(device_get_unit(bus)); 350 cd->cd_pcpu = pc; 351 352 child = device_add_child_ordered(bus, order, name, unit); 353 if (child != NULL) { 354 pc->pc_device = child; 355 device_set_ivars(child, cd); 356 } else 357 free(cd, M_DEVBUF); 358 return (child); 359 } 360 361 static struct resource_list * 362 cpu_get_rlist(device_t dev, device_t child) 363 { 364 struct cpu_device *cpdev; 365 366 cpdev = device_get_ivars(child); 367 return (&cpdev->cd_rl); 368 } 369 370 static int 371 cpu_read_ivar(device_t dev, device_t child, int index, uintptr_t *result) 372 { 373 struct cpu_device *cpdev; 374 375 switch (index) { 376 case CPU_IVAR_PCPU: 377 cpdev = device_get_ivars(child); 378 *result = (uintptr_t)cpdev->cd_pcpu; 379 break; 380 case CPU_IVAR_NOMINAL_MHZ: 381 if (tsc_is_invariant) { 382 *result = (uintptr_t)(atomic_load_acq_64(&tsc_freq) / 383 1000000); 384 break; 385 } 386 /* FALLTHROUGH */ 387 default: 388 return (ENOENT); 389 } 390 return (0); 391 } 392