1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD 3 * 4 * Copyright (c) 2009 Hudson River Trading LLC 5 * Written by: John H. Baldwin <jhb@FreeBSD.org> 6 * All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 18 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 19 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 20 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 21 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 22 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 23 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 24 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 25 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 26 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 27 * SUCH DAMAGE. 28 */ 29 30 /* 31 * Support for x86 machine check architecture. 32 */ 33 34 #include <sys/cdefs.h> 35 __FBSDID("$FreeBSD$"); 36 37 #ifdef __amd64__ 38 #define DEV_APIC 39 #else 40 #include "opt_apic.h" 41 #endif 42 43 #include <sys/param.h> 44 #include <sys/bus.h> 45 #include <sys/interrupt.h> 46 #include <sys/kernel.h> 47 #include <sys/lock.h> 48 #include <sys/malloc.h> 49 #include <sys/mutex.h> 50 #include <sys/proc.h> 51 #include <sys/sched.h> 52 #include <sys/smp.h> 53 #include <sys/sysctl.h> 54 #include <sys/systm.h> 55 #include <sys/taskqueue.h> 56 #include <machine/intr_machdep.h> 57 #include <x86/apicvar.h> 58 #include <machine/cpu.h> 59 #include <machine/cputypes.h> 60 #include <x86/mca.h> 61 #include <machine/md_var.h> 62 #include <machine/specialreg.h> 63 64 /* Modes for mca_scan() */ 65 enum scan_mode { 66 POLLED, 67 MCE, 68 CMCI, 69 }; 70 71 #ifdef DEV_APIC 72 /* 73 * State maintained for each monitored MCx bank to control the 74 * corrected machine check interrupt threshold. 75 */ 76 struct cmc_state { 77 int max_threshold; 78 time_t last_intr; 79 }; 80 81 struct amd_et_state { 82 int cur_threshold; 83 time_t last_intr; 84 }; 85 #endif 86 87 struct mca_internal { 88 struct mca_record rec; 89 STAILQ_ENTRY(mca_internal) link; 90 }; 91 92 struct mca_enumerator_ops { 93 unsigned int (*ctl)(int); 94 unsigned int (*status)(int); 95 unsigned int (*addr)(int); 96 unsigned int (*misc)(int); 97 }; 98 99 static MALLOC_DEFINE(M_MCA, "MCA", "Machine Check Architecture"); 100 101 static volatile int mca_count; /* Number of records stored. */ 102 static int mca_banks; /* Number of per-CPU register banks. */ 103 static int mca_maxcount = -1; /* Limit on records stored. (-1 = unlimited) */ 104 105 static SYSCTL_NODE(_hw, OID_AUTO, mca, CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, 106 "Machine Check Architecture"); 107 108 static int mca_enabled = 1; 109 SYSCTL_INT(_hw_mca, OID_AUTO, enabled, CTLFLAG_RDTUN, &mca_enabled, 0, 110 "Administrative toggle for machine check support"); 111 112 static int amd10h_L1TP = 1; 113 SYSCTL_INT(_hw_mca, OID_AUTO, amd10h_L1TP, CTLFLAG_RDTUN, &amd10h_L1TP, 0, 114 "Administrative toggle for logging of level one TLB parity (L1TP) errors"); 115 116 static int intel6h_HSD131; 117 SYSCTL_INT(_hw_mca, OID_AUTO, intel6h_HSD131, CTLFLAG_RDTUN, &intel6h_HSD131, 0, 118 "Administrative toggle for logging of spurious corrected errors"); 119 120 int workaround_erratum383; 121 SYSCTL_INT(_hw_mca, OID_AUTO, erratum383, CTLFLAG_RDTUN, 122 &workaround_erratum383, 0, 123 "Is the workaround for Erratum 383 on AMD Family 10h processors enabled?"); 124 125 static STAILQ_HEAD(, mca_internal) mca_freelist; 126 static int mca_freecount; 127 static STAILQ_HEAD(, mca_internal) mca_records; 128 static STAILQ_HEAD(, mca_internal) mca_pending; 129 static struct callout mca_timer; 130 static int mca_ticks = 3600; /* Check hourly by default. */ 131 static struct taskqueue *mca_tq; 132 static struct task mca_resize_task, mca_scan_task; 133 static struct mtx mca_lock; 134 135 static unsigned int 136 mca_ia32_ctl_reg(int bank) 137 { 138 return (MSR_MC_CTL(bank)); 139 } 140 141 static unsigned int 142 mca_ia32_status_reg(int bank) 143 { 144 return (MSR_MC_STATUS(bank)); 145 } 146 147 static unsigned int 148 mca_ia32_addr_reg(int bank) 149 { 150 return (MSR_MC_ADDR(bank)); 151 } 152 153 static unsigned int 154 mca_ia32_misc_reg(int bank) 155 { 156 return (MSR_MC_MISC(bank)); 157 } 158 159 static unsigned int 160 mca_smca_ctl_reg(int bank) 161 { 162 return (MSR_SMCA_MC_CTL(bank)); 163 } 164 165 static unsigned int 166 mca_smca_status_reg(int bank) 167 { 168 return (MSR_SMCA_MC_STATUS(bank)); 169 } 170 171 static unsigned int 172 mca_smca_addr_reg(int bank) 173 { 174 return (MSR_SMCA_MC_ADDR(bank)); 175 } 176 177 static unsigned int 178 mca_smca_misc_reg(int bank) 179 { 180 return (MSR_SMCA_MC_MISC(bank)); 181 } 182 183 static struct mca_enumerator_ops mca_msr_ops = { 184 .ctl = mca_ia32_ctl_reg, 185 .status = mca_ia32_status_reg, 186 .addr = mca_ia32_addr_reg, 187 .misc = mca_ia32_misc_reg 188 }; 189 190 #ifdef DEV_APIC 191 static struct cmc_state **cmc_state; /* Indexed by cpuid, bank. */ 192 static struct amd_et_state **amd_et_state; /* Indexed by cpuid, bank. */ 193 static int cmc_throttle = 60; /* Time in seconds to throttle CMCI. */ 194 195 static int amd_elvt = -1; 196 197 static inline bool 198 amd_thresholding_supported(void) 199 { 200 if (cpu_vendor_id != CPU_VENDOR_AMD && 201 cpu_vendor_id != CPU_VENDOR_HYGON) 202 return (false); 203 /* 204 * The RASCap register is wholly reserved in families 0x10-0x15 (through model 1F). 205 * 206 * It begins to be documented in family 0x15 model 30 and family 0x16, 207 * but neither of these families documents the ScalableMca bit, which 208 * supposedly defines the presence of this feature on family 0x17. 209 */ 210 if (CPUID_TO_FAMILY(cpu_id) >= 0x10 && CPUID_TO_FAMILY(cpu_id) <= 0x16) 211 return (true); 212 if (CPUID_TO_FAMILY(cpu_id) >= 0x17) 213 return ((amd_rascap & AMDRAS_SCALABLE_MCA) != 0); 214 return (false); 215 } 216 #endif 217 218 static inline bool 219 cmci_supported(uint64_t mcg_cap) 220 { 221 /* 222 * MCG_CAP_CMCI_P bit is reserved in AMD documentation. Until 223 * it is defined, do not use it to check for CMCI support. 224 */ 225 if (cpu_vendor_id != CPU_VENDOR_INTEL) 226 return (false); 227 return ((mcg_cap & MCG_CAP_CMCI_P) != 0); 228 } 229 230 static int 231 sysctl_positive_int(SYSCTL_HANDLER_ARGS) 232 { 233 int error, value; 234 235 value = *(int *)arg1; 236 error = sysctl_handle_int(oidp, &value, 0, req); 237 if (error || req->newptr == NULL) 238 return (error); 239 if (value <= 0) 240 return (EINVAL); 241 *(int *)arg1 = value; 242 return (0); 243 } 244 245 static int 246 sysctl_mca_records(SYSCTL_HANDLER_ARGS) 247 { 248 int *name = (int *)arg1; 249 u_int namelen = arg2; 250 struct mca_record record; 251 struct mca_internal *rec; 252 int i; 253 254 if (namelen != 1) 255 return (EINVAL); 256 257 if (name[0] < 0 || name[0] >= mca_count) 258 return (EINVAL); 259 260 mtx_lock_spin(&mca_lock); 261 if (name[0] >= mca_count) { 262 mtx_unlock_spin(&mca_lock); 263 return (EINVAL); 264 } 265 i = 0; 266 STAILQ_FOREACH(rec, &mca_records, link) { 267 if (i == name[0]) { 268 record = rec->rec; 269 break; 270 } 271 i++; 272 } 273 mtx_unlock_spin(&mca_lock); 274 return (SYSCTL_OUT(req, &record, sizeof(record))); 275 } 276 277 static const char * 278 mca_error_ttype(uint16_t mca_error) 279 { 280 281 switch ((mca_error & 0x000c) >> 2) { 282 case 0: 283 return ("I"); 284 case 1: 285 return ("D"); 286 case 2: 287 return ("G"); 288 } 289 return ("?"); 290 } 291 292 static const char * 293 mca_error_level(uint16_t mca_error) 294 { 295 296 switch (mca_error & 0x0003) { 297 case 0: 298 return ("L0"); 299 case 1: 300 return ("L1"); 301 case 2: 302 return ("L2"); 303 case 3: 304 return ("LG"); 305 } 306 return ("L?"); 307 } 308 309 static const char * 310 mca_error_request(uint16_t mca_error) 311 { 312 313 switch ((mca_error & 0x00f0) >> 4) { 314 case 0x0: 315 return ("ERR"); 316 case 0x1: 317 return ("RD"); 318 case 0x2: 319 return ("WR"); 320 case 0x3: 321 return ("DRD"); 322 case 0x4: 323 return ("DWR"); 324 case 0x5: 325 return ("IRD"); 326 case 0x6: 327 return ("PREFETCH"); 328 case 0x7: 329 return ("EVICT"); 330 case 0x8: 331 return ("SNOOP"); 332 } 333 return ("???"); 334 } 335 336 static const char * 337 mca_error_mmtype(uint16_t mca_error) 338 { 339 340 switch ((mca_error & 0x70) >> 4) { 341 case 0x0: 342 return ("GEN"); 343 case 0x1: 344 return ("RD"); 345 case 0x2: 346 return ("WR"); 347 case 0x3: 348 return ("AC"); 349 case 0x4: 350 return ("MS"); 351 } 352 return ("???"); 353 } 354 355 static int 356 mca_mute(const struct mca_record *rec) 357 { 358 359 /* 360 * Skip spurious corrected parity errors generated by Intel Haswell- 361 * and Broadwell-based CPUs (see HSD131, HSM142, HSW131 and BDM48 362 * erratum respectively), unless reporting is enabled. 363 * Note that these errors also have been observed with the D0-stepping 364 * of Haswell, while at least initially the CPU specification updates 365 * suggested only the C0-stepping to be affected. Similarly, Celeron 366 * 2955U with a CPU ID of 0x45 apparently are also concerned with the 367 * same problem, with HSM142 only referring to 0x3c and 0x46. 368 */ 369 if (cpu_vendor_id == CPU_VENDOR_INTEL && 370 CPUID_TO_FAMILY(cpu_id) == 0x6 && 371 (CPUID_TO_MODEL(cpu_id) == 0x3c || /* HSD131, HSM142, HSW131 */ 372 CPUID_TO_MODEL(cpu_id) == 0x3d || /* BDM48 */ 373 CPUID_TO_MODEL(cpu_id) == 0x45 || 374 CPUID_TO_MODEL(cpu_id) == 0x46) && /* HSM142 */ 375 rec->mr_bank == 0 && 376 (rec->mr_status & 0xa0000000ffffffff) == 0x80000000000f0005 && 377 !intel6h_HSD131) 378 return (1); 379 380 return (0); 381 } 382 383 /* Dump details about a single machine check. */ 384 static void 385 mca_log(const struct mca_record *rec) 386 { 387 uint16_t mca_error; 388 389 if (mca_mute(rec)) 390 return; 391 392 printf("MCA: Bank %d, Status 0x%016llx\n", rec->mr_bank, 393 (long long)rec->mr_status); 394 printf("MCA: Global Cap 0x%016llx, Status 0x%016llx\n", 395 (long long)rec->mr_mcg_cap, (long long)rec->mr_mcg_status); 396 printf("MCA: Vendor \"%s\", ID 0x%x, APIC ID %d\n", cpu_vendor, 397 rec->mr_cpu_id, rec->mr_apic_id); 398 printf("MCA: CPU %d ", rec->mr_cpu); 399 if (rec->mr_status & MC_STATUS_UC) 400 printf("UNCOR "); 401 else { 402 printf("COR "); 403 if (cmci_supported(rec->mr_mcg_cap)) 404 printf("(%lld) ", ((long long)rec->mr_status & 405 MC_STATUS_COR_COUNT) >> 38); 406 } 407 if (rec->mr_status & MC_STATUS_PCC) 408 printf("PCC "); 409 if (rec->mr_status & MC_STATUS_OVER) 410 printf("OVER "); 411 mca_error = rec->mr_status & MC_STATUS_MCA_ERROR; 412 switch (mca_error) { 413 /* Simple error codes. */ 414 case 0x0000: 415 printf("no error"); 416 break; 417 case 0x0001: 418 printf("unclassified error"); 419 break; 420 case 0x0002: 421 printf("ucode ROM parity error"); 422 break; 423 case 0x0003: 424 printf("external error"); 425 break; 426 case 0x0004: 427 printf("FRC error"); 428 break; 429 case 0x0005: 430 printf("internal parity error"); 431 break; 432 case 0x0400: 433 printf("internal timer error"); 434 break; 435 default: 436 if ((mca_error & 0xfc00) == 0x0400) { 437 printf("internal error %x", mca_error & 0x03ff); 438 break; 439 } 440 441 /* Compound error codes. */ 442 443 /* Memory hierarchy error. */ 444 if ((mca_error & 0xeffc) == 0x000c) { 445 printf("%s memory error", mca_error_level(mca_error)); 446 break; 447 } 448 449 /* TLB error. */ 450 if ((mca_error & 0xeff0) == 0x0010) { 451 printf("%sTLB %s error", mca_error_ttype(mca_error), 452 mca_error_level(mca_error)); 453 break; 454 } 455 456 /* Memory controller error. */ 457 if ((mca_error & 0xef80) == 0x0080) { 458 printf("%s channel ", mca_error_mmtype(mca_error)); 459 if ((mca_error & 0x000f) != 0x000f) 460 printf("%d", mca_error & 0x000f); 461 else 462 printf("??"); 463 printf(" memory error"); 464 break; 465 } 466 467 /* Cache error. */ 468 if ((mca_error & 0xef00) == 0x0100) { 469 printf("%sCACHE %s %s error", 470 mca_error_ttype(mca_error), 471 mca_error_level(mca_error), 472 mca_error_request(mca_error)); 473 break; 474 } 475 476 /* Bus and/or Interconnect error. */ 477 if ((mca_error & 0xe800) == 0x0800) { 478 printf("BUS%s ", mca_error_level(mca_error)); 479 switch ((mca_error & 0x0600) >> 9) { 480 case 0: 481 printf("Source"); 482 break; 483 case 1: 484 printf("Responder"); 485 break; 486 case 2: 487 printf("Observer"); 488 break; 489 default: 490 printf("???"); 491 break; 492 } 493 printf(" %s ", mca_error_request(mca_error)); 494 switch ((mca_error & 0x000c) >> 2) { 495 case 0: 496 printf("Memory"); 497 break; 498 case 2: 499 printf("I/O"); 500 break; 501 case 3: 502 printf("Other"); 503 break; 504 default: 505 printf("???"); 506 break; 507 } 508 if (mca_error & 0x0100) 509 printf(" timed out"); 510 break; 511 } 512 513 printf("unknown error %x", mca_error); 514 break; 515 } 516 printf("\n"); 517 if (rec->mr_status & MC_STATUS_ADDRV) 518 printf("MCA: Address 0x%llx\n", (long long)rec->mr_addr); 519 if (rec->mr_status & MC_STATUS_MISCV) 520 printf("MCA: Misc 0x%llx\n", (long long)rec->mr_misc); 521 } 522 523 static int 524 mca_check_status(int bank, struct mca_record *rec) 525 { 526 uint64_t status; 527 u_int p[4]; 528 529 status = rdmsr(mca_msr_ops.status(bank)); 530 if (!(status & MC_STATUS_VAL)) 531 return (0); 532 533 /* Save exception information. */ 534 rec->mr_status = status; 535 rec->mr_bank = bank; 536 rec->mr_addr = 0; 537 if (status & MC_STATUS_ADDRV) 538 rec->mr_addr = rdmsr(mca_msr_ops.addr(bank)); 539 rec->mr_misc = 0; 540 if (status & MC_STATUS_MISCV) 541 rec->mr_misc = rdmsr(mca_msr_ops.misc(bank)); 542 rec->mr_tsc = rdtsc(); 543 rec->mr_apic_id = PCPU_GET(apic_id); 544 rec->mr_mcg_cap = rdmsr(MSR_MCG_CAP); 545 rec->mr_mcg_status = rdmsr(MSR_MCG_STATUS); 546 rec->mr_cpu_id = cpu_id; 547 rec->mr_cpu_vendor_id = cpu_vendor_id; 548 rec->mr_cpu = PCPU_GET(cpuid); 549 550 /* 551 * Clear machine check. Don't do this for uncorrectable 552 * errors so that the BIOS can see them. 553 */ 554 if (!(rec->mr_status & (MC_STATUS_PCC | MC_STATUS_UC))) { 555 wrmsr(mca_msr_ops.status(bank), 0); 556 do_cpuid(0, p); 557 } 558 return (1); 559 } 560 561 static void 562 mca_resize_freelist(void) 563 { 564 struct mca_internal *next, *rec; 565 STAILQ_HEAD(, mca_internal) tmplist; 566 int count, i, desired_max, desired_min; 567 568 /* 569 * Ensure we have at least one record for each bank and one 570 * record per CPU, but no more than twice that amount. 571 */ 572 desired_min = imax(mp_ncpus, mca_banks); 573 desired_max = imax(mp_ncpus, mca_banks) * 2; 574 STAILQ_INIT(&tmplist); 575 mtx_lock_spin(&mca_lock); 576 while (mca_freecount > desired_max) { 577 rec = STAILQ_FIRST(&mca_freelist); 578 KASSERT(rec != NULL, ("mca_freecount is %d, but list is empty", 579 mca_freecount)); 580 STAILQ_REMOVE_HEAD(&mca_freelist, link); 581 mca_freecount--; 582 STAILQ_INSERT_TAIL(&tmplist, rec, link); 583 } 584 while (mca_freecount < desired_min) { 585 count = desired_min - mca_freecount; 586 mtx_unlock_spin(&mca_lock); 587 for (i = 0; i < count; i++) { 588 rec = malloc(sizeof(*rec), M_MCA, M_WAITOK); 589 STAILQ_INSERT_TAIL(&tmplist, rec, link); 590 } 591 mtx_lock_spin(&mca_lock); 592 STAILQ_CONCAT(&mca_freelist, &tmplist); 593 mca_freecount += count; 594 } 595 mtx_unlock_spin(&mca_lock); 596 STAILQ_FOREACH_SAFE(rec, &tmplist, link, next) 597 free(rec, M_MCA); 598 } 599 600 static void 601 mca_resize(void *context, int pending) 602 { 603 604 mca_resize_freelist(); 605 } 606 607 static void 608 mca_record_entry(enum scan_mode mode, const struct mca_record *record) 609 { 610 struct mca_internal *rec; 611 612 if (mode == POLLED) { 613 rec = malloc(sizeof(*rec), M_MCA, M_WAITOK); 614 mtx_lock_spin(&mca_lock); 615 } else { 616 mtx_lock_spin(&mca_lock); 617 rec = STAILQ_FIRST(&mca_freelist); 618 if (rec == NULL) { 619 printf("MCA: Unable to allocate space for an event.\n"); 620 mca_log(record); 621 mtx_unlock_spin(&mca_lock); 622 return; 623 } 624 STAILQ_REMOVE_HEAD(&mca_freelist, link); 625 mca_freecount--; 626 } 627 628 rec->rec = *record; 629 STAILQ_INSERT_TAIL(&mca_pending, rec, link); 630 mtx_unlock_spin(&mca_lock); 631 } 632 633 #ifdef DEV_APIC 634 /* 635 * Update the interrupt threshold for a CMCI. The strategy is to use 636 * a low trigger that interrupts as soon as the first event occurs. 637 * However, if a steady stream of events arrive, the threshold is 638 * increased until the interrupts are throttled to once every 639 * cmc_throttle seconds or the periodic scan. If a periodic scan 640 * finds that the threshold is too high, it is lowered. 641 */ 642 static int 643 update_threshold(enum scan_mode mode, int valid, int last_intr, int count, 644 int cur_threshold, int max_threshold) 645 { 646 u_int delta; 647 int limit; 648 649 delta = (u_int)(time_uptime - last_intr); 650 limit = cur_threshold; 651 652 /* 653 * If an interrupt was received less than cmc_throttle seconds 654 * since the previous interrupt and the count from the current 655 * event is greater than or equal to the current threshold, 656 * double the threshold up to the max. 657 */ 658 if (mode == CMCI && valid) { 659 if (delta < cmc_throttle && count >= limit && 660 limit < max_threshold) { 661 limit = min(limit << 1, max_threshold); 662 } 663 return (limit); 664 } 665 666 /* 667 * When the banks are polled, check to see if the threshold 668 * should be lowered. 669 */ 670 if (mode != POLLED) 671 return (limit); 672 673 /* If a CMCI occured recently, do nothing for now. */ 674 if (delta < cmc_throttle) 675 return (limit); 676 677 /* 678 * Compute a new limit based on the average rate of events per 679 * cmc_throttle seconds since the last interrupt. 680 */ 681 if (valid) { 682 limit = count * cmc_throttle / delta; 683 if (limit <= 0) 684 limit = 1; 685 else if (limit > max_threshold) 686 limit = max_threshold; 687 } else { 688 limit = 1; 689 } 690 return (limit); 691 } 692 693 static void 694 cmci_update(enum scan_mode mode, int bank, int valid, struct mca_record *rec) 695 { 696 struct cmc_state *cc; 697 uint64_t ctl; 698 int cur_threshold, new_threshold; 699 int count; 700 701 /* Fetch the current limit for this bank. */ 702 cc = &cmc_state[PCPU_GET(cpuid)][bank]; 703 ctl = rdmsr(MSR_MC_CTL2(bank)); 704 count = (rec->mr_status & MC_STATUS_COR_COUNT) >> 38; 705 cur_threshold = ctl & MC_CTL2_THRESHOLD; 706 707 new_threshold = update_threshold(mode, valid, cc->last_intr, count, 708 cur_threshold, cc->max_threshold); 709 710 if (mode == CMCI && valid) 711 cc->last_intr = time_uptime; 712 if (new_threshold != cur_threshold) { 713 ctl &= ~MC_CTL2_THRESHOLD; 714 ctl |= new_threshold; 715 wrmsr(MSR_MC_CTL2(bank), ctl); 716 } 717 } 718 719 static void 720 amd_thresholding_update(enum scan_mode mode, int bank, int valid) 721 { 722 struct amd_et_state *cc; 723 uint64_t misc; 724 int new_threshold; 725 int count; 726 727 cc = &amd_et_state[PCPU_GET(cpuid)][bank]; 728 misc = rdmsr(mca_msr_ops.misc(bank)); 729 count = (misc & MC_MISC_AMD_CNT_MASK) >> MC_MISC_AMD_CNT_SHIFT; 730 count = count - (MC_MISC_AMD_CNT_MAX - cc->cur_threshold); 731 732 new_threshold = update_threshold(mode, valid, cc->last_intr, count, 733 cc->cur_threshold, MC_MISC_AMD_CNT_MAX); 734 735 cc->cur_threshold = new_threshold; 736 misc &= ~MC_MISC_AMD_CNT_MASK; 737 misc |= (uint64_t)(MC_MISC_AMD_CNT_MAX - cc->cur_threshold) 738 << MC_MISC_AMD_CNT_SHIFT; 739 misc &= ~MC_MISC_AMD_OVERFLOW; 740 wrmsr(mca_msr_ops.misc(bank), misc); 741 if (mode == CMCI && valid) 742 cc->last_intr = time_uptime; 743 } 744 #endif 745 746 /* 747 * This scans all the machine check banks of the current CPU to see if 748 * there are any machine checks. Any non-recoverable errors are 749 * reported immediately via mca_log(). The current thread must be 750 * pinned when this is called. The 'mode' parameter indicates if we 751 * are being called from the MC exception handler, the CMCI handler, 752 * or the periodic poller. In the MC exception case this function 753 * returns true if the system is restartable. Otherwise, it returns a 754 * count of the number of valid MC records found. 755 */ 756 static int 757 mca_scan(enum scan_mode mode, int *recoverablep) 758 { 759 struct mca_record rec; 760 uint64_t mcg_cap, ucmask; 761 int count, i, recoverable, valid; 762 763 count = 0; 764 recoverable = 1; 765 ucmask = MC_STATUS_UC | MC_STATUS_PCC; 766 767 /* When handling a MCE#, treat the OVER flag as non-restartable. */ 768 if (mode == MCE) 769 ucmask |= MC_STATUS_OVER; 770 mcg_cap = rdmsr(MSR_MCG_CAP); 771 for (i = 0; i < (mcg_cap & MCG_CAP_COUNT); i++) { 772 #ifdef DEV_APIC 773 /* 774 * For a CMCI, only check banks this CPU is 775 * responsible for. 776 */ 777 if (mode == CMCI && !(PCPU_GET(cmci_mask) & 1 << i)) 778 continue; 779 #endif 780 781 valid = mca_check_status(i, &rec); 782 if (valid) { 783 count++; 784 if (rec.mr_status & ucmask) { 785 recoverable = 0; 786 mtx_lock_spin(&mca_lock); 787 mca_log(&rec); 788 mtx_unlock_spin(&mca_lock); 789 } 790 mca_record_entry(mode, &rec); 791 } 792 793 #ifdef DEV_APIC 794 /* 795 * If this is a bank this CPU monitors via CMCI, 796 * update the threshold. 797 */ 798 if (PCPU_GET(cmci_mask) & 1 << i) { 799 if (cmc_state != NULL) 800 cmci_update(mode, i, valid, &rec); 801 else 802 amd_thresholding_update(mode, i, valid); 803 } 804 #endif 805 } 806 if (recoverablep != NULL) 807 *recoverablep = recoverable; 808 return (count); 809 } 810 811 /* 812 * Store a new record on the mca_records list while enforcing 813 * mca_maxcount. 814 */ 815 static void 816 mca_store_record(struct mca_internal *mca) 817 { 818 819 /* 820 * If we are storing no records (mca_maxcount == 0), 821 * we just free this record. 822 * 823 * If we are storing records (mca_maxcount != 0) and 824 * we have free space on the list, store the record 825 * and increment mca_count. 826 * 827 * If we are storing records and we do not have free 828 * space on the list, store the new record at the 829 * tail and free the oldest one from the head. 830 */ 831 if (mca_maxcount != 0) 832 STAILQ_INSERT_TAIL(&mca_records, mca, link); 833 if (mca_maxcount < 0 || mca_count < mca_maxcount) 834 mca_count++; 835 else { 836 if (mca_maxcount != 0) { 837 mca = STAILQ_FIRST(&mca_records); 838 STAILQ_REMOVE_HEAD(&mca_records, link); 839 } 840 STAILQ_INSERT_TAIL(&mca_freelist, mca, link); 841 mca_freecount++; 842 } 843 } 844 845 /* 846 * Do the work to process machine check records which have just been 847 * gathered. Print any pending logs to the console. Queue them for storage. 848 * Trigger a resizing of the free list. 849 */ 850 static void 851 mca_process_records(enum scan_mode mode) 852 { 853 struct mca_internal *mca; 854 855 mtx_lock_spin(&mca_lock); 856 while ((mca = STAILQ_FIRST(&mca_pending)) != NULL) { 857 STAILQ_REMOVE_HEAD(&mca_pending, link); 858 mca_log(&mca->rec); 859 mca_store_record(mca); 860 } 861 mtx_unlock_spin(&mca_lock); 862 if (mode == POLLED) 863 mca_resize_freelist(); 864 else if (!cold) 865 taskqueue_enqueue(mca_tq, &mca_resize_task); 866 } 867 868 /* 869 * Scan the machine check banks on all CPUs by binding to each CPU in 870 * turn. If any of the CPUs contained new machine check records, log 871 * them to the console. 872 */ 873 static void 874 mca_scan_cpus(void *context, int pending) 875 { 876 struct thread *td; 877 int count, cpu; 878 879 mca_resize_freelist(); 880 td = curthread; 881 count = 0; 882 thread_lock(td); 883 CPU_FOREACH(cpu) { 884 sched_bind(td, cpu); 885 thread_unlock(td); 886 count += mca_scan(POLLED, NULL); 887 thread_lock(td); 888 sched_unbind(td); 889 } 890 thread_unlock(td); 891 if (count != 0) 892 mca_process_records(POLLED); 893 } 894 895 static void 896 mca_periodic_scan(void *arg) 897 { 898 899 taskqueue_enqueue(mca_tq, &mca_scan_task); 900 callout_reset(&mca_timer, mca_ticks * hz, mca_periodic_scan, NULL); 901 } 902 903 static int 904 sysctl_mca_scan(SYSCTL_HANDLER_ARGS) 905 { 906 int error, i; 907 908 i = 0; 909 error = sysctl_handle_int(oidp, &i, 0, req); 910 if (error) 911 return (error); 912 if (i) 913 taskqueue_enqueue(mca_tq, &mca_scan_task); 914 return (0); 915 } 916 917 static int 918 sysctl_mca_maxcount(SYSCTL_HANDLER_ARGS) 919 { 920 struct mca_internal *mca; 921 int error, i; 922 bool doresize; 923 924 i = mca_maxcount; 925 error = sysctl_handle_int(oidp, &i, 0, req); 926 if (error || req->newptr == NULL) 927 return (error); 928 mtx_lock_spin(&mca_lock); 929 mca_maxcount = i; 930 doresize = false; 931 if (mca_maxcount >= 0) 932 while (mca_count > mca_maxcount) { 933 mca = STAILQ_FIRST(&mca_records); 934 STAILQ_REMOVE_HEAD(&mca_records, link); 935 mca_count--; 936 STAILQ_INSERT_TAIL(&mca_freelist, mca, link); 937 mca_freecount++; 938 doresize = true; 939 } 940 mtx_unlock_spin(&mca_lock); 941 if (doresize && !cold) 942 taskqueue_enqueue(mca_tq, &mca_resize_task); 943 return (error); 944 } 945 946 static void 947 mca_createtq(void *dummy) 948 { 949 if (mca_banks <= 0) 950 return; 951 952 mca_tq = taskqueue_create_fast("mca", M_WAITOK, 953 taskqueue_thread_enqueue, &mca_tq); 954 taskqueue_start_threads(&mca_tq, 1, PI_SWI(SWI_TQ), "mca taskq"); 955 956 /* CMCIs during boot may have claimed items from the freelist. */ 957 mca_resize_freelist(); 958 } 959 SYSINIT(mca_createtq, SI_SUB_CONFIGURE, SI_ORDER_ANY, mca_createtq, NULL); 960 961 static void 962 mca_startup(void *dummy) 963 { 964 965 if (mca_banks <= 0) 966 return; 967 968 callout_reset(&mca_timer, mca_ticks * hz, mca_periodic_scan, NULL); 969 } 970 #ifdef EARLY_AP_STARTUP 971 SYSINIT(mca_startup, SI_SUB_KICK_SCHEDULER, SI_ORDER_ANY, mca_startup, NULL); 972 #else 973 SYSINIT(mca_startup, SI_SUB_SMP, SI_ORDER_ANY, mca_startup, NULL); 974 #endif 975 976 #ifdef DEV_APIC 977 static void 978 cmci_setup(void) 979 { 980 int i; 981 982 cmc_state = malloc((mp_maxid + 1) * sizeof(struct cmc_state *), M_MCA, 983 M_WAITOK); 984 for (i = 0; i <= mp_maxid; i++) 985 cmc_state[i] = malloc(sizeof(struct cmc_state) * mca_banks, 986 M_MCA, M_WAITOK | M_ZERO); 987 SYSCTL_ADD_PROC(NULL, SYSCTL_STATIC_CHILDREN(_hw_mca), OID_AUTO, 988 "cmc_throttle", CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_MPSAFE, 989 &cmc_throttle, 0, sysctl_positive_int, "I", 990 "Interval in seconds to throttle corrected MC interrupts"); 991 } 992 993 static void 994 amd_thresholding_setup(void) 995 { 996 u_int i; 997 998 amd_et_state = malloc((mp_maxid + 1) * sizeof(struct amd_et_state *), 999 M_MCA, M_WAITOK); 1000 for (i = 0; i <= mp_maxid; i++) 1001 amd_et_state[i] = malloc(sizeof(struct amd_et_state) * 1002 mca_banks, M_MCA, M_WAITOK | M_ZERO); 1003 SYSCTL_ADD_PROC(NULL, SYSCTL_STATIC_CHILDREN(_hw_mca), OID_AUTO, 1004 "cmc_throttle", CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_MPSAFE, 1005 &cmc_throttle, 0, sysctl_positive_int, "I", 1006 "Interval in seconds to throttle corrected MC interrupts"); 1007 } 1008 #endif 1009 1010 static void 1011 mca_setup(uint64_t mcg_cap) 1012 { 1013 1014 /* 1015 * On AMD Family 10h processors, unless logging of level one TLB 1016 * parity (L1TP) errors is disabled, enable the recommended workaround 1017 * for Erratum 383. 1018 */ 1019 if (cpu_vendor_id == CPU_VENDOR_AMD && 1020 CPUID_TO_FAMILY(cpu_id) == 0x10 && amd10h_L1TP) 1021 workaround_erratum383 = 1; 1022 1023 mca_banks = mcg_cap & MCG_CAP_COUNT; 1024 mtx_init(&mca_lock, "mca", NULL, MTX_SPIN); 1025 STAILQ_INIT(&mca_records); 1026 STAILQ_INIT(&mca_pending); 1027 TASK_INIT(&mca_scan_task, 0, mca_scan_cpus, NULL); 1028 callout_init(&mca_timer, 1); 1029 STAILQ_INIT(&mca_freelist); 1030 TASK_INIT(&mca_resize_task, 0, mca_resize, NULL); 1031 mca_resize_freelist(); 1032 SYSCTL_ADD_INT(NULL, SYSCTL_STATIC_CHILDREN(_hw_mca), OID_AUTO, 1033 "count", CTLFLAG_RD, (int *)(uintptr_t)&mca_count, 0, 1034 "Record count"); 1035 SYSCTL_ADD_PROC(NULL, SYSCTL_STATIC_CHILDREN(_hw_mca), OID_AUTO, 1036 "maxcount", CTLTYPE_INT | CTLFLAG_RWTUN | CTLFLAG_MPSAFE, 1037 &mca_maxcount, 0, sysctl_mca_maxcount, "I", 1038 "Maximum record count (-1 is unlimited)"); 1039 SYSCTL_ADD_PROC(NULL, SYSCTL_STATIC_CHILDREN(_hw_mca), OID_AUTO, 1040 "interval", CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_MPSAFE, &mca_ticks, 1041 0, sysctl_positive_int, "I", 1042 "Periodic interval in seconds to scan for machine checks"); 1043 SYSCTL_ADD_NODE(NULL, SYSCTL_STATIC_CHILDREN(_hw_mca), OID_AUTO, 1044 "records", CTLFLAG_RD | CTLFLAG_MPSAFE, sysctl_mca_records, 1045 "Machine check records"); 1046 SYSCTL_ADD_PROC(NULL, SYSCTL_STATIC_CHILDREN(_hw_mca), OID_AUTO, 1047 "force_scan", CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_MPSAFE, NULL, 0, 1048 sysctl_mca_scan, "I", "Force an immediate scan for machine checks"); 1049 #ifdef DEV_APIC 1050 if (cmci_supported(mcg_cap)) 1051 cmci_setup(); 1052 else if (amd_thresholding_supported()) 1053 amd_thresholding_setup(); 1054 #endif 1055 } 1056 1057 #ifdef DEV_APIC 1058 /* 1059 * See if we should monitor CMCI for this bank. If CMCI_EN is already 1060 * set in MC_CTL2, then another CPU is responsible for this bank, so 1061 * ignore it. If CMCI_EN returns zero after being set, then this bank 1062 * does not support CMCI_EN. If this CPU sets CMCI_EN, then it should 1063 * now monitor this bank. 1064 */ 1065 static void 1066 cmci_monitor(int i) 1067 { 1068 struct cmc_state *cc; 1069 uint64_t ctl; 1070 1071 KASSERT(i < mca_banks, ("CPU %d has more MC banks", PCPU_GET(cpuid))); 1072 1073 ctl = rdmsr(MSR_MC_CTL2(i)); 1074 if (ctl & MC_CTL2_CMCI_EN) 1075 /* Already monitored by another CPU. */ 1076 return; 1077 1078 /* Set the threshold to one event for now. */ 1079 ctl &= ~MC_CTL2_THRESHOLD; 1080 ctl |= MC_CTL2_CMCI_EN | 1; 1081 wrmsr(MSR_MC_CTL2(i), ctl); 1082 ctl = rdmsr(MSR_MC_CTL2(i)); 1083 if (!(ctl & MC_CTL2_CMCI_EN)) 1084 /* This bank does not support CMCI. */ 1085 return; 1086 1087 cc = &cmc_state[PCPU_GET(cpuid)][i]; 1088 1089 /* Determine maximum threshold. */ 1090 ctl &= ~MC_CTL2_THRESHOLD; 1091 ctl |= 0x7fff; 1092 wrmsr(MSR_MC_CTL2(i), ctl); 1093 ctl = rdmsr(MSR_MC_CTL2(i)); 1094 cc->max_threshold = ctl & MC_CTL2_THRESHOLD; 1095 1096 /* Start off with a threshold of 1. */ 1097 ctl &= ~MC_CTL2_THRESHOLD; 1098 ctl |= 1; 1099 wrmsr(MSR_MC_CTL2(i), ctl); 1100 1101 /* Mark this bank as monitored. */ 1102 PCPU_SET(cmci_mask, PCPU_GET(cmci_mask) | 1 << i); 1103 } 1104 1105 /* 1106 * For resume, reset the threshold for any banks we monitor back to 1107 * one and throw away the timestamp of the last interrupt. 1108 */ 1109 static void 1110 cmci_resume(int i) 1111 { 1112 struct cmc_state *cc; 1113 uint64_t ctl; 1114 1115 KASSERT(i < mca_banks, ("CPU %d has more MC banks", PCPU_GET(cpuid))); 1116 1117 /* Ignore banks not monitored by this CPU. */ 1118 if (!(PCPU_GET(cmci_mask) & 1 << i)) 1119 return; 1120 1121 cc = &cmc_state[PCPU_GET(cpuid)][i]; 1122 cc->last_intr = 0; 1123 ctl = rdmsr(MSR_MC_CTL2(i)); 1124 ctl &= ~MC_CTL2_THRESHOLD; 1125 ctl |= MC_CTL2_CMCI_EN | 1; 1126 wrmsr(MSR_MC_CTL2(i), ctl); 1127 } 1128 1129 /* 1130 * Apply an AMD ET configuration to the corresponding MSR. 1131 */ 1132 static void 1133 amd_thresholding_start(struct amd_et_state *cc, int bank) 1134 { 1135 uint64_t misc; 1136 1137 KASSERT(amd_elvt >= 0, ("ELVT offset is not set")); 1138 1139 misc = rdmsr(mca_msr_ops.misc(bank)); 1140 1141 misc &= ~MC_MISC_AMD_INT_MASK; 1142 misc |= MC_MISC_AMD_INT_LVT; 1143 1144 misc &= ~MC_MISC_AMD_LVT_MASK; 1145 misc |= (uint64_t)amd_elvt << MC_MISC_AMD_LVT_SHIFT; 1146 1147 misc &= ~MC_MISC_AMD_CNT_MASK; 1148 misc |= (uint64_t)(MC_MISC_AMD_CNT_MAX - cc->cur_threshold) 1149 << MC_MISC_AMD_CNT_SHIFT; 1150 1151 misc &= ~MC_MISC_AMD_OVERFLOW; 1152 misc |= MC_MISC_AMD_CNTEN; 1153 1154 wrmsr(mca_msr_ops.misc(bank), misc); 1155 } 1156 1157 static void 1158 amd_thresholding_monitor(int i) 1159 { 1160 struct amd_et_state *cc; 1161 uint64_t misc; 1162 1163 /* 1164 * Kludge: On 10h, banks after 4 are not thresholding but also may have 1165 * bogus Valid bits. Skip them. This is definitely fixed in 15h, but 1166 * I have not investigated whether it is fixed in earlier models. 1167 */ 1168 if (CPUID_TO_FAMILY(cpu_id) < 0x15 && i >= 5) 1169 return; 1170 1171 /* The counter must be valid and present. */ 1172 misc = rdmsr(mca_msr_ops.misc(i)); 1173 if ((misc & (MC_MISC_AMD_VAL | MC_MISC_AMD_CNTP)) != 1174 (MC_MISC_AMD_VAL | MC_MISC_AMD_CNTP)) 1175 return; 1176 1177 /* The register should not be locked. */ 1178 if ((misc & MC_MISC_AMD_LOCK) != 0) { 1179 if (bootverbose) 1180 printf("%s: 0x%jx: Bank %d: locked\n", __func__, 1181 (uintmax_t)misc, i); 1182 return; 1183 } 1184 1185 /* 1186 * If counter is enabled then either the firmware or another CPU 1187 * has already claimed it. 1188 */ 1189 if ((misc & MC_MISC_AMD_CNTEN) != 0) { 1190 if (bootverbose) 1191 printf("%s: 0x%jx: Bank %d: already enabled\n", 1192 __func__, (uintmax_t)misc, i); 1193 return; 1194 } 1195 1196 /* 1197 * Configure an Extended Interrupt LVT register for reporting 1198 * counter overflows if that feature is supported and the first 1199 * extended register is available. 1200 */ 1201 amd_elvt = lapic_enable_mca_elvt(); 1202 if (amd_elvt < 0) { 1203 printf("%s: Bank %d: lapic enable mca elvt failed: %d\n", 1204 __func__, i, amd_elvt); 1205 return; 1206 } 1207 1208 /* Re-use Intel CMC support infrastructure. */ 1209 if (bootverbose) 1210 printf("%s: Starting AMD thresholding on bank %d\n", __func__, 1211 i); 1212 1213 cc = &amd_et_state[PCPU_GET(cpuid)][i]; 1214 cc->cur_threshold = 1; 1215 amd_thresholding_start(cc, i); 1216 1217 /* Mark this bank as monitored. */ 1218 PCPU_SET(cmci_mask, PCPU_GET(cmci_mask) | 1 << i); 1219 } 1220 1221 static void 1222 amd_thresholding_resume(int i) 1223 { 1224 struct amd_et_state *cc; 1225 1226 KASSERT(i < mca_banks, ("CPU %d has more MC banks", PCPU_GET(cpuid))); 1227 1228 /* Ignore banks not monitored by this CPU. */ 1229 if (!(PCPU_GET(cmci_mask) & 1 << i)) 1230 return; 1231 1232 cc = &amd_et_state[PCPU_GET(cpuid)][i]; 1233 cc->last_intr = 0; 1234 cc->cur_threshold = 1; 1235 amd_thresholding_start(cc, i); 1236 } 1237 #endif 1238 1239 /* 1240 * Initializes per-CPU machine check registers and enables corrected 1241 * machine check interrupts. 1242 */ 1243 static void 1244 _mca_init(int boot) 1245 { 1246 uint64_t mcg_cap; 1247 uint64_t ctl, mask; 1248 int i, skip, family; 1249 1250 family = CPUID_TO_FAMILY(cpu_id); 1251 1252 /* MCE is required. */ 1253 if (!mca_enabled || !(cpu_feature & CPUID_MCE)) 1254 return; 1255 1256 if (cpu_feature & CPUID_MCA) { 1257 if (boot) 1258 PCPU_SET(cmci_mask, 0); 1259 1260 mcg_cap = rdmsr(MSR_MCG_CAP); 1261 if (mcg_cap & MCG_CAP_CTL_P) 1262 /* Enable MCA features. */ 1263 wrmsr(MSR_MCG_CTL, MCG_CTL_ENABLE); 1264 if (IS_BSP() && boot) 1265 mca_setup(mcg_cap); 1266 1267 /* 1268 * Disable logging of level one TLB parity (L1TP) errors by 1269 * the data cache as an alternative workaround for AMD Family 1270 * 10h Erratum 383. Unlike the recommended workaround, there 1271 * is no performance penalty to this workaround. However, 1272 * L1TP errors will go unreported. 1273 */ 1274 if (cpu_vendor_id == CPU_VENDOR_AMD && family == 0x10 && 1275 !amd10h_L1TP) { 1276 mask = rdmsr(MSR_MC0_CTL_MASK); 1277 if ((mask & (1UL << 5)) == 0) 1278 wrmsr(MSR_MC0_CTL_MASK, mask | (1UL << 5)); 1279 } 1280 if (amd_rascap & AMDRAS_SCALABLE_MCA) { 1281 mca_msr_ops.ctl = mca_smca_ctl_reg; 1282 mca_msr_ops.status = mca_smca_status_reg; 1283 mca_msr_ops.addr = mca_smca_addr_reg; 1284 mca_msr_ops.misc = mca_smca_misc_reg; 1285 } 1286 1287 /* 1288 * The cmci_monitor() must not be executed 1289 * simultaneously by several CPUs. 1290 */ 1291 if (boot) 1292 mtx_lock_spin(&mca_lock); 1293 1294 for (i = 0; i < (mcg_cap & MCG_CAP_COUNT); i++) { 1295 /* By default enable logging of all errors. */ 1296 ctl = 0xffffffffffffffffUL; 1297 skip = 0; 1298 1299 if (cpu_vendor_id == CPU_VENDOR_INTEL) { 1300 /* 1301 * For P6 models before Nehalem MC0_CTL is 1302 * always enabled and reserved. 1303 */ 1304 if (i == 0 && family == 0x6 1305 && CPUID_TO_MODEL(cpu_id) < 0x1a) 1306 skip = 1; 1307 } else if (cpu_vendor_id == CPU_VENDOR_AMD) { 1308 /* BKDG for Family 10h: unset GartTblWkEn. */ 1309 if (i == MC_AMDNB_BANK && family >= 0xf && 1310 family < 0x17) 1311 ctl &= ~(1UL << 10); 1312 } 1313 1314 if (!skip) 1315 wrmsr(mca_msr_ops.ctl(i), ctl); 1316 1317 #ifdef DEV_APIC 1318 if (cmci_supported(mcg_cap)) { 1319 if (boot) 1320 cmci_monitor(i); 1321 else 1322 cmci_resume(i); 1323 } else if (amd_thresholding_supported()) { 1324 if (boot) 1325 amd_thresholding_monitor(i); 1326 else 1327 amd_thresholding_resume(i); 1328 } 1329 #endif 1330 1331 /* Clear all errors. */ 1332 wrmsr(mca_msr_ops.status(i), 0); 1333 } 1334 if (boot) 1335 mtx_unlock_spin(&mca_lock); 1336 1337 #ifdef DEV_APIC 1338 if (!amd_thresholding_supported() && 1339 PCPU_GET(cmci_mask) != 0 && boot) 1340 lapic_enable_cmc(); 1341 #endif 1342 } 1343 1344 load_cr4(rcr4() | CR4_MCE); 1345 } 1346 1347 /* Must be executed on each CPU during boot. */ 1348 void 1349 mca_init(void) 1350 { 1351 1352 _mca_init(1); 1353 } 1354 1355 /* Must be executed on each CPU during resume. */ 1356 void 1357 mca_resume(void) 1358 { 1359 1360 _mca_init(0); 1361 } 1362 1363 /* 1364 * The machine check registers for the BSP cannot be initialized until 1365 * the local APIC is initialized. This happens at SI_SUB_CPU, 1366 * SI_ORDER_SECOND. 1367 */ 1368 static void 1369 mca_init_bsp(void *arg __unused) 1370 { 1371 1372 mca_init(); 1373 } 1374 SYSINIT(mca_init_bsp, SI_SUB_CPU, SI_ORDER_ANY, mca_init_bsp, NULL); 1375 1376 /* Called when a machine check exception fires. */ 1377 void 1378 mca_intr(void) 1379 { 1380 uint64_t mcg_status; 1381 int recoverable, count; 1382 1383 if (!(cpu_feature & CPUID_MCA)) { 1384 /* 1385 * Just print the values of the old Pentium registers 1386 * and panic. 1387 */ 1388 printf("MC Type: 0x%jx Address: 0x%jx\n", 1389 (uintmax_t)rdmsr(MSR_P5_MC_TYPE), 1390 (uintmax_t)rdmsr(MSR_P5_MC_ADDR)); 1391 panic("Machine check"); 1392 } 1393 1394 /* Scan the banks and check for any non-recoverable errors. */ 1395 count = mca_scan(MCE, &recoverable); 1396 mcg_status = rdmsr(MSR_MCG_STATUS); 1397 if (!(mcg_status & MCG_STATUS_RIPV)) 1398 recoverable = 0; 1399 1400 if (!recoverable) { 1401 /* 1402 * Only panic if the error was detected local to this CPU. 1403 * Some errors will assert a machine check on all CPUs, but 1404 * only certain CPUs will find a valid bank to log. 1405 */ 1406 while (count == 0) 1407 cpu_spinwait(); 1408 1409 panic("Unrecoverable machine check exception"); 1410 } 1411 1412 /* Clear MCIP. */ 1413 wrmsr(MSR_MCG_STATUS, mcg_status & ~MCG_STATUS_MCIP); 1414 } 1415 1416 #ifdef DEV_APIC 1417 /* Called for a CMCI (correctable machine check interrupt). */ 1418 void 1419 cmc_intr(void) 1420 { 1421 1422 /* 1423 * Serialize MCA bank scanning to prevent collisions from 1424 * sibling threads. 1425 * 1426 * If we found anything, log them to the console. 1427 */ 1428 if (mca_scan(CMCI, NULL) != 0) 1429 mca_process_records(CMCI); 1430 } 1431 #endif 1432