1 /*- 2 * Copyright (c) 2003 John Baldwin <jhb@FreeBSD.org> 3 * Copyright (c) 1996, by Steve Passe 4 * All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. The name of the developer may NOT be used to endorse or promote products 12 * derived from this software without specific prior written permission. 13 * 14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24 * SUCH DAMAGE. 25 */ 26 27 #include <sys/cdefs.h> 28 __FBSDID("$FreeBSD$"); 29 30 #include "opt_mptable_force_htt.h" 31 #include <sys/param.h> 32 #include <sys/systm.h> 33 #include <sys/bus.h> 34 #include <sys/kernel.h> 35 #include <sys/limits.h> 36 #include <sys/malloc.h> 37 #include <sys/smp.h> 38 #ifdef NEW_PCIB 39 #include <sys/rman.h> 40 #endif 41 42 #include <vm/vm.h> 43 #include <vm/vm_param.h> 44 #include <vm/pmap.h> 45 46 #include <dev/pci/pcivar.h> 47 #ifdef NEW_PCIB 48 #include <dev/pci/pcib_private.h> 49 #endif 50 #include <x86/apicreg.h> 51 #include <x86/mptable.h> 52 #include <machine/frame.h> 53 #include <machine/intr_machdep.h> 54 #include <x86/apicvar.h> 55 #include <machine/md_var.h> 56 #ifdef NEW_PCIB 57 #include <machine/resource.h> 58 #endif 59 #include <machine/specialreg.h> 60 61 /* string defined by the Intel MP Spec as identifying the MP table */ 62 #define MP_SIG 0x5f504d5f /* _MP_ */ 63 64 #ifdef __amd64__ 65 #define MAX_LAPIC_ID 63 /* Max local APIC ID for HTT fixup */ 66 #else 67 #define MAX_LAPIC_ID 31 /* Max local APIC ID for HTT fixup */ 68 #endif 69 70 #define BIOS_BASE (0xf0000) 71 #define BIOS_SIZE (0x10000) 72 #define BIOS_COUNT (BIOS_SIZE/4) 73 74 typedef void mptable_entry_handler(u_char *entry, void *arg); 75 typedef void mptable_extended_entry_handler(ext_entry_ptr entry, void *arg); 76 77 /* descriptions of MP table entries */ 78 typedef struct BASETABLE_ENTRY { 79 uint8_t type; 80 uint8_t length; 81 uint8_t name[16]; 82 } basetable_entry; 83 84 static basetable_entry basetable_entry_types[] = 85 { 86 {0, 20, "Processor"}, 87 {1, 8, "Bus"}, 88 {2, 8, "I/O APIC"}, 89 {3, 8, "I/O INT"}, 90 {4, 8, "Local INT"} 91 }; 92 93 typedef struct BUSDATA { 94 u_char bus_id; 95 enum busTypes bus_type; 96 } bus_datum; 97 98 typedef struct INTDATA { 99 u_char int_type; 100 u_short int_flags; 101 u_char src_bus_id; 102 u_char src_bus_irq; 103 u_char dst_apic_id; 104 u_char dst_apic_int; 105 u_char int_vector; 106 } io_int, local_int; 107 108 typedef struct BUSTYPENAME { 109 u_char type; 110 char name[7]; 111 } bus_type_name; 112 113 /* From MP spec v1.4, table 4-8. */ 114 static bus_type_name bus_type_table[] = 115 { 116 {UNKNOWN_BUSTYPE, "CBUS "}, 117 {UNKNOWN_BUSTYPE, "CBUSII"}, 118 {EISA, "EISA "}, 119 {UNKNOWN_BUSTYPE, "FUTURE"}, 120 {UNKNOWN_BUSTYPE, "INTERN"}, 121 {ISA, "ISA "}, 122 {UNKNOWN_BUSTYPE, "MBI "}, 123 {UNKNOWN_BUSTYPE, "MBII "}, 124 {MCA, "MCA "}, 125 {UNKNOWN_BUSTYPE, "MPI "}, 126 {UNKNOWN_BUSTYPE, "MPSA "}, 127 {UNKNOWN_BUSTYPE, "NUBUS "}, 128 {PCI, "PCI "}, 129 {UNKNOWN_BUSTYPE, "PCMCIA"}, 130 {UNKNOWN_BUSTYPE, "TC "}, 131 {UNKNOWN_BUSTYPE, "VL "}, 132 {UNKNOWN_BUSTYPE, "VME "}, 133 {UNKNOWN_BUSTYPE, "XPRESS"} 134 }; 135 136 /* From MP spec v1.4, table 5-1. */ 137 static int default_data[7][5] = 138 { 139 /* nbus, id0, type0, id1, type1 */ 140 {1, 0, ISA, 255, NOBUS}, 141 {1, 0, EISA, 255, NOBUS}, 142 {1, 0, EISA, 255, NOBUS}, 143 {1, 0, MCA, 255, NOBUS}, 144 {2, 0, ISA, 1, PCI}, 145 {2, 0, EISA, 1, PCI}, 146 {2, 0, MCA, 1, PCI} 147 }; 148 149 struct pci_probe_table_args { 150 u_char bus; 151 u_char found; 152 }; 153 154 struct pci_route_interrupt_args { 155 u_char bus; /* Source bus. */ 156 u_char irq; /* Source slot:pin. */ 157 int vector; /* Return value. */ 158 }; 159 160 static mpfps_t mpfps; 161 static mpcth_t mpct; 162 static ext_entry_ptr mpet; 163 static void *ioapics[IOAPIC_MAX_ID + 1]; 164 static bus_datum *busses; 165 static int mptable_nioapics, mptable_nbusses, mptable_maxbusid; 166 static int pci0 = -1; 167 168 static MALLOC_DEFINE(M_MPTABLE, "mptable", "MP Table Items"); 169 170 static enum intr_polarity conforming_polarity(u_char src_bus, 171 u_char src_bus_irq); 172 static enum intr_trigger conforming_trigger(u_char src_bus, u_char src_bus_irq); 173 static enum intr_polarity intentry_polarity(int_entry_ptr intr); 174 static enum intr_trigger intentry_trigger(int_entry_ptr intr); 175 static int lookup_bus_type(char *name); 176 static void mptable_count_items(void); 177 static void mptable_count_items_handler(u_char *entry, void *arg); 178 #ifdef MPTABLE_FORCE_HTT 179 static void mptable_hyperthread_fixup(u_int id_mask); 180 #endif 181 static void mptable_parse_apics_and_busses(void); 182 static void mptable_parse_apics_and_busses_handler(u_char *entry, 183 void *arg); 184 static void mptable_parse_default_config_ints(void); 185 static void mptable_parse_ints(void); 186 static void mptable_parse_ints_handler(u_char *entry, void *arg); 187 static void mptable_parse_io_int(int_entry_ptr intr); 188 static void mptable_parse_local_int(int_entry_ptr intr); 189 static void mptable_pci_probe_table_handler(u_char *entry, void *arg); 190 static void mptable_pci_route_interrupt_handler(u_char *entry, void *arg); 191 static void mptable_pci_setup(void); 192 static int mptable_probe(void); 193 static int mptable_probe_cpus(void); 194 static void mptable_probe_cpus_handler(u_char *entry, void *arg __unused); 195 static void mptable_setup_cpus_handler(u_char *entry, void *arg __unused); 196 static void mptable_register(void *dummy); 197 static int mptable_setup_local(void); 198 static int mptable_setup_io(void); 199 #ifdef NEW_PCIB 200 static void mptable_walk_extended_table( 201 mptable_extended_entry_handler *handler, void *arg); 202 #endif 203 static void mptable_walk_table(mptable_entry_handler *handler, void *arg); 204 static int search_for_sig(u_int32_t target, int count); 205 206 static struct apic_enumerator mptable_enumerator = { 207 "MPTable", 208 mptable_probe, 209 mptable_probe_cpus, 210 mptable_setup_local, 211 mptable_setup_io 212 }; 213 214 /* 215 * look for the MP spec signature 216 */ 217 218 static int 219 search_for_sig(u_int32_t target, int count) 220 { 221 int x; 222 u_int32_t *addr = (u_int32_t *) (KERNBASE + target); 223 224 for (x = 0; x < count; x += 4) 225 if (addr[x] == MP_SIG) 226 /* make array index a byte index */ 227 return (target + (x * sizeof(u_int32_t))); 228 return (-1); 229 } 230 231 static int 232 lookup_bus_type(char *name) 233 { 234 int x; 235 236 for (x = 0; x < MAX_BUSTYPE; ++x) 237 if (strncmp(bus_type_table[x].name, name, 6) == 0) 238 return (bus_type_table[x].type); 239 240 return (UNKNOWN_BUSTYPE); 241 } 242 243 /* 244 * Look for an Intel MP spec table (ie, SMP capable hardware). 245 */ 246 static int 247 mptable_probe(void) 248 { 249 int x; 250 u_long segment; 251 u_int32_t target; 252 253 /* see if EBDA exists */ 254 if ((segment = (u_long) * (u_short *) (KERNBASE + 0x40e)) != 0) { 255 /* search first 1K of EBDA */ 256 target = (u_int32_t) (segment << 4); 257 if ((x = search_for_sig(target, 1024 / 4)) >= 0) 258 goto found; 259 } else { 260 /* last 1K of base memory, effective 'top of base' passed in */ 261 target = (u_int32_t) ((basemem * 1024) - 0x400); 262 if ((x = search_for_sig(target, 1024 / 4)) >= 0) 263 goto found; 264 } 265 266 /* search the BIOS */ 267 target = (u_int32_t) BIOS_BASE; 268 if ((x = search_for_sig(target, BIOS_COUNT)) >= 0) 269 goto found; 270 271 /* nothing found */ 272 return (ENXIO); 273 274 found: 275 mpfps = (mpfps_t)(KERNBASE + x); 276 277 /* Map in the configuration table if it exists. */ 278 if (mpfps->config_type != 0) { 279 if (bootverbose) 280 printf( 281 "MP Table version 1.%d found using Default Configuration %d\n", 282 mpfps->spec_rev, mpfps->config_type); 283 if (mpfps->config_type != 5 && mpfps->config_type != 6) { 284 printf( 285 "MP Table Default Configuration %d is unsupported\n", 286 mpfps->config_type); 287 return (ENXIO); 288 } 289 mpct = NULL; 290 } else { 291 if ((uintptr_t)mpfps->pap >= 1024 * 1024) { 292 printf("%s: Unable to map MP Configuration Table\n", 293 __func__); 294 return (ENXIO); 295 } 296 mpct = (mpcth_t)(KERNBASE + (uintptr_t)mpfps->pap); 297 if (mpct->base_table_length + (uintptr_t)mpfps->pap >= 298 1024 * 1024) { 299 printf("%s: Unable to map end of MP Config Table\n", 300 __func__); 301 return (ENXIO); 302 } 303 if (mpct->extended_table_length != 0 && 304 mpct->extended_table_length + mpct->base_table_length + 305 (uintptr_t)mpfps->pap < 1024 * 1024) 306 mpet = (ext_entry_ptr)((char *)mpct + 307 mpct->base_table_length); 308 if (mpct->signature[0] != 'P' || mpct->signature[1] != 'C' || 309 mpct->signature[2] != 'M' || mpct->signature[3] != 'P') { 310 printf("%s: MP Config Table has bad signature: %c%c%c%c\n", 311 __func__, mpct->signature[0], mpct->signature[1], 312 mpct->signature[2], mpct->signature[3]); 313 return (ENXIO); 314 } 315 if (bootverbose) 316 printf( 317 "MP Configuration Table version 1.%d found at %p\n", 318 mpct->spec_rev, mpct); 319 } 320 321 return (-100); 322 } 323 324 /* 325 * Run through the MP table enumerating CPUs. 326 */ 327 static int 328 mptable_probe_cpus(void) 329 { 330 u_int cpu_mask; 331 332 /* Is this a pre-defined config? */ 333 if (mpfps->config_type != 0) { 334 #ifdef SMP 335 mp_ncpus = 2; 336 mp_maxid = 1; 337 #endif 338 max_apic_id = 1; 339 } else { 340 mptable_walk_table(mptable_probe_cpus_handler, &cpu_mask); 341 } 342 return (0); 343 } 344 345 /* 346 * Initialize the local APIC on the BSP. 347 */ 348 static int 349 mptable_setup_local(void) 350 { 351 vm_paddr_t addr; 352 u_int cpu_mask; 353 354 /* Is this a pre-defined config? */ 355 printf("MPTable: <"); 356 if (mpfps->config_type != 0) { 357 lapic_create(0, 1); 358 lapic_create(1, 0); 359 addr = DEFAULT_APIC_BASE; 360 printf("Default Configuration %d", mpfps->config_type); 361 362 } else { 363 cpu_mask = 0; 364 mptable_walk_table(mptable_setup_cpus_handler, &cpu_mask); 365 #ifdef MPTABLE_FORCE_HTT 366 mptable_hyperthread_fixup(cpu_mask); 367 #endif 368 addr = mpct->apic_address; 369 printf("%.*s %.*s", (int)sizeof(mpct->oem_id), mpct->oem_id, 370 (int)sizeof(mpct->product_id), mpct->product_id); 371 } 372 printf(">\n"); 373 lapic_init(addr); 374 return (0); 375 } 376 377 /* 378 * Run through the MP table enumerating I/O APICs. 379 */ 380 static int 381 mptable_setup_io(void) 382 { 383 int i; 384 u_char byte; 385 386 /* First, we count individual items and allocate arrays. */ 387 mptable_count_items(); 388 busses = malloc((mptable_maxbusid + 1) * sizeof(bus_datum), M_MPTABLE, 389 M_WAITOK); 390 for (i = 0; i <= mptable_maxbusid; i++) 391 busses[i].bus_type = NOBUS; 392 393 /* Second, we run through adding I/O APIC's and buses. */ 394 mptable_parse_apics_and_busses(); 395 396 /* Third, we run through the table tweaking interrupt sources. */ 397 mptable_parse_ints(); 398 399 /* Fourth, we register all the I/O APIC's. */ 400 for (i = 0; i <= IOAPIC_MAX_ID; i++) 401 if (ioapics[i] != NULL) 402 ioapic_register(ioapics[i]); 403 404 /* Fifth, we setup data structures to handle PCI interrupt routing. */ 405 mptable_pci_setup(); 406 407 /* Finally, we throw the switch to enable the I/O APIC's. */ 408 if (mpfps->mpfb2 & MPFB2_IMCR_PRESENT) { 409 outb(0x22, 0x70); /* select IMCR */ 410 byte = inb(0x23); /* current contents */ 411 byte |= 0x01; /* mask external INTR */ 412 outb(0x23, byte); /* disconnect 8259s/NMI */ 413 } 414 415 return (0); 416 } 417 418 static void 419 mptable_register(void *dummy __unused) 420 { 421 422 apic_register_enumerator(&mptable_enumerator); 423 } 424 SYSINIT(mptable_register, SI_SUB_TUNABLES - 1, SI_ORDER_FIRST, mptable_register, 425 NULL); 426 427 /* 428 * Call the handler routine for each entry in the MP config base table. 429 */ 430 static void 431 mptable_walk_table(mptable_entry_handler *handler, void *arg) 432 { 433 u_int i; 434 u_char *entry; 435 436 entry = (u_char *)(mpct + 1); 437 for (i = 0; i < mpct->entry_count; i++) { 438 switch (*entry) { 439 case MPCT_ENTRY_PROCESSOR: 440 case MPCT_ENTRY_IOAPIC: 441 case MPCT_ENTRY_BUS: 442 case MPCT_ENTRY_INT: 443 case MPCT_ENTRY_LOCAL_INT: 444 break; 445 default: 446 panic("%s: Unknown MP Config Entry %d\n", __func__, 447 (int)*entry); 448 } 449 handler(entry, arg); 450 entry += basetable_entry_types[*entry].length; 451 } 452 } 453 454 #ifdef NEW_PCIB 455 /* 456 * Call the handler routine for each entry in the MP config extended 457 * table. 458 */ 459 static void 460 mptable_walk_extended_table(mptable_extended_entry_handler *handler, void *arg) 461 { 462 ext_entry_ptr end, entry; 463 464 if (mpet == NULL) 465 return; 466 entry = mpet; 467 end = (ext_entry_ptr)((char *)mpet + mpct->extended_table_length); 468 while (entry < end) { 469 handler(entry, arg); 470 entry = (ext_entry_ptr)((char *)entry + entry->length); 471 } 472 } 473 #endif 474 475 static void 476 mptable_probe_cpus_handler(u_char *entry, void *arg) 477 { 478 proc_entry_ptr proc; 479 480 switch (*entry) { 481 case MPCT_ENTRY_PROCESSOR: 482 proc = (proc_entry_ptr)entry; 483 if (proc->cpu_flags & PROCENTRY_FLAG_EN && 484 proc->apic_id < MAX_LAPIC_ID && mp_ncpus < MAXCPU) { 485 #ifdef SMP 486 mp_ncpus++; 487 mp_maxid = mp_ncpus - 1; 488 #endif 489 max_apic_id = max(max_apic_id, proc->apic_id); 490 } 491 break; 492 } 493 } 494 495 496 static void 497 mptable_setup_cpus_handler(u_char *entry, void *arg) 498 { 499 proc_entry_ptr proc; 500 u_int *cpu_mask; 501 502 switch (*entry) { 503 case MPCT_ENTRY_PROCESSOR: 504 proc = (proc_entry_ptr)entry; 505 if (proc->cpu_flags & PROCENTRY_FLAG_EN) { 506 lapic_create(proc->apic_id, proc->cpu_flags & 507 PROCENTRY_FLAG_BP); 508 if (proc->apic_id < MAX_LAPIC_ID) { 509 cpu_mask = (u_int *)arg; 510 *cpu_mask |= (1ul << proc->apic_id); 511 } 512 } 513 break; 514 } 515 } 516 517 static void 518 mptable_count_items_handler(u_char *entry, void *arg __unused) 519 { 520 io_apic_entry_ptr apic; 521 bus_entry_ptr bus; 522 523 switch (*entry) { 524 case MPCT_ENTRY_BUS: 525 bus = (bus_entry_ptr)entry; 526 mptable_nbusses++; 527 if (bus->bus_id > mptable_maxbusid) 528 mptable_maxbusid = bus->bus_id; 529 break; 530 case MPCT_ENTRY_IOAPIC: 531 apic = (io_apic_entry_ptr)entry; 532 if (apic->apic_flags & IOAPICENTRY_FLAG_EN) 533 mptable_nioapics++; 534 break; 535 } 536 } 537 538 /* 539 * Count items in the table. 540 */ 541 static void 542 mptable_count_items(void) 543 { 544 545 /* Is this a pre-defined config? */ 546 if (mpfps->config_type != 0) { 547 mptable_nioapics = 1; 548 switch (mpfps->config_type) { 549 case 1: 550 case 2: 551 case 3: 552 case 4: 553 mptable_nbusses = 1; 554 break; 555 case 5: 556 case 6: 557 case 7: 558 mptable_nbusses = 2; 559 break; 560 default: 561 panic("Unknown pre-defined MP Table config type %d", 562 mpfps->config_type); 563 } 564 mptable_maxbusid = mptable_nbusses - 1; 565 } else 566 mptable_walk_table(mptable_count_items_handler, NULL); 567 } 568 569 /* 570 * Add a bus or I/O APIC from an entry in the table. 571 */ 572 static void 573 mptable_parse_apics_and_busses_handler(u_char *entry, void *arg __unused) 574 { 575 io_apic_entry_ptr apic; 576 bus_entry_ptr bus; 577 enum busTypes bus_type; 578 int i; 579 580 581 switch (*entry) { 582 case MPCT_ENTRY_BUS: 583 bus = (bus_entry_ptr)entry; 584 bus_type = lookup_bus_type(bus->bus_type); 585 if (bus_type == UNKNOWN_BUSTYPE) { 586 printf("MPTable: Unknown bus %d type \"", bus->bus_id); 587 for (i = 0; i < 6; i++) 588 printf("%c", bus->bus_type[i]); 589 printf("\"\n"); 590 } 591 busses[bus->bus_id].bus_id = bus->bus_id; 592 busses[bus->bus_id].bus_type = bus_type; 593 break; 594 case MPCT_ENTRY_IOAPIC: 595 apic = (io_apic_entry_ptr)entry; 596 if (!(apic->apic_flags & IOAPICENTRY_FLAG_EN)) 597 break; 598 if (apic->apic_id > IOAPIC_MAX_ID) 599 panic("%s: I/O APIC ID %d too high", __func__, 600 apic->apic_id); 601 if (ioapics[apic->apic_id] != NULL) 602 panic("%s: Double APIC ID %d", __func__, 603 apic->apic_id); 604 ioapics[apic->apic_id] = ioapic_create(apic->apic_address, 605 apic->apic_id, -1); 606 break; 607 default: 608 break; 609 } 610 } 611 612 /* 613 * Enumerate I/O APIC's and buses. 614 */ 615 static void 616 mptable_parse_apics_and_busses(void) 617 { 618 619 /* Is this a pre-defined config? */ 620 if (mpfps->config_type != 0) { 621 ioapics[2] = ioapic_create(DEFAULT_IO_APIC_BASE, 2, 0); 622 busses[0].bus_id = 0; 623 busses[0].bus_type = default_data[mpfps->config_type - 1][2]; 624 if (mptable_nbusses > 1) { 625 busses[1].bus_id = 1; 626 busses[1].bus_type = 627 default_data[mpfps->config_type - 1][4]; 628 } 629 } else 630 mptable_walk_table(mptable_parse_apics_and_busses_handler, 631 NULL); 632 } 633 634 /* 635 * Determine conforming polarity for a given bus type. 636 */ 637 static enum intr_polarity 638 conforming_polarity(u_char src_bus, u_char src_bus_irq) 639 { 640 641 KASSERT(src_bus <= mptable_maxbusid, ("bus id %d too large", src_bus)); 642 switch (busses[src_bus].bus_type) { 643 case ISA: 644 case EISA: 645 return (INTR_POLARITY_HIGH); 646 case PCI: 647 return (INTR_POLARITY_LOW); 648 default: 649 panic("%s: unknown bus type %d", __func__, 650 busses[src_bus].bus_type); 651 } 652 } 653 654 /* 655 * Determine conforming trigger for a given bus type. 656 */ 657 static enum intr_trigger 658 conforming_trigger(u_char src_bus, u_char src_bus_irq) 659 { 660 661 KASSERT(src_bus <= mptable_maxbusid, ("bus id %d too large", src_bus)); 662 switch (busses[src_bus].bus_type) { 663 case ISA: 664 if (elcr_found) 665 return (elcr_read_trigger(src_bus_irq)); 666 else 667 return (INTR_TRIGGER_EDGE); 668 case PCI: 669 return (INTR_TRIGGER_LEVEL); 670 671 case EISA: 672 KASSERT(src_bus_irq < 16, ("Invalid EISA IRQ %d", src_bus_irq)); 673 KASSERT(elcr_found, ("Missing ELCR")); 674 return (elcr_read_trigger(src_bus_irq)); 675 676 default: 677 panic("%s: unknown bus type %d", __func__, 678 busses[src_bus].bus_type); 679 } 680 } 681 682 static enum intr_polarity 683 intentry_polarity(int_entry_ptr intr) 684 { 685 686 switch (intr->int_flags & INTENTRY_FLAGS_POLARITY) { 687 case INTENTRY_FLAGS_POLARITY_CONFORM: 688 return (conforming_polarity(intr->src_bus_id, 689 intr->src_bus_irq)); 690 case INTENTRY_FLAGS_POLARITY_ACTIVEHI: 691 return (INTR_POLARITY_HIGH); 692 case INTENTRY_FLAGS_POLARITY_ACTIVELO: 693 return (INTR_POLARITY_LOW); 694 default: 695 panic("Bogus interrupt flags"); 696 } 697 } 698 699 static enum intr_trigger 700 intentry_trigger(int_entry_ptr intr) 701 { 702 703 switch (intr->int_flags & INTENTRY_FLAGS_TRIGGER) { 704 case INTENTRY_FLAGS_TRIGGER_CONFORM: 705 return (conforming_trigger(intr->src_bus_id, 706 intr->src_bus_irq)); 707 case INTENTRY_FLAGS_TRIGGER_EDGE: 708 return (INTR_TRIGGER_EDGE); 709 case INTENTRY_FLAGS_TRIGGER_LEVEL: 710 return (INTR_TRIGGER_LEVEL); 711 default: 712 panic("Bogus interrupt flags"); 713 } 714 } 715 716 /* 717 * Parse an interrupt entry for an I/O interrupt routed to a pin on an I/O APIC. 718 */ 719 static void 720 mptable_parse_io_int(int_entry_ptr intr) 721 { 722 void *ioapic; 723 u_int pin, apic_id; 724 725 apic_id = intr->dst_apic_id; 726 if (intr->dst_apic_id == 0xff) { 727 /* 728 * An APIC ID of 0xff means that the interrupt is connected 729 * to the specified pin on all I/O APICs in the system. If 730 * there is only one I/O APIC, then use that APIC to route 731 * the interrupts. If there is more than one I/O APIC, then 732 * punt. 733 */ 734 if (mptable_nioapics == 1) { 735 apic_id = 0; 736 while (ioapics[apic_id] == NULL) 737 apic_id++; 738 } else { 739 printf( 740 "MPTable: Ignoring global interrupt entry for pin %d\n", 741 intr->dst_apic_int); 742 return; 743 } 744 } 745 if (apic_id > IOAPIC_MAX_ID) { 746 printf("MPTable: Ignoring interrupt entry for ioapic%d\n", 747 intr->dst_apic_id); 748 return; 749 } 750 ioapic = ioapics[apic_id]; 751 if (ioapic == NULL) { 752 printf( 753 "MPTable: Ignoring interrupt entry for missing ioapic%d\n", 754 apic_id); 755 return; 756 } 757 pin = intr->dst_apic_int; 758 switch (intr->int_type) { 759 case INTENTRY_TYPE_INT: 760 switch (busses[intr->src_bus_id].bus_type) { 761 case NOBUS: 762 panic("interrupt from missing bus"); 763 case ISA: 764 case EISA: 765 if (busses[intr->src_bus_id].bus_type == ISA) 766 ioapic_set_bus(ioapic, pin, APIC_BUS_ISA); 767 else 768 ioapic_set_bus(ioapic, pin, APIC_BUS_EISA); 769 if (intr->src_bus_irq == pin) 770 break; 771 ioapic_remap_vector(ioapic, pin, intr->src_bus_irq); 772 if (ioapic_get_vector(ioapic, intr->src_bus_irq) == 773 intr->src_bus_irq) 774 ioapic_disable_pin(ioapic, intr->src_bus_irq); 775 break; 776 case PCI: 777 ioapic_set_bus(ioapic, pin, APIC_BUS_PCI); 778 break; 779 default: 780 ioapic_set_bus(ioapic, pin, APIC_BUS_UNKNOWN); 781 break; 782 } 783 break; 784 case INTENTRY_TYPE_NMI: 785 ioapic_set_nmi(ioapic, pin); 786 break; 787 case INTENTRY_TYPE_SMI: 788 ioapic_set_smi(ioapic, pin); 789 break; 790 case INTENTRY_TYPE_EXTINT: 791 ioapic_set_extint(ioapic, pin); 792 break; 793 default: 794 panic("%s: invalid interrupt entry type %d\n", __func__, 795 intr->int_type); 796 } 797 if (intr->int_type == INTENTRY_TYPE_INT || 798 (intr->int_flags & INTENTRY_FLAGS_TRIGGER) != 799 INTENTRY_FLAGS_TRIGGER_CONFORM) 800 ioapic_set_triggermode(ioapic, pin, intentry_trigger(intr)); 801 if (intr->int_type == INTENTRY_TYPE_INT || 802 (intr->int_flags & INTENTRY_FLAGS_POLARITY) != 803 INTENTRY_FLAGS_POLARITY_CONFORM) 804 ioapic_set_polarity(ioapic, pin, intentry_polarity(intr)); 805 } 806 807 /* 808 * Parse an interrupt entry for a local APIC LVT pin. 809 */ 810 static void 811 mptable_parse_local_int(int_entry_ptr intr) 812 { 813 u_int apic_id, pin; 814 815 if (intr->dst_apic_id == 0xff) 816 apic_id = APIC_ID_ALL; 817 else 818 apic_id = intr->dst_apic_id; 819 if (intr->dst_apic_int == 0) 820 pin = APIC_LVT_LINT0; 821 else 822 pin = APIC_LVT_LINT1; 823 switch (intr->int_type) { 824 case INTENTRY_TYPE_INT: 825 #if 1 826 printf( 827 "MPTable: Ignoring vectored local interrupt for LINTIN%d vector %d\n", 828 intr->dst_apic_int, intr->src_bus_irq); 829 return; 830 #else 831 lapic_set_lvt_mode(apic_id, pin, APIC_LVT_DM_FIXED); 832 break; 833 #endif 834 case INTENTRY_TYPE_NMI: 835 lapic_set_lvt_mode(apic_id, pin, APIC_LVT_DM_NMI); 836 break; 837 case INTENTRY_TYPE_SMI: 838 lapic_set_lvt_mode(apic_id, pin, APIC_LVT_DM_SMI); 839 break; 840 case INTENTRY_TYPE_EXTINT: 841 lapic_set_lvt_mode(apic_id, pin, APIC_LVT_DM_EXTINT); 842 break; 843 default: 844 panic("%s: invalid interrupt entry type %d\n", __func__, 845 intr->int_type); 846 } 847 if ((intr->int_flags & INTENTRY_FLAGS_TRIGGER) != 848 INTENTRY_FLAGS_TRIGGER_CONFORM) 849 lapic_set_lvt_triggermode(apic_id, pin, 850 intentry_trigger(intr)); 851 if ((intr->int_flags & INTENTRY_FLAGS_POLARITY) != 852 INTENTRY_FLAGS_POLARITY_CONFORM) 853 lapic_set_lvt_polarity(apic_id, pin, intentry_polarity(intr)); 854 } 855 856 /* 857 * Parse interrupt entries. 858 */ 859 static void 860 mptable_parse_ints_handler(u_char *entry, void *arg __unused) 861 { 862 int_entry_ptr intr; 863 864 intr = (int_entry_ptr)entry; 865 switch (*entry) { 866 case MPCT_ENTRY_INT: 867 mptable_parse_io_int(intr); 868 break; 869 case MPCT_ENTRY_LOCAL_INT: 870 mptable_parse_local_int(intr); 871 break; 872 } 873 } 874 875 /* 876 * Configure interrupt pins for a default configuration. For details see 877 * Table 5-2 in Section 5 of the MP Table specification. 878 */ 879 static void 880 mptable_parse_default_config_ints(void) 881 { 882 struct INTENTRY entry; 883 int pin; 884 885 /* 886 * All default configs route IRQs from bus 0 to the first 16 pins 887 * of the first I/O APIC with an APIC ID of 2. 888 */ 889 entry.type = MPCT_ENTRY_INT; 890 entry.int_flags = INTENTRY_FLAGS_POLARITY_CONFORM | 891 INTENTRY_FLAGS_TRIGGER_CONFORM; 892 entry.src_bus_id = 0; 893 entry.dst_apic_id = 2; 894 895 /* Run through all 16 pins. */ 896 for (pin = 0; pin < 16; pin++) { 897 entry.dst_apic_int = pin; 898 switch (pin) { 899 case 0: 900 /* Pin 0 is an ExtINT pin. */ 901 entry.int_type = INTENTRY_TYPE_EXTINT; 902 break; 903 case 2: 904 /* IRQ 0 is routed to pin 2. */ 905 entry.int_type = INTENTRY_TYPE_INT; 906 entry.src_bus_irq = 0; 907 break; 908 default: 909 /* All other pins are identity mapped. */ 910 entry.int_type = INTENTRY_TYPE_INT; 911 entry.src_bus_irq = pin; 912 break; 913 } 914 mptable_parse_io_int(&entry); 915 } 916 917 /* Certain configs disable certain pins. */ 918 if (mpfps->config_type == 7) 919 ioapic_disable_pin(ioapics[2], 0); 920 if (mpfps->config_type == 2) { 921 ioapic_disable_pin(ioapics[2], 2); 922 ioapic_disable_pin(ioapics[2], 13); 923 } 924 } 925 926 /* 927 * Configure the interrupt pins 928 */ 929 static void 930 mptable_parse_ints(void) 931 { 932 933 /* Is this a pre-defined config? */ 934 if (mpfps->config_type != 0) { 935 /* Configure LINT pins. */ 936 lapic_set_lvt_mode(APIC_ID_ALL, APIC_LVT_LINT0, 937 APIC_LVT_DM_EXTINT); 938 lapic_set_lvt_mode(APIC_ID_ALL, APIC_LVT_LINT1, APIC_LVT_DM_NMI); 939 940 /* Configure I/O APIC pins. */ 941 mptable_parse_default_config_ints(); 942 } else 943 mptable_walk_table(mptable_parse_ints_handler, NULL); 944 } 945 946 #ifdef MPTABLE_FORCE_HTT 947 /* 948 * Perform a hyperthreading "fix-up" to enumerate any logical CPU's 949 * that aren't already listed in the table. 950 * 951 * XXX: We assume that all of the physical CPUs in the 952 * system have the same number of logical CPUs. 953 * 954 * XXX: We assume that APIC ID's are allocated such that 955 * the APIC ID's for a physical processor are aligned 956 * with the number of logical CPU's in the processor. 957 */ 958 static void 959 mptable_hyperthread_fixup(u_int id_mask) 960 { 961 u_int i, id, logical_cpus; 962 963 /* Nothing to do if there is no HTT support. */ 964 if ((cpu_feature & CPUID_HTT) == 0) 965 return; 966 logical_cpus = (cpu_procinfo & CPUID_HTT_CORES) >> 16; 967 if (logical_cpus <= 1) 968 return; 969 970 /* 971 * For each APIC ID of a CPU that is set in the mask, 972 * scan the other candidate APIC ID's for this 973 * physical processor. If any of those ID's are 974 * already in the table, then kill the fixup. 975 */ 976 for (id = 0; id <= MAX_LAPIC_ID; id++) { 977 if ((id_mask & 1 << id) == 0) 978 continue; 979 /* First, make sure we are on a logical_cpus boundary. */ 980 if (id % logical_cpus != 0) 981 return; 982 for (i = id + 1; i < id + logical_cpus; i++) 983 if ((id_mask & 1 << i) != 0) 984 return; 985 } 986 987 /* 988 * Ok, the ID's checked out, so perform the fixup by 989 * adding the logical CPUs. 990 */ 991 while ((id = ffs(id_mask)) != 0) { 992 id--; 993 for (i = id + 1; i < id + logical_cpus; i++) { 994 if (bootverbose) 995 printf( 996 "MPTable: Adding logical CPU %d from main CPU %d\n", 997 i, id); 998 lapic_create(i, 0); 999 } 1000 id_mask &= ~(1 << id); 1001 } 1002 } 1003 #endif /* MPTABLE_FORCE_HTT */ 1004 1005 /* 1006 * Support code for routing PCI interrupts using the MP Table. 1007 */ 1008 static void 1009 mptable_pci_setup(void) 1010 { 1011 int i; 1012 1013 /* 1014 * Find the first pci bus and call it 0. Panic if pci0 is not 1015 * bus zero and there are multiple PCI buses. 1016 */ 1017 for (i = 0; i <= mptable_maxbusid; i++) 1018 if (busses[i].bus_type == PCI) { 1019 if (pci0 == -1) 1020 pci0 = i; 1021 else if (pci0 != 0) 1022 panic( 1023 "MPTable contains multiple PCI buses but no PCI bus 0"); 1024 } 1025 } 1026 1027 static void 1028 mptable_pci_probe_table_handler(u_char *entry, void *arg) 1029 { 1030 struct pci_probe_table_args *args; 1031 int_entry_ptr intr; 1032 1033 if (*entry != MPCT_ENTRY_INT) 1034 return; 1035 intr = (int_entry_ptr)entry; 1036 args = (struct pci_probe_table_args *)arg; 1037 KASSERT(args->bus <= mptable_maxbusid, 1038 ("bus %d is too big", args->bus)); 1039 KASSERT(busses[args->bus].bus_type == PCI, ("probing for non-PCI bus")); 1040 if (intr->src_bus_id == args->bus) 1041 args->found = 1; 1042 } 1043 1044 int 1045 mptable_pci_probe_table(int bus) 1046 { 1047 struct pci_probe_table_args args; 1048 1049 if (bus < 0) 1050 return (EINVAL); 1051 if (mpct == NULL || pci0 == -1 || pci0 + bus > mptable_maxbusid) 1052 return (ENXIO); 1053 if (busses[pci0 + bus].bus_type != PCI) 1054 return (ENXIO); 1055 args.bus = pci0 + bus; 1056 args.found = 0; 1057 mptable_walk_table(mptable_pci_probe_table_handler, &args); 1058 if (args.found == 0) 1059 return (ENXIO); 1060 return (0); 1061 } 1062 1063 static void 1064 mptable_pci_route_interrupt_handler(u_char *entry, void *arg) 1065 { 1066 struct pci_route_interrupt_args *args; 1067 int_entry_ptr intr; 1068 int vector; 1069 1070 if (*entry != MPCT_ENTRY_INT) 1071 return; 1072 intr = (int_entry_ptr)entry; 1073 args = (struct pci_route_interrupt_args *)arg; 1074 if (intr->src_bus_id != args->bus || intr->src_bus_irq != args->irq) 1075 return; 1076 1077 /* Make sure the APIC maps to a known APIC. */ 1078 KASSERT(ioapics[intr->dst_apic_id] != NULL, 1079 ("No I/O APIC %d to route interrupt to", intr->dst_apic_id)); 1080 1081 /* 1082 * Look up the vector for this APIC / pin combination. If we 1083 * have previously matched an entry for this PCI IRQ but it 1084 * has the same vector as this entry, just return. Otherwise, 1085 * we use the vector for this APIC / pin combination. 1086 */ 1087 vector = ioapic_get_vector(ioapics[intr->dst_apic_id], 1088 intr->dst_apic_int); 1089 if (args->vector == vector) 1090 return; 1091 KASSERT(args->vector == -1, 1092 ("Multiple IRQs for PCI interrupt %d.%d.INT%c: %d and %d\n", 1093 args->bus, args->irq >> 2, 'A' + (args->irq & 0x3), args->vector, 1094 vector)); 1095 args->vector = vector; 1096 } 1097 1098 int 1099 mptable_pci_route_interrupt(device_t pcib, device_t dev, int pin) 1100 { 1101 struct pci_route_interrupt_args args; 1102 int slot; 1103 1104 /* Like ACPI, pin numbers are 0-3, not 1-4. */ 1105 pin--; 1106 KASSERT(pci0 != -1, ("do not know how to route PCI interrupts")); 1107 args.bus = pci_get_bus(dev) + pci0; 1108 slot = pci_get_slot(dev); 1109 1110 /* 1111 * PCI interrupt entries in the MP Table encode both the slot and 1112 * pin into the IRQ with the pin being the two least significant 1113 * bits, the slot being the next five bits, and the most significant 1114 * bit being reserved. 1115 */ 1116 args.irq = slot << 2 | pin; 1117 args.vector = -1; 1118 mptable_walk_table(mptable_pci_route_interrupt_handler, &args); 1119 if (args.vector < 0) { 1120 device_printf(pcib, "unable to route slot %d INT%c\n", slot, 1121 'A' + pin); 1122 return (PCI_INVALID_IRQ); 1123 } 1124 if (bootverbose) 1125 device_printf(pcib, "slot %d INT%c routed to irq %d\n", slot, 1126 'A' + pin, args.vector); 1127 return (args.vector); 1128 } 1129 1130 #ifdef NEW_PCIB 1131 struct host_res_args { 1132 struct mptable_hostb_softc *sc; 1133 device_t dev; 1134 u_char bus; 1135 }; 1136 1137 /* 1138 * Initialize a Host-PCI bridge so it can restrict resource allocation 1139 * requests to the resources it actually decodes according to MP 1140 * config table extended entries. 1141 */ 1142 static void 1143 mptable_host_res_handler(ext_entry_ptr entry, void *arg) 1144 { 1145 struct host_res_args *args; 1146 cbasm_entry_ptr cbasm; 1147 sas_entry_ptr sas; 1148 const char *name; 1149 uint64_t start, end; 1150 int error, *flagp, flags, type; 1151 1152 args = arg; 1153 switch (entry->type) { 1154 case MPCT_EXTENTRY_SAS: 1155 sas = (sas_entry_ptr)entry; 1156 if (sas->bus_id != args->bus) 1157 break; 1158 switch (sas->address_type) { 1159 case SASENTRY_TYPE_IO: 1160 type = SYS_RES_IOPORT; 1161 flags = 0; 1162 break; 1163 case SASENTRY_TYPE_MEMORY: 1164 type = SYS_RES_MEMORY; 1165 flags = 0; 1166 break; 1167 case SASENTRY_TYPE_PREFETCH: 1168 type = SYS_RES_MEMORY; 1169 flags = RF_PREFETCHABLE; 1170 break; 1171 default: 1172 printf( 1173 "MPTable: Unknown systems address space type for bus %u: %d\n", 1174 sas->bus_id, sas->address_type); 1175 return; 1176 } 1177 start = sas->address_base; 1178 end = sas->address_base + sas->address_length - 1; 1179 #ifdef __i386__ 1180 if (start > ULONG_MAX) { 1181 device_printf(args->dev, 1182 "Ignoring %d range above 4GB (%#jx-%#jx)\n", 1183 type, (uintmax_t)start, (uintmax_t)end); 1184 break; 1185 } 1186 if (end > ULONG_MAX) { 1187 device_printf(args->dev, 1188 "Truncating end of %d range above 4GB (%#jx-%#jx)\n", 1189 type, (uintmax_t)start, (uintmax_t)end); 1190 end = ULONG_MAX; 1191 } 1192 #endif 1193 error = pcib_host_res_decodes(&args->sc->sc_host_res, type, 1194 start, end, flags); 1195 if (error) 1196 panic("Failed to manage %d range (%#jx-%#jx): %d", 1197 type, (uintmax_t)start, (uintmax_t)end, error); 1198 break; 1199 case MPCT_EXTENTRY_CBASM: 1200 cbasm = (cbasm_entry_ptr)entry; 1201 if (cbasm->bus_id != args->bus) 1202 break; 1203 switch (cbasm->predefined_range) { 1204 case CBASMENTRY_RANGE_ISA_IO: 1205 flagp = &args->sc->sc_decodes_isa_io; 1206 name = "ISA I/O"; 1207 break; 1208 case CBASMENTRY_RANGE_VGA_IO: 1209 flagp = &args->sc->sc_decodes_vga_io; 1210 name = "VGA I/O"; 1211 break; 1212 default: 1213 printf( 1214 "MPTable: Unknown compatiblity address space range for bus %u: %d\n", 1215 cbasm->bus_id, cbasm->predefined_range); 1216 return; 1217 } 1218 if (*flagp != 0) 1219 printf( 1220 "MPTable: Duplicate compatibility %s range for bus %u\n", 1221 name, cbasm->bus_id); 1222 switch (cbasm->address_mod) { 1223 case CBASMENTRY_ADDRESS_MOD_ADD: 1224 *flagp = 1; 1225 if (bootverbose) 1226 device_printf(args->dev, "decoding %s ports\n", 1227 name); 1228 break; 1229 case CBASMENTRY_ADDRESS_MOD_SUBTRACT: 1230 *flagp = -1; 1231 if (bootverbose) 1232 device_printf(args->dev, 1233 "not decoding %s ports\n", name); 1234 break; 1235 default: 1236 printf( 1237 "MPTable: Unknown compatibility address space modifier: %u\n", 1238 cbasm->address_mod); 1239 break; 1240 } 1241 break; 1242 } 1243 } 1244 1245 void 1246 mptable_pci_host_res_init(device_t pcib) 1247 { 1248 struct host_res_args args; 1249 1250 KASSERT(pci0 != -1, ("do not know how to map PCI bus IDs")); 1251 args.bus = pci_get_bus(pcib) + pci0; 1252 args.dev = pcib; 1253 args.sc = device_get_softc(pcib); 1254 if (pcib_host_res_init(pcib, &args.sc->sc_host_res) != 0) 1255 panic("failed to init hostb resources"); 1256 mptable_walk_extended_table(mptable_host_res_handler, &args); 1257 } 1258 #endif 1259