1 2 /* 3 * Copyright (c) 2010-2011 Adrian Chadd, Xenion Pty Ltd. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24 * SUCH DAMAGE. 25 */ 26 27 #include <stdio.h> 28 #include <stdlib.h> 29 #include <unistd.h> 30 #include <string.h> 31 #include <sys/types.h> 32 #include <err.h> 33 34 struct ath_hal; 35 36 #include "ar9300/ar9300eep.h" 37 38 static const char * 39 eeprom_9300_ctl_idx_to_mode(uint8_t idx) 40 { 41 switch (idx & 0xf) { 42 /* 2G CTLs */ 43 case 1: return "CCK"; 44 case 2: return "OFDM"; 45 case 5: return "HT20"; 46 case 7: return "HT40"; 47 /* 5G CTLs */ 48 case 0: return "OFDM"; 49 case 6: return "HT20"; 50 case 8: return "HT40"; 51 default: return ""; 52 } 53 } 54 55 static const char * 56 eeprom_9300_ctl_idx_to_regdomain(uint8_t idx) 57 { 58 switch (idx & 0xf0) { 59 case 0x10: return "FCC"; 60 case 0x30: return "ETSI"; 61 case 0x40: return "JP"; 62 default: return ""; 63 } 64 } 65 66 static void 67 eeprom_9300_hdr_print(const uint16_t *buf) 68 { 69 const ar9300_eeprom_t *ee = (ar9300_eeprom_t *) buf; 70 71 printf("| Version: %d, Template: %d, MAC: %02x:%02x:%02x:%02x:%02x:%02x |\n", 72 ee->eeprom_version, 73 ee->template_version, 74 ee->mac_addr[0], 75 ee->mac_addr[1], 76 ee->mac_addr[2], 77 ee->mac_addr[3], 78 ee->mac_addr[4], 79 ee->mac_addr[5]); 80 } 81 82 static void 83 eeprom_9300_base_print(const uint16_t *buf) 84 { 85 const ar9300_eeprom_t *ee = (ar9300_eeprom_t *) buf; 86 const OSPREY_BASE_EEP_HEADER *ee_base = &ee->base_eep_header; 87 88 printf("| RegDomain: 0x%02x 0x%02x TxRxMask: 0x%02x OpFlags: 0x%02x OpMisc: 0x%02x |\n", 89 ee_base->reg_dmn[0], 90 ee_base->reg_dmn[1], 91 ee_base->txrx_mask, 92 ee_base->op_cap_flags.op_flags, 93 ee_base->op_cap_flags.eepMisc); 94 95 printf("| RfSilent: 0x%02x BtOptions: 0x%02x DeviceCap: 0x%02x DeviceType: 0x%02x |\n", 96 ee_base->rf_silent, 97 ee_base->blue_tooth_options, 98 ee_base->device_cap, 99 ee_base->device_type); 100 101 printf("| pwrTableOffset: %d dB, TuningCaps=0x%02x 0x%02x feature_enable: 0x%02x MiscConfig: 0x%02x |\n", 102 ee_base->pwrTableOffset, 103 ee_base->params_for_tuning_caps[0], 104 ee_base->params_for_tuning_caps[1], 105 ee_base->feature_enable, 106 ee_base->misc_configuration); 107 108 printf("| EepromWriteGpio: %d, WlanDisableGpio: %d, WlanLedGpio: %d RxBandSelectGpio: %d |\n", 109 ee_base->eeprom_write_enable_gpio, 110 ee_base->wlan_disable_gpio, 111 ee_base->wlan_led_gpio, 112 ee_base->rx_band_select_gpio); 113 114 printf("| TxRxGain: %d, SwReg: %d |\n", 115 ee_base->txrxgain, 116 ee_base->swreg); 117 } 118 119 static void 120 eeprom_9300_modal_print(const OSPREY_MODAL_EEP_HEADER *m) 121 { 122 int i; 123 124 printf("| AntCtrl: 0x%08x AntCtrl2: 0x%08x |\n", 125 m->ant_ctrl_common, 126 m->ant_ctrl_common2); 127 128 for (i = 0; i < OSPREY_MAX_CHAINS; i++) { 129 printf("| Ch %d: AntCtrl: 0x%08x Atten1: %d, atten1_margin: %d, NfThresh: %d |\n", 130 i, 131 m->ant_ctrl_chain[i], 132 m->xatten1_db[i], 133 m->xatten1_margin[i], 134 m->noise_floor_thresh_ch[i]); 135 } 136 137 printf("| Spur: "); 138 for (i = 0; i < OSPREY_EEPROM_MODAL_SPURS; i++) { 139 printf("(%d: %d) ", i, m->spur_chans[i]); 140 } 141 printf("|\n"); 142 143 printf("| TempSlope: %d, VoltSlope: %d, QuickDrop: %d, XpaBiasLvl %d |\n", 144 m->temp_slope, 145 m->voltSlope, 146 m->quick_drop, 147 m->xpa_bias_lvl); 148 149 printf("| txFrameToDataStart: %d, TxFrameToPaOn: %d, TxEndToXpaOff: %d, TxEndToRxOn: %d, TxFrameToXpaOn: %d |\n", 150 m->tx_frame_to_data_start, 151 m->tx_frame_to_pa_on, 152 m->tx_end_to_xpa_off, 153 m->txEndToRxOn, 154 m->tx_frame_to_xpa_on); 155 156 printf("| txClip: %d, AntGain: %d, SwitchSettling: %d, adcDesiredSize: %d |\n", 157 m->txClip, 158 m->antenna_gain, 159 m->switchSettling, 160 m->adcDesiredSize); 161 162 printf("| Thresh62: %d, PaprdMaskHt20: 0x%08x, PaPrdMaskHt40: 0x%08x |\n", 163 m->thresh62, 164 m->paprd_rate_mask_ht20, 165 m->paprd_rate_mask_ht40); 166 167 printf("| SwitchComSpdt: %02x, XlnaBiasStrength: %d, RfGainCap: %d, TxGainCap: %x\n", 168 m->switchcomspdt, 169 m->xLNA_bias_strength, 170 m->rf_gain_cap, 171 m->tx_gain_cap); 172 173 #if 0 174 u_int8_t reserved[MAX_MODAL_RESERVED]; 175 u_int16_t switchcomspdt; 176 u_int8_t xLNA_bias_strength; // bit: 0,1:chain0, 2,3:chain1, 4,5:chain2 177 u_int8_t rf_gain_cap; 178 u_int8_t tx_gain_cap; // bit0:4 txgain cap, txgain index for max_txgain + 20 (10dBm higher than max txgain) 179 u_int8_t futureModal[MAX_MODAL_FUTURE]; 180 // last 12 bytes stolen and moved to newly created base extension structure 181 #endif 182 } 183 184 static void 185 eeprom_9300_print_2g_target_cck(const ar9300_eeprom_t *ee) 186 { 187 int i; 188 189 for (i = 0; i < OSPREY_NUM_2G_CCK_TARGET_POWERS; i++) { 190 printf("| Freq %u CCK: pow2x 1/5L %u 5S %u 11L %u 11S %u\n", 191 FBIN2FREQ(ee->cal_target_freqbin_cck[i], 1), 192 ee->cal_target_power_cck[i].t_pow2x[LEGACY_TARGET_RATE_1L_5L], 193 ee->cal_target_power_cck[i].t_pow2x[LEGACY_TARGET_RATE_5S], 194 ee->cal_target_power_cck[i].t_pow2x[LEGACY_TARGET_RATE_11L], 195 ee->cal_target_power_cck[i].t_pow2x[LEGACY_TARGET_RATE_11S]); 196 } 197 } 198 199 static void 200 eeprom_9300_print_2g_target_ofdm(const ar9300_eeprom_t *ee) 201 { 202 int i; 203 204 for (i = 0; i < OSPREY_NUM_2G_20_TARGET_POWERS; i++) { 205 printf("| Freq %u OFDM: pow2x 6/12/18/24M %u 36M %u 48M %u 54M %u\n", 206 FBIN2FREQ(ee->cal_target_freqbin_2g[i], 1), 207 ee->cal_target_power_2g[i].t_pow2x[LEGACY_TARGET_RATE_6_24], 208 ee->cal_target_power_2g[i].t_pow2x[LEGACY_TARGET_RATE_36], 209 ee->cal_target_power_2g[i].t_pow2x[LEGACY_TARGET_RATE_48], 210 ee->cal_target_power_2g[i].t_pow2x[LEGACY_TARGET_RATE_54]); 211 } 212 } 213 214 static void 215 eeprom_9300_print_2g_target_ht20(const ar9300_eeprom_t *ee) 216 { 217 int i; 218 219 for (i = 0; i < OSPREY_NUM_2G_20_TARGET_POWERS; i++) { 220 printf("| Freq %u HT20 MCS0-7 pow2x %u %u %u %u %u %u %u %u\n", 221 FBIN2FREQ(ee->cal_target_freqbin_2g_ht20[i], 1), 222 ee->cal_target_power_2g_ht20[i].t_pow2x[HT_TARGET_RATE_0_8_16], 223 ee->cal_target_power_2g_ht20[i].t_pow2x[HT_TARGET_RATE_1_3_9_11_17_19], 224 ee->cal_target_power_2g_ht20[i].t_pow2x[HT_TARGET_RATE_1_3_9_11_17_19], 225 ee->cal_target_power_2g_ht20[i].t_pow2x[HT_TARGET_RATE_1_3_9_11_17_19], 226 ee->cal_target_power_2g_ht20[i].t_pow2x[HT_TARGET_RATE_4], 227 ee->cal_target_power_2g_ht20[i].t_pow2x[HT_TARGET_RATE_5], 228 ee->cal_target_power_2g_ht20[i].t_pow2x[HT_TARGET_RATE_6], 229 ee->cal_target_power_2g_ht20[i].t_pow2x[HT_TARGET_RATE_7]); 230 printf("| Freq %u HT20 MCS8-15 pow2x %u %u %u %u %u %u %u %u\n", 231 FBIN2FREQ(ee->cal_target_freqbin_2g_ht20[i], 1), 232 ee->cal_target_power_2g_ht20[i].t_pow2x[HT_TARGET_RATE_0_8_16], 233 ee->cal_target_power_2g_ht20[i].t_pow2x[HT_TARGET_RATE_1_3_9_11_17_19], 234 ee->cal_target_power_2g_ht20[i].t_pow2x[HT_TARGET_RATE_1_3_9_11_17_19], 235 ee->cal_target_power_2g_ht20[i].t_pow2x[HT_TARGET_RATE_1_3_9_11_17_19], 236 ee->cal_target_power_2g_ht20[i].t_pow2x[HT_TARGET_RATE_12], 237 ee->cal_target_power_2g_ht20[i].t_pow2x[HT_TARGET_RATE_13], 238 ee->cal_target_power_2g_ht20[i].t_pow2x[HT_TARGET_RATE_14], 239 ee->cal_target_power_2g_ht20[i].t_pow2x[HT_TARGET_RATE_15]); 240 printf("| Freq %u HT20 MCS16-23 pow2x %u %u %u %u %u %u %u %u\n", 241 FBIN2FREQ(ee->cal_target_freqbin_2g_ht20[i], 1), 242 ee->cal_target_power_2g_ht20[i].t_pow2x[HT_TARGET_RATE_0_8_16], 243 ee->cal_target_power_2g_ht20[i].t_pow2x[HT_TARGET_RATE_1_3_9_11_17_19], 244 ee->cal_target_power_2g_ht20[i].t_pow2x[HT_TARGET_RATE_1_3_9_11_17_19], 245 ee->cal_target_power_2g_ht20[i].t_pow2x[HT_TARGET_RATE_1_3_9_11_17_19], 246 ee->cal_target_power_2g_ht20[i].t_pow2x[HT_TARGET_RATE_20], 247 ee->cal_target_power_2g_ht20[i].t_pow2x[HT_TARGET_RATE_21], 248 ee->cal_target_power_2g_ht20[i].t_pow2x[HT_TARGET_RATE_22], 249 ee->cal_target_power_2g_ht20[i].t_pow2x[HT_TARGET_RATE_23]); 250 } 251 } 252 253 static void 254 eeprom_9300_print_2g_target_ht40(const ar9300_eeprom_t *ee) 255 { 256 int i; 257 258 for (i = 0; i < OSPREY_NUM_2G_40_TARGET_POWERS; i++) { 259 printf("| Freq %u HT40 MCS0-7 pow2x %u %u %u %u %u %u %u %u\n", 260 FBIN2FREQ(ee->cal_target_freqbin_2g_ht40[i], 1), 261 ee->cal_target_power_2g_ht40[i].t_pow2x[HT_TARGET_RATE_0_8_16], 262 ee->cal_target_power_2g_ht40[i].t_pow2x[HT_TARGET_RATE_1_3_9_11_17_19], 263 ee->cal_target_power_2g_ht40[i].t_pow2x[HT_TARGET_RATE_1_3_9_11_17_19], 264 ee->cal_target_power_2g_ht40[i].t_pow2x[HT_TARGET_RATE_1_3_9_11_17_19], 265 ee->cal_target_power_2g_ht40[i].t_pow2x[HT_TARGET_RATE_4], 266 ee->cal_target_power_2g_ht40[i].t_pow2x[HT_TARGET_RATE_5], 267 ee->cal_target_power_2g_ht40[i].t_pow2x[HT_TARGET_RATE_6], 268 ee->cal_target_power_2g_ht40[i].t_pow2x[HT_TARGET_RATE_7]); 269 printf("| Freq %u HT40 MCS8-15 pow2x %u %u %u %u %u %u %u %u\n", 270 FBIN2FREQ(ee->cal_target_freqbin_2g_ht40[i], 1), 271 ee->cal_target_power_2g_ht40[i].t_pow2x[HT_TARGET_RATE_0_8_16], 272 ee->cal_target_power_2g_ht40[i].t_pow2x[HT_TARGET_RATE_1_3_9_11_17_19], 273 ee->cal_target_power_2g_ht40[i].t_pow2x[HT_TARGET_RATE_1_3_9_11_17_19], 274 ee->cal_target_power_2g_ht40[i].t_pow2x[HT_TARGET_RATE_1_3_9_11_17_19], 275 ee->cal_target_power_2g_ht40[i].t_pow2x[HT_TARGET_RATE_12], 276 ee->cal_target_power_2g_ht40[i].t_pow2x[HT_TARGET_RATE_13], 277 ee->cal_target_power_2g_ht40[i].t_pow2x[HT_TARGET_RATE_14], 278 ee->cal_target_power_2g_ht40[i].t_pow2x[HT_TARGET_RATE_15]); 279 printf("| Freq %u HT40 MCS16-23 pow2x %u %u %u %u %u %u %u %u\n", 280 FBIN2FREQ(ee->cal_target_freqbin_2g_ht40[i], 1), 281 ee->cal_target_power_2g_ht40[i].t_pow2x[HT_TARGET_RATE_0_8_16], 282 ee->cal_target_power_2g_ht40[i].t_pow2x[HT_TARGET_RATE_1_3_9_11_17_19], 283 ee->cal_target_power_2g_ht40[i].t_pow2x[HT_TARGET_RATE_1_3_9_11_17_19], 284 ee->cal_target_power_2g_ht40[i].t_pow2x[HT_TARGET_RATE_1_3_9_11_17_19], 285 ee->cal_target_power_2g_ht40[i].t_pow2x[HT_TARGET_RATE_20], 286 ee->cal_target_power_2g_ht40[i].t_pow2x[HT_TARGET_RATE_21], 287 ee->cal_target_power_2g_ht40[i].t_pow2x[HT_TARGET_RATE_22], 288 ee->cal_target_power_2g_ht40[i].t_pow2x[HT_TARGET_RATE_23]); 289 } 290 } 291 292 static void 293 eeprom_9300_print_2g_ctls(const ar9300_eeprom_t *ee) 294 { 295 int i, j; 296 297 for (i = 0; i < OSPREY_NUM_CTLS_2G; i++) { 298 printf("| CTL index 0x%.02x (%s %s)\n", 299 ee->ctl_index_2g[i], 300 eeprom_9300_ctl_idx_to_regdomain(ee->ctl_index_2g[i]), 301 eeprom_9300_ctl_idx_to_mode(ee->ctl_index_2g[i])); 302 for (j = 0; j < OSPREY_NUM_BAND_EDGES_2G; j++) { 303 printf("| Freq %u pow2x %u flags 0x%x\n", 304 FBIN2FREQ(ee->ctl_freqbin_2G[i][j], 1), 305 ee->ctl_power_data_2g[i].ctl_edges[j].t_power, 306 ee->ctl_power_data_2g[i].ctl_edges[j].flag); 307 } 308 printf("\n"); 309 } 310 } 311 312 static void 313 eeprom_9300_print_5g_target_ofdm(const ar9300_eeprom_t *ee) 314 { 315 int i; 316 317 for (i = 0; i < OSPREY_NUM_5G_20_TARGET_POWERS; i++) { 318 printf("| Freq %u OFDM: pow2x 6/12/18/24M %u 36M %u 48M %u 54M %u\n", 319 FBIN2FREQ(ee->cal_target_freqbin_5g[i], 0), 320 ee->cal_target_power_5g[i].t_pow2x[LEGACY_TARGET_RATE_6_24], 321 ee->cal_target_power_5g[i].t_pow2x[LEGACY_TARGET_RATE_36], 322 ee->cal_target_power_5g[i].t_pow2x[LEGACY_TARGET_RATE_48], 323 ee->cal_target_power_5g[i].t_pow2x[LEGACY_TARGET_RATE_54]); 324 } 325 } 326 327 static void 328 eeprom_9300_print_5g_target_ht20(const ar9300_eeprom_t *ee) 329 { 330 int i; 331 332 for (i = 0; i < OSPREY_NUM_5G_20_TARGET_POWERS; i++) { 333 printf("| Freq %u HT20 MCS0-7 pow2x %u %u %u %u %u %u %u %u\n", 334 FBIN2FREQ(ee->cal_target_freqbin_5g_ht20[i], 0), 335 ee->cal_target_power_5g_ht20[i].t_pow2x[HT_TARGET_RATE_0_8_16], 336 ee->cal_target_power_5g_ht20[i].t_pow2x[HT_TARGET_RATE_1_3_9_11_17_19], 337 ee->cal_target_power_5g_ht20[i].t_pow2x[HT_TARGET_RATE_1_3_9_11_17_19], 338 ee->cal_target_power_5g_ht20[i].t_pow2x[HT_TARGET_RATE_1_3_9_11_17_19], 339 ee->cal_target_power_5g_ht20[i].t_pow2x[HT_TARGET_RATE_4], 340 ee->cal_target_power_5g_ht20[i].t_pow2x[HT_TARGET_RATE_5], 341 ee->cal_target_power_5g_ht20[i].t_pow2x[HT_TARGET_RATE_6], 342 ee->cal_target_power_5g_ht20[i].t_pow2x[HT_TARGET_RATE_7]); 343 printf("| Freq %u HT20 MCS8-15 pow2x %u %u %u %u %u %u %u %u\n", 344 FBIN2FREQ(ee->cal_target_freqbin_5g_ht20[i], 0), 345 ee->cal_target_power_5g_ht20[i].t_pow2x[HT_TARGET_RATE_0_8_16], 346 ee->cal_target_power_5g_ht20[i].t_pow2x[HT_TARGET_RATE_1_3_9_11_17_19], 347 ee->cal_target_power_5g_ht20[i].t_pow2x[HT_TARGET_RATE_1_3_9_11_17_19], 348 ee->cal_target_power_5g_ht20[i].t_pow2x[HT_TARGET_RATE_1_3_9_11_17_19], 349 ee->cal_target_power_5g_ht20[i].t_pow2x[HT_TARGET_RATE_12], 350 ee->cal_target_power_5g_ht20[i].t_pow2x[HT_TARGET_RATE_13], 351 ee->cal_target_power_5g_ht20[i].t_pow2x[HT_TARGET_RATE_14], 352 ee->cal_target_power_5g_ht20[i].t_pow2x[HT_TARGET_RATE_15]); 353 printf("| Freq %u HT20 MCS16-23 pow2x %u %u %u %u %u %u %u %u\n", 354 FBIN2FREQ(ee->cal_target_freqbin_5g_ht20[i], 0), 355 ee->cal_target_power_5g_ht20[i].t_pow2x[HT_TARGET_RATE_0_8_16], 356 ee->cal_target_power_5g_ht20[i].t_pow2x[HT_TARGET_RATE_1_3_9_11_17_19], 357 ee->cal_target_power_5g_ht20[i].t_pow2x[HT_TARGET_RATE_1_3_9_11_17_19], 358 ee->cal_target_power_5g_ht20[i].t_pow2x[HT_TARGET_RATE_1_3_9_11_17_19], 359 ee->cal_target_power_5g_ht20[i].t_pow2x[HT_TARGET_RATE_20], 360 ee->cal_target_power_5g_ht20[i].t_pow2x[HT_TARGET_RATE_21], 361 ee->cal_target_power_5g_ht20[i].t_pow2x[HT_TARGET_RATE_22], 362 ee->cal_target_power_5g_ht20[i].t_pow2x[HT_TARGET_RATE_23]); 363 } 364 } 365 366 static void 367 eeprom_9300_print_5g_target_ht40(const ar9300_eeprom_t *ee) 368 { 369 int i; 370 371 for (i = 0; i < OSPREY_NUM_5G_40_TARGET_POWERS; i++) { 372 printf("| Freq %u HT40 MCS0-7 pow2x %u %u %u %u %u %u %u %u\n", 373 FBIN2FREQ(ee->cal_target_freqbin_5g_ht40[i], 0), 374 ee->cal_target_power_5g_ht40[i].t_pow2x[HT_TARGET_RATE_0_8_16], 375 ee->cal_target_power_5g_ht40[i].t_pow2x[HT_TARGET_RATE_1_3_9_11_17_19], 376 ee->cal_target_power_5g_ht40[i].t_pow2x[HT_TARGET_RATE_1_3_9_11_17_19], 377 ee->cal_target_power_5g_ht40[i].t_pow2x[HT_TARGET_RATE_1_3_9_11_17_19], 378 ee->cal_target_power_5g_ht40[i].t_pow2x[HT_TARGET_RATE_4], 379 ee->cal_target_power_5g_ht40[i].t_pow2x[HT_TARGET_RATE_5], 380 ee->cal_target_power_5g_ht40[i].t_pow2x[HT_TARGET_RATE_6], 381 ee->cal_target_power_5g_ht40[i].t_pow2x[HT_TARGET_RATE_7]); 382 printf("| Freq %u HT40 MCS8-15 pow2x %u %u %u %u %u %u %u %u\n", 383 FBIN2FREQ(ee->cal_target_freqbin_5g_ht40[i], 0), 384 ee->cal_target_power_5g_ht40[i].t_pow2x[HT_TARGET_RATE_0_8_16], 385 ee->cal_target_power_5g_ht40[i].t_pow2x[HT_TARGET_RATE_1_3_9_11_17_19], 386 ee->cal_target_power_5g_ht40[i].t_pow2x[HT_TARGET_RATE_1_3_9_11_17_19], 387 ee->cal_target_power_5g_ht40[i].t_pow2x[HT_TARGET_RATE_1_3_9_11_17_19], 388 ee->cal_target_power_5g_ht40[i].t_pow2x[HT_TARGET_RATE_12], 389 ee->cal_target_power_5g_ht40[i].t_pow2x[HT_TARGET_RATE_13], 390 ee->cal_target_power_5g_ht40[i].t_pow2x[HT_TARGET_RATE_14], 391 ee->cal_target_power_5g_ht40[i].t_pow2x[HT_TARGET_RATE_15]); 392 printf("| Freq %u HT40 MCS16-23 pow2x %u %u %u %u %u %u %u %u\n", 393 FBIN2FREQ(ee->cal_target_freqbin_5g_ht40[i], 0), 394 ee->cal_target_power_5g_ht40[i].t_pow2x[HT_TARGET_RATE_0_8_16], 395 ee->cal_target_power_5g_ht40[i].t_pow2x[HT_TARGET_RATE_1_3_9_11_17_19], 396 ee->cal_target_power_5g_ht40[i].t_pow2x[HT_TARGET_RATE_1_3_9_11_17_19], 397 ee->cal_target_power_5g_ht40[i].t_pow2x[HT_TARGET_RATE_1_3_9_11_17_19], 398 ee->cal_target_power_5g_ht40[i].t_pow2x[HT_TARGET_RATE_20], 399 ee->cal_target_power_5g_ht40[i].t_pow2x[HT_TARGET_RATE_21], 400 ee->cal_target_power_5g_ht40[i].t_pow2x[HT_TARGET_RATE_22], 401 ee->cal_target_power_5g_ht40[i].t_pow2x[HT_TARGET_RATE_23]); 402 } 403 } 404 405 static void 406 eeprom_9300_print_5g_ctls(const ar9300_eeprom_t *ee) 407 { 408 int i, j; 409 410 for (i = 0; i < OSPREY_NUM_CTLS_5G; i++) { 411 printf("| CTL index 0x%.02x (%s %s)\n", ee->ctl_index_5g[i], 412 eeprom_9300_ctl_idx_to_regdomain(ee->ctl_index_5g[i]), 413 eeprom_9300_ctl_idx_to_mode(ee->ctl_index_5g[i])); 414 for (j = 0; j < OSPREY_NUM_BAND_EDGES_5G; j++) { 415 printf("| Freq %u pow2x %u Flags 0x%x\n", 416 FBIN2FREQ(ee->ctl_freqbin_5G[i][j], 0), 417 ee->ctl_power_data_5g[i].ctl_edges[j].t_power, 418 ee->ctl_power_data_5g[i].ctl_edges[j].flag); 419 } 420 printf("\n"); 421 } 422 } 423 424 static void 425 load_eeprom_dump(const char *file, uint16_t *buf) 426 { 427 unsigned int r[8]; 428 FILE *fp; 429 char b[1024]; 430 int i; 431 432 fp = fopen(file, "r"); 433 if (!fp) 434 err(1, "fopen"); 435 436 while (!feof(fp)) { 437 if (fgets(b, 1024, fp) == NULL) 438 break; 439 if (feof(fp)) 440 break; 441 if (strlen(b) > 0) 442 b[strlen(b)-1] = '\0'; 443 if (strlen(b) == 0) 444 break; 445 sscanf(b, "%x: %x %x %x %x %x %x %x %x\n", 446 &i, &r[0], &r[1], &r[2], &r[3], &r[4], 447 &r[5], &r[6], &r[7]); 448 buf[i++] = r[0]; 449 buf[i++] = r[1]; 450 buf[i++] = r[2]; 451 buf[i++] = r[3]; 452 buf[i++] = r[4]; 453 buf[i++] = r[5]; 454 buf[i++] = r[6]; 455 buf[i++] = r[7]; 456 } 457 fclose(fp); 458 } 459 460 void 461 usage(char *argv[]) 462 { 463 printf("Usage: %s <eeprom dump file>\n", argv[0]); 464 printf("\n"); 465 printf(" The eeprom dump file is a text hexdump of an EEPROM.\n"); 466 printf(" The lines must be formatted as follows:\n"); 467 printf(" 0xAAAA: 0xDD 0xDD 0xDD 0xDD 0xDD 0xDD 0xDD 0xDD\n"); 468 printf(" where each line must have exactly eight data bytes.\n"); 469 exit(127); 470 } 471 472 int 473 main(int argc, char *argv[]) 474 { 475 uint16_t *eep = NULL; 476 const ar9300_eeprom_t *ee; 477 478 eep = calloc(4096, sizeof(int16_t)); 479 480 if (argc < 2) 481 usage(argv); 482 483 load_eeprom_dump(argv[1], eep); 484 ee = (ar9300_eeprom_t *) eep; 485 486 eeprom_9300_hdr_print(eep); 487 eeprom_9300_base_print(eep); 488 489 printf("\n2GHz modal:\n"); 490 eeprom_9300_modal_print(&ee->modal_header_2g); 491 // TODO: open-loop calibration 492 eeprom_9300_print_2g_target_cck(ee); 493 eeprom_9300_print_2g_target_ofdm(ee); 494 eeprom_9300_print_2g_target_ht20(ee); 495 eeprom_9300_print_2g_target_ht40(ee); 496 eeprom_9300_print_2g_ctls(ee); 497 498 printf("\n5GHz modal:\n"); 499 eeprom_9300_modal_print(&ee->modal_header_5g); 500 eeprom_9300_print_5g_target_ofdm(ee); 501 eeprom_9300_print_5g_target_ht20(ee); 502 eeprom_9300_print_5g_target_ht40(ee); 503 eeprom_9300_print_5g_ctls(ee); 504 505 free(eep); 506 exit(0); 507 } 508