1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause 3 * 4 * Copyright (c) 2012 NetApp, Inc. 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY NETAPP, INC ``AS IS'' AND 17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 19 * ARE DISCLAIMED. IN NO EVENT SHALL NETAPP, INC OR CONTRIBUTORS BE LIABLE 20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 */ 28 29 #include <sys/types.h> 30 #include <sys/errno.h> 31 #include <x86/mptable.h> 32 33 #include <stdio.h> 34 #include <string.h> 35 36 #include "acpi.h" 37 #include "debug.h" 38 #include "bhyverun.h" 39 #include "mptbl.h" 40 #include "pci_emul.h" 41 42 #define MPTABLE_BASE 0xF0000 43 44 /* floating pointer length + maximum length of configuration table */ 45 #define MPTABLE_MAX_LENGTH (65536 + 16) 46 47 #define LAPIC_PADDR 0xFEE00000 48 #define LAPIC_VERSION 16 49 50 #define IOAPIC_PADDR 0xFEC00000 51 #define IOAPIC_VERSION 0x11 52 53 #define MP_SPECREV 4 54 #define MPFP_SIG "_MP_" 55 56 /* Configuration header defines */ 57 #define MPCH_SIG "PCMP" 58 #define MPCH_OEMID "BHyVe " 59 #define MPCH_OEMID_LEN 8 60 #define MPCH_PRODID "Hypervisor " 61 #define MPCH_PRODID_LEN 12 62 63 /* Processor entry defines */ 64 #define MPEP_SIG_FAMILY 6 /* XXX bhyve should supply this */ 65 #define MPEP_SIG_MODEL 26 66 #define MPEP_SIG_STEPPING 5 67 #define MPEP_SIG \ 68 ((MPEP_SIG_FAMILY << 8) | \ 69 (MPEP_SIG_MODEL << 4) | \ 70 (MPEP_SIG_STEPPING)) 71 72 #define MPEP_FEATURES (0xBFEBFBFF) /* XXX Intel i7 */ 73 74 /* Number of local intr entries */ 75 #define MPEII_NUM_LOCAL_IRQ 2 76 77 /* Bus entry defines */ 78 #define MPE_NUM_BUSES 2 79 #define MPE_BUSNAME_LEN 6 80 #define MPE_BUSNAME_ISA "ISA " 81 #define MPE_BUSNAME_PCI "PCI " 82 83 static void *oem_tbl_start; 84 static int oem_tbl_size; 85 86 static uint8_t 87 mpt_compute_checksum(void *base, size_t len) 88 { 89 uint8_t *bytes; 90 uint8_t sum; 91 92 for(bytes = base, sum = 0; len > 0; len--) { 93 sum += *bytes++; 94 } 95 96 return (256 - sum); 97 } 98 99 static void 100 mpt_build_mpfp(mpfps_t mpfp, vm_paddr_t gpa) 101 { 102 103 memset(mpfp, 0, sizeof(*mpfp)); 104 memcpy(mpfp->signature, MPFP_SIG, 4); 105 mpfp->pap = gpa + sizeof(*mpfp); 106 mpfp->length = 1; 107 mpfp->spec_rev = MP_SPECREV; 108 mpfp->checksum = mpt_compute_checksum(mpfp, sizeof(*mpfp)); 109 } 110 111 static void 112 mpt_build_mpch(mpcth_t mpch) 113 { 114 115 memset(mpch, 0, sizeof(*mpch)); 116 memcpy(mpch->signature, MPCH_SIG, 4); 117 mpch->spec_rev = MP_SPECREV; 118 memcpy(mpch->oem_id, MPCH_OEMID, MPCH_OEMID_LEN); 119 memcpy(mpch->product_id, MPCH_PRODID, MPCH_PRODID_LEN); 120 mpch->apic_address = LAPIC_PADDR; 121 } 122 123 static void 124 mpt_build_proc_entries(proc_entry_ptr mpep, int ncpu) 125 { 126 int i; 127 128 for (i = 0; i < ncpu; i++) { 129 memset(mpep, 0, sizeof(*mpep)); 130 mpep->type = MPCT_ENTRY_PROCESSOR; 131 mpep->apic_id = i; // XXX 132 mpep->apic_version = LAPIC_VERSION; 133 mpep->cpu_flags = PROCENTRY_FLAG_EN; 134 if (i == 0) 135 mpep->cpu_flags |= PROCENTRY_FLAG_BP; 136 mpep->cpu_signature = MPEP_SIG; 137 mpep->feature_flags = MPEP_FEATURES; 138 mpep++; 139 } 140 } 141 142 static void 143 mpt_build_localint_entries(int_entry_ptr mpie) 144 { 145 146 /* Hardcode LINT0 as ExtINT on all CPUs. */ 147 memset(mpie, 0, sizeof(*mpie)); 148 mpie->type = MPCT_ENTRY_LOCAL_INT; 149 mpie->int_type = INTENTRY_TYPE_EXTINT; 150 mpie->int_flags = INTENTRY_FLAGS_POLARITY_CONFORM | 151 INTENTRY_FLAGS_TRIGGER_CONFORM; 152 mpie->dst_apic_id = 0xff; 153 mpie->dst_apic_int = 0; 154 mpie++; 155 156 /* Hardcode LINT1 as NMI on all CPUs. */ 157 memset(mpie, 0, sizeof(*mpie)); 158 mpie->type = MPCT_ENTRY_LOCAL_INT; 159 mpie->int_type = INTENTRY_TYPE_NMI; 160 mpie->int_flags = INTENTRY_FLAGS_POLARITY_CONFORM | 161 INTENTRY_FLAGS_TRIGGER_CONFORM; 162 mpie->dst_apic_id = 0xff; 163 mpie->dst_apic_int = 1; 164 } 165 166 static void 167 mpt_build_bus_entries(bus_entry_ptr mpeb) 168 { 169 170 memset(mpeb, 0, sizeof(*mpeb)); 171 mpeb->type = MPCT_ENTRY_BUS; 172 mpeb->bus_id = 0; 173 memcpy(mpeb->bus_type, MPE_BUSNAME_PCI, MPE_BUSNAME_LEN); 174 mpeb++; 175 176 memset(mpeb, 0, sizeof(*mpeb)); 177 mpeb->type = MPCT_ENTRY_BUS; 178 mpeb->bus_id = 1; 179 memcpy(mpeb->bus_type, MPE_BUSNAME_ISA, MPE_BUSNAME_LEN); 180 } 181 182 static void 183 mpt_build_ioapic_entries(io_apic_entry_ptr mpei, int id) 184 { 185 186 memset(mpei, 0, sizeof(*mpei)); 187 mpei->type = MPCT_ENTRY_IOAPIC; 188 mpei->apic_id = id; 189 mpei->apic_version = IOAPIC_VERSION; 190 mpei->apic_flags = IOAPICENTRY_FLAG_EN; 191 mpei->apic_address = IOAPIC_PADDR; 192 } 193 194 static int 195 mpt_count_ioint_entries(void) 196 { 197 int bus, count; 198 199 count = 0; 200 for (bus = 0; bus <= PCI_BUSMAX; bus++) 201 count += pci_count_lintr(bus); 202 203 /* 204 * Always include entries for the first 16 pins along with a entry 205 * for each active PCI INTx pin. 206 */ 207 return (16 + count); 208 } 209 210 static void 211 mpt_generate_pci_int(int bus, int slot, int pin, struct pci_irq *irq, 212 void *arg) 213 { 214 int_entry_ptr *mpiep, mpie; 215 216 mpiep = arg; 217 mpie = *mpiep; 218 memset(mpie, 0, sizeof(*mpie)); 219 220 /* 221 * This is always after another I/O interrupt entry, so cheat 222 * and fetch the I/O APIC ID from the prior entry. 223 */ 224 mpie->type = MPCT_ENTRY_INT; 225 mpie->int_type = INTENTRY_TYPE_INT; 226 mpie->src_bus_id = bus; 227 mpie->src_bus_irq = slot << 2 | (pin - 1); 228 mpie->dst_apic_id = mpie[-1].dst_apic_id; 229 mpie->dst_apic_int = irq->ioapic_irq; 230 231 *mpiep = mpie + 1; 232 } 233 234 static void 235 mpt_build_ioint_entries(int_entry_ptr mpie, int id) 236 { 237 int pin, bus; 238 239 /* 240 * The following config is taken from kernel mptable.c 241 * mptable_parse_default_config_ints(...), for now 242 * just use the default config, tweek later if needed. 243 */ 244 245 /* First, generate the first 16 pins. */ 246 for (pin = 0; pin < 16; pin++) { 247 memset(mpie, 0, sizeof(*mpie)); 248 mpie->type = MPCT_ENTRY_INT; 249 mpie->src_bus_id = 1; 250 mpie->dst_apic_id = id; 251 252 /* 253 * All default configs route IRQs from bus 0 to the first 16 254 * pins of the first I/O APIC with an APIC ID of 2. 255 */ 256 mpie->dst_apic_int = pin; 257 switch (pin) { 258 case 0: 259 /* Pin 0 is an ExtINT pin. */ 260 mpie->int_type = INTENTRY_TYPE_EXTINT; 261 break; 262 case 2: 263 /* IRQ 0 is routed to pin 2. */ 264 mpie->int_type = INTENTRY_TYPE_INT; 265 mpie->src_bus_irq = 0; 266 break; 267 case SCI_INT: 268 /* ACPI SCI is level triggered and active-lo. */ 269 mpie->int_flags = INTENTRY_FLAGS_POLARITY_ACTIVELO | 270 INTENTRY_FLAGS_TRIGGER_LEVEL; 271 mpie->int_type = INTENTRY_TYPE_INT; 272 mpie->src_bus_irq = SCI_INT; 273 break; 274 default: 275 /* All other pins are identity mapped. */ 276 mpie->int_type = INTENTRY_TYPE_INT; 277 mpie->src_bus_irq = pin; 278 break; 279 } 280 mpie++; 281 } 282 283 /* Next, generate entries for any PCI INTx interrupts. */ 284 for (bus = 0; bus <= PCI_BUSMAX; bus++) 285 pci_walk_lintr(bus, mpt_generate_pci_int, &mpie); 286 } 287 288 void 289 mptable_add_oemtbl(void *tbl, int tblsz) 290 { 291 292 oem_tbl_start = tbl; 293 oem_tbl_size = tblsz; 294 } 295 296 int 297 mptable_build(struct vmctx *ctx, int ncpu) 298 { 299 mpcth_t mpch; 300 bus_entry_ptr mpeb; 301 io_apic_entry_ptr mpei; 302 proc_entry_ptr mpep; 303 mpfps_t mpfp; 304 int_entry_ptr mpie; 305 int ioints, bus; 306 char *curraddr; 307 char *startaddr; 308 309 startaddr = paddr_guest2host(ctx, MPTABLE_BASE, MPTABLE_MAX_LENGTH); 310 if (startaddr == NULL) { 311 EPRINTLN("mptable requires mapped mem"); 312 return (ENOMEM); 313 } 314 315 /* 316 * There is no way to advertise multiple PCI hierarchies via MPtable 317 * so require that there is no PCI hierarchy with a non-zero bus 318 * number. 319 */ 320 for (bus = 1; bus <= PCI_BUSMAX; bus++) { 321 if (pci_bus_configured(bus)) { 322 EPRINTLN("MPtable is incompatible with " 323 "multiple PCI hierarchies."); 324 EPRINTLN("MPtable generation can be disabled " 325 "by passing the -Y option to bhyve(8)."); 326 return (EINVAL); 327 } 328 } 329 330 curraddr = startaddr; 331 mpfp = (mpfps_t)curraddr; 332 mpt_build_mpfp(mpfp, MPTABLE_BASE); 333 curraddr += sizeof(*mpfp); 334 335 mpch = (mpcth_t)curraddr; 336 mpt_build_mpch(mpch); 337 curraddr += sizeof(*mpch); 338 339 mpep = (proc_entry_ptr)curraddr; 340 mpt_build_proc_entries(mpep, ncpu); 341 curraddr += sizeof(*mpep) * ncpu; 342 mpch->entry_count += ncpu; 343 344 mpeb = (bus_entry_ptr) curraddr; 345 mpt_build_bus_entries(mpeb); 346 curraddr += sizeof(*mpeb) * MPE_NUM_BUSES; 347 mpch->entry_count += MPE_NUM_BUSES; 348 349 mpei = (io_apic_entry_ptr)curraddr; 350 mpt_build_ioapic_entries(mpei, 0); 351 curraddr += sizeof(*mpei); 352 mpch->entry_count++; 353 354 mpie = (int_entry_ptr) curraddr; 355 ioints = mpt_count_ioint_entries(); 356 mpt_build_ioint_entries(mpie, 0); 357 curraddr += sizeof(*mpie) * ioints; 358 mpch->entry_count += ioints; 359 360 mpie = (int_entry_ptr)curraddr; 361 mpt_build_localint_entries(mpie); 362 curraddr += sizeof(*mpie) * MPEII_NUM_LOCAL_IRQ; 363 mpch->entry_count += MPEII_NUM_LOCAL_IRQ; 364 365 if (oem_tbl_start) { 366 mpch->oem_table_pointer = curraddr - startaddr + MPTABLE_BASE; 367 mpch->oem_table_size = oem_tbl_size; 368 memcpy(curraddr, oem_tbl_start, oem_tbl_size); 369 } 370 371 mpch->base_table_length = curraddr - (char *)mpch; 372 mpch->checksum = mpt_compute_checksum(mpch, mpch->base_table_length); 373 374 return (0); 375 } 376