16b021cc2SWarner Losh /*- 24d846d26SWarner Losh * SPDX-License-Identifier: BSD-2-Clause 33e21da8aSMarcelo Araujo * 46b021cc2SWarner Losh * Copyright (c) 2006 Stephane E. Potvin <sepotvin@videotron.ca> 56b021cc2SWarner Losh * All rights reserved. 66b021cc2SWarner Losh * 76b021cc2SWarner Losh * Redistribution and use in source and binary forms, with or without 86b021cc2SWarner Losh * modification, are permitted provided that the following conditions 96b021cc2SWarner Losh * are met: 106b021cc2SWarner Losh * 1. Redistributions of source code must retain the above copyright 116b021cc2SWarner Losh * notice, this list of conditions and the following disclaimer. 126b021cc2SWarner Losh * 2. Redistributions in binary form must reproduce the above copyright 136b021cc2SWarner Losh * notice, this list of conditions and the following disclaimer in the 146b021cc2SWarner Losh * documentation and/or other materials provided with the distribution. 156b021cc2SWarner Losh * 166b021cc2SWarner Losh * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 176b021cc2SWarner Losh * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 186b021cc2SWarner Losh * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 196b021cc2SWarner Losh * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 206b021cc2SWarner Losh * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 216b021cc2SWarner Losh * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 226b021cc2SWarner Losh * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 236b021cc2SWarner Losh * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 246b021cc2SWarner Losh * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 256b021cc2SWarner Losh * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 266b021cc2SWarner Losh * SUCH DAMAGE. 276b021cc2SWarner Losh */ 286b021cc2SWarner Losh 296b021cc2SWarner Losh #ifndef _HDAC_REG_H_ 306b021cc2SWarner Losh #define _HDAC_REG_H_ 316b021cc2SWarner Losh 326b021cc2SWarner Losh /**************************************************************************** 336b021cc2SWarner Losh * HDA Controller Register Set 346b021cc2SWarner Losh ****************************************************************************/ 356b021cc2SWarner Losh #define HDAC_GCAP 0x00 /* 2 - Global Capabilities*/ 366b021cc2SWarner Losh #define HDAC_VMIN 0x02 /* 1 - Minor Version */ 376b021cc2SWarner Losh #define HDAC_VMAJ 0x03 /* 1 - Major Version */ 386b021cc2SWarner Losh #define HDAC_OUTPAY 0x04 /* 2 - Output Payload Capability */ 396b021cc2SWarner Losh #define HDAC_INPAY 0x06 /* 2 - Input Payload Capability */ 406b021cc2SWarner Losh #define HDAC_GCTL 0x08 /* 4 - Global Control */ 416b021cc2SWarner Losh #define HDAC_WAKEEN 0x0c /* 2 - Wake Enable */ 426b021cc2SWarner Losh #define HDAC_STATESTS 0x0e /* 2 - State Change Status */ 436b021cc2SWarner Losh #define HDAC_GSTS 0x10 /* 2 - Global Status */ 446b021cc2SWarner Losh #define HDAC_OUTSTRMPAY 0x18 /* 2 - Output Stream Payload Capability */ 456b021cc2SWarner Losh #define HDAC_INSTRMPAY 0x1a /* 2 - Input Stream Payload Capability */ 466b021cc2SWarner Losh #define HDAC_INTCTL 0x20 /* 4 - Interrupt Control */ 476b021cc2SWarner Losh #define HDAC_INTSTS 0x24 /* 4 - Interrupt Status */ 486b021cc2SWarner Losh #define HDAC_WALCLK 0x30 /* 4 - Wall Clock Counter */ 496b021cc2SWarner Losh #define HDAC_SSYNC 0x38 /* 4 - Stream Synchronization */ 506b021cc2SWarner Losh #define HDAC_CORBLBASE 0x40 /* 4 - CORB Lower Base Address */ 516b021cc2SWarner Losh #define HDAC_CORBUBASE 0x44 /* 4 - CORB Upper Base Address */ 526b021cc2SWarner Losh #define HDAC_CORBWP 0x48 /* 2 - CORB Write Pointer */ 536b021cc2SWarner Losh #define HDAC_CORBRP 0x4a /* 2 - CORB Read Pointer */ 546b021cc2SWarner Losh #define HDAC_CORBCTL 0x4c /* 1 - CORB Control */ 556b021cc2SWarner Losh #define HDAC_CORBSTS 0x4d /* 1 - CORB Status */ 566b021cc2SWarner Losh #define HDAC_CORBSIZE 0x4e /* 1 - CORB Size */ 576b021cc2SWarner Losh #define HDAC_RIRBLBASE 0x50 /* 4 - RIRB Lower Base Address */ 586b021cc2SWarner Losh #define HDAC_RIRBUBASE 0x54 /* 4 - RIRB Upper Base Address */ 596b021cc2SWarner Losh #define HDAC_RIRBWP 0x58 /* 2 - RIRB Write Pointer */ 606b021cc2SWarner Losh #define HDAC_RINTCNT 0x5a /* 2 - Response Interrupt Count */ 616b021cc2SWarner Losh #define HDAC_RIRBCTL 0x5c /* 1 - RIRB Control */ 626b021cc2SWarner Losh #define HDAC_RIRBSTS 0x5d /* 1 - RIRB Status */ 636b021cc2SWarner Losh #define HDAC_RIRBSIZE 0x5e /* 1 - RIRB Size */ 646b021cc2SWarner Losh #define HDAC_ICOI 0x60 /* 4 - Immediate Command Output Interface */ 656b021cc2SWarner Losh #define HDAC_ICII 0x64 /* 4 - Immediate Command Input Interface */ 666b021cc2SWarner Losh #define HDAC_ICIS 0x68 /* 2 - Immediate Command Status */ 676b021cc2SWarner Losh #define HDAC_DPIBLBASE 0x70 /* 4 - DMA Position Buffer Lower Base */ 686b021cc2SWarner Losh #define HDAC_DPIBUBASE 0x74 /* 4 - DMA Position Buffer Upper Base */ 696b021cc2SWarner Losh #define HDAC_SDCTL0 0x80 /* 3 - Stream Descriptor Control */ 706b021cc2SWarner Losh #define HDAC_SDCTL1 0x81 /* 3 - Stream Descriptor Control */ 716b021cc2SWarner Losh #define HDAC_SDCTL2 0x82 /* 3 - Stream Descriptor Control */ 726b021cc2SWarner Losh #define HDAC_SDSTS 0x83 /* 1 - Stream Descriptor Status */ 736b021cc2SWarner Losh #define HDAC_SDLPIB 0x84 /* 4 - Link Position in Buffer */ 746b021cc2SWarner Losh #define HDAC_SDCBL 0x88 /* 4 - Cyclic Buffer Length */ 756b021cc2SWarner Losh #define HDAC_SDLVI 0x8C /* 2 - Last Valid Index */ 766b021cc2SWarner Losh #define HDAC_SDFIFOS 0x90 /* 2 - FIFOS */ 776b021cc2SWarner Losh #define HDAC_SDFMT 0x92 /* 2 - fmt */ 786b021cc2SWarner Losh #define HDAC_SDBDPL 0x98 /* 4 - Buffer Descriptor Pointer Lower Base */ 796b021cc2SWarner Losh #define HDAC_SDBDPU 0x9C /* 4 - Buffer Descriptor Pointer Upper Base */ 806b021cc2SWarner Losh 816b021cc2SWarner Losh #define _HDAC_ISDOFFSET(n, iss, oss) (0x80 + ((n) * 0x20)) 826b021cc2SWarner Losh #define _HDAC_ISDCTL(n, iss, oss) (0x00 + _HDAC_ISDOFFSET(n, iss, oss)) 836b021cc2SWarner Losh #define _HDAC_ISDSTS(n, iss, oss) (0x03 + _HDAC_ISDOFFSET(n, iss, oss)) 846b021cc2SWarner Losh #define _HDAC_ISDPICB(n, iss, oss) (0x04 + _HDAC_ISDOFFSET(n, iss, oss)) 856b021cc2SWarner Losh #define _HDAC_ISDCBL(n, iss, oss) (0x08 + _HDAC_ISDOFFSET(n, iss, oss)) 866b021cc2SWarner Losh #define _HDAC_ISDLVI(n, iss, oss) (0x0c + _HDAC_ISDOFFSET(n, iss, oss)) 876b021cc2SWarner Losh #define _HDAC_ISDFIFOD(n, iss, oss) (0x10 + _HDAC_ISDOFFSET(n, iss, oss)) 886b021cc2SWarner Losh #define _HDAC_ISDFMT(n, iss, oss) (0x12 + _HDAC_ISDOFFSET(n, iss, oss)) 896b021cc2SWarner Losh #define _HDAC_ISDBDPL(n, iss, oss) (0x18 + _HDAC_ISDOFFSET(n, iss, oss)) 906b021cc2SWarner Losh #define _HDAC_ISDBDPU(n, iss, oss) (0x1c + _HDAC_ISDOFFSET(n, iss, oss)) 916b021cc2SWarner Losh 926b021cc2SWarner Losh #define _HDAC_OSDOFFSET(n, iss, oss) (0x80 + ((iss) * 0x20) + ((n) * 0x20)) 936b021cc2SWarner Losh #define _HDAC_OSDCTL(n, iss, oss) (0x00 + _HDAC_OSDOFFSET(n, iss, oss)) 946b021cc2SWarner Losh #define _HDAC_OSDSTS(n, iss, oss) (0x03 + _HDAC_OSDOFFSET(n, iss, oss)) 956b021cc2SWarner Losh #define _HDAC_OSDPICB(n, iss, oss) (0x04 + _HDAC_OSDOFFSET(n, iss, oss)) 966b021cc2SWarner Losh #define _HDAC_OSDCBL(n, iss, oss) (0x08 + _HDAC_OSDOFFSET(n, iss, oss)) 976b021cc2SWarner Losh #define _HDAC_OSDLVI(n, iss, oss) (0x0c + _HDAC_OSDOFFSET(n, iss, oss)) 986b021cc2SWarner Losh #define _HDAC_OSDFIFOD(n, iss, oss) (0x10 + _HDAC_OSDOFFSET(n, iss, oss)) 996b021cc2SWarner Losh #define _HDAC_OSDFMT(n, iss, oss) (0x12 + _HDAC_OSDOFFSET(n, iss, oss)) 1006b021cc2SWarner Losh #define _HDAC_OSDBDPL(n, iss, oss) (0x18 + _HDAC_OSDOFFSET(n, iss, oss)) 1016b021cc2SWarner Losh #define _HDAC_OSDBDPU(n, iss, oss) (0x1c + _HDAC_OSDOFFSET(n, iss, oss)) 1026b021cc2SWarner Losh 1036b021cc2SWarner Losh #define _HDAC_BSDOFFSET(n, iss, oss) \ 1046b021cc2SWarner Losh (0x80 + ((iss) * 0x20) + ((oss) * 0x20) + ((n) * 0x20)) 1056b021cc2SWarner Losh #define _HDAC_BSDCTL(n, iss, oss) (0x00 + _HDAC_BSDOFFSET(n, iss, oss)) 1066b021cc2SWarner Losh #define _HDAC_BSDSTS(n, iss, oss) (0x03 + _HDAC_BSDOFFSET(n, iss, oss)) 1076b021cc2SWarner Losh #define _HDAC_BSDPICB(n, iss, oss) (0x04 + _HDAC_BSDOFFSET(n, iss, oss)) 1086b021cc2SWarner Losh #define _HDAC_BSDCBL(n, iss, oss) (0x08 + _HDAC_BSDOFFSET(n, iss, oss)) 1096b021cc2SWarner Losh #define _HDAC_BSDLVI(n, iss, oss) (0x0c + _HDAC_BSDOFFSET(n, iss, oss)) 1106b021cc2SWarner Losh #define _HDAC_BSDFIFOD(n, iss, oss) (0x10 + _HDAC_BSDOFFSET(n, iss, oss)) 1116b021cc2SWarner Losh #define _HDAC_BSDFMT(n, iss, oss) (0x12 + _HDAC_BSDOFFSET(n, iss, oss)) 1126b021cc2SWarner Losh #define _HDAC_BSDBDPL(n, iss, oss) (0x18 + _HDAC_BSDOFFSET(n, iss, oss)) 1136b021cc2SWarner Losh #define _HDAC_BSDBDBU(n, iss, oss) (0x1c + _HDAC_BSDOFFSET(n, iss, oss)) 1146b021cc2SWarner Losh 1156b021cc2SWarner Losh /**************************************************************************** 1166b021cc2SWarner Losh * HDA Controller Register Fields 1176b021cc2SWarner Losh ****************************************************************************/ 1186b021cc2SWarner Losh 1196b021cc2SWarner Losh /* GCAP - Global Capabilities */ 1206b021cc2SWarner Losh #define HDAC_GCAP_64OK 0x0001 1216b021cc2SWarner Losh #define HDAC_GCAP_NSDO_MASK 0x0006 1226b021cc2SWarner Losh #define HDAC_GCAP_NSDO_SHIFT 1 1236b021cc2SWarner Losh #define HDAC_GCAP_BSS_MASK 0x00f8 1246b021cc2SWarner Losh #define HDAC_GCAP_BSS_SHIFT 3 1256b021cc2SWarner Losh #define HDAC_GCAP_ISS_MASK 0x0f00 1266b021cc2SWarner Losh #define HDAC_GCAP_ISS_SHIFT 8 1276b021cc2SWarner Losh #define HDAC_GCAP_OSS_MASK 0xf000 1286b021cc2SWarner Losh #define HDAC_GCAP_OSS_SHIFT 12 1296b021cc2SWarner Losh 1306b021cc2SWarner Losh #define HDAC_GCAP_NSDO_1SDO 0x00 1316b021cc2SWarner Losh #define HDAC_GCAP_NSDO_2SDO 0x02 1326b021cc2SWarner Losh #define HDAC_GCAP_NSDO_4SDO 0x04 1336b021cc2SWarner Losh 1346b021cc2SWarner Losh #define HDAC_GCAP_BSS(gcap) \ 1356b021cc2SWarner Losh (((gcap) & HDAC_GCAP_BSS_MASK) >> HDAC_GCAP_BSS_SHIFT) 1366b021cc2SWarner Losh #define HDAC_GCAP_ISS(gcap) \ 1376b021cc2SWarner Losh (((gcap) & HDAC_GCAP_ISS_MASK) >> HDAC_GCAP_ISS_SHIFT) 1386b021cc2SWarner Losh #define HDAC_GCAP_OSS(gcap) \ 1396b021cc2SWarner Losh (((gcap) & HDAC_GCAP_OSS_MASK) >> HDAC_GCAP_OSS_SHIFT) 1406b021cc2SWarner Losh #define HDAC_GCAP_NSDO(gcap) \ 1416b021cc2SWarner Losh (((gcap) & HDAC_GCAP_NSDO_MASK) >> HDAC_GCAP_NSDO_SHIFT) 1426b021cc2SWarner Losh 1436b021cc2SWarner Losh /* GCTL - Global Control */ 1446b021cc2SWarner Losh #define HDAC_GCTL_CRST 0x00000001 1456b021cc2SWarner Losh #define HDAC_GCTL_FCNTRL 0x00000002 1466b021cc2SWarner Losh #define HDAC_GCTL_UNSOL 0x00000100 1476b021cc2SWarner Losh 1486b021cc2SWarner Losh /* WAKEEN - Wake Enable */ 1496b021cc2SWarner Losh #define HDAC_WAKEEN_SDIWEN_MASK 0x7fff 1506b021cc2SWarner Losh #define HDAC_WAKEEN_SDIWEN_SHIFT 0 1516b021cc2SWarner Losh 1526b021cc2SWarner Losh /* STATESTS - State Change Status */ 1536b021cc2SWarner Losh #define HDAC_STATESTS_SDIWAKE_MASK 0x7fff 1546b021cc2SWarner Losh #define HDAC_STATESTS_SDIWAKE_SHIFT 0 1556b021cc2SWarner Losh 1566b021cc2SWarner Losh #define HDAC_STATESTS_SDIWAKE(statests, n) \ 1576b021cc2SWarner Losh (((((statests) & HDAC_STATESTS_SDIWAKE_MASK) >> \ 1586b021cc2SWarner Losh HDAC_STATESTS_SDIWAKE_SHIFT) >> (n)) & 0x0001) 1596b021cc2SWarner Losh 1606b021cc2SWarner Losh /* GSTS - Global Status */ 1616b021cc2SWarner Losh #define HDAC_GSTS_FSTS 0x0002 1626b021cc2SWarner Losh 1636b021cc2SWarner Losh /* INTCTL - Interrut Control */ 1646b021cc2SWarner Losh #define HDAC_INTCTL_SIE_MASK 0x3fffffff 1656b021cc2SWarner Losh #define HDAC_INTCTL_SIE_SHIFT 0 1666b021cc2SWarner Losh #define HDAC_INTCTL_CIE 0x40000000 1676b021cc2SWarner Losh #define HDAC_INTCTL_GIE 0x80000000 1686b021cc2SWarner Losh 1696b021cc2SWarner Losh /* INTSTS - Interrupt Status */ 1706b021cc2SWarner Losh #define HDAC_INTSTS_SIS_MASK 0x3fffffff 1716b021cc2SWarner Losh #define HDAC_INTSTS_SIS_SHIFT 0 1726b021cc2SWarner Losh #define HDAC_INTSTS_CIS 0x40000000 1736b021cc2SWarner Losh #define HDAC_INTSTS_GIS 0x80000000 1746b021cc2SWarner Losh 1756b021cc2SWarner Losh /* SSYNC - Stream Synchronization */ 1766b021cc2SWarner Losh #define HDAC_SSYNC_SSYNC_MASK 0x3fffffff 1776b021cc2SWarner Losh #define HDAC_SSYNC_SSYNC_SHIFT 0 1786b021cc2SWarner Losh 1796b021cc2SWarner Losh /* CORBWP - CORB Write Pointer */ 1806b021cc2SWarner Losh #define HDAC_CORBWP_CORBWP_MASK 0x00ff 1816b021cc2SWarner Losh #define HDAC_CORBWP_CORBWP_SHIFT 0 1826b021cc2SWarner Losh 1836b021cc2SWarner Losh /* CORBRP - CORB Read Pointer */ 1846b021cc2SWarner Losh #define HDAC_CORBRP_CORBRP_MASK 0x00ff 1856b021cc2SWarner Losh #define HDAC_CORBRP_CORBRP_SHIFT 0 1866b021cc2SWarner Losh #define HDAC_CORBRP_CORBRPRST 0x8000 1876b021cc2SWarner Losh 1886b021cc2SWarner Losh /* CORBCTL - CORB Control */ 1896b021cc2SWarner Losh #define HDAC_CORBCTL_CMEIE 0x01 1906b021cc2SWarner Losh #define HDAC_CORBCTL_CORBRUN 0x02 1916b021cc2SWarner Losh 1926b021cc2SWarner Losh /* CORBSTS - CORB Status */ 1936b021cc2SWarner Losh #define HDAC_CORBSTS_CMEI 0x01 1946b021cc2SWarner Losh 1956b021cc2SWarner Losh /* CORBSIZE - CORB Size */ 1966b021cc2SWarner Losh #define HDAC_CORBSIZE_CORBSIZE_MASK 0x03 1976b021cc2SWarner Losh #define HDAC_CORBSIZE_CORBSIZE_SHIFT 0 1986b021cc2SWarner Losh #define HDAC_CORBSIZE_CORBSZCAP_MASK 0xf0 1996b021cc2SWarner Losh #define HDAC_CORBSIZE_CORBSZCAP_SHIFT 4 2006b021cc2SWarner Losh 2016b021cc2SWarner Losh #define HDAC_CORBSIZE_CORBSIZE_2 0x00 2026b021cc2SWarner Losh #define HDAC_CORBSIZE_CORBSIZE_16 0x01 2036b021cc2SWarner Losh #define HDAC_CORBSIZE_CORBSIZE_256 0x02 2046b021cc2SWarner Losh 2056b021cc2SWarner Losh #define HDAC_CORBSIZE_CORBSZCAP_2 0x10 2066b021cc2SWarner Losh #define HDAC_CORBSIZE_CORBSZCAP_16 0x20 2076b021cc2SWarner Losh #define HDAC_CORBSIZE_CORBSZCAP_256 0x40 2086b021cc2SWarner Losh 2096b021cc2SWarner Losh #define HDAC_CORBSIZE_CORBSIZE(corbsize) \ 2106b021cc2SWarner Losh (((corbsize) & HDAC_CORBSIZE_CORBSIZE_MASK) >> HDAC_CORBSIZE_CORBSIZE_SHIFT) 2116b021cc2SWarner Losh 2126b021cc2SWarner Losh /* RIRBWP - RIRB Write Pointer */ 2136b021cc2SWarner Losh #define HDAC_RIRBWP_RIRBWP_MASK 0x00ff 2146b021cc2SWarner Losh #define HDAC_RIRBWP_RIRBWP_SHIFT 0 2156b021cc2SWarner Losh #define HDAC_RIRBWP_RIRBWPRST 0x8000 2166b021cc2SWarner Losh 2176b021cc2SWarner Losh /* RINTCTN - Response Interrupt Count */ 2186b021cc2SWarner Losh #define HDAC_RINTCNT_MASK 0x00ff 2196b021cc2SWarner Losh #define HDAC_RINTCNT_SHIFT 0 2206b021cc2SWarner Losh 2216b021cc2SWarner Losh /* RIRBCTL - RIRB Control */ 2226b021cc2SWarner Losh #define HDAC_RIRBCTL_RINTCTL 0x01 2236b021cc2SWarner Losh #define HDAC_RIRBCTL_RIRBDMAEN 0x02 2246b021cc2SWarner Losh #define HDAC_RIRBCTL_RIRBOIC 0x04 2256b021cc2SWarner Losh 2266b021cc2SWarner Losh /* RIRBSTS - RIRB Status */ 2276b021cc2SWarner Losh #define HDAC_RIRBSTS_RINTFL 0x01 2286b021cc2SWarner Losh #define HDAC_RIRBSTS_RIRBOIS 0x04 2296b021cc2SWarner Losh 2306b021cc2SWarner Losh /* RIRBSIZE - RIRB Size */ 2316b021cc2SWarner Losh #define HDAC_RIRBSIZE_RIRBSIZE_MASK 0x03 2326b021cc2SWarner Losh #define HDAC_RIRBSIZE_RIRBSIZE_SHIFT 0 2336b021cc2SWarner Losh #define HDAC_RIRBSIZE_RIRBSZCAP_MASK 0xf0 2346b021cc2SWarner Losh #define HDAC_RIRBSIZE_RIRBSZCAP_SHIFT 4 2356b021cc2SWarner Losh 2366b021cc2SWarner Losh #define HDAC_RIRBSIZE_RIRBSIZE_2 0x00 2376b021cc2SWarner Losh #define HDAC_RIRBSIZE_RIRBSIZE_16 0x01 2386b021cc2SWarner Losh #define HDAC_RIRBSIZE_RIRBSIZE_256 0x02 2396b021cc2SWarner Losh 2406b021cc2SWarner Losh #define HDAC_RIRBSIZE_RIRBSZCAP_2 0x10 2416b021cc2SWarner Losh #define HDAC_RIRBSIZE_RIRBSZCAP_16 0x20 2426b021cc2SWarner Losh #define HDAC_RIRBSIZE_RIRBSZCAP_256 0x40 2436b021cc2SWarner Losh 2446b021cc2SWarner Losh #define HDAC_RIRBSIZE_RIRBSIZE(rirbsize) \ 2456b021cc2SWarner Losh (((rirbsize) & HDAC_RIRBSIZE_RIRBSIZE_MASK) >> HDAC_RIRBSIZE_RIRBSIZE_SHIFT) 2466b021cc2SWarner Losh 2476b021cc2SWarner Losh /* DPLBASE - DMA Position Lower Base Address */ 2486b021cc2SWarner Losh #define HDAC_DPLBASE_DPLBASE_MASK 0xffffff80 2496b021cc2SWarner Losh #define HDAC_DPLBASE_DPLBASE_SHIFT 7 2506b021cc2SWarner Losh #define HDAC_DPLBASE_DPLBASE_DMAPBE 0x00000001 2516b021cc2SWarner Losh 2526b021cc2SWarner Losh /* SDCTL - Stream Descriptor Control */ 2536b021cc2SWarner Losh #define HDAC_SDCTL_SRST 0x000001 2546b021cc2SWarner Losh #define HDAC_SDCTL_RUN 0x000002 2556b021cc2SWarner Losh #define HDAC_SDCTL_IOCE 0x000004 2566b021cc2SWarner Losh #define HDAC_SDCTL_FEIE 0x000008 2576b021cc2SWarner Losh #define HDAC_SDCTL_DEIE 0x000010 2586b021cc2SWarner Losh #define HDAC_SDCTL2_STRIPE_MASK 0x03 2596b021cc2SWarner Losh #define HDAC_SDCTL2_STRIPE_SHIFT 0 2606b021cc2SWarner Losh #define HDAC_SDCTL2_TP 0x04 2616b021cc2SWarner Losh #define HDAC_SDCTL2_DIR 0x08 2626b021cc2SWarner Losh #define HDAC_SDCTL2_STRM_MASK 0xf0 2636b021cc2SWarner Losh #define HDAC_SDCTL2_STRM_SHIFT 4 2646b021cc2SWarner Losh 2656b021cc2SWarner Losh #define HDAC_SDSTS_DESE (1 << 4) 2666b021cc2SWarner Losh #define HDAC_SDSTS_FIFOE (1 << 3) 2676b021cc2SWarner Losh #define HDAC_SDSTS_BCIS (1 << 2) 2686b021cc2SWarner Losh 2696b021cc2SWarner Losh #endif /* _HDAC_REG_H_ */ 270