1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause 3 * 4 * Copyright (c) 2011 NetApp, Inc. 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY NETAPP, INC ``AS IS'' AND 17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 19 * ARE DISCLAIMED. IN NO EVENT SHALL NETAPP, INC OR CONTRIBUTORS BE LIABLE 20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 * 28 * $FreeBSD$ 29 */ 30 31 #include <sys/cdefs.h> 32 __FBSDID("$FreeBSD$"); 33 34 #include <sys/param.h> 35 #include <sys/linker_set.h> 36 #include <sys/mman.h> 37 38 #include <ctype.h> 39 #include <err.h> 40 #include <errno.h> 41 #include <pthread.h> 42 #include <stdio.h> 43 #include <stdlib.h> 44 #include <string.h> 45 #include <strings.h> 46 #include <assert.h> 47 #include <stdbool.h> 48 #include <sysexits.h> 49 50 #include <machine/vmm.h> 51 #include <machine/vmm_snapshot.h> 52 #include <vmmapi.h> 53 54 #include "acpi.h" 55 #include "bhyverun.h" 56 #include "config.h" 57 #include "debug.h" 58 #include "inout.h" 59 #include "ioapic.h" 60 #include "mem.h" 61 #include "pci_emul.h" 62 #include "pci_irq.h" 63 #include "pci_lpc.h" 64 #include "pci_passthru.h" 65 #include "qemu_fwcfg.h" 66 67 #define CONF1_ADDR_PORT 0x0cf8 68 #define CONF1_DATA_PORT 0x0cfc 69 70 #define CONF1_ENABLE 0x80000000ul 71 72 #define MAXBUSES (PCI_BUSMAX + 1) 73 #define MAXSLOTS (PCI_SLOTMAX + 1) 74 #define MAXFUNCS (PCI_FUNCMAX + 1) 75 76 #define GB (1024 * 1024 * 1024UL) 77 78 struct funcinfo { 79 nvlist_t *fi_config; 80 struct pci_devemu *fi_pde; 81 struct pci_devinst *fi_devi; 82 }; 83 84 struct intxinfo { 85 int ii_count; 86 int ii_pirq_pin; 87 int ii_ioapic_irq; 88 }; 89 90 struct slotinfo { 91 struct intxinfo si_intpins[4]; 92 struct funcinfo si_funcs[MAXFUNCS]; 93 }; 94 95 struct businfo { 96 uint16_t iobase, iolimit; /* I/O window */ 97 uint32_t membase32, memlimit32; /* mmio window below 4GB */ 98 uint64_t membase64, memlimit64; /* mmio window above 4GB */ 99 struct slotinfo slotinfo[MAXSLOTS]; 100 }; 101 102 static struct businfo *pci_businfo[MAXBUSES]; 103 104 SET_DECLARE(pci_devemu_set, struct pci_devemu); 105 106 static uint64_t pci_emul_iobase; 107 static uint8_t *pci_emul_rombase; 108 static uint64_t pci_emul_romoffset; 109 static uint8_t *pci_emul_romlim; 110 static uint64_t pci_emul_membase32; 111 static uint64_t pci_emul_membase64; 112 static uint64_t pci_emul_memlim64; 113 114 struct pci_bar_allocation { 115 TAILQ_ENTRY(pci_bar_allocation) chain; 116 struct pci_devinst *pdi; 117 int idx; 118 enum pcibar_type type; 119 uint64_t size; 120 }; 121 122 static TAILQ_HEAD(pci_bar_list, pci_bar_allocation) pci_bars = 123 TAILQ_HEAD_INITIALIZER(pci_bars); 124 125 struct boot_device { 126 TAILQ_ENTRY(boot_device) boot_device_chain; 127 struct pci_devinst *pdi; 128 int bootindex; 129 }; 130 static TAILQ_HEAD(boot_list, boot_device) boot_devices = TAILQ_HEAD_INITIALIZER( 131 boot_devices); 132 133 #define PCI_EMUL_IOBASE 0x2000 134 #define PCI_EMUL_IOLIMIT 0x10000 135 136 #define PCI_EMUL_ROMSIZE 0x10000000 137 138 #define PCI_EMUL_ECFG_BASE 0xE0000000 /* 3.5GB */ 139 #define PCI_EMUL_ECFG_SIZE (MAXBUSES * 1024 * 1024) /* 1MB per bus */ 140 SYSRES_MEM(PCI_EMUL_ECFG_BASE, PCI_EMUL_ECFG_SIZE); 141 142 /* 143 * OVMF always uses 0xC0000000 as base address for 32 bit PCI MMIO. Don't 144 * change this address without changing it in OVMF. 145 */ 146 #define PCI_EMUL_MEMBASE32 0xC0000000 147 #define PCI_EMUL_MEMLIMIT32 PCI_EMUL_ECFG_BASE 148 #define PCI_EMUL_MEMSIZE64 (32*GB) 149 150 static struct pci_devemu *pci_emul_finddev(const char *name); 151 static void pci_lintr_route(struct pci_devinst *pi); 152 static void pci_lintr_update(struct pci_devinst *pi); 153 static void pci_cfgrw(int in, int bus, int slot, int func, int coff, 154 int bytes, uint32_t *val); 155 156 static __inline void 157 CFGWRITE(struct pci_devinst *pi, int coff, uint32_t val, int bytes) 158 { 159 160 if (bytes == 1) 161 pci_set_cfgdata8(pi, coff, val); 162 else if (bytes == 2) 163 pci_set_cfgdata16(pi, coff, val); 164 else 165 pci_set_cfgdata32(pi, coff, val); 166 } 167 168 static __inline uint32_t 169 CFGREAD(struct pci_devinst *pi, int coff, int bytes) 170 { 171 172 if (bytes == 1) 173 return (pci_get_cfgdata8(pi, coff)); 174 else if (bytes == 2) 175 return (pci_get_cfgdata16(pi, coff)); 176 else 177 return (pci_get_cfgdata32(pi, coff)); 178 } 179 180 static int 181 is_pcir_bar(int coff) 182 { 183 return (coff >= PCIR_BAR(0) && coff < PCIR_BAR(PCI_BARMAX + 1)); 184 } 185 186 static int 187 is_pcir_bios(int coff) 188 { 189 return (coff >= PCIR_BIOS && coff < PCIR_BIOS + 4); 190 } 191 192 /* 193 * I/O access 194 */ 195 196 /* 197 * Slot options are in the form: 198 * 199 * <bus>:<slot>:<func>,<emul>[,<config>] 200 * <slot>[:<func>],<emul>[,<config>] 201 * 202 * slot is 0..31 203 * func is 0..7 204 * emul is a string describing the type of PCI device e.g. virtio-net 205 * config is an optional string, depending on the device, that can be 206 * used for configuration. 207 * Examples are: 208 * 1,virtio-net,tap0 209 * 3:0,dummy 210 */ 211 static void 212 pci_parse_slot_usage(char *aopt) 213 { 214 215 EPRINTLN("Invalid PCI slot info field \"%s\"", aopt); 216 } 217 218 /* 219 * Helper function to parse a list of comma-separated options where 220 * each option is formatted as "name[=value]". If no value is 221 * provided, the option is treated as a boolean and is given a value 222 * of true. 223 */ 224 int 225 pci_parse_legacy_config(nvlist_t *nvl, const char *opt) 226 { 227 char *config, *name, *tofree, *value; 228 229 if (opt == NULL) 230 return (0); 231 232 config = tofree = strdup(opt); 233 while ((name = strsep(&config, ",")) != NULL) { 234 value = strchr(name, '='); 235 if (value != NULL) { 236 *value = '\0'; 237 value++; 238 set_config_value_node(nvl, name, value); 239 } else 240 set_config_bool_node(nvl, name, true); 241 } 242 free(tofree); 243 return (0); 244 } 245 246 /* 247 * PCI device configuration is stored in MIBs that encode the device's 248 * location: 249 * 250 * pci.<bus>.<slot>.<func> 251 * 252 * Where "bus", "slot", and "func" are all decimal values without 253 * leading zeroes. Each valid device must have a "device" node which 254 * identifies the driver model of the device. 255 * 256 * Device backends can provide a parser for the "config" string. If 257 * a custom parser is not provided, pci_parse_legacy_config() is used 258 * to parse the string. 259 */ 260 int 261 pci_parse_slot(char *opt) 262 { 263 char node_name[sizeof("pci.XXX.XX.X")]; 264 struct pci_devemu *pde; 265 char *emul, *config, *str, *cp; 266 int error, bnum, snum, fnum; 267 nvlist_t *nvl; 268 269 error = -1; 270 str = strdup(opt); 271 272 emul = config = NULL; 273 if ((cp = strchr(str, ',')) != NULL) { 274 *cp = '\0'; 275 emul = cp + 1; 276 if ((cp = strchr(emul, ',')) != NULL) { 277 *cp = '\0'; 278 config = cp + 1; 279 } 280 } else { 281 pci_parse_slot_usage(opt); 282 goto done; 283 } 284 285 /* <bus>:<slot>:<func> */ 286 if (sscanf(str, "%d:%d:%d", &bnum, &snum, &fnum) != 3) { 287 bnum = 0; 288 /* <slot>:<func> */ 289 if (sscanf(str, "%d:%d", &snum, &fnum) != 2) { 290 fnum = 0; 291 /* <slot> */ 292 if (sscanf(str, "%d", &snum) != 1) { 293 snum = -1; 294 } 295 } 296 } 297 298 if (bnum < 0 || bnum >= MAXBUSES || snum < 0 || snum >= MAXSLOTS || 299 fnum < 0 || fnum >= MAXFUNCS) { 300 pci_parse_slot_usage(opt); 301 goto done; 302 } 303 304 pde = pci_emul_finddev(emul); 305 if (pde == NULL) { 306 EPRINTLN("pci slot %d:%d:%d: unknown device \"%s\"", bnum, snum, 307 fnum, emul); 308 goto done; 309 } 310 311 snprintf(node_name, sizeof(node_name), "pci.%d.%d.%d", bnum, snum, 312 fnum); 313 nvl = find_config_node(node_name); 314 if (nvl != NULL) { 315 EPRINTLN("pci slot %d:%d:%d already occupied!", bnum, snum, 316 fnum); 317 goto done; 318 } 319 nvl = create_config_node(node_name); 320 if (pde->pe_alias != NULL) 321 set_config_value_node(nvl, "device", pde->pe_alias); 322 else 323 set_config_value_node(nvl, "device", pde->pe_emu); 324 325 if (pde->pe_legacy_config != NULL) 326 error = pde->pe_legacy_config(nvl, config); 327 else 328 error = pci_parse_legacy_config(nvl, config); 329 done: 330 free(str); 331 return (error); 332 } 333 334 void 335 pci_print_supported_devices(void) 336 { 337 struct pci_devemu **pdpp, *pdp; 338 339 SET_FOREACH(pdpp, pci_devemu_set) { 340 pdp = *pdpp; 341 printf("%s\n", pdp->pe_emu); 342 } 343 } 344 345 uint32_t 346 pci_config_read_reg(const struct pcisel *const host_sel, nvlist_t *nvl, 347 const uint32_t reg, const uint8_t size, const uint32_t def) 348 { 349 const char *config; 350 const nvlist_t *pci_regs; 351 352 assert(size == 1 || size == 2 || size == 4); 353 354 pci_regs = find_relative_config_node(nvl, "pcireg"); 355 if (pci_regs == NULL) { 356 return def; 357 } 358 359 switch (reg) { 360 case PCIR_DEVICE: 361 config = get_config_value_node(pci_regs, "device"); 362 break; 363 case PCIR_VENDOR: 364 config = get_config_value_node(pci_regs, "vendor"); 365 break; 366 case PCIR_REVID: 367 config = get_config_value_node(pci_regs, "revid"); 368 break; 369 case PCIR_SUBVEND_0: 370 config = get_config_value_node(pci_regs, "subvendor"); 371 break; 372 case PCIR_SUBDEV_0: 373 config = get_config_value_node(pci_regs, "subdevice"); 374 break; 375 default: 376 return (-1); 377 } 378 379 if (config == NULL) { 380 return def; 381 } else if (host_sel != NULL && strcmp(config, "host") == 0) { 382 return read_config(host_sel, reg, size); 383 } else { 384 return strtol(config, NULL, 16); 385 } 386 } 387 388 static int 389 pci_valid_pba_offset(struct pci_devinst *pi, uint64_t offset) 390 { 391 392 if (offset < pi->pi_msix.pba_offset) 393 return (0); 394 395 if (offset >= pi->pi_msix.pba_offset + pi->pi_msix.pba_size) { 396 return (0); 397 } 398 399 return (1); 400 } 401 402 int 403 pci_emul_msix_twrite(struct pci_devinst *pi, uint64_t offset, int size, 404 uint64_t value) 405 { 406 int msix_entry_offset; 407 int tab_index; 408 char *dest; 409 410 /* support only 4 or 8 byte writes */ 411 if (size != 4 && size != 8) 412 return (-1); 413 414 /* 415 * Return if table index is beyond what device supports 416 */ 417 tab_index = offset / MSIX_TABLE_ENTRY_SIZE; 418 if (tab_index >= pi->pi_msix.table_count) 419 return (-1); 420 421 msix_entry_offset = offset % MSIX_TABLE_ENTRY_SIZE; 422 423 /* support only aligned writes */ 424 if ((msix_entry_offset % size) != 0) 425 return (-1); 426 427 dest = (char *)(pi->pi_msix.table + tab_index); 428 dest += msix_entry_offset; 429 430 if (size == 4) 431 *((uint32_t *)dest) = value; 432 else 433 *((uint64_t *)dest) = value; 434 435 return (0); 436 } 437 438 uint64_t 439 pci_emul_msix_tread(struct pci_devinst *pi, uint64_t offset, int size) 440 { 441 char *dest; 442 int msix_entry_offset; 443 int tab_index; 444 uint64_t retval = ~0; 445 446 /* 447 * The PCI standard only allows 4 and 8 byte accesses to the MSI-X 448 * table but we also allow 1 byte access to accommodate reads from 449 * ddb. 450 */ 451 if (size != 1 && size != 4 && size != 8) 452 return (retval); 453 454 msix_entry_offset = offset % MSIX_TABLE_ENTRY_SIZE; 455 456 /* support only aligned reads */ 457 if ((msix_entry_offset % size) != 0) { 458 return (retval); 459 } 460 461 tab_index = offset / MSIX_TABLE_ENTRY_SIZE; 462 463 if (tab_index < pi->pi_msix.table_count) { 464 /* valid MSI-X Table access */ 465 dest = (char *)(pi->pi_msix.table + tab_index); 466 dest += msix_entry_offset; 467 468 if (size == 1) 469 retval = *((uint8_t *)dest); 470 else if (size == 4) 471 retval = *((uint32_t *)dest); 472 else 473 retval = *((uint64_t *)dest); 474 } else if (pci_valid_pba_offset(pi, offset)) { 475 /* return 0 for PBA access */ 476 retval = 0; 477 } 478 479 return (retval); 480 } 481 482 int 483 pci_msix_table_bar(struct pci_devinst *pi) 484 { 485 486 if (pi->pi_msix.table != NULL) 487 return (pi->pi_msix.table_bar); 488 else 489 return (-1); 490 } 491 492 int 493 pci_msix_pba_bar(struct pci_devinst *pi) 494 { 495 496 if (pi->pi_msix.table != NULL) 497 return (pi->pi_msix.pba_bar); 498 else 499 return (-1); 500 } 501 502 static int 503 pci_emul_io_handler(struct vmctx *ctx __unused, int in, int port, 504 int bytes, uint32_t *eax, void *arg) 505 { 506 struct pci_devinst *pdi = arg; 507 struct pci_devemu *pe = pdi->pi_d; 508 uint64_t offset; 509 int i; 510 511 assert(port >= 0); 512 513 for (i = 0; i <= PCI_BARMAX; i++) { 514 if (pdi->pi_bar[i].type == PCIBAR_IO && 515 (uint64_t)port >= pdi->pi_bar[i].addr && 516 (uint64_t)port + bytes <= 517 pdi->pi_bar[i].addr + pdi->pi_bar[i].size) { 518 offset = port - pdi->pi_bar[i].addr; 519 if (in) 520 *eax = (*pe->pe_barread)(pdi, i, 521 offset, bytes); 522 else 523 (*pe->pe_barwrite)(pdi, i, offset, 524 bytes, *eax); 525 return (0); 526 } 527 } 528 return (-1); 529 } 530 531 static int 532 pci_emul_mem_handler(struct vcpu *vcpu __unused, int dir, 533 uint64_t addr, int size, uint64_t *val, void *arg1, long arg2) 534 { 535 struct pci_devinst *pdi = arg1; 536 struct pci_devemu *pe = pdi->pi_d; 537 uint64_t offset; 538 int bidx = (int) arg2; 539 540 assert(bidx <= PCI_BARMAX); 541 assert(pdi->pi_bar[bidx].type == PCIBAR_MEM32 || 542 pdi->pi_bar[bidx].type == PCIBAR_MEM64); 543 assert(addr >= pdi->pi_bar[bidx].addr && 544 addr + size <= pdi->pi_bar[bidx].addr + pdi->pi_bar[bidx].size); 545 546 offset = addr - pdi->pi_bar[bidx].addr; 547 548 if (dir == MEM_F_WRITE) { 549 if (size == 8) { 550 (*pe->pe_barwrite)(pdi, bidx, offset, 551 4, *val & 0xffffffff); 552 (*pe->pe_barwrite)(pdi, bidx, offset + 4, 553 4, *val >> 32); 554 } else { 555 (*pe->pe_barwrite)(pdi, bidx, offset, 556 size, *val); 557 } 558 } else { 559 if (size == 8) { 560 *val = (*pe->pe_barread)(pdi, bidx, 561 offset, 4); 562 *val |= (*pe->pe_barread)(pdi, bidx, 563 offset + 4, 4) << 32; 564 } else { 565 *val = (*pe->pe_barread)(pdi, bidx, 566 offset, size); 567 } 568 } 569 570 return (0); 571 } 572 573 574 static int 575 pci_emul_alloc_resource(uint64_t *baseptr, uint64_t limit, uint64_t size, 576 uint64_t *addr) 577 { 578 uint64_t base; 579 580 assert((size & (size - 1)) == 0); /* must be a power of 2 */ 581 582 base = roundup2(*baseptr, size); 583 584 if (base + size <= limit) { 585 *addr = base; 586 *baseptr = base + size; 587 return (0); 588 } else 589 return (-1); 590 } 591 592 /* 593 * Register (or unregister) the MMIO or I/O region associated with the BAR 594 * register 'idx' of an emulated pci device. 595 */ 596 static void 597 modify_bar_registration(struct pci_devinst *pi, int idx, int registration) 598 { 599 struct pci_devemu *pe; 600 int error; 601 struct inout_port iop; 602 struct mem_range mr; 603 604 pe = pi->pi_d; 605 switch (pi->pi_bar[idx].type) { 606 case PCIBAR_IO: 607 bzero(&iop, sizeof(struct inout_port)); 608 iop.name = pi->pi_name; 609 iop.port = pi->pi_bar[idx].addr; 610 iop.size = pi->pi_bar[idx].size; 611 if (registration) { 612 iop.flags = IOPORT_F_INOUT; 613 iop.handler = pci_emul_io_handler; 614 iop.arg = pi; 615 error = register_inout(&iop); 616 } else 617 error = unregister_inout(&iop); 618 if (pe->pe_baraddr != NULL) 619 (*pe->pe_baraddr)(pi, idx, registration, 620 pi->pi_bar[idx].addr); 621 break; 622 case PCIBAR_MEM32: 623 case PCIBAR_MEM64: 624 bzero(&mr, sizeof(struct mem_range)); 625 mr.name = pi->pi_name; 626 mr.base = pi->pi_bar[idx].addr; 627 mr.size = pi->pi_bar[idx].size; 628 if (registration) { 629 mr.flags = MEM_F_RW; 630 mr.handler = pci_emul_mem_handler; 631 mr.arg1 = pi; 632 mr.arg2 = idx; 633 error = register_mem(&mr); 634 } else 635 error = unregister_mem(&mr); 636 if (pe->pe_baraddr != NULL) 637 (*pe->pe_baraddr)(pi, idx, registration, 638 pi->pi_bar[idx].addr); 639 break; 640 case PCIBAR_ROM: 641 error = 0; 642 if (pe->pe_baraddr != NULL) 643 (*pe->pe_baraddr)(pi, idx, registration, 644 pi->pi_bar[idx].addr); 645 break; 646 default: 647 error = EINVAL; 648 break; 649 } 650 assert(error == 0); 651 } 652 653 static void 654 unregister_bar(struct pci_devinst *pi, int idx) 655 { 656 657 modify_bar_registration(pi, idx, 0); 658 } 659 660 static void 661 register_bar(struct pci_devinst *pi, int idx) 662 { 663 664 modify_bar_registration(pi, idx, 1); 665 } 666 667 /* Is the ROM enabled for the emulated pci device? */ 668 static int 669 romen(struct pci_devinst *pi) 670 { 671 return (pi->pi_bar[PCI_ROM_IDX].lobits & PCIM_BIOS_ENABLE) == 672 PCIM_BIOS_ENABLE; 673 } 674 675 /* Are we decoding i/o port accesses for the emulated pci device? */ 676 static int 677 porten(struct pci_devinst *pi) 678 { 679 uint16_t cmd; 680 681 cmd = pci_get_cfgdata16(pi, PCIR_COMMAND); 682 683 return (cmd & PCIM_CMD_PORTEN); 684 } 685 686 /* Are we decoding memory accesses for the emulated pci device? */ 687 static int 688 memen(struct pci_devinst *pi) 689 { 690 uint16_t cmd; 691 692 cmd = pci_get_cfgdata16(pi, PCIR_COMMAND); 693 694 return (cmd & PCIM_CMD_MEMEN); 695 } 696 697 /* 698 * Update the MMIO or I/O address that is decoded by the BAR register. 699 * 700 * If the pci device has enabled the address space decoding then intercept 701 * the address range decoded by the BAR register. 702 */ 703 static void 704 update_bar_address(struct pci_devinst *pi, uint64_t addr, int idx, int type) 705 { 706 int decode; 707 708 if (pi->pi_bar[idx].type == PCIBAR_IO) 709 decode = porten(pi); 710 else 711 decode = memen(pi); 712 713 if (decode) 714 unregister_bar(pi, idx); 715 716 switch (type) { 717 case PCIBAR_IO: 718 case PCIBAR_MEM32: 719 pi->pi_bar[idx].addr = addr; 720 break; 721 case PCIBAR_MEM64: 722 pi->pi_bar[idx].addr &= ~0xffffffffUL; 723 pi->pi_bar[idx].addr |= addr; 724 break; 725 case PCIBAR_MEMHI64: 726 pi->pi_bar[idx].addr &= 0xffffffff; 727 pi->pi_bar[idx].addr |= addr; 728 break; 729 default: 730 assert(0); 731 } 732 733 if (decode) 734 register_bar(pi, idx); 735 } 736 737 int 738 pci_emul_alloc_bar(struct pci_devinst *pdi, int idx, enum pcibar_type type, 739 uint64_t size) 740 { 741 assert((type == PCIBAR_ROM) || (idx >= 0 && idx <= PCI_BARMAX)); 742 assert((type != PCIBAR_ROM) || (idx == PCI_ROM_IDX)); 743 744 if ((size & (size - 1)) != 0) 745 size = 1UL << flsl(size); /* round up to a power of 2 */ 746 747 /* Enforce minimum BAR sizes required by the PCI standard */ 748 if (type == PCIBAR_IO) { 749 if (size < 4) 750 size = 4; 751 } else if (type == PCIBAR_ROM) { 752 if (size < ~PCIM_BIOS_ADDR_MASK + 1) 753 size = ~PCIM_BIOS_ADDR_MASK + 1; 754 } else { 755 if (size < 16) 756 size = 16; 757 } 758 759 /* 760 * To reduce fragmentation of the MMIO space, we allocate the BARs by 761 * size. Therefore, don't allocate the BAR yet. We create a list of all 762 * BAR allocation which is sorted by BAR size. When all PCI devices are 763 * initialized, we will assign an address to the BARs. 764 */ 765 766 /* create a new list entry */ 767 struct pci_bar_allocation *const new_bar = malloc(sizeof(*new_bar)); 768 memset(new_bar, 0, sizeof(*new_bar)); 769 new_bar->pdi = pdi; 770 new_bar->idx = idx; 771 new_bar->type = type; 772 new_bar->size = size; 773 774 /* 775 * Search for a BAR which size is lower than the size of our newly 776 * allocated BAR. 777 */ 778 struct pci_bar_allocation *bar = NULL; 779 TAILQ_FOREACH(bar, &pci_bars, chain) { 780 if (bar->size < size) { 781 break; 782 } 783 } 784 785 if (bar == NULL) { 786 /* 787 * Either the list is empty or new BAR is the smallest BAR of 788 * the list. Append it to the end of our list. 789 */ 790 TAILQ_INSERT_TAIL(&pci_bars, new_bar, chain); 791 } else { 792 /* 793 * The found BAR is smaller than our new BAR. For that reason, 794 * insert our new BAR before the found BAR. 795 */ 796 TAILQ_INSERT_BEFORE(bar, new_bar, chain); 797 } 798 799 /* 800 * pci_passthru devices synchronize their physical and virtual command 801 * register on init. For that reason, the virtual cmd reg should be 802 * updated as early as possible. 803 */ 804 uint16_t enbit = 0; 805 switch (type) { 806 case PCIBAR_IO: 807 enbit = PCIM_CMD_PORTEN; 808 break; 809 case PCIBAR_MEM64: 810 case PCIBAR_MEM32: 811 enbit = PCIM_CMD_MEMEN; 812 break; 813 default: 814 enbit = 0; 815 break; 816 } 817 818 const uint16_t cmd = pci_get_cfgdata16(pdi, PCIR_COMMAND); 819 pci_set_cfgdata16(pdi, PCIR_COMMAND, cmd | enbit); 820 821 return (0); 822 } 823 824 static int 825 pci_emul_assign_bar(struct pci_devinst *const pdi, const int idx, 826 const enum pcibar_type type, const uint64_t size) 827 { 828 int error; 829 uint64_t *baseptr, limit, addr, mask, lobits, bar; 830 831 switch (type) { 832 case PCIBAR_NONE: 833 baseptr = NULL; 834 addr = mask = lobits = 0; 835 break; 836 case PCIBAR_IO: 837 baseptr = &pci_emul_iobase; 838 limit = PCI_EMUL_IOLIMIT; 839 mask = PCIM_BAR_IO_BASE; 840 lobits = PCIM_BAR_IO_SPACE; 841 break; 842 case PCIBAR_MEM64: 843 /* 844 * XXX 845 * Some drivers do not work well if the 64-bit BAR is allocated 846 * above 4GB. Allow for this by allocating small requests under 847 * 4GB unless then allocation size is larger than some arbitrary 848 * number (128MB currently). 849 */ 850 if (size > 128 * 1024 * 1024) { 851 baseptr = &pci_emul_membase64; 852 limit = pci_emul_memlim64; 853 mask = PCIM_BAR_MEM_BASE; 854 lobits = PCIM_BAR_MEM_SPACE | PCIM_BAR_MEM_64 | 855 PCIM_BAR_MEM_PREFETCH; 856 } else { 857 baseptr = &pci_emul_membase32; 858 limit = PCI_EMUL_MEMLIMIT32; 859 mask = PCIM_BAR_MEM_BASE; 860 lobits = PCIM_BAR_MEM_SPACE | PCIM_BAR_MEM_64; 861 } 862 break; 863 case PCIBAR_MEM32: 864 baseptr = &pci_emul_membase32; 865 limit = PCI_EMUL_MEMLIMIT32; 866 mask = PCIM_BAR_MEM_BASE; 867 lobits = PCIM_BAR_MEM_SPACE | PCIM_BAR_MEM_32; 868 break; 869 case PCIBAR_ROM: 870 /* do not claim memory for ROM. OVMF will do it for us. */ 871 baseptr = NULL; 872 limit = 0; 873 mask = PCIM_BIOS_ADDR_MASK; 874 lobits = 0; 875 break; 876 default: 877 printf("pci_emul_alloc_base: invalid bar type %d\n", type); 878 assert(0); 879 } 880 881 if (baseptr != NULL) { 882 error = pci_emul_alloc_resource(baseptr, limit, size, &addr); 883 if (error != 0) 884 return (error); 885 } else { 886 addr = 0; 887 } 888 889 pdi->pi_bar[idx].type = type; 890 pdi->pi_bar[idx].addr = addr; 891 pdi->pi_bar[idx].size = size; 892 /* 893 * passthru devices are using same lobits as physical device they set 894 * this property 895 */ 896 if (pdi->pi_bar[idx].lobits != 0) { 897 lobits = pdi->pi_bar[idx].lobits; 898 } else { 899 pdi->pi_bar[idx].lobits = lobits; 900 } 901 902 /* Initialize the BAR register in config space */ 903 bar = (addr & mask) | lobits; 904 pci_set_cfgdata32(pdi, PCIR_BAR(idx), bar); 905 906 if (type == PCIBAR_MEM64) { 907 assert(idx + 1 <= PCI_BARMAX); 908 pdi->pi_bar[idx + 1].type = PCIBAR_MEMHI64; 909 pci_set_cfgdata32(pdi, PCIR_BAR(idx + 1), bar >> 32); 910 } 911 912 if (type != PCIBAR_ROM) { 913 register_bar(pdi, idx); 914 } 915 916 return (0); 917 } 918 919 int 920 pci_emul_alloc_rom(struct pci_devinst *const pdi, const uint64_t size, 921 void **const addr) 922 { 923 /* allocate ROM space once on first call */ 924 if (pci_emul_rombase == 0) { 925 pci_emul_rombase = vm_create_devmem(pdi->pi_vmctx, VM_PCIROM, 926 "pcirom", PCI_EMUL_ROMSIZE); 927 if (pci_emul_rombase == MAP_FAILED) { 928 warnx("%s: failed to create rom segment", __func__); 929 return (-1); 930 } 931 pci_emul_romlim = pci_emul_rombase + PCI_EMUL_ROMSIZE; 932 pci_emul_romoffset = 0; 933 } 934 935 /* ROM size should be a power of 2 and greater than 2 KB */ 936 const uint64_t rom_size = MAX(1UL << flsl(size), 937 ~PCIM_BIOS_ADDR_MASK + 1); 938 939 /* check if ROM fits into ROM space */ 940 if (pci_emul_romoffset + rom_size > PCI_EMUL_ROMSIZE) { 941 warnx("%s: no space left in rom segment:", __func__); 942 warnx("%16lu bytes left", 943 PCI_EMUL_ROMSIZE - pci_emul_romoffset); 944 warnx("%16lu bytes required by %d/%d/%d", rom_size, pdi->pi_bus, 945 pdi->pi_slot, pdi->pi_func); 946 return (-1); 947 } 948 949 /* allocate ROM BAR */ 950 const int error = pci_emul_alloc_bar(pdi, PCI_ROM_IDX, PCIBAR_ROM, 951 rom_size); 952 if (error) 953 return error; 954 955 /* return address */ 956 *addr = pci_emul_rombase + pci_emul_romoffset; 957 958 /* save offset into ROM Space */ 959 pdi->pi_romoffset = pci_emul_romoffset; 960 961 /* increase offset for next ROM */ 962 pci_emul_romoffset += rom_size; 963 964 return (0); 965 } 966 967 int 968 pci_emul_add_boot_device(struct pci_devinst *pi, int bootindex) 969 { 970 struct boot_device *new_device, *device; 971 972 /* don't permit a negative bootindex */ 973 if (bootindex < 0) { 974 errx(4, "Invalid bootindex %d for %s", bootindex, pi->pi_name); 975 } 976 977 /* alloc new boot device */ 978 new_device = calloc(1, sizeof(struct boot_device)); 979 if (new_device == NULL) { 980 return (ENOMEM); 981 } 982 new_device->pdi = pi; 983 new_device->bootindex = bootindex; 984 985 /* search for boot device with higher boot index */ 986 TAILQ_FOREACH(device, &boot_devices, boot_device_chain) { 987 if (device->bootindex == bootindex) { 988 errx(4, 989 "Could not set bootindex %d for %s. Bootindex already occupied by %s", 990 bootindex, pi->pi_name, device->pdi->pi_name); 991 } else if (device->bootindex > bootindex) { 992 break; 993 } 994 } 995 996 /* add boot device to queue */ 997 if (device == NULL) { 998 TAILQ_INSERT_TAIL(&boot_devices, new_device, boot_device_chain); 999 } else { 1000 TAILQ_INSERT_BEFORE(device, new_device, boot_device_chain); 1001 } 1002 1003 return (0); 1004 } 1005 1006 #define CAP_START_OFFSET 0x40 1007 static int 1008 pci_emul_add_capability(struct pci_devinst *pi, u_char *capdata, int caplen) 1009 { 1010 int i, capoff, reallen; 1011 uint16_t sts; 1012 1013 assert(caplen > 0); 1014 1015 reallen = roundup2(caplen, 4); /* dword aligned */ 1016 1017 sts = pci_get_cfgdata16(pi, PCIR_STATUS); 1018 if ((sts & PCIM_STATUS_CAPPRESENT) == 0) 1019 capoff = CAP_START_OFFSET; 1020 else 1021 capoff = pi->pi_capend + 1; 1022 1023 /* Check if we have enough space */ 1024 if (capoff + reallen > PCI_REGMAX + 1) 1025 return (-1); 1026 1027 /* Set the previous capability pointer */ 1028 if ((sts & PCIM_STATUS_CAPPRESENT) == 0) { 1029 pci_set_cfgdata8(pi, PCIR_CAP_PTR, capoff); 1030 pci_set_cfgdata16(pi, PCIR_STATUS, sts|PCIM_STATUS_CAPPRESENT); 1031 } else 1032 pci_set_cfgdata8(pi, pi->pi_prevcap + 1, capoff); 1033 1034 /* Copy the capability */ 1035 for (i = 0; i < caplen; i++) 1036 pci_set_cfgdata8(pi, capoff + i, capdata[i]); 1037 1038 /* Set the next capability pointer */ 1039 pci_set_cfgdata8(pi, capoff + 1, 0); 1040 1041 pi->pi_prevcap = capoff; 1042 pi->pi_capend = capoff + reallen - 1; 1043 return (0); 1044 } 1045 1046 static struct pci_devemu * 1047 pci_emul_finddev(const char *name) 1048 { 1049 struct pci_devemu **pdpp, *pdp; 1050 1051 SET_FOREACH(pdpp, pci_devemu_set) { 1052 pdp = *pdpp; 1053 if (!strcmp(pdp->pe_emu, name)) { 1054 return (pdp); 1055 } 1056 } 1057 1058 return (NULL); 1059 } 1060 1061 static int 1062 pci_emul_init(struct vmctx *ctx, struct pci_devemu *pde, int bus, int slot, 1063 int func, struct funcinfo *fi) 1064 { 1065 struct pci_devinst *pdi; 1066 int err; 1067 1068 pdi = calloc(1, sizeof(struct pci_devinst)); 1069 1070 pdi->pi_vmctx = ctx; 1071 pdi->pi_bus = bus; 1072 pdi->pi_slot = slot; 1073 pdi->pi_func = func; 1074 pthread_mutex_init(&pdi->pi_lintr.lock, NULL); 1075 pdi->pi_lintr.pin = 0; 1076 pdi->pi_lintr.state = IDLE; 1077 pdi->pi_lintr.pirq_pin = 0; 1078 pdi->pi_lintr.ioapic_irq = 0; 1079 pdi->pi_d = pde; 1080 snprintf(pdi->pi_name, PI_NAMESZ, "%s@pci.%d.%d.%d", pde->pe_emu, bus, 1081 slot, func); 1082 1083 /* Disable legacy interrupts */ 1084 pci_set_cfgdata8(pdi, PCIR_INTLINE, 255); 1085 pci_set_cfgdata8(pdi, PCIR_INTPIN, 0); 1086 1087 pci_set_cfgdata8(pdi, PCIR_COMMAND, PCIM_CMD_BUSMASTEREN); 1088 1089 err = (*pde->pe_init)(pdi, fi->fi_config); 1090 if (err == 0) 1091 fi->fi_devi = pdi; 1092 else 1093 free(pdi); 1094 1095 return (err); 1096 } 1097 1098 void 1099 pci_populate_msicap(struct msicap *msicap, int msgnum, int nextptr) 1100 { 1101 int mmc; 1102 1103 /* Number of msi messages must be a power of 2 between 1 and 32 */ 1104 assert((msgnum & (msgnum - 1)) == 0 && msgnum >= 1 && msgnum <= 32); 1105 mmc = ffs(msgnum) - 1; 1106 1107 bzero(msicap, sizeof(struct msicap)); 1108 msicap->capid = PCIY_MSI; 1109 msicap->nextptr = nextptr; 1110 msicap->msgctrl = PCIM_MSICTRL_64BIT | (mmc << 1); 1111 } 1112 1113 int 1114 pci_emul_add_msicap(struct pci_devinst *pi, int msgnum) 1115 { 1116 struct msicap msicap; 1117 1118 pci_populate_msicap(&msicap, msgnum, 0); 1119 1120 return (pci_emul_add_capability(pi, (u_char *)&msicap, sizeof(msicap))); 1121 } 1122 1123 static void 1124 pci_populate_msixcap(struct msixcap *msixcap, int msgnum, int barnum, 1125 uint32_t msix_tab_size) 1126 { 1127 1128 assert(msix_tab_size % 4096 == 0); 1129 1130 bzero(msixcap, sizeof(struct msixcap)); 1131 msixcap->capid = PCIY_MSIX; 1132 1133 /* 1134 * Message Control Register, all fields set to 1135 * zero except for the Table Size. 1136 * Note: Table size N is encoded as N-1 1137 */ 1138 msixcap->msgctrl = msgnum - 1; 1139 1140 /* 1141 * MSI-X BAR setup: 1142 * - MSI-X table start at offset 0 1143 * - PBA table starts at a 4K aligned offset after the MSI-X table 1144 */ 1145 msixcap->table_info = barnum & PCIM_MSIX_BIR_MASK; 1146 msixcap->pba_info = msix_tab_size | (barnum & PCIM_MSIX_BIR_MASK); 1147 } 1148 1149 static void 1150 pci_msix_table_init(struct pci_devinst *pi, int table_entries) 1151 { 1152 int i, table_size; 1153 1154 assert(table_entries > 0); 1155 assert(table_entries <= MAX_MSIX_TABLE_ENTRIES); 1156 1157 table_size = table_entries * MSIX_TABLE_ENTRY_SIZE; 1158 pi->pi_msix.table = calloc(1, table_size); 1159 1160 /* set mask bit of vector control register */ 1161 for (i = 0; i < table_entries; i++) 1162 pi->pi_msix.table[i].vector_control |= PCIM_MSIX_VCTRL_MASK; 1163 } 1164 1165 int 1166 pci_emul_add_msixcap(struct pci_devinst *pi, int msgnum, int barnum) 1167 { 1168 uint32_t tab_size; 1169 struct msixcap msixcap; 1170 1171 assert(msgnum >= 1 && msgnum <= MAX_MSIX_TABLE_ENTRIES); 1172 assert(barnum >= 0 && barnum <= PCIR_MAX_BAR_0); 1173 1174 tab_size = msgnum * MSIX_TABLE_ENTRY_SIZE; 1175 1176 /* Align table size to nearest 4K */ 1177 tab_size = roundup2(tab_size, 4096); 1178 1179 pi->pi_msix.table_bar = barnum; 1180 pi->pi_msix.pba_bar = barnum; 1181 pi->pi_msix.table_offset = 0; 1182 pi->pi_msix.table_count = msgnum; 1183 pi->pi_msix.pba_offset = tab_size; 1184 pi->pi_msix.pba_size = PBA_SIZE(msgnum); 1185 1186 pci_msix_table_init(pi, msgnum); 1187 1188 pci_populate_msixcap(&msixcap, msgnum, barnum, tab_size); 1189 1190 /* allocate memory for MSI-X Table and PBA */ 1191 pci_emul_alloc_bar(pi, barnum, PCIBAR_MEM32, 1192 tab_size + pi->pi_msix.pba_size); 1193 1194 return (pci_emul_add_capability(pi, (u_char *)&msixcap, 1195 sizeof(msixcap))); 1196 } 1197 1198 static void 1199 msixcap_cfgwrite(struct pci_devinst *pi, int capoff, int offset, 1200 int bytes, uint32_t val) 1201 { 1202 uint16_t msgctrl, rwmask; 1203 int off; 1204 1205 off = offset - capoff; 1206 /* Message Control Register */ 1207 if (off == 2 && bytes == 2) { 1208 rwmask = PCIM_MSIXCTRL_MSIX_ENABLE | PCIM_MSIXCTRL_FUNCTION_MASK; 1209 msgctrl = pci_get_cfgdata16(pi, offset); 1210 msgctrl &= ~rwmask; 1211 msgctrl |= val & rwmask; 1212 val = msgctrl; 1213 1214 pi->pi_msix.enabled = val & PCIM_MSIXCTRL_MSIX_ENABLE; 1215 pi->pi_msix.function_mask = val & PCIM_MSIXCTRL_FUNCTION_MASK; 1216 pci_lintr_update(pi); 1217 } 1218 1219 CFGWRITE(pi, offset, val, bytes); 1220 } 1221 1222 static void 1223 msicap_cfgwrite(struct pci_devinst *pi, int capoff, int offset, 1224 int bytes, uint32_t val) 1225 { 1226 uint16_t msgctrl, rwmask, msgdata, mme; 1227 uint32_t addrlo; 1228 1229 /* 1230 * If guest is writing to the message control register make sure 1231 * we do not overwrite read-only fields. 1232 */ 1233 if ((offset - capoff) == 2 && bytes == 2) { 1234 rwmask = PCIM_MSICTRL_MME_MASK | PCIM_MSICTRL_MSI_ENABLE; 1235 msgctrl = pci_get_cfgdata16(pi, offset); 1236 msgctrl &= ~rwmask; 1237 msgctrl |= val & rwmask; 1238 val = msgctrl; 1239 } 1240 CFGWRITE(pi, offset, val, bytes); 1241 1242 msgctrl = pci_get_cfgdata16(pi, capoff + 2); 1243 addrlo = pci_get_cfgdata32(pi, capoff + 4); 1244 if (msgctrl & PCIM_MSICTRL_64BIT) 1245 msgdata = pci_get_cfgdata16(pi, capoff + 12); 1246 else 1247 msgdata = pci_get_cfgdata16(pi, capoff + 8); 1248 1249 mme = msgctrl & PCIM_MSICTRL_MME_MASK; 1250 pi->pi_msi.enabled = msgctrl & PCIM_MSICTRL_MSI_ENABLE ? 1 : 0; 1251 if (pi->pi_msi.enabled) { 1252 pi->pi_msi.addr = addrlo; 1253 pi->pi_msi.msg_data = msgdata; 1254 pi->pi_msi.maxmsgnum = 1 << (mme >> 4); 1255 } else { 1256 pi->pi_msi.maxmsgnum = 0; 1257 } 1258 pci_lintr_update(pi); 1259 } 1260 1261 static void 1262 pciecap_cfgwrite(struct pci_devinst *pi, int capoff __unused, int offset, 1263 int bytes, uint32_t val) 1264 { 1265 1266 /* XXX don't write to the readonly parts */ 1267 CFGWRITE(pi, offset, val, bytes); 1268 } 1269 1270 #define PCIECAP_VERSION 0x2 1271 int 1272 pci_emul_add_pciecap(struct pci_devinst *pi, int type) 1273 { 1274 int err; 1275 struct pciecap pciecap; 1276 1277 bzero(&pciecap, sizeof(pciecap)); 1278 1279 /* 1280 * Use the integrated endpoint type for endpoints on a root complex bus. 1281 * 1282 * NB: bhyve currently only supports a single PCI bus that is the root 1283 * complex bus, so all endpoints are integrated. 1284 */ 1285 if ((type == PCIEM_TYPE_ENDPOINT) && (pi->pi_bus == 0)) 1286 type = PCIEM_TYPE_ROOT_INT_EP; 1287 1288 pciecap.capid = PCIY_EXPRESS; 1289 pciecap.pcie_capabilities = PCIECAP_VERSION | type; 1290 if (type != PCIEM_TYPE_ROOT_INT_EP) { 1291 pciecap.link_capabilities = 0x411; /* gen1, x1 */ 1292 pciecap.link_status = 0x11; /* gen1, x1 */ 1293 } 1294 1295 err = pci_emul_add_capability(pi, (u_char *)&pciecap, sizeof(pciecap)); 1296 return (err); 1297 } 1298 1299 /* 1300 * This function assumes that 'coff' is in the capabilities region of the 1301 * config space. A capoff parameter of zero will force a search for the 1302 * offset and type. 1303 */ 1304 void 1305 pci_emul_capwrite(struct pci_devinst *pi, int offset, int bytes, uint32_t val, 1306 uint8_t capoff, int capid) 1307 { 1308 uint8_t nextoff; 1309 1310 /* Do not allow un-aligned writes */ 1311 if ((offset & (bytes - 1)) != 0) 1312 return; 1313 1314 if (capoff == 0) { 1315 /* Find the capability that we want to update */ 1316 capoff = CAP_START_OFFSET; 1317 while (1) { 1318 nextoff = pci_get_cfgdata8(pi, capoff + 1); 1319 if (nextoff == 0) 1320 break; 1321 if (offset >= capoff && offset < nextoff) 1322 break; 1323 1324 capoff = nextoff; 1325 } 1326 assert(offset >= capoff); 1327 capid = pci_get_cfgdata8(pi, capoff); 1328 } 1329 1330 /* 1331 * Capability ID and Next Capability Pointer are readonly. 1332 * However, some o/s's do 4-byte writes that include these. 1333 * For this case, trim the write back to 2 bytes and adjust 1334 * the data. 1335 */ 1336 if (offset == capoff || offset == capoff + 1) { 1337 if (offset == capoff && bytes == 4) { 1338 bytes = 2; 1339 offset += 2; 1340 val >>= 16; 1341 } else 1342 return; 1343 } 1344 1345 switch (capid) { 1346 case PCIY_MSI: 1347 msicap_cfgwrite(pi, capoff, offset, bytes, val); 1348 break; 1349 case PCIY_MSIX: 1350 msixcap_cfgwrite(pi, capoff, offset, bytes, val); 1351 break; 1352 case PCIY_EXPRESS: 1353 pciecap_cfgwrite(pi, capoff, offset, bytes, val); 1354 break; 1355 default: 1356 break; 1357 } 1358 } 1359 1360 static int 1361 pci_emul_iscap(struct pci_devinst *pi, int offset) 1362 { 1363 uint16_t sts; 1364 1365 sts = pci_get_cfgdata16(pi, PCIR_STATUS); 1366 if ((sts & PCIM_STATUS_CAPPRESENT) != 0) { 1367 if (offset >= CAP_START_OFFSET && offset <= pi->pi_capend) 1368 return (1); 1369 } 1370 return (0); 1371 } 1372 1373 static int 1374 pci_emul_fallback_handler(struct vcpu *vcpu __unused, int dir, 1375 uint64_t addr __unused, int size __unused, uint64_t *val, 1376 void *arg1 __unused, long arg2 __unused) 1377 { 1378 /* 1379 * Ignore writes; return 0xff's for reads. The mem read code 1380 * will take care of truncating to the correct size. 1381 */ 1382 if (dir == MEM_F_READ) { 1383 *val = 0xffffffffffffffff; 1384 } 1385 1386 return (0); 1387 } 1388 1389 static int 1390 pci_emul_ecfg_handler(struct vcpu *vcpu __unused, int dir, uint64_t addr, 1391 int bytes, uint64_t *val, void *arg1 __unused, long arg2 __unused) 1392 { 1393 int bus, slot, func, coff, in; 1394 1395 coff = addr & 0xfff; 1396 func = (addr >> 12) & 0x7; 1397 slot = (addr >> 15) & 0x1f; 1398 bus = (addr >> 20) & 0xff; 1399 in = (dir == MEM_F_READ); 1400 if (in) 1401 *val = ~0UL; 1402 pci_cfgrw(in, bus, slot, func, coff, bytes, (uint32_t *)val); 1403 return (0); 1404 } 1405 1406 uint64_t 1407 pci_ecfg_base(void) 1408 { 1409 1410 return (PCI_EMUL_ECFG_BASE); 1411 } 1412 1413 static int 1414 init_bootorder(void) 1415 { 1416 struct boot_device *device; 1417 FILE *fp; 1418 char *bootorder; 1419 size_t bootorder_len; 1420 1421 if (TAILQ_EMPTY(&boot_devices)) 1422 return (0); 1423 1424 fp = open_memstream(&bootorder, &bootorder_len); 1425 TAILQ_FOREACH(device, &boot_devices, boot_device_chain) { 1426 fprintf(fp, "/pci@i0cf8/pci@%d,%d\n", 1427 device->pdi->pi_slot, device->pdi->pi_func); 1428 } 1429 fclose(fp); 1430 1431 return (qemu_fwcfg_add_file("bootorder", bootorder_len, bootorder)); 1432 } 1433 1434 #define BUSIO_ROUNDUP 32 1435 #define BUSMEM32_ROUNDUP (1024 * 1024) 1436 #define BUSMEM64_ROUNDUP (512 * 1024 * 1024) 1437 1438 int 1439 init_pci(struct vmctx *ctx) 1440 { 1441 char node_name[sizeof("pci.XXX.XX.X")]; 1442 struct mem_range mr; 1443 struct pci_devemu *pde; 1444 struct businfo *bi; 1445 struct slotinfo *si; 1446 struct funcinfo *fi; 1447 nvlist_t *nvl; 1448 const char *emul; 1449 size_t lowmem; 1450 int bus, slot, func; 1451 int error; 1452 1453 if (vm_get_lowmem_limit(ctx) > PCI_EMUL_MEMBASE32) 1454 errx(EX_OSERR, "Invalid lowmem limit"); 1455 1456 pci_emul_iobase = PCI_EMUL_IOBASE; 1457 pci_emul_membase32 = PCI_EMUL_MEMBASE32; 1458 1459 pci_emul_membase64 = 4*GB + vm_get_highmem_size(ctx); 1460 pci_emul_membase64 = roundup2(pci_emul_membase64, PCI_EMUL_MEMSIZE64); 1461 pci_emul_memlim64 = pci_emul_membase64 + PCI_EMUL_MEMSIZE64; 1462 1463 TAILQ_INIT(&boot_devices); 1464 1465 for (bus = 0; bus < MAXBUSES; bus++) { 1466 snprintf(node_name, sizeof(node_name), "pci.%d", bus); 1467 nvl = find_config_node(node_name); 1468 if (nvl == NULL) 1469 continue; 1470 pci_businfo[bus] = calloc(1, sizeof(struct businfo)); 1471 bi = pci_businfo[bus]; 1472 1473 /* 1474 * Keep track of the i/o and memory resources allocated to 1475 * this bus. 1476 */ 1477 bi->iobase = pci_emul_iobase; 1478 bi->membase32 = pci_emul_membase32; 1479 bi->membase64 = pci_emul_membase64; 1480 1481 /* first run: init devices */ 1482 for (slot = 0; slot < MAXSLOTS; slot++) { 1483 si = &bi->slotinfo[slot]; 1484 for (func = 0; func < MAXFUNCS; func++) { 1485 fi = &si->si_funcs[func]; 1486 snprintf(node_name, sizeof(node_name), 1487 "pci.%d.%d.%d", bus, slot, func); 1488 nvl = find_config_node(node_name); 1489 if (nvl == NULL) 1490 continue; 1491 1492 fi->fi_config = nvl; 1493 emul = get_config_value_node(nvl, "device"); 1494 if (emul == NULL) { 1495 EPRINTLN("pci slot %d:%d:%d: missing " 1496 "\"device\" value", bus, slot, func); 1497 return (EINVAL); 1498 } 1499 pde = pci_emul_finddev(emul); 1500 if (pde == NULL) { 1501 EPRINTLN("pci slot %d:%d:%d: unknown " 1502 "device \"%s\"", bus, slot, func, 1503 emul); 1504 return (EINVAL); 1505 } 1506 if (pde->pe_alias != NULL) { 1507 EPRINTLN("pci slot %d:%d:%d: legacy " 1508 "device \"%s\", use \"%s\" instead", 1509 bus, slot, func, emul, 1510 pde->pe_alias); 1511 return (EINVAL); 1512 } 1513 fi->fi_pde = pde; 1514 error = pci_emul_init(ctx, pde, bus, slot, 1515 func, fi); 1516 if (error) 1517 return (error); 1518 } 1519 } 1520 1521 /* second run: assign BARs and free list */ 1522 struct pci_bar_allocation *bar; 1523 struct pci_bar_allocation *bar_tmp; 1524 TAILQ_FOREACH_SAFE(bar, &pci_bars, chain, bar_tmp) { 1525 pci_emul_assign_bar(bar->pdi, bar->idx, bar->type, 1526 bar->size); 1527 free(bar); 1528 } 1529 TAILQ_INIT(&pci_bars); 1530 1531 /* 1532 * Add some slop to the I/O and memory resources decoded by 1533 * this bus to give a guest some flexibility if it wants to 1534 * reprogram the BARs. 1535 */ 1536 pci_emul_iobase += BUSIO_ROUNDUP; 1537 pci_emul_iobase = roundup2(pci_emul_iobase, BUSIO_ROUNDUP); 1538 bi->iolimit = pci_emul_iobase; 1539 1540 pci_emul_membase32 += BUSMEM32_ROUNDUP; 1541 pci_emul_membase32 = roundup2(pci_emul_membase32, 1542 BUSMEM32_ROUNDUP); 1543 bi->memlimit32 = pci_emul_membase32; 1544 1545 pci_emul_membase64 += BUSMEM64_ROUNDUP; 1546 pci_emul_membase64 = roundup2(pci_emul_membase64, 1547 BUSMEM64_ROUNDUP); 1548 bi->memlimit64 = pci_emul_membase64; 1549 } 1550 1551 /* 1552 * PCI backends are initialized before routing INTx interrupts 1553 * so that LPC devices are able to reserve ISA IRQs before 1554 * routing PIRQ pins. 1555 */ 1556 for (bus = 0; bus < MAXBUSES; bus++) { 1557 if ((bi = pci_businfo[bus]) == NULL) 1558 continue; 1559 1560 for (slot = 0; slot < MAXSLOTS; slot++) { 1561 si = &bi->slotinfo[slot]; 1562 for (func = 0; func < MAXFUNCS; func++) { 1563 fi = &si->si_funcs[func]; 1564 if (fi->fi_devi == NULL) 1565 continue; 1566 pci_lintr_route(fi->fi_devi); 1567 } 1568 } 1569 } 1570 lpc_pirq_routed(); 1571 1572 if ((error = init_bootorder()) != 0) { 1573 warnx("%s: Unable to init bootorder", __func__); 1574 return (error); 1575 } 1576 1577 /* 1578 * The guest physical memory map looks like the following: 1579 * [0, lowmem) guest system memory 1580 * [lowmem, 0xC0000000) memory hole (may be absent) 1581 * [0xC0000000, 0xE0000000) PCI hole (32-bit BAR allocation) 1582 * [0xE0000000, 0xF0000000) PCI extended config window 1583 * [0xF0000000, 4GB) LAPIC, IOAPIC, HPET, firmware 1584 * [4GB, 4GB + highmem) 1585 */ 1586 1587 /* 1588 * Accesses to memory addresses that are not allocated to system 1589 * memory or PCI devices return 0xff's. 1590 */ 1591 lowmem = vm_get_lowmem_size(ctx); 1592 bzero(&mr, sizeof(struct mem_range)); 1593 mr.name = "PCI hole"; 1594 mr.flags = MEM_F_RW | MEM_F_IMMUTABLE; 1595 mr.base = lowmem; 1596 mr.size = (4ULL * 1024 * 1024 * 1024) - lowmem; 1597 mr.handler = pci_emul_fallback_handler; 1598 error = register_mem_fallback(&mr); 1599 assert(error == 0); 1600 1601 /* PCI extended config space */ 1602 bzero(&mr, sizeof(struct mem_range)); 1603 mr.name = "PCI ECFG"; 1604 mr.flags = MEM_F_RW | MEM_F_IMMUTABLE; 1605 mr.base = PCI_EMUL_ECFG_BASE; 1606 mr.size = PCI_EMUL_ECFG_SIZE; 1607 mr.handler = pci_emul_ecfg_handler; 1608 error = register_mem(&mr); 1609 assert(error == 0); 1610 1611 return (0); 1612 } 1613 1614 static void 1615 pci_apic_prt_entry(int bus __unused, int slot, int pin, int pirq_pin __unused, 1616 int ioapic_irq, void *arg __unused) 1617 { 1618 1619 dsdt_line(" Package ()"); 1620 dsdt_line(" {"); 1621 dsdt_line(" 0x%X,", slot << 16 | 0xffff); 1622 dsdt_line(" 0x%02X,", pin - 1); 1623 dsdt_line(" Zero,"); 1624 dsdt_line(" 0x%X", ioapic_irq); 1625 dsdt_line(" },"); 1626 } 1627 1628 static void 1629 pci_pirq_prt_entry(int bus __unused, int slot, int pin, int pirq_pin, 1630 int ioapic_irq __unused, void *arg __unused) 1631 { 1632 char *name; 1633 1634 name = lpc_pirq_name(pirq_pin); 1635 if (name == NULL) 1636 return; 1637 dsdt_line(" Package ()"); 1638 dsdt_line(" {"); 1639 dsdt_line(" 0x%X,", slot << 16 | 0xffff); 1640 dsdt_line(" 0x%02X,", pin - 1); 1641 dsdt_line(" %s,", name); 1642 dsdt_line(" 0x00"); 1643 dsdt_line(" },"); 1644 free(name); 1645 } 1646 1647 /* 1648 * A bhyve virtual machine has a flat PCI hierarchy with a root port 1649 * corresponding to each PCI bus. 1650 */ 1651 static void 1652 pci_bus_write_dsdt(int bus) 1653 { 1654 struct businfo *bi; 1655 struct slotinfo *si; 1656 struct pci_devinst *pi; 1657 int count, func, slot; 1658 1659 /* 1660 * If there are no devices on this 'bus' then just return. 1661 */ 1662 if ((bi = pci_businfo[bus]) == NULL) { 1663 /* 1664 * Bus 0 is special because it decodes the I/O ports used 1665 * for PCI config space access even if there are no devices 1666 * on it. 1667 */ 1668 if (bus != 0) 1669 return; 1670 } 1671 1672 dsdt_line(" Device (PC%02X)", bus); 1673 dsdt_line(" {"); 1674 dsdt_line(" Name (_HID, EisaId (\"PNP0A03\"))"); 1675 1676 dsdt_line(" Method (_BBN, 0, NotSerialized)"); 1677 dsdt_line(" {"); 1678 dsdt_line(" Return (0x%08X)", bus); 1679 dsdt_line(" }"); 1680 dsdt_line(" Name (_CRS, ResourceTemplate ()"); 1681 dsdt_line(" {"); 1682 dsdt_line(" WordBusNumber (ResourceProducer, MinFixed, " 1683 "MaxFixed, PosDecode,"); 1684 dsdt_line(" 0x0000, // Granularity"); 1685 dsdt_line(" 0x%04X, // Range Minimum", bus); 1686 dsdt_line(" 0x%04X, // Range Maximum", bus); 1687 dsdt_line(" 0x0000, // Translation Offset"); 1688 dsdt_line(" 0x0001, // Length"); 1689 dsdt_line(" ,, )"); 1690 1691 if (bus == 0) { 1692 dsdt_indent(3); 1693 dsdt_fixed_ioport(0xCF8, 8); 1694 dsdt_unindent(3); 1695 1696 dsdt_line(" WordIO (ResourceProducer, MinFixed, MaxFixed, " 1697 "PosDecode, EntireRange,"); 1698 dsdt_line(" 0x0000, // Granularity"); 1699 dsdt_line(" 0x0000, // Range Minimum"); 1700 dsdt_line(" 0x0CF7, // Range Maximum"); 1701 dsdt_line(" 0x0000, // Translation Offset"); 1702 dsdt_line(" 0x0CF8, // Length"); 1703 dsdt_line(" ,, , TypeStatic)"); 1704 1705 dsdt_line(" WordIO (ResourceProducer, MinFixed, MaxFixed, " 1706 "PosDecode, EntireRange,"); 1707 dsdt_line(" 0x0000, // Granularity"); 1708 dsdt_line(" 0x0D00, // Range Minimum"); 1709 dsdt_line(" 0x%04X, // Range Maximum", 1710 PCI_EMUL_IOBASE - 1); 1711 dsdt_line(" 0x0000, // Translation Offset"); 1712 dsdt_line(" 0x%04X, // Length", 1713 PCI_EMUL_IOBASE - 0x0D00); 1714 dsdt_line(" ,, , TypeStatic)"); 1715 1716 if (bi == NULL) { 1717 dsdt_line(" })"); 1718 goto done; 1719 } 1720 } 1721 assert(bi != NULL); 1722 1723 /* i/o window */ 1724 dsdt_line(" WordIO (ResourceProducer, MinFixed, MaxFixed, " 1725 "PosDecode, EntireRange,"); 1726 dsdt_line(" 0x0000, // Granularity"); 1727 dsdt_line(" 0x%04X, // Range Minimum", bi->iobase); 1728 dsdt_line(" 0x%04X, // Range Maximum", 1729 bi->iolimit - 1); 1730 dsdt_line(" 0x0000, // Translation Offset"); 1731 dsdt_line(" 0x%04X, // Length", 1732 bi->iolimit - bi->iobase); 1733 dsdt_line(" ,, , TypeStatic)"); 1734 1735 /* mmio window (32-bit) */ 1736 dsdt_line(" DWordMemory (ResourceProducer, PosDecode, " 1737 "MinFixed, MaxFixed, NonCacheable, ReadWrite,"); 1738 dsdt_line(" 0x00000000, // Granularity"); 1739 dsdt_line(" 0x%08X, // Range Minimum\n", bi->membase32); 1740 dsdt_line(" 0x%08X, // Range Maximum\n", 1741 bi->memlimit32 - 1); 1742 dsdt_line(" 0x00000000, // Translation Offset"); 1743 dsdt_line(" 0x%08X, // Length\n", 1744 bi->memlimit32 - bi->membase32); 1745 dsdt_line(" ,, , AddressRangeMemory, TypeStatic)"); 1746 1747 /* mmio window (64-bit) */ 1748 dsdt_line(" QWordMemory (ResourceProducer, PosDecode, " 1749 "MinFixed, MaxFixed, NonCacheable, ReadWrite,"); 1750 dsdt_line(" 0x0000000000000000, // Granularity"); 1751 dsdt_line(" 0x%016lX, // Range Minimum\n", bi->membase64); 1752 dsdt_line(" 0x%016lX, // Range Maximum\n", 1753 bi->memlimit64 - 1); 1754 dsdt_line(" 0x0000000000000000, // Translation Offset"); 1755 dsdt_line(" 0x%016lX, // Length\n", 1756 bi->memlimit64 - bi->membase64); 1757 dsdt_line(" ,, , AddressRangeMemory, TypeStatic)"); 1758 dsdt_line(" })"); 1759 1760 count = pci_count_lintr(bus); 1761 if (count != 0) { 1762 dsdt_indent(2); 1763 dsdt_line("Name (PPRT, Package ()"); 1764 dsdt_line("{"); 1765 pci_walk_lintr(bus, pci_pirq_prt_entry, NULL); 1766 dsdt_line("})"); 1767 dsdt_line("Name (APRT, Package ()"); 1768 dsdt_line("{"); 1769 pci_walk_lintr(bus, pci_apic_prt_entry, NULL); 1770 dsdt_line("})"); 1771 dsdt_line("Method (_PRT, 0, NotSerialized)"); 1772 dsdt_line("{"); 1773 dsdt_line(" If (PICM)"); 1774 dsdt_line(" {"); 1775 dsdt_line(" Return (APRT)"); 1776 dsdt_line(" }"); 1777 dsdt_line(" Else"); 1778 dsdt_line(" {"); 1779 dsdt_line(" Return (PPRT)"); 1780 dsdt_line(" }"); 1781 dsdt_line("}"); 1782 dsdt_unindent(2); 1783 } 1784 1785 dsdt_indent(2); 1786 for (slot = 0; slot < MAXSLOTS; slot++) { 1787 si = &bi->slotinfo[slot]; 1788 for (func = 0; func < MAXFUNCS; func++) { 1789 pi = si->si_funcs[func].fi_devi; 1790 if (pi != NULL && pi->pi_d->pe_write_dsdt != NULL) 1791 pi->pi_d->pe_write_dsdt(pi); 1792 } 1793 } 1794 dsdt_unindent(2); 1795 done: 1796 dsdt_line(" }"); 1797 } 1798 1799 void 1800 pci_write_dsdt(void) 1801 { 1802 int bus; 1803 1804 dsdt_indent(1); 1805 dsdt_line("Name (PICM, 0x00)"); 1806 dsdt_line("Method (_PIC, 1, NotSerialized)"); 1807 dsdt_line("{"); 1808 dsdt_line(" Store (Arg0, PICM)"); 1809 dsdt_line("}"); 1810 dsdt_line(""); 1811 dsdt_line("Scope (_SB)"); 1812 dsdt_line("{"); 1813 for (bus = 0; bus < MAXBUSES; bus++) 1814 pci_bus_write_dsdt(bus); 1815 dsdt_line("}"); 1816 dsdt_unindent(1); 1817 } 1818 1819 int 1820 pci_bus_configured(int bus) 1821 { 1822 assert(bus >= 0 && bus < MAXBUSES); 1823 return (pci_businfo[bus] != NULL); 1824 } 1825 1826 int 1827 pci_msi_enabled(struct pci_devinst *pi) 1828 { 1829 return (pi->pi_msi.enabled); 1830 } 1831 1832 int 1833 pci_msi_maxmsgnum(struct pci_devinst *pi) 1834 { 1835 if (pi->pi_msi.enabled) 1836 return (pi->pi_msi.maxmsgnum); 1837 else 1838 return (0); 1839 } 1840 1841 int 1842 pci_msix_enabled(struct pci_devinst *pi) 1843 { 1844 1845 return (pi->pi_msix.enabled && !pi->pi_msi.enabled); 1846 } 1847 1848 void 1849 pci_generate_msix(struct pci_devinst *pi, int index) 1850 { 1851 struct msix_table_entry *mte; 1852 1853 if (!pci_msix_enabled(pi)) 1854 return; 1855 1856 if (pi->pi_msix.function_mask) 1857 return; 1858 1859 if (index >= pi->pi_msix.table_count) 1860 return; 1861 1862 mte = &pi->pi_msix.table[index]; 1863 if ((mte->vector_control & PCIM_MSIX_VCTRL_MASK) == 0) { 1864 /* XXX Set PBA bit if interrupt is disabled */ 1865 vm_lapic_msi(pi->pi_vmctx, mte->addr, mte->msg_data); 1866 } 1867 } 1868 1869 void 1870 pci_generate_msi(struct pci_devinst *pi, int index) 1871 { 1872 1873 if (pci_msi_enabled(pi) && index < pci_msi_maxmsgnum(pi)) { 1874 vm_lapic_msi(pi->pi_vmctx, pi->pi_msi.addr, 1875 pi->pi_msi.msg_data + index); 1876 } 1877 } 1878 1879 static bool 1880 pci_lintr_permitted(struct pci_devinst *pi) 1881 { 1882 uint16_t cmd; 1883 1884 cmd = pci_get_cfgdata16(pi, PCIR_COMMAND); 1885 return (!(pi->pi_msi.enabled || pi->pi_msix.enabled || 1886 (cmd & PCIM_CMD_INTxDIS))); 1887 } 1888 1889 void 1890 pci_lintr_request(struct pci_devinst *pi) 1891 { 1892 struct businfo *bi; 1893 struct slotinfo *si; 1894 int bestpin, bestcount, pin; 1895 1896 bi = pci_businfo[pi->pi_bus]; 1897 assert(bi != NULL); 1898 1899 /* 1900 * Just allocate a pin from our slot. The pin will be 1901 * assigned IRQs later when interrupts are routed. 1902 */ 1903 si = &bi->slotinfo[pi->pi_slot]; 1904 bestpin = 0; 1905 bestcount = si->si_intpins[0].ii_count; 1906 for (pin = 1; pin < 4; pin++) { 1907 if (si->si_intpins[pin].ii_count < bestcount) { 1908 bestpin = pin; 1909 bestcount = si->si_intpins[pin].ii_count; 1910 } 1911 } 1912 1913 si->si_intpins[bestpin].ii_count++; 1914 pi->pi_lintr.pin = bestpin + 1; 1915 pci_set_cfgdata8(pi, PCIR_INTPIN, bestpin + 1); 1916 } 1917 1918 static void 1919 pci_lintr_route(struct pci_devinst *pi) 1920 { 1921 struct businfo *bi; 1922 struct intxinfo *ii; 1923 1924 if (pi->pi_lintr.pin == 0) 1925 return; 1926 1927 bi = pci_businfo[pi->pi_bus]; 1928 assert(bi != NULL); 1929 ii = &bi->slotinfo[pi->pi_slot].si_intpins[pi->pi_lintr.pin - 1]; 1930 1931 /* 1932 * Attempt to allocate an I/O APIC pin for this intpin if one 1933 * is not yet assigned. 1934 */ 1935 if (ii->ii_ioapic_irq == 0) 1936 ii->ii_ioapic_irq = ioapic_pci_alloc_irq(pi); 1937 assert(ii->ii_ioapic_irq > 0); 1938 1939 /* 1940 * Attempt to allocate a PIRQ pin for this intpin if one is 1941 * not yet assigned. 1942 */ 1943 if (ii->ii_pirq_pin == 0) 1944 ii->ii_pirq_pin = pirq_alloc_pin(pi); 1945 assert(ii->ii_pirq_pin > 0); 1946 1947 pi->pi_lintr.ioapic_irq = ii->ii_ioapic_irq; 1948 pi->pi_lintr.pirq_pin = ii->ii_pirq_pin; 1949 pci_set_cfgdata8(pi, PCIR_INTLINE, pirq_irq(ii->ii_pirq_pin)); 1950 } 1951 1952 void 1953 pci_lintr_assert(struct pci_devinst *pi) 1954 { 1955 1956 assert(pi->pi_lintr.pin > 0); 1957 1958 pthread_mutex_lock(&pi->pi_lintr.lock); 1959 if (pi->pi_lintr.state == IDLE) { 1960 if (pci_lintr_permitted(pi)) { 1961 pi->pi_lintr.state = ASSERTED; 1962 pci_irq_assert(pi); 1963 } else 1964 pi->pi_lintr.state = PENDING; 1965 } 1966 pthread_mutex_unlock(&pi->pi_lintr.lock); 1967 } 1968 1969 void 1970 pci_lintr_deassert(struct pci_devinst *pi) 1971 { 1972 1973 assert(pi->pi_lintr.pin > 0); 1974 1975 pthread_mutex_lock(&pi->pi_lintr.lock); 1976 if (pi->pi_lintr.state == ASSERTED) { 1977 pi->pi_lintr.state = IDLE; 1978 pci_irq_deassert(pi); 1979 } else if (pi->pi_lintr.state == PENDING) 1980 pi->pi_lintr.state = IDLE; 1981 pthread_mutex_unlock(&pi->pi_lintr.lock); 1982 } 1983 1984 static void 1985 pci_lintr_update(struct pci_devinst *pi) 1986 { 1987 1988 pthread_mutex_lock(&pi->pi_lintr.lock); 1989 if (pi->pi_lintr.state == ASSERTED && !pci_lintr_permitted(pi)) { 1990 pci_irq_deassert(pi); 1991 pi->pi_lintr.state = PENDING; 1992 } else if (pi->pi_lintr.state == PENDING && pci_lintr_permitted(pi)) { 1993 pi->pi_lintr.state = ASSERTED; 1994 pci_irq_assert(pi); 1995 } 1996 pthread_mutex_unlock(&pi->pi_lintr.lock); 1997 } 1998 1999 int 2000 pci_count_lintr(int bus) 2001 { 2002 int count, slot, pin; 2003 struct slotinfo *slotinfo; 2004 2005 count = 0; 2006 if (pci_businfo[bus] != NULL) { 2007 for (slot = 0; slot < MAXSLOTS; slot++) { 2008 slotinfo = &pci_businfo[bus]->slotinfo[slot]; 2009 for (pin = 0; pin < 4; pin++) { 2010 if (slotinfo->si_intpins[pin].ii_count != 0) 2011 count++; 2012 } 2013 } 2014 } 2015 return (count); 2016 } 2017 2018 void 2019 pci_walk_lintr(int bus, pci_lintr_cb cb, void *arg) 2020 { 2021 struct businfo *bi; 2022 struct slotinfo *si; 2023 struct intxinfo *ii; 2024 int slot, pin; 2025 2026 if ((bi = pci_businfo[bus]) == NULL) 2027 return; 2028 2029 for (slot = 0; slot < MAXSLOTS; slot++) { 2030 si = &bi->slotinfo[slot]; 2031 for (pin = 0; pin < 4; pin++) { 2032 ii = &si->si_intpins[pin]; 2033 if (ii->ii_count != 0) 2034 cb(bus, slot, pin + 1, ii->ii_pirq_pin, 2035 ii->ii_ioapic_irq, arg); 2036 } 2037 } 2038 } 2039 2040 /* 2041 * Return 1 if the emulated device in 'slot' is a multi-function device. 2042 * Return 0 otherwise. 2043 */ 2044 static int 2045 pci_emul_is_mfdev(int bus, int slot) 2046 { 2047 struct businfo *bi; 2048 struct slotinfo *si; 2049 int f, numfuncs; 2050 2051 numfuncs = 0; 2052 if ((bi = pci_businfo[bus]) != NULL) { 2053 si = &bi->slotinfo[slot]; 2054 for (f = 0; f < MAXFUNCS; f++) { 2055 if (si->si_funcs[f].fi_devi != NULL) { 2056 numfuncs++; 2057 } 2058 } 2059 } 2060 return (numfuncs > 1); 2061 } 2062 2063 /* 2064 * Ensure that the PCIM_MFDEV bit is properly set (or unset) depending on 2065 * whether or not is a multi-function being emulated in the pci 'slot'. 2066 */ 2067 static void 2068 pci_emul_hdrtype_fixup(int bus, int slot, int off, int bytes, uint32_t *rv) 2069 { 2070 int mfdev; 2071 2072 if (off <= PCIR_HDRTYPE && off + bytes > PCIR_HDRTYPE) { 2073 mfdev = pci_emul_is_mfdev(bus, slot); 2074 switch (bytes) { 2075 case 1: 2076 case 2: 2077 *rv &= ~PCIM_MFDEV; 2078 if (mfdev) { 2079 *rv |= PCIM_MFDEV; 2080 } 2081 break; 2082 case 4: 2083 *rv &= ~(PCIM_MFDEV << 16); 2084 if (mfdev) { 2085 *rv |= (PCIM_MFDEV << 16); 2086 } 2087 break; 2088 } 2089 } 2090 } 2091 2092 /* 2093 * Update device state in response to changes to the PCI command 2094 * register. 2095 */ 2096 void 2097 pci_emul_cmd_changed(struct pci_devinst *pi, uint16_t old) 2098 { 2099 int i; 2100 uint16_t changed, new; 2101 2102 new = pci_get_cfgdata16(pi, PCIR_COMMAND); 2103 changed = old ^ new; 2104 2105 /* 2106 * If the MMIO or I/O address space decoding has changed then 2107 * register/unregister all BARs that decode that address space. 2108 */ 2109 for (i = 0; i <= PCI_BARMAX_WITH_ROM; i++) { 2110 switch (pi->pi_bar[i].type) { 2111 case PCIBAR_NONE: 2112 case PCIBAR_MEMHI64: 2113 break; 2114 case PCIBAR_IO: 2115 /* I/O address space decoding changed? */ 2116 if (changed & PCIM_CMD_PORTEN) { 2117 if (new & PCIM_CMD_PORTEN) 2118 register_bar(pi, i); 2119 else 2120 unregister_bar(pi, i); 2121 } 2122 break; 2123 case PCIBAR_ROM: 2124 /* skip (un-)register of ROM if it disabled */ 2125 if (!romen(pi)) 2126 break; 2127 /* fallthrough */ 2128 case PCIBAR_MEM32: 2129 case PCIBAR_MEM64: 2130 /* MMIO address space decoding changed? */ 2131 if (changed & PCIM_CMD_MEMEN) { 2132 if (new & PCIM_CMD_MEMEN) 2133 register_bar(pi, i); 2134 else 2135 unregister_bar(pi, i); 2136 } 2137 break; 2138 default: 2139 assert(0); 2140 } 2141 } 2142 2143 /* 2144 * If INTx has been unmasked and is pending, assert the 2145 * interrupt. 2146 */ 2147 pci_lintr_update(pi); 2148 } 2149 2150 static void 2151 pci_emul_cmdsts_write(struct pci_devinst *pi, int coff, uint32_t new, int bytes) 2152 { 2153 int rshift; 2154 uint32_t cmd, old, readonly; 2155 2156 cmd = pci_get_cfgdata16(pi, PCIR_COMMAND); /* stash old value */ 2157 2158 /* 2159 * From PCI Local Bus Specification 3.0 sections 6.2.2 and 6.2.3. 2160 * 2161 * XXX Bits 8, 11, 12, 13, 14 and 15 in the status register are 2162 * 'write 1 to clear'. However these bits are not set to '1' by 2163 * any device emulation so it is simpler to treat them as readonly. 2164 */ 2165 rshift = (coff & 0x3) * 8; 2166 readonly = 0xFFFFF880 >> rshift; 2167 2168 old = CFGREAD(pi, coff, bytes); 2169 new &= ~readonly; 2170 new |= (old & readonly); 2171 CFGWRITE(pi, coff, new, bytes); /* update config */ 2172 2173 pci_emul_cmd_changed(pi, cmd); 2174 } 2175 2176 static void 2177 pci_cfgrw(int in, int bus, int slot, int func, int coff, int bytes, 2178 uint32_t *eax) 2179 { 2180 struct businfo *bi; 2181 struct slotinfo *si; 2182 struct pci_devinst *pi; 2183 struct pci_devemu *pe; 2184 int idx, needcfg; 2185 uint64_t addr, bar, mask; 2186 2187 if ((bi = pci_businfo[bus]) != NULL) { 2188 si = &bi->slotinfo[slot]; 2189 pi = si->si_funcs[func].fi_devi; 2190 } else 2191 pi = NULL; 2192 2193 /* 2194 * Just return if there is no device at this slot:func or if the 2195 * the guest is doing an un-aligned access. 2196 */ 2197 if (pi == NULL || (bytes != 1 && bytes != 2 && bytes != 4) || 2198 (coff & (bytes - 1)) != 0) { 2199 if (in) 2200 *eax = 0xffffffff; 2201 return; 2202 } 2203 2204 /* 2205 * Ignore all writes beyond the standard config space and return all 2206 * ones on reads. 2207 */ 2208 if (coff >= PCI_REGMAX + 1) { 2209 if (in) { 2210 *eax = 0xffffffff; 2211 /* 2212 * Extended capabilities begin at offset 256 in config 2213 * space. Absence of extended capabilities is signaled 2214 * with all 0s in the extended capability header at 2215 * offset 256. 2216 */ 2217 if (coff <= PCI_REGMAX + 4) 2218 *eax = 0x00000000; 2219 } 2220 return; 2221 } 2222 2223 pe = pi->pi_d; 2224 2225 /* 2226 * Config read 2227 */ 2228 if (in) { 2229 /* Let the device emulation override the default handler */ 2230 if (pe->pe_cfgread != NULL) { 2231 needcfg = pe->pe_cfgread(pi, coff, bytes, eax); 2232 } else { 2233 needcfg = 1; 2234 } 2235 2236 if (needcfg) 2237 *eax = CFGREAD(pi, coff, bytes); 2238 2239 pci_emul_hdrtype_fixup(bus, slot, coff, bytes, eax); 2240 } else { 2241 /* Let the device emulation override the default handler */ 2242 if (pe->pe_cfgwrite != NULL && 2243 (*pe->pe_cfgwrite)(pi, coff, bytes, *eax) == 0) 2244 return; 2245 2246 /* 2247 * Special handling for write to BAR and ROM registers 2248 */ 2249 if (is_pcir_bar(coff) || is_pcir_bios(coff)) { 2250 /* 2251 * Ignore writes to BAR registers that are not 2252 * 4-byte aligned. 2253 */ 2254 if (bytes != 4 || (coff & 0x3) != 0) 2255 return; 2256 2257 if (is_pcir_bar(coff)) { 2258 idx = (coff - PCIR_BAR(0)) / 4; 2259 } else if (is_pcir_bios(coff)) { 2260 idx = PCI_ROM_IDX; 2261 } else { 2262 errx(4, "%s: invalid BAR offset %d", __func__, 2263 coff); 2264 } 2265 2266 mask = ~(pi->pi_bar[idx].size - 1); 2267 switch (pi->pi_bar[idx].type) { 2268 case PCIBAR_NONE: 2269 pi->pi_bar[idx].addr = bar = 0; 2270 break; 2271 case PCIBAR_IO: 2272 addr = *eax & mask; 2273 addr &= 0xffff; 2274 bar = addr | pi->pi_bar[idx].lobits; 2275 /* 2276 * Register the new BAR value for interception 2277 */ 2278 if (addr != pi->pi_bar[idx].addr) { 2279 update_bar_address(pi, addr, idx, 2280 PCIBAR_IO); 2281 } 2282 break; 2283 case PCIBAR_MEM32: 2284 addr = bar = *eax & mask; 2285 bar |= pi->pi_bar[idx].lobits; 2286 if (addr != pi->pi_bar[idx].addr) { 2287 update_bar_address(pi, addr, idx, 2288 PCIBAR_MEM32); 2289 } 2290 break; 2291 case PCIBAR_MEM64: 2292 addr = bar = *eax & mask; 2293 bar |= pi->pi_bar[idx].lobits; 2294 if (addr != (uint32_t)pi->pi_bar[idx].addr) { 2295 update_bar_address(pi, addr, idx, 2296 PCIBAR_MEM64); 2297 } 2298 break; 2299 case PCIBAR_MEMHI64: 2300 mask = ~(pi->pi_bar[idx - 1].size - 1); 2301 addr = ((uint64_t)*eax << 32) & mask; 2302 bar = addr >> 32; 2303 if (bar != pi->pi_bar[idx - 1].addr >> 32) { 2304 update_bar_address(pi, addr, idx - 1, 2305 PCIBAR_MEMHI64); 2306 } 2307 break; 2308 case PCIBAR_ROM: 2309 addr = bar = *eax & mask; 2310 if (memen(pi) && romen(pi)) { 2311 unregister_bar(pi, idx); 2312 } 2313 pi->pi_bar[idx].addr = addr; 2314 pi->pi_bar[idx].lobits = *eax & 2315 PCIM_BIOS_ENABLE; 2316 /* romen could have changed it value */ 2317 if (memen(pi) && romen(pi)) { 2318 register_bar(pi, idx); 2319 } 2320 bar |= pi->pi_bar[idx].lobits; 2321 break; 2322 default: 2323 assert(0); 2324 } 2325 pci_set_cfgdata32(pi, coff, bar); 2326 2327 } else if (pci_emul_iscap(pi, coff)) { 2328 pci_emul_capwrite(pi, coff, bytes, *eax, 0, 0); 2329 } else if (coff >= PCIR_COMMAND && coff < PCIR_REVID) { 2330 pci_emul_cmdsts_write(pi, coff, *eax, bytes); 2331 } else { 2332 CFGWRITE(pi, coff, *eax, bytes); 2333 } 2334 } 2335 } 2336 2337 static int cfgenable, cfgbus, cfgslot, cfgfunc, cfgoff; 2338 2339 static int 2340 pci_emul_cfgaddr(struct vmctx *ctx __unused, int in, 2341 int port __unused, int bytes, uint32_t *eax, void *arg __unused) 2342 { 2343 uint32_t x; 2344 2345 if (bytes != 4) { 2346 if (in) 2347 *eax = (bytes == 2) ? 0xffff : 0xff; 2348 return (0); 2349 } 2350 2351 if (in) { 2352 x = (cfgbus << 16) | (cfgslot << 11) | (cfgfunc << 8) | cfgoff; 2353 if (cfgenable) 2354 x |= CONF1_ENABLE; 2355 *eax = x; 2356 } else { 2357 x = *eax; 2358 cfgenable = (x & CONF1_ENABLE) == CONF1_ENABLE; 2359 cfgoff = (x & PCI_REGMAX) & ~0x03; 2360 cfgfunc = (x >> 8) & PCI_FUNCMAX; 2361 cfgslot = (x >> 11) & PCI_SLOTMAX; 2362 cfgbus = (x >> 16) & PCI_BUSMAX; 2363 } 2364 2365 return (0); 2366 } 2367 INOUT_PORT(pci_cfgaddr, CONF1_ADDR_PORT, IOPORT_F_INOUT, pci_emul_cfgaddr); 2368 2369 static int 2370 pci_emul_cfgdata(struct vmctx *ctx __unused, int in, int port, 2371 int bytes, uint32_t *eax, void *arg __unused) 2372 { 2373 int coff; 2374 2375 assert(bytes == 1 || bytes == 2 || bytes == 4); 2376 2377 coff = cfgoff + (port - CONF1_DATA_PORT); 2378 if (cfgenable) { 2379 pci_cfgrw(in, cfgbus, cfgslot, cfgfunc, coff, bytes, eax); 2380 } else { 2381 /* Ignore accesses to cfgdata if not enabled by cfgaddr */ 2382 if (in) 2383 *eax = 0xffffffff; 2384 } 2385 return (0); 2386 } 2387 2388 INOUT_PORT(pci_cfgdata, CONF1_DATA_PORT+0, IOPORT_F_INOUT, pci_emul_cfgdata); 2389 INOUT_PORT(pci_cfgdata, CONF1_DATA_PORT+1, IOPORT_F_INOUT, pci_emul_cfgdata); 2390 INOUT_PORT(pci_cfgdata, CONF1_DATA_PORT+2, IOPORT_F_INOUT, pci_emul_cfgdata); 2391 INOUT_PORT(pci_cfgdata, CONF1_DATA_PORT+3, IOPORT_F_INOUT, pci_emul_cfgdata); 2392 2393 #ifdef BHYVE_SNAPSHOT 2394 /* 2395 * Saves/restores PCI device emulated state. Returns 0 on success. 2396 */ 2397 static int 2398 pci_snapshot_pci_dev(struct vm_snapshot_meta *meta) 2399 { 2400 struct pci_devinst *pi; 2401 int i; 2402 int ret; 2403 2404 pi = meta->dev_data; 2405 2406 SNAPSHOT_VAR_OR_LEAVE(pi->pi_msi.enabled, meta, ret, done); 2407 SNAPSHOT_VAR_OR_LEAVE(pi->pi_msi.addr, meta, ret, done); 2408 SNAPSHOT_VAR_OR_LEAVE(pi->pi_msi.msg_data, meta, ret, done); 2409 SNAPSHOT_VAR_OR_LEAVE(pi->pi_msi.maxmsgnum, meta, ret, done); 2410 2411 SNAPSHOT_VAR_OR_LEAVE(pi->pi_msix.enabled, meta, ret, done); 2412 SNAPSHOT_VAR_OR_LEAVE(pi->pi_msix.table_bar, meta, ret, done); 2413 SNAPSHOT_VAR_OR_LEAVE(pi->pi_msix.pba_bar, meta, ret, done); 2414 SNAPSHOT_VAR_OR_LEAVE(pi->pi_msix.table_offset, meta, ret, done); 2415 SNAPSHOT_VAR_OR_LEAVE(pi->pi_msix.table_count, meta, ret, done); 2416 SNAPSHOT_VAR_OR_LEAVE(pi->pi_msix.pba_offset, meta, ret, done); 2417 SNAPSHOT_VAR_OR_LEAVE(pi->pi_msix.pba_size, meta, ret, done); 2418 SNAPSHOT_VAR_OR_LEAVE(pi->pi_msix.function_mask, meta, ret, done); 2419 2420 SNAPSHOT_BUF_OR_LEAVE(pi->pi_cfgdata, sizeof(pi->pi_cfgdata), 2421 meta, ret, done); 2422 2423 for (i = 0; i < (int)nitems(pi->pi_bar); i++) { 2424 SNAPSHOT_VAR_OR_LEAVE(pi->pi_bar[i].type, meta, ret, done); 2425 SNAPSHOT_VAR_OR_LEAVE(pi->pi_bar[i].size, meta, ret, done); 2426 SNAPSHOT_VAR_OR_LEAVE(pi->pi_bar[i].addr, meta, ret, done); 2427 } 2428 2429 /* Restore MSI-X table. */ 2430 for (i = 0; i < pi->pi_msix.table_count; i++) { 2431 SNAPSHOT_VAR_OR_LEAVE(pi->pi_msix.table[i].addr, 2432 meta, ret, done); 2433 SNAPSHOT_VAR_OR_LEAVE(pi->pi_msix.table[i].msg_data, 2434 meta, ret, done); 2435 SNAPSHOT_VAR_OR_LEAVE(pi->pi_msix.table[i].vector_control, 2436 meta, ret, done); 2437 } 2438 2439 done: 2440 return (ret); 2441 } 2442 2443 int 2444 pci_snapshot(struct vm_snapshot_meta *meta) 2445 { 2446 struct pci_devemu *pde; 2447 struct pci_devinst *pdi; 2448 int ret; 2449 2450 assert(meta->dev_name != NULL); 2451 2452 pdi = meta->dev_data; 2453 pde = pdi->pi_d; 2454 2455 if (pde->pe_snapshot == NULL) 2456 return (ENOTSUP); 2457 2458 ret = pci_snapshot_pci_dev(meta); 2459 if (ret == 0) 2460 ret = (*pde->pe_snapshot)(meta); 2461 2462 return (ret); 2463 } 2464 2465 int 2466 pci_pause(struct pci_devinst *pdi) 2467 { 2468 struct pci_devemu *pde = pdi->pi_d; 2469 2470 if (pde->pe_pause == NULL) { 2471 /* The pause/resume functionality is optional. */ 2472 return (0); 2473 } 2474 2475 return (*pde->pe_pause)(pdi); 2476 } 2477 2478 int 2479 pci_resume(struct pci_devinst *pdi) 2480 { 2481 struct pci_devemu *pde = pdi->pi_d; 2482 2483 if (pde->pe_resume == NULL) { 2484 /* The pause/resume functionality is optional. */ 2485 return (0); 2486 } 2487 2488 return (*pde->pe_resume)(pdi); 2489 } 2490 #endif 2491 2492 #define PCI_EMUL_TEST 2493 #ifdef PCI_EMUL_TEST 2494 /* 2495 * Define a dummy test device 2496 */ 2497 #define DIOSZ 8 2498 #define DMEMSZ 4096 2499 struct pci_emul_dsoftc { 2500 uint8_t ioregs[DIOSZ]; 2501 uint8_t memregs[2][DMEMSZ]; 2502 }; 2503 2504 #define PCI_EMUL_MSI_MSGS 4 2505 #define PCI_EMUL_MSIX_MSGS 16 2506 2507 static int 2508 pci_emul_dinit(struct pci_devinst *pi, nvlist_t *nvl __unused) 2509 { 2510 int error; 2511 struct pci_emul_dsoftc *sc; 2512 2513 sc = calloc(1, sizeof(struct pci_emul_dsoftc)); 2514 2515 pi->pi_arg = sc; 2516 2517 pci_set_cfgdata16(pi, PCIR_DEVICE, 0x0001); 2518 pci_set_cfgdata16(pi, PCIR_VENDOR, 0x10DD); 2519 pci_set_cfgdata8(pi, PCIR_CLASS, 0x02); 2520 2521 error = pci_emul_add_msicap(pi, PCI_EMUL_MSI_MSGS); 2522 assert(error == 0); 2523 2524 error = pci_emul_alloc_bar(pi, 0, PCIBAR_IO, DIOSZ); 2525 assert(error == 0); 2526 2527 error = pci_emul_alloc_bar(pi, 1, PCIBAR_MEM32, DMEMSZ); 2528 assert(error == 0); 2529 2530 error = pci_emul_alloc_bar(pi, 2, PCIBAR_MEM32, DMEMSZ); 2531 assert(error == 0); 2532 2533 return (0); 2534 } 2535 2536 static void 2537 pci_emul_diow(struct pci_devinst *pi, int baridx, uint64_t offset, int size, 2538 uint64_t value) 2539 { 2540 int i; 2541 struct pci_emul_dsoftc *sc = pi->pi_arg; 2542 2543 if (baridx == 0) { 2544 if (offset + size > DIOSZ) { 2545 printf("diow: iow too large, offset %ld size %d\n", 2546 offset, size); 2547 return; 2548 } 2549 2550 if (size == 1) { 2551 sc->ioregs[offset] = value & 0xff; 2552 } else if (size == 2) { 2553 *(uint16_t *)&sc->ioregs[offset] = value & 0xffff; 2554 } else if (size == 4) { 2555 *(uint32_t *)&sc->ioregs[offset] = value; 2556 } else { 2557 printf("diow: iow unknown size %d\n", size); 2558 } 2559 2560 /* 2561 * Special magic value to generate an interrupt 2562 */ 2563 if (offset == 4 && size == 4 && pci_msi_enabled(pi)) 2564 pci_generate_msi(pi, value % pci_msi_maxmsgnum(pi)); 2565 2566 if (value == 0xabcdef) { 2567 for (i = 0; i < pci_msi_maxmsgnum(pi); i++) 2568 pci_generate_msi(pi, i); 2569 } 2570 } 2571 2572 if (baridx == 1 || baridx == 2) { 2573 if (offset + size > DMEMSZ) { 2574 printf("diow: memw too large, offset %ld size %d\n", 2575 offset, size); 2576 return; 2577 } 2578 2579 i = baridx - 1; /* 'memregs' index */ 2580 2581 if (size == 1) { 2582 sc->memregs[i][offset] = value; 2583 } else if (size == 2) { 2584 *(uint16_t *)&sc->memregs[i][offset] = value; 2585 } else if (size == 4) { 2586 *(uint32_t *)&sc->memregs[i][offset] = value; 2587 } else if (size == 8) { 2588 *(uint64_t *)&sc->memregs[i][offset] = value; 2589 } else { 2590 printf("diow: memw unknown size %d\n", size); 2591 } 2592 2593 /* 2594 * magic interrupt ?? 2595 */ 2596 } 2597 2598 if (baridx > 2 || baridx < 0) { 2599 printf("diow: unknown bar idx %d\n", baridx); 2600 } 2601 } 2602 2603 static uint64_t 2604 pci_emul_dior(struct pci_devinst *pi, int baridx, uint64_t offset, int size) 2605 { 2606 struct pci_emul_dsoftc *sc = pi->pi_arg; 2607 uint32_t value; 2608 int i; 2609 2610 if (baridx == 0) { 2611 if (offset + size > DIOSZ) { 2612 printf("dior: ior too large, offset %ld size %d\n", 2613 offset, size); 2614 return (0); 2615 } 2616 2617 value = 0; 2618 if (size == 1) { 2619 value = sc->ioregs[offset]; 2620 } else if (size == 2) { 2621 value = *(uint16_t *) &sc->ioregs[offset]; 2622 } else if (size == 4) { 2623 value = *(uint32_t *) &sc->ioregs[offset]; 2624 } else { 2625 printf("dior: ior unknown size %d\n", size); 2626 } 2627 } 2628 2629 if (baridx == 1 || baridx == 2) { 2630 if (offset + size > DMEMSZ) { 2631 printf("dior: memr too large, offset %ld size %d\n", 2632 offset, size); 2633 return (0); 2634 } 2635 2636 i = baridx - 1; /* 'memregs' index */ 2637 2638 if (size == 1) { 2639 value = sc->memregs[i][offset]; 2640 } else if (size == 2) { 2641 value = *(uint16_t *) &sc->memregs[i][offset]; 2642 } else if (size == 4) { 2643 value = *(uint32_t *) &sc->memregs[i][offset]; 2644 } else if (size == 8) { 2645 value = *(uint64_t *) &sc->memregs[i][offset]; 2646 } else { 2647 printf("dior: ior unknown size %d\n", size); 2648 } 2649 } 2650 2651 2652 if (baridx > 2 || baridx < 0) { 2653 printf("dior: unknown bar idx %d\n", baridx); 2654 return (0); 2655 } 2656 2657 return (value); 2658 } 2659 2660 #ifdef BHYVE_SNAPSHOT 2661 struct pci_devinst * 2662 pci_next(const struct pci_devinst *cursor) 2663 { 2664 unsigned bus = 0, slot = 0, func = 0; 2665 struct businfo *bi; 2666 struct slotinfo *si; 2667 struct funcinfo *fi; 2668 2669 bus = cursor ? cursor->pi_bus : 0; 2670 slot = cursor ? cursor->pi_slot : 0; 2671 func = cursor ? (cursor->pi_func + 1) : 0; 2672 2673 for (; bus < MAXBUSES; bus++) { 2674 if ((bi = pci_businfo[bus]) == NULL) 2675 continue; 2676 2677 if (slot >= MAXSLOTS) 2678 slot = 0; 2679 2680 for (; slot < MAXSLOTS; slot++) { 2681 si = &bi->slotinfo[slot]; 2682 if (func >= MAXFUNCS) 2683 func = 0; 2684 for (; func < MAXFUNCS; func++) { 2685 fi = &si->si_funcs[func]; 2686 if (fi->fi_devi == NULL) 2687 continue; 2688 2689 return (fi->fi_devi); 2690 } 2691 } 2692 } 2693 2694 return (NULL); 2695 } 2696 2697 static int 2698 pci_emul_snapshot(struct vm_snapshot_meta *meta __unused) 2699 { 2700 return (0); 2701 } 2702 #endif 2703 2704 static const struct pci_devemu pci_dummy = { 2705 .pe_emu = "dummy", 2706 .pe_init = pci_emul_dinit, 2707 .pe_barwrite = pci_emul_diow, 2708 .pe_barread = pci_emul_dior, 2709 #ifdef BHYVE_SNAPSHOT 2710 .pe_snapshot = pci_emul_snapshot, 2711 #endif 2712 }; 2713 PCI_EMUL_SET(pci_dummy); 2714 2715 #endif /* PCI_EMUL_TEST */ 2716