1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD 3 * 4 * Copyright (c) 2011 NetApp, Inc. 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY NETAPP, INC ``AS IS'' AND 17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 19 * ARE DISCLAIMED. IN NO EVENT SHALL NETAPP, INC OR CONTRIBUTORS BE LIABLE 20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 * 28 * $FreeBSD$ 29 */ 30 31 #include <sys/cdefs.h> 32 __FBSDID("$FreeBSD$"); 33 34 #include <sys/param.h> 35 #include <sys/linker_set.h> 36 37 #include <ctype.h> 38 #include <errno.h> 39 #include <pthread.h> 40 #include <stdio.h> 41 #include <stdlib.h> 42 #include <string.h> 43 #include <strings.h> 44 #include <assert.h> 45 #include <stdbool.h> 46 47 #include <machine/vmm.h> 48 #include <vmmapi.h> 49 50 #include "acpi.h" 51 #include "bhyverun.h" 52 #include "debug.h" 53 #include "inout.h" 54 #include "ioapic.h" 55 #include "mem.h" 56 #include "pci_emul.h" 57 #include "pci_irq.h" 58 #include "pci_lpc.h" 59 60 #define CONF1_ADDR_PORT 0x0cf8 61 #define CONF1_DATA_PORT 0x0cfc 62 63 #define CONF1_ENABLE 0x80000000ul 64 65 #define MAXBUSES (PCI_BUSMAX + 1) 66 #define MAXSLOTS (PCI_SLOTMAX + 1) 67 #define MAXFUNCS (PCI_FUNCMAX + 1) 68 69 struct funcinfo { 70 char *fi_name; 71 char *fi_param; 72 struct pci_devinst *fi_devi; 73 }; 74 75 struct intxinfo { 76 int ii_count; 77 int ii_pirq_pin; 78 int ii_ioapic_irq; 79 }; 80 81 struct slotinfo { 82 struct intxinfo si_intpins[4]; 83 struct funcinfo si_funcs[MAXFUNCS]; 84 }; 85 86 struct businfo { 87 uint16_t iobase, iolimit; /* I/O window */ 88 uint32_t membase32, memlimit32; /* mmio window below 4GB */ 89 uint64_t membase64, memlimit64; /* mmio window above 4GB */ 90 struct slotinfo slotinfo[MAXSLOTS]; 91 }; 92 93 static struct businfo *pci_businfo[MAXBUSES]; 94 95 SET_DECLARE(pci_devemu_set, struct pci_devemu); 96 97 static uint64_t pci_emul_iobase; 98 static uint64_t pci_emul_membase32; 99 static uint64_t pci_emul_membase64; 100 101 #define PCI_EMUL_IOBASE 0x2000 102 #define PCI_EMUL_IOLIMIT 0x10000 103 104 #define PCI_EMUL_ECFG_BASE 0xE0000000 /* 3.5GB */ 105 #define PCI_EMUL_ECFG_SIZE (MAXBUSES * 1024 * 1024) /* 1MB per bus */ 106 SYSRES_MEM(PCI_EMUL_ECFG_BASE, PCI_EMUL_ECFG_SIZE); 107 108 #define PCI_EMUL_MEMLIMIT32 PCI_EMUL_ECFG_BASE 109 110 #define PCI_EMUL_MEMBASE64 0xD000000000UL 111 #define PCI_EMUL_MEMLIMIT64 0xFD00000000UL 112 113 static struct pci_devemu *pci_emul_finddev(char *name); 114 static void pci_lintr_route(struct pci_devinst *pi); 115 static void pci_lintr_update(struct pci_devinst *pi); 116 static void pci_cfgrw(struct vmctx *ctx, int vcpu, int in, int bus, int slot, 117 int func, int coff, int bytes, uint32_t *val); 118 119 static __inline void 120 CFGWRITE(struct pci_devinst *pi, int coff, uint32_t val, int bytes) 121 { 122 123 if (bytes == 1) 124 pci_set_cfgdata8(pi, coff, val); 125 else if (bytes == 2) 126 pci_set_cfgdata16(pi, coff, val); 127 else 128 pci_set_cfgdata32(pi, coff, val); 129 } 130 131 static __inline uint32_t 132 CFGREAD(struct pci_devinst *pi, int coff, int bytes) 133 { 134 135 if (bytes == 1) 136 return (pci_get_cfgdata8(pi, coff)); 137 else if (bytes == 2) 138 return (pci_get_cfgdata16(pi, coff)); 139 else 140 return (pci_get_cfgdata32(pi, coff)); 141 } 142 143 /* 144 * I/O access 145 */ 146 147 /* 148 * Slot options are in the form: 149 * 150 * <bus>:<slot>:<func>,<emul>[,<config>] 151 * <slot>[:<func>],<emul>[,<config>] 152 * 153 * slot is 0..31 154 * func is 0..7 155 * emul is a string describing the type of PCI device e.g. virtio-net 156 * config is an optional string, depending on the device, that can be 157 * used for configuration. 158 * Examples are: 159 * 1,virtio-net,tap0 160 * 3:0,dummy 161 */ 162 static void 163 pci_parse_slot_usage(char *aopt) 164 { 165 166 EPRINTLN("Invalid PCI slot info field \"%s\"", aopt); 167 } 168 169 int 170 pci_parse_slot(char *opt) 171 { 172 struct businfo *bi; 173 struct slotinfo *si; 174 char *emul, *config, *str, *cp; 175 int error, bnum, snum, fnum; 176 177 error = -1; 178 str = strdup(opt); 179 180 emul = config = NULL; 181 if ((cp = strchr(str, ',')) != NULL) { 182 *cp = '\0'; 183 emul = cp + 1; 184 if ((cp = strchr(emul, ',')) != NULL) { 185 *cp = '\0'; 186 config = cp + 1; 187 } 188 } else { 189 pci_parse_slot_usage(opt); 190 goto done; 191 } 192 193 /* <bus>:<slot>:<func> */ 194 if (sscanf(str, "%d:%d:%d", &bnum, &snum, &fnum) != 3) { 195 bnum = 0; 196 /* <slot>:<func> */ 197 if (sscanf(str, "%d:%d", &snum, &fnum) != 2) { 198 fnum = 0; 199 /* <slot> */ 200 if (sscanf(str, "%d", &snum) != 1) { 201 snum = -1; 202 } 203 } 204 } 205 206 if (bnum < 0 || bnum >= MAXBUSES || snum < 0 || snum >= MAXSLOTS || 207 fnum < 0 || fnum >= MAXFUNCS) { 208 pci_parse_slot_usage(opt); 209 goto done; 210 } 211 212 if (pci_businfo[bnum] == NULL) 213 pci_businfo[bnum] = calloc(1, sizeof(struct businfo)); 214 215 bi = pci_businfo[bnum]; 216 si = &bi->slotinfo[snum]; 217 218 if (si->si_funcs[fnum].fi_name != NULL) { 219 EPRINTLN("pci slot %d:%d already occupied!", 220 snum, fnum); 221 goto done; 222 } 223 224 if (pci_emul_finddev(emul) == NULL) { 225 EPRINTLN("pci slot %d:%d: unknown device \"%s\"", 226 snum, fnum, emul); 227 goto done; 228 } 229 230 error = 0; 231 si->si_funcs[fnum].fi_name = emul; 232 si->si_funcs[fnum].fi_param = config; 233 234 done: 235 if (error) 236 free(str); 237 238 return (error); 239 } 240 241 void 242 pci_print_supported_devices() 243 { 244 struct pci_devemu **pdpp, *pdp; 245 246 SET_FOREACH(pdpp, pci_devemu_set) { 247 pdp = *pdpp; 248 printf("%s\n", pdp->pe_emu); 249 } 250 } 251 252 static int 253 pci_valid_pba_offset(struct pci_devinst *pi, uint64_t offset) 254 { 255 256 if (offset < pi->pi_msix.pba_offset) 257 return (0); 258 259 if (offset >= pi->pi_msix.pba_offset + pi->pi_msix.pba_size) { 260 return (0); 261 } 262 263 return (1); 264 } 265 266 int 267 pci_emul_msix_twrite(struct pci_devinst *pi, uint64_t offset, int size, 268 uint64_t value) 269 { 270 int msix_entry_offset; 271 int tab_index; 272 char *dest; 273 274 /* support only 4 or 8 byte writes */ 275 if (size != 4 && size != 8) 276 return (-1); 277 278 /* 279 * Return if table index is beyond what device supports 280 */ 281 tab_index = offset / MSIX_TABLE_ENTRY_SIZE; 282 if (tab_index >= pi->pi_msix.table_count) 283 return (-1); 284 285 msix_entry_offset = offset % MSIX_TABLE_ENTRY_SIZE; 286 287 /* support only aligned writes */ 288 if ((msix_entry_offset % size) != 0) 289 return (-1); 290 291 dest = (char *)(pi->pi_msix.table + tab_index); 292 dest += msix_entry_offset; 293 294 if (size == 4) 295 *((uint32_t *)dest) = value; 296 else 297 *((uint64_t *)dest) = value; 298 299 return (0); 300 } 301 302 uint64_t 303 pci_emul_msix_tread(struct pci_devinst *pi, uint64_t offset, int size) 304 { 305 char *dest; 306 int msix_entry_offset; 307 int tab_index; 308 uint64_t retval = ~0; 309 310 /* 311 * The PCI standard only allows 4 and 8 byte accesses to the MSI-X 312 * table but we also allow 1 byte access to accommodate reads from 313 * ddb. 314 */ 315 if (size != 1 && size != 4 && size != 8) 316 return (retval); 317 318 msix_entry_offset = offset % MSIX_TABLE_ENTRY_SIZE; 319 320 /* support only aligned reads */ 321 if ((msix_entry_offset % size) != 0) { 322 return (retval); 323 } 324 325 tab_index = offset / MSIX_TABLE_ENTRY_SIZE; 326 327 if (tab_index < pi->pi_msix.table_count) { 328 /* valid MSI-X Table access */ 329 dest = (char *)(pi->pi_msix.table + tab_index); 330 dest += msix_entry_offset; 331 332 if (size == 1) 333 retval = *((uint8_t *)dest); 334 else if (size == 4) 335 retval = *((uint32_t *)dest); 336 else 337 retval = *((uint64_t *)dest); 338 } else if (pci_valid_pba_offset(pi, offset)) { 339 /* return 0 for PBA access */ 340 retval = 0; 341 } 342 343 return (retval); 344 } 345 346 int 347 pci_msix_table_bar(struct pci_devinst *pi) 348 { 349 350 if (pi->pi_msix.table != NULL) 351 return (pi->pi_msix.table_bar); 352 else 353 return (-1); 354 } 355 356 int 357 pci_msix_pba_bar(struct pci_devinst *pi) 358 { 359 360 if (pi->pi_msix.table != NULL) 361 return (pi->pi_msix.pba_bar); 362 else 363 return (-1); 364 } 365 366 static int 367 pci_emul_io_handler(struct vmctx *ctx, int vcpu, int in, int port, int bytes, 368 uint32_t *eax, void *arg) 369 { 370 struct pci_devinst *pdi = arg; 371 struct pci_devemu *pe = pdi->pi_d; 372 uint64_t offset; 373 int i; 374 375 for (i = 0; i <= PCI_BARMAX; i++) { 376 if (pdi->pi_bar[i].type == PCIBAR_IO && 377 port >= pdi->pi_bar[i].addr && 378 port + bytes <= pdi->pi_bar[i].addr + pdi->pi_bar[i].size) { 379 offset = port - pdi->pi_bar[i].addr; 380 if (in) 381 *eax = (*pe->pe_barread)(ctx, vcpu, pdi, i, 382 offset, bytes); 383 else 384 (*pe->pe_barwrite)(ctx, vcpu, pdi, i, offset, 385 bytes, *eax); 386 return (0); 387 } 388 } 389 return (-1); 390 } 391 392 static int 393 pci_emul_mem_handler(struct vmctx *ctx, int vcpu, int dir, uint64_t addr, 394 int size, uint64_t *val, void *arg1, long arg2) 395 { 396 struct pci_devinst *pdi = arg1; 397 struct pci_devemu *pe = pdi->pi_d; 398 uint64_t offset; 399 int bidx = (int) arg2; 400 401 assert(bidx <= PCI_BARMAX); 402 assert(pdi->pi_bar[bidx].type == PCIBAR_MEM32 || 403 pdi->pi_bar[bidx].type == PCIBAR_MEM64); 404 assert(addr >= pdi->pi_bar[bidx].addr && 405 addr + size <= pdi->pi_bar[bidx].addr + pdi->pi_bar[bidx].size); 406 407 offset = addr - pdi->pi_bar[bidx].addr; 408 409 if (dir == MEM_F_WRITE) { 410 if (size == 8) { 411 (*pe->pe_barwrite)(ctx, vcpu, pdi, bidx, offset, 412 4, *val & 0xffffffff); 413 (*pe->pe_barwrite)(ctx, vcpu, pdi, bidx, offset + 4, 414 4, *val >> 32); 415 } else { 416 (*pe->pe_barwrite)(ctx, vcpu, pdi, bidx, offset, 417 size, *val); 418 } 419 } else { 420 if (size == 8) { 421 *val = (*pe->pe_barread)(ctx, vcpu, pdi, bidx, 422 offset, 4); 423 *val |= (*pe->pe_barread)(ctx, vcpu, pdi, bidx, 424 offset + 4, 4) << 32; 425 } else { 426 *val = (*pe->pe_barread)(ctx, vcpu, pdi, bidx, 427 offset, size); 428 } 429 } 430 431 return (0); 432 } 433 434 435 static int 436 pci_emul_alloc_resource(uint64_t *baseptr, uint64_t limit, uint64_t size, 437 uint64_t *addr) 438 { 439 uint64_t base; 440 441 assert((size & (size - 1)) == 0); /* must be a power of 2 */ 442 443 base = roundup2(*baseptr, size); 444 445 if (base + size <= limit) { 446 *addr = base; 447 *baseptr = base + size; 448 return (0); 449 } else 450 return (-1); 451 } 452 453 int 454 pci_emul_alloc_bar(struct pci_devinst *pdi, int idx, enum pcibar_type type, 455 uint64_t size) 456 { 457 458 return (pci_emul_alloc_pbar(pdi, idx, 0, type, size)); 459 } 460 461 /* 462 * Register (or unregister) the MMIO or I/O region associated with the BAR 463 * register 'idx' of an emulated pci device. 464 */ 465 static void 466 modify_bar_registration(struct pci_devinst *pi, int idx, int registration) 467 { 468 int error; 469 struct inout_port iop; 470 struct mem_range mr; 471 472 switch (pi->pi_bar[idx].type) { 473 case PCIBAR_IO: 474 bzero(&iop, sizeof(struct inout_port)); 475 iop.name = pi->pi_name; 476 iop.port = pi->pi_bar[idx].addr; 477 iop.size = pi->pi_bar[idx].size; 478 if (registration) { 479 iop.flags = IOPORT_F_INOUT; 480 iop.handler = pci_emul_io_handler; 481 iop.arg = pi; 482 error = register_inout(&iop); 483 } else 484 error = unregister_inout(&iop); 485 break; 486 case PCIBAR_MEM32: 487 case PCIBAR_MEM64: 488 bzero(&mr, sizeof(struct mem_range)); 489 mr.name = pi->pi_name; 490 mr.base = pi->pi_bar[idx].addr; 491 mr.size = pi->pi_bar[idx].size; 492 if (registration) { 493 mr.flags = MEM_F_RW; 494 mr.handler = pci_emul_mem_handler; 495 mr.arg1 = pi; 496 mr.arg2 = idx; 497 error = register_mem(&mr); 498 } else 499 error = unregister_mem(&mr); 500 break; 501 default: 502 error = EINVAL; 503 break; 504 } 505 assert(error == 0); 506 } 507 508 static void 509 unregister_bar(struct pci_devinst *pi, int idx) 510 { 511 512 modify_bar_registration(pi, idx, 0); 513 } 514 515 static void 516 register_bar(struct pci_devinst *pi, int idx) 517 { 518 519 modify_bar_registration(pi, idx, 1); 520 } 521 522 /* Are we decoding i/o port accesses for the emulated pci device? */ 523 static int 524 porten(struct pci_devinst *pi) 525 { 526 uint16_t cmd; 527 528 cmd = pci_get_cfgdata16(pi, PCIR_COMMAND); 529 530 return (cmd & PCIM_CMD_PORTEN); 531 } 532 533 /* Are we decoding memory accesses for the emulated pci device? */ 534 static int 535 memen(struct pci_devinst *pi) 536 { 537 uint16_t cmd; 538 539 cmd = pci_get_cfgdata16(pi, PCIR_COMMAND); 540 541 return (cmd & PCIM_CMD_MEMEN); 542 } 543 544 /* 545 * Update the MMIO or I/O address that is decoded by the BAR register. 546 * 547 * If the pci device has enabled the address space decoding then intercept 548 * the address range decoded by the BAR register. 549 */ 550 static void 551 update_bar_address(struct pci_devinst *pi, uint64_t addr, int idx, int type) 552 { 553 int decode; 554 555 if (pi->pi_bar[idx].type == PCIBAR_IO) 556 decode = porten(pi); 557 else 558 decode = memen(pi); 559 560 if (decode) 561 unregister_bar(pi, idx); 562 563 switch (type) { 564 case PCIBAR_IO: 565 case PCIBAR_MEM32: 566 pi->pi_bar[idx].addr = addr; 567 break; 568 case PCIBAR_MEM64: 569 pi->pi_bar[idx].addr &= ~0xffffffffUL; 570 pi->pi_bar[idx].addr |= addr; 571 break; 572 case PCIBAR_MEMHI64: 573 pi->pi_bar[idx].addr &= 0xffffffff; 574 pi->pi_bar[idx].addr |= addr; 575 break; 576 default: 577 assert(0); 578 } 579 580 if (decode) 581 register_bar(pi, idx); 582 } 583 584 int 585 pci_emul_alloc_pbar(struct pci_devinst *pdi, int idx, uint64_t hostbase, 586 enum pcibar_type type, uint64_t size) 587 { 588 int error; 589 uint64_t *baseptr, limit, addr, mask, lobits, bar; 590 uint16_t cmd, enbit; 591 592 assert(idx >= 0 && idx <= PCI_BARMAX); 593 594 if ((size & (size - 1)) != 0) 595 size = 1UL << flsl(size); /* round up to a power of 2 */ 596 597 /* Enforce minimum BAR sizes required by the PCI standard */ 598 if (type == PCIBAR_IO) { 599 if (size < 4) 600 size = 4; 601 } else { 602 if (size < 16) 603 size = 16; 604 } 605 606 switch (type) { 607 case PCIBAR_NONE: 608 baseptr = NULL; 609 addr = mask = lobits = enbit = 0; 610 break; 611 case PCIBAR_IO: 612 baseptr = &pci_emul_iobase; 613 limit = PCI_EMUL_IOLIMIT; 614 mask = PCIM_BAR_IO_BASE; 615 lobits = PCIM_BAR_IO_SPACE; 616 enbit = PCIM_CMD_PORTEN; 617 break; 618 case PCIBAR_MEM64: 619 /* 620 * XXX 621 * Some drivers do not work well if the 64-bit BAR is allocated 622 * above 4GB. Allow for this by allocating small requests under 623 * 4GB unless then allocation size is larger than some arbitrary 624 * number (32MB currently). 625 */ 626 if (size > 32 * 1024 * 1024) { 627 /* 628 * XXX special case for device requiring peer-peer DMA 629 */ 630 if (size == 0x100000000UL) 631 baseptr = &hostbase; 632 else 633 baseptr = &pci_emul_membase64; 634 limit = PCI_EMUL_MEMLIMIT64; 635 mask = PCIM_BAR_MEM_BASE; 636 lobits = PCIM_BAR_MEM_SPACE | PCIM_BAR_MEM_64 | 637 PCIM_BAR_MEM_PREFETCH; 638 } else { 639 baseptr = &pci_emul_membase32; 640 limit = PCI_EMUL_MEMLIMIT32; 641 mask = PCIM_BAR_MEM_BASE; 642 lobits = PCIM_BAR_MEM_SPACE | PCIM_BAR_MEM_64; 643 } 644 enbit = PCIM_CMD_MEMEN; 645 break; 646 case PCIBAR_MEM32: 647 baseptr = &pci_emul_membase32; 648 limit = PCI_EMUL_MEMLIMIT32; 649 mask = PCIM_BAR_MEM_BASE; 650 lobits = PCIM_BAR_MEM_SPACE | PCIM_BAR_MEM_32; 651 enbit = PCIM_CMD_MEMEN; 652 break; 653 default: 654 printf("pci_emul_alloc_base: invalid bar type %d\n", type); 655 assert(0); 656 } 657 658 if (baseptr != NULL) { 659 error = pci_emul_alloc_resource(baseptr, limit, size, &addr); 660 if (error != 0) 661 return (error); 662 } 663 664 pdi->pi_bar[idx].type = type; 665 pdi->pi_bar[idx].addr = addr; 666 pdi->pi_bar[idx].size = size; 667 668 /* Initialize the BAR register in config space */ 669 bar = (addr & mask) | lobits; 670 pci_set_cfgdata32(pdi, PCIR_BAR(idx), bar); 671 672 if (type == PCIBAR_MEM64) { 673 assert(idx + 1 <= PCI_BARMAX); 674 pdi->pi_bar[idx + 1].type = PCIBAR_MEMHI64; 675 pci_set_cfgdata32(pdi, PCIR_BAR(idx + 1), bar >> 32); 676 } 677 678 cmd = pci_get_cfgdata16(pdi, PCIR_COMMAND); 679 if ((cmd & enbit) != enbit) 680 pci_set_cfgdata16(pdi, PCIR_COMMAND, cmd | enbit); 681 register_bar(pdi, idx); 682 683 return (0); 684 } 685 686 #define CAP_START_OFFSET 0x40 687 static int 688 pci_emul_add_capability(struct pci_devinst *pi, u_char *capdata, int caplen) 689 { 690 int i, capoff, reallen; 691 uint16_t sts; 692 693 assert(caplen > 0); 694 695 reallen = roundup2(caplen, 4); /* dword aligned */ 696 697 sts = pci_get_cfgdata16(pi, PCIR_STATUS); 698 if ((sts & PCIM_STATUS_CAPPRESENT) == 0) 699 capoff = CAP_START_OFFSET; 700 else 701 capoff = pi->pi_capend + 1; 702 703 /* Check if we have enough space */ 704 if (capoff + reallen > PCI_REGMAX + 1) 705 return (-1); 706 707 /* Set the previous capability pointer */ 708 if ((sts & PCIM_STATUS_CAPPRESENT) == 0) { 709 pci_set_cfgdata8(pi, PCIR_CAP_PTR, capoff); 710 pci_set_cfgdata16(pi, PCIR_STATUS, sts|PCIM_STATUS_CAPPRESENT); 711 } else 712 pci_set_cfgdata8(pi, pi->pi_prevcap + 1, capoff); 713 714 /* Copy the capability */ 715 for (i = 0; i < caplen; i++) 716 pci_set_cfgdata8(pi, capoff + i, capdata[i]); 717 718 /* Set the next capability pointer */ 719 pci_set_cfgdata8(pi, capoff + 1, 0); 720 721 pi->pi_prevcap = capoff; 722 pi->pi_capend = capoff + reallen - 1; 723 return (0); 724 } 725 726 static struct pci_devemu * 727 pci_emul_finddev(char *name) 728 { 729 struct pci_devemu **pdpp, *pdp; 730 731 SET_FOREACH(pdpp, pci_devemu_set) { 732 pdp = *pdpp; 733 if (!strcmp(pdp->pe_emu, name)) { 734 return (pdp); 735 } 736 } 737 738 return (NULL); 739 } 740 741 static int 742 pci_emul_init(struct vmctx *ctx, struct pci_devemu *pde, int bus, int slot, 743 int func, struct funcinfo *fi) 744 { 745 struct pci_devinst *pdi; 746 int err; 747 748 pdi = calloc(1, sizeof(struct pci_devinst)); 749 750 pdi->pi_vmctx = ctx; 751 pdi->pi_bus = bus; 752 pdi->pi_slot = slot; 753 pdi->pi_func = func; 754 pthread_mutex_init(&pdi->pi_lintr.lock, NULL); 755 pdi->pi_lintr.pin = 0; 756 pdi->pi_lintr.state = IDLE; 757 pdi->pi_lintr.pirq_pin = 0; 758 pdi->pi_lintr.ioapic_irq = 0; 759 pdi->pi_d = pde; 760 snprintf(pdi->pi_name, PI_NAMESZ, "%s-pci-%d", pde->pe_emu, slot); 761 762 /* Disable legacy interrupts */ 763 pci_set_cfgdata8(pdi, PCIR_INTLINE, 255); 764 pci_set_cfgdata8(pdi, PCIR_INTPIN, 0); 765 766 pci_set_cfgdata8(pdi, PCIR_COMMAND, PCIM_CMD_BUSMASTEREN); 767 768 err = (*pde->pe_init)(ctx, pdi, fi->fi_param); 769 if (err == 0) 770 fi->fi_devi = pdi; 771 else 772 free(pdi); 773 774 return (err); 775 } 776 777 void 778 pci_populate_msicap(struct msicap *msicap, int msgnum, int nextptr) 779 { 780 int mmc; 781 782 /* Number of msi messages must be a power of 2 between 1 and 32 */ 783 assert((msgnum & (msgnum - 1)) == 0 && msgnum >= 1 && msgnum <= 32); 784 mmc = ffs(msgnum) - 1; 785 786 bzero(msicap, sizeof(struct msicap)); 787 msicap->capid = PCIY_MSI; 788 msicap->nextptr = nextptr; 789 msicap->msgctrl = PCIM_MSICTRL_64BIT | (mmc << 1); 790 } 791 792 int 793 pci_emul_add_msicap(struct pci_devinst *pi, int msgnum) 794 { 795 struct msicap msicap; 796 797 pci_populate_msicap(&msicap, msgnum, 0); 798 799 return (pci_emul_add_capability(pi, (u_char *)&msicap, sizeof(msicap))); 800 } 801 802 static void 803 pci_populate_msixcap(struct msixcap *msixcap, int msgnum, int barnum, 804 uint32_t msix_tab_size) 805 { 806 807 assert(msix_tab_size % 4096 == 0); 808 809 bzero(msixcap, sizeof(struct msixcap)); 810 msixcap->capid = PCIY_MSIX; 811 812 /* 813 * Message Control Register, all fields set to 814 * zero except for the Table Size. 815 * Note: Table size N is encoded as N-1 816 */ 817 msixcap->msgctrl = msgnum - 1; 818 819 /* 820 * MSI-X BAR setup: 821 * - MSI-X table start at offset 0 822 * - PBA table starts at a 4K aligned offset after the MSI-X table 823 */ 824 msixcap->table_info = barnum & PCIM_MSIX_BIR_MASK; 825 msixcap->pba_info = msix_tab_size | (barnum & PCIM_MSIX_BIR_MASK); 826 } 827 828 static void 829 pci_msix_table_init(struct pci_devinst *pi, int table_entries) 830 { 831 int i, table_size; 832 833 assert(table_entries > 0); 834 assert(table_entries <= MAX_MSIX_TABLE_ENTRIES); 835 836 table_size = table_entries * MSIX_TABLE_ENTRY_SIZE; 837 pi->pi_msix.table = calloc(1, table_size); 838 839 /* set mask bit of vector control register */ 840 for (i = 0; i < table_entries; i++) 841 pi->pi_msix.table[i].vector_control |= PCIM_MSIX_VCTRL_MASK; 842 } 843 844 int 845 pci_emul_add_msixcap(struct pci_devinst *pi, int msgnum, int barnum) 846 { 847 uint32_t tab_size; 848 struct msixcap msixcap; 849 850 assert(msgnum >= 1 && msgnum <= MAX_MSIX_TABLE_ENTRIES); 851 assert(barnum >= 0 && barnum <= PCIR_MAX_BAR_0); 852 853 tab_size = msgnum * MSIX_TABLE_ENTRY_SIZE; 854 855 /* Align table size to nearest 4K */ 856 tab_size = roundup2(tab_size, 4096); 857 858 pi->pi_msix.table_bar = barnum; 859 pi->pi_msix.pba_bar = barnum; 860 pi->pi_msix.table_offset = 0; 861 pi->pi_msix.table_count = msgnum; 862 pi->pi_msix.pba_offset = tab_size; 863 pi->pi_msix.pba_size = PBA_SIZE(msgnum); 864 865 pci_msix_table_init(pi, msgnum); 866 867 pci_populate_msixcap(&msixcap, msgnum, barnum, tab_size); 868 869 /* allocate memory for MSI-X Table and PBA */ 870 pci_emul_alloc_bar(pi, barnum, PCIBAR_MEM32, 871 tab_size + pi->pi_msix.pba_size); 872 873 return (pci_emul_add_capability(pi, (u_char *)&msixcap, 874 sizeof(msixcap))); 875 } 876 877 void 878 msixcap_cfgwrite(struct pci_devinst *pi, int capoff, int offset, 879 int bytes, uint32_t val) 880 { 881 uint16_t msgctrl, rwmask; 882 int off; 883 884 off = offset - capoff; 885 /* Message Control Register */ 886 if (off == 2 && bytes == 2) { 887 rwmask = PCIM_MSIXCTRL_MSIX_ENABLE | PCIM_MSIXCTRL_FUNCTION_MASK; 888 msgctrl = pci_get_cfgdata16(pi, offset); 889 msgctrl &= ~rwmask; 890 msgctrl |= val & rwmask; 891 val = msgctrl; 892 893 pi->pi_msix.enabled = val & PCIM_MSIXCTRL_MSIX_ENABLE; 894 pi->pi_msix.function_mask = val & PCIM_MSIXCTRL_FUNCTION_MASK; 895 pci_lintr_update(pi); 896 } 897 898 CFGWRITE(pi, offset, val, bytes); 899 } 900 901 void 902 msicap_cfgwrite(struct pci_devinst *pi, int capoff, int offset, 903 int bytes, uint32_t val) 904 { 905 uint16_t msgctrl, rwmask, msgdata, mme; 906 uint32_t addrlo; 907 908 /* 909 * If guest is writing to the message control register make sure 910 * we do not overwrite read-only fields. 911 */ 912 if ((offset - capoff) == 2 && bytes == 2) { 913 rwmask = PCIM_MSICTRL_MME_MASK | PCIM_MSICTRL_MSI_ENABLE; 914 msgctrl = pci_get_cfgdata16(pi, offset); 915 msgctrl &= ~rwmask; 916 msgctrl |= val & rwmask; 917 val = msgctrl; 918 919 addrlo = pci_get_cfgdata32(pi, capoff + 4); 920 if (msgctrl & PCIM_MSICTRL_64BIT) 921 msgdata = pci_get_cfgdata16(pi, capoff + 12); 922 else 923 msgdata = pci_get_cfgdata16(pi, capoff + 8); 924 925 mme = msgctrl & PCIM_MSICTRL_MME_MASK; 926 pi->pi_msi.enabled = msgctrl & PCIM_MSICTRL_MSI_ENABLE ? 1 : 0; 927 if (pi->pi_msi.enabled) { 928 pi->pi_msi.addr = addrlo; 929 pi->pi_msi.msg_data = msgdata; 930 pi->pi_msi.maxmsgnum = 1 << (mme >> 4); 931 } else { 932 pi->pi_msi.maxmsgnum = 0; 933 } 934 pci_lintr_update(pi); 935 } 936 937 CFGWRITE(pi, offset, val, bytes); 938 } 939 940 void 941 pciecap_cfgwrite(struct pci_devinst *pi, int capoff, int offset, 942 int bytes, uint32_t val) 943 { 944 945 /* XXX don't write to the readonly parts */ 946 CFGWRITE(pi, offset, val, bytes); 947 } 948 949 #define PCIECAP_VERSION 0x2 950 int 951 pci_emul_add_pciecap(struct pci_devinst *pi, int type) 952 { 953 int err; 954 struct pciecap pciecap; 955 956 bzero(&pciecap, sizeof(pciecap)); 957 958 /* 959 * Use the integrated endpoint type for endpoints on a root complex bus. 960 * 961 * NB: bhyve currently only supports a single PCI bus that is the root 962 * complex bus, so all endpoints are integrated. 963 */ 964 if ((type == PCIEM_TYPE_ENDPOINT) && (pi->pi_bus == 0)) 965 type = PCIEM_TYPE_ROOT_INT_EP; 966 967 pciecap.capid = PCIY_EXPRESS; 968 pciecap.pcie_capabilities = PCIECAP_VERSION | type; 969 if (type != PCIEM_TYPE_ROOT_INT_EP) { 970 pciecap.link_capabilities = 0x411; /* gen1, x1 */ 971 pciecap.link_status = 0x11; /* gen1, x1 */ 972 } 973 974 err = pci_emul_add_capability(pi, (u_char *)&pciecap, sizeof(pciecap)); 975 return (err); 976 } 977 978 /* 979 * This function assumes that 'coff' is in the capabilities region of the 980 * config space. 981 */ 982 static void 983 pci_emul_capwrite(struct pci_devinst *pi, int offset, int bytes, uint32_t val) 984 { 985 int capid; 986 uint8_t capoff, nextoff; 987 988 /* Do not allow un-aligned writes */ 989 if ((offset & (bytes - 1)) != 0) 990 return; 991 992 /* Find the capability that we want to update */ 993 capoff = CAP_START_OFFSET; 994 while (1) { 995 nextoff = pci_get_cfgdata8(pi, capoff + 1); 996 if (nextoff == 0) 997 break; 998 if (offset >= capoff && offset < nextoff) 999 break; 1000 1001 capoff = nextoff; 1002 } 1003 assert(offset >= capoff); 1004 1005 /* 1006 * Capability ID and Next Capability Pointer are readonly. 1007 * However, some o/s's do 4-byte writes that include these. 1008 * For this case, trim the write back to 2 bytes and adjust 1009 * the data. 1010 */ 1011 if (offset == capoff || offset == capoff + 1) { 1012 if (offset == capoff && bytes == 4) { 1013 bytes = 2; 1014 offset += 2; 1015 val >>= 16; 1016 } else 1017 return; 1018 } 1019 1020 capid = pci_get_cfgdata8(pi, capoff); 1021 switch (capid) { 1022 case PCIY_MSI: 1023 msicap_cfgwrite(pi, capoff, offset, bytes, val); 1024 break; 1025 case PCIY_MSIX: 1026 msixcap_cfgwrite(pi, capoff, offset, bytes, val); 1027 break; 1028 case PCIY_EXPRESS: 1029 pciecap_cfgwrite(pi, capoff, offset, bytes, val); 1030 break; 1031 default: 1032 break; 1033 } 1034 } 1035 1036 static int 1037 pci_emul_iscap(struct pci_devinst *pi, int offset) 1038 { 1039 uint16_t sts; 1040 1041 sts = pci_get_cfgdata16(pi, PCIR_STATUS); 1042 if ((sts & PCIM_STATUS_CAPPRESENT) != 0) { 1043 if (offset >= CAP_START_OFFSET && offset <= pi->pi_capend) 1044 return (1); 1045 } 1046 return (0); 1047 } 1048 1049 static int 1050 pci_emul_fallback_handler(struct vmctx *ctx, int vcpu, int dir, uint64_t addr, 1051 int size, uint64_t *val, void *arg1, long arg2) 1052 { 1053 /* 1054 * Ignore writes; return 0xff's for reads. The mem read code 1055 * will take care of truncating to the correct size. 1056 */ 1057 if (dir == MEM_F_READ) { 1058 *val = 0xffffffffffffffff; 1059 } 1060 1061 return (0); 1062 } 1063 1064 static int 1065 pci_emul_ecfg_handler(struct vmctx *ctx, int vcpu, int dir, uint64_t addr, 1066 int bytes, uint64_t *val, void *arg1, long arg2) 1067 { 1068 int bus, slot, func, coff, in; 1069 1070 coff = addr & 0xfff; 1071 func = (addr >> 12) & 0x7; 1072 slot = (addr >> 15) & 0x1f; 1073 bus = (addr >> 20) & 0xff; 1074 in = (dir == MEM_F_READ); 1075 if (in) 1076 *val = ~0UL; 1077 pci_cfgrw(ctx, vcpu, in, bus, slot, func, coff, bytes, (uint32_t *)val); 1078 return (0); 1079 } 1080 1081 uint64_t 1082 pci_ecfg_base(void) 1083 { 1084 1085 return (PCI_EMUL_ECFG_BASE); 1086 } 1087 1088 #define BUSIO_ROUNDUP 32 1089 #define BUSMEM_ROUNDUP (1024 * 1024) 1090 1091 int 1092 init_pci(struct vmctx *ctx) 1093 { 1094 struct mem_range mr; 1095 struct pci_devemu *pde; 1096 struct businfo *bi; 1097 struct slotinfo *si; 1098 struct funcinfo *fi; 1099 size_t lowmem; 1100 int bus, slot, func; 1101 int error; 1102 1103 pci_emul_iobase = PCI_EMUL_IOBASE; 1104 pci_emul_membase32 = vm_get_lowmem_limit(ctx); 1105 pci_emul_membase64 = PCI_EMUL_MEMBASE64; 1106 1107 for (bus = 0; bus < MAXBUSES; bus++) { 1108 if ((bi = pci_businfo[bus]) == NULL) 1109 continue; 1110 /* 1111 * Keep track of the i/o and memory resources allocated to 1112 * this bus. 1113 */ 1114 bi->iobase = pci_emul_iobase; 1115 bi->membase32 = pci_emul_membase32; 1116 bi->membase64 = pci_emul_membase64; 1117 1118 for (slot = 0; slot < MAXSLOTS; slot++) { 1119 si = &bi->slotinfo[slot]; 1120 for (func = 0; func < MAXFUNCS; func++) { 1121 fi = &si->si_funcs[func]; 1122 if (fi->fi_name == NULL) 1123 continue; 1124 pde = pci_emul_finddev(fi->fi_name); 1125 assert(pde != NULL); 1126 error = pci_emul_init(ctx, pde, bus, slot, 1127 func, fi); 1128 if (error) 1129 return (error); 1130 } 1131 } 1132 1133 /* 1134 * Add some slop to the I/O and memory resources decoded by 1135 * this bus to give a guest some flexibility if it wants to 1136 * reprogram the BARs. 1137 */ 1138 pci_emul_iobase += BUSIO_ROUNDUP; 1139 pci_emul_iobase = roundup2(pci_emul_iobase, BUSIO_ROUNDUP); 1140 bi->iolimit = pci_emul_iobase; 1141 1142 pci_emul_membase32 += BUSMEM_ROUNDUP; 1143 pci_emul_membase32 = roundup2(pci_emul_membase32, 1144 BUSMEM_ROUNDUP); 1145 bi->memlimit32 = pci_emul_membase32; 1146 1147 pci_emul_membase64 += BUSMEM_ROUNDUP; 1148 pci_emul_membase64 = roundup2(pci_emul_membase64, 1149 BUSMEM_ROUNDUP); 1150 bi->memlimit64 = pci_emul_membase64; 1151 } 1152 1153 /* 1154 * PCI backends are initialized before routing INTx interrupts 1155 * so that LPC devices are able to reserve ISA IRQs before 1156 * routing PIRQ pins. 1157 */ 1158 for (bus = 0; bus < MAXBUSES; bus++) { 1159 if ((bi = pci_businfo[bus]) == NULL) 1160 continue; 1161 1162 for (slot = 0; slot < MAXSLOTS; slot++) { 1163 si = &bi->slotinfo[slot]; 1164 for (func = 0; func < MAXFUNCS; func++) { 1165 fi = &si->si_funcs[func]; 1166 if (fi->fi_devi == NULL) 1167 continue; 1168 pci_lintr_route(fi->fi_devi); 1169 } 1170 } 1171 } 1172 lpc_pirq_routed(); 1173 1174 /* 1175 * The guest physical memory map looks like the following: 1176 * [0, lowmem) guest system memory 1177 * [lowmem, lowmem_limit) memory hole (may be absent) 1178 * [lowmem_limit, 0xE0000000) PCI hole (32-bit BAR allocation) 1179 * [0xE0000000, 0xF0000000) PCI extended config window 1180 * [0xF0000000, 4GB) LAPIC, IOAPIC, HPET, firmware 1181 * [4GB, 4GB + highmem) 1182 */ 1183 1184 /* 1185 * Accesses to memory addresses that are not allocated to system 1186 * memory or PCI devices return 0xff's. 1187 */ 1188 lowmem = vm_get_lowmem_size(ctx); 1189 bzero(&mr, sizeof(struct mem_range)); 1190 mr.name = "PCI hole"; 1191 mr.flags = MEM_F_RW | MEM_F_IMMUTABLE; 1192 mr.base = lowmem; 1193 mr.size = (4ULL * 1024 * 1024 * 1024) - lowmem; 1194 mr.handler = pci_emul_fallback_handler; 1195 error = register_mem_fallback(&mr); 1196 assert(error == 0); 1197 1198 /* PCI extended config space */ 1199 bzero(&mr, sizeof(struct mem_range)); 1200 mr.name = "PCI ECFG"; 1201 mr.flags = MEM_F_RW | MEM_F_IMMUTABLE; 1202 mr.base = PCI_EMUL_ECFG_BASE; 1203 mr.size = PCI_EMUL_ECFG_SIZE; 1204 mr.handler = pci_emul_ecfg_handler; 1205 error = register_mem(&mr); 1206 assert(error == 0); 1207 1208 return (0); 1209 } 1210 1211 static void 1212 pci_apic_prt_entry(int bus, int slot, int pin, int pirq_pin, int ioapic_irq, 1213 void *arg) 1214 { 1215 1216 dsdt_line(" Package ()"); 1217 dsdt_line(" {"); 1218 dsdt_line(" 0x%X,", slot << 16 | 0xffff); 1219 dsdt_line(" 0x%02X,", pin - 1); 1220 dsdt_line(" Zero,"); 1221 dsdt_line(" 0x%X", ioapic_irq); 1222 dsdt_line(" },"); 1223 } 1224 1225 static void 1226 pci_pirq_prt_entry(int bus, int slot, int pin, int pirq_pin, int ioapic_irq, 1227 void *arg) 1228 { 1229 char *name; 1230 1231 name = lpc_pirq_name(pirq_pin); 1232 if (name == NULL) 1233 return; 1234 dsdt_line(" Package ()"); 1235 dsdt_line(" {"); 1236 dsdt_line(" 0x%X,", slot << 16 | 0xffff); 1237 dsdt_line(" 0x%02X,", pin - 1); 1238 dsdt_line(" %s,", name); 1239 dsdt_line(" 0x00"); 1240 dsdt_line(" },"); 1241 free(name); 1242 } 1243 1244 /* 1245 * A bhyve virtual machine has a flat PCI hierarchy with a root port 1246 * corresponding to each PCI bus. 1247 */ 1248 static void 1249 pci_bus_write_dsdt(int bus) 1250 { 1251 struct businfo *bi; 1252 struct slotinfo *si; 1253 struct pci_devinst *pi; 1254 int count, func, slot; 1255 1256 /* 1257 * If there are no devices on this 'bus' then just return. 1258 */ 1259 if ((bi = pci_businfo[bus]) == NULL) { 1260 /* 1261 * Bus 0 is special because it decodes the I/O ports used 1262 * for PCI config space access even if there are no devices 1263 * on it. 1264 */ 1265 if (bus != 0) 1266 return; 1267 } 1268 1269 dsdt_line(" Device (PC%02X)", bus); 1270 dsdt_line(" {"); 1271 dsdt_line(" Name (_HID, EisaId (\"PNP0A03\"))"); 1272 1273 dsdt_line(" Method (_BBN, 0, NotSerialized)"); 1274 dsdt_line(" {"); 1275 dsdt_line(" Return (0x%08X)", bus); 1276 dsdt_line(" }"); 1277 dsdt_line(" Name (_CRS, ResourceTemplate ()"); 1278 dsdt_line(" {"); 1279 dsdt_line(" WordBusNumber (ResourceProducer, MinFixed, " 1280 "MaxFixed, PosDecode,"); 1281 dsdt_line(" 0x0000, // Granularity"); 1282 dsdt_line(" 0x%04X, // Range Minimum", bus); 1283 dsdt_line(" 0x%04X, // Range Maximum", bus); 1284 dsdt_line(" 0x0000, // Translation Offset"); 1285 dsdt_line(" 0x0001, // Length"); 1286 dsdt_line(" ,, )"); 1287 1288 if (bus == 0) { 1289 dsdt_indent(3); 1290 dsdt_fixed_ioport(0xCF8, 8); 1291 dsdt_unindent(3); 1292 1293 dsdt_line(" WordIO (ResourceProducer, MinFixed, MaxFixed, " 1294 "PosDecode, EntireRange,"); 1295 dsdt_line(" 0x0000, // Granularity"); 1296 dsdt_line(" 0x0000, // Range Minimum"); 1297 dsdt_line(" 0x0CF7, // Range Maximum"); 1298 dsdt_line(" 0x0000, // Translation Offset"); 1299 dsdt_line(" 0x0CF8, // Length"); 1300 dsdt_line(" ,, , TypeStatic)"); 1301 1302 dsdt_line(" WordIO (ResourceProducer, MinFixed, MaxFixed, " 1303 "PosDecode, EntireRange,"); 1304 dsdt_line(" 0x0000, // Granularity"); 1305 dsdt_line(" 0x0D00, // Range Minimum"); 1306 dsdt_line(" 0x%04X, // Range Maximum", 1307 PCI_EMUL_IOBASE - 1); 1308 dsdt_line(" 0x0000, // Translation Offset"); 1309 dsdt_line(" 0x%04X, // Length", 1310 PCI_EMUL_IOBASE - 0x0D00); 1311 dsdt_line(" ,, , TypeStatic)"); 1312 1313 if (bi == NULL) { 1314 dsdt_line(" })"); 1315 goto done; 1316 } 1317 } 1318 assert(bi != NULL); 1319 1320 /* i/o window */ 1321 dsdt_line(" WordIO (ResourceProducer, MinFixed, MaxFixed, " 1322 "PosDecode, EntireRange,"); 1323 dsdt_line(" 0x0000, // Granularity"); 1324 dsdt_line(" 0x%04X, // Range Minimum", bi->iobase); 1325 dsdt_line(" 0x%04X, // Range Maximum", 1326 bi->iolimit - 1); 1327 dsdt_line(" 0x0000, // Translation Offset"); 1328 dsdt_line(" 0x%04X, // Length", 1329 bi->iolimit - bi->iobase); 1330 dsdt_line(" ,, , TypeStatic)"); 1331 1332 /* mmio window (32-bit) */ 1333 dsdt_line(" DWordMemory (ResourceProducer, PosDecode, " 1334 "MinFixed, MaxFixed, NonCacheable, ReadWrite,"); 1335 dsdt_line(" 0x00000000, // Granularity"); 1336 dsdt_line(" 0x%08X, // Range Minimum\n", bi->membase32); 1337 dsdt_line(" 0x%08X, // Range Maximum\n", 1338 bi->memlimit32 - 1); 1339 dsdt_line(" 0x00000000, // Translation Offset"); 1340 dsdt_line(" 0x%08X, // Length\n", 1341 bi->memlimit32 - bi->membase32); 1342 dsdt_line(" ,, , AddressRangeMemory, TypeStatic)"); 1343 1344 /* mmio window (64-bit) */ 1345 dsdt_line(" QWordMemory (ResourceProducer, PosDecode, " 1346 "MinFixed, MaxFixed, NonCacheable, ReadWrite,"); 1347 dsdt_line(" 0x0000000000000000, // Granularity"); 1348 dsdt_line(" 0x%016lX, // Range Minimum\n", bi->membase64); 1349 dsdt_line(" 0x%016lX, // Range Maximum\n", 1350 bi->memlimit64 - 1); 1351 dsdt_line(" 0x0000000000000000, // Translation Offset"); 1352 dsdt_line(" 0x%016lX, // Length\n", 1353 bi->memlimit64 - bi->membase64); 1354 dsdt_line(" ,, , AddressRangeMemory, TypeStatic)"); 1355 dsdt_line(" })"); 1356 1357 count = pci_count_lintr(bus); 1358 if (count != 0) { 1359 dsdt_indent(2); 1360 dsdt_line("Name (PPRT, Package ()"); 1361 dsdt_line("{"); 1362 pci_walk_lintr(bus, pci_pirq_prt_entry, NULL); 1363 dsdt_line("})"); 1364 dsdt_line("Name (APRT, Package ()"); 1365 dsdt_line("{"); 1366 pci_walk_lintr(bus, pci_apic_prt_entry, NULL); 1367 dsdt_line("})"); 1368 dsdt_line("Method (_PRT, 0, NotSerialized)"); 1369 dsdt_line("{"); 1370 dsdt_line(" If (PICM)"); 1371 dsdt_line(" {"); 1372 dsdt_line(" Return (APRT)"); 1373 dsdt_line(" }"); 1374 dsdt_line(" Else"); 1375 dsdt_line(" {"); 1376 dsdt_line(" Return (PPRT)"); 1377 dsdt_line(" }"); 1378 dsdt_line("}"); 1379 dsdt_unindent(2); 1380 } 1381 1382 dsdt_indent(2); 1383 for (slot = 0; slot < MAXSLOTS; slot++) { 1384 si = &bi->slotinfo[slot]; 1385 for (func = 0; func < MAXFUNCS; func++) { 1386 pi = si->si_funcs[func].fi_devi; 1387 if (pi != NULL && pi->pi_d->pe_write_dsdt != NULL) 1388 pi->pi_d->pe_write_dsdt(pi); 1389 } 1390 } 1391 dsdt_unindent(2); 1392 done: 1393 dsdt_line(" }"); 1394 } 1395 1396 void 1397 pci_write_dsdt(void) 1398 { 1399 int bus; 1400 1401 dsdt_indent(1); 1402 dsdt_line("Name (PICM, 0x00)"); 1403 dsdt_line("Method (_PIC, 1, NotSerialized)"); 1404 dsdt_line("{"); 1405 dsdt_line(" Store (Arg0, PICM)"); 1406 dsdt_line("}"); 1407 dsdt_line(""); 1408 dsdt_line("Scope (_SB)"); 1409 dsdt_line("{"); 1410 for (bus = 0; bus < MAXBUSES; bus++) 1411 pci_bus_write_dsdt(bus); 1412 dsdt_line("}"); 1413 dsdt_unindent(1); 1414 } 1415 1416 int 1417 pci_bus_configured(int bus) 1418 { 1419 assert(bus >= 0 && bus < MAXBUSES); 1420 return (pci_businfo[bus] != NULL); 1421 } 1422 1423 int 1424 pci_msi_enabled(struct pci_devinst *pi) 1425 { 1426 return (pi->pi_msi.enabled); 1427 } 1428 1429 int 1430 pci_msi_maxmsgnum(struct pci_devinst *pi) 1431 { 1432 if (pi->pi_msi.enabled) 1433 return (pi->pi_msi.maxmsgnum); 1434 else 1435 return (0); 1436 } 1437 1438 int 1439 pci_msix_enabled(struct pci_devinst *pi) 1440 { 1441 1442 return (pi->pi_msix.enabled && !pi->pi_msi.enabled); 1443 } 1444 1445 void 1446 pci_generate_msix(struct pci_devinst *pi, int index) 1447 { 1448 struct msix_table_entry *mte; 1449 1450 if (!pci_msix_enabled(pi)) 1451 return; 1452 1453 if (pi->pi_msix.function_mask) 1454 return; 1455 1456 if (index >= pi->pi_msix.table_count) 1457 return; 1458 1459 mte = &pi->pi_msix.table[index]; 1460 if ((mte->vector_control & PCIM_MSIX_VCTRL_MASK) == 0) { 1461 /* XXX Set PBA bit if interrupt is disabled */ 1462 vm_lapic_msi(pi->pi_vmctx, mte->addr, mte->msg_data); 1463 } 1464 } 1465 1466 void 1467 pci_generate_msi(struct pci_devinst *pi, int index) 1468 { 1469 1470 if (pci_msi_enabled(pi) && index < pci_msi_maxmsgnum(pi)) { 1471 vm_lapic_msi(pi->pi_vmctx, pi->pi_msi.addr, 1472 pi->pi_msi.msg_data + index); 1473 } 1474 } 1475 1476 static bool 1477 pci_lintr_permitted(struct pci_devinst *pi) 1478 { 1479 uint16_t cmd; 1480 1481 cmd = pci_get_cfgdata16(pi, PCIR_COMMAND); 1482 return (!(pi->pi_msi.enabled || pi->pi_msix.enabled || 1483 (cmd & PCIM_CMD_INTxDIS))); 1484 } 1485 1486 void 1487 pci_lintr_request(struct pci_devinst *pi) 1488 { 1489 struct businfo *bi; 1490 struct slotinfo *si; 1491 int bestpin, bestcount, pin; 1492 1493 bi = pci_businfo[pi->pi_bus]; 1494 assert(bi != NULL); 1495 1496 /* 1497 * Just allocate a pin from our slot. The pin will be 1498 * assigned IRQs later when interrupts are routed. 1499 */ 1500 si = &bi->slotinfo[pi->pi_slot]; 1501 bestpin = 0; 1502 bestcount = si->si_intpins[0].ii_count; 1503 for (pin = 1; pin < 4; pin++) { 1504 if (si->si_intpins[pin].ii_count < bestcount) { 1505 bestpin = pin; 1506 bestcount = si->si_intpins[pin].ii_count; 1507 } 1508 } 1509 1510 si->si_intpins[bestpin].ii_count++; 1511 pi->pi_lintr.pin = bestpin + 1; 1512 pci_set_cfgdata8(pi, PCIR_INTPIN, bestpin + 1); 1513 } 1514 1515 static void 1516 pci_lintr_route(struct pci_devinst *pi) 1517 { 1518 struct businfo *bi; 1519 struct intxinfo *ii; 1520 1521 if (pi->pi_lintr.pin == 0) 1522 return; 1523 1524 bi = pci_businfo[pi->pi_bus]; 1525 assert(bi != NULL); 1526 ii = &bi->slotinfo[pi->pi_slot].si_intpins[pi->pi_lintr.pin - 1]; 1527 1528 /* 1529 * Attempt to allocate an I/O APIC pin for this intpin if one 1530 * is not yet assigned. 1531 */ 1532 if (ii->ii_ioapic_irq == 0) 1533 ii->ii_ioapic_irq = ioapic_pci_alloc_irq(pi); 1534 assert(ii->ii_ioapic_irq > 0); 1535 1536 /* 1537 * Attempt to allocate a PIRQ pin for this intpin if one is 1538 * not yet assigned. 1539 */ 1540 if (ii->ii_pirq_pin == 0) 1541 ii->ii_pirq_pin = pirq_alloc_pin(pi); 1542 assert(ii->ii_pirq_pin > 0); 1543 1544 pi->pi_lintr.ioapic_irq = ii->ii_ioapic_irq; 1545 pi->pi_lintr.pirq_pin = ii->ii_pirq_pin; 1546 pci_set_cfgdata8(pi, PCIR_INTLINE, pirq_irq(ii->ii_pirq_pin)); 1547 } 1548 1549 void 1550 pci_lintr_assert(struct pci_devinst *pi) 1551 { 1552 1553 assert(pi->pi_lintr.pin > 0); 1554 1555 pthread_mutex_lock(&pi->pi_lintr.lock); 1556 if (pi->pi_lintr.state == IDLE) { 1557 if (pci_lintr_permitted(pi)) { 1558 pi->pi_lintr.state = ASSERTED; 1559 pci_irq_assert(pi); 1560 } else 1561 pi->pi_lintr.state = PENDING; 1562 } 1563 pthread_mutex_unlock(&pi->pi_lintr.lock); 1564 } 1565 1566 void 1567 pci_lintr_deassert(struct pci_devinst *pi) 1568 { 1569 1570 assert(pi->pi_lintr.pin > 0); 1571 1572 pthread_mutex_lock(&pi->pi_lintr.lock); 1573 if (pi->pi_lintr.state == ASSERTED) { 1574 pi->pi_lintr.state = IDLE; 1575 pci_irq_deassert(pi); 1576 } else if (pi->pi_lintr.state == PENDING) 1577 pi->pi_lintr.state = IDLE; 1578 pthread_mutex_unlock(&pi->pi_lintr.lock); 1579 } 1580 1581 static void 1582 pci_lintr_update(struct pci_devinst *pi) 1583 { 1584 1585 pthread_mutex_lock(&pi->pi_lintr.lock); 1586 if (pi->pi_lintr.state == ASSERTED && !pci_lintr_permitted(pi)) { 1587 pci_irq_deassert(pi); 1588 pi->pi_lintr.state = PENDING; 1589 } else if (pi->pi_lintr.state == PENDING && pci_lintr_permitted(pi)) { 1590 pi->pi_lintr.state = ASSERTED; 1591 pci_irq_assert(pi); 1592 } 1593 pthread_mutex_unlock(&pi->pi_lintr.lock); 1594 } 1595 1596 int 1597 pci_count_lintr(int bus) 1598 { 1599 int count, slot, pin; 1600 struct slotinfo *slotinfo; 1601 1602 count = 0; 1603 if (pci_businfo[bus] != NULL) { 1604 for (slot = 0; slot < MAXSLOTS; slot++) { 1605 slotinfo = &pci_businfo[bus]->slotinfo[slot]; 1606 for (pin = 0; pin < 4; pin++) { 1607 if (slotinfo->si_intpins[pin].ii_count != 0) 1608 count++; 1609 } 1610 } 1611 } 1612 return (count); 1613 } 1614 1615 void 1616 pci_walk_lintr(int bus, pci_lintr_cb cb, void *arg) 1617 { 1618 struct businfo *bi; 1619 struct slotinfo *si; 1620 struct intxinfo *ii; 1621 int slot, pin; 1622 1623 if ((bi = pci_businfo[bus]) == NULL) 1624 return; 1625 1626 for (slot = 0; slot < MAXSLOTS; slot++) { 1627 si = &bi->slotinfo[slot]; 1628 for (pin = 0; pin < 4; pin++) { 1629 ii = &si->si_intpins[pin]; 1630 if (ii->ii_count != 0) 1631 cb(bus, slot, pin + 1, ii->ii_pirq_pin, 1632 ii->ii_ioapic_irq, arg); 1633 } 1634 } 1635 } 1636 1637 /* 1638 * Return 1 if the emulated device in 'slot' is a multi-function device. 1639 * Return 0 otherwise. 1640 */ 1641 static int 1642 pci_emul_is_mfdev(int bus, int slot) 1643 { 1644 struct businfo *bi; 1645 struct slotinfo *si; 1646 int f, numfuncs; 1647 1648 numfuncs = 0; 1649 if ((bi = pci_businfo[bus]) != NULL) { 1650 si = &bi->slotinfo[slot]; 1651 for (f = 0; f < MAXFUNCS; f++) { 1652 if (si->si_funcs[f].fi_devi != NULL) { 1653 numfuncs++; 1654 } 1655 } 1656 } 1657 return (numfuncs > 1); 1658 } 1659 1660 /* 1661 * Ensure that the PCIM_MFDEV bit is properly set (or unset) depending on 1662 * whether or not is a multi-function being emulated in the pci 'slot'. 1663 */ 1664 static void 1665 pci_emul_hdrtype_fixup(int bus, int slot, int off, int bytes, uint32_t *rv) 1666 { 1667 int mfdev; 1668 1669 if (off <= PCIR_HDRTYPE && off + bytes > PCIR_HDRTYPE) { 1670 mfdev = pci_emul_is_mfdev(bus, slot); 1671 switch (bytes) { 1672 case 1: 1673 case 2: 1674 *rv &= ~PCIM_MFDEV; 1675 if (mfdev) { 1676 *rv |= PCIM_MFDEV; 1677 } 1678 break; 1679 case 4: 1680 *rv &= ~(PCIM_MFDEV << 16); 1681 if (mfdev) { 1682 *rv |= (PCIM_MFDEV << 16); 1683 } 1684 break; 1685 } 1686 } 1687 } 1688 1689 /* 1690 * Update device state in response to changes to the PCI command 1691 * register. 1692 */ 1693 void 1694 pci_emul_cmd_changed(struct pci_devinst *pi, uint16_t old) 1695 { 1696 int i; 1697 uint16_t changed, new; 1698 1699 new = pci_get_cfgdata16(pi, PCIR_COMMAND); 1700 changed = old ^ new; 1701 1702 /* 1703 * If the MMIO or I/O address space decoding has changed then 1704 * register/unregister all BARs that decode that address space. 1705 */ 1706 for (i = 0; i <= PCI_BARMAX; i++) { 1707 switch (pi->pi_bar[i].type) { 1708 case PCIBAR_NONE: 1709 case PCIBAR_MEMHI64: 1710 break; 1711 case PCIBAR_IO: 1712 /* I/O address space decoding changed? */ 1713 if (changed & PCIM_CMD_PORTEN) { 1714 if (new & PCIM_CMD_PORTEN) 1715 register_bar(pi, i); 1716 else 1717 unregister_bar(pi, i); 1718 } 1719 break; 1720 case PCIBAR_MEM32: 1721 case PCIBAR_MEM64: 1722 /* MMIO address space decoding changed? */ 1723 if (changed & PCIM_CMD_MEMEN) { 1724 if (new & PCIM_CMD_MEMEN) 1725 register_bar(pi, i); 1726 else 1727 unregister_bar(pi, i); 1728 } 1729 break; 1730 default: 1731 assert(0); 1732 } 1733 } 1734 1735 /* 1736 * If INTx has been unmasked and is pending, assert the 1737 * interrupt. 1738 */ 1739 pci_lintr_update(pi); 1740 } 1741 1742 static void 1743 pci_emul_cmdsts_write(struct pci_devinst *pi, int coff, uint32_t new, int bytes) 1744 { 1745 int rshift; 1746 uint32_t cmd, old, readonly; 1747 1748 cmd = pci_get_cfgdata16(pi, PCIR_COMMAND); /* stash old value */ 1749 1750 /* 1751 * From PCI Local Bus Specification 3.0 sections 6.2.2 and 6.2.3. 1752 * 1753 * XXX Bits 8, 11, 12, 13, 14 and 15 in the status register are 1754 * 'write 1 to clear'. However these bits are not set to '1' by 1755 * any device emulation so it is simpler to treat them as readonly. 1756 */ 1757 rshift = (coff & 0x3) * 8; 1758 readonly = 0xFFFFF880 >> rshift; 1759 1760 old = CFGREAD(pi, coff, bytes); 1761 new &= ~readonly; 1762 new |= (old & readonly); 1763 CFGWRITE(pi, coff, new, bytes); /* update config */ 1764 1765 pci_emul_cmd_changed(pi, cmd); 1766 } 1767 1768 static void 1769 pci_cfgrw(struct vmctx *ctx, int vcpu, int in, int bus, int slot, int func, 1770 int coff, int bytes, uint32_t *eax) 1771 { 1772 struct businfo *bi; 1773 struct slotinfo *si; 1774 struct pci_devinst *pi; 1775 struct pci_devemu *pe; 1776 int idx, needcfg; 1777 uint64_t addr, bar, mask; 1778 1779 if ((bi = pci_businfo[bus]) != NULL) { 1780 si = &bi->slotinfo[slot]; 1781 pi = si->si_funcs[func].fi_devi; 1782 } else 1783 pi = NULL; 1784 1785 /* 1786 * Just return if there is no device at this slot:func or if the 1787 * the guest is doing an un-aligned access. 1788 */ 1789 if (pi == NULL || (bytes != 1 && bytes != 2 && bytes != 4) || 1790 (coff & (bytes - 1)) != 0) { 1791 if (in) 1792 *eax = 0xffffffff; 1793 return; 1794 } 1795 1796 /* 1797 * Ignore all writes beyond the standard config space and return all 1798 * ones on reads. 1799 */ 1800 if (coff >= PCI_REGMAX + 1) { 1801 if (in) { 1802 *eax = 0xffffffff; 1803 /* 1804 * Extended capabilities begin at offset 256 in config 1805 * space. Absence of extended capabilities is signaled 1806 * with all 0s in the extended capability header at 1807 * offset 256. 1808 */ 1809 if (coff <= PCI_REGMAX + 4) 1810 *eax = 0x00000000; 1811 } 1812 return; 1813 } 1814 1815 pe = pi->pi_d; 1816 1817 /* 1818 * Config read 1819 */ 1820 if (in) { 1821 /* Let the device emulation override the default handler */ 1822 if (pe->pe_cfgread != NULL) { 1823 needcfg = pe->pe_cfgread(ctx, vcpu, pi, coff, bytes, 1824 eax); 1825 } else { 1826 needcfg = 1; 1827 } 1828 1829 if (needcfg) 1830 *eax = CFGREAD(pi, coff, bytes); 1831 1832 pci_emul_hdrtype_fixup(bus, slot, coff, bytes, eax); 1833 } else { 1834 /* Let the device emulation override the default handler */ 1835 if (pe->pe_cfgwrite != NULL && 1836 (*pe->pe_cfgwrite)(ctx, vcpu, pi, coff, bytes, *eax) == 0) 1837 return; 1838 1839 /* 1840 * Special handling for write to BAR registers 1841 */ 1842 if (coff >= PCIR_BAR(0) && coff < PCIR_BAR(PCI_BARMAX + 1)) { 1843 /* 1844 * Ignore writes to BAR registers that are not 1845 * 4-byte aligned. 1846 */ 1847 if (bytes != 4 || (coff & 0x3) != 0) 1848 return; 1849 idx = (coff - PCIR_BAR(0)) / 4; 1850 mask = ~(pi->pi_bar[idx].size - 1); 1851 switch (pi->pi_bar[idx].type) { 1852 case PCIBAR_NONE: 1853 pi->pi_bar[idx].addr = bar = 0; 1854 break; 1855 case PCIBAR_IO: 1856 addr = *eax & mask; 1857 addr &= 0xffff; 1858 bar = addr | PCIM_BAR_IO_SPACE; 1859 /* 1860 * Register the new BAR value for interception 1861 */ 1862 if (addr != pi->pi_bar[idx].addr) { 1863 update_bar_address(pi, addr, idx, 1864 PCIBAR_IO); 1865 } 1866 break; 1867 case PCIBAR_MEM32: 1868 addr = bar = *eax & mask; 1869 bar |= PCIM_BAR_MEM_SPACE | PCIM_BAR_MEM_32; 1870 if (addr != pi->pi_bar[idx].addr) { 1871 update_bar_address(pi, addr, idx, 1872 PCIBAR_MEM32); 1873 } 1874 break; 1875 case PCIBAR_MEM64: 1876 addr = bar = *eax & mask; 1877 bar |= PCIM_BAR_MEM_SPACE | PCIM_BAR_MEM_64 | 1878 PCIM_BAR_MEM_PREFETCH; 1879 if (addr != (uint32_t)pi->pi_bar[idx].addr) { 1880 update_bar_address(pi, addr, idx, 1881 PCIBAR_MEM64); 1882 } 1883 break; 1884 case PCIBAR_MEMHI64: 1885 mask = ~(pi->pi_bar[idx - 1].size - 1); 1886 addr = ((uint64_t)*eax << 32) & mask; 1887 bar = addr >> 32; 1888 if (bar != pi->pi_bar[idx - 1].addr >> 32) { 1889 update_bar_address(pi, addr, idx - 1, 1890 PCIBAR_MEMHI64); 1891 } 1892 break; 1893 default: 1894 assert(0); 1895 } 1896 pci_set_cfgdata32(pi, coff, bar); 1897 1898 } else if (pci_emul_iscap(pi, coff)) { 1899 pci_emul_capwrite(pi, coff, bytes, *eax); 1900 } else if (coff >= PCIR_COMMAND && coff < PCIR_REVID) { 1901 pci_emul_cmdsts_write(pi, coff, *eax, bytes); 1902 } else { 1903 CFGWRITE(pi, coff, *eax, bytes); 1904 } 1905 } 1906 } 1907 1908 static int cfgenable, cfgbus, cfgslot, cfgfunc, cfgoff; 1909 1910 static int 1911 pci_emul_cfgaddr(struct vmctx *ctx, int vcpu, int in, int port, int bytes, 1912 uint32_t *eax, void *arg) 1913 { 1914 uint32_t x; 1915 1916 if (bytes != 4) { 1917 if (in) 1918 *eax = (bytes == 2) ? 0xffff : 0xff; 1919 return (0); 1920 } 1921 1922 if (in) { 1923 x = (cfgbus << 16) | (cfgslot << 11) | (cfgfunc << 8) | cfgoff; 1924 if (cfgenable) 1925 x |= CONF1_ENABLE; 1926 *eax = x; 1927 } else { 1928 x = *eax; 1929 cfgenable = (x & CONF1_ENABLE) == CONF1_ENABLE; 1930 cfgoff = x & PCI_REGMAX; 1931 cfgfunc = (x >> 8) & PCI_FUNCMAX; 1932 cfgslot = (x >> 11) & PCI_SLOTMAX; 1933 cfgbus = (x >> 16) & PCI_BUSMAX; 1934 } 1935 1936 return (0); 1937 } 1938 INOUT_PORT(pci_cfgaddr, CONF1_ADDR_PORT, IOPORT_F_INOUT, pci_emul_cfgaddr); 1939 1940 static int 1941 pci_emul_cfgdata(struct vmctx *ctx, int vcpu, int in, int port, int bytes, 1942 uint32_t *eax, void *arg) 1943 { 1944 int coff; 1945 1946 assert(bytes == 1 || bytes == 2 || bytes == 4); 1947 1948 coff = cfgoff + (port - CONF1_DATA_PORT); 1949 if (cfgenable) { 1950 pci_cfgrw(ctx, vcpu, in, cfgbus, cfgslot, cfgfunc, coff, bytes, 1951 eax); 1952 } else { 1953 /* Ignore accesses to cfgdata if not enabled by cfgaddr */ 1954 if (in) 1955 *eax = 0xffffffff; 1956 } 1957 return (0); 1958 } 1959 1960 INOUT_PORT(pci_cfgdata, CONF1_DATA_PORT+0, IOPORT_F_INOUT, pci_emul_cfgdata); 1961 INOUT_PORT(pci_cfgdata, CONF1_DATA_PORT+1, IOPORT_F_INOUT, pci_emul_cfgdata); 1962 INOUT_PORT(pci_cfgdata, CONF1_DATA_PORT+2, IOPORT_F_INOUT, pci_emul_cfgdata); 1963 INOUT_PORT(pci_cfgdata, CONF1_DATA_PORT+3, IOPORT_F_INOUT, pci_emul_cfgdata); 1964 1965 #define PCI_EMUL_TEST 1966 #ifdef PCI_EMUL_TEST 1967 /* 1968 * Define a dummy test device 1969 */ 1970 #define DIOSZ 8 1971 #define DMEMSZ 4096 1972 struct pci_emul_dsoftc { 1973 uint8_t ioregs[DIOSZ]; 1974 uint8_t memregs[2][DMEMSZ]; 1975 }; 1976 1977 #define PCI_EMUL_MSI_MSGS 4 1978 #define PCI_EMUL_MSIX_MSGS 16 1979 1980 static int 1981 pci_emul_dinit(struct vmctx *ctx, struct pci_devinst *pi, char *opts) 1982 { 1983 int error; 1984 struct pci_emul_dsoftc *sc; 1985 1986 sc = calloc(1, sizeof(struct pci_emul_dsoftc)); 1987 1988 pi->pi_arg = sc; 1989 1990 pci_set_cfgdata16(pi, PCIR_DEVICE, 0x0001); 1991 pci_set_cfgdata16(pi, PCIR_VENDOR, 0x10DD); 1992 pci_set_cfgdata8(pi, PCIR_CLASS, 0x02); 1993 1994 error = pci_emul_add_msicap(pi, PCI_EMUL_MSI_MSGS); 1995 assert(error == 0); 1996 1997 error = pci_emul_alloc_bar(pi, 0, PCIBAR_IO, DIOSZ); 1998 assert(error == 0); 1999 2000 error = pci_emul_alloc_bar(pi, 1, PCIBAR_MEM32, DMEMSZ); 2001 assert(error == 0); 2002 2003 error = pci_emul_alloc_bar(pi, 2, PCIBAR_MEM32, DMEMSZ); 2004 assert(error == 0); 2005 2006 return (0); 2007 } 2008 2009 static void 2010 pci_emul_diow(struct vmctx *ctx, int vcpu, struct pci_devinst *pi, int baridx, 2011 uint64_t offset, int size, uint64_t value) 2012 { 2013 int i; 2014 struct pci_emul_dsoftc *sc = pi->pi_arg; 2015 2016 if (baridx == 0) { 2017 if (offset + size > DIOSZ) { 2018 printf("diow: iow too large, offset %ld size %d\n", 2019 offset, size); 2020 return; 2021 } 2022 2023 if (size == 1) { 2024 sc->ioregs[offset] = value & 0xff; 2025 } else if (size == 2) { 2026 *(uint16_t *)&sc->ioregs[offset] = value & 0xffff; 2027 } else if (size == 4) { 2028 *(uint32_t *)&sc->ioregs[offset] = value; 2029 } else { 2030 printf("diow: iow unknown size %d\n", size); 2031 } 2032 2033 /* 2034 * Special magic value to generate an interrupt 2035 */ 2036 if (offset == 4 && size == 4 && pci_msi_enabled(pi)) 2037 pci_generate_msi(pi, value % pci_msi_maxmsgnum(pi)); 2038 2039 if (value == 0xabcdef) { 2040 for (i = 0; i < pci_msi_maxmsgnum(pi); i++) 2041 pci_generate_msi(pi, i); 2042 } 2043 } 2044 2045 if (baridx == 1 || baridx == 2) { 2046 if (offset + size > DMEMSZ) { 2047 printf("diow: memw too large, offset %ld size %d\n", 2048 offset, size); 2049 return; 2050 } 2051 2052 i = baridx - 1; /* 'memregs' index */ 2053 2054 if (size == 1) { 2055 sc->memregs[i][offset] = value; 2056 } else if (size == 2) { 2057 *(uint16_t *)&sc->memregs[i][offset] = value; 2058 } else if (size == 4) { 2059 *(uint32_t *)&sc->memregs[i][offset] = value; 2060 } else if (size == 8) { 2061 *(uint64_t *)&sc->memregs[i][offset] = value; 2062 } else { 2063 printf("diow: memw unknown size %d\n", size); 2064 } 2065 2066 /* 2067 * magic interrupt ?? 2068 */ 2069 } 2070 2071 if (baridx > 2 || baridx < 0) { 2072 printf("diow: unknown bar idx %d\n", baridx); 2073 } 2074 } 2075 2076 static uint64_t 2077 pci_emul_dior(struct vmctx *ctx, int vcpu, struct pci_devinst *pi, int baridx, 2078 uint64_t offset, int size) 2079 { 2080 struct pci_emul_dsoftc *sc = pi->pi_arg; 2081 uint32_t value; 2082 int i; 2083 2084 if (baridx == 0) { 2085 if (offset + size > DIOSZ) { 2086 printf("dior: ior too large, offset %ld size %d\n", 2087 offset, size); 2088 return (0); 2089 } 2090 2091 value = 0; 2092 if (size == 1) { 2093 value = sc->ioregs[offset]; 2094 } else if (size == 2) { 2095 value = *(uint16_t *) &sc->ioregs[offset]; 2096 } else if (size == 4) { 2097 value = *(uint32_t *) &sc->ioregs[offset]; 2098 } else { 2099 printf("dior: ior unknown size %d\n", size); 2100 } 2101 } 2102 2103 if (baridx == 1 || baridx == 2) { 2104 if (offset + size > DMEMSZ) { 2105 printf("dior: memr too large, offset %ld size %d\n", 2106 offset, size); 2107 return (0); 2108 } 2109 2110 i = baridx - 1; /* 'memregs' index */ 2111 2112 if (size == 1) { 2113 value = sc->memregs[i][offset]; 2114 } else if (size == 2) { 2115 value = *(uint16_t *) &sc->memregs[i][offset]; 2116 } else if (size == 4) { 2117 value = *(uint32_t *) &sc->memregs[i][offset]; 2118 } else if (size == 8) { 2119 value = *(uint64_t *) &sc->memregs[i][offset]; 2120 } else { 2121 printf("dior: ior unknown size %d\n", size); 2122 } 2123 } 2124 2125 2126 if (baridx > 2 || baridx < 0) { 2127 printf("dior: unknown bar idx %d\n", baridx); 2128 return (0); 2129 } 2130 2131 return (value); 2132 } 2133 2134 struct pci_devemu pci_dummy = { 2135 .pe_emu = "dummy", 2136 .pe_init = pci_emul_dinit, 2137 .pe_barwrite = pci_emul_diow, 2138 .pe_barread = pci_emul_dior 2139 }; 2140 PCI_EMUL_SET(pci_dummy); 2141 2142 #endif /* PCI_EMUL_TEST */ 2143