1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD 3 * 4 * Copyright (c) 2011 NetApp, Inc. 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY NETAPP, INC ``AS IS'' AND 17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 19 * ARE DISCLAIMED. IN NO EVENT SHALL NETAPP, INC OR CONTRIBUTORS BE LIABLE 20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 * 28 * $FreeBSD$ 29 */ 30 31 #ifndef _PCI_EMUL_H_ 32 #define _PCI_EMUL_H_ 33 34 #include <sys/types.h> 35 #include <sys/queue.h> 36 #include <sys/kernel.h> 37 #include <sys/nv.h> 38 #include <sys/pciio.h> 39 #include <sys/_pthreadtypes.h> 40 41 #include <dev/pci/pcireg.h> 42 43 #include <assert.h> 44 45 #define PCI_BARMAX PCIR_MAX_BAR_0 /* BAR registers in a Type 0 header */ 46 #define PCI_BARMAX_WITH_ROM (PCI_BARMAX + 1) 47 #define PCI_ROM_IDX (PCI_BARMAX + 1) 48 49 struct vmctx; 50 struct pci_devinst; 51 struct memory_region; 52 struct vm_snapshot_meta; 53 54 struct pci_devemu { 55 const char *pe_emu; /* Name of device emulation */ 56 57 /* instance creation */ 58 int (*pe_init)(struct pci_devinst *, nvlist_t *); 59 int (*pe_legacy_config)(nvlist_t *, const char *); 60 const char *pe_alias; 61 62 /* ACPI DSDT enumeration */ 63 void (*pe_write_dsdt)(struct pci_devinst *); 64 65 /* config space read/write callbacks */ 66 int (*pe_cfgwrite)(struct pci_devinst *pi, int offset, 67 int bytes, uint32_t val); 68 int (*pe_cfgread)(struct pci_devinst *pi, int offset, 69 int bytes, uint32_t *retval); 70 71 /* BAR read/write callbacks */ 72 void (*pe_barwrite)(struct pci_devinst *pi, int baridx, 73 uint64_t offset, int size, uint64_t value); 74 uint64_t (*pe_barread)(struct pci_devinst *pi, int baridx, 75 uint64_t offset, int size); 76 77 void (*pe_baraddr)(struct pci_devinst *pi, 78 int baridx, int enabled, uint64_t address); 79 80 /* Save/restore device state */ 81 int (*pe_snapshot)(struct vm_snapshot_meta *meta); 82 int (*pe_pause)(struct pci_devinst *pi); 83 int (*pe_resume)(struct pci_devinst *pi); 84 85 }; 86 #define PCI_EMUL_SET(x) DATA_SET(pci_devemu_set, x) 87 88 enum pcibar_type { 89 PCIBAR_NONE, 90 PCIBAR_IO, 91 PCIBAR_MEM32, 92 PCIBAR_MEM64, 93 PCIBAR_MEMHI64, 94 PCIBAR_ROM, 95 }; 96 97 struct pcibar { 98 enum pcibar_type type; /* io or memory */ 99 uint64_t size; 100 uint64_t addr; 101 uint8_t lobits; 102 }; 103 104 #define PI_NAMESZ 40 105 106 struct msix_table_entry { 107 uint64_t addr; 108 uint32_t msg_data; 109 uint32_t vector_control; 110 } __packed; 111 112 /* 113 * In case the structure is modified to hold extra information, use a define 114 * for the size that should be emulated. 115 */ 116 #define MSIX_TABLE_ENTRY_SIZE 16 117 #define MAX_MSIX_TABLE_ENTRIES 2048 118 #define PBA_SIZE(msgnum) (roundup2((msgnum), 64) / 8) 119 120 enum lintr_stat { 121 IDLE, 122 ASSERTED, 123 PENDING 124 }; 125 126 struct pci_devinst { 127 struct pci_devemu *pi_d; 128 struct vmctx *pi_vmctx; 129 uint8_t pi_bus, pi_slot, pi_func; 130 char pi_name[PI_NAMESZ]; 131 int pi_bar_getsize; 132 int pi_prevcap; 133 int pi_capend; 134 135 struct { 136 int8_t pin; 137 enum lintr_stat state; 138 int pirq_pin; 139 int ioapic_irq; 140 pthread_mutex_t lock; 141 } pi_lintr; 142 143 struct { 144 int enabled; 145 uint64_t addr; 146 uint64_t msg_data; 147 int maxmsgnum; 148 } pi_msi; 149 150 struct { 151 int enabled; 152 int table_bar; 153 int pba_bar; 154 uint32_t table_offset; 155 int table_count; 156 uint32_t pba_offset; 157 int pba_size; 158 int function_mask; 159 struct msix_table_entry *table; /* allocated at runtime */ 160 uint8_t *mapped_addr; 161 size_t mapped_size; 162 } pi_msix; 163 164 void *pi_arg; /* devemu-private data */ 165 166 u_char pi_cfgdata[PCI_REGMAX + 1]; 167 /* ROM is handled like a BAR */ 168 struct pcibar pi_bar[PCI_BARMAX_WITH_ROM + 1]; 169 uint64_t pi_romoffset; 170 }; 171 172 struct msicap { 173 uint8_t capid; 174 uint8_t nextptr; 175 uint16_t msgctrl; 176 uint32_t addrlo; 177 uint32_t addrhi; 178 uint16_t msgdata; 179 } __packed; 180 static_assert(sizeof(struct msicap) == 14, "compile-time assertion failed"); 181 182 struct msixcap { 183 uint8_t capid; 184 uint8_t nextptr; 185 uint16_t msgctrl; 186 uint32_t table_info; /* bar index and offset within it */ 187 uint32_t pba_info; /* bar index and offset within it */ 188 } __packed; 189 static_assert(sizeof(struct msixcap) == 12, "compile-time assertion failed"); 190 191 struct pciecap { 192 uint8_t capid; 193 uint8_t nextptr; 194 uint16_t pcie_capabilities; 195 196 uint32_t dev_capabilities; /* all devices */ 197 uint16_t dev_control; 198 uint16_t dev_status; 199 200 uint32_t link_capabilities; /* devices with links */ 201 uint16_t link_control; 202 uint16_t link_status; 203 204 uint32_t slot_capabilities; /* ports with slots */ 205 uint16_t slot_control; 206 uint16_t slot_status; 207 208 uint16_t root_control; /* root ports */ 209 uint16_t root_capabilities; 210 uint32_t root_status; 211 212 uint32_t dev_capabilities2; /* all devices */ 213 uint16_t dev_control2; 214 uint16_t dev_status2; 215 216 uint32_t link_capabilities2; /* devices with links */ 217 uint16_t link_control2; 218 uint16_t link_status2; 219 220 uint32_t slot_capabilities2; /* ports with slots */ 221 uint16_t slot_control2; 222 uint16_t slot_status2; 223 } __packed; 224 static_assert(sizeof(struct pciecap) == 60, "compile-time assertion failed"); 225 226 typedef void (*pci_lintr_cb)(int b, int s, int pin, int pirq_pin, 227 int ioapic_irq, void *arg); 228 229 int init_pci(struct vmctx *ctx); 230 void pci_callback(void); 231 uint32_t pci_config_read_reg(const struct pcisel *host_sel, nvlist_t *nvl, 232 uint32_t reg, uint8_t size, uint32_t def); 233 int pci_emul_alloc_bar(struct pci_devinst *pdi, int idx, 234 enum pcibar_type type, uint64_t size); 235 int pci_emul_alloc_rom(struct pci_devinst *const pdi, const uint64_t size, 236 void **const addr); 237 int pci_emul_add_msicap(struct pci_devinst *pi, int msgnum); 238 int pci_emul_add_pciecap(struct pci_devinst *pi, int pcie_device_type); 239 void pci_emul_capwrite(struct pci_devinst *pi, int offset, int bytes, 240 uint32_t val, uint8_t capoff, int capid); 241 void pci_emul_cmd_changed(struct pci_devinst *pi, uint16_t old); 242 void pci_generate_msi(struct pci_devinst *pi, int msgnum); 243 void pci_generate_msix(struct pci_devinst *pi, int msgnum); 244 void pci_lintr_assert(struct pci_devinst *pi); 245 void pci_lintr_deassert(struct pci_devinst *pi); 246 void pci_lintr_request(struct pci_devinst *pi); 247 int pci_msi_enabled(struct pci_devinst *pi); 248 int pci_msix_enabled(struct pci_devinst *pi); 249 int pci_msix_table_bar(struct pci_devinst *pi); 250 int pci_msix_pba_bar(struct pci_devinst *pi); 251 int pci_msi_maxmsgnum(struct pci_devinst *pi); 252 int pci_parse_legacy_config(nvlist_t *nvl, const char *opt); 253 int pci_parse_slot(char *opt); 254 void pci_print_supported_devices(void); 255 void pci_populate_msicap(struct msicap *cap, int msgs, int nextptr); 256 int pci_emul_add_msixcap(struct pci_devinst *pi, int msgnum, int barnum); 257 int pci_emul_msix_twrite(struct pci_devinst *pi, uint64_t offset, int size, 258 uint64_t value); 259 uint64_t pci_emul_msix_tread(struct pci_devinst *pi, uint64_t offset, int size); 260 int pci_count_lintr(int bus); 261 void pci_walk_lintr(int bus, pci_lintr_cb cb, void *arg); 262 void pci_write_dsdt(void); 263 uint64_t pci_ecfg_base(void); 264 int pci_bus_configured(int bus); 265 #ifdef BHYVE_SNAPSHOT 266 int pci_snapshot(struct vm_snapshot_meta *meta); 267 int pci_pause(const char *dev_name); 268 int pci_resume(const char *dev_name); 269 #endif 270 271 static __inline void 272 pci_set_cfgdata8(struct pci_devinst *pi, int offset, uint8_t val) 273 { 274 assert(offset <= PCI_REGMAX); 275 *(uint8_t *)(pi->pi_cfgdata + offset) = val; 276 } 277 278 static __inline void 279 pci_set_cfgdata16(struct pci_devinst *pi, int offset, uint16_t val) 280 { 281 assert(offset <= (PCI_REGMAX - 1) && (offset & 1) == 0); 282 *(uint16_t *)(pi->pi_cfgdata + offset) = val; 283 } 284 285 static __inline void 286 pci_set_cfgdata32(struct pci_devinst *pi, int offset, uint32_t val) 287 { 288 assert(offset <= (PCI_REGMAX - 3) && (offset & 3) == 0); 289 *(uint32_t *)(pi->pi_cfgdata + offset) = val; 290 } 291 292 static __inline uint8_t 293 pci_get_cfgdata8(struct pci_devinst *pi, int offset) 294 { 295 assert(offset <= PCI_REGMAX); 296 return (*(uint8_t *)(pi->pi_cfgdata + offset)); 297 } 298 299 static __inline uint16_t 300 pci_get_cfgdata16(struct pci_devinst *pi, int offset) 301 { 302 assert(offset <= (PCI_REGMAX - 1) && (offset & 1) == 0); 303 return (*(uint16_t *)(pi->pi_cfgdata + offset)); 304 } 305 306 static __inline uint32_t 307 pci_get_cfgdata32(struct pci_devinst *pi, int offset) 308 { 309 assert(offset <= (PCI_REGMAX - 3) && (offset & 3) == 0); 310 return (*(uint32_t *)(pi->pi_cfgdata + offset)); 311 } 312 313 #endif /* _PCI_EMUL_H_ */ 314