xref: /freebsd/usr.sbin/bhyve/pci_emul.h (revision e17f5b1d)
1 /*-
2  * SPDX-License-Identifier: BSD-2-Clause-FreeBSD
3  *
4  * Copyright (c) 2011 NetApp, Inc.
5  * All rights reserved.
6  *
7  * Redistribution and use in source and binary forms, with or without
8  * modification, are permitted provided that the following conditions
9  * are met:
10  * 1. Redistributions of source code must retain the above copyright
11  *    notice, this list of conditions and the following disclaimer.
12  * 2. Redistributions in binary form must reproduce the above copyright
13  *    notice, this list of conditions and the following disclaimer in the
14  *    documentation and/or other materials provided with the distribution.
15  *
16  * THIS SOFTWARE IS PROVIDED BY NETAPP, INC ``AS IS'' AND
17  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
18  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
19  * ARE DISCLAIMED.  IN NO EVENT SHALL NETAPP, INC OR CONTRIBUTORS BE LIABLE
20  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
21  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
22  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
23  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
24  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
25  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
26  * SUCH DAMAGE.
27  *
28  * $FreeBSD$
29  */
30 
31 #ifndef _PCI_EMUL_H_
32 #define _PCI_EMUL_H_
33 
34 #include <sys/types.h>
35 #include <sys/queue.h>
36 #include <sys/kernel.h>
37 #include <sys/_pthreadtypes.h>
38 
39 #include <dev/pci/pcireg.h>
40 
41 #include <assert.h>
42 
43 #define	PCI_BARMAX	PCIR_MAX_BAR_0	/* BAR registers in a Type 0 header */
44 
45 struct vmctx;
46 struct pci_devinst;
47 struct memory_region;
48 struct vm_snapshot_meta;
49 
50 struct pci_devemu {
51 	char      *pe_emu;		/* Name of device emulation */
52 
53 	/* instance creation */
54 	int       (*pe_init)(struct vmctx *, struct pci_devinst *,
55 			     char *opts);
56 
57 	/* ACPI DSDT enumeration */
58 	void	(*pe_write_dsdt)(struct pci_devinst *);
59 
60 	/* config space read/write callbacks */
61 	int	(*pe_cfgwrite)(struct vmctx *ctx, int vcpu,
62 			       struct pci_devinst *pi, int offset,
63 			       int bytes, uint32_t val);
64 	int	(*pe_cfgread)(struct vmctx *ctx, int vcpu,
65 			      struct pci_devinst *pi, int offset,
66 			      int bytes, uint32_t *retval);
67 
68 	/* BAR read/write callbacks */
69 	void      (*pe_barwrite)(struct vmctx *ctx, int vcpu,
70 				 struct pci_devinst *pi, int baridx,
71 				 uint64_t offset, int size, uint64_t value);
72 	uint64_t  (*pe_barread)(struct vmctx *ctx, int vcpu,
73 				struct pci_devinst *pi, int baridx,
74 				uint64_t offset, int size);
75 
76 	/* Save/restore device state */
77 	int	(*pe_snapshot)(struct vm_snapshot_meta *meta);
78 	int	(*pe_pause)(struct vmctx *ctx, struct pci_devinst *pi);
79 	int	(*pe_resume)(struct vmctx *ctx, struct pci_devinst *pi);
80 };
81 #define PCI_EMUL_SET(x)   DATA_SET(pci_devemu_set, x);
82 
83 enum pcibar_type {
84 	PCIBAR_NONE,
85 	PCIBAR_IO,
86 	PCIBAR_MEM32,
87 	PCIBAR_MEM64,
88 	PCIBAR_MEMHI64
89 };
90 
91 struct pcibar {
92 	enum pcibar_type	type;		/* io or memory */
93 	uint64_t		size;
94 	uint64_t		addr;
95 };
96 
97 #define PI_NAMESZ	40
98 
99 struct msix_table_entry {
100 	uint64_t	addr;
101 	uint32_t	msg_data;
102 	uint32_t	vector_control;
103 } __packed;
104 
105 /*
106  * In case the structure is modified to hold extra information, use a define
107  * for the size that should be emulated.
108  */
109 #define	MSIX_TABLE_ENTRY_SIZE	16
110 #define MAX_MSIX_TABLE_ENTRIES	2048
111 #define	PBA_SIZE(msgnum)	(roundup2((msgnum), 64) / 8)
112 
113 enum lintr_stat {
114 	IDLE,
115 	ASSERTED,
116 	PENDING
117 };
118 
119 struct pci_devinst {
120 	struct pci_devemu *pi_d;
121 	struct vmctx *pi_vmctx;
122 	uint8_t	  pi_bus, pi_slot, pi_func;
123 	char	  pi_name[PI_NAMESZ];
124 	int	  pi_bar_getsize;
125 	int	  pi_prevcap;
126 	int	  pi_capend;
127 
128 	struct {
129 		int8_t    	pin;
130 		enum lintr_stat	state;
131 		int		pirq_pin;
132 		int	  	ioapic_irq;
133 		pthread_mutex_t	lock;
134 	} pi_lintr;
135 
136 	struct {
137 		int		enabled;
138 		uint64_t	addr;
139 		uint64_t	msg_data;
140 		int		maxmsgnum;
141 	} pi_msi;
142 
143 	struct {
144 		int	enabled;
145 		int	table_bar;
146 		int	pba_bar;
147 		uint32_t table_offset;
148 		int	table_count;
149 		uint32_t pba_offset;
150 		int	pba_size;
151 		int	function_mask;
152 		struct msix_table_entry *table;	/* allocated at runtime */
153 		void	*pba_page;
154 		int	pba_page_offset;
155 	} pi_msix;
156 
157 	void      *pi_arg;		/* devemu-private data */
158 
159 	u_char	  pi_cfgdata[PCI_REGMAX + 1];
160 	struct pcibar pi_bar[PCI_BARMAX + 1];
161 };
162 
163 struct msicap {
164 	uint8_t		capid;
165 	uint8_t		nextptr;
166 	uint16_t	msgctrl;
167 	uint32_t	addrlo;
168 	uint32_t	addrhi;
169 	uint16_t	msgdata;
170 } __packed;
171 static_assert(sizeof(struct msicap) == 14, "compile-time assertion failed");
172 
173 struct msixcap {
174 	uint8_t		capid;
175 	uint8_t		nextptr;
176 	uint16_t	msgctrl;
177 	uint32_t	table_info;	/* bar index and offset within it */
178 	uint32_t	pba_info;	/* bar index and offset within it */
179 } __packed;
180 static_assert(sizeof(struct msixcap) == 12, "compile-time assertion failed");
181 
182 struct pciecap {
183 	uint8_t		capid;
184 	uint8_t		nextptr;
185 	uint16_t	pcie_capabilities;
186 
187 	uint32_t	dev_capabilities;	/* all devices */
188 	uint16_t	dev_control;
189 	uint16_t	dev_status;
190 
191 	uint32_t	link_capabilities;	/* devices with links */
192 	uint16_t	link_control;
193 	uint16_t	link_status;
194 
195 	uint32_t	slot_capabilities;	/* ports with slots */
196 	uint16_t	slot_control;
197 	uint16_t	slot_status;
198 
199 	uint16_t	root_control;		/* root ports */
200 	uint16_t	root_capabilities;
201 	uint32_t	root_status;
202 
203 	uint32_t	dev_capabilities2;	/* all devices */
204 	uint16_t	dev_control2;
205 	uint16_t	dev_status2;
206 
207 	uint32_t	link_capabilities2;	/* devices with links */
208 	uint16_t	link_control2;
209 	uint16_t	link_status2;
210 
211 	uint32_t	slot_capabilities2;	/* ports with slots */
212 	uint16_t	slot_control2;
213 	uint16_t	slot_status2;
214 } __packed;
215 static_assert(sizeof(struct pciecap) == 60, "compile-time assertion failed");
216 
217 typedef void (*pci_lintr_cb)(int b, int s, int pin, int pirq_pin,
218     int ioapic_irq, void *arg);
219 
220 int	init_pci(struct vmctx *ctx);
221 void	pci_callback(void);
222 int	pci_emul_alloc_bar(struct pci_devinst *pdi, int idx,
223 	    enum pcibar_type type, uint64_t size);
224 int	pci_emul_alloc_pbar(struct pci_devinst *pdi, int idx,
225 	    uint64_t hostbase, enum pcibar_type type, uint64_t size);
226 int	pci_emul_add_msicap(struct pci_devinst *pi, int msgnum);
227 int	pci_emul_add_pciecap(struct pci_devinst *pi, int pcie_device_type);
228 void	pci_emul_capwrite(struct pci_devinst *pi, int offset, int bytes,
229 	    uint32_t val, uint8_t capoff, int capid);
230 void	pci_emul_cmd_changed(struct pci_devinst *pi, uint16_t old);
231 void	pci_generate_msi(struct pci_devinst *pi, int msgnum);
232 void	pci_generate_msix(struct pci_devinst *pi, int msgnum);
233 void	pci_lintr_assert(struct pci_devinst *pi);
234 void	pci_lintr_deassert(struct pci_devinst *pi);
235 void	pci_lintr_request(struct pci_devinst *pi);
236 int	pci_msi_enabled(struct pci_devinst *pi);
237 int	pci_msix_enabled(struct pci_devinst *pi);
238 int	pci_msix_table_bar(struct pci_devinst *pi);
239 int	pci_msix_pba_bar(struct pci_devinst *pi);
240 int	pci_msi_maxmsgnum(struct pci_devinst *pi);
241 int	pci_parse_slot(char *opt);
242 void    pci_print_supported_devices();
243 void	pci_populate_msicap(struct msicap *cap, int msgs, int nextptr);
244 int	pci_emul_add_msixcap(struct pci_devinst *pi, int msgnum, int barnum);
245 int	pci_emul_msix_twrite(struct pci_devinst *pi, uint64_t offset, int size,
246 			     uint64_t value);
247 uint64_t pci_emul_msix_tread(struct pci_devinst *pi, uint64_t offset, int size);
248 int	pci_count_lintr(int bus);
249 void	pci_walk_lintr(int bus, pci_lintr_cb cb, void *arg);
250 void	pci_write_dsdt(void);
251 uint64_t pci_ecfg_base(void);
252 int	pci_bus_configured(int bus);
253 #ifdef BHYVE_SNAPSHOT
254 int	pci_snapshot(struct vm_snapshot_meta *meta);
255 int	pci_pause(struct vmctx *ctx, const char *dev_name);
256 int	pci_resume(struct vmctx *ctx, const char *dev_name);
257 #endif
258 
259 static __inline void
260 pci_set_cfgdata8(struct pci_devinst *pi, int offset, uint8_t val)
261 {
262 	assert(offset <= PCI_REGMAX);
263 	*(uint8_t *)(pi->pi_cfgdata + offset) = val;
264 }
265 
266 static __inline void
267 pci_set_cfgdata16(struct pci_devinst *pi, int offset, uint16_t val)
268 {
269 	assert(offset <= (PCI_REGMAX - 1) && (offset & 1) == 0);
270 	*(uint16_t *)(pi->pi_cfgdata + offset) = val;
271 }
272 
273 static __inline void
274 pci_set_cfgdata32(struct pci_devinst *pi, int offset, uint32_t val)
275 {
276 	assert(offset <= (PCI_REGMAX - 3) && (offset & 3) == 0);
277 	*(uint32_t *)(pi->pi_cfgdata + offset) = val;
278 }
279 
280 static __inline uint8_t
281 pci_get_cfgdata8(struct pci_devinst *pi, int offset)
282 {
283 	assert(offset <= PCI_REGMAX);
284 	return (*(uint8_t *)(pi->pi_cfgdata + offset));
285 }
286 
287 static __inline uint16_t
288 pci_get_cfgdata16(struct pci_devinst *pi, int offset)
289 {
290 	assert(offset <= (PCI_REGMAX - 1) && (offset & 1) == 0);
291 	return (*(uint16_t *)(pi->pi_cfgdata + offset));
292 }
293 
294 static __inline uint32_t
295 pci_get_cfgdata32(struct pci_devinst *pi, int offset)
296 {
297 	assert(offset <= (PCI_REGMAX - 3) && (offset & 3) == 0);
298 	return (*(uint32_t *)(pi->pi_cfgdata + offset));
299 }
300 
301 #endif /* _PCI_EMUL_H_ */
302