1 /*- 2 * SPDX-License-Identifier: BSD-3-Clause 3 * 4 * Copyright (c) 2007 Yahoo!, Inc. 5 * All rights reserved. 6 * Written by: John Baldwin <jhb@FreeBSD.org> 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 3. Neither the name of the author nor the names of any co-contributors 17 * may be used to endorse or promote products derived from this software 18 * without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 24 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 25 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 26 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 27 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 28 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 29 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 30 * SUCH DAMAGE. 31 */ 32 33 #ifndef lint 34 static const char rcsid[] = 35 "$FreeBSD$"; 36 #endif /* not lint */ 37 38 #include <sys/types.h> 39 40 #include <err.h> 41 #include <stdio.h> 42 #include <strings.h> 43 #include <sys/agpio.h> 44 #include <sys/pciio.h> 45 46 #include <dev/agp/agpreg.h> 47 #include <dev/pci/pcireg.h> 48 49 #include "pciconf.h" 50 51 static void list_ecaps(int fd, struct pci_conf *p); 52 53 static int cap_level; 54 55 static void 56 cap_power(int fd, struct pci_conf *p, uint8_t ptr) 57 { 58 uint16_t cap, status; 59 60 cap = read_config(fd, &p->pc_sel, ptr + PCIR_POWER_CAP, 2); 61 status = read_config(fd, &p->pc_sel, ptr + PCIR_POWER_STATUS, 2); 62 printf("powerspec %d supports D0%s%s D3 current D%d", 63 cap & PCIM_PCAP_SPEC, 64 cap & PCIM_PCAP_D1SUPP ? " D1" : "", 65 cap & PCIM_PCAP_D2SUPP ? " D2" : "", 66 status & PCIM_PSTAT_DMASK); 67 } 68 69 static void 70 cap_agp(int fd, struct pci_conf *p, uint8_t ptr) 71 { 72 uint32_t status, command; 73 74 status = read_config(fd, &p->pc_sel, ptr + AGP_STATUS, 4); 75 command = read_config(fd, &p->pc_sel, ptr + AGP_CAPID, 4); 76 printf("AGP "); 77 if (AGP_MODE_GET_MODE_3(status)) { 78 printf("v3 "); 79 if (AGP_MODE_GET_RATE(status) & AGP_MODE_V3_RATE_8x) 80 printf("8x "); 81 if (AGP_MODE_GET_RATE(status) & AGP_MODE_V3_RATE_4x) 82 printf("4x "); 83 } else { 84 if (AGP_MODE_GET_RATE(status) & AGP_MODE_V2_RATE_4x) 85 printf("4x "); 86 if (AGP_MODE_GET_RATE(status) & AGP_MODE_V2_RATE_2x) 87 printf("2x "); 88 if (AGP_MODE_GET_RATE(status) & AGP_MODE_V2_RATE_1x) 89 printf("1x "); 90 } 91 if (AGP_MODE_GET_SBA(status)) 92 printf("SBA "); 93 if (AGP_MODE_GET_AGP(command)) { 94 printf("enabled at "); 95 if (AGP_MODE_GET_MODE_3(command)) { 96 printf("v3 "); 97 switch (AGP_MODE_GET_RATE(command)) { 98 case AGP_MODE_V3_RATE_8x: 99 printf("8x "); 100 break; 101 case AGP_MODE_V3_RATE_4x: 102 printf("4x "); 103 break; 104 } 105 } else 106 switch (AGP_MODE_GET_RATE(command)) { 107 case AGP_MODE_V2_RATE_4x: 108 printf("4x "); 109 break; 110 case AGP_MODE_V2_RATE_2x: 111 printf("2x "); 112 break; 113 case AGP_MODE_V2_RATE_1x: 114 printf("1x "); 115 break; 116 } 117 if (AGP_MODE_GET_SBA(command)) 118 printf("SBA "); 119 } else 120 printf("disabled"); 121 } 122 123 static void 124 cap_vpd(int fd __unused, struct pci_conf *p __unused, uint8_t ptr __unused) 125 { 126 127 printf("VPD"); 128 } 129 130 static void 131 cap_msi(int fd, struct pci_conf *p, uint8_t ptr) 132 { 133 uint16_t ctrl; 134 int msgnum; 135 136 ctrl = read_config(fd, &p->pc_sel, ptr + PCIR_MSI_CTRL, 2); 137 msgnum = 1 << ((ctrl & PCIM_MSICTRL_MMC_MASK) >> 1); 138 printf("MSI supports %d message%s%s%s ", msgnum, 139 (msgnum == 1) ? "" : "s", 140 (ctrl & PCIM_MSICTRL_64BIT) ? ", 64 bit" : "", 141 (ctrl & PCIM_MSICTRL_VECTOR) ? ", vector masks" : ""); 142 if (ctrl & PCIM_MSICTRL_MSI_ENABLE) { 143 msgnum = 1 << ((ctrl & PCIM_MSICTRL_MME_MASK) >> 4); 144 printf("enabled with %d message%s", msgnum, 145 (msgnum == 1) ? "" : "s"); 146 } 147 } 148 149 static void 150 cap_pcix(int fd, struct pci_conf *p, uint8_t ptr) 151 { 152 uint32_t status; 153 int comma, max_splits, max_burst_read; 154 155 status = read_config(fd, &p->pc_sel, ptr + PCIXR_STATUS, 4); 156 printf("PCI-X "); 157 if (status & PCIXM_STATUS_64BIT) 158 printf("64-bit "); 159 if ((p->pc_hdr & PCIM_HDRTYPE) == 1) 160 printf("bridge "); 161 if ((p->pc_hdr & PCIM_HDRTYPE) != 1 || (status & (PCIXM_STATUS_133CAP | 162 PCIXM_STATUS_266CAP | PCIXM_STATUS_533CAP)) != 0) 163 printf("supports"); 164 comma = 0; 165 if (status & PCIXM_STATUS_133CAP) { 166 printf(" 133MHz"); 167 comma = 1; 168 } 169 if (status & PCIXM_STATUS_266CAP) { 170 printf("%s 266MHz", comma ? "," : ""); 171 comma = 1; 172 } 173 if (status & PCIXM_STATUS_533CAP) { 174 printf("%s 533MHz", comma ? "," : ""); 175 comma = 1; 176 } 177 if ((p->pc_hdr & PCIM_HDRTYPE) == 1) 178 return; 179 max_burst_read = 0; 180 switch (status & PCIXM_STATUS_MAX_READ) { 181 case PCIXM_STATUS_MAX_READ_512: 182 max_burst_read = 512; 183 break; 184 case PCIXM_STATUS_MAX_READ_1024: 185 max_burst_read = 1024; 186 break; 187 case PCIXM_STATUS_MAX_READ_2048: 188 max_burst_read = 2048; 189 break; 190 case PCIXM_STATUS_MAX_READ_4096: 191 max_burst_read = 4096; 192 break; 193 } 194 max_splits = 0; 195 switch (status & PCIXM_STATUS_MAX_SPLITS) { 196 case PCIXM_STATUS_MAX_SPLITS_1: 197 max_splits = 1; 198 break; 199 case PCIXM_STATUS_MAX_SPLITS_2: 200 max_splits = 2; 201 break; 202 case PCIXM_STATUS_MAX_SPLITS_3: 203 max_splits = 3; 204 break; 205 case PCIXM_STATUS_MAX_SPLITS_4: 206 max_splits = 4; 207 break; 208 case PCIXM_STATUS_MAX_SPLITS_8: 209 max_splits = 8; 210 break; 211 case PCIXM_STATUS_MAX_SPLITS_12: 212 max_splits = 12; 213 break; 214 case PCIXM_STATUS_MAX_SPLITS_16: 215 max_splits = 16; 216 break; 217 case PCIXM_STATUS_MAX_SPLITS_32: 218 max_splits = 32; 219 break; 220 } 221 printf("%s %d burst read, %d split transaction%s", comma ? "," : "", 222 max_burst_read, max_splits, max_splits == 1 ? "" : "s"); 223 } 224 225 static void 226 cap_ht(int fd, struct pci_conf *p, uint8_t ptr) 227 { 228 uint32_t reg; 229 uint16_t command; 230 231 command = read_config(fd, &p->pc_sel, ptr + PCIR_HT_COMMAND, 2); 232 printf("HT "); 233 if ((command & 0xe000) == PCIM_HTCAP_SLAVE) 234 printf("slave"); 235 else if ((command & 0xe000) == PCIM_HTCAP_HOST) 236 printf("host"); 237 else 238 switch (command & PCIM_HTCMD_CAP_MASK) { 239 case PCIM_HTCAP_SWITCH: 240 printf("switch"); 241 break; 242 case PCIM_HTCAP_INTERRUPT: 243 printf("interrupt"); 244 break; 245 case PCIM_HTCAP_REVISION_ID: 246 printf("revision ID"); 247 break; 248 case PCIM_HTCAP_UNITID_CLUMPING: 249 printf("unit ID clumping"); 250 break; 251 case PCIM_HTCAP_EXT_CONFIG_SPACE: 252 printf("extended config space"); 253 break; 254 case PCIM_HTCAP_ADDRESS_MAPPING: 255 printf("address mapping"); 256 break; 257 case PCIM_HTCAP_MSI_MAPPING: 258 printf("MSI %saddress window %s at 0x", 259 command & PCIM_HTCMD_MSI_FIXED ? "fixed " : "", 260 command & PCIM_HTCMD_MSI_ENABLE ? "enabled" : 261 "disabled"); 262 if (command & PCIM_HTCMD_MSI_FIXED) 263 printf("fee00000"); 264 else { 265 reg = read_config(fd, &p->pc_sel, 266 ptr + PCIR_HTMSI_ADDRESS_HI, 4); 267 if (reg != 0) 268 printf("%08x", reg); 269 reg = read_config(fd, &p->pc_sel, 270 ptr + PCIR_HTMSI_ADDRESS_LO, 4); 271 printf("%08x", reg); 272 } 273 break; 274 case PCIM_HTCAP_DIRECT_ROUTE: 275 printf("direct route"); 276 break; 277 case PCIM_HTCAP_VCSET: 278 printf("VC set"); 279 break; 280 case PCIM_HTCAP_RETRY_MODE: 281 printf("retry mode"); 282 break; 283 case PCIM_HTCAP_X86_ENCODING: 284 printf("X86 encoding"); 285 break; 286 case PCIM_HTCAP_GEN3: 287 printf("Gen3"); 288 break; 289 case PCIM_HTCAP_FLE: 290 printf("function-level extension"); 291 break; 292 case PCIM_HTCAP_PM: 293 printf("power management"); 294 break; 295 case PCIM_HTCAP_HIGH_NODE_COUNT: 296 printf("high node count"); 297 break; 298 default: 299 printf("unknown %02x", command); 300 break; 301 } 302 } 303 304 static void 305 cap_vendor(int fd, struct pci_conf *p, uint8_t ptr) 306 { 307 uint8_t length; 308 309 length = read_config(fd, &p->pc_sel, ptr + PCIR_VENDOR_LENGTH, 1); 310 printf("vendor (length %d)", length); 311 if (p->pc_vendor == 0x8086) { 312 /* Intel */ 313 uint8_t version; 314 315 version = read_config(fd, &p->pc_sel, ptr + PCIR_VENDOR_DATA, 316 1); 317 printf(" Intel cap %d version %d", version >> 4, version & 0xf); 318 if (version >> 4 == 1 && length == 12) { 319 /* Feature Detection */ 320 uint32_t fvec; 321 int comma; 322 323 comma = 0; 324 fvec = read_config(fd, &p->pc_sel, ptr + 325 PCIR_VENDOR_DATA + 5, 4); 326 printf("\n\t\t features:"); 327 if (fvec & (1 << 0)) { 328 printf(" AMT"); 329 comma = 1; 330 } 331 fvec = read_config(fd, &p->pc_sel, ptr + 332 PCIR_VENDOR_DATA + 1, 4); 333 if (fvec & (1 << 21)) { 334 printf("%s Quick Resume", comma ? "," : ""); 335 comma = 1; 336 } 337 if (fvec & (1 << 18)) { 338 printf("%s SATA RAID-5", comma ? "," : ""); 339 comma = 1; 340 } 341 if (fvec & (1 << 9)) { 342 printf("%s Mobile", comma ? "," : ""); 343 comma = 1; 344 } 345 if (fvec & (1 << 7)) { 346 printf("%s 6 PCI-e x1 slots", comma ? "," : ""); 347 comma = 1; 348 } else { 349 printf("%s 4 PCI-e x1 slots", comma ? "," : ""); 350 comma = 1; 351 } 352 if (fvec & (1 << 5)) { 353 printf("%s SATA RAID-0/1/10", comma ? "," : ""); 354 comma = 1; 355 } 356 if (fvec & (1 << 3)) 357 printf(", SATA AHCI"); 358 } 359 } 360 } 361 362 static void 363 cap_debug(int fd, struct pci_conf *p, uint8_t ptr) 364 { 365 uint16_t debug_port; 366 367 debug_port = read_config(fd, &p->pc_sel, ptr + PCIR_DEBUG_PORT, 2); 368 printf("EHCI Debug Port at offset 0x%x in map 0x%x", debug_port & 369 PCIM_DEBUG_PORT_OFFSET, PCIR_BAR(debug_port >> 13)); 370 } 371 372 static void 373 cap_subvendor(int fd, struct pci_conf *p, uint8_t ptr) 374 { 375 uint32_t id; 376 uint16_t ssid, ssvid; 377 378 id = read_config(fd, &p->pc_sel, ptr + PCIR_SUBVENDCAP_ID, 4); 379 ssid = id >> 16; 380 ssvid = id & 0xffff; 381 printf("PCI Bridge subvendor=0x%04x subdevice=0x%04x", ssvid, ssid); 382 } 383 384 #define MAX_PAYLOAD(field) (128 << (field)) 385 386 static const char * 387 link_speed_string(uint8_t speed) 388 { 389 390 switch (speed) { 391 case 1: 392 return ("2.5"); 393 case 2: 394 return ("5.0"); 395 case 3: 396 return ("8.0"); 397 case 4: 398 return ("16.0"); 399 default: 400 return ("undef"); 401 } 402 } 403 404 static const char * 405 max_read_string(u_int max_read) 406 { 407 408 switch (max_read) { 409 case 0x0: 410 return ("128"); 411 case 0x1: 412 return ("256"); 413 case 0x2: 414 return ("512"); 415 case 0x3: 416 return ("1024"); 417 case 0x4: 418 return ("2048"); 419 case 0x5: 420 return ("4096"); 421 default: 422 return ("undef"); 423 } 424 } 425 426 static const char * 427 aspm_string(uint8_t aspm) 428 { 429 430 switch (aspm) { 431 case 1: 432 return ("L0s"); 433 case 2: 434 return ("L1"); 435 case 3: 436 return ("L0s/L1"); 437 default: 438 return ("disabled"); 439 } 440 } 441 442 static int 443 slot_power(uint32_t cap) 444 { 445 int mwatts; 446 447 mwatts = (cap & PCIEM_SLOT_CAP_SPLV) >> 7; 448 switch (cap & PCIEM_SLOT_CAP_SPLS) { 449 case 0x0: 450 mwatts *= 1000; 451 break; 452 case 0x1: 453 mwatts *= 100; 454 break; 455 case 0x2: 456 mwatts *= 10; 457 break; 458 default: 459 break; 460 } 461 return (mwatts); 462 } 463 464 static void 465 cap_express(int fd, struct pci_conf *p, uint8_t ptr) 466 { 467 uint32_t cap; 468 uint16_t ctl, flags, sta; 469 unsigned int version; 470 471 flags = read_config(fd, &p->pc_sel, ptr + PCIER_FLAGS, 2); 472 version = flags & PCIEM_FLAGS_VERSION; 473 printf("PCI-Express %u ", version); 474 switch (flags & PCIEM_FLAGS_TYPE) { 475 case PCIEM_TYPE_ENDPOINT: 476 printf("endpoint"); 477 break; 478 case PCIEM_TYPE_LEGACY_ENDPOINT: 479 printf("legacy endpoint"); 480 break; 481 case PCIEM_TYPE_ROOT_PORT: 482 printf("root port"); 483 break; 484 case PCIEM_TYPE_UPSTREAM_PORT: 485 printf("upstream port"); 486 break; 487 case PCIEM_TYPE_DOWNSTREAM_PORT: 488 printf("downstream port"); 489 break; 490 case PCIEM_TYPE_PCI_BRIDGE: 491 printf("PCI bridge"); 492 break; 493 case PCIEM_TYPE_PCIE_BRIDGE: 494 printf("PCI to PCIe bridge"); 495 break; 496 case PCIEM_TYPE_ROOT_INT_EP: 497 printf("root endpoint"); 498 break; 499 case PCIEM_TYPE_ROOT_EC: 500 printf("event collector"); 501 break; 502 default: 503 printf("type %d", (flags & PCIEM_FLAGS_TYPE) >> 4); 504 break; 505 } 506 if (flags & PCIEM_FLAGS_IRQ) 507 printf(" MSI %d", (flags & PCIEM_FLAGS_IRQ) >> 9); 508 cap = read_config(fd, &p->pc_sel, ptr + PCIER_DEVICE_CAP, 4); 509 ctl = read_config(fd, &p->pc_sel, ptr + PCIER_DEVICE_CTL, 2); 510 printf(" max data %d(%d)", 511 MAX_PAYLOAD((ctl & PCIEM_CTL_MAX_PAYLOAD) >> 5), 512 MAX_PAYLOAD(cap & PCIEM_CAP_MAX_PAYLOAD)); 513 if ((cap & PCIEM_CAP_FLR) != 0) 514 printf(" FLR"); 515 if (ctl & PCIEM_CTL_RELAXED_ORD_ENABLE) 516 printf(" RO"); 517 if (ctl & PCIEM_CTL_NOSNOOP_ENABLE) 518 printf(" NS"); 519 if (version >= 2) { 520 cap = read_config(fd, &p->pc_sel, ptr + PCIER_DEVICE_CAP2, 4); 521 if ((cap & PCIEM_CAP2_ARI) != 0) { 522 ctl = read_config(fd, &p->pc_sel, 523 ptr + PCIER_DEVICE_CTL2, 4); 524 printf(" ARI %s", 525 (ctl & PCIEM_CTL2_ARI) ? "enabled" : "disabled"); 526 } 527 } 528 printf("\n max read %s", max_read_string((ctl & 529 PCIEM_CTL_MAX_READ_REQUEST) >> 12)); 530 cap = read_config(fd, &p->pc_sel, ptr + PCIER_LINK_CAP, 4); 531 sta = read_config(fd, &p->pc_sel, ptr + PCIER_LINK_STA, 2); 532 if (cap == 0 && sta == 0) 533 return; 534 printf("\n "); 535 printf(" link x%d(x%d)", (sta & PCIEM_LINK_STA_WIDTH) >> 4, 536 (cap & PCIEM_LINK_CAP_MAX_WIDTH) >> 4); 537 if ((cap & PCIEM_LINK_CAP_MAX_WIDTH) != 0) { 538 printf(" speed %s(%s)", (sta & PCIEM_LINK_STA_WIDTH) == 0 ? 539 "0.0" : link_speed_string(sta & PCIEM_LINK_STA_SPEED), 540 link_speed_string(cap & PCIEM_LINK_CAP_MAX_SPEED)); 541 } 542 if ((cap & PCIEM_LINK_CAP_ASPM) != 0) { 543 ctl = read_config(fd, &p->pc_sel, ptr + PCIER_LINK_CTL, 2); 544 printf(" ASPM %s(%s)", aspm_string(ctl & PCIEM_LINK_CTL_ASPMC), 545 aspm_string((cap & PCIEM_LINK_CAP_ASPM) >> 10)); 546 } 547 if ((cap & PCIEM_LINK_CAP_CLOCK_PM) != 0) { 548 ctl = read_config(fd, &p->pc_sel, ptr + PCIER_LINK_CTL, 2); 549 printf(" ClockPM %s", (ctl & PCIEM_LINK_CTL_ECPM) ? 550 "enabled" : "disabled"); 551 } 552 if (!(flags & PCIEM_FLAGS_SLOT)) 553 return; 554 cap = read_config(fd, &p->pc_sel, ptr + PCIER_SLOT_CAP, 4); 555 sta = read_config(fd, &p->pc_sel, ptr + PCIER_SLOT_STA, 2); 556 ctl = read_config(fd, &p->pc_sel, ptr + PCIER_SLOT_CTL, 2); 557 printf("\n "); 558 printf(" slot %d", (cap & PCIEM_SLOT_CAP_PSN) >> 19); 559 printf(" power limit %d mW", slot_power(cap)); 560 if (cap & PCIEM_SLOT_CAP_HPC) 561 printf(" HotPlug(%s)", sta & PCIEM_SLOT_STA_PDS ? "present" : 562 "empty"); 563 if (cap & PCIEM_SLOT_CAP_HPS) 564 printf(" surprise"); 565 if (cap & PCIEM_SLOT_CAP_APB) 566 printf(" Attn Button"); 567 if (cap & PCIEM_SLOT_CAP_PCP) 568 printf(" PC(%s)", ctl & PCIEM_SLOT_CTL_PCC ? "off" : "on"); 569 if (cap & PCIEM_SLOT_CAP_MRLSP) 570 printf(" MRL(%s)", sta & PCIEM_SLOT_STA_MRLSS ? "open" : 571 "closed"); 572 if (cap & PCIEM_SLOT_CAP_EIP) 573 printf(" EI(%s)", sta & PCIEM_SLOT_STA_EIS ? "engaged" : 574 "disengaged"); 575 } 576 577 static void 578 cap_msix(int fd, struct pci_conf *p, uint8_t ptr) 579 { 580 uint32_t pba_offset, table_offset, val; 581 int msgnum, pba_bar, table_bar; 582 uint16_t ctrl; 583 584 ctrl = read_config(fd, &p->pc_sel, ptr + PCIR_MSIX_CTRL, 2); 585 msgnum = (ctrl & PCIM_MSIXCTRL_TABLE_SIZE) + 1; 586 587 val = read_config(fd, &p->pc_sel, ptr + PCIR_MSIX_TABLE, 4); 588 table_bar = PCIR_BAR(val & PCIM_MSIX_BIR_MASK); 589 table_offset = val & ~PCIM_MSIX_BIR_MASK; 590 591 val = read_config(fd, &p->pc_sel, ptr + PCIR_MSIX_PBA, 4); 592 pba_bar = PCIR_BAR(val & PCIM_MSIX_BIR_MASK); 593 pba_offset = val & ~PCIM_MSIX_BIR_MASK; 594 595 printf("MSI-X supports %d message%s%s\n", msgnum, 596 (msgnum == 1) ? "" : "s", 597 (ctrl & PCIM_MSIXCTRL_MSIX_ENABLE) ? ", enabled" : ""); 598 599 printf(" "); 600 printf("Table in map 0x%x[0x%x], PBA in map 0x%x[0x%x]", 601 table_bar, table_offset, pba_bar, pba_offset); 602 } 603 604 static void 605 cap_sata(int fd __unused, struct pci_conf *p __unused, uint8_t ptr __unused) 606 { 607 608 printf("SATA Index-Data Pair"); 609 } 610 611 static void 612 cap_pciaf(int fd, struct pci_conf *p, uint8_t ptr) 613 { 614 uint8_t cap; 615 616 cap = read_config(fd, &p->pc_sel, ptr + PCIR_PCIAF_CAP, 1); 617 printf("PCI Advanced Features:%s%s", 618 cap & PCIM_PCIAFCAP_FLR ? " FLR" : "", 619 cap & PCIM_PCIAFCAP_TP ? " TP" : ""); 620 } 621 622 static const char * 623 ea_bei_to_name(int bei) 624 { 625 static const char *barstr[] = { 626 "BAR0", "BAR1", "BAR2", "BAR3", "BAR4", "BAR5" 627 }; 628 static const char *vfbarstr[] = { 629 "VFBAR0", "VFBAR1", "VFBAR2", "VFBAR3", "VFBAR4", "VFBAR5" 630 }; 631 632 if ((bei >= PCIM_EA_BEI_BAR_0) && (bei <= PCIM_EA_BEI_BAR_5)) 633 return (barstr[bei - PCIM_EA_BEI_BAR_0]); 634 if ((bei >= PCIM_EA_BEI_VF_BAR_0) && (bei <= PCIM_EA_BEI_VF_BAR_5)) 635 return (vfbarstr[bei - PCIM_EA_BEI_VF_BAR_0]); 636 637 switch (bei) { 638 case PCIM_EA_BEI_BRIDGE: 639 return "BRIDGE"; 640 case PCIM_EA_BEI_ENI: 641 return "ENI"; 642 case PCIM_EA_BEI_ROM: 643 return "ROM"; 644 case PCIM_EA_BEI_RESERVED: 645 default: 646 return "RSVD"; 647 } 648 } 649 650 static const char * 651 ea_prop_to_name(uint8_t prop) 652 { 653 654 switch (prop) { 655 case PCIM_EA_P_MEM: 656 return "Non-Prefetchable Memory"; 657 case PCIM_EA_P_MEM_PREFETCH: 658 return "Prefetchable Memory"; 659 case PCIM_EA_P_IO: 660 return "I/O Space"; 661 case PCIM_EA_P_VF_MEM_PREFETCH: 662 return "VF Prefetchable Memory"; 663 case PCIM_EA_P_VF_MEM: 664 return "VF Non-Prefetchable Memory"; 665 case PCIM_EA_P_BRIDGE_MEM: 666 return "Bridge Non-Prefetchable Memory"; 667 case PCIM_EA_P_BRIDGE_MEM_PREFETCH: 668 return "Bridge Prefetchable Memory"; 669 case PCIM_EA_P_BRIDGE_IO: 670 return "Bridge I/O Space"; 671 case PCIM_EA_P_MEM_RESERVED: 672 return "Reserved Memory"; 673 case PCIM_EA_P_IO_RESERVED: 674 return "Reserved I/O Space"; 675 case PCIM_EA_P_UNAVAILABLE: 676 return "Unavailable"; 677 default: 678 return "Reserved"; 679 } 680 } 681 682 static void 683 cap_ea(int fd, struct pci_conf *p, uint8_t ptr) 684 { 685 int num_ent; 686 int a, b; 687 uint32_t bei; 688 uint32_t val; 689 int ent_size; 690 uint32_t dw[4]; 691 uint32_t flags, flags_pp, flags_sp; 692 uint64_t base, max_offset; 693 uint8_t fixed_sub_bus_nr, fixed_sec_bus_nr; 694 695 /* Determine the number of entries */ 696 num_ent = read_config(fd, &p->pc_sel, ptr + PCIR_EA_NUM_ENT, 2); 697 num_ent &= PCIM_EA_NUM_ENT_MASK; 698 699 printf("PCI Enhanced Allocation (%d entries)", num_ent); 700 701 /* Find the first entry to care of */ 702 ptr += PCIR_EA_FIRST_ENT; 703 704 /* Print BUS numbers for bridges */ 705 if ((p->pc_hdr & PCIM_HDRTYPE) == PCIM_HDRTYPE_BRIDGE) { 706 val = read_config(fd, &p->pc_sel, ptr, 4); 707 708 fixed_sec_bus_nr = PCIM_EA_SEC_NR(val); 709 fixed_sub_bus_nr = PCIM_EA_SUB_NR(val); 710 711 printf("\n\t\t BRIDGE, sec bus [%d], sub bus [%d]", 712 fixed_sec_bus_nr, fixed_sub_bus_nr); 713 ptr += 4; 714 } 715 716 for (a = 0; a < num_ent; a++) { 717 /* Read a number of dwords in the entry */ 718 val = read_config(fd, &p->pc_sel, ptr, 4); 719 ptr += 4; 720 ent_size = (val & PCIM_EA_ES); 721 722 for (b = 0; b < ent_size; b++) { 723 dw[b] = read_config(fd, &p->pc_sel, ptr, 4); 724 ptr += 4; 725 } 726 727 flags = val; 728 flags_pp = (flags & PCIM_EA_PP) >> PCIM_EA_PP_OFFSET; 729 flags_sp = (flags & PCIM_EA_SP) >> PCIM_EA_SP_OFFSET; 730 bei = (PCIM_EA_BEI & val) >> PCIM_EA_BEI_OFFSET; 731 732 base = dw[0] & PCIM_EA_FIELD_MASK; 733 max_offset = dw[1] | ~PCIM_EA_FIELD_MASK; 734 b = 2; 735 if (((dw[0] & PCIM_EA_IS_64) != 0) && (b < ent_size)) { 736 base |= (uint64_t)dw[b] << 32UL; 737 b++; 738 } 739 if (((dw[1] & PCIM_EA_IS_64) != 0) 740 && (b < ent_size)) { 741 max_offset |= (uint64_t)dw[b] << 32UL; 742 b++; 743 } 744 745 printf("\n\t\t [%d] %s, %s, %s, base [0x%jx], size [0x%jx]" 746 "\n\t\t\tPrimary properties [0x%x] (%s)" 747 "\n\t\t\tSecondary properties [0x%x] (%s)", 748 bei, ea_bei_to_name(bei), 749 (flags & PCIM_EA_ENABLE ? "Enabled" : "Disabled"), 750 (flags & PCIM_EA_WRITABLE ? "Writable" : "Read-only"), 751 (uintmax_t)base, (uintmax_t)(max_offset + 1), 752 flags_pp, ea_prop_to_name(flags_pp), 753 flags_sp, ea_prop_to_name(flags_sp)); 754 } 755 } 756 757 void 758 list_caps(int fd, struct pci_conf *p, int level) 759 { 760 int express; 761 uint16_t sta; 762 uint8_t ptr, cap; 763 764 /* Are capabilities present for this device? */ 765 sta = read_config(fd, &p->pc_sel, PCIR_STATUS, 2); 766 if (!(sta & PCIM_STATUS_CAPPRESENT)) 767 return; 768 769 cap_level = level; 770 771 switch (p->pc_hdr & PCIM_HDRTYPE) { 772 case PCIM_HDRTYPE_NORMAL: 773 case PCIM_HDRTYPE_BRIDGE: 774 ptr = PCIR_CAP_PTR; 775 break; 776 case PCIM_HDRTYPE_CARDBUS: 777 ptr = PCIR_CAP_PTR_2; 778 break; 779 default: 780 errx(1, "list_caps: bad header type"); 781 } 782 783 /* Walk the capability list. */ 784 express = 0; 785 ptr = read_config(fd, &p->pc_sel, ptr, 1); 786 while (ptr != 0 && ptr != 0xff) { 787 cap = read_config(fd, &p->pc_sel, ptr + PCICAP_ID, 1); 788 printf(" cap %02x[%02x] = ", cap, ptr); 789 switch (cap) { 790 case PCIY_PMG: 791 cap_power(fd, p, ptr); 792 break; 793 case PCIY_AGP: 794 cap_agp(fd, p, ptr); 795 break; 796 case PCIY_VPD: 797 cap_vpd(fd, p, ptr); 798 break; 799 case PCIY_MSI: 800 cap_msi(fd, p, ptr); 801 break; 802 case PCIY_PCIX: 803 cap_pcix(fd, p, ptr); 804 break; 805 case PCIY_HT: 806 cap_ht(fd, p, ptr); 807 break; 808 case PCIY_VENDOR: 809 cap_vendor(fd, p, ptr); 810 break; 811 case PCIY_DEBUG: 812 cap_debug(fd, p, ptr); 813 break; 814 case PCIY_SUBVENDOR: 815 cap_subvendor(fd, p, ptr); 816 break; 817 case PCIY_EXPRESS: 818 express = 1; 819 cap_express(fd, p, ptr); 820 break; 821 case PCIY_MSIX: 822 cap_msix(fd, p, ptr); 823 break; 824 case PCIY_SATA: 825 cap_sata(fd, p, ptr); 826 break; 827 case PCIY_PCIAF: 828 cap_pciaf(fd, p, ptr); 829 break; 830 case PCIY_EA: 831 cap_ea(fd, p, ptr); 832 break; 833 default: 834 printf("unknown"); 835 break; 836 } 837 printf("\n"); 838 ptr = read_config(fd, &p->pc_sel, ptr + PCICAP_NEXTPTR, 1); 839 } 840 841 if (express) 842 list_ecaps(fd, p); 843 } 844 845 /* From <sys/systm.h>. */ 846 static __inline uint32_t 847 bitcount32(uint32_t x) 848 { 849 850 x = (x & 0x55555555) + ((x & 0xaaaaaaaa) >> 1); 851 x = (x & 0x33333333) + ((x & 0xcccccccc) >> 2); 852 x = (x + (x >> 4)) & 0x0f0f0f0f; 853 x = (x + (x >> 8)); 854 x = (x + (x >> 16)) & 0x000000ff; 855 return (x); 856 } 857 858 static void 859 ecap_aer(int fd, struct pci_conf *p, uint16_t ptr, uint8_t ver) 860 { 861 uint32_t sta, mask; 862 863 printf("AER %d", ver); 864 if (ver < 1) { 865 printf("\n"); 866 return; 867 } 868 sta = read_config(fd, &p->pc_sel, ptr + PCIR_AER_UC_STATUS, 4); 869 mask = read_config(fd, &p->pc_sel, ptr + PCIR_AER_UC_SEVERITY, 4); 870 printf(" %d fatal", bitcount32(sta & mask)); 871 printf(" %d non-fatal", bitcount32(sta & ~mask)); 872 sta = read_config(fd, &p->pc_sel, ptr + PCIR_AER_COR_STATUS, 4); 873 printf(" %d corrected\n", bitcount32(sta)); 874 } 875 876 static void 877 ecap_vc(int fd, struct pci_conf *p, uint16_t ptr, uint8_t ver) 878 { 879 uint32_t cap1; 880 881 printf("VC %d", ver); 882 if (ver < 1) { 883 printf("\n"); 884 return; 885 } 886 cap1 = read_config(fd, &p->pc_sel, ptr + PCIR_VC_CAP1, 4); 887 printf(" max VC%d", cap1 & PCIM_VC_CAP1_EXT_COUNT); 888 if ((cap1 & PCIM_VC_CAP1_LOWPRI_EXT_COUNT) != 0) 889 printf(" lowpri VC0-VC%d", 890 (cap1 & PCIM_VC_CAP1_LOWPRI_EXT_COUNT) >> 4); 891 printf("\n"); 892 } 893 894 static void 895 ecap_sernum(int fd, struct pci_conf *p, uint16_t ptr, uint8_t ver) 896 { 897 uint32_t high, low; 898 899 printf("Serial %d", ver); 900 if (ver < 1) { 901 printf("\n"); 902 return; 903 } 904 low = read_config(fd, &p->pc_sel, ptr + PCIR_SERIAL_LOW, 4); 905 high = read_config(fd, &p->pc_sel, ptr + PCIR_SERIAL_HIGH, 4); 906 printf(" %08x%08x\n", high, low); 907 } 908 909 static void 910 ecap_vendor(int fd, struct pci_conf *p, uint16_t ptr, uint8_t ver) 911 { 912 uint32_t val, hdr; 913 uint16_t nextptr, len; 914 int i; 915 916 val = read_config(fd, &p->pc_sel, ptr, 4); 917 nextptr = PCI_EXTCAP_NEXTPTR(val); 918 hdr = read_config(fd, &p->pc_sel, ptr + PCIR_VSEC_HEADER, 4); 919 len = PCIR_VSEC_LENGTH(hdr); 920 if (len == 0) { 921 if (nextptr == 0) 922 nextptr = 0x1000; 923 len = nextptr - ptr; 924 } 925 926 printf("Vendor [%d] ID %04x Rev %d Length %d\n", ver, 927 PCIR_VSEC_ID(hdr), PCIR_VSEC_REV(hdr), len); 928 if ((ver < 1) || (cap_level <= 1)) 929 return; 930 for (i = 0; i < len; i += 4) { 931 val = read_config(fd, &p->pc_sel, ptr + i, 4); 932 if ((i % 16) == 0) 933 printf(" "); 934 printf("%02x %02x %02x %02x", val & 0xff, (val >> 8) & 0xff, 935 (val >> 16) & 0xff, (val >> 24) & 0xff); 936 if ((((i + 4) % 16) == 0 ) || ((i + 4) >= len)) 937 printf("\n"); 938 else 939 printf(" "); 940 } 941 } 942 943 static void 944 ecap_sec_pcie(int fd, struct pci_conf *p, uint16_t ptr, uint8_t ver) 945 { 946 uint32_t val; 947 948 printf("PCIe Sec %d", ver); 949 if (ver < 1) { 950 printf("\n"); 951 return; 952 } 953 val = read_config(fd, &p->pc_sel, ptr + 8, 4); 954 printf(" lane errors %#x\n", val); 955 } 956 957 static const char * 958 check_enabled(int value) 959 { 960 961 return (value ? "enabled" : "disabled"); 962 } 963 964 static void 965 ecap_sriov(int fd, struct pci_conf *p, uint16_t ptr, uint8_t ver) 966 { 967 const char *comma, *enabled; 968 uint16_t iov_ctl, total_vfs, num_vfs, vf_offset, vf_stride, vf_did; 969 uint32_t page_caps, page_size, page_shift, size; 970 int i; 971 972 printf("SR-IOV %d ", ver); 973 974 iov_ctl = read_config(fd, &p->pc_sel, ptr + PCIR_SRIOV_CTL, 2); 975 printf("IOV %s, Memory Space %s, ARI %s\n", 976 check_enabled(iov_ctl & PCIM_SRIOV_VF_EN), 977 check_enabled(iov_ctl & PCIM_SRIOV_VF_MSE), 978 check_enabled(iov_ctl & PCIM_SRIOV_ARI_EN)); 979 980 total_vfs = read_config(fd, &p->pc_sel, ptr + PCIR_SRIOV_TOTAL_VFS, 2); 981 num_vfs = read_config(fd, &p->pc_sel, ptr + PCIR_SRIOV_NUM_VFS, 2); 982 printf(" "); 983 printf("%d VFs configured out of %d supported\n", num_vfs, total_vfs); 984 985 vf_offset = read_config(fd, &p->pc_sel, ptr + PCIR_SRIOV_VF_OFF, 2); 986 vf_stride = read_config(fd, &p->pc_sel, ptr + PCIR_SRIOV_VF_STRIDE, 2); 987 printf(" "); 988 printf("First VF RID Offset 0x%04x, VF RID Stride 0x%04x\n", vf_offset, 989 vf_stride); 990 991 vf_did = read_config(fd, &p->pc_sel, ptr + PCIR_SRIOV_VF_DID, 2); 992 printf(" VF Device ID 0x%04x\n", vf_did); 993 994 page_caps = read_config(fd, &p->pc_sel, ptr + PCIR_SRIOV_PAGE_CAP, 4); 995 page_size = read_config(fd, &p->pc_sel, ptr + PCIR_SRIOV_PAGE_SIZE, 4); 996 printf(" "); 997 printf("Page Sizes: "); 998 comma = ""; 999 while (page_caps != 0) { 1000 page_shift = ffs(page_caps) - 1; 1001 1002 if (page_caps & page_size) 1003 enabled = " (enabled)"; 1004 else 1005 enabled = ""; 1006 1007 size = (1 << (page_shift + PCI_SRIOV_BASE_PAGE_SHIFT)); 1008 printf("%s%d%s", comma, size, enabled); 1009 comma = ", "; 1010 1011 page_caps &= ~(1 << page_shift); 1012 } 1013 printf("\n"); 1014 1015 for (i = 0; i <= PCIR_MAX_BAR_0; i++) 1016 print_bar(fd, p, "iov bar ", ptr + PCIR_SRIOV_BAR(i)); 1017 } 1018 1019 static const char * 1020 check_avail_and_state(u_int cap, u_int capbit, u_int ctl, u_int ctlbit) 1021 { 1022 1023 if (cap & capbit) 1024 return (ctl & ctlbit ? "enabled" : "disabled"); 1025 else 1026 return "unavailable"; 1027 } 1028 1029 static void 1030 ecap_acs(int fd, struct pci_conf *p, uint16_t ptr, uint8_t ver) 1031 { 1032 uint16_t acs_cap, acs_ctl; 1033 static const char *const acc[] = { "access enabled", "blocking enabled", 1034 "redirect enabled", "reserved" }; 1035 1036 printf("ACS %d ", ver); 1037 if (ver != 1) { 1038 printf("\n"); 1039 return; 1040 } 1041 1042 #define CHECK_AVAIL_STATE(bit) \ 1043 check_avail_and_state(acs_cap, bit, acs_ctl, bit##_ENABLE) 1044 1045 acs_cap = read_config(fd, &p->pc_sel, ptr + PCIR_ACS_CAP, 2); 1046 acs_ctl = read_config(fd, &p->pc_sel, ptr + PCIR_ACS_CTL, 2); 1047 printf("Source Validation %s, Translation Blocking %s\n", 1048 CHECK_AVAIL_STATE(PCIM_ACS_SOURCE_VALIDATION), 1049 CHECK_AVAIL_STATE(PCIM_ACS_TRANSLATION_BLOCKING)); 1050 1051 printf(" "); 1052 printf("P2P Req Redirect %s, P2P Cmpl Redirect %s\n", 1053 CHECK_AVAIL_STATE(PCIM_ACS_P2P_REQ_REDIRECT), 1054 CHECK_AVAIL_STATE(PCIM_ACS_P2P_CMP_REDIRECT)); 1055 printf(" "); 1056 printf("P2P Upstream Forwarding %s, P2P Egress Control %s\n", 1057 CHECK_AVAIL_STATE(PCIM_ACS_P2P_UPSTREAM_FORWARDING), 1058 CHECK_AVAIL_STATE(PCIM_ACS_P2P_EGRESS_CTL)); 1059 printf(" "); 1060 printf("P2P Direct Translated %s, Enhanced Capability %s\n", 1061 CHECK_AVAIL_STATE(PCIM_ACS_P2P_DIRECT_TRANSLATED), 1062 acs_ctl & PCIM_ACS_ENHANCED_CAP ? "available" : "unavailable"); 1063 #undef CHECK_AVAIL_STATE 1064 1065 if (acs_cap & PCIM_ACS_ENHANCED_CAP) { 1066 printf(" "); 1067 printf("I/O Req Blocking %s, Unclaimed Req Redirect Control %s\n", 1068 check_enabled(acs_ctl & PCIM_ACS_IO_REQ_BLOCKING_ENABLE), 1069 check_enabled(acs_ctl & PCIM_ACS_UNCLAIMED_REQ_REDIRECT_CTL)); 1070 printf(" "); 1071 printf("DSP BAR %s, USP BAR %s\n", 1072 acc[(acs_cap & PCIM_ACS_DSP_MEM_TGT_ACC_CTL) >> 8], 1073 acc[(acs_cap & PCIM_ACS_USP_MEM_TGT_ACC_CTL) >> 10]); 1074 } 1075 } 1076 1077 static struct { 1078 uint16_t id; 1079 const char *name; 1080 } ecap_names[] = { 1081 { PCIZ_AER, "AER" }, 1082 { PCIZ_VC, "Virtual Channel" }, 1083 { PCIZ_SERNUM, "Device Serial Number" }, 1084 { PCIZ_PWRBDGT, "Power Budgeting" }, 1085 { PCIZ_RCLINK_DCL, "Root Complex Link Declaration" }, 1086 { PCIZ_RCLINK_CTL, "Root Complex Internal Link Control" }, 1087 { PCIZ_RCEC_ASSOC, "Root Complex Event Collector ASsociation" }, 1088 { PCIZ_MFVC, "MFVC" }, 1089 { PCIZ_VC2, "Virtual Channel 2" }, 1090 { PCIZ_RCRB, "RCRB" }, 1091 { PCIZ_CAC, "Configuration Access Correction" }, 1092 { PCIZ_ACS, "ACS" }, 1093 { PCIZ_ARI, "ARI" }, 1094 { PCIZ_ATS, "ATS" }, 1095 { PCIZ_SRIOV, "SRIOV" }, 1096 { PCIZ_MRIOV, "MRIOV" }, 1097 { PCIZ_MULTICAST, "Multicast" }, 1098 { PCIZ_PAGE_REQ, "Page Page Request" }, 1099 { PCIZ_AMD, "AMD proprietary "}, 1100 { PCIZ_RESIZE_BAR, "Resizable BAR" }, 1101 { PCIZ_DPA, "DPA" }, 1102 { PCIZ_TPH_REQ, "TPH Requester" }, 1103 { PCIZ_LTR, "LTR" }, 1104 { PCIZ_SEC_PCIE, "Secondary PCI Express" }, 1105 { PCIZ_PMUX, "Protocol Multiplexing" }, 1106 { PCIZ_PASID, "Process Address Space ID" }, 1107 { PCIZ_LN_REQ, "LN Requester" }, 1108 { PCIZ_DPC, "Downstream Port Containment" }, 1109 { PCIZ_L1PM, "L1 PM Substates" }, 1110 { PCIZ_PTM, "Precision Time Measurement" }, 1111 { PCIZ_M_PCIE, "PCIe over M-PHY" }, 1112 { PCIZ_FRS, "FRS Queuing" }, 1113 { PCIZ_RTR, "Readiness Time Reporting" }, 1114 { PCIZ_DVSEC, "Designated Vendor-Specific" }, 1115 { PCIZ_VF_REBAR, "VF Resizable BAR" }, 1116 { PCIZ_DLNK, "Data Link Feature" }, 1117 { PCIZ_16GT, "Physical Layer 16.0 GT/s" }, 1118 { PCIZ_LMR, "Lane Margining at Receiver" }, 1119 { PCIZ_HIER_ID, "Hierarchy ID" }, 1120 { PCIZ_NPEM, "Native PCIe Enclosure Management" }, 1121 { PCIZ_PL32, "Physical Layer 32.0 GT/s" }, 1122 { PCIZ_AP, "Alternate Protocol" }, 1123 { PCIZ_SFI, "System Firmware Intermediary" }, 1124 { 0, NULL } 1125 }; 1126 1127 static void 1128 list_ecaps(int fd, struct pci_conf *p) 1129 { 1130 const char *name; 1131 uint32_t ecap; 1132 uint16_t ptr; 1133 int i; 1134 1135 ptr = PCIR_EXTCAP; 1136 ecap = read_config(fd, &p->pc_sel, ptr, 4); 1137 if (ecap == 0xffffffff || ecap == 0) 1138 return; 1139 for (;;) { 1140 printf(" ecap %04x[%03x] = ", PCI_EXTCAP_ID(ecap), ptr); 1141 switch (PCI_EXTCAP_ID(ecap)) { 1142 case PCIZ_AER: 1143 ecap_aer(fd, p, ptr, PCI_EXTCAP_VER(ecap)); 1144 break; 1145 case PCIZ_VC: 1146 ecap_vc(fd, p, ptr, PCI_EXTCAP_VER(ecap)); 1147 break; 1148 case PCIZ_SERNUM: 1149 ecap_sernum(fd, p, ptr, PCI_EXTCAP_VER(ecap)); 1150 break; 1151 case PCIZ_VENDOR: 1152 ecap_vendor(fd, p, ptr, PCI_EXTCAP_VER(ecap)); 1153 break; 1154 case PCIZ_SEC_PCIE: 1155 ecap_sec_pcie(fd, p, ptr, PCI_EXTCAP_VER(ecap)); 1156 break; 1157 case PCIZ_SRIOV: 1158 ecap_sriov(fd, p, ptr, PCI_EXTCAP_VER(ecap)); 1159 break; 1160 case PCIZ_ACS: 1161 ecap_acs(fd, p, ptr, PCI_EXTCAP_VER(ecap)); 1162 break; 1163 default: 1164 name = "unknown"; 1165 for (i = 0; ecap_names[i].name != NULL; i++) 1166 if (ecap_names[i].id == PCI_EXTCAP_ID(ecap)) { 1167 name = ecap_names[i].name; 1168 break; 1169 } 1170 printf("%s %d\n", name, PCI_EXTCAP_VER(ecap)); 1171 break; 1172 } 1173 ptr = PCI_EXTCAP_NEXTPTR(ecap); 1174 if (ptr == 0) 1175 break; 1176 ecap = read_config(fd, &p->pc_sel, ptr, 4); 1177 } 1178 } 1179 1180 /* Find offset of a specific capability. Returns 0 on failure. */ 1181 uint8_t 1182 pci_find_cap(int fd, struct pci_conf *p, uint8_t id) 1183 { 1184 uint16_t sta; 1185 uint8_t ptr, cap; 1186 1187 /* Are capabilities present for this device? */ 1188 sta = read_config(fd, &p->pc_sel, PCIR_STATUS, 2); 1189 if (!(sta & PCIM_STATUS_CAPPRESENT)) 1190 return (0); 1191 1192 switch (p->pc_hdr & PCIM_HDRTYPE) { 1193 case PCIM_HDRTYPE_NORMAL: 1194 case PCIM_HDRTYPE_BRIDGE: 1195 ptr = PCIR_CAP_PTR; 1196 break; 1197 case PCIM_HDRTYPE_CARDBUS: 1198 ptr = PCIR_CAP_PTR_2; 1199 break; 1200 default: 1201 return (0); 1202 } 1203 1204 ptr = read_config(fd, &p->pc_sel, ptr, 1); 1205 while (ptr != 0 && ptr != 0xff) { 1206 cap = read_config(fd, &p->pc_sel, ptr + PCICAP_ID, 1); 1207 if (cap == id) 1208 return (ptr); 1209 ptr = read_config(fd, &p->pc_sel, ptr + PCICAP_NEXTPTR, 1); 1210 } 1211 return (0); 1212 } 1213 1214 /* Find offset of a specific extended capability. Returns 0 on failure. */ 1215 uint16_t 1216 pcie_find_cap(int fd, struct pci_conf *p, uint16_t id) 1217 { 1218 uint32_t ecap; 1219 uint16_t ptr; 1220 1221 ptr = PCIR_EXTCAP; 1222 ecap = read_config(fd, &p->pc_sel, ptr, 4); 1223 if (ecap == 0xffffffff || ecap == 0) 1224 return (0); 1225 for (;;) { 1226 if (PCI_EXTCAP_ID(ecap) == id) 1227 return (ptr); 1228 ptr = PCI_EXTCAP_NEXTPTR(ecap); 1229 if (ptr == 0) 1230 break; 1231 ecap = read_config(fd, &p->pc_sel, ptr, 4); 1232 } 1233 return (0); 1234 } 1235