1 /*- 2 * SPDX-License-Identifier: BSD-3-Clause 3 * 4 * Copyright (c) 2007 Yahoo!, Inc. 5 * All rights reserved. 6 * Written by: John Baldwin <jhb@FreeBSD.org> 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 3. Neither the name of the author nor the names of any co-contributors 17 * may be used to endorse or promote products derived from this software 18 * without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 24 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 25 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 26 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 27 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 28 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 29 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 30 * SUCH DAMAGE. 31 */ 32 33 #ifndef lint 34 static const char rcsid[] = 35 "$FreeBSD$"; 36 #endif /* not lint */ 37 38 #include <sys/types.h> 39 40 #include <err.h> 41 #include <stdio.h> 42 #include <strings.h> 43 #include <sys/agpio.h> 44 #include <sys/pciio.h> 45 46 #include <dev/agp/agpreg.h> 47 #include <dev/pci/pcireg.h> 48 49 #include "pciconf.h" 50 51 static void list_ecaps(int fd, struct pci_conf *p); 52 53 static int cap_level; 54 55 static void 56 cap_power(int fd, struct pci_conf *p, uint8_t ptr) 57 { 58 uint16_t cap, status; 59 60 cap = read_config(fd, &p->pc_sel, ptr + PCIR_POWER_CAP, 2); 61 status = read_config(fd, &p->pc_sel, ptr + PCIR_POWER_STATUS, 2); 62 printf("powerspec %d supports D0%s%s D3 current D%d", 63 cap & PCIM_PCAP_SPEC, 64 cap & PCIM_PCAP_D1SUPP ? " D1" : "", 65 cap & PCIM_PCAP_D2SUPP ? " D2" : "", 66 status & PCIM_PSTAT_DMASK); 67 } 68 69 static void 70 cap_agp(int fd, struct pci_conf *p, uint8_t ptr) 71 { 72 uint32_t status, command; 73 74 status = read_config(fd, &p->pc_sel, ptr + AGP_STATUS, 4); 75 command = read_config(fd, &p->pc_sel, ptr + AGP_CAPID, 4); 76 printf("AGP "); 77 if (AGP_MODE_GET_MODE_3(status)) { 78 printf("v3 "); 79 if (AGP_MODE_GET_RATE(status) & AGP_MODE_V3_RATE_8x) 80 printf("8x "); 81 if (AGP_MODE_GET_RATE(status) & AGP_MODE_V3_RATE_4x) 82 printf("4x "); 83 } else { 84 if (AGP_MODE_GET_RATE(status) & AGP_MODE_V2_RATE_4x) 85 printf("4x "); 86 if (AGP_MODE_GET_RATE(status) & AGP_MODE_V2_RATE_2x) 87 printf("2x "); 88 if (AGP_MODE_GET_RATE(status) & AGP_MODE_V2_RATE_1x) 89 printf("1x "); 90 } 91 if (AGP_MODE_GET_SBA(status)) 92 printf("SBA "); 93 if (AGP_MODE_GET_AGP(command)) { 94 printf("enabled at "); 95 if (AGP_MODE_GET_MODE_3(command)) { 96 printf("v3 "); 97 switch (AGP_MODE_GET_RATE(command)) { 98 case AGP_MODE_V3_RATE_8x: 99 printf("8x "); 100 break; 101 case AGP_MODE_V3_RATE_4x: 102 printf("4x "); 103 break; 104 } 105 } else 106 switch (AGP_MODE_GET_RATE(command)) { 107 case AGP_MODE_V2_RATE_4x: 108 printf("4x "); 109 break; 110 case AGP_MODE_V2_RATE_2x: 111 printf("2x "); 112 break; 113 case AGP_MODE_V2_RATE_1x: 114 printf("1x "); 115 break; 116 } 117 if (AGP_MODE_GET_SBA(command)) 118 printf("SBA "); 119 } else 120 printf("disabled"); 121 } 122 123 static void 124 cap_vpd(int fd __unused, struct pci_conf *p __unused, uint8_t ptr __unused) 125 { 126 127 printf("VPD"); 128 } 129 130 static void 131 cap_msi(int fd, struct pci_conf *p, uint8_t ptr) 132 { 133 uint16_t ctrl; 134 int msgnum; 135 136 ctrl = read_config(fd, &p->pc_sel, ptr + PCIR_MSI_CTRL, 2); 137 msgnum = 1 << ((ctrl & PCIM_MSICTRL_MMC_MASK) >> 1); 138 printf("MSI supports %d message%s%s%s ", msgnum, 139 (msgnum == 1) ? "" : "s", 140 (ctrl & PCIM_MSICTRL_64BIT) ? ", 64 bit" : "", 141 (ctrl & PCIM_MSICTRL_VECTOR) ? ", vector masks" : ""); 142 if (ctrl & PCIM_MSICTRL_MSI_ENABLE) { 143 msgnum = 1 << ((ctrl & PCIM_MSICTRL_MME_MASK) >> 4); 144 printf("enabled with %d message%s", msgnum, 145 (msgnum == 1) ? "" : "s"); 146 } 147 } 148 149 static void 150 cap_pcix(int fd, struct pci_conf *p, uint8_t ptr) 151 { 152 uint32_t status; 153 int comma, max_splits, max_burst_read; 154 155 status = read_config(fd, &p->pc_sel, ptr + PCIXR_STATUS, 4); 156 printf("PCI-X "); 157 if (status & PCIXM_STATUS_64BIT) 158 printf("64-bit "); 159 if ((p->pc_hdr & PCIM_HDRTYPE) == 1) 160 printf("bridge "); 161 if ((p->pc_hdr & PCIM_HDRTYPE) != 1 || (status & (PCIXM_STATUS_133CAP | 162 PCIXM_STATUS_266CAP | PCIXM_STATUS_533CAP)) != 0) 163 printf("supports"); 164 comma = 0; 165 if (status & PCIXM_STATUS_133CAP) { 166 printf(" 133MHz"); 167 comma = 1; 168 } 169 if (status & PCIXM_STATUS_266CAP) { 170 printf("%s 266MHz", comma ? "," : ""); 171 comma = 1; 172 } 173 if (status & PCIXM_STATUS_533CAP) { 174 printf("%s 533MHz", comma ? "," : ""); 175 comma = 1; 176 } 177 if ((p->pc_hdr & PCIM_HDRTYPE) == 1) 178 return; 179 max_burst_read = 0; 180 switch (status & PCIXM_STATUS_MAX_READ) { 181 case PCIXM_STATUS_MAX_READ_512: 182 max_burst_read = 512; 183 break; 184 case PCIXM_STATUS_MAX_READ_1024: 185 max_burst_read = 1024; 186 break; 187 case PCIXM_STATUS_MAX_READ_2048: 188 max_burst_read = 2048; 189 break; 190 case PCIXM_STATUS_MAX_READ_4096: 191 max_burst_read = 4096; 192 break; 193 } 194 max_splits = 0; 195 switch (status & PCIXM_STATUS_MAX_SPLITS) { 196 case PCIXM_STATUS_MAX_SPLITS_1: 197 max_splits = 1; 198 break; 199 case PCIXM_STATUS_MAX_SPLITS_2: 200 max_splits = 2; 201 break; 202 case PCIXM_STATUS_MAX_SPLITS_3: 203 max_splits = 3; 204 break; 205 case PCIXM_STATUS_MAX_SPLITS_4: 206 max_splits = 4; 207 break; 208 case PCIXM_STATUS_MAX_SPLITS_8: 209 max_splits = 8; 210 break; 211 case PCIXM_STATUS_MAX_SPLITS_12: 212 max_splits = 12; 213 break; 214 case PCIXM_STATUS_MAX_SPLITS_16: 215 max_splits = 16; 216 break; 217 case PCIXM_STATUS_MAX_SPLITS_32: 218 max_splits = 32; 219 break; 220 } 221 printf("%s %d burst read, %d split transaction%s", comma ? "," : "", 222 max_burst_read, max_splits, max_splits == 1 ? "" : "s"); 223 } 224 225 static void 226 cap_ht(int fd, struct pci_conf *p, uint8_t ptr) 227 { 228 uint32_t reg; 229 uint16_t command; 230 231 command = read_config(fd, &p->pc_sel, ptr + PCIR_HT_COMMAND, 2); 232 printf("HT "); 233 if ((command & 0xe000) == PCIM_HTCAP_SLAVE) 234 printf("slave"); 235 else if ((command & 0xe000) == PCIM_HTCAP_HOST) 236 printf("host"); 237 else 238 switch (command & PCIM_HTCMD_CAP_MASK) { 239 case PCIM_HTCAP_SWITCH: 240 printf("switch"); 241 break; 242 case PCIM_HTCAP_INTERRUPT: 243 printf("interrupt"); 244 break; 245 case PCIM_HTCAP_REVISION_ID: 246 printf("revision ID"); 247 break; 248 case PCIM_HTCAP_UNITID_CLUMPING: 249 printf("unit ID clumping"); 250 break; 251 case PCIM_HTCAP_EXT_CONFIG_SPACE: 252 printf("extended config space"); 253 break; 254 case PCIM_HTCAP_ADDRESS_MAPPING: 255 printf("address mapping"); 256 break; 257 case PCIM_HTCAP_MSI_MAPPING: 258 printf("MSI %saddress window %s at 0x", 259 command & PCIM_HTCMD_MSI_FIXED ? "fixed " : "", 260 command & PCIM_HTCMD_MSI_ENABLE ? "enabled" : 261 "disabled"); 262 if (command & PCIM_HTCMD_MSI_FIXED) 263 printf("fee00000"); 264 else { 265 reg = read_config(fd, &p->pc_sel, 266 ptr + PCIR_HTMSI_ADDRESS_HI, 4); 267 if (reg != 0) 268 printf("%08x", reg); 269 reg = read_config(fd, &p->pc_sel, 270 ptr + PCIR_HTMSI_ADDRESS_LO, 4); 271 printf("%08x", reg); 272 } 273 break; 274 case PCIM_HTCAP_DIRECT_ROUTE: 275 printf("direct route"); 276 break; 277 case PCIM_HTCAP_VCSET: 278 printf("VC set"); 279 break; 280 case PCIM_HTCAP_RETRY_MODE: 281 printf("retry mode"); 282 break; 283 case PCIM_HTCAP_X86_ENCODING: 284 printf("X86 encoding"); 285 break; 286 case PCIM_HTCAP_GEN3: 287 printf("Gen3"); 288 break; 289 case PCIM_HTCAP_FLE: 290 printf("function-level extension"); 291 break; 292 case PCIM_HTCAP_PM: 293 printf("power management"); 294 break; 295 case PCIM_HTCAP_HIGH_NODE_COUNT: 296 printf("high node count"); 297 break; 298 default: 299 printf("unknown %02x", command); 300 break; 301 } 302 } 303 304 static void 305 cap_vendor(int fd, struct pci_conf *p, uint8_t ptr) 306 { 307 uint8_t length; 308 309 length = read_config(fd, &p->pc_sel, ptr + PCIR_VENDOR_LENGTH, 1); 310 printf("vendor (length %d)", length); 311 if (p->pc_vendor == 0x8086) { 312 /* Intel */ 313 uint8_t version; 314 315 version = read_config(fd, &p->pc_sel, ptr + PCIR_VENDOR_DATA, 316 1); 317 printf(" Intel cap %d version %d", version >> 4, version & 0xf); 318 if (version >> 4 == 1 && length == 12) { 319 /* Feature Detection */ 320 uint32_t fvec; 321 int comma; 322 323 comma = 0; 324 fvec = read_config(fd, &p->pc_sel, ptr + 325 PCIR_VENDOR_DATA + 5, 4); 326 printf("\n\t\t features:"); 327 if (fvec & (1 << 0)) { 328 printf(" AMT"); 329 comma = 1; 330 } 331 fvec = read_config(fd, &p->pc_sel, ptr + 332 PCIR_VENDOR_DATA + 1, 4); 333 if (fvec & (1 << 21)) { 334 printf("%s Quick Resume", comma ? "," : ""); 335 comma = 1; 336 } 337 if (fvec & (1 << 18)) { 338 printf("%s SATA RAID-5", comma ? "," : ""); 339 comma = 1; 340 } 341 if (fvec & (1 << 9)) { 342 printf("%s Mobile", comma ? "," : ""); 343 comma = 1; 344 } 345 if (fvec & (1 << 7)) { 346 printf("%s 6 PCI-e x1 slots", comma ? "," : ""); 347 comma = 1; 348 } else { 349 printf("%s 4 PCI-e x1 slots", comma ? "," : ""); 350 comma = 1; 351 } 352 if (fvec & (1 << 5)) { 353 printf("%s SATA RAID-0/1/10", comma ? "," : ""); 354 comma = 1; 355 } 356 if (fvec & (1 << 3)) 357 printf(", SATA AHCI"); 358 } 359 } 360 } 361 362 static void 363 cap_debug(int fd, struct pci_conf *p, uint8_t ptr) 364 { 365 uint16_t debug_port; 366 367 debug_port = read_config(fd, &p->pc_sel, ptr + PCIR_DEBUG_PORT, 2); 368 printf("EHCI Debug Port at offset 0x%x in map 0x%x", debug_port & 369 PCIM_DEBUG_PORT_OFFSET, PCIR_BAR(debug_port >> 13)); 370 } 371 372 static void 373 cap_subvendor(int fd, struct pci_conf *p, uint8_t ptr) 374 { 375 uint32_t id; 376 uint16_t ssid, ssvid; 377 378 id = read_config(fd, &p->pc_sel, ptr + PCIR_SUBVENDCAP_ID, 4); 379 ssid = id >> 16; 380 ssvid = id & 0xffff; 381 printf("PCI Bridge subvendor=0x%04x subdevice=0x%04x", ssvid, ssid); 382 } 383 384 #define MAX_PAYLOAD(field) (128 << (field)) 385 386 static const char * 387 link_speed_string(uint8_t speed) 388 { 389 390 switch (speed) { 391 case 1: 392 return ("2.5"); 393 case 2: 394 return ("5.0"); 395 case 3: 396 return ("8.0"); 397 case 4: 398 return ("16.0"); 399 default: 400 return ("undef"); 401 } 402 } 403 404 static const char * 405 aspm_string(uint8_t aspm) 406 { 407 408 switch (aspm) { 409 case 1: 410 return ("L0s"); 411 case 2: 412 return ("L1"); 413 case 3: 414 return ("L0s/L1"); 415 default: 416 return ("disabled"); 417 } 418 } 419 420 static int 421 slot_power(uint32_t cap) 422 { 423 int mwatts; 424 425 mwatts = (cap & PCIEM_SLOT_CAP_SPLV) >> 7; 426 switch (cap & PCIEM_SLOT_CAP_SPLS) { 427 case 0x0: 428 mwatts *= 1000; 429 break; 430 case 0x1: 431 mwatts *= 100; 432 break; 433 case 0x2: 434 mwatts *= 10; 435 break; 436 default: 437 break; 438 } 439 return (mwatts); 440 } 441 442 static void 443 cap_express(int fd, struct pci_conf *p, uint8_t ptr) 444 { 445 uint32_t cap; 446 uint16_t ctl, flags, sta; 447 unsigned int version; 448 449 flags = read_config(fd, &p->pc_sel, ptr + PCIER_FLAGS, 2); 450 version = flags & PCIEM_FLAGS_VERSION; 451 printf("PCI-Express %u ", version); 452 switch (flags & PCIEM_FLAGS_TYPE) { 453 case PCIEM_TYPE_ENDPOINT: 454 printf("endpoint"); 455 break; 456 case PCIEM_TYPE_LEGACY_ENDPOINT: 457 printf("legacy endpoint"); 458 break; 459 case PCIEM_TYPE_ROOT_PORT: 460 printf("root port"); 461 break; 462 case PCIEM_TYPE_UPSTREAM_PORT: 463 printf("upstream port"); 464 break; 465 case PCIEM_TYPE_DOWNSTREAM_PORT: 466 printf("downstream port"); 467 break; 468 case PCIEM_TYPE_PCI_BRIDGE: 469 printf("PCI bridge"); 470 break; 471 case PCIEM_TYPE_PCIE_BRIDGE: 472 printf("PCI to PCIe bridge"); 473 break; 474 case PCIEM_TYPE_ROOT_INT_EP: 475 printf("root endpoint"); 476 break; 477 case PCIEM_TYPE_ROOT_EC: 478 printf("event collector"); 479 break; 480 default: 481 printf("type %d", (flags & PCIEM_FLAGS_TYPE) >> 4); 482 break; 483 } 484 if (flags & PCIEM_FLAGS_IRQ) 485 printf(" MSI %d", (flags & PCIEM_FLAGS_IRQ) >> 9); 486 cap = read_config(fd, &p->pc_sel, ptr + PCIER_DEVICE_CAP, 4); 487 ctl = read_config(fd, &p->pc_sel, ptr + PCIER_DEVICE_CTL, 2); 488 printf(" max data %d(%d)", 489 MAX_PAYLOAD((ctl & PCIEM_CTL_MAX_PAYLOAD) >> 5), 490 MAX_PAYLOAD(cap & PCIEM_CAP_MAX_PAYLOAD)); 491 if ((cap & PCIEM_CAP_FLR) != 0) 492 printf(" FLR"); 493 if (ctl & PCIEM_CTL_RELAXED_ORD_ENABLE) 494 printf(" RO"); 495 if (ctl & PCIEM_CTL_NOSNOOP_ENABLE) 496 printf(" NS"); 497 if (version >= 2) { 498 cap = read_config(fd, &p->pc_sel, ptr + PCIER_DEVICE_CAP2, 4); 499 if ((cap & PCIEM_CAP2_ARI) != 0) { 500 ctl = read_config(fd, &p->pc_sel, 501 ptr + PCIER_DEVICE_CTL2, 4); 502 printf(" ARI %s", 503 (ctl & PCIEM_CTL2_ARI) ? "enabled" : "disabled"); 504 } 505 } 506 cap = read_config(fd, &p->pc_sel, ptr + PCIER_LINK_CAP, 4); 507 sta = read_config(fd, &p->pc_sel, ptr + PCIER_LINK_STA, 2); 508 if (cap == 0 && sta == 0) 509 return; 510 printf("\n "); 511 printf(" link x%d(x%d)", (sta & PCIEM_LINK_STA_WIDTH) >> 4, 512 (cap & PCIEM_LINK_CAP_MAX_WIDTH) >> 4); 513 if ((cap & PCIEM_LINK_CAP_MAX_WIDTH) != 0) { 514 printf(" speed %s(%s)", (sta & PCIEM_LINK_STA_WIDTH) == 0 ? 515 "0.0" : link_speed_string(sta & PCIEM_LINK_STA_SPEED), 516 link_speed_string(cap & PCIEM_LINK_CAP_MAX_SPEED)); 517 } 518 if ((cap & PCIEM_LINK_CAP_ASPM) != 0) { 519 ctl = read_config(fd, &p->pc_sel, ptr + PCIER_LINK_CTL, 2); 520 printf(" ASPM %s(%s)", aspm_string(ctl & PCIEM_LINK_CTL_ASPMC), 521 aspm_string((cap & PCIEM_LINK_CAP_ASPM) >> 10)); 522 } 523 if ((cap & PCIEM_LINK_CAP_CLOCK_PM) != 0) { 524 ctl = read_config(fd, &p->pc_sel, ptr + PCIER_LINK_CTL, 2); 525 printf(" ClockPM %s", (ctl & PCIEM_LINK_CTL_ECPM) ? 526 "enabled" : "disabled"); 527 } 528 if (!(flags & PCIEM_FLAGS_SLOT)) 529 return; 530 cap = read_config(fd, &p->pc_sel, ptr + PCIER_SLOT_CAP, 4); 531 sta = read_config(fd, &p->pc_sel, ptr + PCIER_SLOT_STA, 2); 532 ctl = read_config(fd, &p->pc_sel, ptr + PCIER_SLOT_CTL, 2); 533 printf("\n "); 534 printf(" slot %d", (cap & PCIEM_SLOT_CAP_PSN) >> 19); 535 printf(" power limit %d mW", slot_power(cap)); 536 if (cap & PCIEM_SLOT_CAP_HPC) 537 printf(" HotPlug(%s)", sta & PCIEM_SLOT_STA_PDS ? "present" : 538 "empty"); 539 if (cap & PCIEM_SLOT_CAP_HPS) 540 printf(" surprise"); 541 if (cap & PCIEM_SLOT_CAP_APB) 542 printf(" Attn Button"); 543 if (cap & PCIEM_SLOT_CAP_PCP) 544 printf(" PC(%s)", ctl & PCIEM_SLOT_CTL_PCC ? "off" : "on"); 545 if (cap & PCIEM_SLOT_CAP_MRLSP) 546 printf(" MRL(%s)", sta & PCIEM_SLOT_STA_MRLSS ? "open" : 547 "closed"); 548 if (cap & PCIEM_SLOT_CAP_EIP) 549 printf(" EI(%s)", sta & PCIEM_SLOT_STA_EIS ? "engaged" : 550 "disengaged"); 551 } 552 553 static void 554 cap_msix(int fd, struct pci_conf *p, uint8_t ptr) 555 { 556 uint32_t pba_offset, table_offset, val; 557 int msgnum, pba_bar, table_bar; 558 uint16_t ctrl; 559 560 ctrl = read_config(fd, &p->pc_sel, ptr + PCIR_MSIX_CTRL, 2); 561 msgnum = (ctrl & PCIM_MSIXCTRL_TABLE_SIZE) + 1; 562 563 val = read_config(fd, &p->pc_sel, ptr + PCIR_MSIX_TABLE, 4); 564 table_bar = PCIR_BAR(val & PCIM_MSIX_BIR_MASK); 565 table_offset = val & ~PCIM_MSIX_BIR_MASK; 566 567 val = read_config(fd, &p->pc_sel, ptr + PCIR_MSIX_PBA, 4); 568 pba_bar = PCIR_BAR(val & PCIM_MSIX_BIR_MASK); 569 pba_offset = val & ~PCIM_MSIX_BIR_MASK; 570 571 printf("MSI-X supports %d message%s%s\n", msgnum, 572 (msgnum == 1) ? "" : "s", 573 (ctrl & PCIM_MSIXCTRL_MSIX_ENABLE) ? ", enabled" : ""); 574 575 printf(" "); 576 printf("Table in map 0x%x[0x%x], PBA in map 0x%x[0x%x]", 577 table_bar, table_offset, pba_bar, pba_offset); 578 } 579 580 static void 581 cap_sata(int fd __unused, struct pci_conf *p __unused, uint8_t ptr __unused) 582 { 583 584 printf("SATA Index-Data Pair"); 585 } 586 587 static void 588 cap_pciaf(int fd, struct pci_conf *p, uint8_t ptr) 589 { 590 uint8_t cap; 591 592 cap = read_config(fd, &p->pc_sel, ptr + PCIR_PCIAF_CAP, 1); 593 printf("PCI Advanced Features:%s%s", 594 cap & PCIM_PCIAFCAP_FLR ? " FLR" : "", 595 cap & PCIM_PCIAFCAP_TP ? " TP" : ""); 596 } 597 598 static const char * 599 ea_bei_to_name(int bei) 600 { 601 static const char *barstr[] = { 602 "BAR0", "BAR1", "BAR2", "BAR3", "BAR4", "BAR5" 603 }; 604 static const char *vfbarstr[] = { 605 "VFBAR0", "VFBAR1", "VFBAR2", "VFBAR3", "VFBAR4", "VFBAR5" 606 }; 607 608 if ((bei >= PCIM_EA_BEI_BAR_0) && (bei <= PCIM_EA_BEI_BAR_5)) 609 return (barstr[bei - PCIM_EA_BEI_BAR_0]); 610 if ((bei >= PCIM_EA_BEI_VF_BAR_0) && (bei <= PCIM_EA_BEI_VF_BAR_5)) 611 return (vfbarstr[bei - PCIM_EA_BEI_VF_BAR_0]); 612 613 switch (bei) { 614 case PCIM_EA_BEI_BRIDGE: 615 return "BRIDGE"; 616 case PCIM_EA_BEI_ENI: 617 return "ENI"; 618 case PCIM_EA_BEI_ROM: 619 return "ROM"; 620 case PCIM_EA_BEI_RESERVED: 621 default: 622 return "RSVD"; 623 } 624 } 625 626 static const char * 627 ea_prop_to_name(uint8_t prop) 628 { 629 630 switch (prop) { 631 case PCIM_EA_P_MEM: 632 return "Non-Prefetchable Memory"; 633 case PCIM_EA_P_MEM_PREFETCH: 634 return "Prefetchable Memory"; 635 case PCIM_EA_P_IO: 636 return "I/O Space"; 637 case PCIM_EA_P_VF_MEM_PREFETCH: 638 return "VF Prefetchable Memory"; 639 case PCIM_EA_P_VF_MEM: 640 return "VF Non-Prefetchable Memory"; 641 case PCIM_EA_P_BRIDGE_MEM: 642 return "Bridge Non-Prefetchable Memory"; 643 case PCIM_EA_P_BRIDGE_MEM_PREFETCH: 644 return "Bridge Prefetchable Memory"; 645 case PCIM_EA_P_BRIDGE_IO: 646 return "Bridge I/O Space"; 647 case PCIM_EA_P_MEM_RESERVED: 648 return "Reserved Memory"; 649 case PCIM_EA_P_IO_RESERVED: 650 return "Reserved I/O Space"; 651 case PCIM_EA_P_UNAVAILABLE: 652 return "Unavailable"; 653 default: 654 return "Reserved"; 655 } 656 } 657 658 static void 659 cap_ea(int fd, struct pci_conf *p, uint8_t ptr) 660 { 661 int num_ent; 662 int a, b; 663 uint32_t bei; 664 uint32_t val; 665 int ent_size; 666 uint32_t dw[4]; 667 uint32_t flags, flags_pp, flags_sp; 668 uint64_t base, max_offset; 669 uint8_t fixed_sub_bus_nr, fixed_sec_bus_nr; 670 671 /* Determine the number of entries */ 672 num_ent = read_config(fd, &p->pc_sel, ptr + PCIR_EA_NUM_ENT, 2); 673 num_ent &= PCIM_EA_NUM_ENT_MASK; 674 675 printf("PCI Enhanced Allocation (%d entries)", num_ent); 676 677 /* Find the first entry to care of */ 678 ptr += PCIR_EA_FIRST_ENT; 679 680 /* Print BUS numbers for bridges */ 681 if ((p->pc_hdr & PCIM_HDRTYPE) == PCIM_HDRTYPE_BRIDGE) { 682 val = read_config(fd, &p->pc_sel, ptr, 4); 683 684 fixed_sec_bus_nr = PCIM_EA_SEC_NR(val); 685 fixed_sub_bus_nr = PCIM_EA_SUB_NR(val); 686 687 printf("\n\t\t BRIDGE, sec bus [%d], sub bus [%d]", 688 fixed_sec_bus_nr, fixed_sub_bus_nr); 689 ptr += 4; 690 } 691 692 for (a = 0; a < num_ent; a++) { 693 /* Read a number of dwords in the entry */ 694 val = read_config(fd, &p->pc_sel, ptr, 4); 695 ptr += 4; 696 ent_size = (val & PCIM_EA_ES); 697 698 for (b = 0; b < ent_size; b++) { 699 dw[b] = read_config(fd, &p->pc_sel, ptr, 4); 700 ptr += 4; 701 } 702 703 flags = val; 704 flags_pp = (flags & PCIM_EA_PP) >> PCIM_EA_PP_OFFSET; 705 flags_sp = (flags & PCIM_EA_SP) >> PCIM_EA_SP_OFFSET; 706 bei = (PCIM_EA_BEI & val) >> PCIM_EA_BEI_OFFSET; 707 708 base = dw[0] & PCIM_EA_FIELD_MASK; 709 max_offset = dw[1] | ~PCIM_EA_FIELD_MASK; 710 b = 2; 711 if (((dw[0] & PCIM_EA_IS_64) != 0) && (b < ent_size)) { 712 base |= (uint64_t)dw[b] << 32UL; 713 b++; 714 } 715 if (((dw[1] & PCIM_EA_IS_64) != 0) 716 && (b < ent_size)) { 717 max_offset |= (uint64_t)dw[b] << 32UL; 718 b++; 719 } 720 721 printf("\n\t\t [%d] %s, %s, %s, base [0x%jx], size [0x%jx]" 722 "\n\t\t\tPrimary properties [0x%x] (%s)" 723 "\n\t\t\tSecondary properties [0x%x] (%s)", 724 bei, ea_bei_to_name(bei), 725 (flags & PCIM_EA_ENABLE ? "Enabled" : "Disabled"), 726 (flags & PCIM_EA_WRITABLE ? "Writable" : "Read-only"), 727 (uintmax_t)base, (uintmax_t)(max_offset + 1), 728 flags_pp, ea_prop_to_name(flags_pp), 729 flags_sp, ea_prop_to_name(flags_sp)); 730 } 731 } 732 733 void 734 list_caps(int fd, struct pci_conf *p, int level) 735 { 736 int express; 737 uint16_t sta; 738 uint8_t ptr, cap; 739 740 /* Are capabilities present for this device? */ 741 sta = read_config(fd, &p->pc_sel, PCIR_STATUS, 2); 742 if (!(sta & PCIM_STATUS_CAPPRESENT)) 743 return; 744 745 cap_level = level; 746 747 switch (p->pc_hdr & PCIM_HDRTYPE) { 748 case PCIM_HDRTYPE_NORMAL: 749 case PCIM_HDRTYPE_BRIDGE: 750 ptr = PCIR_CAP_PTR; 751 break; 752 case PCIM_HDRTYPE_CARDBUS: 753 ptr = PCIR_CAP_PTR_2; 754 break; 755 default: 756 errx(1, "list_caps: bad header type"); 757 } 758 759 /* Walk the capability list. */ 760 express = 0; 761 ptr = read_config(fd, &p->pc_sel, ptr, 1); 762 while (ptr != 0 && ptr != 0xff) { 763 cap = read_config(fd, &p->pc_sel, ptr + PCICAP_ID, 1); 764 printf(" cap %02x[%02x] = ", cap, ptr); 765 switch (cap) { 766 case PCIY_PMG: 767 cap_power(fd, p, ptr); 768 break; 769 case PCIY_AGP: 770 cap_agp(fd, p, ptr); 771 break; 772 case PCIY_VPD: 773 cap_vpd(fd, p, ptr); 774 break; 775 case PCIY_MSI: 776 cap_msi(fd, p, ptr); 777 break; 778 case PCIY_PCIX: 779 cap_pcix(fd, p, ptr); 780 break; 781 case PCIY_HT: 782 cap_ht(fd, p, ptr); 783 break; 784 case PCIY_VENDOR: 785 cap_vendor(fd, p, ptr); 786 break; 787 case PCIY_DEBUG: 788 cap_debug(fd, p, ptr); 789 break; 790 case PCIY_SUBVENDOR: 791 cap_subvendor(fd, p, ptr); 792 break; 793 case PCIY_EXPRESS: 794 express = 1; 795 cap_express(fd, p, ptr); 796 break; 797 case PCIY_MSIX: 798 cap_msix(fd, p, ptr); 799 break; 800 case PCIY_SATA: 801 cap_sata(fd, p, ptr); 802 break; 803 case PCIY_PCIAF: 804 cap_pciaf(fd, p, ptr); 805 break; 806 case PCIY_EA: 807 cap_ea(fd, p, ptr); 808 break; 809 default: 810 printf("unknown"); 811 break; 812 } 813 printf("\n"); 814 ptr = read_config(fd, &p->pc_sel, ptr + PCICAP_NEXTPTR, 1); 815 } 816 817 if (express) 818 list_ecaps(fd, p); 819 } 820 821 /* From <sys/systm.h>. */ 822 static __inline uint32_t 823 bitcount32(uint32_t x) 824 { 825 826 x = (x & 0x55555555) + ((x & 0xaaaaaaaa) >> 1); 827 x = (x & 0x33333333) + ((x & 0xcccccccc) >> 2); 828 x = (x + (x >> 4)) & 0x0f0f0f0f; 829 x = (x + (x >> 8)); 830 x = (x + (x >> 16)) & 0x000000ff; 831 return (x); 832 } 833 834 static void 835 ecap_aer(int fd, struct pci_conf *p, uint16_t ptr, uint8_t ver) 836 { 837 uint32_t sta, mask; 838 839 printf("AER %d", ver); 840 if (ver < 1) 841 return; 842 sta = read_config(fd, &p->pc_sel, ptr + PCIR_AER_UC_STATUS, 4); 843 mask = read_config(fd, &p->pc_sel, ptr + PCIR_AER_UC_SEVERITY, 4); 844 printf(" %d fatal", bitcount32(sta & mask)); 845 printf(" %d non-fatal", bitcount32(sta & ~mask)); 846 sta = read_config(fd, &p->pc_sel, ptr + PCIR_AER_COR_STATUS, 4); 847 printf(" %d corrected\n", bitcount32(sta)); 848 } 849 850 static void 851 ecap_vc(int fd, struct pci_conf *p, uint16_t ptr, uint8_t ver) 852 { 853 uint32_t cap1; 854 855 printf("VC %d", ver); 856 if (ver < 1) 857 return; 858 cap1 = read_config(fd, &p->pc_sel, ptr + PCIR_VC_CAP1, 4); 859 printf(" max VC%d", cap1 & PCIM_VC_CAP1_EXT_COUNT); 860 if ((cap1 & PCIM_VC_CAP1_LOWPRI_EXT_COUNT) != 0) 861 printf(" lowpri VC0-VC%d", 862 (cap1 & PCIM_VC_CAP1_LOWPRI_EXT_COUNT) >> 4); 863 printf("\n"); 864 } 865 866 static void 867 ecap_sernum(int fd, struct pci_conf *p, uint16_t ptr, uint8_t ver) 868 { 869 uint32_t high, low; 870 871 printf("Serial %d", ver); 872 if (ver < 1) 873 return; 874 low = read_config(fd, &p->pc_sel, ptr + PCIR_SERIAL_LOW, 4); 875 high = read_config(fd, &p->pc_sel, ptr + PCIR_SERIAL_HIGH, 4); 876 printf(" %08x%08x\n", high, low); 877 } 878 879 static void 880 ecap_vendor(int fd, struct pci_conf *p, uint16_t ptr, uint8_t ver) 881 { 882 uint32_t val, hdr; 883 uint16_t nextptr, len; 884 int i; 885 886 val = read_config(fd, &p->pc_sel, ptr, 4); 887 nextptr = PCI_EXTCAP_NEXTPTR(val); 888 hdr = read_config(fd, &p->pc_sel, ptr + PCIR_VSEC_HEADER, 4); 889 len = PCIR_VSEC_LENGTH(hdr); 890 if (len == 0) { 891 if (nextptr == 0) 892 nextptr = 0x1000; 893 len = nextptr - ptr; 894 } 895 896 printf("Vendor [%d] ID %04x Rev %d Length %d\n", ver, 897 PCIR_VSEC_ID(hdr), PCIR_VSEC_REV(hdr), len); 898 if ((ver < 1) || (cap_level <= 1)) 899 return; 900 for (i = 0; i < len; i += 4) { 901 val = read_config(fd, &p->pc_sel, ptr + i, 4); 902 if ((i % 16) == 0) 903 printf(" "); 904 printf("%02x %02x %02x %02x", val & 0xff, (val >> 8) & 0xff, 905 (val >> 16) & 0xff, (val >> 24) & 0xff); 906 if ((((i + 4) % 16) == 0 ) || ((i + 4) >= len)) 907 printf("\n"); 908 else 909 printf(" "); 910 } 911 } 912 913 static void 914 ecap_sec_pcie(int fd, struct pci_conf *p, uint16_t ptr, uint8_t ver) 915 { 916 uint32_t val; 917 918 printf("PCIe Sec %d", ver); 919 if (ver < 1) 920 return; 921 val = read_config(fd, &p->pc_sel, ptr + 8, 4); 922 printf(" lane errors %#x\n", val); 923 } 924 925 static const char * 926 check_enabled(int value) 927 { 928 929 return (value ? "enabled" : "disabled"); 930 } 931 932 static void 933 ecap_sriov(int fd, struct pci_conf *p, uint16_t ptr, uint8_t ver) 934 { 935 const char *comma, *enabled; 936 uint16_t iov_ctl, total_vfs, num_vfs, vf_offset, vf_stride, vf_did; 937 uint32_t page_caps, page_size, page_shift, size; 938 int i; 939 940 printf("SR-IOV %d ", ver); 941 942 iov_ctl = read_config(fd, &p->pc_sel, ptr + PCIR_SRIOV_CTL, 2); 943 printf("IOV %s, Memory Space %s, ARI %s\n", 944 check_enabled(iov_ctl & PCIM_SRIOV_VF_EN), 945 check_enabled(iov_ctl & PCIM_SRIOV_VF_MSE), 946 check_enabled(iov_ctl & PCIM_SRIOV_ARI_EN)); 947 948 total_vfs = read_config(fd, &p->pc_sel, ptr + PCIR_SRIOV_TOTAL_VFS, 2); 949 num_vfs = read_config(fd, &p->pc_sel, ptr + PCIR_SRIOV_NUM_VFS, 2); 950 printf(" "); 951 printf("%d VFs configured out of %d supported\n", num_vfs, total_vfs); 952 953 vf_offset = read_config(fd, &p->pc_sel, ptr + PCIR_SRIOV_VF_OFF, 2); 954 vf_stride = read_config(fd, &p->pc_sel, ptr + PCIR_SRIOV_VF_STRIDE, 2); 955 printf(" "); 956 printf("First VF RID Offset 0x%04x, VF RID Stride 0x%04x\n", vf_offset, 957 vf_stride); 958 959 vf_did = read_config(fd, &p->pc_sel, ptr + PCIR_SRIOV_VF_DID, 2); 960 printf(" VF Device ID 0x%04x\n", vf_did); 961 962 page_caps = read_config(fd, &p->pc_sel, ptr + PCIR_SRIOV_PAGE_CAP, 4); 963 page_size = read_config(fd, &p->pc_sel, ptr + PCIR_SRIOV_PAGE_SIZE, 4); 964 printf(" "); 965 printf("Page Sizes: "); 966 comma = ""; 967 while (page_caps != 0) { 968 page_shift = ffs(page_caps) - 1; 969 970 if (page_caps & page_size) 971 enabled = " (enabled)"; 972 else 973 enabled = ""; 974 975 size = (1 << (page_shift + PCI_SRIOV_BASE_PAGE_SHIFT)); 976 printf("%s%d%s", comma, size, enabled); 977 comma = ", "; 978 979 page_caps &= ~(1 << page_shift); 980 } 981 printf("\n"); 982 983 for (i = 0; i <= PCIR_MAX_BAR_0; i++) 984 print_bar(fd, p, "iov bar ", ptr + PCIR_SRIOV_BAR(i)); 985 } 986 987 static struct { 988 uint16_t id; 989 const char *name; 990 } ecap_names[] = { 991 { PCIZ_AER, "AER" }, 992 { PCIZ_VC, "Virtual Channel" }, 993 { PCIZ_SERNUM, "Device Serial Number" }, 994 { PCIZ_PWRBDGT, "Power Budgeting" }, 995 { PCIZ_RCLINK_DCL, "Root Complex Link Declaration" }, 996 { PCIZ_RCLINK_CTL, "Root Complex Internal Link Control" }, 997 { PCIZ_RCEC_ASSOC, "Root Complex Event Collector ASsociation" }, 998 { PCIZ_MFVC, "MFVC" }, 999 { PCIZ_VC2, "Virtual Channel 2" }, 1000 { PCIZ_RCRB, "RCRB" }, 1001 { PCIZ_CAC, "Configuration Access Correction" }, 1002 { PCIZ_ACS, "ACS" }, 1003 { PCIZ_ARI, "ARI" }, 1004 { PCIZ_ATS, "ATS" }, 1005 { PCIZ_SRIOV, "SRIOV" }, 1006 { PCIZ_MRIOV, "MRIOV" }, 1007 { PCIZ_MULTICAST, "Multicast" }, 1008 { PCIZ_PAGE_REQ, "Page Page Request" }, 1009 { PCIZ_AMD, "AMD proprietary "}, 1010 { PCIZ_RESIZE_BAR, "Resizable BAR" }, 1011 { PCIZ_DPA, "DPA" }, 1012 { PCIZ_TPH_REQ, "TPH Requester" }, 1013 { PCIZ_LTR, "LTR" }, 1014 { PCIZ_SEC_PCIE, "Secondary PCI Express" }, 1015 { PCIZ_PMUX, "Protocol Multiplexing" }, 1016 { PCIZ_PASID, "Process Address Space ID" }, 1017 { PCIZ_LN_REQ, "LN Requester" }, 1018 { PCIZ_DPC, "Downstream Port Containment" }, 1019 { PCIZ_L1PM, "L1 PM Substates" }, 1020 { PCIZ_PTM, "Precision Time Measurement" }, 1021 { PCIZ_M_PCIE, "PCIe over M-PHY" }, 1022 { PCIZ_FRS, "FRS Queuing" }, 1023 { PCIZ_RTR, "Readiness Time Reporting" }, 1024 { PCIZ_DVSEC, "Designated Vendor-Specific" }, 1025 { PCIZ_VF_REBAR, "VF Resizable BAR" }, 1026 { PCIZ_DLNK, "Data Link Feature" }, 1027 { PCIZ_16GT, "Physical Layer 16.0 GT/s" }, 1028 { PCIZ_LMR, "Lane Margining at Receiver" }, 1029 { PCIZ_HIER_ID, "Hierarchy ID" }, 1030 { PCIZ_NPEM, "Native PCIe Enclosure Management" }, 1031 { PCIZ_PL32, "Physical Layer 32.0 GT/s" }, 1032 { PCIZ_AP, "Alternate Protocol" }, 1033 { PCIZ_SFI, "System Firmware Intermediary" }, 1034 { 0, NULL } 1035 }; 1036 1037 static void 1038 list_ecaps(int fd, struct pci_conf *p) 1039 { 1040 const char *name; 1041 uint32_t ecap; 1042 uint16_t ptr; 1043 int i; 1044 1045 ptr = PCIR_EXTCAP; 1046 ecap = read_config(fd, &p->pc_sel, ptr, 4); 1047 if (ecap == 0xffffffff || ecap == 0) 1048 return; 1049 for (;;) { 1050 printf(" ecap %04x[%03x] = ", PCI_EXTCAP_ID(ecap), ptr); 1051 switch (PCI_EXTCAP_ID(ecap)) { 1052 case PCIZ_AER: 1053 ecap_aer(fd, p, ptr, PCI_EXTCAP_VER(ecap)); 1054 break; 1055 case PCIZ_VC: 1056 ecap_vc(fd, p, ptr, PCI_EXTCAP_VER(ecap)); 1057 break; 1058 case PCIZ_SERNUM: 1059 ecap_sernum(fd, p, ptr, PCI_EXTCAP_VER(ecap)); 1060 break; 1061 case PCIZ_VENDOR: 1062 ecap_vendor(fd, p, ptr, PCI_EXTCAP_VER(ecap)); 1063 break; 1064 case PCIZ_SEC_PCIE: 1065 ecap_sec_pcie(fd, p, ptr, PCI_EXTCAP_VER(ecap)); 1066 break; 1067 case PCIZ_SRIOV: 1068 ecap_sriov(fd, p, ptr, PCI_EXTCAP_VER(ecap)); 1069 break; 1070 default: 1071 name = "unknown"; 1072 for (i = 0; ecap_names[i].name != NULL; i++) 1073 if (ecap_names[i].id == PCI_EXTCAP_ID(ecap)) { 1074 name = ecap_names[i].name; 1075 break; 1076 } 1077 printf("%s %d\n", name, PCI_EXTCAP_VER(ecap)); 1078 break; 1079 } 1080 ptr = PCI_EXTCAP_NEXTPTR(ecap); 1081 if (ptr == 0) 1082 break; 1083 ecap = read_config(fd, &p->pc_sel, ptr, 4); 1084 } 1085 } 1086 1087 /* Find offset of a specific capability. Returns 0 on failure. */ 1088 uint8_t 1089 pci_find_cap(int fd, struct pci_conf *p, uint8_t id) 1090 { 1091 uint16_t sta; 1092 uint8_t ptr, cap; 1093 1094 /* Are capabilities present for this device? */ 1095 sta = read_config(fd, &p->pc_sel, PCIR_STATUS, 2); 1096 if (!(sta & PCIM_STATUS_CAPPRESENT)) 1097 return (0); 1098 1099 switch (p->pc_hdr & PCIM_HDRTYPE) { 1100 case PCIM_HDRTYPE_NORMAL: 1101 case PCIM_HDRTYPE_BRIDGE: 1102 ptr = PCIR_CAP_PTR; 1103 break; 1104 case PCIM_HDRTYPE_CARDBUS: 1105 ptr = PCIR_CAP_PTR_2; 1106 break; 1107 default: 1108 return (0); 1109 } 1110 1111 ptr = read_config(fd, &p->pc_sel, ptr, 1); 1112 while (ptr != 0 && ptr != 0xff) { 1113 cap = read_config(fd, &p->pc_sel, ptr + PCICAP_ID, 1); 1114 if (cap == id) 1115 return (ptr); 1116 ptr = read_config(fd, &p->pc_sel, ptr + PCICAP_NEXTPTR, 1); 1117 } 1118 return (0); 1119 } 1120 1121 /* Find offset of a specific extended capability. Returns 0 on failure. */ 1122 uint16_t 1123 pcie_find_cap(int fd, struct pci_conf *p, uint16_t id) 1124 { 1125 uint32_t ecap; 1126 uint16_t ptr; 1127 1128 ptr = PCIR_EXTCAP; 1129 ecap = read_config(fd, &p->pc_sel, ptr, 4); 1130 if (ecap == 0xffffffff || ecap == 0) 1131 return (0); 1132 for (;;) { 1133 if (PCI_EXTCAP_ID(ecap) == id) 1134 return (ptr); 1135 ptr = PCI_EXTCAP_NEXTPTR(ecap); 1136 if (ptr == 0) 1137 break; 1138 ecap = read_config(fd, &p->pc_sel, ptr, 4); 1139 } 1140 return (0); 1141 } 1142