1 /* 2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD 3 * 4 * Copyright (c) 2016 Alexander Motin <mav@FreeBSD.org> 5 * Copyright (c) 2015 Peter Grehan <grehan@freebsd.org> 6 * Copyright (c) 2013 Jeremiah Lott, Avere Systems 7 * All rights reserved. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer 14 * in this position and unchanged. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 20 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 21 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 22 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 23 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 24 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 25 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 26 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 27 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 28 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 29 * SUCH DAMAGE. 30 */ 31 32 #include <sys/cdefs.h> 33 __FBSDID("$FreeBSD$"); 34 35 #include <sys/types.h> 36 #ifndef WITHOUT_CAPSICUM 37 #include <sys/capsicum.h> 38 #endif 39 #include <sys/limits.h> 40 #include <sys/ioctl.h> 41 #include <sys/uio.h> 42 #include <net/ethernet.h> 43 #include <netinet/in.h> 44 #include <netinet/tcp.h> 45 46 #ifndef WITHOUT_CAPSICUM 47 #include <capsicum_helpers.h> 48 #endif 49 50 #include <err.h> 51 #include <errno.h> 52 #include <fcntl.h> 53 #include <md5.h> 54 #include <stdio.h> 55 #include <stdlib.h> 56 #include <string.h> 57 #include <sysexits.h> 58 #include <unistd.h> 59 #include <pthread.h> 60 #include <pthread_np.h> 61 62 #include "e1000_regs.h" 63 #include "e1000_defines.h" 64 #include "mii.h" 65 66 #include "bhyverun.h" 67 #include "config.h" 68 #include "debug.h" 69 #include "pci_emul.h" 70 #include "mevent.h" 71 #include "net_utils.h" 72 #include "net_backends.h" 73 74 /* Hardware/register definitions XXX: move some to common code. */ 75 #define E82545_VENDOR_ID_INTEL 0x8086 76 #define E82545_DEV_ID_82545EM_COPPER 0x100F 77 #define E82545_SUBDEV_ID 0x1008 78 79 #define E82545_REVISION_4 4 80 81 #define E82545_MDIC_DATA_MASK 0x0000FFFF 82 #define E82545_MDIC_OP_MASK 0x0c000000 83 #define E82545_MDIC_IE 0x20000000 84 85 #define E82545_EECD_FWE_DIS 0x00000010 /* Flash writes disabled */ 86 #define E82545_EECD_FWE_EN 0x00000020 /* Flash writes enabled */ 87 #define E82545_EECD_FWE_MASK 0x00000030 /* Flash writes mask */ 88 89 #define E82545_BAR_REGISTER 0 90 #define E82545_BAR_REGISTER_LEN (128*1024) 91 #define E82545_BAR_FLASH 1 92 #define E82545_BAR_FLASH_LEN (64*1024) 93 #define E82545_BAR_IO 2 94 #define E82545_BAR_IO_LEN 8 95 96 #define E82545_IOADDR 0x00000000 97 #define E82545_IODATA 0x00000004 98 #define E82545_IO_REGISTER_MAX 0x0001FFFF 99 #define E82545_IO_FLASH_BASE 0x00080000 100 #define E82545_IO_FLASH_MAX 0x000FFFFF 101 102 #define E82545_ARRAY_ENTRY(reg, offset) (reg + (offset<<2)) 103 #define E82545_RAR_MAX 15 104 #define E82545_MTA_MAX 127 105 #define E82545_VFTA_MAX 127 106 107 /* Slightly modified from the driver versions, hardcoded for 3 opcode bits, 108 * followed by 6 address bits. 109 * TODO: make opcode bits and addr bits configurable? 110 * NVM Commands - Microwire */ 111 #define E82545_NVM_OPCODE_BITS 3 112 #define E82545_NVM_ADDR_BITS 6 113 #define E82545_NVM_DATA_BITS 16 114 #define E82545_NVM_OPADDR_BITS (E82545_NVM_OPCODE_BITS + E82545_NVM_ADDR_BITS) 115 #define E82545_NVM_ADDR_MASK ((1 << E82545_NVM_ADDR_BITS)-1) 116 #define E82545_NVM_OPCODE_MASK \ 117 (((1 << E82545_NVM_OPCODE_BITS) - 1) << E82545_NVM_ADDR_BITS) 118 #define E82545_NVM_OPCODE_READ (0x6 << E82545_NVM_ADDR_BITS) /* read */ 119 #define E82545_NVM_OPCODE_WRITE (0x5 << E82545_NVM_ADDR_BITS) /* write */ 120 #define E82545_NVM_OPCODE_ERASE (0x7 << E82545_NVM_ADDR_BITS) /* erase */ 121 #define E82545_NVM_OPCODE_EWEN (0x4 << E82545_NVM_ADDR_BITS) /* wr-enable */ 122 123 #define E82545_NVM_EEPROM_SIZE 64 /* 64 * 16-bit values == 128K */ 124 125 #define E1000_ICR_SRPD 0x00010000 126 127 /* This is an arbitrary number. There is no hard limit on the chip. */ 128 #define I82545_MAX_TXSEGS 64 129 130 /* Legacy receive descriptor */ 131 struct e1000_rx_desc { 132 uint64_t buffer_addr; /* Address of the descriptor's data buffer */ 133 uint16_t length; /* Length of data DMAed into data buffer */ 134 uint16_t csum; /* Packet checksum */ 135 uint8_t status; /* Descriptor status */ 136 uint8_t errors; /* Descriptor Errors */ 137 uint16_t special; 138 }; 139 140 /* Transmit descriptor types */ 141 #define E1000_TXD_MASK (E1000_TXD_CMD_DEXT | 0x00F00000) 142 #define E1000_TXD_TYP_L (0) 143 #define E1000_TXD_TYP_C (E1000_TXD_CMD_DEXT | E1000_TXD_DTYP_C) 144 #define E1000_TXD_TYP_D (E1000_TXD_CMD_DEXT | E1000_TXD_DTYP_D) 145 146 /* Legacy transmit descriptor */ 147 struct e1000_tx_desc { 148 uint64_t buffer_addr; /* Address of the descriptor's data buffer */ 149 union { 150 uint32_t data; 151 struct { 152 uint16_t length; /* Data buffer length */ 153 uint8_t cso; /* Checksum offset */ 154 uint8_t cmd; /* Descriptor control */ 155 } flags; 156 } lower; 157 union { 158 uint32_t data; 159 struct { 160 uint8_t status; /* Descriptor status */ 161 uint8_t css; /* Checksum start */ 162 uint16_t special; 163 } fields; 164 } upper; 165 }; 166 167 /* Context descriptor */ 168 struct e1000_context_desc { 169 union { 170 uint32_t ip_config; 171 struct { 172 uint8_t ipcss; /* IP checksum start */ 173 uint8_t ipcso; /* IP checksum offset */ 174 uint16_t ipcse; /* IP checksum end */ 175 } ip_fields; 176 } lower_setup; 177 union { 178 uint32_t tcp_config; 179 struct { 180 uint8_t tucss; /* TCP checksum start */ 181 uint8_t tucso; /* TCP checksum offset */ 182 uint16_t tucse; /* TCP checksum end */ 183 } tcp_fields; 184 } upper_setup; 185 uint32_t cmd_and_length; 186 union { 187 uint32_t data; 188 struct { 189 uint8_t status; /* Descriptor status */ 190 uint8_t hdr_len; /* Header length */ 191 uint16_t mss; /* Maximum segment size */ 192 } fields; 193 } tcp_seg_setup; 194 }; 195 196 /* Data descriptor */ 197 struct e1000_data_desc { 198 uint64_t buffer_addr; /* Address of the descriptor's buffer address */ 199 union { 200 uint32_t data; 201 struct { 202 uint16_t length; /* Data buffer length */ 203 uint8_t typ_len_ext; 204 uint8_t cmd; 205 } flags; 206 } lower; 207 union { 208 uint32_t data; 209 struct { 210 uint8_t status; /* Descriptor status */ 211 uint8_t popts; /* Packet Options */ 212 uint16_t special; 213 } fields; 214 } upper; 215 }; 216 217 union e1000_tx_udesc { 218 struct e1000_tx_desc td; 219 struct e1000_context_desc cd; 220 struct e1000_data_desc dd; 221 }; 222 223 /* Tx checksum info for a packet. */ 224 struct ck_info { 225 int ck_valid; /* ck_info is valid */ 226 uint8_t ck_start; /* start byte of cksum calcuation */ 227 uint8_t ck_off; /* offset of cksum insertion */ 228 uint16_t ck_len; /* length of cksum calc: 0 is to packet-end */ 229 }; 230 231 /* 232 * Debug printf 233 */ 234 static int e82545_debug = 0; 235 #define WPRINTF(msg,params...) PRINTLN("e82545: " msg, params) 236 #define DPRINTF(msg,params...) if (e82545_debug) WPRINTF(msg, params) 237 238 #define MIN(a,b) (((a)<(b))?(a):(b)) 239 #define MAX(a,b) (((a)>(b))?(a):(b)) 240 241 /* s/w representation of the RAL/RAH regs */ 242 struct eth_uni { 243 int eu_valid; 244 int eu_addrsel; 245 struct ether_addr eu_eth; 246 }; 247 248 249 struct e82545_softc { 250 struct pci_devinst *esc_pi; 251 struct vmctx *esc_ctx; 252 struct mevent *esc_mevpitr; 253 pthread_mutex_t esc_mtx; 254 struct ether_addr esc_mac; 255 net_backend_t *esc_be; 256 257 /* General */ 258 uint32_t esc_CTRL; /* x0000 device ctl */ 259 uint32_t esc_FCAL; /* x0028 flow ctl addr lo */ 260 uint32_t esc_FCAH; /* x002C flow ctl addr hi */ 261 uint32_t esc_FCT; /* x0030 flow ctl type */ 262 uint32_t esc_VET; /* x0038 VLAN eth type */ 263 uint32_t esc_FCTTV; /* x0170 flow ctl tx timer */ 264 uint32_t esc_LEDCTL; /* x0E00 LED control */ 265 uint32_t esc_PBA; /* x1000 pkt buffer allocation */ 266 267 /* Interrupt control */ 268 int esc_irq_asserted; 269 uint32_t esc_ICR; /* x00C0 cause read/clear */ 270 uint32_t esc_ITR; /* x00C4 intr throttling */ 271 uint32_t esc_ICS; /* x00C8 cause set */ 272 uint32_t esc_IMS; /* x00D0 mask set/read */ 273 uint32_t esc_IMC; /* x00D8 mask clear */ 274 275 /* Transmit */ 276 union e1000_tx_udesc *esc_txdesc; 277 struct e1000_context_desc esc_txctx; 278 pthread_t esc_tx_tid; 279 pthread_cond_t esc_tx_cond; 280 int esc_tx_enabled; 281 int esc_tx_active; 282 uint32_t esc_TXCW; /* x0178 transmit config */ 283 uint32_t esc_TCTL; /* x0400 transmit ctl */ 284 uint32_t esc_TIPG; /* x0410 inter-packet gap */ 285 uint16_t esc_AIT; /* x0458 Adaptive Interframe Throttle */ 286 uint64_t esc_tdba; /* verified 64-bit desc table addr */ 287 uint32_t esc_TDBAL; /* x3800 desc table addr, low bits */ 288 uint32_t esc_TDBAH; /* x3804 desc table addr, hi 32-bits */ 289 uint32_t esc_TDLEN; /* x3808 # descriptors in bytes */ 290 uint16_t esc_TDH; /* x3810 desc table head idx */ 291 uint16_t esc_TDHr; /* internal read version of TDH */ 292 uint16_t esc_TDT; /* x3818 desc table tail idx */ 293 uint32_t esc_TIDV; /* x3820 intr delay */ 294 uint32_t esc_TXDCTL; /* x3828 desc control */ 295 uint32_t esc_TADV; /* x382C intr absolute delay */ 296 297 /* L2 frame acceptance */ 298 struct eth_uni esc_uni[16]; /* 16 x unicast MAC addresses */ 299 uint32_t esc_fmcast[128]; /* Multicast filter bit-match */ 300 uint32_t esc_fvlan[128]; /* VLAN 4096-bit filter */ 301 302 /* Receive */ 303 struct e1000_rx_desc *esc_rxdesc; 304 pthread_cond_t esc_rx_cond; 305 int esc_rx_enabled; 306 int esc_rx_active; 307 int esc_rx_loopback; 308 uint32_t esc_RCTL; /* x0100 receive ctl */ 309 uint32_t esc_FCRTL; /* x2160 flow cntl thresh, low */ 310 uint32_t esc_FCRTH; /* x2168 flow cntl thresh, hi */ 311 uint64_t esc_rdba; /* verified 64-bit desc table addr */ 312 uint32_t esc_RDBAL; /* x2800 desc table addr, low bits */ 313 uint32_t esc_RDBAH; /* x2804 desc table addr, hi 32-bits*/ 314 uint32_t esc_RDLEN; /* x2808 #descriptors */ 315 uint16_t esc_RDH; /* x2810 desc table head idx */ 316 uint16_t esc_RDT; /* x2818 desc table tail idx */ 317 uint32_t esc_RDTR; /* x2820 intr delay */ 318 uint32_t esc_RXDCTL; /* x2828 desc control */ 319 uint32_t esc_RADV; /* x282C intr absolute delay */ 320 uint32_t esc_RSRPD; /* x2C00 recv small packet detect */ 321 uint32_t esc_RXCSUM; /* x5000 receive cksum ctl */ 322 323 /* IO Port register access */ 324 uint32_t io_addr; 325 326 /* Shadow copy of MDIC */ 327 uint32_t mdi_control; 328 /* Shadow copy of EECD */ 329 uint32_t eeprom_control; 330 /* Latest NVM in/out */ 331 uint16_t nvm_data; 332 uint16_t nvm_opaddr; 333 /* stats */ 334 uint32_t missed_pkt_count; /* dropped for no room in rx queue */ 335 uint32_t pkt_rx_by_size[6]; 336 uint32_t pkt_tx_by_size[6]; 337 uint32_t good_pkt_rx_count; 338 uint32_t bcast_pkt_rx_count; 339 uint32_t mcast_pkt_rx_count; 340 uint32_t good_pkt_tx_count; 341 uint32_t bcast_pkt_tx_count; 342 uint32_t mcast_pkt_tx_count; 343 uint32_t oversize_rx_count; 344 uint32_t tso_tx_count; 345 uint64_t good_octets_rx; 346 uint64_t good_octets_tx; 347 uint64_t missed_octets; /* counts missed and oversized */ 348 349 uint8_t nvm_bits:6; /* number of bits remaining in/out */ 350 uint8_t nvm_mode:2; 351 #define E82545_NVM_MODE_OPADDR 0x0 352 #define E82545_NVM_MODE_DATAIN 0x1 353 #define E82545_NVM_MODE_DATAOUT 0x2 354 /* EEPROM data */ 355 uint16_t eeprom_data[E82545_NVM_EEPROM_SIZE]; 356 }; 357 358 static void e82545_reset(struct e82545_softc *sc, int dev); 359 static void e82545_rx_enable(struct e82545_softc *sc); 360 static void e82545_rx_disable(struct e82545_softc *sc); 361 static void e82545_rx_callback(int fd, enum ev_type type, void *param); 362 static void e82545_tx_start(struct e82545_softc *sc); 363 static void e82545_tx_enable(struct e82545_softc *sc); 364 static void e82545_tx_disable(struct e82545_softc *sc); 365 366 static inline int 367 e82545_size_stat_index(uint32_t size) 368 { 369 if (size <= 64) { 370 return 0; 371 } else if (size >= 1024) { 372 return 5; 373 } else { 374 /* should be 1-4 */ 375 return (ffs(size) - 6); 376 } 377 } 378 379 static void 380 e82545_init_eeprom(struct e82545_softc *sc) 381 { 382 uint16_t checksum, i; 383 384 /* mac addr */ 385 sc->eeprom_data[NVM_MAC_ADDR] = ((uint16_t)sc->esc_mac.octet[0]) | 386 (((uint16_t)sc->esc_mac.octet[1]) << 8); 387 sc->eeprom_data[NVM_MAC_ADDR+1] = ((uint16_t)sc->esc_mac.octet[2]) | 388 (((uint16_t)sc->esc_mac.octet[3]) << 8); 389 sc->eeprom_data[NVM_MAC_ADDR+2] = ((uint16_t)sc->esc_mac.octet[4]) | 390 (((uint16_t)sc->esc_mac.octet[5]) << 8); 391 392 /* pci ids */ 393 sc->eeprom_data[NVM_SUB_DEV_ID] = E82545_SUBDEV_ID; 394 sc->eeprom_data[NVM_SUB_VEN_ID] = E82545_VENDOR_ID_INTEL; 395 sc->eeprom_data[NVM_DEV_ID] = E82545_DEV_ID_82545EM_COPPER; 396 sc->eeprom_data[NVM_VEN_ID] = E82545_VENDOR_ID_INTEL; 397 398 /* fill in the checksum */ 399 checksum = 0; 400 for (i = 0; i < NVM_CHECKSUM_REG; i++) { 401 checksum += sc->eeprom_data[i]; 402 } 403 checksum = NVM_SUM - checksum; 404 sc->eeprom_data[NVM_CHECKSUM_REG] = checksum; 405 DPRINTF("eeprom checksum: 0x%x", checksum); 406 } 407 408 static void 409 e82545_write_mdi(struct e82545_softc *sc, uint8_t reg_addr, 410 uint8_t phy_addr, uint32_t data) 411 { 412 DPRINTF("Write mdi reg:0x%x phy:0x%x data: 0x%x", reg_addr, phy_addr, data); 413 } 414 415 static uint32_t 416 e82545_read_mdi(struct e82545_softc *sc, uint8_t reg_addr, 417 uint8_t phy_addr) 418 { 419 //DPRINTF("Read mdi reg:0x%x phy:0x%x", reg_addr, phy_addr); 420 switch (reg_addr) { 421 case PHY_STATUS: 422 return (MII_SR_LINK_STATUS | MII_SR_AUTONEG_CAPS | 423 MII_SR_AUTONEG_COMPLETE); 424 case PHY_AUTONEG_ADV: 425 return NWAY_AR_SELECTOR_FIELD; 426 case PHY_LP_ABILITY: 427 return 0; 428 case PHY_1000T_STATUS: 429 return (SR_1000T_LP_FD_CAPS | SR_1000T_REMOTE_RX_STATUS | 430 SR_1000T_LOCAL_RX_STATUS); 431 case PHY_ID1: 432 return (M88E1011_I_PHY_ID >> 16) & 0xFFFF; 433 case PHY_ID2: 434 return (M88E1011_I_PHY_ID | E82545_REVISION_4) & 0xFFFF; 435 default: 436 DPRINTF("Unknown mdi read reg:0x%x phy:0x%x", reg_addr, phy_addr); 437 return 0; 438 } 439 /* not reached */ 440 } 441 442 static void 443 e82545_eecd_strobe(struct e82545_softc *sc) 444 { 445 /* Microwire state machine */ 446 /* 447 DPRINTF("eeprom state machine srtobe " 448 "0x%x 0x%x 0x%x 0x%x", 449 sc->nvm_mode, sc->nvm_bits, 450 sc->nvm_opaddr, sc->nvm_data);*/ 451 452 if (sc->nvm_bits == 0) { 453 DPRINTF("eeprom state machine not expecting data! " 454 "0x%x 0x%x 0x%x 0x%x", 455 sc->nvm_mode, sc->nvm_bits, 456 sc->nvm_opaddr, sc->nvm_data); 457 return; 458 } 459 sc->nvm_bits--; 460 if (sc->nvm_mode == E82545_NVM_MODE_DATAOUT) { 461 /* shifting out */ 462 if (sc->nvm_data & 0x8000) { 463 sc->eeprom_control |= E1000_EECD_DO; 464 } else { 465 sc->eeprom_control &= ~E1000_EECD_DO; 466 } 467 sc->nvm_data <<= 1; 468 if (sc->nvm_bits == 0) { 469 /* read done, back to opcode mode. */ 470 sc->nvm_opaddr = 0; 471 sc->nvm_mode = E82545_NVM_MODE_OPADDR; 472 sc->nvm_bits = E82545_NVM_OPADDR_BITS; 473 } 474 } else if (sc->nvm_mode == E82545_NVM_MODE_DATAIN) { 475 /* shifting in */ 476 sc->nvm_data <<= 1; 477 if (sc->eeprom_control & E1000_EECD_DI) { 478 sc->nvm_data |= 1; 479 } 480 if (sc->nvm_bits == 0) { 481 /* eeprom write */ 482 uint16_t op = sc->nvm_opaddr & E82545_NVM_OPCODE_MASK; 483 uint16_t addr = sc->nvm_opaddr & E82545_NVM_ADDR_MASK; 484 if (op != E82545_NVM_OPCODE_WRITE) { 485 DPRINTF("Illegal eeprom write op 0x%x", 486 sc->nvm_opaddr); 487 } else if (addr >= E82545_NVM_EEPROM_SIZE) { 488 DPRINTF("Illegal eeprom write addr 0x%x", 489 sc->nvm_opaddr); 490 } else { 491 DPRINTF("eeprom write eeprom[0x%x] = 0x%x", 492 addr, sc->nvm_data); 493 sc->eeprom_data[addr] = sc->nvm_data; 494 } 495 /* back to opcode mode */ 496 sc->nvm_opaddr = 0; 497 sc->nvm_mode = E82545_NVM_MODE_OPADDR; 498 sc->nvm_bits = E82545_NVM_OPADDR_BITS; 499 } 500 } else if (sc->nvm_mode == E82545_NVM_MODE_OPADDR) { 501 sc->nvm_opaddr <<= 1; 502 if (sc->eeprom_control & E1000_EECD_DI) { 503 sc->nvm_opaddr |= 1; 504 } 505 if (sc->nvm_bits == 0) { 506 uint16_t op = sc->nvm_opaddr & E82545_NVM_OPCODE_MASK; 507 switch (op) { 508 case E82545_NVM_OPCODE_EWEN: 509 DPRINTF("eeprom write enable: 0x%x", 510 sc->nvm_opaddr); 511 /* back to opcode mode */ 512 sc->nvm_opaddr = 0; 513 sc->nvm_mode = E82545_NVM_MODE_OPADDR; 514 sc->nvm_bits = E82545_NVM_OPADDR_BITS; 515 break; 516 case E82545_NVM_OPCODE_READ: 517 { 518 uint16_t addr = sc->nvm_opaddr & 519 E82545_NVM_ADDR_MASK; 520 sc->nvm_mode = E82545_NVM_MODE_DATAOUT; 521 sc->nvm_bits = E82545_NVM_DATA_BITS; 522 if (addr < E82545_NVM_EEPROM_SIZE) { 523 sc->nvm_data = sc->eeprom_data[addr]; 524 DPRINTF("eeprom read: eeprom[0x%x] = 0x%x", 525 addr, sc->nvm_data); 526 } else { 527 DPRINTF("eeprom illegal read: 0x%x", 528 sc->nvm_opaddr); 529 sc->nvm_data = 0; 530 } 531 break; 532 } 533 case E82545_NVM_OPCODE_WRITE: 534 sc->nvm_mode = E82545_NVM_MODE_DATAIN; 535 sc->nvm_bits = E82545_NVM_DATA_BITS; 536 sc->nvm_data = 0; 537 break; 538 default: 539 DPRINTF("eeprom unknown op: 0x%x", 540 sc->nvm_opaddr); 541 /* back to opcode mode */ 542 sc->nvm_opaddr = 0; 543 sc->nvm_mode = E82545_NVM_MODE_OPADDR; 544 sc->nvm_bits = E82545_NVM_OPADDR_BITS; 545 } 546 } 547 } else { 548 DPRINTF("eeprom state machine wrong state! " 549 "0x%x 0x%x 0x%x 0x%x", 550 sc->nvm_mode, sc->nvm_bits, 551 sc->nvm_opaddr, sc->nvm_data); 552 } 553 } 554 555 static void 556 e82545_itr_callback(int fd, enum ev_type type, void *param) 557 { 558 uint32_t new; 559 struct e82545_softc *sc = param; 560 561 pthread_mutex_lock(&sc->esc_mtx); 562 new = sc->esc_ICR & sc->esc_IMS; 563 if (new && !sc->esc_irq_asserted) { 564 DPRINTF("itr callback: lintr assert %x", new); 565 sc->esc_irq_asserted = 1; 566 pci_lintr_assert(sc->esc_pi); 567 } else { 568 mevent_delete(sc->esc_mevpitr); 569 sc->esc_mevpitr = NULL; 570 } 571 pthread_mutex_unlock(&sc->esc_mtx); 572 } 573 574 static void 575 e82545_icr_assert(struct e82545_softc *sc, uint32_t bits) 576 { 577 uint32_t new; 578 579 DPRINTF("icr assert: 0x%x", bits); 580 581 /* 582 * An interrupt is only generated if bits are set that 583 * aren't already in the ICR, these bits are unmasked, 584 * and there isn't an interrupt already pending. 585 */ 586 new = bits & ~sc->esc_ICR & sc->esc_IMS; 587 sc->esc_ICR |= bits; 588 589 if (new == 0) { 590 DPRINTF("icr assert: masked %x, ims %x", new, sc->esc_IMS); 591 } else if (sc->esc_mevpitr != NULL) { 592 DPRINTF("icr assert: throttled %x, ims %x", new, sc->esc_IMS); 593 } else if (!sc->esc_irq_asserted) { 594 DPRINTF("icr assert: lintr assert %x", new); 595 sc->esc_irq_asserted = 1; 596 pci_lintr_assert(sc->esc_pi); 597 if (sc->esc_ITR != 0) { 598 sc->esc_mevpitr = mevent_add( 599 (sc->esc_ITR + 3905) / 3906, /* 256ns -> 1ms */ 600 EVF_TIMER, e82545_itr_callback, sc); 601 } 602 } 603 } 604 605 static void 606 e82545_ims_change(struct e82545_softc *sc, uint32_t bits) 607 { 608 uint32_t new; 609 610 /* 611 * Changing the mask may allow previously asserted 612 * but masked interrupt requests to generate an interrupt. 613 */ 614 new = bits & sc->esc_ICR & ~sc->esc_IMS; 615 sc->esc_IMS |= bits; 616 617 if (new == 0) { 618 DPRINTF("ims change: masked %x, ims %x", new, sc->esc_IMS); 619 } else if (sc->esc_mevpitr != NULL) { 620 DPRINTF("ims change: throttled %x, ims %x", new, sc->esc_IMS); 621 } else if (!sc->esc_irq_asserted) { 622 DPRINTF("ims change: lintr assert %x", new); 623 sc->esc_irq_asserted = 1; 624 pci_lintr_assert(sc->esc_pi); 625 if (sc->esc_ITR != 0) { 626 sc->esc_mevpitr = mevent_add( 627 (sc->esc_ITR + 3905) / 3906, /* 256ns -> 1ms */ 628 EVF_TIMER, e82545_itr_callback, sc); 629 } 630 } 631 } 632 633 static void 634 e82545_icr_deassert(struct e82545_softc *sc, uint32_t bits) 635 { 636 637 DPRINTF("icr deassert: 0x%x", bits); 638 sc->esc_ICR &= ~bits; 639 640 /* 641 * If there are no longer any interrupt sources and there 642 * was an asserted interrupt, clear it 643 */ 644 if (sc->esc_irq_asserted && !(sc->esc_ICR & sc->esc_IMS)) { 645 DPRINTF("icr deassert: lintr deassert %x", bits); 646 pci_lintr_deassert(sc->esc_pi); 647 sc->esc_irq_asserted = 0; 648 } 649 } 650 651 static void 652 e82545_intr_write(struct e82545_softc *sc, uint32_t offset, uint32_t value) 653 { 654 655 DPRINTF("intr_write: off %x, val %x", offset, value); 656 657 switch (offset) { 658 case E1000_ICR: 659 e82545_icr_deassert(sc, value); 660 break; 661 case E1000_ITR: 662 sc->esc_ITR = value; 663 break; 664 case E1000_ICS: 665 sc->esc_ICS = value; /* not used: store for debug */ 666 e82545_icr_assert(sc, value); 667 break; 668 case E1000_IMS: 669 e82545_ims_change(sc, value); 670 break; 671 case E1000_IMC: 672 sc->esc_IMC = value; /* for debug */ 673 sc->esc_IMS &= ~value; 674 // XXX clear interrupts if all ICR bits now masked 675 // and interrupt was pending ? 676 break; 677 default: 678 break; 679 } 680 } 681 682 static uint32_t 683 e82545_intr_read(struct e82545_softc *sc, uint32_t offset) 684 { 685 uint32_t retval; 686 687 retval = 0; 688 689 DPRINTF("intr_read: off %x", offset); 690 691 switch (offset) { 692 case E1000_ICR: 693 retval = sc->esc_ICR; 694 sc->esc_ICR = 0; 695 e82545_icr_deassert(sc, ~0); 696 break; 697 case E1000_ITR: 698 retval = sc->esc_ITR; 699 break; 700 case E1000_ICS: 701 /* write-only register */ 702 break; 703 case E1000_IMS: 704 retval = sc->esc_IMS; 705 break; 706 case E1000_IMC: 707 /* write-only register */ 708 break; 709 default: 710 break; 711 } 712 713 return (retval); 714 } 715 716 static void 717 e82545_devctl(struct e82545_softc *sc, uint32_t val) 718 { 719 720 sc->esc_CTRL = val & ~E1000_CTRL_RST; 721 722 if (val & E1000_CTRL_RST) { 723 DPRINTF("e1k: s/w reset, ctl %x", val); 724 e82545_reset(sc, 1); 725 } 726 /* XXX check for phy reset ? */ 727 } 728 729 static void 730 e82545_rx_update_rdba(struct e82545_softc *sc) 731 { 732 733 /* XXX verify desc base/len within phys mem range */ 734 sc->esc_rdba = (uint64_t)sc->esc_RDBAH << 32 | 735 sc->esc_RDBAL; 736 737 /* Cache host mapping of guest descriptor array */ 738 sc->esc_rxdesc = paddr_guest2host(sc->esc_ctx, 739 sc->esc_rdba, sc->esc_RDLEN); 740 } 741 742 static void 743 e82545_rx_ctl(struct e82545_softc *sc, uint32_t val) 744 { 745 int on; 746 747 on = ((val & E1000_RCTL_EN) == E1000_RCTL_EN); 748 749 /* Save RCTL after stripping reserved bits 31:27,24,21,14,11:10,0 */ 750 sc->esc_RCTL = val & ~0xF9204c01; 751 752 DPRINTF("rx_ctl - %s RCTL %x, val %x", 753 on ? "on" : "off", sc->esc_RCTL, val); 754 755 /* state change requested */ 756 if (on != sc->esc_rx_enabled) { 757 if (on) { 758 /* Catch disallowed/unimplemented settings */ 759 //assert(!(val & E1000_RCTL_LBM_TCVR)); 760 761 if (sc->esc_RCTL & E1000_RCTL_LBM_TCVR) { 762 sc->esc_rx_loopback = 1; 763 } else { 764 sc->esc_rx_loopback = 0; 765 } 766 767 e82545_rx_update_rdba(sc); 768 e82545_rx_enable(sc); 769 } else { 770 e82545_rx_disable(sc); 771 sc->esc_rx_loopback = 0; 772 sc->esc_rdba = 0; 773 sc->esc_rxdesc = NULL; 774 } 775 } 776 } 777 778 static void 779 e82545_tx_update_tdba(struct e82545_softc *sc) 780 { 781 782 /* XXX verify desc base/len within phys mem range */ 783 sc->esc_tdba = (uint64_t)sc->esc_TDBAH << 32 | sc->esc_TDBAL; 784 785 /* Cache host mapping of guest descriptor array */ 786 sc->esc_txdesc = paddr_guest2host(sc->esc_ctx, sc->esc_tdba, 787 sc->esc_TDLEN); 788 } 789 790 static void 791 e82545_tx_ctl(struct e82545_softc *sc, uint32_t val) 792 { 793 int on; 794 795 on = ((val & E1000_TCTL_EN) == E1000_TCTL_EN); 796 797 /* ignore TCTL_EN settings that don't change state */ 798 if (on == sc->esc_tx_enabled) 799 return; 800 801 if (on) { 802 e82545_tx_update_tdba(sc); 803 e82545_tx_enable(sc); 804 } else { 805 e82545_tx_disable(sc); 806 sc->esc_tdba = 0; 807 sc->esc_txdesc = NULL; 808 } 809 810 /* Save TCTL value after stripping reserved bits 31:25,23,2,0 */ 811 sc->esc_TCTL = val & ~0xFE800005; 812 } 813 814 int 815 e82545_bufsz(uint32_t rctl) 816 { 817 818 switch (rctl & (E1000_RCTL_BSEX | E1000_RCTL_SZ_256)) { 819 case (E1000_RCTL_SZ_2048): return (2048); 820 case (E1000_RCTL_SZ_1024): return (1024); 821 case (E1000_RCTL_SZ_512): return (512); 822 case (E1000_RCTL_SZ_256): return (256); 823 case (E1000_RCTL_BSEX|E1000_RCTL_SZ_16384): return (16384); 824 case (E1000_RCTL_BSEX|E1000_RCTL_SZ_8192): return (8192); 825 case (E1000_RCTL_BSEX|E1000_RCTL_SZ_4096): return (4096); 826 } 827 return (256); /* Forbidden value. */ 828 } 829 830 /* XXX one packet at a time until this is debugged */ 831 static void 832 e82545_rx_callback(int fd, enum ev_type type, void *param) 833 { 834 struct e82545_softc *sc = param; 835 struct e1000_rx_desc *rxd; 836 struct iovec vec[64]; 837 int left, len, lim, maxpktsz, maxpktdesc, bufsz, i, n, size; 838 uint32_t cause = 0; 839 uint16_t *tp, tag, head; 840 841 pthread_mutex_lock(&sc->esc_mtx); 842 DPRINTF("rx_run: head %x, tail %x", sc->esc_RDH, sc->esc_RDT); 843 844 if (!sc->esc_rx_enabled || sc->esc_rx_loopback) { 845 DPRINTF("rx disabled (!%d || %d) -- packet(s) dropped", 846 sc->esc_rx_enabled, sc->esc_rx_loopback); 847 while (netbe_rx_discard(sc->esc_be) > 0) { 848 } 849 goto done1; 850 } 851 bufsz = e82545_bufsz(sc->esc_RCTL); 852 maxpktsz = (sc->esc_RCTL & E1000_RCTL_LPE) ? 16384 : 1522; 853 maxpktdesc = (maxpktsz + bufsz - 1) / bufsz; 854 size = sc->esc_RDLEN / 16; 855 head = sc->esc_RDH; 856 left = (size + sc->esc_RDT - head) % size; 857 if (left < maxpktdesc) { 858 DPRINTF("rx overflow (%d < %d) -- packet(s) dropped", 859 left, maxpktdesc); 860 while (netbe_rx_discard(sc->esc_be) > 0) { 861 } 862 goto done1; 863 } 864 865 sc->esc_rx_active = 1; 866 pthread_mutex_unlock(&sc->esc_mtx); 867 868 for (lim = size / 4; lim > 0 && left >= maxpktdesc; lim -= n) { 869 870 /* Grab rx descriptor pointed to by the head pointer */ 871 for (i = 0; i < maxpktdesc; i++) { 872 rxd = &sc->esc_rxdesc[(head + i) % size]; 873 vec[i].iov_base = paddr_guest2host(sc->esc_ctx, 874 rxd->buffer_addr, bufsz); 875 vec[i].iov_len = bufsz; 876 } 877 len = netbe_recv(sc->esc_be, vec, maxpktdesc); 878 if (len <= 0) { 879 DPRINTF("netbe_recv() returned %d", len); 880 goto done; 881 } 882 883 /* 884 * Adjust the packet length based on whether the CRC needs 885 * to be stripped or if the packet is less than the minimum 886 * eth packet size. 887 */ 888 if (len < ETHER_MIN_LEN - ETHER_CRC_LEN) 889 len = ETHER_MIN_LEN - ETHER_CRC_LEN; 890 if (!(sc->esc_RCTL & E1000_RCTL_SECRC)) 891 len += ETHER_CRC_LEN; 892 n = (len + bufsz - 1) / bufsz; 893 894 DPRINTF("packet read %d bytes, %d segs, head %d", 895 len, n, head); 896 897 /* Apply VLAN filter. */ 898 tp = (uint16_t *)vec[0].iov_base + 6; 899 if ((sc->esc_RCTL & E1000_RCTL_VFE) && 900 (ntohs(tp[0]) == sc->esc_VET)) { 901 tag = ntohs(tp[1]) & 0x0fff; 902 if ((sc->esc_fvlan[tag >> 5] & 903 (1 << (tag & 0x1f))) != 0) { 904 DPRINTF("known VLAN %d", tag); 905 } else { 906 DPRINTF("unknown VLAN %d", tag); 907 n = 0; 908 continue; 909 } 910 } 911 912 /* Update all consumed descriptors. */ 913 for (i = 0; i < n - 1; i++) { 914 rxd = &sc->esc_rxdesc[(head + i) % size]; 915 rxd->length = bufsz; 916 rxd->csum = 0; 917 rxd->errors = 0; 918 rxd->special = 0; 919 rxd->status = E1000_RXD_STAT_DD; 920 } 921 rxd = &sc->esc_rxdesc[(head + i) % size]; 922 rxd->length = len % bufsz; 923 rxd->csum = 0; 924 rxd->errors = 0; 925 rxd->special = 0; 926 /* XXX signal no checksum for now */ 927 rxd->status = E1000_RXD_STAT_PIF | E1000_RXD_STAT_IXSM | 928 E1000_RXD_STAT_EOP | E1000_RXD_STAT_DD; 929 930 /* Schedule receive interrupts. */ 931 if (len <= sc->esc_RSRPD) { 932 cause |= E1000_ICR_SRPD | E1000_ICR_RXT0; 933 } else { 934 /* XXX: RDRT and RADV timers should be here. */ 935 cause |= E1000_ICR_RXT0; 936 } 937 938 head = (head + n) % size; 939 left -= n; 940 } 941 942 done: 943 pthread_mutex_lock(&sc->esc_mtx); 944 sc->esc_rx_active = 0; 945 if (sc->esc_rx_enabled == 0) 946 pthread_cond_signal(&sc->esc_rx_cond); 947 948 sc->esc_RDH = head; 949 /* Respect E1000_RCTL_RDMTS */ 950 left = (size + sc->esc_RDT - head) % size; 951 if (left < (size >> (((sc->esc_RCTL >> 8) & 3) + 1))) 952 cause |= E1000_ICR_RXDMT0; 953 /* Assert all accumulated interrupts. */ 954 if (cause != 0) 955 e82545_icr_assert(sc, cause); 956 done1: 957 DPRINTF("rx_run done: head %x, tail %x", sc->esc_RDH, sc->esc_RDT); 958 pthread_mutex_unlock(&sc->esc_mtx); 959 } 960 961 static uint16_t 962 e82545_carry(uint32_t sum) 963 { 964 965 sum = (sum & 0xFFFF) + (sum >> 16); 966 if (sum > 0xFFFF) 967 sum -= 0xFFFF; 968 return (sum); 969 } 970 971 static uint16_t 972 e82545_buf_checksum(uint8_t *buf, int len) 973 { 974 int i; 975 uint32_t sum = 0; 976 977 /* Checksum all the pairs of bytes first... */ 978 for (i = 0; i < (len & ~1U); i += 2) 979 sum += *((u_int16_t *)(buf + i)); 980 981 /* 982 * If there's a single byte left over, checksum it, too. 983 * Network byte order is big-endian, so the remaining byte is 984 * the high byte. 985 */ 986 if (i < len) 987 sum += htons(buf[i] << 8); 988 989 return (e82545_carry(sum)); 990 } 991 992 static uint16_t 993 e82545_iov_checksum(struct iovec *iov, int iovcnt, int off, int len) 994 { 995 int now, odd; 996 uint32_t sum = 0, s; 997 998 /* Skip completely unneeded vectors. */ 999 while (iovcnt > 0 && iov->iov_len <= off && off > 0) { 1000 off -= iov->iov_len; 1001 iov++; 1002 iovcnt--; 1003 } 1004 1005 /* Calculate checksum of requested range. */ 1006 odd = 0; 1007 while (len > 0 && iovcnt > 0) { 1008 now = MIN(len, iov->iov_len - off); 1009 #ifdef __FreeBSD__ 1010 s = e82545_buf_checksum(iov->iov_base + off, now); 1011 #else 1012 s = e82545_buf_checksum((uint8_t *)iov->iov_base + off, now); 1013 #endif 1014 sum += odd ? (s << 8) : s; 1015 odd ^= (now & 1); 1016 len -= now; 1017 off = 0; 1018 iov++; 1019 iovcnt--; 1020 } 1021 1022 return (e82545_carry(sum)); 1023 } 1024 1025 /* 1026 * Return the transmit descriptor type. 1027 */ 1028 int 1029 e82545_txdesc_type(uint32_t lower) 1030 { 1031 int type; 1032 1033 type = 0; 1034 1035 if (lower & E1000_TXD_CMD_DEXT) 1036 type = lower & E1000_TXD_MASK; 1037 1038 return (type); 1039 } 1040 1041 static void 1042 e82545_transmit_checksum(struct iovec *iov, int iovcnt, struct ck_info *ck) 1043 { 1044 uint16_t cksum; 1045 int cklen; 1046 1047 DPRINTF("tx cksum: iovcnt/s/off/len %d/%d/%d/%d", 1048 iovcnt, ck->ck_start, ck->ck_off, ck->ck_len); 1049 cklen = ck->ck_len ? ck->ck_len - ck->ck_start + 1 : INT_MAX; 1050 cksum = e82545_iov_checksum(iov, iovcnt, ck->ck_start, cklen); 1051 *(uint16_t *)((uint8_t *)iov[0].iov_base + ck->ck_off) = ~cksum; 1052 } 1053 1054 static void 1055 e82545_transmit_backend(struct e82545_softc *sc, struct iovec *iov, int iovcnt) 1056 { 1057 1058 if (sc->esc_be == NULL) 1059 return; 1060 1061 (void) netbe_send(sc->esc_be, iov, iovcnt); 1062 } 1063 1064 static void 1065 e82545_transmit_done(struct e82545_softc *sc, uint16_t head, uint16_t tail, 1066 uint16_t dsize, int *tdwb) 1067 { 1068 union e1000_tx_udesc *dsc; 1069 1070 for ( ; head != tail; head = (head + 1) % dsize) { 1071 dsc = &sc->esc_txdesc[head]; 1072 if (dsc->td.lower.data & E1000_TXD_CMD_RS) { 1073 dsc->td.upper.data |= E1000_TXD_STAT_DD; 1074 *tdwb = 1; 1075 } 1076 } 1077 } 1078 1079 static int 1080 e82545_transmit(struct e82545_softc *sc, uint16_t head, uint16_t tail, 1081 uint16_t dsize, uint16_t *rhead, int *tdwb) 1082 { 1083 uint8_t *hdr, *hdrp; 1084 struct iovec iovb[I82545_MAX_TXSEGS + 2]; 1085 struct iovec tiov[I82545_MAX_TXSEGS + 2]; 1086 struct e1000_context_desc *cd; 1087 struct ck_info ckinfo[2]; 1088 struct iovec *iov; 1089 union e1000_tx_udesc *dsc; 1090 int desc, dtype, len, ntype, iovcnt, tcp, tso; 1091 int mss, paylen, seg, tiovcnt, left, now, nleft, nnow, pv, pvoff; 1092 unsigned hdrlen, vlen; 1093 uint32_t tcpsum, tcpseq; 1094 uint16_t ipcs, tcpcs, ipid, ohead; 1095 1096 ckinfo[0].ck_valid = ckinfo[1].ck_valid = 0; 1097 iovcnt = 0; 1098 ntype = 0; 1099 tso = 0; 1100 ohead = head; 1101 1102 /* iovb[0/1] may be used for writable copy of headers. */ 1103 iov = &iovb[2]; 1104 1105 for (desc = 0; ; desc++, head = (head + 1) % dsize) { 1106 if (head == tail) { 1107 *rhead = head; 1108 return (0); 1109 } 1110 dsc = &sc->esc_txdesc[head]; 1111 dtype = e82545_txdesc_type(dsc->td.lower.data); 1112 1113 if (desc == 0) { 1114 switch (dtype) { 1115 case E1000_TXD_TYP_C: 1116 DPRINTF("tx ctxt desc idx %d: %016jx " 1117 "%08x%08x", 1118 head, dsc->td.buffer_addr, 1119 dsc->td.upper.data, dsc->td.lower.data); 1120 /* Save context and return */ 1121 sc->esc_txctx = dsc->cd; 1122 goto done; 1123 case E1000_TXD_TYP_L: 1124 DPRINTF("tx legacy desc idx %d: %08x%08x", 1125 head, dsc->td.upper.data, dsc->td.lower.data); 1126 /* 1127 * legacy cksum start valid in first descriptor 1128 */ 1129 ntype = dtype; 1130 ckinfo[0].ck_start = dsc->td.upper.fields.css; 1131 break; 1132 case E1000_TXD_TYP_D: 1133 DPRINTF("tx data desc idx %d: %08x%08x", 1134 head, dsc->td.upper.data, dsc->td.lower.data); 1135 ntype = dtype; 1136 break; 1137 default: 1138 break; 1139 } 1140 } else { 1141 /* Descriptor type must be consistent */ 1142 assert(dtype == ntype); 1143 DPRINTF("tx next desc idx %d: %08x%08x", 1144 head, dsc->td.upper.data, dsc->td.lower.data); 1145 } 1146 1147 len = (dtype == E1000_TXD_TYP_L) ? dsc->td.lower.flags.length : 1148 dsc->dd.lower.data & 0xFFFFF; 1149 1150 if (len > 0) { 1151 /* Strip checksum supplied by guest. */ 1152 if ((dsc->td.lower.data & E1000_TXD_CMD_EOP) != 0 && 1153 (dsc->td.lower.data & E1000_TXD_CMD_IFCS) == 0) 1154 len -= 2; 1155 if (iovcnt < I82545_MAX_TXSEGS) { 1156 iov[iovcnt].iov_base = paddr_guest2host( 1157 sc->esc_ctx, dsc->td.buffer_addr, len); 1158 iov[iovcnt].iov_len = len; 1159 } 1160 iovcnt++; 1161 } 1162 1163 /* 1164 * Pull out info that is valid in the final descriptor 1165 * and exit descriptor loop. 1166 */ 1167 if (dsc->td.lower.data & E1000_TXD_CMD_EOP) { 1168 if (dtype == E1000_TXD_TYP_L) { 1169 if (dsc->td.lower.data & E1000_TXD_CMD_IC) { 1170 ckinfo[0].ck_valid = 1; 1171 ckinfo[0].ck_off = 1172 dsc->td.lower.flags.cso; 1173 ckinfo[0].ck_len = 0; 1174 } 1175 } else { 1176 cd = &sc->esc_txctx; 1177 if (dsc->dd.lower.data & E1000_TXD_CMD_TSE) 1178 tso = 1; 1179 if (dsc->dd.upper.fields.popts & 1180 E1000_TXD_POPTS_IXSM) 1181 ckinfo[0].ck_valid = 1; 1182 if (dsc->dd.upper.fields.popts & 1183 E1000_TXD_POPTS_IXSM || tso) { 1184 ckinfo[0].ck_start = 1185 cd->lower_setup.ip_fields.ipcss; 1186 ckinfo[0].ck_off = 1187 cd->lower_setup.ip_fields.ipcso; 1188 ckinfo[0].ck_len = 1189 cd->lower_setup.ip_fields.ipcse; 1190 } 1191 if (dsc->dd.upper.fields.popts & 1192 E1000_TXD_POPTS_TXSM) 1193 ckinfo[1].ck_valid = 1; 1194 if (dsc->dd.upper.fields.popts & 1195 E1000_TXD_POPTS_TXSM || tso) { 1196 ckinfo[1].ck_start = 1197 cd->upper_setup.tcp_fields.tucss; 1198 ckinfo[1].ck_off = 1199 cd->upper_setup.tcp_fields.tucso; 1200 ckinfo[1].ck_len = 1201 cd->upper_setup.tcp_fields.tucse; 1202 } 1203 } 1204 break; 1205 } 1206 } 1207 1208 if (iovcnt > I82545_MAX_TXSEGS) { 1209 WPRINTF("tx too many descriptors (%d > %d) -- dropped", 1210 iovcnt, I82545_MAX_TXSEGS); 1211 goto done; 1212 } 1213 1214 hdrlen = vlen = 0; 1215 /* Estimate writable space for VLAN header insertion. */ 1216 if ((sc->esc_CTRL & E1000_CTRL_VME) && 1217 (dsc->td.lower.data & E1000_TXD_CMD_VLE)) { 1218 hdrlen = ETHER_ADDR_LEN*2; 1219 vlen = ETHER_VLAN_ENCAP_LEN; 1220 } 1221 if (!tso) { 1222 /* Estimate required writable space for checksums. */ 1223 if (ckinfo[0].ck_valid) 1224 hdrlen = MAX(hdrlen, ckinfo[0].ck_off + 2); 1225 if (ckinfo[1].ck_valid) 1226 hdrlen = MAX(hdrlen, ckinfo[1].ck_off + 2); 1227 /* Round up writable space to the first vector. */ 1228 if (hdrlen != 0 && iov[0].iov_len > hdrlen && 1229 iov[0].iov_len < hdrlen + 100) 1230 hdrlen = iov[0].iov_len; 1231 } else { 1232 /* In case of TSO header length provided by software. */ 1233 hdrlen = sc->esc_txctx.tcp_seg_setup.fields.hdr_len; 1234 1235 /* 1236 * Cap the header length at 240 based on 7.2.4.5 of 1237 * the Intel 82576EB (Rev 2.63) datasheet. 1238 */ 1239 if (hdrlen > 240) { 1240 WPRINTF("TSO hdrlen too large: %d", hdrlen); 1241 goto done; 1242 } 1243 1244 /* 1245 * If VLAN insertion is requested, ensure the header 1246 * at least holds the amount of data copied during 1247 * VLAN insertion below. 1248 * 1249 * XXX: Realistic packets will include a full Ethernet 1250 * header before the IP header at ckinfo[0].ck_start, 1251 * but this check is sufficient to prevent 1252 * out-of-bounds access below. 1253 */ 1254 if (vlen != 0 && hdrlen < ETHER_ADDR_LEN*2) { 1255 WPRINTF("TSO hdrlen too small for vlan insertion " 1256 "(%d vs %d) -- dropped", hdrlen, 1257 ETHER_ADDR_LEN*2); 1258 goto done; 1259 } 1260 1261 /* 1262 * Ensure that the header length covers the used fields 1263 * in the IP and TCP headers as well as the IP and TCP 1264 * checksums. The following fields are accessed below: 1265 * 1266 * Header | Field | Offset | Length 1267 * -------+-------+--------+------- 1268 * IPv4 | len | 2 | 2 1269 * IPv4 | ID | 4 | 2 1270 * IPv6 | len | 4 | 2 1271 * TCP | seq # | 4 | 4 1272 * TCP | flags | 13 | 1 1273 * UDP | len | 4 | 4 1274 */ 1275 if (hdrlen < ckinfo[0].ck_start + 6 || 1276 hdrlen < ckinfo[0].ck_off + 2) { 1277 WPRINTF("TSO hdrlen too small for IP fields (%d) " 1278 "-- dropped", hdrlen); 1279 goto done; 1280 } 1281 if (sc->esc_txctx.cmd_and_length & E1000_TXD_CMD_TCP) { 1282 if (hdrlen < ckinfo[1].ck_start + 14) { 1283 WPRINTF("TSO hdrlen too small for TCP fields " 1284 "(%d) -- dropped", hdrlen); 1285 goto done; 1286 } 1287 } else { 1288 if (hdrlen < ckinfo[1].ck_start + 8) { 1289 WPRINTF("TSO hdrlen too small for UDP fields " 1290 "(%d) -- dropped", hdrlen); 1291 goto done; 1292 } 1293 } 1294 if (ckinfo[1].ck_valid && hdrlen < ckinfo[1].ck_off + 2) { 1295 WPRINTF("TSO hdrlen too small for TCP/UDP fields " 1296 "(%d) -- dropped", hdrlen); 1297 goto done; 1298 } 1299 } 1300 1301 /* Allocate, fill and prepend writable header vector. */ 1302 if (hdrlen != 0) { 1303 hdr = __builtin_alloca(hdrlen + vlen); 1304 hdr += vlen; 1305 for (left = hdrlen, hdrp = hdr; left > 0; 1306 left -= now, hdrp += now) { 1307 now = MIN(left, iov->iov_len); 1308 memcpy(hdrp, iov->iov_base, now); 1309 iov->iov_base += now; 1310 iov->iov_len -= now; 1311 if (iov->iov_len == 0) { 1312 iov++; 1313 iovcnt--; 1314 } 1315 } 1316 iov--; 1317 iovcnt++; 1318 #ifdef __FreeBSD__ 1319 iov->iov_base = hdr; 1320 #else 1321 iov->iov_base = (caddr_t)hdr; 1322 #endif 1323 iov->iov_len = hdrlen; 1324 } else 1325 hdr = NULL; 1326 1327 /* Insert VLAN tag. */ 1328 if (vlen != 0) { 1329 hdr -= ETHER_VLAN_ENCAP_LEN; 1330 memmove(hdr, hdr + ETHER_VLAN_ENCAP_LEN, ETHER_ADDR_LEN*2); 1331 hdrlen += ETHER_VLAN_ENCAP_LEN; 1332 hdr[ETHER_ADDR_LEN*2 + 0] = sc->esc_VET >> 8; 1333 hdr[ETHER_ADDR_LEN*2 + 1] = sc->esc_VET & 0xff; 1334 hdr[ETHER_ADDR_LEN*2 + 2] = dsc->td.upper.fields.special >> 8; 1335 hdr[ETHER_ADDR_LEN*2 + 3] = dsc->td.upper.fields.special & 0xff; 1336 #ifdef __FreeBSD__ 1337 iov->iov_base = hdr; 1338 #else 1339 iov->iov_base = (caddr_t)hdr; 1340 #endif 1341 iov->iov_len += ETHER_VLAN_ENCAP_LEN; 1342 /* Correct checksum offsets after VLAN tag insertion. */ 1343 ckinfo[0].ck_start += ETHER_VLAN_ENCAP_LEN; 1344 ckinfo[0].ck_off += ETHER_VLAN_ENCAP_LEN; 1345 if (ckinfo[0].ck_len != 0) 1346 ckinfo[0].ck_len += ETHER_VLAN_ENCAP_LEN; 1347 ckinfo[1].ck_start += ETHER_VLAN_ENCAP_LEN; 1348 ckinfo[1].ck_off += ETHER_VLAN_ENCAP_LEN; 1349 if (ckinfo[1].ck_len != 0) 1350 ckinfo[1].ck_len += ETHER_VLAN_ENCAP_LEN; 1351 } 1352 1353 /* Simple non-TSO case. */ 1354 if (!tso) { 1355 /* Calculate checksums and transmit. */ 1356 if (ckinfo[0].ck_valid) 1357 e82545_transmit_checksum(iov, iovcnt, &ckinfo[0]); 1358 if (ckinfo[1].ck_valid) 1359 e82545_transmit_checksum(iov, iovcnt, &ckinfo[1]); 1360 e82545_transmit_backend(sc, iov, iovcnt); 1361 goto done; 1362 } 1363 1364 /* Doing TSO. */ 1365 tcp = (sc->esc_txctx.cmd_and_length & E1000_TXD_CMD_TCP) != 0; 1366 mss = sc->esc_txctx.tcp_seg_setup.fields.mss; 1367 paylen = (sc->esc_txctx.cmd_and_length & 0x000fffff); 1368 DPRINTF("tx %s segmentation offload %d+%d/%d bytes %d iovs", 1369 tcp ? "TCP" : "UDP", hdrlen, paylen, mss, iovcnt); 1370 ipid = ntohs(*(uint16_t *)&hdr[ckinfo[0].ck_start + 4]); 1371 tcpseq = 0; 1372 if (tcp) 1373 tcpseq = ntohl(*(uint32_t *)&hdr[ckinfo[1].ck_start + 4]); 1374 ipcs = *(uint16_t *)&hdr[ckinfo[0].ck_off]; 1375 tcpcs = 0; 1376 if (ckinfo[1].ck_valid) /* Save partial pseudo-header checksum. */ 1377 tcpcs = *(uint16_t *)&hdr[ckinfo[1].ck_off]; 1378 pv = 1; 1379 pvoff = 0; 1380 for (seg = 0, left = paylen; left > 0; seg++, left -= now) { 1381 now = MIN(left, mss); 1382 1383 /* Construct IOVs for the segment. */ 1384 /* Include whole original header. */ 1385 #ifdef __FreeBSD__ 1386 tiov[0].iov_base = hdr; 1387 #else 1388 tiov[0].iov_base = (caddr_t)hdr; 1389 #endif 1390 tiov[0].iov_len = hdrlen; 1391 tiovcnt = 1; 1392 /* Include respective part of payload IOV. */ 1393 for (nleft = now; pv < iovcnt && nleft > 0; nleft -= nnow) { 1394 nnow = MIN(nleft, iov[pv].iov_len - pvoff); 1395 tiov[tiovcnt].iov_base = iov[pv].iov_base + pvoff; 1396 tiov[tiovcnt++].iov_len = nnow; 1397 if (pvoff + nnow == iov[pv].iov_len) { 1398 pv++; 1399 pvoff = 0; 1400 } else 1401 pvoff += nnow; 1402 } 1403 DPRINTF("tx segment %d %d+%d bytes %d iovs", 1404 seg, hdrlen, now, tiovcnt); 1405 1406 /* Update IP header. */ 1407 if (sc->esc_txctx.cmd_and_length & E1000_TXD_CMD_IP) { 1408 /* IPv4 -- set length and ID */ 1409 *(uint16_t *)&hdr[ckinfo[0].ck_start + 2] = 1410 htons(hdrlen - ckinfo[0].ck_start + now); 1411 *(uint16_t *)&hdr[ckinfo[0].ck_start + 4] = 1412 htons(ipid + seg); 1413 } else { 1414 /* IPv6 -- set length */ 1415 *(uint16_t *)&hdr[ckinfo[0].ck_start + 4] = 1416 htons(hdrlen - ckinfo[0].ck_start - 40 + 1417 now); 1418 } 1419 1420 /* Update pseudo-header checksum. */ 1421 tcpsum = tcpcs; 1422 tcpsum += htons(hdrlen - ckinfo[1].ck_start + now); 1423 1424 /* Update TCP/UDP headers. */ 1425 if (tcp) { 1426 /* Update sequence number and FIN/PUSH flags. */ 1427 *(uint32_t *)&hdr[ckinfo[1].ck_start + 4] = 1428 htonl(tcpseq + paylen - left); 1429 if (now < left) { 1430 hdr[ckinfo[1].ck_start + 13] &= 1431 ~(TH_FIN | TH_PUSH); 1432 } 1433 } else { 1434 /* Update payload length. */ 1435 *(uint32_t *)&hdr[ckinfo[1].ck_start + 4] = 1436 hdrlen - ckinfo[1].ck_start + now; 1437 } 1438 1439 /* Calculate checksums and transmit. */ 1440 if (ckinfo[0].ck_valid) { 1441 *(uint16_t *)&hdr[ckinfo[0].ck_off] = ipcs; 1442 e82545_transmit_checksum(tiov, tiovcnt, &ckinfo[0]); 1443 } 1444 if (ckinfo[1].ck_valid) { 1445 *(uint16_t *)&hdr[ckinfo[1].ck_off] = 1446 e82545_carry(tcpsum); 1447 e82545_transmit_checksum(tiov, tiovcnt, &ckinfo[1]); 1448 } 1449 e82545_transmit_backend(sc, tiov, tiovcnt); 1450 } 1451 1452 done: 1453 head = (head + 1) % dsize; 1454 e82545_transmit_done(sc, ohead, head, dsize, tdwb); 1455 1456 *rhead = head; 1457 return (desc + 1); 1458 } 1459 1460 static void 1461 e82545_tx_run(struct e82545_softc *sc) 1462 { 1463 uint32_t cause; 1464 uint16_t head, rhead, tail, size; 1465 int lim, tdwb, sent; 1466 1467 head = sc->esc_TDH; 1468 tail = sc->esc_TDT; 1469 size = sc->esc_TDLEN / 16; 1470 DPRINTF("tx_run: head %x, rhead %x, tail %x", 1471 sc->esc_TDH, sc->esc_TDHr, sc->esc_TDT); 1472 1473 pthread_mutex_unlock(&sc->esc_mtx); 1474 rhead = head; 1475 tdwb = 0; 1476 for (lim = size / 4; sc->esc_tx_enabled && lim > 0; lim -= sent) { 1477 sent = e82545_transmit(sc, head, tail, size, &rhead, &tdwb); 1478 if (sent == 0) 1479 break; 1480 head = rhead; 1481 } 1482 pthread_mutex_lock(&sc->esc_mtx); 1483 1484 sc->esc_TDH = head; 1485 sc->esc_TDHr = rhead; 1486 cause = 0; 1487 if (tdwb) 1488 cause |= E1000_ICR_TXDW; 1489 if (lim != size / 4 && sc->esc_TDH == sc->esc_TDT) 1490 cause |= E1000_ICR_TXQE; 1491 if (cause) 1492 e82545_icr_assert(sc, cause); 1493 1494 DPRINTF("tx_run done: head %x, rhead %x, tail %x", 1495 sc->esc_TDH, sc->esc_TDHr, sc->esc_TDT); 1496 } 1497 1498 static _Noreturn void * 1499 e82545_tx_thread(void *param) 1500 { 1501 struct e82545_softc *sc = param; 1502 1503 pthread_mutex_lock(&sc->esc_mtx); 1504 for (;;) { 1505 while (!sc->esc_tx_enabled || sc->esc_TDHr == sc->esc_TDT) { 1506 if (sc->esc_tx_enabled && sc->esc_TDHr != sc->esc_TDT) 1507 break; 1508 sc->esc_tx_active = 0; 1509 if (sc->esc_tx_enabled == 0) 1510 pthread_cond_signal(&sc->esc_tx_cond); 1511 pthread_cond_wait(&sc->esc_tx_cond, &sc->esc_mtx); 1512 } 1513 sc->esc_tx_active = 1; 1514 1515 /* Process some tx descriptors. Lock dropped inside. */ 1516 e82545_tx_run(sc); 1517 } 1518 } 1519 1520 static void 1521 e82545_tx_start(struct e82545_softc *sc) 1522 { 1523 1524 if (sc->esc_tx_active == 0) 1525 pthread_cond_signal(&sc->esc_tx_cond); 1526 } 1527 1528 static void 1529 e82545_tx_enable(struct e82545_softc *sc) 1530 { 1531 1532 sc->esc_tx_enabled = 1; 1533 } 1534 1535 static void 1536 e82545_tx_disable(struct e82545_softc *sc) 1537 { 1538 1539 sc->esc_tx_enabled = 0; 1540 while (sc->esc_tx_active) 1541 pthread_cond_wait(&sc->esc_tx_cond, &sc->esc_mtx); 1542 } 1543 1544 static void 1545 e82545_rx_enable(struct e82545_softc *sc) 1546 { 1547 1548 sc->esc_rx_enabled = 1; 1549 } 1550 1551 static void 1552 e82545_rx_disable(struct e82545_softc *sc) 1553 { 1554 1555 sc->esc_rx_enabled = 0; 1556 while (sc->esc_rx_active) 1557 pthread_cond_wait(&sc->esc_rx_cond, &sc->esc_mtx); 1558 } 1559 1560 static void 1561 e82545_write_ra(struct e82545_softc *sc, int reg, uint32_t wval) 1562 { 1563 struct eth_uni *eu; 1564 int idx; 1565 1566 idx = reg >> 1; 1567 assert(idx < 15); 1568 1569 eu = &sc->esc_uni[idx]; 1570 1571 if (reg & 0x1) { 1572 /* RAH */ 1573 eu->eu_valid = ((wval & E1000_RAH_AV) == E1000_RAH_AV); 1574 eu->eu_addrsel = (wval >> 16) & 0x3; 1575 eu->eu_eth.octet[5] = wval >> 8; 1576 eu->eu_eth.octet[4] = wval; 1577 } else { 1578 /* RAL */ 1579 eu->eu_eth.octet[3] = wval >> 24; 1580 eu->eu_eth.octet[2] = wval >> 16; 1581 eu->eu_eth.octet[1] = wval >> 8; 1582 eu->eu_eth.octet[0] = wval; 1583 } 1584 } 1585 1586 static uint32_t 1587 e82545_read_ra(struct e82545_softc *sc, int reg) 1588 { 1589 struct eth_uni *eu; 1590 uint32_t retval; 1591 int idx; 1592 1593 idx = reg >> 1; 1594 assert(idx < 15); 1595 1596 eu = &sc->esc_uni[idx]; 1597 1598 if (reg & 0x1) { 1599 /* RAH */ 1600 retval = (eu->eu_valid << 31) | 1601 (eu->eu_addrsel << 16) | 1602 (eu->eu_eth.octet[5] << 8) | 1603 eu->eu_eth.octet[4]; 1604 } else { 1605 /* RAL */ 1606 retval = (eu->eu_eth.octet[3] << 24) | 1607 (eu->eu_eth.octet[2] << 16) | 1608 (eu->eu_eth.octet[1] << 8) | 1609 eu->eu_eth.octet[0]; 1610 } 1611 1612 return (retval); 1613 } 1614 1615 static void 1616 e82545_write_register(struct e82545_softc *sc, uint32_t offset, uint32_t value) 1617 { 1618 int ridx; 1619 1620 if (offset & 0x3) { 1621 DPRINTF("Unaligned register write offset:0x%x value:0x%x", offset, value); 1622 return; 1623 } 1624 DPRINTF("Register write: 0x%x value: 0x%x", offset, value); 1625 1626 switch (offset) { 1627 case E1000_CTRL: 1628 case E1000_CTRL_DUP: 1629 e82545_devctl(sc, value); 1630 break; 1631 case E1000_FCAL: 1632 sc->esc_FCAL = value; 1633 break; 1634 case E1000_FCAH: 1635 sc->esc_FCAH = value & ~0xFFFF0000; 1636 break; 1637 case E1000_FCT: 1638 sc->esc_FCT = value & ~0xFFFF0000; 1639 break; 1640 case E1000_VET: 1641 sc->esc_VET = value & ~0xFFFF0000; 1642 break; 1643 case E1000_FCTTV: 1644 sc->esc_FCTTV = value & ~0xFFFF0000; 1645 break; 1646 case E1000_LEDCTL: 1647 sc->esc_LEDCTL = value & ~0x30303000; 1648 break; 1649 case E1000_PBA: 1650 sc->esc_PBA = value & 0x0000FF80; 1651 break; 1652 case E1000_ICR: 1653 case E1000_ITR: 1654 case E1000_ICS: 1655 case E1000_IMS: 1656 case E1000_IMC: 1657 e82545_intr_write(sc, offset, value); 1658 break; 1659 case E1000_RCTL: 1660 e82545_rx_ctl(sc, value); 1661 break; 1662 case E1000_FCRTL: 1663 sc->esc_FCRTL = value & ~0xFFFF0007; 1664 break; 1665 case E1000_FCRTH: 1666 sc->esc_FCRTH = value & ~0xFFFF0007; 1667 break; 1668 case E1000_RDBAL(0): 1669 sc->esc_RDBAL = value & ~0xF; 1670 if (sc->esc_rx_enabled) { 1671 /* Apparently legal: update cached address */ 1672 e82545_rx_update_rdba(sc); 1673 } 1674 break; 1675 case E1000_RDBAH(0): 1676 assert(!sc->esc_rx_enabled); 1677 sc->esc_RDBAH = value; 1678 break; 1679 case E1000_RDLEN(0): 1680 assert(!sc->esc_rx_enabled); 1681 sc->esc_RDLEN = value & ~0xFFF0007F; 1682 break; 1683 case E1000_RDH(0): 1684 /* XXX should only ever be zero ? Range check ? */ 1685 sc->esc_RDH = value; 1686 break; 1687 case E1000_RDT(0): 1688 /* XXX if this opens up the rx ring, do something ? */ 1689 sc->esc_RDT = value; 1690 break; 1691 case E1000_RDTR: 1692 /* ignore FPD bit 31 */ 1693 sc->esc_RDTR = value & ~0xFFFF0000; 1694 break; 1695 case E1000_RXDCTL(0): 1696 sc->esc_RXDCTL = value & ~0xFEC0C0C0; 1697 break; 1698 case E1000_RADV: 1699 sc->esc_RADV = value & ~0xFFFF0000; 1700 break; 1701 case E1000_RSRPD: 1702 sc->esc_RSRPD = value & ~0xFFFFF000; 1703 break; 1704 case E1000_RXCSUM: 1705 sc->esc_RXCSUM = value & ~0xFFFFF800; 1706 break; 1707 case E1000_TXCW: 1708 sc->esc_TXCW = value & ~0x3FFF0000; 1709 break; 1710 case E1000_TCTL: 1711 e82545_tx_ctl(sc, value); 1712 break; 1713 case E1000_TIPG: 1714 sc->esc_TIPG = value; 1715 break; 1716 case E1000_AIT: 1717 sc->esc_AIT = value; 1718 break; 1719 case E1000_TDBAL(0): 1720 sc->esc_TDBAL = value & ~0xF; 1721 if (sc->esc_tx_enabled) 1722 e82545_tx_update_tdba(sc); 1723 break; 1724 case E1000_TDBAH(0): 1725 sc->esc_TDBAH = value; 1726 if (sc->esc_tx_enabled) 1727 e82545_tx_update_tdba(sc); 1728 break; 1729 case E1000_TDLEN(0): 1730 sc->esc_TDLEN = value & ~0xFFF0007F; 1731 if (sc->esc_tx_enabled) 1732 e82545_tx_update_tdba(sc); 1733 break; 1734 case E1000_TDH(0): 1735 //assert(!sc->esc_tx_enabled); 1736 /* XXX should only ever be zero ? Range check ? */ 1737 sc->esc_TDHr = sc->esc_TDH = value; 1738 break; 1739 case E1000_TDT(0): 1740 /* XXX range check ? */ 1741 sc->esc_TDT = value; 1742 if (sc->esc_tx_enabled) 1743 e82545_tx_start(sc); 1744 break; 1745 case E1000_TIDV: 1746 sc->esc_TIDV = value & ~0xFFFF0000; 1747 break; 1748 case E1000_TXDCTL(0): 1749 //assert(!sc->esc_tx_enabled); 1750 sc->esc_TXDCTL = value & ~0xC0C0C0; 1751 break; 1752 case E1000_TADV: 1753 sc->esc_TADV = value & ~0xFFFF0000; 1754 break; 1755 case E1000_RAL(0) ... E1000_RAH(15): 1756 /* convert to u32 offset */ 1757 ridx = (offset - E1000_RAL(0)) >> 2; 1758 e82545_write_ra(sc, ridx, value); 1759 break; 1760 case E1000_MTA ... (E1000_MTA + (127*4)): 1761 sc->esc_fmcast[(offset - E1000_MTA) >> 2] = value; 1762 break; 1763 case E1000_VFTA ... (E1000_VFTA + (127*4)): 1764 sc->esc_fvlan[(offset - E1000_VFTA) >> 2] = value; 1765 break; 1766 case E1000_EECD: 1767 { 1768 //DPRINTF("EECD write 0x%x -> 0x%x", sc->eeprom_control, value); 1769 /* edge triggered low->high */ 1770 uint32_t eecd_strobe = ((sc->eeprom_control & E1000_EECD_SK) ? 1771 0 : (value & E1000_EECD_SK)); 1772 uint32_t eecd_mask = (E1000_EECD_SK|E1000_EECD_CS| 1773 E1000_EECD_DI|E1000_EECD_REQ); 1774 sc->eeprom_control &= ~eecd_mask; 1775 sc->eeprom_control |= (value & eecd_mask); 1776 /* grant/revoke immediately */ 1777 if (value & E1000_EECD_REQ) { 1778 sc->eeprom_control |= E1000_EECD_GNT; 1779 } else { 1780 sc->eeprom_control &= ~E1000_EECD_GNT; 1781 } 1782 if (eecd_strobe && (sc->eeprom_control & E1000_EECD_CS)) { 1783 e82545_eecd_strobe(sc); 1784 } 1785 return; 1786 } 1787 case E1000_MDIC: 1788 { 1789 uint8_t reg_addr = (uint8_t)((value & E1000_MDIC_REG_MASK) >> 1790 E1000_MDIC_REG_SHIFT); 1791 uint8_t phy_addr = (uint8_t)((value & E1000_MDIC_PHY_MASK) >> 1792 E1000_MDIC_PHY_SHIFT); 1793 sc->mdi_control = 1794 (value & ~(E1000_MDIC_ERROR|E1000_MDIC_DEST)); 1795 if ((value & E1000_MDIC_READY) != 0) { 1796 DPRINTF("Incorrect MDIC ready bit: 0x%x", value); 1797 return; 1798 } 1799 switch (value & E82545_MDIC_OP_MASK) { 1800 case E1000_MDIC_OP_READ: 1801 sc->mdi_control &= ~E82545_MDIC_DATA_MASK; 1802 sc->mdi_control |= e82545_read_mdi(sc, reg_addr, phy_addr); 1803 break; 1804 case E1000_MDIC_OP_WRITE: 1805 e82545_write_mdi(sc, reg_addr, phy_addr, 1806 value & E82545_MDIC_DATA_MASK); 1807 break; 1808 default: 1809 DPRINTF("Unknown MDIC op: 0x%x", value); 1810 return; 1811 } 1812 /* TODO: barrier? */ 1813 sc->mdi_control |= E1000_MDIC_READY; 1814 if (value & E82545_MDIC_IE) { 1815 // TODO: generate interrupt 1816 } 1817 return; 1818 } 1819 case E1000_MANC: 1820 case E1000_STATUS: 1821 return; 1822 default: 1823 DPRINTF("Unknown write register: 0x%x value:%x", offset, value); 1824 return; 1825 } 1826 } 1827 1828 static uint32_t 1829 e82545_read_register(struct e82545_softc *sc, uint32_t offset) 1830 { 1831 uint32_t retval; 1832 int ridx; 1833 1834 if (offset & 0x3) { 1835 DPRINTF("Unaligned register read offset:0x%x", offset); 1836 return 0; 1837 } 1838 1839 DPRINTF("Register read: 0x%x", offset); 1840 1841 switch (offset) { 1842 case E1000_CTRL: 1843 retval = sc->esc_CTRL; 1844 break; 1845 case E1000_STATUS: 1846 retval = E1000_STATUS_FD | E1000_STATUS_LU | 1847 E1000_STATUS_SPEED_1000; 1848 break; 1849 case E1000_FCAL: 1850 retval = sc->esc_FCAL; 1851 break; 1852 case E1000_FCAH: 1853 retval = sc->esc_FCAH; 1854 break; 1855 case E1000_FCT: 1856 retval = sc->esc_FCT; 1857 break; 1858 case E1000_VET: 1859 retval = sc->esc_VET; 1860 break; 1861 case E1000_FCTTV: 1862 retval = sc->esc_FCTTV; 1863 break; 1864 case E1000_LEDCTL: 1865 retval = sc->esc_LEDCTL; 1866 break; 1867 case E1000_PBA: 1868 retval = sc->esc_PBA; 1869 break; 1870 case E1000_ICR: 1871 case E1000_ITR: 1872 case E1000_ICS: 1873 case E1000_IMS: 1874 case E1000_IMC: 1875 retval = e82545_intr_read(sc, offset); 1876 break; 1877 case E1000_RCTL: 1878 retval = sc->esc_RCTL; 1879 break; 1880 case E1000_FCRTL: 1881 retval = sc->esc_FCRTL; 1882 break; 1883 case E1000_FCRTH: 1884 retval = sc->esc_FCRTH; 1885 break; 1886 case E1000_RDBAL(0): 1887 retval = sc->esc_RDBAL; 1888 break; 1889 case E1000_RDBAH(0): 1890 retval = sc->esc_RDBAH; 1891 break; 1892 case E1000_RDLEN(0): 1893 retval = sc->esc_RDLEN; 1894 break; 1895 case E1000_RDH(0): 1896 retval = sc->esc_RDH; 1897 break; 1898 case E1000_RDT(0): 1899 retval = sc->esc_RDT; 1900 break; 1901 case E1000_RDTR: 1902 retval = sc->esc_RDTR; 1903 break; 1904 case E1000_RXDCTL(0): 1905 retval = sc->esc_RXDCTL; 1906 break; 1907 case E1000_RADV: 1908 retval = sc->esc_RADV; 1909 break; 1910 case E1000_RSRPD: 1911 retval = sc->esc_RSRPD; 1912 break; 1913 case E1000_RXCSUM: 1914 retval = sc->esc_RXCSUM; 1915 break; 1916 case E1000_TXCW: 1917 retval = sc->esc_TXCW; 1918 break; 1919 case E1000_TCTL: 1920 retval = sc->esc_TCTL; 1921 break; 1922 case E1000_TIPG: 1923 retval = sc->esc_TIPG; 1924 break; 1925 case E1000_AIT: 1926 retval = sc->esc_AIT; 1927 break; 1928 case E1000_TDBAL(0): 1929 retval = sc->esc_TDBAL; 1930 break; 1931 case E1000_TDBAH(0): 1932 retval = sc->esc_TDBAH; 1933 break; 1934 case E1000_TDLEN(0): 1935 retval = sc->esc_TDLEN; 1936 break; 1937 case E1000_TDH(0): 1938 retval = sc->esc_TDH; 1939 break; 1940 case E1000_TDT(0): 1941 retval = sc->esc_TDT; 1942 break; 1943 case E1000_TIDV: 1944 retval = sc->esc_TIDV; 1945 break; 1946 case E1000_TXDCTL(0): 1947 retval = sc->esc_TXDCTL; 1948 break; 1949 case E1000_TADV: 1950 retval = sc->esc_TADV; 1951 break; 1952 case E1000_RAL(0) ... E1000_RAH(15): 1953 /* convert to u32 offset */ 1954 ridx = (offset - E1000_RAL(0)) >> 2; 1955 retval = e82545_read_ra(sc, ridx); 1956 break; 1957 case E1000_MTA ... (E1000_MTA + (127*4)): 1958 retval = sc->esc_fmcast[(offset - E1000_MTA) >> 2]; 1959 break; 1960 case E1000_VFTA ... (E1000_VFTA + (127*4)): 1961 retval = sc->esc_fvlan[(offset - E1000_VFTA) >> 2]; 1962 break; 1963 case E1000_EECD: 1964 //DPRINTF("EECD read %x", sc->eeprom_control); 1965 retval = sc->eeprom_control; 1966 break; 1967 case E1000_MDIC: 1968 retval = sc->mdi_control; 1969 break; 1970 case E1000_MANC: 1971 retval = 0; 1972 break; 1973 /* stats that we emulate. */ 1974 case E1000_MPC: 1975 retval = sc->missed_pkt_count; 1976 break; 1977 case E1000_PRC64: 1978 retval = sc->pkt_rx_by_size[0]; 1979 break; 1980 case E1000_PRC127: 1981 retval = sc->pkt_rx_by_size[1]; 1982 break; 1983 case E1000_PRC255: 1984 retval = sc->pkt_rx_by_size[2]; 1985 break; 1986 case E1000_PRC511: 1987 retval = sc->pkt_rx_by_size[3]; 1988 break; 1989 case E1000_PRC1023: 1990 retval = sc->pkt_rx_by_size[4]; 1991 break; 1992 case E1000_PRC1522: 1993 retval = sc->pkt_rx_by_size[5]; 1994 break; 1995 case E1000_GPRC: 1996 retval = sc->good_pkt_rx_count; 1997 break; 1998 case E1000_BPRC: 1999 retval = sc->bcast_pkt_rx_count; 2000 break; 2001 case E1000_MPRC: 2002 retval = sc->mcast_pkt_rx_count; 2003 break; 2004 case E1000_GPTC: 2005 case E1000_TPT: 2006 retval = sc->good_pkt_tx_count; 2007 break; 2008 case E1000_GORCL: 2009 retval = (uint32_t)sc->good_octets_rx; 2010 break; 2011 case E1000_GORCH: 2012 retval = (uint32_t)(sc->good_octets_rx >> 32); 2013 break; 2014 case E1000_TOTL: 2015 case E1000_GOTCL: 2016 retval = (uint32_t)sc->good_octets_tx; 2017 break; 2018 case E1000_TOTH: 2019 case E1000_GOTCH: 2020 retval = (uint32_t)(sc->good_octets_tx >> 32); 2021 break; 2022 case E1000_ROC: 2023 retval = sc->oversize_rx_count; 2024 break; 2025 case E1000_TORL: 2026 retval = (uint32_t)(sc->good_octets_rx + sc->missed_octets); 2027 break; 2028 case E1000_TORH: 2029 retval = (uint32_t)((sc->good_octets_rx + 2030 sc->missed_octets) >> 32); 2031 break; 2032 case E1000_TPR: 2033 retval = sc->good_pkt_rx_count + sc->missed_pkt_count + 2034 sc->oversize_rx_count; 2035 break; 2036 case E1000_PTC64: 2037 retval = sc->pkt_tx_by_size[0]; 2038 break; 2039 case E1000_PTC127: 2040 retval = sc->pkt_tx_by_size[1]; 2041 break; 2042 case E1000_PTC255: 2043 retval = sc->pkt_tx_by_size[2]; 2044 break; 2045 case E1000_PTC511: 2046 retval = sc->pkt_tx_by_size[3]; 2047 break; 2048 case E1000_PTC1023: 2049 retval = sc->pkt_tx_by_size[4]; 2050 break; 2051 case E1000_PTC1522: 2052 retval = sc->pkt_tx_by_size[5]; 2053 break; 2054 case E1000_MPTC: 2055 retval = sc->mcast_pkt_tx_count; 2056 break; 2057 case E1000_BPTC: 2058 retval = sc->bcast_pkt_tx_count; 2059 break; 2060 case E1000_TSCTC: 2061 retval = sc->tso_tx_count; 2062 break; 2063 /* stats that are always 0. */ 2064 case E1000_CRCERRS: 2065 case E1000_ALGNERRC: 2066 case E1000_SYMERRS: 2067 case E1000_RXERRC: 2068 case E1000_SCC: 2069 case E1000_ECOL: 2070 case E1000_MCC: 2071 case E1000_LATECOL: 2072 case E1000_COLC: 2073 case E1000_DC: 2074 case E1000_TNCRS: 2075 case E1000_SEC: 2076 case E1000_CEXTERR: 2077 case E1000_RLEC: 2078 case E1000_XONRXC: 2079 case E1000_XONTXC: 2080 case E1000_XOFFRXC: 2081 case E1000_XOFFTXC: 2082 case E1000_FCRUC: 2083 case E1000_RNBC: 2084 case E1000_RUC: 2085 case E1000_RFC: 2086 case E1000_RJC: 2087 case E1000_MGTPRC: 2088 case E1000_MGTPDC: 2089 case E1000_MGTPTC: 2090 case E1000_TSCTFC: 2091 retval = 0; 2092 break; 2093 default: 2094 DPRINTF("Unknown read register: 0x%x", offset); 2095 retval = 0; 2096 break; 2097 } 2098 2099 return (retval); 2100 } 2101 2102 static void 2103 e82545_write(struct vmctx *ctx, int vcpu, struct pci_devinst *pi, int baridx, 2104 uint64_t offset, int size, uint64_t value) 2105 { 2106 struct e82545_softc *sc; 2107 2108 //DPRINTF("Write bar:%d offset:0x%lx value:0x%lx size:%d", baridx, offset, value, size); 2109 2110 sc = pi->pi_arg; 2111 2112 pthread_mutex_lock(&sc->esc_mtx); 2113 2114 switch (baridx) { 2115 case E82545_BAR_IO: 2116 switch (offset) { 2117 case E82545_IOADDR: 2118 if (size != 4) { 2119 DPRINTF("Wrong io addr write sz:%d value:0x%lx", size, value); 2120 } else 2121 sc->io_addr = (uint32_t)value; 2122 break; 2123 case E82545_IODATA: 2124 if (size != 4) { 2125 DPRINTF("Wrong io data write size:%d value:0x%lx", size, value); 2126 } else if (sc->io_addr > E82545_IO_REGISTER_MAX) { 2127 DPRINTF("Non-register io write addr:0x%x value:0x%lx", sc->io_addr, value); 2128 } else 2129 e82545_write_register(sc, sc->io_addr, 2130 (uint32_t)value); 2131 break; 2132 default: 2133 DPRINTF("Unknown io bar write offset:0x%lx value:0x%lx size:%d", offset, value, size); 2134 break; 2135 } 2136 break; 2137 case E82545_BAR_REGISTER: 2138 if (size != 4) { 2139 DPRINTF("Wrong register write size:%d offset:0x%lx value:0x%lx", size, offset, value); 2140 } else 2141 e82545_write_register(sc, (uint32_t)offset, 2142 (uint32_t)value); 2143 break; 2144 default: 2145 DPRINTF("Unknown write bar:%d off:0x%lx val:0x%lx size:%d", 2146 baridx, offset, value, size); 2147 } 2148 2149 pthread_mutex_unlock(&sc->esc_mtx); 2150 } 2151 2152 static uint64_t 2153 e82545_read(struct vmctx *ctx, int vcpu, struct pci_devinst *pi, int baridx, 2154 uint64_t offset, int size) 2155 { 2156 struct e82545_softc *sc; 2157 uint64_t retval; 2158 2159 //DPRINTF("Read bar:%d offset:0x%lx size:%d", baridx, offset, size); 2160 sc = pi->pi_arg; 2161 retval = 0; 2162 2163 pthread_mutex_lock(&sc->esc_mtx); 2164 2165 switch (baridx) { 2166 case E82545_BAR_IO: 2167 switch (offset) { 2168 case E82545_IOADDR: 2169 if (size != 4) { 2170 DPRINTF("Wrong io addr read sz:%d", size); 2171 } else 2172 retval = sc->io_addr; 2173 break; 2174 case E82545_IODATA: 2175 if (size != 4) { 2176 DPRINTF("Wrong io data read sz:%d", size); 2177 } 2178 if (sc->io_addr > E82545_IO_REGISTER_MAX) { 2179 DPRINTF("Non-register io read addr:0x%x", 2180 sc->io_addr); 2181 } else 2182 retval = e82545_read_register(sc, sc->io_addr); 2183 break; 2184 default: 2185 DPRINTF("Unknown io bar read offset:0x%lx size:%d", 2186 offset, size); 2187 break; 2188 } 2189 break; 2190 case E82545_BAR_REGISTER: 2191 if (size != 4) { 2192 DPRINTF("Wrong register read size:%d offset:0x%lx", 2193 size, offset); 2194 } else 2195 retval = e82545_read_register(sc, (uint32_t)offset); 2196 break; 2197 default: 2198 DPRINTF("Unknown read bar:%d offset:0x%lx size:%d", 2199 baridx, offset, size); 2200 break; 2201 } 2202 2203 pthread_mutex_unlock(&sc->esc_mtx); 2204 2205 return (retval); 2206 } 2207 2208 static void 2209 e82545_reset(struct e82545_softc *sc, int drvr) 2210 { 2211 int i; 2212 2213 e82545_rx_disable(sc); 2214 e82545_tx_disable(sc); 2215 2216 /* clear outstanding interrupts */ 2217 if (sc->esc_irq_asserted) 2218 pci_lintr_deassert(sc->esc_pi); 2219 2220 /* misc */ 2221 if (!drvr) { 2222 sc->esc_FCAL = 0; 2223 sc->esc_FCAH = 0; 2224 sc->esc_FCT = 0; 2225 sc->esc_VET = 0; 2226 sc->esc_FCTTV = 0; 2227 } 2228 sc->esc_LEDCTL = 0x07061302; 2229 sc->esc_PBA = 0x00100030; 2230 2231 /* start nvm in opcode mode. */ 2232 sc->nvm_opaddr = 0; 2233 sc->nvm_mode = E82545_NVM_MODE_OPADDR; 2234 sc->nvm_bits = E82545_NVM_OPADDR_BITS; 2235 sc->eeprom_control = E1000_EECD_PRES | E82545_EECD_FWE_EN; 2236 e82545_init_eeprom(sc); 2237 2238 /* interrupt */ 2239 sc->esc_ICR = 0; 2240 sc->esc_ITR = 250; 2241 sc->esc_ICS = 0; 2242 sc->esc_IMS = 0; 2243 sc->esc_IMC = 0; 2244 2245 /* L2 filters */ 2246 if (!drvr) { 2247 memset(sc->esc_fvlan, 0, sizeof(sc->esc_fvlan)); 2248 memset(sc->esc_fmcast, 0, sizeof(sc->esc_fmcast)); 2249 memset(sc->esc_uni, 0, sizeof(sc->esc_uni)); 2250 2251 /* XXX not necessary on 82545 ?? */ 2252 sc->esc_uni[0].eu_valid = 1; 2253 memcpy(sc->esc_uni[0].eu_eth.octet, sc->esc_mac.octet, 2254 ETHER_ADDR_LEN); 2255 } else { 2256 /* Clear RAH valid bits */ 2257 for (i = 0; i < 16; i++) 2258 sc->esc_uni[i].eu_valid = 0; 2259 } 2260 2261 /* receive */ 2262 if (!drvr) { 2263 sc->esc_RDBAL = 0; 2264 sc->esc_RDBAH = 0; 2265 } 2266 sc->esc_RCTL = 0; 2267 sc->esc_FCRTL = 0; 2268 sc->esc_FCRTH = 0; 2269 sc->esc_RDLEN = 0; 2270 sc->esc_RDH = 0; 2271 sc->esc_RDT = 0; 2272 sc->esc_RDTR = 0; 2273 sc->esc_RXDCTL = (1 << 24) | (1 << 16); /* default GRAN/WTHRESH */ 2274 sc->esc_RADV = 0; 2275 sc->esc_RXCSUM = 0; 2276 2277 /* transmit */ 2278 if (!drvr) { 2279 sc->esc_TDBAL = 0; 2280 sc->esc_TDBAH = 0; 2281 sc->esc_TIPG = 0; 2282 sc->esc_AIT = 0; 2283 sc->esc_TIDV = 0; 2284 sc->esc_TADV = 0; 2285 } 2286 sc->esc_tdba = 0; 2287 sc->esc_txdesc = NULL; 2288 sc->esc_TXCW = 0; 2289 sc->esc_TCTL = 0; 2290 sc->esc_TDLEN = 0; 2291 sc->esc_TDT = 0; 2292 sc->esc_TDHr = sc->esc_TDH = 0; 2293 sc->esc_TXDCTL = 0; 2294 } 2295 2296 static int 2297 e82545_init(struct vmctx *ctx, struct pci_devinst *pi, nvlist_t *nvl) 2298 { 2299 char nstr[80]; 2300 struct e82545_softc *sc; 2301 const char *mac; 2302 int err; 2303 2304 /* Setup our softc */ 2305 sc = calloc(1, sizeof(*sc)); 2306 2307 pi->pi_arg = sc; 2308 sc->esc_pi = pi; 2309 sc->esc_ctx = ctx; 2310 2311 pthread_mutex_init(&sc->esc_mtx, NULL); 2312 pthread_cond_init(&sc->esc_rx_cond, NULL); 2313 pthread_cond_init(&sc->esc_tx_cond, NULL); 2314 pthread_create(&sc->esc_tx_tid, NULL, e82545_tx_thread, sc); 2315 snprintf(nstr, sizeof(nstr), "e82545-%d:%d tx", pi->pi_slot, 2316 pi->pi_func); 2317 pthread_set_name_np(sc->esc_tx_tid, nstr); 2318 2319 pci_set_cfgdata16(pi, PCIR_DEVICE, E82545_DEV_ID_82545EM_COPPER); 2320 pci_set_cfgdata16(pi, PCIR_VENDOR, E82545_VENDOR_ID_INTEL); 2321 pci_set_cfgdata8(pi, PCIR_CLASS, PCIC_NETWORK); 2322 pci_set_cfgdata8(pi, PCIR_SUBCLASS, PCIS_NETWORK_ETHERNET); 2323 pci_set_cfgdata16(pi, PCIR_SUBDEV_0, E82545_SUBDEV_ID); 2324 pci_set_cfgdata16(pi, PCIR_SUBVEND_0, E82545_VENDOR_ID_INTEL); 2325 2326 pci_set_cfgdata8(pi, PCIR_HDRTYPE, PCIM_HDRTYPE_NORMAL); 2327 pci_set_cfgdata8(pi, PCIR_INTPIN, 0x1); 2328 2329 /* TODO: this card also supports msi, but the freebsd driver for it 2330 * does not, so I have not implemented it. */ 2331 pci_lintr_request(pi); 2332 2333 pci_emul_alloc_bar(pi, E82545_BAR_REGISTER, PCIBAR_MEM32, 2334 E82545_BAR_REGISTER_LEN); 2335 pci_emul_alloc_bar(pi, E82545_BAR_FLASH, PCIBAR_MEM32, 2336 E82545_BAR_FLASH_LEN); 2337 pci_emul_alloc_bar(pi, E82545_BAR_IO, PCIBAR_IO, 2338 E82545_BAR_IO_LEN); 2339 2340 mac = get_config_value_node(nvl, "mac"); 2341 if (mac != NULL) { 2342 err = net_parsemac(mac, sc->esc_mac.octet); 2343 if (err) { 2344 free(sc); 2345 return (err); 2346 } 2347 } else 2348 net_genmac(pi, sc->esc_mac.octet); 2349 2350 err = netbe_init(&sc->esc_be, nvl, e82545_rx_callback, sc); 2351 if (err) { 2352 free(sc); 2353 return (err); 2354 } 2355 2356 #ifndef __FreeBSD__ 2357 size_t buflen = sizeof (sc->esc_mac.octet); 2358 2359 err = netbe_get_mac(sc->esc_be, sc->esc_mac.octet, &buflen); 2360 if (err != 0) { 2361 free(sc); 2362 return (err); 2363 } 2364 #endif 2365 2366 netbe_rx_enable(sc->esc_be); 2367 2368 /* H/w initiated reset */ 2369 e82545_reset(sc, 0); 2370 2371 return (0); 2372 } 2373 2374 struct pci_devemu pci_de_e82545 = { 2375 .pe_emu = "e1000", 2376 .pe_init = e82545_init, 2377 .pe_legacy_config = netbe_legacy_config, 2378 .pe_barwrite = e82545_write, 2379 .pe_barread = e82545_read, 2380 }; 2381 PCI_EMUL_SET(pci_de_e82545); 2382 2383