1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD 3 * 4 * Copyright (c) 2015 Nahanni Systems, Inc. 5 * Copyright 2018 Joyent, Inc. 6 * All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND 18 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 19 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 20 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 21 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 22 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 23 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 24 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 25 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 26 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 27 * SUCH DAMAGE. 28 * 29 * $FreeBSD$ 30 */ 31 32 #include <sys/cdefs.h> 33 __FBSDID("$FreeBSD$"); 34 35 #include <sys/types.h> 36 #include <sys/mman.h> 37 38 #include <machine/vmm.h> 39 #include <vmmapi.h> 40 41 #include <stdio.h> 42 #include <stdlib.h> 43 #include <string.h> 44 45 #include <errno.h> 46 #include <unistd.h> 47 48 #include "bhyvegc.h" 49 #include "bhyverun.h" 50 #include "config.h" 51 #include "debug.h" 52 #include "console.h" 53 #include "inout.h" 54 #include "pci_emul.h" 55 #include "rfb.h" 56 #include "vga.h" 57 58 /* 59 * bhyve Framebuffer device emulation. 60 * BAR0 points to the current mode information. 61 * BAR1 is the 32-bit framebuffer address. 62 * 63 * -s <b>,fbuf,wait,vga=on|io|off,rfb=<ip>:port,w=width,h=height 64 */ 65 66 static int fbuf_debug = 1; 67 #define DEBUG_INFO 1 68 #define DEBUG_VERBOSE 4 69 #define DPRINTF(level, params) if (level <= fbuf_debug) PRINTLN params 70 71 72 #define KB (1024UL) 73 #define MB (1024 * 1024UL) 74 75 #define DMEMSZ 128 76 77 #define FB_SIZE (16*MB) 78 79 #define COLS_MAX 1920 80 #define ROWS_MAX 1200 81 82 #define COLS_DEFAULT 1024 83 #define ROWS_DEFAULT 768 84 85 #define COLS_MIN 640 86 #define ROWS_MIN 480 87 88 struct pci_fbuf_softc { 89 struct pci_devinst *fsc_pi; 90 struct { 91 uint32_t fbsize; 92 uint16_t width; 93 uint16_t height; 94 uint16_t depth; 95 uint16_t refreshrate; 96 uint8_t reserved[116]; 97 } __packed memregs; 98 99 /* rfb server */ 100 char *rfb_host; 101 char *rfb_password; 102 int rfb_port; 103 #ifndef __FreeBSD__ 104 const char *rfb_unix; 105 #endif 106 int rfb_wait; 107 int vga_enabled; 108 int vga_full; 109 110 uint32_t fbaddr; 111 char *fb_base; 112 uint16_t gc_width; 113 uint16_t gc_height; 114 void *vgasc; 115 struct bhyvegc_image *gc_image; 116 }; 117 118 static struct pci_fbuf_softc *fbuf_sc; 119 120 #define PCI_FBUF_MSI_MSGS 4 121 122 static void 123 pci_fbuf_write(struct vmctx *ctx, int vcpu, struct pci_devinst *pi, 124 int baridx, uint64_t offset, int size, uint64_t value) 125 { 126 struct pci_fbuf_softc *sc; 127 uint8_t *p; 128 129 assert(baridx == 0); 130 131 sc = pi->pi_arg; 132 133 DPRINTF(DEBUG_VERBOSE, 134 ("fbuf wr: offset 0x%lx, size: %d, value: 0x%lx", 135 offset, size, value)); 136 137 if (offset + size > DMEMSZ) { 138 printf("fbuf: write too large, offset %ld size %d\n", 139 offset, size); 140 return; 141 } 142 143 p = (uint8_t *)&sc->memregs + offset; 144 145 switch (size) { 146 case 1: 147 *p = value; 148 break; 149 case 2: 150 *(uint16_t *)p = value; 151 break; 152 case 4: 153 *(uint32_t *)p = value; 154 break; 155 case 8: 156 *(uint64_t *)p = value; 157 break; 158 default: 159 printf("fbuf: write unknown size %d\n", size); 160 break; 161 } 162 163 if (!sc->gc_image->vgamode && sc->memregs.width == 0 && 164 sc->memregs.height == 0) { 165 DPRINTF(DEBUG_INFO, ("switching to VGA mode")); 166 sc->gc_image->vgamode = 1; 167 sc->gc_width = 0; 168 sc->gc_height = 0; 169 } else if (sc->gc_image->vgamode && sc->memregs.width != 0 && 170 sc->memregs.height != 0) { 171 DPRINTF(DEBUG_INFO, ("switching to VESA mode")); 172 sc->gc_image->vgamode = 0; 173 } 174 } 175 176 uint64_t 177 pci_fbuf_read(struct vmctx *ctx, int vcpu, struct pci_devinst *pi, 178 int baridx, uint64_t offset, int size) 179 { 180 struct pci_fbuf_softc *sc; 181 uint8_t *p; 182 uint64_t value; 183 184 assert(baridx == 0); 185 186 sc = pi->pi_arg; 187 188 189 if (offset + size > DMEMSZ) { 190 printf("fbuf: read too large, offset %ld size %d\n", 191 offset, size); 192 return (0); 193 } 194 195 p = (uint8_t *)&sc->memregs + offset; 196 value = 0; 197 switch (size) { 198 case 1: 199 value = *p; 200 break; 201 case 2: 202 value = *(uint16_t *)p; 203 break; 204 case 4: 205 value = *(uint32_t *)p; 206 break; 207 case 8: 208 value = *(uint64_t *)p; 209 break; 210 default: 211 printf("fbuf: read unknown size %d\n", size); 212 break; 213 } 214 215 DPRINTF(DEBUG_VERBOSE, 216 ("fbuf rd: offset 0x%lx, size: %d, value: 0x%lx", 217 offset, size, value)); 218 219 return (value); 220 } 221 222 static void 223 pci_fbuf_baraddr(struct vmctx *ctx, struct pci_devinst *pi, int baridx, 224 int enabled, uint64_t address) 225 { 226 struct pci_fbuf_softc *sc; 227 int prot; 228 229 if (baridx != 1) 230 return; 231 232 sc = pi->pi_arg; 233 if (!enabled && sc->fbaddr != 0) { 234 if (vm_munmap_memseg(ctx, sc->fbaddr, FB_SIZE) != 0) 235 EPRINTLN("pci_fbuf: munmap_memseg failed"); 236 sc->fbaddr = 0; 237 } else if (sc->fb_base != NULL && sc->fbaddr == 0) { 238 prot = PROT_READ | PROT_WRITE; 239 if (vm_mmap_memseg(ctx, address, VM_FRAMEBUFFER, 0, FB_SIZE, prot) != 0) 240 EPRINTLN("pci_fbuf: mmap_memseg failed"); 241 sc->fbaddr = address; 242 } 243 } 244 245 246 static int 247 pci_fbuf_parse_config(struct pci_fbuf_softc *sc, nvlist_t *nvl) 248 { 249 const char *value; 250 char *cp; 251 252 sc->rfb_wait = get_config_bool_node_default(nvl, "wait", false); 253 254 /* Prefer "rfb" to "tcp". */ 255 value = get_config_value_node(nvl, "rfb"); 256 if (value == NULL) 257 value = get_config_value_node(nvl, "tcp"); 258 if (value != NULL) { 259 /* 260 * IPv4 -- host-ip:port 261 * IPv6 -- [host-ip%zone]:port 262 * XXX for now port is mandatory for IPv4. 263 */ 264 if (value[0] == '[') { 265 cp = strchr(value + 1, ']'); 266 if (cp == NULL || cp == value + 1) { 267 EPRINTLN("fbuf: Invalid IPv6 address: \"%s\"", 268 value); 269 return (-1); 270 } 271 sc->rfb_host = strndup(value + 1, cp - (value + 1)); 272 cp++; 273 if (*cp == ':') { 274 cp++; 275 if (*cp == '\0') { 276 EPRINTLN( 277 "fbuf: Missing port number: \"%s\"", 278 value); 279 return (-1); 280 } 281 sc->rfb_port = atoi(cp); 282 } else if (*cp != '\0') { 283 EPRINTLN("fbuf: Invalid IPv6 address: \"%s\"", 284 value); 285 return (-1); 286 } 287 } else { 288 cp = strchr(value, ':'); 289 if (cp == NULL) { 290 sc->rfb_port = atoi(value); 291 } else { 292 sc->rfb_host = strndup(value, cp - value); 293 cp++; 294 if (*cp == '\0') { 295 EPRINTLN( 296 "fbuf: Missing port number: \"%s\"", 297 value); 298 return (-1); 299 } 300 sc->rfb_port = atoi(cp); 301 } 302 } 303 } 304 305 #ifndef __FreeBSD__ 306 sc->rfb_unix = get_config_value_node(nvl, "unix"); 307 #endif 308 309 value = get_config_value_node(nvl, "vga"); 310 if (value != NULL) { 311 if (strcmp(value, "off") == 0) { 312 sc->vga_enabled = 0; 313 } else if (strcmp(value, "io") == 0) { 314 sc->vga_enabled = 1; 315 sc->vga_full = 0; 316 } else if (strcmp(value, "on") == 0) { 317 sc->vga_enabled = 1; 318 sc->vga_full = 1; 319 } else { 320 EPRINTLN("fbuf: Invalid vga setting: \"%s\"", value); 321 return (-1); 322 } 323 } 324 325 value = get_config_value_node(nvl, "w"); 326 if (value != NULL) { 327 sc->memregs.width = atoi(value); 328 if (sc->memregs.width > COLS_MAX) { 329 EPRINTLN("fbuf: width %d too large", sc->memregs.width); 330 return (-1); 331 } 332 if (sc->memregs.width == 0) 333 sc->memregs.width = 1920; 334 } 335 336 value = get_config_value_node(nvl, "h"); 337 if (value != NULL) { 338 sc->memregs.height = atoi(value); 339 if (sc->memregs.height > ROWS_MAX) { 340 EPRINTLN("fbuf: height %d too large", 341 sc->memregs.height); 342 return (-1); 343 } 344 if (sc->memregs.height == 0) 345 sc->memregs.height = 1080; 346 } 347 348 value = get_config_value_node(nvl, "password"); 349 if (value != NULL) 350 sc->rfb_password = strdup(value); 351 352 return (0); 353 } 354 355 356 extern void vga_render(struct bhyvegc *gc, void *arg); 357 358 void 359 pci_fbuf_render(struct bhyvegc *gc, void *arg) 360 { 361 struct pci_fbuf_softc *sc; 362 363 sc = arg; 364 365 if (sc->vga_full && sc->gc_image->vgamode) { 366 /* TODO: mode switching to vga and vesa should use the special 367 * EFI-bhyve protocol port. 368 */ 369 vga_render(gc, sc->vgasc); 370 return; 371 } 372 if (sc->gc_width != sc->memregs.width || 373 sc->gc_height != sc->memregs.height) { 374 bhyvegc_resize(gc, sc->memregs.width, sc->memregs.height); 375 sc->gc_width = sc->memregs.width; 376 sc->gc_height = sc->memregs.height; 377 } 378 379 return; 380 } 381 382 static int 383 pci_fbuf_init(struct vmctx *ctx, struct pci_devinst *pi, nvlist_t *nvl) 384 { 385 int error, prot; 386 struct pci_fbuf_softc *sc; 387 388 if (fbuf_sc != NULL) { 389 EPRINTLN("Only one frame buffer device is allowed."); 390 return (-1); 391 } 392 393 sc = calloc(1, sizeof(struct pci_fbuf_softc)); 394 395 pi->pi_arg = sc; 396 397 /* initialize config space */ 398 pci_set_cfgdata16(pi, PCIR_DEVICE, 0x40FB); 399 pci_set_cfgdata16(pi, PCIR_VENDOR, 0xFB5D); 400 pci_set_cfgdata8(pi, PCIR_CLASS, PCIC_DISPLAY); 401 pci_set_cfgdata8(pi, PCIR_SUBCLASS, PCIS_DISPLAY_VGA); 402 403 error = pci_emul_alloc_bar(pi, 0, PCIBAR_MEM32, DMEMSZ); 404 assert(error == 0); 405 406 error = pci_emul_alloc_bar(pi, 1, PCIBAR_MEM32, FB_SIZE); 407 assert(error == 0); 408 409 error = pci_emul_add_msicap(pi, PCI_FBUF_MSI_MSGS); 410 assert(error == 0); 411 412 sc->fbaddr = pi->pi_bar[1].addr; 413 sc->memregs.fbsize = FB_SIZE; 414 sc->memregs.width = COLS_DEFAULT; 415 sc->memregs.height = ROWS_DEFAULT; 416 sc->memregs.depth = 32; 417 418 sc->vga_enabled = 1; 419 sc->vga_full = 0; 420 421 sc->fsc_pi = pi; 422 423 error = pci_fbuf_parse_config(sc, nvl); 424 if (error != 0) 425 goto done; 426 427 /* XXX until VGA rendering is enabled */ 428 if (sc->vga_full != 0) { 429 EPRINTLN("pci_fbuf: VGA rendering not enabled"); 430 goto done; 431 } 432 433 sc->fb_base = vm_create_devmem(ctx, VM_FRAMEBUFFER, "framebuffer", FB_SIZE); 434 if (sc->fb_base == MAP_FAILED) { 435 error = -1; 436 goto done; 437 } 438 DPRINTF(DEBUG_INFO, ("fbuf frame buffer base: %p [sz %lu]", 439 sc->fb_base, FB_SIZE)); 440 441 /* 442 * Map the framebuffer into the guest address space. 443 * XXX This may fail if the BAR is different than a prior 444 * run. In this case flag the error. This will be fixed 445 * when a change_memseg api is available. 446 */ 447 prot = PROT_READ | PROT_WRITE; 448 if (vm_mmap_memseg(ctx, sc->fbaddr, VM_FRAMEBUFFER, 0, FB_SIZE, prot) != 0) { 449 EPRINTLN("pci_fbuf: mapseg failed - try deleting VM and restarting"); 450 error = -1; 451 goto done; 452 } 453 454 console_init(sc->memregs.width, sc->memregs.height, sc->fb_base); 455 console_fb_register(pci_fbuf_render, sc); 456 457 if (sc->vga_enabled) 458 sc->vgasc = vga_init(!sc->vga_full); 459 sc->gc_image = console_get_image(); 460 461 fbuf_sc = sc; 462 463 memset((void *)sc->fb_base, 0, FB_SIZE); 464 465 #ifdef __FreeBSD__ 466 error = rfb_init(sc->rfb_host, sc->rfb_port, sc->rfb_wait, sc->rfb_password); 467 #else 468 if (sc->rfb_unix != NULL) { 469 error = rfb_init_unix(sc->rfb_unix, sc->rfb_wait, 470 sc->rfb_password); 471 } else { 472 error = rfb_init(sc->rfb_host, sc->rfb_port, sc->rfb_wait, 473 sc->rfb_password); 474 } 475 #endif 476 done: 477 if (error) 478 free(sc); 479 480 return (error); 481 } 482 483 struct pci_devemu pci_fbuf = { 484 .pe_emu = "fbuf", 485 .pe_init = pci_fbuf_init, 486 .pe_barwrite = pci_fbuf_write, 487 .pe_barread = pci_fbuf_read, 488 .pe_baraddr = pci_fbuf_baraddr, 489 }; 490 PCI_EMUL_SET(pci_fbuf); 491