1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License (the "License"). 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9 * or http://www.opensolaris.org/os/licensing. 10 * See the License for the specific language governing permissions 11 * and limitations under the License. 12 * 13 * When distributing Covered Code, include this CDDL HEADER in each 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15 * If applicable, add the following below this CDDL HEADER, with the 16 * fields enclosed by brackets "[]" replaced with your own identifying 17 * information: Portions Copyright [yyyy] [name of copyright owner] 18 * 19 * CDDL HEADER END 20 */ 21 22 /* Copyright 2010 QLogic Corporation */ 23 24 /* 25 * ISP2xxx Solaris Fibre Channel Adapter (FCA) qlc mdb source file. 26 * 27 * *********************************************************************** 28 * * ** 29 * * NOTICE ** 30 * * COPYRIGHT (C) 1996-2010 QLOGIC CORPORATION ** 31 * * ALL RIGHTS RESERVED ** 32 * * ** 33 * *********************************************************************** 34 * 35 */ 36 37 /* 38 * Copyright 2019 Joyent, Inc. 39 */ 40 41 #include <sys/mdb_modapi.h> 42 #include <ql_apps.h> 43 #include <ql_api.h> 44 #include <ql_init.h> 45 #include <ql_debug.h> 46 47 /* 48 * local prototypes 49 */ 50 static int32_t ql_doprint(uintptr_t, int8_t *); 51 static void ql_dump_flags(uint64_t, int8_t **); 52 static int qlclinks_dcmd(uintptr_t, uint_t, int, const mdb_arg_t *); 53 static int qlcstate_dcmd(uintptr_t, uint_t, int, const mdb_arg_t *); 54 static int qlc_osc_dcmd(uintptr_t, uint_t, int, const mdb_arg_t *); 55 static int qlc_wdog_dcmd(uintptr_t, uint_t, int, const mdb_arg_t *); 56 static int qlc_getdump_dcmd(uintptr_t, uint_t, int, const mdb_arg_t *); 57 static int qlc_gettrace_dcmd(uintptr_t, uint_t, int, const mdb_arg_t *); 58 #if 0 59 static int qlc_triggerdump_dcmd(uintptr_t, uint_t, int, const mdb_arg_t *); 60 #endif 61 static int qlcver_dcmd(uintptr_t, uint_t, int, const mdb_arg_t *); 62 static int qlstates_walk_init(mdb_walk_state_t *); 63 static int qlstates_walk_step(mdb_walk_state_t *); 64 static void qlstates_walk_fini(mdb_walk_state_t *); 65 static int qlsrb_walk_init(mdb_walk_state_t *); 66 static int qlsrb_walk_step(mdb_walk_state_t *); 67 static void qlsrb_walk_fini(mdb_walk_state_t *); 68 static int get_next_link(ql_link_t *); 69 static int get_first_link(ql_head_t *, ql_link_t *); 70 71 static int ql_24xx_dump_dcmd(ql_adapter_state_t *, uint_t, int, 72 const mdb_arg_t *); 73 static int ql_23xx_dump_dcmd(ql_adapter_state_t *, uint_t, int, 74 const mdb_arg_t *); 75 static int ql_25xx_dump_dcmd(ql_adapter_state_t *, uint_t, int, 76 const mdb_arg_t *); 77 static int ql_81xx_dump_dcmd(ql_adapter_state_t *, uint_t, int, 78 const mdb_arg_t *); 79 static void ql_elog_common(ql_adapter_state_t *, boolean_t); 80 81 /* 82 * local adapter state flags strings 83 */ 84 int8_t *adapter_state_flags[] = { 85 "FCA_BOUND", 86 "QL_OPENED", 87 "ONLINE", 88 "INTERRUPTS_ENABLED", 89 "ABORT_CMDS_LOOP_DOWN_TMO", 90 "POINT_TO_POINT", 91 "IP_ENABLED", 92 "IP_INITIALIZED", 93 "MENLO_LOGIN_OPERATIONAL", 94 "ADAPTER_SUSPENDED", 95 "ADAPTER_TIMER_BUSY", 96 "PARITY_ERROR", 97 "FLASH_ERRLOG_MARKER", 98 "VP_ENABLED", 99 "FDISC_ENABLED", 100 "FUNCTION_1", 101 "MPI_RESET_NEEDED", 102 NULL 103 }; 104 105 int8_t *adapter_config_flags[] = { 106 "ENABLE_HARD_ADDRESS", 107 "ENABLE_64BIT_ADDRESSING", 108 "ENABLE_LIP_RESET", 109 "ENABLE_FULL_LIP_LOGIN", 110 "ENABLE_TARGET_RESET", 111 "ENABLE_LINK_DOWN_REPORTING", 112 "DISABLE_EXTENDED_LOGGING_TRACE", 113 "ENABLE_FCP_2_SUPPORT", 114 "MULTI_CHIP_ADAPTER", 115 "SBUS_CARD", 116 "CTRL_2300", 117 "CTRL_6322", 118 "CTRL_2200", 119 "CTRL_2422", 120 "CTRL_25XX", 121 "ENABLE_EXTENDED_LOGGING", 122 "DISABLE_RISC_CODE_LOAD", 123 "SET_CACHE_LINE_SIZE_1", 124 "CTRL_MENLO", 125 "EXT_FW_INTERFACE", 126 "LOAD_FLASH_FW", 127 "DUMP_MAILBOX_TIMEOUT", 128 "DUMP_ISP_SYSTEM_ERROR", 129 "DUMP_DRIVER_COMMAND_TIMEOUT", 130 "DUMP_LOOP_OFFLINE_TIMEOUT", 131 "ENABLE_FWEXTTRACE", 132 "ENABLE_FWFCETRACE", 133 "FW_MISMATCH", 134 "CTRL_81XX", 135 "CTRL_8021", 136 "ENABLE_FAST_TIMEOUT", 137 "LR_SUPPORT", 138 NULL 139 }; 140 141 /* 142 * local task daemon flags strings 143 */ 144 int8_t *task_daemon_flags[] = { 145 "TASK_DAEMON_STOP_FLG", 146 "TASK_DAEMON_SLEEPING_FLG", 147 "TASK_DAEMON_ALIVE_FLG", 148 "TASK_DAEMON_IDLE_CHK_FLG", 149 "SUSPENDED_WAKEUP_FLG", 150 "FC_STATE_CHANGE", 151 "NEED_UNSOLICITED_BUFFERS", 152 "RESET_MARKER_NEEDED", 153 "RESET_ACTIVE", 154 "ISP_ABORT_NEEDED", 155 "ABORT_ISP_ACTIVE", 156 "LOOP_RESYNC_NEEDED", 157 "LOOP_RESYNC_ACTIVE", 158 "LOOP_DOWN", 159 "DRIVER_STALL", 160 "COMMAND_WAIT_NEEDED", 161 "COMMAND_WAIT_ACTIVE", 162 "STATE_ONLINE", 163 "ABORT_QUEUES_NEEDED", 164 "TASK_DAEMON_STALLED_FLG", 165 "TASK_THREAD_CALLED", 166 "FIRMWARE_UP", 167 "LIP_RESET_PENDING", 168 "FIRMWARE_LOADED", 169 "RSCN_UPDATE_NEEDED", 170 "HANDLE_PORT_BYPASS_CHANGE", 171 "PORT_RETRY_NEEDED", 172 "TASK_DAEMON_POWERING_DOWN", 173 "TD_IIDMA_NEEDED", 174 "SEND_PLOGI", 175 "IDC_EVENT", 176 NULL 177 }; 178 179 /* 180 * local interrupt aif flags 181 */ 182 int8_t *aif_flags[] = { 183 "IFLG_INTR_LEGACY", 184 "IFLG_INTR_FIXED", 185 "IFLG_INTR_MSI", 186 "IFLG_INTR_MSIX", 187 NULL 188 }; 189 190 int8_t *qlsrb_flags[] = { 191 "SRB_ISP_STARTED", 192 "SRB_ISP_COMPLETED", 193 "SRB_RETRY", 194 "SRB_POLL", 195 "SRB_WATCHDOG_ENABLED", 196 "SRB_ABORT", 197 "SRB_UB_IN_FCA", 198 "SRB_UB_IN_ISP", 199 "SRB_UB_CALLBACK", 200 "SRB_UB_RSCN", 201 "SRB_UB_FCP", 202 "SRB_FCP_CMD_PKT", 203 "SRB_FCP_DATA_PKT", 204 "SRB_FCP_RSP_PKT", 205 "SRB_IP_PKT", 206 "SRB_GENERIC_SERVICES_PKT", 207 "SRB_COMMAND_TIMEOUT", 208 "SRB_ABORTING", 209 "SRB_IN_DEVICE_QUEUE", 210 "SRB_IN_TOKEN_ARRAY", 211 "SRB_UB_FREE_REQUESTED", 212 "SRB_UB_ACQUIRED", 213 "SRB_MS_PKT", 214 NULL 215 }; 216 217 int8_t *qllun_flags[] = { 218 "LQF_UNTAGGED_PENDING", 219 NULL 220 }; 221 222 int8_t *qltgt_flags[] = { 223 "TQF_TAPE_DEVICE", 224 "TQF_QUEUE_SUSPENDED", 225 "TQF_FABRIC_DEVICE", 226 "TQF_INITIATOR_DEVICE", 227 "TQF_RSCN_RCVD", 228 "TQF_NEED_AUTHENTICATION", 229 "TQF_PLOGI_PROGRS", 230 "TQF_IIDMA_NEEDED", 231 NULL 232 }; 233 234 int8_t *qldump_flags[] = { 235 "QL_DUMPING", 236 "QL_DUMP_VALID", 237 "QL_DUMP_UPLOADED", 238 NULL 239 }; 240 241 /* 242 * qlclinks_dcmd 243 * mdb dcmd which prints out the ql_hba pointers 244 * 245 * Input: 246 * addr = User supplied address -- error if supplied. 247 * flags = mdb flags. 248 * argc = Number of user supplied args -- error if non-zero. 249 * argv = Arg array. 250 * 251 * Returns: 252 * DCMD_ERR, DCMD_USAGE, or DCMD_OK 253 * 254 * Context: 255 * User context. 256 * 257 */ 258 /*ARGSUSED*/ 259 static int 260 qlclinks_dcmd(uintptr_t addr, uint_t flags, int argc, const mdb_arg_t *argv) 261 { 262 ql_head_t ql_hba; 263 ql_adapter_state_t *qlstate; 264 uintptr_t hbaptr = 0; 265 266 if ((flags & DCMD_ADDRSPEC) || argc != 0) { 267 return (DCMD_USAGE); 268 } 269 270 if (mdb_readvar(&ql_hba, "ql_hba") == -1) { 271 mdb_warn("failed to read ql_hba structure"); 272 return (DCMD_ERR); 273 } 274 275 if (&ql_hba == NULL) { 276 mdb_warn("failed to read ql_hba structure -- is qlc loaded?"); 277 return (DCMD_ERR); 278 } 279 280 mdb_printf("\nqlc adapter state linkages (f=0x%llx, l=0x%llx)\n\n", 281 ql_hba.first, ql_hba.last); 282 283 if ((qlstate = (ql_adapter_state_t *)mdb_alloc( 284 sizeof (ql_adapter_state_t), UM_SLEEP)) == NULL) { 285 mdb_warn("Unable to allocate memory for ql_adapter_state\n"); 286 return (DCMD_OK); 287 } 288 289 (void) mdb_inc_indent((ulong_t)4); 290 mdb_printf("%<u>%-?s\t%-45s%</u>\n\n", "baseaddr", "instance"); 291 292 hbaptr = (uintptr_t)ql_hba.first; 293 while (hbaptr != 0) { 294 295 if (mdb_vread(qlstate, sizeof (ql_adapter_state_t), 296 hbaptr) == -1) { 297 mdb_free(qlstate, sizeof (ql_adapter_state_t)); 298 mdb_warn("failed to read ql_adapter_state at %p", 299 hbaptr); 300 return (DCMD_OK); 301 } 302 303 mdb_printf("%<b>0x%016p%t%d%</b>\n", 304 qlstate->hba.base_address, qlstate->instance); 305 306 /* 307 * If vp exists, loop through those 308 */ 309 310 if ((qlstate->flags & VP_ENABLED) && 311 (qlstate->vp_next != NULL)) { 312 313 ql_adapter_state_t *vqlstate; 314 uintptr_t vhbaptr = 0; 315 316 vhbaptr = (uintptr_t)qlstate->vp_next; 317 318 if ((vqlstate = (ql_adapter_state_t *)mdb_alloc( 319 sizeof (ql_adapter_state_t), UM_SLEEP)) == NULL) { 320 mdb_warn("Unable to allocate memory for " 321 "ql_adapter_state vp\n"); 322 mdb_free(qlstate, sizeof (ql_adapter_state_t)); 323 return (DCMD_OK); 324 } 325 326 (void) mdb_inc_indent((ulong_t)30); 327 328 mdb_printf("%<u>vp baseaddr\t\tvp index%</u>\n"); 329 330 while (vhbaptr != 0) { 331 332 if (mdb_vread(vqlstate, 333 sizeof (ql_adapter_state_t), vhbaptr) == 334 -1) { 335 mdb_free(vqlstate, 336 sizeof (ql_adapter_state_t)); 337 mdb_free(qlstate, 338 sizeof (ql_adapter_state_t)); 339 mdb_warn("failed to read vp " 340 "ql_adapter_state at %p", vhbaptr); 341 return (DCMD_OK); 342 } 343 344 mdb_printf("%<b>0x%016p%t%d%</b>\n", 345 vqlstate->hba.base_address, 346 vqlstate->vp_index); 347 348 vhbaptr = (uintptr_t)vqlstate->vp_next; 349 } 350 351 mdb_free(vqlstate, sizeof (ql_adapter_state_t)); 352 353 (void) mdb_dec_indent((ulong_t)30); 354 355 mdb_printf("\n"); 356 } 357 358 hbaptr = (uintptr_t)qlstate->hba.next; 359 } 360 361 (void) mdb_dec_indent((ulong_t)4); 362 363 mdb_free(qlstate, sizeof (ql_adapter_state_t)); 364 365 return (DCMD_OK); 366 } 367 368 /* 369 * qlcver_dcmd 370 * mdb dcmd which prints out the qlc driver version the mdb 371 * module was compiled with, and the verison of qlc which is 372 * currently loaded on the machine. 373 * 374 * Input: 375 * addr = User supplied address -- error if supplied. 376 * flags = mdb flags. 377 * argc = Number of user supplied args -- error if non-zero. 378 * argv = Arg array. 379 * 380 * Returns: 381 * DCMD_USAGE, or DCMD_OK 382 * 383 * Context: 384 * User context. 385 * 386 */ 387 /*ARGSUSED*/ 388 static int 389 qlcver_dcmd(uintptr_t addr, uint_t flags, int argc, const mdb_arg_t *argv) 390 { 391 int8_t qlcversion[100]; 392 struct fw_table fw_table[10], *fwt = NULL; 393 uint8_t *fwverptr = NULL; 394 ql_head_t ql_hba; 395 uint32_t found = 0; 396 397 if ((flags & DCMD_ADDRSPEC) || argc != 0) { 398 return (DCMD_USAGE); 399 } 400 401 if (mdb_readvar(&qlcversion, "qlc_driver_version") == -1) { 402 mdb_warn("unable to read qlc driver version\n"); 403 } else { 404 mdb_printf("\n%s version currently loaded is: %s\n", 405 QL_NAME, qlcversion); 406 } 407 408 mdb_printf("qlc mdb library compiled with %s version: %s\n", 409 QL_NAME, QL_VERSION); 410 411 if ((fwverptr = (uint8_t *)(mdb_alloc(50, UM_SLEEP))) == NULL) { 412 mdb_warn("unable to alloc fwverptr\n"); 413 return (DCMD_OK); 414 } 415 416 if (mdb_readvar(&fw_table, "fw_table") == -1) { 417 mdb_warn("unable to read firmware table\n"); 418 } else { 419 ql_adapter_state_t *qlstate; 420 uintptr_t hbaptr = 0; 421 422 if (mdb_readvar(&ql_hba, "ql_hba") == -1) { 423 mdb_warn("failed to read ql_hba structure"); 424 return (DCMD_ERR); 425 } 426 427 if ((qlstate = (ql_adapter_state_t *)mdb_alloc( 428 sizeof (ql_adapter_state_t), UM_SLEEP)) == NULL) { 429 mdb_warn("Unable to allocate memory for " 430 "ql_adapter_state\n"); 431 return (DCMD_OK); 432 } 433 434 mdb_printf("\n%-8s%-11s%s\n", "f/w", "compiled", "loaded"); 435 mdb_printf("%<u>%-8s%-11s%-13s%s%</u>\n\n", "class", "version", 436 "version", "instance list"); 437 438 for (fwt = &fw_table[0]; fwt->fw_class; fwt++) { 439 440 if (mdb_vread(fwverptr, sizeof (void *), 441 (uintptr_t)fwt->fw_version) == -1) { 442 mdb_warn("unable to read fwverptr\n"); 443 mdb_free(fwverptr, sizeof (void *)); 444 mdb_free(qlstate, sizeof (ql_adapter_state_t)); 445 return (DCMD_OK); 446 } 447 448 mdb_printf("%x\t%-11s", fwt->fw_class, fwverptr); 449 450 if (&ql_hba == NULL) { 451 mdb_warn("failed to read ql_hba structure"); 452 hbaptr = 0; 453 } else { 454 hbaptr = (uintptr_t)ql_hba.first; 455 } 456 457 found = 0; 458 while (hbaptr != 0) { 459 460 if (mdb_vread(qlstate, 461 sizeof (ql_adapter_state_t), hbaptr) == 462 -1) { 463 mdb_warn("failed to read " 464 "ql_adapter_state at %p", hbaptr); 465 break; 466 } 467 468 if (qlstate->fw_class == fwt->fw_class) { 469 if (found == 0) { 470 mdb_printf("%x.%02x.%02x\t", 471 qlstate->fw_major_version, 472 qlstate->fw_minor_version, 473 qlstate-> 474 fw_subminor_version); 475 mdb_printf("%d", 476 qlstate->instance); 477 } else { 478 mdb_printf(", %d", 479 qlstate->instance); 480 } 481 found = 1; 482 } 483 484 hbaptr = (uintptr_t)qlstate->hba.next; 485 } 486 487 if (found == 1) { 488 mdb_printf("\n"); 489 } else { 490 mdb_printf("not loaded\n"); 491 } 492 } 493 494 mdb_free(qlstate, sizeof (ql_adapter_state_t)); 495 mdb_free(fwverptr, sizeof (void *)); 496 } 497 498 return (DCMD_OK); 499 } 500 501 /* 502 * qlc_el_dcmd 503 * mdb dcmd which turns the extended logging bit on or off 504 * for the specificed qlc instance(s). 505 * 506 * Input: 507 * addr = User supplied address -- error if supplied. 508 * flags = mdb flags. 509 * argc = Number of user supplied args -- error if non-zero. 510 * argv = Arg array. 511 * 512 * Returns: 513 * DCMD_USAGE, or DCMD_OK 514 * 515 * Context: 516 * User context. 517 * 518 */ 519 /*ARGSUSED*/ 520 static int 521 qlc_el_dcmd(uintptr_t addr, uint_t flags, int argc, const mdb_arg_t *argv) 522 { 523 int8_t qlcversion[100]; 524 boolean_t elswitch; 525 uint32_t argcnt; 526 int mdbs; 527 uint32_t instance; 528 uint32_t qlsize = sizeof (ql_adapter_state_t); 529 ql_adapter_state_t *qlstate; 530 uintptr_t hbaptr = 0; 531 ql_head_t ql_hba; 532 533 if ((mdbs = mdb_get_state()) == MDB_STATE_DEAD) { 534 mdb_warn("Cannot change core file data (state=%xh)\n", mdbs); 535 return (DCMD_OK); 536 } 537 538 if ((flags & DCMD_ADDRSPEC) || argc < 2) { 539 return (DCMD_USAGE); 540 } 541 542 /* 543 * Check and make sure the driver version and the mdb versions 544 * match so all the structures and flags line up 545 */ 546 547 if (mdb_readvar(&qlcversion, "qlc_driver_version") == -1) { 548 mdb_warn("unable to read qlc driver version\n"); 549 return (DCMD_OK); 550 } 551 552 if ((strcmp(QL_VERSION, (const char *)&qlcversion)) != 0) { 553 mdb_warn("Error: qlc driver/qlc mdb version mismatch\n"); 554 mdb_printf("\tqlc mdb library compiled version is: %s\n", 555 QL_VERSION); 556 mdb_printf("\tqlc driver version is: %s\n", qlcversion); 557 558 return (DCMD_OK); 559 } 560 561 if ((strcasecmp(argv[0].a_un.a_str, "on")) == 0) { 562 elswitch = TRUE; 563 } else if ((strcasecmp(argv[0].a_un.a_str, "off")) == 0) { 564 elswitch = FALSE; 565 } else { 566 return (DCMD_USAGE); 567 } 568 569 if (mdb_readvar(&ql_hba, "ql_hba") == -1) { 570 mdb_warn("failed to read ql_hba structure"); 571 return (DCMD_ERR); 572 } 573 574 if (&ql_hba == NULL) { 575 mdb_warn("failed to read ql_hba structure - is qlc loaded?"); 576 return (DCMD_ERR); 577 } 578 579 if ((qlstate = (ql_adapter_state_t *)mdb_alloc(qlsize, 580 UM_SLEEP)) == NULL) { 581 mdb_warn("Unable to allocate memory for " 582 "ql_adapter_state\n"); 583 return (DCMD_OK); 584 } 585 586 if ((strcasecmp(argv[1].a_un.a_str, "all")) == 0) { 587 588 if (argc != 2) { 589 mdb_free(qlstate, qlsize); 590 return (DCMD_USAGE); 591 } 592 593 hbaptr = (uintptr_t)ql_hba.first; 594 595 while (hbaptr != 0) { 596 597 if (mdb_vread(qlstate, qlsize, hbaptr) == -1) { 598 mdb_free(qlstate, qlsize); 599 mdb_warn("failed to read ql_adapter_state " 600 "at %p", hbaptr); 601 return (DCMD_OK); 602 } 603 604 ql_elog_common(qlstate, elswitch); 605 606 hbaptr = (uintptr_t)qlstate->hba.next; 607 } 608 } else { 609 for (argcnt = 1; argcnt < argc; argcnt++) { 610 611 instance = (uint32_t)mdb_strtoull( 612 argv[argcnt].a_un.a_str); 613 614 /* find the correct instance to change */ 615 hbaptr = (uintptr_t)ql_hba.first; 616 while (hbaptr != 0) { 617 618 if (mdb_vread(qlstate, qlsize, hbaptr) == -1) { 619 mdb_free(qlstate, qlsize); 620 mdb_warn("failed to read " 621 "ql_adapter_state at %p", hbaptr); 622 return (DCMD_OK); 623 } 624 625 if (qlstate->instance == instance) { 626 break; 627 } 628 629 hbaptr = (uintptr_t)qlstate->hba.next; 630 } 631 632 if (hbaptr == 0) { 633 mdb_printf("instance %d is not loaded", 634 instance); 635 continue; 636 } 637 638 ql_elog_common(qlstate, elswitch); 639 } 640 } 641 642 mdb_free(qlstate, qlsize); 643 644 return (DCMD_OK); 645 } 646 647 /* 648 * qlc_elog_common 649 * mdb helper function which set/resets the extended logging bit 650 * 651 * Input: 652 * qlstate = adapter state structure 653 * elswitch = boolean which specifies to reset (0) or set (1) the 654 * extended logging bit. 655 * 656 * Returns: 657 * 658 * Context: 659 * User context. 660 * 661 */ 662 static void 663 ql_elog_common(ql_adapter_state_t *qlstate, boolean_t elswitch) 664 { 665 uintptr_t hbaptr = (uintptr_t)qlstate->hba.base_address; 666 size_t qlsize = sizeof (ql_adapter_state_t); 667 668 if (elswitch) { 669 if ((qlstate->cfg_flags & CFG_ENABLE_EXTENDED_LOGGING) == 0) { 670 671 qlstate->cfg_flags |= CFG_ENABLE_EXTENDED_LOGGING; 672 673 if ((mdb_vwrite((const void *)qlstate, qlsize, 674 hbaptr)) != (ssize_t)qlsize) { 675 mdb_warn("instance %d - unable to update", 676 qlstate->instance); 677 } else { 678 mdb_printf("instance %d extended logging is " 679 "now on\n", qlstate->instance); 680 } 681 } else { 682 mdb_printf("instance %d extended logging is " 683 "already on\n", qlstate->instance); 684 } 685 } else { 686 if ((qlstate->cfg_flags & CFG_ENABLE_EXTENDED_LOGGING) != 0) { 687 688 qlstate->cfg_flags &= ~CFG_ENABLE_EXTENDED_LOGGING; 689 690 if ((mdb_vwrite((const void *)qlstate, qlsize, 691 hbaptr)) != (ssize_t)qlsize) { 692 mdb_warn("instance %d - unable to update", 693 qlstate->instance); 694 } else { 695 mdb_printf("instance %d extended logging is " 696 "now off\n", qlstate->instance); 697 } 698 } else { 699 mdb_printf("instance %d extended logging is " 700 "already off\n", qlstate->instance); 701 } 702 } 703 } 704 705 /* 706 * qlc_ocs_dcmd 707 * mdb dcmd which prints out the outstanding command array using 708 * caller supplied address (which sb the ha structure). 709 * 710 * Input: 711 * addr = User supplied ha address. 712 * flags = mdb flags. 713 * argc = Number of user supplied args. 714 * argv = Arg array. 715 * 716 * Returns: 717 * DCMD_USAGE, or DCMD_OK 718 * 719 * Context: 720 * User context. 721 * 722 * 723 */ 724 static int 725 /*ARGSUSED*/ 726 qlc_osc_dcmd(uintptr_t addr, uint_t flags, int argc, const mdb_arg_t *argv) 727 { 728 ql_adapter_state_t *qlstate; 729 uintptr_t qlosc, ptr1; 730 uint32_t indx, found = 0; 731 ql_srb_t *qlsrb; 732 733 if (!(flags & DCMD_ADDRSPEC)) { 734 return (DCMD_USAGE); 735 } 736 737 if ((qlstate = (ql_adapter_state_t *) 738 mdb_alloc(sizeof (ql_adapter_state_t), UM_SLEEP)) == NULL) { 739 mdb_warn("Unable to allocate memory for ql_adapter_state\n"); 740 return (DCMD_OK); 741 } 742 if (mdb_vread(qlstate, sizeof (ql_adapter_state_t), addr) == -1) { 743 mdb_free(qlstate, sizeof (ql_adapter_state_t)); 744 mdb_warn("failed to read ql_adapter_state at %p", addr); 745 return (DCMD_OK); 746 } 747 748 qlosc = (uintptr_t)qlstate->outstanding_cmds; 749 mdb_printf("qlc instance: %d, base addr = %llx, osc base = %p\n", 750 qlstate->instance, qlstate->hba.base_address, qlosc); 751 752 if ((qlsrb = (ql_srb_t *)mdb_alloc(sizeof (ql_srb_t), UM_SLEEP)) == 753 NULL) { 754 mdb_free(qlstate, sizeof (ql_adapter_state_t)); 755 mdb_warn("failed to allocate space for srb_t\n"); 756 return (DCMD_OK); 757 } 758 for (indx = 0; indx < MAX_OUTSTANDING_COMMANDS; indx++, qlosc += 8) { 759 if (mdb_vread(&ptr1, 8, qlosc) == -1) { 760 mdb_warn("failed to read ptr1, indx=%d", indx); 761 break; 762 } 763 if (ptr1 == 0) { 764 continue; 765 } 766 767 mdb_printf("osc ptr = %p, indx = %xh\n", ptr1, indx); 768 769 if (mdb_vread(qlsrb, sizeof (ql_srb_t), ptr1) == -1) { 770 mdb_warn("failed to read ql_srb_t at %p", ptr1); 771 break; 772 } 773 (void) ql_doprint(ptr1, "struct ql_srb"); 774 found++; 775 } 776 777 mdb_free(qlsrb, sizeof (ql_srb_t)); 778 mdb_free(qlstate, sizeof (ql_adapter_state_t)); 779 780 mdb_printf("number of outstanding command srb's is: %d\n", found); 781 782 return (DCMD_OK); 783 } 784 785 /* 786 * qlc_wdog_dcmd 787 * mdb dcmd which prints out the commands which are linked 788 * on the watchdog linked list. Caller supplied address (which 789 * sb the ha structure). 790 * 791 * Input: 792 * addr = User supplied ha address. 793 * flags = mdb flags. 794 * argc = Number of user supplied args. 795 * argv = Arg array. 796 * 797 * Returns: 798 * DCMD_USAGE, or DCMD_OK 799 * 800 * Context: 801 * User context. 802 * 803 * 804 */ 805 static int 806 /*ARGSUSED*/ 807 qlc_wdog_dcmd(uintptr_t addr, uint_t flags, int argc, const mdb_arg_t *argv) 808 { 809 ql_adapter_state_t *qlstate; 810 uint16_t index, count; 811 ql_head_t *dev; 812 ql_srb_t *srb; 813 ql_tgt_t *tq; 814 ql_lun_t *lq; 815 ql_link_t *tqlink, *srblink, *lqlink; 816 int nextlink; 817 818 if (!(flags & DCMD_ADDRSPEC)) { 819 mdb_warn("Address required\n", addr); 820 return (DCMD_USAGE); 821 } 822 823 if ((qlstate = (ql_adapter_state_t *) 824 mdb_alloc(sizeof (ql_adapter_state_t), UM_SLEEP)) == NULL) { 825 mdb_warn("Unable to allocate memory for ql_adapter_state\n"); 826 return (DCMD_OK); 827 } 828 829 if (mdb_vread(qlstate, sizeof (ql_adapter_state_t), addr) == -1) { 830 mdb_free(qlstate, sizeof (ql_adapter_state_t)); 831 mdb_warn("failed to read ql_adapter_state at %p", addr); 832 return (DCMD_OK); 833 } 834 835 /* 836 * Read in the device array 837 */ 838 dev = (ql_head_t *) 839 mdb_alloc(sizeof (ql_head_t) * DEVICE_HEAD_LIST_SIZE, UM_SLEEP); 840 841 if (mdb_vread(dev, sizeof (ql_head_t) * DEVICE_HEAD_LIST_SIZE, 842 (uintptr_t)qlstate->dev) == -1) { 843 mdb_warn("failed to read ql_head_t (dev) at %p", qlstate->dev); 844 mdb_free(qlstate, sizeof (ql_adapter_state_t)); 845 mdb_free(dev, sizeof (ql_head_t) * DEVICE_HEAD_LIST_SIZE); 846 return (DCMD_OK); 847 } 848 849 tqlink = (ql_link_t *)mdb_alloc(sizeof (ql_link_t), UM_SLEEP); 850 tq = (ql_tgt_t *)mdb_alloc(sizeof (ql_tgt_t), UM_SLEEP); 851 lqlink = (ql_link_t *)mdb_alloc(sizeof (ql_link_t), UM_SLEEP); 852 lq = (ql_lun_t *)mdb_alloc(sizeof (ql_lun_t), UM_SLEEP); 853 srblink = (ql_link_t *)mdb_alloc(sizeof (ql_link_t), UM_SLEEP); 854 srb = (ql_srb_t *)mdb_alloc(sizeof (ql_srb_t), UM_SLEEP); 855 856 /* 857 * Validate the devices watchdog queue 858 */ 859 for (index = 0; index < DEVICE_HEAD_LIST_SIZE; index++) { 860 861 /* Skip empty ones */ 862 if (dev[index].first == NULL) { 863 continue; 864 } 865 866 mdb_printf("dev array index = %x\n", index); 867 868 /* Loop through targets on device linked list */ 869 /* get the first link */ 870 871 nextlink = get_first_link(&dev[index], tqlink); 872 873 /* 874 * traverse the targets linked list at this device array index. 875 */ 876 while (nextlink == DCMD_OK) { 877 /* Get the target */ 878 if (mdb_vread(tq, sizeof (ql_tgt_t), 879 (uintptr_t)(tqlink->base_address)) == -1) { 880 mdb_warn("failed to read ql_tgt at %p", 881 tqlink->base_address); 882 break; 883 } 884 mdb_printf("tgt q base = %llx, ", 885 tqlink->base_address); 886 887 mdb_printf("flags: (%xh)", tq->flags); 888 889 if (tq->flags) { 890 ql_dump_flags((uint64_t)tq->flags, qltgt_flags); 891 } 892 893 mdb_printf("tgt: %02x%02x%02x%02x%02x%02x%02x%02x ", 894 tq->node_name[0], tq->node_name[1], 895 tq->node_name[2], tq->node_name[3], 896 tq->node_name[4], tq->node_name[5], 897 tq->node_name[6], tq->node_name[7]); 898 899 /* 900 * Loop through commands on this targets watchdog queue. 901 */ 902 903 /* Get the first link on the targets cmd wdg q. */ 904 if (tq->wdg.first == NULL) { 905 mdb_printf(" watchdog list empty "); 906 break; 907 } else { 908 if (mdb_vread(srblink, sizeof (ql_link_t), 909 (uintptr_t)tq->wdg.first) == -1) { 910 mdb_warn("failed to read ql_link_t" 911 " at %p", tq->wdg.first); 912 break; 913 } 914 /* There is aleast one. */ 915 count = 1; 916 /* 917 * Count the remaining items in the 918 * cmd watchdog list. 919 */ 920 while (srblink->next != NULL) { 921 /* Read in the next ql_link_t header */ 922 if (mdb_vread(srblink, 923 sizeof (ql_link_t), 924 (uintptr_t)srblink->next) == -1) { 925 mdb_warn("failed to read" 926 " ql_link_t next at %p", 927 srblink->next); 928 break; 929 } 930 count = (uint16_t)(count + 1); 931 } 932 mdb_printf(" watchdog list: %d entries\n", 933 count); 934 /* get the first one again */ 935 if (mdb_vread(srblink, sizeof (ql_link_t), 936 (uintptr_t)tq->wdg.first) == -1) { 937 mdb_warn("failed to read ql_link_t" 938 " at %p", tq->wdg.first); 939 break; 940 } 941 } 942 /* 943 * Traverse the targets cmd watchdog linked list 944 * verifying srb's from the list are on a lun cmd list. 945 */ 946 while (nextlink == DCMD_OK) { 947 int found = 0; 948 /* get the srb */ 949 if (mdb_vread(srb, sizeof (ql_srb_t), 950 (uintptr_t)srblink->base_address) == -1) { 951 mdb_warn("failed to read ql_srb_t" 952 " at %p", srblink->base_address); 953 break; 954 } 955 mdb_printf("ql_srb %llx ", 956 srblink->base_address); 957 958 /* 959 * Get the lun q the srb is on 960 */ 961 if (mdb_vread(lq, sizeof (ql_lun_t), 962 (uintptr_t)srb->lun_queue) == -1) { 963 mdb_warn("failed to read ql_srb_t" 964 " at %p", srb->lun_queue); 965 break; 966 } 967 nextlink = get_first_link(&lq->cmd, lqlink); 968 /* 969 * traverse the lun cmd linked list looking 970 * for the srb from the targets watchdog list 971 */ 972 while (nextlink == DCMD_OK) { 973 if (srblink->base_address == 974 lqlink->base_address) { 975 mdb_printf("on lun %d cmd q\n", 976 lq->lun_no); 977 found = 1; 978 break; 979 } 980 /* get next item on lun cmd list */ 981 nextlink = get_next_link(lqlink); 982 } 983 if (!found) { 984 mdb_printf("not found on lun cmd q\n"); 985 } 986 /* get next item in the watchdog list */ 987 nextlink = get_next_link(srblink); 988 } /* End targets command watchdog list */ 989 /* get next item in this target list */ 990 nextlink = get_next_link(tqlink); 991 } /* End traverse the device targets linked list */ 992 mdb_printf("\n"); 993 } /* End device array */ 994 995 mdb_free(tq, sizeof (ql_tgt_t)); 996 mdb_free(lq, sizeof (ql_lun_t)); 997 mdb_free(srb, sizeof (ql_srb_t)); 998 mdb_free(tqlink, sizeof (ql_link_t)); 999 mdb_free(srblink, sizeof (ql_link_t)); 1000 mdb_free(lqlink, sizeof (ql_link_t)); 1001 mdb_free(qlstate, sizeof (ql_adapter_state_t)); 1002 mdb_free(dev, sizeof (ql_head_t)*DEVICE_HEAD_LIST_SIZE); 1003 1004 return (DCMD_OK); 1005 } 1006 1007 /* 1008 * get_first_link 1009 * Gets the first ql_link_t header on ql_head. 1010 * 1011 * Input: 1012 * ql_head = pointer to a ql_head_t structure. 1013 * ql_link = pointer to a ql_link_t structure. 1014 * 1015 * Returns: 1016 * DCMD_ABORT, or DCMD_OK 1017 * 1018 * Context: 1019 * User context. 1020 * 1021 */ 1022 static int 1023 get_first_link(ql_head_t *qlhead, ql_link_t *qllink) 1024 { 1025 int rval = DCMD_ABORT; 1026 1027 if (qlhead != NULL) { 1028 if (qlhead->first != NULL) { 1029 /* Read in the first ql_link_t header */ 1030 if (mdb_vread(qllink, sizeof (ql_link_t), 1031 (uintptr_t)(qlhead->first)) == -1) { 1032 mdb_warn("failed to read ql_link_t " 1033 "next at %p", qlhead->first); 1034 } else { 1035 rval = DCMD_OK; 1036 } 1037 } 1038 } 1039 return (rval); 1040 } 1041 1042 /* 1043 * get_next_link 1044 * Gets the next ql_link_t structure. 1045 * 1046 * Input: 1047 * ql_link = pointer to a ql_link_t structure. 1048 * 1049 * Returns: 1050 * DCMD_ABORT, or DCMD_OK 1051 * 1052 * Context: 1053 * User context. 1054 * 1055 */ 1056 static int 1057 get_next_link(ql_link_t *qllink) 1058 { 1059 int rval = DCMD_ABORT; 1060 1061 if (qllink != NULL) { 1062 if (qllink->next != NULL) { 1063 /* Read in the next ql_link_t header */ 1064 if (mdb_vread(qllink, sizeof (ql_link_t), 1065 (uintptr_t)(qllink->next)) == -1) { 1066 mdb_warn("failed to read ql_link_t " 1067 "next at %p", qllink->next); 1068 } else { 1069 rval = DCMD_OK; 1070 } 1071 } 1072 } 1073 return (rval); 1074 } 1075 1076 /* 1077 * qlcstate_dcmd 1078 * mdb dcmd which prints out the ql_state info using 1079 * caller supplied address. 1080 * 1081 * Input: 1082 * addr = User supplied address. 1083 * flags = mdb flags. 1084 * argc = Number of user supplied args. 1085 * argv = Arg array. 1086 * 1087 * Returns: 1088 * DCMD_USAGE, or DCMD_OK 1089 * 1090 * Context: 1091 * User context. 1092 * 1093 */ 1094 static int 1095 qlcstate_dcmd(uintptr_t addr, uint_t flags, int argc, const mdb_arg_t *argv) 1096 { 1097 ql_adapter_state_t *qlstate; 1098 int verbose = 0; 1099 1100 if (!(flags & DCMD_ADDRSPEC)) { 1101 return (DCMD_USAGE); 1102 } 1103 1104 if (mdb_getopts(argc, argv, 'v', MDB_OPT_SETBITS, TRUE, &verbose, 1105 NULL) != argc) { 1106 return (DCMD_USAGE); 1107 } 1108 1109 if ((qlstate = (ql_adapter_state_t *) 1110 mdb_alloc(sizeof (ql_adapter_state_t), UM_SLEEP)) == NULL) { 1111 mdb_warn("failed to allocate memory for ql_adapter_state\n"); 1112 return (DCMD_OK); 1113 } 1114 if (mdb_vread(qlstate, sizeof (ql_adapter_state_t), addr) == -1) { 1115 mdb_free(qlstate, sizeof (ql_adapter_state_t)); 1116 mdb_warn("failed to read ql_adapter_state at %p", addr); 1117 return (DCMD_OK); 1118 } 1119 1120 mdb_printf("qlc instance: %d, base addr = %llx\n", qlstate->instance, 1121 addr); 1122 1123 mdb_printf("\nadapter state flags:\n"); 1124 ql_dump_flags((uint64_t)qlstate->flags, adapter_state_flags); 1125 mdb_printf("\nadapter cfg flags:\n"); 1126 ql_dump_flags((uint64_t)qlstate->cfg_flags, adapter_config_flags); 1127 mdb_printf("\ntask daemon state flags:\n"); 1128 ql_dump_flags((uint64_t)qlstate->task_daemon_flags, 1129 task_daemon_flags); 1130 1131 if (verbose) { 1132 (void) ql_doprint(addr, "struct ql_adapter_state"); 1133 } 1134 1135 mdb_free(qlstate, sizeof (ql_adapter_state_t)); 1136 1137 return (DCMD_OK); 1138 } 1139 1140 /* 1141 * qlcstates_walk_init 1142 * mdb walker init which prints out all qlc states info. 1143 * 1144 * Input: 1145 * wsp - Pointer to walker state struct 1146 * 1147 * Returns: 1148 * WALK_ERR, or WALK_NEXT 1149 * 1150 * Context: 1151 * User context. 1152 * 1153 */ 1154 static int 1155 qlstates_walk_init(mdb_walk_state_t *wsp) 1156 { 1157 ql_head_t ql_hba; 1158 1159 if (wsp->walk_addr == 0) { 1160 if ((mdb_readvar(&ql_hba, "ql_hba") == -1) || 1161 (&ql_hba == NULL)) { 1162 mdb_warn("failed to read ql_hba structure"); 1163 return (WALK_ERR); 1164 } 1165 1166 wsp->walk_addr = (uintptr_t)ql_hba.first; 1167 wsp->walk_data = mdb_alloc(sizeof (ql_adapter_state_t), 1168 UM_SLEEP); 1169 return (WALK_NEXT); 1170 } else { 1171 return (ql_doprint(wsp->walk_addr, "struct ql_adapter_state")); 1172 } 1173 } 1174 1175 /* 1176 * qlstates_walk_step 1177 * mdb walker step which prints out all qlc states info. 1178 * 1179 * Input: 1180 * wsp - Pointer to walker state struct 1181 * 1182 * Returns: 1183 * WALK_DONE, or WALK_NEXT 1184 * 1185 * Context: 1186 * User context. 1187 * 1188 */ 1189 static int 1190 qlstates_walk_step(mdb_walk_state_t *wsp) 1191 { 1192 ql_adapter_state_t *qlstate; 1193 1194 if (wsp->walk_addr == 0) { 1195 return (WALK_DONE); 1196 } 1197 1198 if (mdb_vread(wsp->walk_data, sizeof (ql_adapter_state_t), 1199 wsp->walk_addr) == -1) { 1200 mdb_warn("failed to read ql_adapter_state at %p", 1201 wsp->walk_addr); 1202 return (WALK_DONE); 1203 } 1204 1205 qlstate = (ql_adapter_state_t *)(wsp->walk_data); 1206 mdb_printf("qlc instance: %d, base addr = %llx\n", 1207 qlstate->instance, wsp->walk_addr); 1208 1209 mdb_printf("\nadapter state flags:\n"); 1210 ql_dump_flags((uint64_t)qlstate->flags, adapter_state_flags); 1211 mdb_printf("\nadapter cfg flags:\n"); 1212 ql_dump_flags((uint64_t)qlstate->cfg_flags, adapter_config_flags); 1213 mdb_printf("\ntask daemon state flags:\n"); 1214 ql_dump_flags((uint64_t)qlstate->task_daemon_flags, 1215 task_daemon_flags); 1216 1217 mdb_printf("\nadapter state:\n"); 1218 (void) ql_doprint(wsp->walk_addr, "struct ql_adapter_state"); 1219 1220 mdb_printf("\n"); 1221 1222 wsp->walk_addr = (uintptr_t) 1223 (((ql_adapter_state_t *)wsp->walk_data)->hba.next); 1224 1225 return (WALK_NEXT); 1226 } 1227 1228 /* 1229 * qlstates_walk_fini 1230 * mdb walker fini which wraps up the walker 1231 * 1232 * Input: 1233 * wsp - Pointer to walker state struct 1234 * 1235 * Returns: 1236 * 1237 * Context: 1238 * User context. 1239 * 1240 */ 1241 static void 1242 qlstates_walk_fini(mdb_walk_state_t *wsp) 1243 { 1244 mdb_free(wsp->walk_data, sizeof (ql_adapter_state_t)); 1245 } 1246 1247 /* 1248 * qlsrb_walk_init 1249 * mdb walker init which prints out linked srb's 1250 * 1251 * Input: 1252 * wsp - Pointer to walker ql_srb struct 1253 * 1254 * Returns: 1255 * WALK_ERR, or WALK_NEXT 1256 * 1257 * Context: 1258 * User context. 1259 * 1260 */ 1261 static int 1262 qlsrb_walk_init(mdb_walk_state_t *wsp) 1263 { 1264 if (wsp->walk_addr == 0) { 1265 mdb_warn("failed to read ql_srb addr at %p", 1266 wsp->walk_addr); 1267 return (WALK_ERR); 1268 } 1269 1270 wsp->walk_data = mdb_alloc(sizeof (ql_srb_t), UM_SLEEP); 1271 1272 return (WALK_NEXT); 1273 } 1274 1275 /* 1276 * qlcsrb_walk_step 1277 * mdb walker step which prints out linked ql_srb structures 1278 * 1279 * Input: 1280 * wsp - Pointer to walker srb struct 1281 * 1282 * Returns: 1283 * WALK_DONE, or WALK_NEXT 1284 * 1285 * Context: 1286 * User context. 1287 * 1288 */ 1289 static int 1290 qlsrb_walk_step(mdb_walk_state_t *wsp) 1291 { 1292 ql_srb_t *qlsrb; 1293 1294 if (wsp->walk_addr == 0) 1295 return (WALK_DONE); 1296 1297 if (mdb_vread(wsp->walk_data, sizeof (ql_srb_t), 1298 wsp->walk_addr) == -1) { 1299 mdb_warn("failed to read ql_srb at %p", wsp->walk_addr); 1300 return (WALK_DONE); 1301 } 1302 1303 qlsrb = (ql_srb_t *)(wsp->walk_data); 1304 mdb_printf("ql_srb base addr = %llx\n", wsp->walk_addr); 1305 1306 mdb_printf("\nql_srb flags:\n"); 1307 ql_dump_flags((uint64_t)qlsrb->flags, qlsrb_flags); 1308 1309 mdb_printf("\nql_srb:\n"); 1310 (void) ql_doprint(wsp->walk_addr, "struct ql_srb"); 1311 1312 mdb_printf("\n"); 1313 1314 wsp->walk_addr = (uintptr_t) 1315 (((ql_srb_t *)wsp->walk_data)->cmd.next); 1316 1317 return (WALK_NEXT); 1318 } 1319 1320 /* 1321 * qlsrb_walk_fini 1322 * mdb walker fini which wraps up the walker 1323 * 1324 * Input: 1325 * wsp - Pointer to walker state struct 1326 * 1327 * Returns: 1328 * 1329 * Context: 1330 * User context. 1331 * 1332 */ 1333 static void 1334 qlsrb_walk_fini(mdb_walk_state_t *wsp) 1335 { 1336 mdb_free(wsp->walk_data, sizeof (ql_srb_t)); 1337 } 1338 1339 /* 1340 * qllunq_dcmd 1341 * mdb walker which prints out lun q's 1342 * 1343 * Input: 1344 * wsp - Pointer to walker ql_lun struct 1345 * 1346 * Returns: 1347 * WALK_ERR, or WALK_NEXT 1348 * 1349 * Context: 1350 * User context. 1351 * 1352 */ 1353 static int 1354 qllunq_walk_init(mdb_walk_state_t *wsp) 1355 { 1356 if (wsp->walk_addr == 0) { 1357 mdb_warn("failed to read ql_lun addr at %p", 1358 wsp->walk_addr); 1359 return (WALK_ERR); 1360 } 1361 1362 wsp->walk_data = mdb_alloc(sizeof (ql_lun_t), UM_SLEEP); 1363 1364 return (WALK_NEXT); 1365 } 1366 1367 /* 1368 * qlclunq_walk_step 1369 * mdb walker step which prints out linked ql_lun structures 1370 * 1371 * Input: 1372 * wsp - Pointer to walker srb struct 1373 * 1374 * Returns: 1375 * WALK_DONE, or WALK_NEXT 1376 * 1377 * Context: 1378 * User context. 1379 * 1380 */ 1381 static int 1382 qllunq_walk_step(mdb_walk_state_t *wsp) 1383 { 1384 ql_lun_t *qllun; 1385 ql_link_t ql_link; 1386 ql_link_t *qllink; 1387 1388 if (wsp->walk_addr == 0) 1389 return (WALK_DONE); 1390 1391 if (mdb_vread(wsp->walk_data, sizeof (ql_lun_t), 1392 wsp->walk_addr) == -1) { 1393 mdb_warn("failed to read ql_lun at %p", wsp->walk_addr); 1394 return (WALK_DONE); 1395 } 1396 1397 qllun = (ql_lun_t *)(wsp->walk_data); 1398 mdb_printf("ql_lun base addr = %llx\n", wsp->walk_addr); 1399 1400 mdb_printf("\nql_lun flags:\n"); 1401 ql_dump_flags((uint64_t)qllun->flags, qllun_flags); 1402 1403 mdb_printf("\nql_lun:\n"); 1404 (void) ql_doprint(wsp->walk_addr, "struct ql_lun"); 1405 1406 mdb_printf("\n"); 1407 1408 qllink = (ql_link_t *) 1409 (((ql_lun_t *)wsp->walk_data)->link.next); 1410 1411 if (qllink == NULL) { 1412 return (WALK_DONE); 1413 } else { 1414 /* 1415 * Read in the next link_t header 1416 */ 1417 if (mdb_vread(&ql_link, sizeof (ql_link_t), 1418 (uintptr_t)qllink) == -1) { 1419 mdb_warn("failed to read ql_link_t " 1420 "next at %p", qllink->next); 1421 return (WALK_DONE); 1422 } 1423 qllink = &ql_link; 1424 } 1425 1426 wsp->walk_addr = (uintptr_t)qllink->base_address; 1427 1428 return (WALK_NEXT); 1429 } 1430 1431 /* 1432 * qllunq_walk_fini 1433 * mdb walker fini which wraps up the walker 1434 * 1435 * Input: 1436 * wsp - Pointer to walker state struct 1437 * 1438 * Returns: 1439 * 1440 * Context: 1441 * User context. 1442 * 1443 */ 1444 static void 1445 qllunq_walk_fini(mdb_walk_state_t *wsp) 1446 { 1447 mdb_free(wsp->walk_data, sizeof (ql_lun_t)); 1448 } 1449 1450 /* 1451 * qltgtq_dcmd 1452 * mdb dcmd which prints out an hs's tq struct info. 1453 * 1454 * Input: 1455 * addr = User supplied address. (NB: nust be an ha) 1456 * flags = mdb flags. 1457 * argc = Number of user supplied args. 1458 * argv = Arg array. 1459 * 1460 * Returns: 1461 * DCMD_USAGE, or DCMD_OK 1462 * 1463 * Context: 1464 * User context. 1465 * 1466 */ 1467 /*ARGSUSED*/ 1468 static int 1469 qltgtq_dcmd(uintptr_t addr, uint_t flags, int argc, const mdb_arg_t *argv) 1470 { 1471 ql_adapter_state_t *ha; 1472 ql_link_t *link; 1473 ql_tgt_t *tq; 1474 uint32_t index; 1475 ql_head_t *dev; 1476 1477 if ((!(flags & DCMD_ADDRSPEC)) || addr == 0) { 1478 mdb_warn("ql_hba structure addr is required"); 1479 return (DCMD_USAGE); 1480 } 1481 1482 /* 1483 * Get the adapter state struct which was passed 1484 */ 1485 1486 ha = (ql_adapter_state_t *)mdb_alloc(sizeof (ql_adapter_state_t), 1487 UM_SLEEP); 1488 1489 if (mdb_vread(ha, sizeof (ql_adapter_state_t), addr) == -1) { 1490 mdb_warn("failed to read ql_adapter_state at %p", addr); 1491 mdb_free(ha, sizeof (ql_adapter_state_t)); 1492 return (DCMD_OK); 1493 } 1494 1495 if (ha->dev == NULL) { 1496 mdb_warn("dev ptr is NULL for ha: %p", addr); 1497 mdb_free(ha, sizeof (ql_adapter_state_t)); 1498 return (DCMD_OK); 1499 } 1500 1501 /* 1502 * Read in the device array 1503 */ 1504 dev = (ql_head_t *) 1505 mdb_alloc(sizeof (ql_head_t) * DEVICE_HEAD_LIST_SIZE, UM_SLEEP); 1506 1507 if (mdb_vread(dev, sizeof (ql_head_t) * DEVICE_HEAD_LIST_SIZE, 1508 (uintptr_t)ha->dev) == -1) { 1509 mdb_warn("failed to read ql_head_t (dev) at %p", ha->dev); 1510 mdb_free(ha, sizeof (ql_adapter_state_t)); 1511 mdb_free(dev, sizeof (ql_head_t) * DEVICE_HEAD_LIST_SIZE); 1512 } 1513 1514 tq = (ql_tgt_t *)mdb_alloc(sizeof (ql_tgt_t), UM_SLEEP); 1515 link = (ql_link_t *)mdb_alloc(sizeof (ql_link_t), UM_SLEEP); 1516 1517 for (index = 0; index < DEVICE_HEAD_LIST_SIZE; index++) { 1518 1519 if (dev[index].first == NULL) { 1520 continue; 1521 } 1522 1523 if (mdb_vread(link, sizeof (ql_link_t), 1524 (uintptr_t)dev[index].first) == -1) { 1525 mdb_warn("failed to read ql_link_t at %p", 1526 dev[index].first); 1527 break; 1528 } 1529 1530 while (link != NULL) { 1531 if (mdb_vread(tq, sizeof (ql_tgt_t), 1532 (uintptr_t)(link->base_address)) == -1) { 1533 mdb_warn("failed to read ql_tgt at %p", 1534 link->base_address); 1535 break; 1536 } 1537 1538 mdb_printf("tgt queue base addr = %llx\n", 1539 link->base_address); 1540 1541 mdb_printf("\ntgt queue flags: (%xh)\n", tq->flags); 1542 ql_dump_flags((uint64_t)tq->flags, qltgt_flags); 1543 1544 mdb_printf("\ntgt queue:\n"); 1545 1546 (void) ql_doprint((uintptr_t)link->base_address, 1547 "struct ql_target"); 1548 1549 mdb_printf("\n"); 1550 1551 if (get_next_link(link) != DCMD_OK) { 1552 break; 1553 } 1554 } 1555 } 1556 1557 mdb_free(ha, sizeof (ql_adapter_state_t)); 1558 mdb_free(tq, sizeof (ql_tgt_t)); 1559 mdb_free(link, sizeof (ql_link_t)); 1560 mdb_free(dev, sizeof (ql_head_t)*DEVICE_HEAD_LIST_SIZE); 1561 1562 return (DCMD_OK); 1563 } 1564 1565 /* 1566 * ql_triggerdump_dcmd 1567 * Triggers the driver to take a firmware dump 1568 * 1569 * Input: 1570 * addr = User supplied address (optional) 1571 * flags = mdb flags. 1572 * argc = Number of user supplied args. 1573 * argv = Arg array (instance #, optional). 1574 * 1575 * Returns: 1576 * DCMD_OK or DCMD_ERR 1577 * 1578 * Context: 1579 * User context. 1580 * 1581 */ 1582 1583 #if 0 1584 1585 /*ARGSUSED*/ 1586 static int 1587 qlc_triggerdump_dcmd(uintptr_t addr, uint_t flags, int argc, 1588 const mdb_arg_t *argv) 1589 { 1590 ql_adapter_state_t *qlstate; 1591 uintptr_t hbaptr = NULL; 1592 ql_head_t ql_hba; 1593 uint32_t qlsize = sizeof (ql_adapter_state_t); 1594 int mdbs; 1595 1596 if ((mdbs = mdb_get_state()) == MDB_STATE_DEAD) { 1597 mdb_warn("Cannot change core file data (state=%xh)\n", mdbs); 1598 return (DCMD_OK); 1599 } 1600 1601 if ((qlstate = (ql_adapter_state_t *)mdb_alloc(qlsize, 1602 UM_SLEEP)) == NULL) { 1603 mdb_warn("Unable to allocate memory for ql_adapter_state\n"); 1604 return (DCMD_OK); 1605 } 1606 1607 if (addr == NULL) { 1608 char *tptr; 1609 uint32_t instance; 1610 1611 if (argc == 0) { 1612 mdb_warn("must specify either the ha addr or " 1613 "the instance number\n"); 1614 mdb_free(qlstate, qlsize); 1615 return (DCMD_OK); 1616 } 1617 1618 /* 1619 * find the specified instance in the ha list 1620 */ 1621 1622 instance = (uint32_t)strtol(argv[1].a_un.a_str, &tptr, 16); 1623 if (tptr == argv[1].a_un.a_str) { 1624 mdb_printf("instance # is illegal: '%s'\n", 1625 argv[1].a_un.a_str); 1626 mdb_free(qlstate, qlsize); 1627 return (DCMD_OK); 1628 } 1629 1630 if (mdb_readvar(&ql_hba, "ql_hba") == -1) { 1631 mdb_warn("failed to read ql_hba structure"); 1632 mdb_free(qlstate, qlsize); 1633 return (DCMD_ERR); 1634 } 1635 1636 if (&ql_hba == NULL) { 1637 mdb_warn("failed to read ql_hba structure - " 1638 "is qlc loaded?"); 1639 mdb_free(qlstate, qlsize); 1640 return (DCMD_ERR); 1641 } 1642 1643 hbaptr = (uintptr_t)ql_hba.first; 1644 while (hbaptr != NULL) { 1645 1646 if (mdb_vread(qlstate, qlsize, hbaptr) == -1) { 1647 mdb_free(qlstate, qlsize); 1648 mdb_warn("failed to read " 1649 "ql_adapter_state at %p", hbaptr); 1650 return (DCMD_OK); 1651 } 1652 1653 if (qlstate->instance == instance) { 1654 break; 1655 } 1656 1657 hbaptr = (uintptr_t)qlstate->hba.next; 1658 } 1659 } else { 1660 1661 /* 1662 * verify the addr specified 1663 */ 1664 1665 if (mdb_readvar(&ql_hba, "ql_hba") == -1) { 1666 mdb_warn("failed to read ql_hba structure"); 1667 mdb_free(qlstate, qlsize); 1668 return (DCMD_ERR); 1669 } 1670 1671 if (&ql_hba == NULL) { 1672 mdb_warn("failed to read ql_hba structure - " 1673 "is qlc loaded?"); 1674 mdb_free(qlstate, qlsize); 1675 return (DCMD_ERR); 1676 } 1677 1678 hbaptr = (uintptr_t)ql_hba.first; 1679 while (hbaptr != NULL) { 1680 1681 if (mdb_vread(qlstate, qlsize, hbaptr) == -1) { 1682 mdb_free(qlstate, qlsize); 1683 mdb_warn("failed to read " 1684 "ql_adapter_state at %p", hbaptr); 1685 return (DCMD_OK); 1686 } 1687 1688 if (hbaptr == addr) { 1689 break; 1690 } 1691 1692 hbaptr = (uintptr_t)qlstate->hba.next; 1693 } 1694 } 1695 1696 if (hbaptr == NULL) { 1697 mdb_free(qlstate, qlsize); 1698 if (argc == 0) { 1699 mdb_warn("addr specified is not in the hba list\n"); 1700 } else { 1701 mdb_warn("instance specified does not exist\n"); 1702 } 1703 return (DCMD_OK); 1704 } 1705 1706 if (((qlstate->ql_dump_state & QL_DUMP_VALID) != 0) || 1707 (qlstate->ql_dump_ptr != NULL)) { 1708 mdb_warn("instance %d already has a valid dump\n", 1709 qlstate->instance); 1710 mdb_free(qlstate, qlsize); 1711 return (DCMD_OK); 1712 } 1713 } 1714 #endif 1715 1716 /* 1717 * ql_getdump_dcmd 1718 * prints out the firmware dump buffer 1719 * 1720 * Input: 1721 * addr = User supplied address. (NB: must be an ha) 1722 * flags = mdb flags. 1723 * argc = Number of user supplied args. 1724 * argv = Arg array. 1725 * 1726 * Returns: 1727 * DCMD_OK or DCMD_ERR 1728 * 1729 * Context: 1730 * User context. 1731 * 1732 */ 1733 static int 1734 qlc_getdump_dcmd(uintptr_t addr, uint_t flags, int argc, const mdb_arg_t *argv) 1735 { 1736 ql_adapter_state_t *ha; 1737 ql_head_t ql_hba; 1738 uintptr_t hbaptr = 0; 1739 int verbose = 0; 1740 1741 if ((!(flags & DCMD_ADDRSPEC)) || addr == 0) { 1742 mdb_warn("ql_adapter_state structure addr is required"); 1743 return (DCMD_USAGE); 1744 } 1745 1746 if (mdb_getopts(argc, argv, 'v', MDB_OPT_SETBITS, TRUE, &verbose, 1747 NULL) != argc) { 1748 return (DCMD_USAGE); 1749 } 1750 1751 /* 1752 * Get the adapter state struct which was passed 1753 */ 1754 if ((ha = (ql_adapter_state_t *)mdb_alloc(sizeof (ql_adapter_state_t), 1755 UM_SLEEP)) == NULL) { 1756 mdb_warn("failed to allocate memory for ql_adapter_state\n"); 1757 return (DCMD_OK); 1758 } 1759 1760 /* 1761 * show user which instances have valid f/w dumps available if 1762 * user has specified verbose option 1763 */ 1764 if (mdb_readvar(&ql_hba, "ql_hba") == -1) { 1765 mdb_warn("failed to read ql_hba structure"); 1766 } else if (&ql_hba == NULL) { 1767 mdb_warn("failed to read ql_hba structure -- is qlc loaded?"); 1768 } else if (verbose) { 1769 hbaptr = (uintptr_t)ql_hba.first; 1770 while (hbaptr != 0) { 1771 1772 if (mdb_vread(ha, sizeof (ql_adapter_state_t), 1773 hbaptr) == -1) { 1774 mdb_free(ha, sizeof (ql_adapter_state_t)); 1775 mdb_warn("failed read ql_adapter_state at %p", 1776 hbaptr); 1777 return (DCMD_OK); 1778 } 1779 1780 mdb_printf("instance %d:\n", ha->instance); 1781 (void) mdb_inc_indent((ulong_t)4); 1782 1783 if (ha->ql_dump_state == 0) { 1784 mdb_printf("no dump flags\n"); 1785 } else { 1786 ql_dump_flags((uint64_t)ha->ql_dump_state, 1787 qldump_flags); 1788 } 1789 1790 if (ha->ql_dump_ptr == NULL) { 1791 mdb_printf("no dump address\n"); 1792 } else { 1793 mdb_printf("dump address is: %p\n", 1794 ha->ql_dump_ptr); 1795 } 1796 1797 (void) mdb_dec_indent((ulong_t)4); 1798 1799 hbaptr = (uintptr_t)ha->hba.next; 1800 } 1801 mdb_printf("\n"); 1802 } 1803 1804 if (mdb_vread(ha, sizeof (ql_adapter_state_t), addr) == -1) { 1805 mdb_warn("failed to read ql_adapter_state at %p", addr); 1806 mdb_free(ha, sizeof (ql_adapter_state_t)); 1807 return (DCMD_OK); 1808 } 1809 1810 /* 1811 * If its not a valid dump or there's not a f/w dump binary (???) 1812 * then bail out 1813 */ 1814 if (((ha->ql_dump_state & QL_DUMP_VALID) == 0) || 1815 (ha->ql_dump_ptr == NULL)) { 1816 mdb_warn("dump does not exist for instance %d (%x, %p)\n", 1817 ha->instance, ha->ql_dump_state, ha->ql_dump_ptr); 1818 mdb_free(ha, sizeof (ql_adapter_state_t)); 1819 return (DCMD_OK); 1820 } 1821 1822 if (CFG_IST(ha, CFG_CTRL_2422)) { 1823 (void) ql_24xx_dump_dcmd(ha, flags, argc, argv); 1824 } else if (CFG_IST(ha, CFG_CTRL_25XX)) { 1825 (void) ql_25xx_dump_dcmd(ha, flags, argc, argv); 1826 } else if (CFG_IST(ha, CFG_CTRL_81XX)) { 1827 (void) ql_81xx_dump_dcmd(ha, flags, argc, argv); 1828 } else if (!(CFG_IST(ha, CFG_CTRL_8021))) { 1829 (void) ql_23xx_dump_dcmd(ha, flags, argc, argv); 1830 } 1831 1832 mdb_free(ha, sizeof (ql_adapter_state_t)); 1833 1834 return (DCMD_OK); 1835 } 1836 1837 /* 1838 * ql_23xx_dump_dcmd 1839 * prints out a firmware dump buffer 1840 * 1841 * Input: 1842 * addr = User supplied address. (NB: nust be an ha) 1843 * flags = mdb flags. 1844 * argc = Number of user supplied args. 1845 * argv = Arg array. 1846 * 1847 * Returns: 1848 * DCMD_OK or DCMD_ERR 1849 * 1850 * Context: 1851 * User context. 1852 * 1853 */ 1854 /*ARGSUSED*/ 1855 static int 1856 ql_23xx_dump_dcmd(ql_adapter_state_t *ha, uint_t flags, int argc, 1857 const mdb_arg_t *argv) 1858 { 1859 ql_fw_dump_t *fw; 1860 uint32_t cnt = 0; 1861 int mbox_cnt; 1862 1863 fw = (ql_fw_dump_t *)mdb_alloc(ha->ql_dump_size, UM_SLEEP); 1864 1865 if (mdb_vread(fw, ha->ql_dump_size, 1866 (uintptr_t)ha->ql_dump_ptr) == -1) { 1867 mdb_warn("failed to read ql_dump_ptr (no f/w dump active?)"); 1868 mdb_free(fw, ha->ql_dump_size); 1869 return (DCMD_OK); 1870 } 1871 1872 if (ha->cfg_flags & CFG_CTRL_2300) { 1873 mdb_printf("\nISP 2300IP "); 1874 } else if (ha->cfg_flags & CFG_CTRL_6322) { 1875 mdb_printf("\nISP 6322FLX "); 1876 } else { 1877 mdb_printf("\nISP 2200IP "); 1878 } 1879 1880 mdb_printf("Firmware Version %d.%d.%d\n", 1881 ha->fw_major_version, ha->fw_minor_version, 1882 ha->fw_subminor_version); 1883 1884 mdb_printf("\nPBIU Registers:"); 1885 for (cnt = 0; cnt < sizeof (fw->pbiu_reg) / 2; cnt++) { 1886 if (cnt % 8 == 0) { 1887 mdb_printf("\n"); 1888 } 1889 mdb_printf("%04x ", fw->pbiu_reg[cnt]); 1890 } 1891 1892 if (ha->cfg_flags & (CFG_CTRL_2300 | CFG_CTRL_6322)) { 1893 mdb_printf("\n\nReqQ-RspQ-Risc2Host Status registers:"); 1894 for (cnt = 0; cnt < sizeof (fw->risc_host_reg) / 2; cnt++) { 1895 if (cnt % 8 == 0) { 1896 mdb_printf("\n"); 1897 } 1898 mdb_printf("%04x ", fw->risc_host_reg[cnt]); 1899 } 1900 } 1901 1902 mdb_printf("\n\nMailbox Registers:"); 1903 mbox_cnt = (ha->cfg_flags & (CFG_CTRL_2300 | CFG_CTRL_6322)) ? 16 : 8; 1904 for (cnt = 0; cnt < mbox_cnt; cnt++) { 1905 if (cnt % 8 == 0) { 1906 mdb_printf("\n"); 1907 } 1908 mdb_printf("%04x ", fw->mailbox_reg[cnt]); 1909 } 1910 1911 if (ha->cfg_flags & (CFG_CTRL_2300 | CFG_CTRL_6322)) { 1912 mdb_printf("\n\nAuto Request Response DMA Registers:"); 1913 for (cnt = 0; cnt < sizeof (fw->resp_dma_reg) / 2; cnt++) { 1914 if (cnt % 8 == 0) { 1915 mdb_printf("\n"); 1916 } 1917 mdb_printf("%04x ", fw->resp_dma_reg[cnt]); 1918 } 1919 } 1920 1921 mdb_printf("\n\nDMA Registers:"); 1922 for (cnt = 0; cnt < sizeof (fw->dma_reg) / 2; cnt++) { 1923 if (cnt % 8 == 0) { 1924 mdb_printf("\n"); 1925 } 1926 mdb_printf("%04x ", fw->dma_reg[cnt]); 1927 } 1928 1929 mdb_printf("\n\nRISC Hardware Registers:"); 1930 for (cnt = 0; cnt < sizeof (fw->risc_hdw_reg) / 2; cnt++) { 1931 if (cnt % 8 == 0) { 1932 mdb_printf("\n"); 1933 } 1934 mdb_printf("%04x ", fw->risc_hdw_reg[cnt]); 1935 } 1936 1937 mdb_printf("\n\nRISC GP0 Registers:"); 1938 for (cnt = 0; cnt < sizeof (fw->risc_gp0_reg) / 2; cnt++) { 1939 if (cnt % 8 == 0) { 1940 mdb_printf("\n"); 1941 } 1942 mdb_printf("%04x ", fw->risc_gp0_reg[cnt]); 1943 } 1944 1945 mdb_printf("\n\nRISC GP1 Registers:"); 1946 for (cnt = 0; cnt < sizeof (fw->risc_gp1_reg) / 2; cnt++) { 1947 if (cnt % 8 == 0) { 1948 mdb_printf("\n"); 1949 } 1950 mdb_printf("%04x ", fw->risc_gp1_reg[cnt]); 1951 } 1952 1953 mdb_printf("\n\nRISC GP2 Registers:"); 1954 for (cnt = 0; cnt < sizeof (fw->risc_gp2_reg) / 2; cnt++) { 1955 if (cnt % 8 == 0) { 1956 mdb_printf("\n"); 1957 } 1958 mdb_printf("%04x ", fw->risc_gp2_reg[cnt]); 1959 } 1960 1961 mdb_printf("\n\nRISC GP3 Registers:"); 1962 for (cnt = 0; cnt < sizeof (fw->risc_gp3_reg) / 2; cnt++) { 1963 if (cnt % 8 == 0) { 1964 mdb_printf("\n"); 1965 } 1966 mdb_printf("%04x ", fw->risc_gp3_reg[cnt]); 1967 } 1968 1969 mdb_printf("\n\nRISC GP4 Registers:"); 1970 for (cnt = 0; cnt < sizeof (fw->risc_gp4_reg) / 2; cnt++) { 1971 if (cnt % 8 == 0) { 1972 mdb_printf("\n"); 1973 } 1974 mdb_printf("%04x ", fw->risc_gp4_reg[cnt]); 1975 } 1976 1977 mdb_printf("\n\nRISC GP5 Registers:"); 1978 for (cnt = 0; cnt < sizeof (fw->risc_gp5_reg) / 2; cnt++) { 1979 if (cnt % 8 == 0) { 1980 mdb_printf("\n"); 1981 } 1982 mdb_printf("%04x ", fw->risc_gp5_reg[cnt]); 1983 } 1984 1985 mdb_printf("\n\nRISC GP6 Registers:"); 1986 for (cnt = 0; cnt < sizeof (fw->risc_gp6_reg) / 2; cnt++) { 1987 if (cnt % 8 == 0) { 1988 mdb_printf("\n"); 1989 } 1990 mdb_printf("%04x ", fw->risc_gp6_reg[cnt]); 1991 } 1992 1993 mdb_printf("\n\nRISC GP7 Registers:"); 1994 for (cnt = 0; cnt < sizeof (fw->risc_gp7_reg) / 2; cnt++) { 1995 if (cnt % 8 == 0) { 1996 mdb_printf("\n"); 1997 } 1998 mdb_printf("%04x ", fw->risc_gp7_reg[cnt]); 1999 } 2000 2001 mdb_printf("\n\nFrame Buffer Hardware Registers:"); 2002 for (cnt = 0; cnt < sizeof (fw->frame_buf_hdw_reg) / 2; cnt++) { 2003 if ((cnt == 16) && 2004 ((ha->cfg_flags & (CFG_CTRL_2300 | CFG_CTRL_6322)) == 0)) { 2005 break; 2006 } 2007 if (cnt % 8 == 0) { 2008 mdb_printf("\n"); 2009 } 2010 mdb_printf("%04x ", fw->frame_buf_hdw_reg[cnt]); 2011 } 2012 2013 mdb_printf("\n\nFPM B0 Registers:"); 2014 for (cnt = 0; cnt < sizeof (fw->fpm_b0_reg) / 2; cnt++) { 2015 if (cnt % 8 == 0) { 2016 mdb_printf("\n"); 2017 } 2018 mdb_printf("%04x ", fw->fpm_b0_reg[cnt]); 2019 } 2020 2021 mdb_printf("\n\nFPM B1 Registers:"); 2022 for (cnt = 0; cnt < sizeof (fw->fpm_b1_reg) / 2; cnt++) { 2023 if (cnt % 8 == 0) { 2024 mdb_printf("\n"); 2025 } 2026 mdb_printf("%04x ", fw->fpm_b1_reg[cnt]); 2027 } 2028 2029 if (ha->cfg_flags & (CFG_CTRL_2300 | CFG_CTRL_6322)) { 2030 mdb_printf("\n\nCode RAM Dump:"); 2031 for (cnt = 0; cnt < sizeof (fw->risc_ram) / 2; cnt++) { 2032 if (cnt % 8 == 0) { 2033 mdb_printf("\n%05x: ", cnt + 0x0800); 2034 } 2035 mdb_printf("%04x ", fw->risc_ram[cnt]); 2036 } 2037 2038 mdb_printf("\n\nStack RAM Dump:"); 2039 for (cnt = 0; cnt < sizeof (fw->stack_ram) / 2; cnt++) { 2040 if (cnt % 8 == 0) { 2041 mdb_printf("\n%05x: ", cnt + 0x010000); 2042 } 2043 mdb_printf("%04x ", fw->stack_ram[cnt]); 2044 } 2045 2046 mdb_printf("\n\nData RAM Dump:"); 2047 for (cnt = 0; cnt < sizeof (fw->data_ram) / 2; cnt++) { 2048 if (cnt % 8 == 0) { 2049 mdb_printf("\n%05x: ", cnt + 0x010800); 2050 } 2051 mdb_printf("%04x ", fw->data_ram[cnt]); 2052 } 2053 2054 mdb_printf("\n\n[<==END] ISP Debug Dump.\n"); 2055 2056 mdb_printf("\n\nRequest Queue"); 2057 2058 for (cnt = 0; cnt < REQUEST_QUEUE_SIZE / 4; cnt++) { 2059 if (cnt % 8 == 0) { 2060 mdb_printf("\n%08x: ", cnt); 2061 } 2062 mdb_printf("%08x ", fw->req_q[cnt]); 2063 } 2064 2065 mdb_printf("\n\nResponse Queue"); 2066 2067 for (cnt = 0; cnt < RESPONSE_QUEUE_SIZE / 4; cnt++) { 2068 if (cnt % 8 == 0) { 2069 mdb_printf("\n%08x: ", cnt); 2070 } 2071 mdb_printf("%08x ", fw->rsp_q[cnt]); 2072 } 2073 2074 mdb_printf("\n"); 2075 2076 } else { 2077 mdb_printf("\n\nRISC SRAM:"); 2078 for (cnt = 0; cnt < 0xf000; cnt++) { 2079 if (cnt % 8 == 0) { 2080 mdb_printf("\n%04x: ", cnt + 0x1000); 2081 } 2082 mdb_printf("%04x ", fw->risc_ram[cnt]); 2083 } 2084 } 2085 2086 mdb_free(fw, ha->ql_dump_size); 2087 2088 return (DCMD_OK); 2089 } 2090 2091 /* 2092 * ql_24xx_dump_dcmd 2093 * prints out a firmware dump buffer 2094 * 2095 * Input: 2096 * addr = User supplied address. (NB: nust be an ha) 2097 * flags = mdb flags. 2098 * argc = Number of user supplied args. 2099 * argv = Arg array. 2100 * 2101 * Returns: 2102 * DCMD_OK or DCMD_ERR 2103 * 2104 * Context: 2105 * User context. 2106 * 2107 */ 2108 /*ARGSUSED*/ 2109 static int 2110 ql_24xx_dump_dcmd(ql_adapter_state_t *ha, uint_t flags, int argc, 2111 const mdb_arg_t *argv) 2112 { 2113 ql_24xx_fw_dump_t *fw; 2114 uint32_t cnt = 0; 2115 2116 fw = (ql_24xx_fw_dump_t *)mdb_alloc(ha->ql_dump_size, UM_SLEEP); 2117 2118 if (mdb_vread(fw, ha->ql_dump_size, 2119 (uintptr_t)ha->ql_dump_ptr) == -1) { 2120 mdb_warn("failed to read ql_dump_ptr (no f/w dump active?)"); 2121 mdb_free(fw, ha->ql_dump_size); 2122 return (DCMD_OK); 2123 } 2124 2125 mdb_printf("ISP FW Version %d.%02d.%02d Attributes %X\n", 2126 ha->fw_major_version, ha->fw_minor_version, 2127 ha->fw_subminor_version, ha->fw_attributes); 2128 2129 mdb_printf("\nHCCR Register\n%08x\n", fw->hccr); 2130 2131 mdb_printf("\nHost Interface Registers"); 2132 for (cnt = 0; cnt < sizeof (fw->host_reg) / 4; cnt++) { 2133 if (cnt % 8 == 0) { 2134 mdb_printf("\n"); 2135 } 2136 mdb_printf("%08x ", fw->host_reg[cnt]); 2137 } 2138 2139 mdb_printf("\n\nMailbox Registers"); 2140 for (cnt = 0; cnt < sizeof (fw->mailbox_reg) / 2; cnt++) { 2141 if (cnt % 16 == 0) { 2142 mdb_printf("\n"); 2143 } 2144 mdb_printf("%04x ", fw->mailbox_reg[cnt]); 2145 } 2146 2147 mdb_printf("\n\nXSEQ GP Registers"); 2148 for (cnt = 0; cnt < sizeof (fw->xseq_gp_reg) / 4; cnt++) { 2149 if (cnt % 8 == 0) { 2150 mdb_printf("\n"); 2151 } 2152 mdb_printf("%08x ", fw->xseq_gp_reg[cnt]); 2153 } 2154 2155 mdb_printf("\n\nXSEQ-0 Registers"); 2156 for (cnt = 0; cnt < sizeof (fw->xseq_0_reg) / 4; cnt++) { 2157 if (cnt % 8 == 0) { 2158 mdb_printf("\n"); 2159 } 2160 mdb_printf("%08x ", fw->xseq_0_reg[cnt]); 2161 } 2162 2163 mdb_printf("\n\nXSEQ-1 Registers"); 2164 for (cnt = 0; cnt < sizeof (fw->xseq_1_reg) / 4; cnt++) { 2165 if (cnt % 8 == 0) { 2166 mdb_printf("\n"); 2167 } 2168 mdb_printf("%08x ", fw->xseq_1_reg[cnt]); 2169 } 2170 2171 mdb_printf("\n\nRSEQ GP Registers"); 2172 for (cnt = 0; cnt < sizeof (fw->rseq_gp_reg) / 4; cnt++) { 2173 if (cnt % 8 == 0) { 2174 mdb_printf("\n"); 2175 } 2176 mdb_printf("%08x ", fw->rseq_gp_reg[cnt]); 2177 } 2178 2179 mdb_printf("\n\nRSEQ-0 Registers"); 2180 for (cnt = 0; cnt < sizeof (fw->rseq_0_reg) / 4; cnt++) { 2181 if (cnt % 8 == 0) { 2182 mdb_printf("\n"); 2183 } 2184 mdb_printf("%08x ", fw->rseq_0_reg[cnt]); 2185 } 2186 2187 mdb_printf("\n\nRSEQ-1 Registers"); 2188 for (cnt = 0; cnt < sizeof (fw->rseq_1_reg) / 4; cnt++) { 2189 if (cnt % 8 == 0) { 2190 mdb_printf("\n"); 2191 } 2192 mdb_printf("%08x ", fw->rseq_1_reg[cnt]); 2193 } 2194 2195 mdb_printf("\n\nRSEQ-2 Registers"); 2196 for (cnt = 0; cnt < sizeof (fw->rseq_2_reg) / 4; cnt++) { 2197 if (cnt % 8 == 0) { 2198 mdb_printf("\n"); 2199 } 2200 mdb_printf("%08x ", fw->rseq_2_reg[cnt]); 2201 } 2202 2203 mdb_printf("\n\nCommand DMA Registers"); 2204 for (cnt = 0; cnt < sizeof (fw->cmd_dma_reg) / 4; cnt++) { 2205 if (cnt % 8 == 0) { 2206 mdb_printf("\n"); 2207 } 2208 mdb_printf("%08x ", fw->cmd_dma_reg[cnt]); 2209 } 2210 2211 mdb_printf("\n\nRequest0 Queue DMA Channel Registers"); 2212 for (cnt = 0; cnt < sizeof (fw->req0_dma_reg) / 4; cnt++) { 2213 if (cnt % 8 == 0) { 2214 mdb_printf("\n"); 2215 } 2216 mdb_printf("%08x ", fw->req0_dma_reg[cnt]); 2217 } 2218 2219 mdb_printf("\n\nResponse0 Queue DMA Channel Registers"); 2220 for (cnt = 0; cnt < sizeof (fw->resp0_dma_reg) / 4; cnt++) { 2221 if (cnt % 8 == 0) { 2222 mdb_printf("\n"); 2223 } 2224 mdb_printf("%08x ", fw->resp0_dma_reg[cnt]); 2225 } 2226 2227 mdb_printf("\n\nRequest1 Queue DMA Channel Registers"); 2228 for (cnt = 0; cnt < sizeof (fw->req1_dma_reg) / 4; cnt++) { 2229 if (cnt % 8 == 0) { 2230 mdb_printf("\n"); 2231 } 2232 mdb_printf("%08x ", fw->req1_dma_reg[cnt]); 2233 } 2234 2235 mdb_printf("\n\nXMT0 Data DMA Registers"); 2236 for (cnt = 0; cnt < sizeof (fw->xmt0_dma_reg) / 4; cnt++) { 2237 if (cnt % 8 == 0) { 2238 mdb_printf("\n"); 2239 } 2240 mdb_printf("%08x ", fw->xmt0_dma_reg[cnt]); 2241 } 2242 2243 mdb_printf("\n\nXMT1 Data DMA Registers"); 2244 for (cnt = 0; cnt < sizeof (fw->xmt1_dma_reg) / 4; cnt++) { 2245 if (cnt % 8 == 0) { 2246 mdb_printf("\n"); 2247 } 2248 mdb_printf("%08x ", fw->xmt1_dma_reg[cnt]); 2249 } 2250 2251 mdb_printf("\n\nXMT2 Data DMA Registers"); 2252 for (cnt = 0; cnt < sizeof (fw->xmt2_dma_reg) / 4; cnt++) { 2253 if (cnt % 8 == 0) { 2254 mdb_printf("\n"); 2255 } 2256 mdb_printf("%08x ", fw->xmt2_dma_reg[cnt]); 2257 } 2258 2259 mdb_printf("\n\nXMT3 Data DMA Registers"); 2260 for (cnt = 0; cnt < sizeof (fw->xmt3_dma_reg) / 4; cnt++) { 2261 if (cnt % 8 == 0) { 2262 mdb_printf("\n"); 2263 } 2264 mdb_printf("%08x ", fw->xmt3_dma_reg[cnt]); 2265 } 2266 2267 mdb_printf("\n\nXMT4 Data DMA Registers"); 2268 for (cnt = 0; cnt < sizeof (fw->xmt4_dma_reg) / 4; cnt++) { 2269 if (cnt % 8 == 0) { 2270 mdb_printf("\n"); 2271 } 2272 mdb_printf("%08x ", fw->xmt4_dma_reg[cnt]); 2273 } 2274 2275 mdb_printf("\n\nXMT Data DMA Common Registers"); 2276 for (cnt = 0; cnt < sizeof (fw->xmt_data_dma_reg) / 4; cnt++) { 2277 if (cnt % 8 == 0) { 2278 mdb_printf("\n"); 2279 } 2280 mdb_printf("%08x ", fw->xmt_data_dma_reg[cnt]); 2281 } 2282 2283 mdb_printf("\n\nRCV Thread 0 Data DMA Registers"); 2284 for (cnt = 0; cnt < sizeof (fw->rcvt0_data_dma_reg) / 4; cnt++) { 2285 if (cnt % 8 == 0) { 2286 mdb_printf("\n"); 2287 } 2288 mdb_printf("%08x ", fw->rcvt0_data_dma_reg[cnt]); 2289 } 2290 2291 mdb_printf("\n\nRCV Thread 1 Data DMA Registers"); 2292 for (cnt = 0; cnt < sizeof (fw->rcvt1_data_dma_reg) / 4; cnt++) { 2293 if (cnt % 8 == 0) { 2294 mdb_printf("\n"); 2295 } 2296 mdb_printf("%08x ", fw->rcvt1_data_dma_reg[cnt]); 2297 } 2298 2299 mdb_printf("\n\nRISC GP Registers"); 2300 for (cnt = 0; cnt < sizeof (fw->risc_gp_reg) / 4; cnt++) { 2301 if (cnt % 8 == 0) { 2302 mdb_printf("\n"); 2303 } 2304 mdb_printf("%08x ", fw->risc_gp_reg[cnt]); 2305 } 2306 2307 mdb_printf("\n\nShadow Registers"); 2308 for (cnt = 0; cnt < sizeof (fw->shadow_reg) / 4; cnt++) { 2309 if (cnt % 8 == 0) { 2310 mdb_printf("\n"); 2311 } 2312 mdb_printf("%08x ", fw->shadow_reg[cnt]); 2313 } 2314 2315 mdb_printf("\n\nLMC Registers"); 2316 for (cnt = 0; cnt < sizeof (fw->lmc_reg) / 4; cnt++) { 2317 if (cnt % 8 == 0) { 2318 mdb_printf("\n"); 2319 } 2320 mdb_printf("%08x ", fw->lmc_reg[cnt]); 2321 } 2322 2323 mdb_printf("\n\nFPM Hardware Registers"); 2324 for (cnt = 0; cnt < sizeof (fw->fpm_hdw_reg) / 4; cnt++) { 2325 if (cnt % 8 == 0) { 2326 mdb_printf("\n"); 2327 } 2328 mdb_printf("%08x ", fw->fpm_hdw_reg[cnt]); 2329 } 2330 2331 mdb_printf("\n\nFB Hardware Registers"); 2332 for (cnt = 0; cnt < sizeof (fw->fb_hdw_reg) / 4; cnt++) { 2333 if (cnt % 8 == 0) { 2334 mdb_printf("\n"); 2335 } 2336 mdb_printf("%08x ", fw->fb_hdw_reg[cnt]); 2337 } 2338 2339 mdb_printf("\n\nCode RAM"); 2340 for (cnt = 0; cnt < sizeof (fw->code_ram) / 4; cnt++) { 2341 if (cnt % 8 == 0) { 2342 mdb_printf("\n%08x: ", cnt + 0x20000); 2343 } 2344 mdb_printf("%08x ", fw->code_ram[cnt]); 2345 } 2346 2347 mdb_printf("\n\nExternal Memory"); 2348 for (cnt = 0; cnt < ha->fw_ext_memory_size / 4; cnt++) { 2349 if (cnt % 8 == 0) { 2350 mdb_printf("\n%08x: ", cnt + 0x100000); 2351 } 2352 mdb_printf("%08x ", fw->ext_mem[cnt]); 2353 } 2354 2355 mdb_printf("\n[<==END] ISP Debug Dump"); 2356 2357 mdb_printf("\n\nRequest Queue"); 2358 2359 for (cnt = 0; cnt < REQUEST_QUEUE_SIZE / 4; cnt++) { 2360 if (cnt % 8 == 0) { 2361 mdb_printf("\n%08x: ", cnt); 2362 } 2363 mdb_printf("%08x ", fw->req_q[cnt]); 2364 } 2365 2366 mdb_printf("\n\nResponse Queue"); 2367 2368 for (cnt = 0; cnt < RESPONSE_QUEUE_SIZE / 4; cnt++) { 2369 if (cnt % 8 == 0) { 2370 mdb_printf("\n%08x: ", cnt); 2371 } 2372 mdb_printf("%08x ", fw->rsp_q[cnt]); 2373 } 2374 2375 if ((ha->cfg_flags & CFG_ENABLE_FWEXTTRACE) && 2376 (ha->fwexttracebuf.bp != NULL)) { 2377 uint32_t cnt_b = 0; 2378 uint32_t *w32 = ha->fwexttracebuf.bp; 2379 2380 mdb_printf("\n\nExtended Trace Buffer Memory"); 2381 /* show data address as a byte address, data as long words */ 2382 for (cnt = 0; cnt < FWEXTSIZE / 4; cnt++) { 2383 cnt_b = cnt * 4; 2384 if (cnt_b % 32 == 0) { 2385 mdb_printf("\n%08x: ", w32 + cnt_b); 2386 } 2387 mdb_printf("%08x ", fw->ext_trace_buf[cnt]); 2388 } 2389 } 2390 2391 if ((ha->cfg_flags & CFG_ENABLE_FWFCETRACE) && 2392 (ha->fwfcetracebuf.bp != NULL)) { 2393 uint32_t cnt_b = 0; 2394 uint32_t *w32 = ha->fwfcetracebuf.bp; 2395 2396 mdb_printf("\n\nFC Event Trace Buffer Memory"); 2397 /* show data address as a byte address, data as long words */ 2398 for (cnt = 0; cnt < FWFCESIZE / 4; cnt++) { 2399 cnt_b = cnt * 4; 2400 if (cnt_b % 32 == 0) { 2401 mdb_printf("\n%08x: ", w32 + cnt_b); 2402 } 2403 mdb_printf("%08x ", fw->fce_trace_buf[cnt]); 2404 } 2405 } 2406 mdb_free(fw, ha->ql_dump_size); 2407 2408 return (DCMD_OK); 2409 } 2410 2411 /* 2412 * ql_25xx_dump_dcmd 2413 * prints out a firmware dump buffer 2414 * 2415 * Input: 2416 * addr = User supplied address. (NB: nust be an ha) 2417 * flags = mdb flags. 2418 * argc = Number of user supplied args. 2419 * argv = Arg array. 2420 * 2421 * Returns: 2422 * DCMD_OK or DCMD_ERR 2423 * 2424 * Context: 2425 * User context. 2426 * 2427 */ 2428 /*ARGSUSED*/ 2429 static int 2430 ql_25xx_dump_dcmd(ql_adapter_state_t *ha, uint_t flags, int argc, 2431 const mdb_arg_t *argv) 2432 { 2433 ql_25xx_fw_dump_t *fw; 2434 uint32_t cnt = 0; 2435 2436 fw = (ql_25xx_fw_dump_t *)mdb_alloc(ha->ql_dump_size, UM_SLEEP); 2437 2438 if (mdb_vread(fw, ha->ql_dump_size, 2439 (uintptr_t)ha->ql_dump_ptr) == -1) { 2440 mdb_warn("failed to read ql_dump_ptr (no f/w dump active?)"); 2441 mdb_free(fw, ha->ql_dump_size); 2442 return (DCMD_OK); 2443 } 2444 2445 mdb_printf("\nISP FW Version %d.%02d.%02d Attributes %X\n", 2446 ha->fw_major_version, ha->fw_minor_version, 2447 ha->fw_subminor_version, ha->fw_attributes); 2448 2449 mdb_printf("\nR2H Register\n%08x\n", fw->r2h_status); 2450 2451 mdb_printf("\n\nHostRisc Registers"); 2452 for (cnt = 0; cnt < sizeof (fw->hostrisc_reg) / 4; cnt++) { 2453 if (cnt % 8 == 0) { 2454 mdb_printf("\n"); 2455 } 2456 mdb_printf("%08x ", fw->hostrisc_reg[cnt]); 2457 } 2458 2459 mdb_printf("\n\nPCIe Registers"); 2460 for (cnt = 0; cnt < sizeof (fw->pcie_reg) / 4; cnt++) { 2461 if (cnt % 8 == 0) { 2462 mdb_printf("\n"); 2463 } 2464 mdb_printf("%08x ", fw->pcie_reg[cnt]); 2465 } 2466 2467 mdb_printf("\n\nHost Interface Registers"); 2468 for (cnt = 0; cnt < sizeof (fw->host_reg) / 4; cnt++) { 2469 if (cnt % 8 == 0) { 2470 mdb_printf("\n"); 2471 } 2472 mdb_printf("%08x ", fw->host_reg[cnt]); 2473 } 2474 2475 mdb_printf("\n\nShadow Registers"); 2476 for (cnt = 0; cnt < sizeof (fw->shadow_reg) / 4; cnt++) { 2477 if (cnt % 8 == 0) { 2478 mdb_printf("\n"); 2479 } 2480 2481 mdb_printf("%08x ", fw->shadow_reg[cnt]); 2482 } 2483 2484 mdb_printf("\n\nMailbox Registers"); 2485 for (cnt = 0; cnt < sizeof (fw->mailbox_reg) / 2; cnt++) { 2486 if (cnt % 16 == 0) { 2487 mdb_printf("\n"); 2488 } 2489 mdb_printf("%04x ", fw->mailbox_reg[cnt]); 2490 } 2491 2492 mdb_printf("\n\nXSEQ GP Registers"); 2493 for (cnt = 0; cnt < sizeof (fw->xseq_gp_reg) / 4; cnt++) { 2494 if (cnt % 8 == 0) { 2495 mdb_printf("\n"); 2496 } 2497 mdb_printf("%08x ", fw->xseq_gp_reg[cnt]); 2498 } 2499 2500 mdb_printf("\n\nXSEQ-0 Registers"); 2501 for (cnt = 0; cnt < sizeof (fw->xseq_0_reg) / 4; cnt++) { 2502 if (cnt % 8 == 0) { 2503 mdb_printf("\n"); 2504 } 2505 mdb_printf("%08x ", fw->xseq_0_reg[cnt]); 2506 } 2507 2508 mdb_printf("\n\nXSEQ-1 Registers"); 2509 for (cnt = 0; cnt < sizeof (fw->xseq_1_reg) / 4; cnt++) { 2510 if (cnt % 8 == 0) { 2511 mdb_printf("\n"); 2512 } 2513 mdb_printf("%08x ", fw->xseq_1_reg[cnt]); 2514 } 2515 2516 mdb_printf("\n\nRSEQ GP Registers"); 2517 for (cnt = 0; cnt < sizeof (fw->rseq_gp_reg) / 4; cnt++) { 2518 if (cnt % 8 == 0) { 2519 mdb_printf("\n"); 2520 } 2521 mdb_printf("%08x ", fw->rseq_gp_reg[cnt]); 2522 } 2523 2524 mdb_printf("\n\nRSEQ-0 Registers"); 2525 for (cnt = 0; cnt < sizeof (fw->rseq_0_reg) / 4; cnt++) { 2526 if (cnt % 8 == 0) { 2527 mdb_printf("\n"); 2528 } 2529 mdb_printf("%08x ", fw->rseq_0_reg[cnt]); 2530 } 2531 2532 mdb_printf("\n\nRSEQ-1 Registers"); 2533 for (cnt = 0; cnt < sizeof (fw->rseq_1_reg) / 4; cnt++) { 2534 if (cnt % 8 == 0) { 2535 mdb_printf("\n"); 2536 } 2537 mdb_printf("%08x ", fw->rseq_1_reg[cnt]); 2538 } 2539 2540 mdb_printf("\n\nRSEQ-2 Registers"); 2541 for (cnt = 0; cnt < sizeof (fw->rseq_2_reg) / 4; cnt++) { 2542 if (cnt % 8 == 0) { 2543 mdb_printf("\n"); 2544 } 2545 mdb_printf("%08x ", fw->rseq_2_reg[cnt]); 2546 } 2547 2548 mdb_printf("\n\nASEQ GP Registers"); 2549 for (cnt = 0; cnt < sizeof (fw->aseq_gp_reg) / 4; cnt++) { 2550 if (cnt % 8 == 0) { 2551 mdb_printf("\n"); 2552 } 2553 mdb_printf("%08x ", fw->aseq_gp_reg[cnt]); 2554 } 2555 2556 mdb_printf("\n\nASEQ-0 GP Registers"); 2557 for (cnt = 0; cnt < sizeof (fw->aseq_0_reg) / 4; cnt++) { 2558 if (cnt % 8 == 0) { 2559 mdb_printf("\n"); 2560 } 2561 2562 mdb_printf("%08x ", fw->aseq_0_reg[cnt]); 2563 } 2564 2565 mdb_printf("\n\nASEQ-1 GP Registers"); 2566 for (cnt = 0; cnt < sizeof (fw->aseq_1_reg) / 4; cnt++) { 2567 if (cnt % 8 == 0) { 2568 mdb_printf("\n"); 2569 } 2570 2571 mdb_printf("%08x ", fw->aseq_1_reg[cnt]); 2572 } 2573 2574 mdb_printf("\n\nASEQ-2 GP Registers"); 2575 for (cnt = 0; cnt < sizeof (fw->aseq_2_reg) / 4; cnt++) { 2576 if (cnt % 8 == 0) { 2577 mdb_printf("\n"); 2578 } 2579 mdb_printf("%08x ", fw->aseq_2_reg[cnt]); 2580 } 2581 2582 mdb_printf("\n\nCommand DMA Registers"); 2583 for (cnt = 0; cnt < sizeof (fw->cmd_dma_reg) / 4; cnt++) { 2584 if (cnt % 8 == 0) { 2585 mdb_printf("\n"); 2586 } 2587 mdb_printf("%08x ", fw->cmd_dma_reg[cnt]); 2588 } 2589 2590 mdb_printf("\n\nRequest0 Queue DMA Channel Registers"); 2591 for (cnt = 0; cnt < sizeof (fw->req0_dma_reg) / 4; cnt++) { 2592 if (cnt % 8 == 0) { 2593 mdb_printf("\n"); 2594 } 2595 mdb_printf("%08x ", fw->req0_dma_reg[cnt]); 2596 } 2597 2598 mdb_printf("\n\nResponse0 Queue DMA Channel Registers"); 2599 for (cnt = 0; cnt < sizeof (fw->resp0_dma_reg) / 4; cnt++) { 2600 if (cnt % 8 == 0) { 2601 mdb_printf("\n"); 2602 } 2603 mdb_printf("%08x ", fw->resp0_dma_reg[cnt]); 2604 } 2605 2606 mdb_printf("\n\nRequest1 Queue DMA Channel Registers"); 2607 for (cnt = 0; cnt < sizeof (fw->req1_dma_reg) / 4; cnt++) { 2608 if (cnt % 8 == 0) { 2609 mdb_printf("\n"); 2610 } 2611 mdb_printf("%08x ", fw->req1_dma_reg[cnt]); 2612 } 2613 2614 mdb_printf("\n\nXMT0 Data DMA Registers"); 2615 for (cnt = 0; cnt < sizeof (fw->xmt0_dma_reg) / 4; cnt++) { 2616 if (cnt % 8 == 0) { 2617 mdb_printf("\n"); 2618 } 2619 mdb_printf("%08x ", fw->xmt0_dma_reg[cnt]); 2620 } 2621 2622 mdb_printf("\n\nXMT1 Data DMA Registers"); 2623 for (cnt = 0; cnt < sizeof (fw->xmt1_dma_reg) / 4; cnt++) { 2624 if (cnt % 8 == 0) { 2625 mdb_printf("\n"); 2626 } 2627 mdb_printf("%08x ", fw->xmt1_dma_reg[cnt]); 2628 } 2629 2630 mdb_printf("\n\nXMT2 Data DMA Registers"); 2631 for (cnt = 0; cnt < sizeof (fw->xmt2_dma_reg) / 4; cnt++) { 2632 if (cnt % 8 == 0) { 2633 mdb_printf("\n"); 2634 } 2635 mdb_printf("%08x ", fw->xmt2_dma_reg[cnt]); 2636 } 2637 2638 mdb_printf("\n\nXMT3 Data DMA Registers"); 2639 for (cnt = 0; cnt < sizeof (fw->xmt3_dma_reg) / 4; cnt++) { 2640 if (cnt % 8 == 0) { 2641 mdb_printf("\n"); 2642 } 2643 mdb_printf("%08x ", fw->xmt3_dma_reg[cnt]); 2644 } 2645 2646 mdb_printf("\n\nXMT4 Data DMA Registers"); 2647 for (cnt = 0; cnt < sizeof (fw->xmt4_dma_reg) / 4; cnt++) { 2648 if (cnt % 8 == 0) { 2649 mdb_printf("\n"); 2650 } 2651 mdb_printf("%08x ", fw->xmt4_dma_reg[cnt]); 2652 } 2653 2654 mdb_printf("\n\nXMT Data DMA Common Registers"); 2655 for (cnt = 0; cnt < sizeof (fw->xmt_data_dma_reg) / 4; cnt++) { 2656 if (cnt % 8 == 0) { 2657 mdb_printf("\n"); 2658 } 2659 mdb_printf("%08x ", fw->xmt_data_dma_reg[cnt]); 2660 } 2661 2662 mdb_printf("\n\nRCV Thread 0 Data DMA Registers"); 2663 for (cnt = 0; cnt < sizeof (fw->rcvt0_data_dma_reg) / 4; cnt++) { 2664 if (cnt % 8 == 0) { 2665 mdb_printf("\n"); 2666 } 2667 mdb_printf("%08x ", fw->rcvt0_data_dma_reg[cnt]); 2668 } 2669 2670 mdb_printf("\n\nRCV Thread 1 Data DMA Registers"); 2671 for (cnt = 0; cnt < sizeof (fw->rcvt1_data_dma_reg) / 4; cnt++) { 2672 if (cnt % 8 == 0) { 2673 mdb_printf("\n"); 2674 } 2675 mdb_printf("%08x ", fw->rcvt1_data_dma_reg[cnt]); 2676 } 2677 2678 mdb_printf("\n\nRISC GP Registers"); 2679 for (cnt = 0; cnt < sizeof (fw->risc_gp_reg) / 4; cnt++) { 2680 if (cnt % 8 == 0) { 2681 mdb_printf("\n"); 2682 } 2683 mdb_printf("%08x ", fw->risc_gp_reg[cnt]); 2684 } 2685 2686 mdb_printf("\n\nRISC IO Register\n%08x", fw->risc_io); 2687 2688 mdb_printf("\n\nLMC Registers"); 2689 for (cnt = 0; cnt < sizeof (fw->lmc_reg) / 4; cnt++) { 2690 if (cnt % 8 == 0) { 2691 mdb_printf("\n"); 2692 } 2693 mdb_printf("%08x ", fw->lmc_reg[cnt]); 2694 } 2695 2696 mdb_printf("\n\nFPM Hardware Registers"); 2697 for (cnt = 0; cnt < sizeof (fw->fpm_hdw_reg) / 4; cnt++) { 2698 if (cnt % 8 == 0) { 2699 mdb_printf("\n"); 2700 } 2701 mdb_printf("%08x ", fw->fpm_hdw_reg[cnt]); 2702 } 2703 2704 mdb_printf("\n\nFB Hardware Registers"); 2705 for (cnt = 0; cnt < sizeof (fw->fb_hdw_reg) / 4; cnt++) { 2706 if (cnt % 8 == 0) { 2707 mdb_printf("\n"); 2708 } 2709 mdb_printf("%08x ", fw->fb_hdw_reg[cnt]); 2710 } 2711 2712 mdb_printf("\n\nCode RAM"); 2713 for (cnt = 0; cnt < sizeof (fw->code_ram) / 4; cnt++) { 2714 if (cnt % 8 == 0) { 2715 mdb_printf("\n%08x: ", cnt + 0x20000); 2716 } 2717 mdb_printf("%08x ", fw->code_ram[cnt]); 2718 } 2719 2720 mdb_printf("\n\nExternal Memory"); 2721 for (cnt = 0; cnt < ha->fw_ext_memory_size / 4; cnt++) { 2722 if (cnt % 8 == 0) { 2723 mdb_printf("\n%08x: ", cnt + 0x100000); 2724 } 2725 mdb_printf("%08x ", fw->ext_mem[cnt]); 2726 } 2727 2728 mdb_printf("\n[<==END] ISP Debug Dump"); 2729 2730 mdb_printf("\n\nRequest Queue"); 2731 2732 for (cnt = 0; cnt < REQUEST_QUEUE_SIZE / 4; cnt++) { 2733 if (cnt % 8 == 0) { 2734 mdb_printf("\n%08x: ", cnt); 2735 } 2736 mdb_printf("%08x ", fw->req_q[cnt]); 2737 } 2738 2739 mdb_printf("\n\nResponse Queue"); 2740 2741 for (cnt = 0; cnt < RESPONSE_QUEUE_SIZE / 4; cnt++) { 2742 if (cnt % 8 == 0) { 2743 mdb_printf("\n%08x: ", cnt); 2744 } 2745 mdb_printf("%08x ", fw->rsp_q[cnt]); 2746 } 2747 2748 if ((ha->cfg_flags & CFG_ENABLE_FWEXTTRACE) && 2749 (ha->fwexttracebuf.bp != NULL)) { 2750 uint32_t cnt_b = 0; 2751 uint32_t *w32 = ha->fwexttracebuf.bp; 2752 2753 mdb_printf("\n\nExtended Trace Buffer Memory"); 2754 /* show data address as a byte address, data as long words */ 2755 for (cnt = 0; cnt < FWEXTSIZE / 4; cnt++) { 2756 cnt_b = cnt * 4; 2757 if (cnt_b % 32 == 0) { 2758 mdb_printf("\n%08x: ", w32 + cnt_b); 2759 } 2760 mdb_printf("%08x ", fw->ext_trace_buf[cnt]); 2761 } 2762 } 2763 2764 if ((ha->cfg_flags & CFG_ENABLE_FWFCETRACE) && 2765 (ha->fwfcetracebuf.bp != NULL)) { 2766 uint32_t cnt_b = 0; 2767 uint32_t *w32 = ha->fwfcetracebuf.bp; 2768 2769 mdb_printf("\n\nFC Event Trace Buffer Memory"); 2770 /* show data address as a byte address, data as long words */ 2771 for (cnt = 0; cnt < FWFCESIZE / 4; cnt++) { 2772 cnt_b = cnt * 4; 2773 if (cnt_b % 32 == 0) { 2774 mdb_printf("\n%08x: ", w32 + cnt_b); 2775 } 2776 mdb_printf("%08x ", fw->fce_trace_buf[cnt]); 2777 } 2778 } 2779 2780 mdb_free(fw, ha->ql_dump_size); 2781 2782 mdb_printf("\n\nreturn exit\n"); 2783 2784 return (DCMD_OK); 2785 } 2786 2787 /* 2788 * ql_81xx_dump_dcmd 2789 * prints out a firmware dump buffer 2790 * 2791 * Input: 2792 * addr = User supplied address. (NB: nust be an ha) 2793 * flags = mdb flags. 2794 * argc = Number of user supplied args. 2795 * argv = Arg array. 2796 * 2797 * Returns: 2798 * DCMD_OK or DCMD_ERR 2799 * 2800 * Context: 2801 * User context. 2802 * 2803 */ 2804 /*ARGSUSED*/ 2805 static int 2806 ql_81xx_dump_dcmd(ql_adapter_state_t *ha, uint_t flags, int argc, 2807 const mdb_arg_t *argv) 2808 { 2809 ql_81xx_fw_dump_t *fw; 2810 uint32_t cnt = 0; 2811 2812 fw = (ql_81xx_fw_dump_t *)mdb_alloc(ha->ql_dump_size, UM_SLEEP); 2813 2814 if (mdb_vread(fw, ha->ql_dump_size, 2815 (uintptr_t)ha->ql_dump_ptr) == -1) { 2816 mdb_warn("failed to read ql_dump_ptr (no f/w dump active?)"); 2817 mdb_free(fw, ha->ql_dump_size); 2818 return (DCMD_OK); 2819 } 2820 2821 mdb_printf("\nISP FW Version %d.%02d.%02d Attributes %X\n", 2822 ha->fw_major_version, ha->fw_minor_version, 2823 ha->fw_subminor_version, ha->fw_attributes); 2824 2825 mdb_printf("\nR2H Register\n%08x\n", fw->r2h_status); 2826 2827 mdb_printf("\n\nHostRisc Registers"); 2828 for (cnt = 0; cnt < sizeof (fw->hostrisc_reg) / 4; cnt++) { 2829 if (cnt % 8 == 0) { 2830 mdb_printf("\n"); 2831 } 2832 mdb_printf("%08x ", fw->hostrisc_reg[cnt]); 2833 } 2834 2835 mdb_printf("\n\nPCIe Registers"); 2836 for (cnt = 0; cnt < sizeof (fw->pcie_reg) / 4; cnt++) { 2837 if (cnt % 8 == 0) { 2838 mdb_printf("\n"); 2839 } 2840 mdb_printf("%08x ", fw->pcie_reg[cnt]); 2841 } 2842 2843 mdb_printf("\n\nHost Interface Registers"); 2844 for (cnt = 0; cnt < sizeof (fw->host_reg) / 4; cnt++) { 2845 if (cnt % 8 == 0) { 2846 mdb_printf("\n"); 2847 } 2848 mdb_printf("%08x ", fw->host_reg[cnt]); 2849 } 2850 2851 mdb_printf("\n\nShadow Registers"); 2852 for (cnt = 0; cnt < sizeof (fw->shadow_reg) / 4; cnt++) { 2853 if (cnt % 8 == 0) { 2854 mdb_printf("\n"); 2855 } 2856 2857 mdb_printf("%08x ", fw->shadow_reg[cnt]); 2858 } 2859 2860 mdb_printf("\n\nMailbox Registers"); 2861 for (cnt = 0; cnt < sizeof (fw->mailbox_reg) / 2; cnt++) { 2862 if (cnt % 16 == 0) { 2863 mdb_printf("\n"); 2864 } 2865 mdb_printf("%04x ", fw->mailbox_reg[cnt]); 2866 } 2867 2868 mdb_printf("\n\nXSEQ GP Registers"); 2869 for (cnt = 0; cnt < sizeof (fw->xseq_gp_reg) / 4; cnt++) { 2870 if (cnt % 8 == 0) { 2871 mdb_printf("\n"); 2872 } 2873 mdb_printf("%08x ", fw->xseq_gp_reg[cnt]); 2874 } 2875 2876 mdb_printf("\n\nXSEQ-0 Registers"); 2877 for (cnt = 0; cnt < sizeof (fw->xseq_0_reg) / 4; cnt++) { 2878 if (cnt % 8 == 0) { 2879 mdb_printf("\n"); 2880 } 2881 mdb_printf("%08x ", fw->xseq_0_reg[cnt]); 2882 } 2883 2884 mdb_printf("\n\nXSEQ-1 Registers"); 2885 for (cnt = 0; cnt < sizeof (fw->xseq_1_reg) / 4; cnt++) { 2886 if (cnt % 8 == 0) { 2887 mdb_printf("\n"); 2888 } 2889 mdb_printf("%08x ", fw->xseq_1_reg[cnt]); 2890 } 2891 2892 mdb_printf("\n\nRSEQ GP Registers"); 2893 for (cnt = 0; cnt < sizeof (fw->rseq_gp_reg) / 4; cnt++) { 2894 if (cnt % 8 == 0) { 2895 mdb_printf("\n"); 2896 } 2897 mdb_printf("%08x ", fw->rseq_gp_reg[cnt]); 2898 } 2899 2900 mdb_printf("\n\nRSEQ-0 Registers"); 2901 for (cnt = 0; cnt < sizeof (fw->rseq_0_reg) / 4; cnt++) { 2902 if (cnt % 8 == 0) { 2903 mdb_printf("\n"); 2904 } 2905 mdb_printf("%08x ", fw->rseq_0_reg[cnt]); 2906 } 2907 2908 mdb_printf("\n\nRSEQ-1 Registers"); 2909 for (cnt = 0; cnt < sizeof (fw->rseq_1_reg) / 4; cnt++) { 2910 if (cnt % 8 == 0) { 2911 mdb_printf("\n"); 2912 } 2913 mdb_printf("%08x ", fw->rseq_1_reg[cnt]); 2914 } 2915 2916 mdb_printf("\n\nRSEQ-2 Registers"); 2917 for (cnt = 0; cnt < sizeof (fw->rseq_2_reg) / 4; cnt++) { 2918 if (cnt % 8 == 0) { 2919 mdb_printf("\n"); 2920 } 2921 mdb_printf("%08x ", fw->rseq_2_reg[cnt]); 2922 } 2923 2924 mdb_printf("\n\nASEQ GP Registers"); 2925 for (cnt = 0; cnt < sizeof (fw->aseq_gp_reg) / 4; cnt++) { 2926 if (cnt % 8 == 0) { 2927 mdb_printf("\n"); 2928 } 2929 mdb_printf("%08x ", fw->aseq_gp_reg[cnt]); 2930 } 2931 2932 mdb_printf("\n\nASEQ-0 GP Registers"); 2933 for (cnt = 0; cnt < sizeof (fw->aseq_0_reg) / 4; cnt++) { 2934 if (cnt % 8 == 0) { 2935 mdb_printf("\n"); 2936 } 2937 2938 mdb_printf("%08x ", fw->aseq_0_reg[cnt]); 2939 } 2940 2941 mdb_printf("\n\nASEQ-1 GP Registers"); 2942 for (cnt = 0; cnt < sizeof (fw->aseq_1_reg) / 4; cnt++) { 2943 if (cnt % 8 == 0) { 2944 mdb_printf("\n"); 2945 } 2946 2947 mdb_printf("%08x ", fw->aseq_1_reg[cnt]); 2948 } 2949 2950 mdb_printf("\n\nASEQ-2 GP Registers"); 2951 for (cnt = 0; cnt < sizeof (fw->aseq_2_reg) / 4; cnt++) { 2952 if (cnt % 8 == 0) { 2953 mdb_printf("\n"); 2954 } 2955 mdb_printf("%08x ", fw->aseq_2_reg[cnt]); 2956 } 2957 2958 mdb_printf("\n\nCommand DMA Registers"); 2959 for (cnt = 0; cnt < sizeof (fw->cmd_dma_reg) / 4; cnt++) { 2960 if (cnt % 8 == 0) { 2961 mdb_printf("\n"); 2962 } 2963 mdb_printf("%08x ", fw->cmd_dma_reg[cnt]); 2964 } 2965 2966 mdb_printf("\n\nRequest0 Queue DMA Channel Registers"); 2967 for (cnt = 0; cnt < sizeof (fw->req0_dma_reg) / 4; cnt++) { 2968 if (cnt % 8 == 0) { 2969 mdb_printf("\n"); 2970 } 2971 mdb_printf("%08x ", fw->req0_dma_reg[cnt]); 2972 } 2973 2974 mdb_printf("\n\nResponse0 Queue DMA Channel Registers"); 2975 for (cnt = 0; cnt < sizeof (fw->resp0_dma_reg) / 4; cnt++) { 2976 if (cnt % 8 == 0) { 2977 mdb_printf("\n"); 2978 } 2979 mdb_printf("%08x ", fw->resp0_dma_reg[cnt]); 2980 } 2981 2982 mdb_printf("\n\nRequest1 Queue DMA Channel Registers"); 2983 for (cnt = 0; cnt < sizeof (fw->req1_dma_reg) / 4; cnt++) { 2984 if (cnt % 8 == 0) { 2985 mdb_printf("\n"); 2986 } 2987 mdb_printf("%08x ", fw->req1_dma_reg[cnt]); 2988 } 2989 2990 mdb_printf("\n\nXMT0 Data DMA Registers"); 2991 for (cnt = 0; cnt < sizeof (fw->xmt0_dma_reg) / 4; cnt++) { 2992 if (cnt % 8 == 0) { 2993 mdb_printf("\n"); 2994 } 2995 mdb_printf("%08x ", fw->xmt0_dma_reg[cnt]); 2996 } 2997 2998 mdb_printf("\n\nXMT1 Data DMA Registers"); 2999 for (cnt = 0; cnt < sizeof (fw->xmt1_dma_reg) / 4; cnt++) { 3000 if (cnt % 8 == 0) { 3001 mdb_printf("\n"); 3002 } 3003 mdb_printf("%08x ", fw->xmt1_dma_reg[cnt]); 3004 } 3005 3006 mdb_printf("\n\nXMT2 Data DMA Registers"); 3007 for (cnt = 0; cnt < sizeof (fw->xmt2_dma_reg) / 4; cnt++) { 3008 if (cnt % 8 == 0) { 3009 mdb_printf("\n"); 3010 } 3011 mdb_printf("%08x ", fw->xmt2_dma_reg[cnt]); 3012 } 3013 3014 mdb_printf("\n\nXMT3 Data DMA Registers"); 3015 for (cnt = 0; cnt < sizeof (fw->xmt3_dma_reg) / 4; cnt++) { 3016 if (cnt % 8 == 0) { 3017 mdb_printf("\n"); 3018 } 3019 mdb_printf("%08x ", fw->xmt3_dma_reg[cnt]); 3020 } 3021 3022 mdb_printf("\n\nXMT4 Data DMA Registers"); 3023 for (cnt = 0; cnt < sizeof (fw->xmt4_dma_reg) / 4; cnt++) { 3024 if (cnt % 8 == 0) { 3025 mdb_printf("\n"); 3026 } 3027 mdb_printf("%08x ", fw->xmt4_dma_reg[cnt]); 3028 } 3029 3030 mdb_printf("\n\nXMT Data DMA Common Registers"); 3031 for (cnt = 0; cnt < sizeof (fw->xmt_data_dma_reg) / 4; cnt++) { 3032 if (cnt % 8 == 0) { 3033 mdb_printf("\n"); 3034 } 3035 mdb_printf("%08x ", fw->xmt_data_dma_reg[cnt]); 3036 } 3037 3038 mdb_printf("\n\nRCV Thread 0 Data DMA Registers"); 3039 for (cnt = 0; cnt < sizeof (fw->rcvt0_data_dma_reg) / 4; cnt++) { 3040 if (cnt % 8 == 0) { 3041 mdb_printf("\n"); 3042 } 3043 mdb_printf("%08x ", fw->rcvt0_data_dma_reg[cnt]); 3044 } 3045 3046 mdb_printf("\n\nRCV Thread 1 Data DMA Registers"); 3047 for (cnt = 0; cnt < sizeof (fw->rcvt1_data_dma_reg) / 4; cnt++) { 3048 if (cnt % 8 == 0) { 3049 mdb_printf("\n"); 3050 } 3051 mdb_printf("%08x ", fw->rcvt1_data_dma_reg[cnt]); 3052 } 3053 3054 mdb_printf("\n\nRISC GP Registers"); 3055 for (cnt = 0; cnt < sizeof (fw->risc_gp_reg) / 4; cnt++) { 3056 if (cnt % 8 == 0) { 3057 mdb_printf("\n"); 3058 } 3059 mdb_printf("%08x ", fw->risc_gp_reg[cnt]); 3060 } 3061 3062 mdb_printf("\n\nRISC IO Register\n%08x", fw->risc_io); 3063 3064 mdb_printf("\n\nLMC Registers"); 3065 for (cnt = 0; cnt < sizeof (fw->lmc_reg) / 4; cnt++) { 3066 if (cnt % 8 == 0) { 3067 mdb_printf("\n"); 3068 } 3069 mdb_printf("%08x ", fw->lmc_reg[cnt]); 3070 } 3071 3072 mdb_printf("\n\nFPM Hardware Registers"); 3073 for (cnt = 0; cnt < sizeof (fw->fpm_hdw_reg) / 4; cnt++) { 3074 if (cnt % 8 == 0) { 3075 mdb_printf("\n"); 3076 } 3077 mdb_printf("%08x ", fw->fpm_hdw_reg[cnt]); 3078 } 3079 3080 mdb_printf("\n\nFB Hardware Registers"); 3081 for (cnt = 0; cnt < sizeof (fw->fb_hdw_reg) / 4; cnt++) { 3082 if (cnt % 8 == 0) { 3083 mdb_printf("\n"); 3084 } 3085 mdb_printf("%08x ", fw->fb_hdw_reg[cnt]); 3086 } 3087 3088 mdb_printf("\n\nCode RAM"); 3089 for (cnt = 0; cnt < sizeof (fw->code_ram) / 4; cnt++) { 3090 if (cnt % 8 == 0) { 3091 mdb_printf("\n%08x: ", cnt + 0x20000); 3092 } 3093 mdb_printf("%08x ", fw->code_ram[cnt]); 3094 } 3095 3096 mdb_printf("\n\nExternal Memory"); 3097 for (cnt = 0; cnt < ha->fw_ext_memory_size / 4; cnt++) { 3098 if (cnt % 8 == 0) { 3099 mdb_printf("\n%08x: ", cnt + 0x100000); 3100 } 3101 mdb_printf("%08x ", fw->ext_mem[cnt]); 3102 } 3103 3104 mdb_printf("\n[<==END] ISP Debug Dump"); 3105 3106 mdb_printf("\n\nRequest Queue"); 3107 3108 for (cnt = 0; cnt < REQUEST_QUEUE_SIZE / 4; cnt++) { 3109 if (cnt % 8 == 0) { 3110 mdb_printf("\n%08x: ", cnt); 3111 } 3112 mdb_printf("%08x ", fw->req_q[cnt]); 3113 } 3114 3115 mdb_printf("\n\nResponse Queue"); 3116 3117 for (cnt = 0; cnt < RESPONSE_QUEUE_SIZE / 4; cnt++) { 3118 if (cnt % 8 == 0) { 3119 mdb_printf("\n%08x: ", cnt); 3120 } 3121 mdb_printf("%08x ", fw->rsp_q[cnt]); 3122 } 3123 3124 if ((ha->cfg_flags & CFG_ENABLE_FWEXTTRACE) && 3125 (ha->fwexttracebuf.bp != NULL)) { 3126 uint32_t cnt_b = 0; 3127 uint32_t *w32 = ha->fwexttracebuf.bp; 3128 3129 mdb_printf("\n\nExtended Trace Buffer Memory"); 3130 /* show data address as a byte address, data as long words */ 3131 for (cnt = 0; cnt < FWEXTSIZE / 4; cnt++) { 3132 cnt_b = cnt * 4; 3133 if (cnt_b % 32 == 0) { 3134 mdb_printf("\n%08x: ", w32 + cnt_b); 3135 } 3136 mdb_printf("%08x ", fw->ext_trace_buf[cnt]); 3137 } 3138 } 3139 3140 if ((ha->cfg_flags & CFG_ENABLE_FWFCETRACE) && 3141 (ha->fwfcetracebuf.bp != NULL)) { 3142 uint32_t cnt_b = 0; 3143 uint32_t *w32 = ha->fwfcetracebuf.bp; 3144 3145 mdb_printf("\n\nFC Event Trace Buffer Memory"); 3146 /* show data address as a byte address, data as long words */ 3147 for (cnt = 0; cnt < FWFCESIZE / 4; cnt++) { 3148 cnt_b = cnt * 4; 3149 if (cnt_b % 32 == 0) { 3150 mdb_printf("\n%08x: ", w32 + cnt_b); 3151 } 3152 mdb_printf("%08x ", fw->fce_trace_buf[cnt]); 3153 } 3154 } 3155 3156 mdb_free(fw, ha->ql_dump_size); 3157 3158 mdb_printf("\n\nreturn exit\n"); 3159 3160 return (DCMD_OK); 3161 } 3162 3163 /* 3164 * ql_gettrace_dcmd 3165 * prints out the Extended Logging trace buffer 3166 * 3167 * Input: 3168 * addr = User supplied address. (NB: must be an ha) 3169 * flags = mdb flags. 3170 * argc = Number of user supplied args. 3171 * argv = Arg array. 3172 * 3173 * Returns: 3174 * DCMD_OK or DCMD_ERR 3175 * 3176 * Context: 3177 * User context. 3178 * 3179 */ 3180 static int 3181 qlc_gettrace_dcmd(uintptr_t addr, uint_t flags, int argc, const mdb_arg_t *argv) 3182 { 3183 ql_adapter_state_t *ha; 3184 int verbose = 0; 3185 int wrapped = 0; 3186 char *trace_start; 3187 char *trace_end; 3188 char *dump_start = 0; 3189 char *trace_next = 0; 3190 char *dump_current = 0; 3191 el_trace_desc_t *trace_desc; 3192 3193 if ((!(flags & DCMD_ADDRSPEC)) || addr == 0) { 3194 mdb_warn("ql_adapter_state structure addr is required"); 3195 return (DCMD_USAGE); 3196 } 3197 3198 if (mdb_getopts(argc, argv, 'v', MDB_OPT_SETBITS, TRUE, &verbose, 3199 NULL) != argc) { 3200 return (DCMD_USAGE); 3201 } 3202 3203 /* 3204 * Get the adapter state struct which was passed 3205 */ 3206 if ((ha = (ql_adapter_state_t *)mdb_alloc(sizeof (ql_adapter_state_t), 3207 UM_SLEEP)) == NULL) { 3208 mdb_warn("failed to allocate memory for ql_adapter_state\n"); 3209 return (DCMD_OK); 3210 } 3211 3212 if (mdb_vread(ha, sizeof (ql_adapter_state_t), addr) == -1) { 3213 mdb_warn("failed to read ql_adapter_state at %p", addr); 3214 mdb_free(ha, sizeof (ql_adapter_state_t)); 3215 return (DCMD_OK); 3216 } 3217 3218 /* 3219 * If its not a valid trace descriptor then bail out 3220 */ 3221 if (ha->el_trace_desc == NULL) { 3222 mdb_warn("trace descriptor does not exist for instance %d\n", 3223 ha->instance); 3224 mdb_free(ha, sizeof (ql_adapter_state_t)); 3225 return (DCMD_OK); 3226 } else { 3227 trace_desc = (el_trace_desc_t *) 3228 mdb_alloc(sizeof (el_trace_desc_t), UM_SLEEP); 3229 if (mdb_vread(trace_desc, sizeof (el_trace_desc_t), 3230 (uintptr_t)ha->el_trace_desc) == -1) { 3231 mdb_warn("failed to read ql_adapter_state at %p", 3232 addr); 3233 mdb_free(trace_desc, sizeof (el_trace_desc_t)); 3234 mdb_free(ha, sizeof (ql_adapter_state_t)); 3235 return (DCMD_OK); 3236 } 3237 if (trace_desc->trace_buffer == NULL) { 3238 mdb_warn("trace buffer does not exist for " 3239 "instance %d\n", ha->instance); 3240 mdb_free(trace_desc, sizeof (el_trace_desc_t)); 3241 mdb_free(ha, sizeof (ql_adapter_state_t)); 3242 return (DCMD_OK); 3243 } 3244 } 3245 3246 /* Get the trace buffer */ 3247 3248 trace_start = (char *) 3249 mdb_zalloc(trace_desc->trace_buffer_size, UM_SLEEP); 3250 3251 if (mdb_vread(trace_start, trace_desc->trace_buffer_size, 3252 (uintptr_t)trace_desc->trace_buffer) == -1) { 3253 mdb_warn("failed to read trace buffer?)"); 3254 mdb_free(trace_start, trace_desc->trace_buffer_size); 3255 mdb_free(ha, sizeof (ql_adapter_state_t)); 3256 return (DCMD_OK); 3257 } 3258 3259 /* set the end of the trace buffer. */ 3260 trace_end = trace_start + trace_desc->trace_buffer_size; 3261 3262 /* Find the start point of trace. */ 3263 trace_next = trace_start + trace_desc->next; 3264 3265 /* 3266 * If the buffer has not wrapped next will point at a null so 3267 * start is the begining of the buffer. If next points at a char 3268 * then we must traverse the buffer further until a null is detected. 3269 * The location after the null will be the beginning of the oldest 3270 * whole object in the buffer, which we use as the start. 3271 */ 3272 3273 if ((trace_next + EL_BUFFER_RESERVE) >= trace_end) { 3274 dump_start = trace_start; 3275 } else if (*trace_next != '\0') { 3276 dump_start = trace_next + (strlen(trace_next) + 1); 3277 } else { 3278 dump_start = trace_start; 3279 } 3280 3281 dump_current = dump_start; 3282 3283 mdb_printf("\nExtended Logging trace buffer @%x, start @%x, " 3284 "size=%d\n\n", trace_start, dump_current, 3285 trace_desc->trace_buffer_size); 3286 3287 /* Don't run off the end, no matter what. */ 3288 while (((uintptr_t)dump_current - (uintptr_t)trace_start) <= 3289 (uintptr_t)trace_desc->trace_buffer_size) { 3290 /* Show it... */ 3291 mdb_printf("%s", dump_current); 3292 /* Calculate the next and make it the current */ 3293 dump_current += (strlen(dump_current) + 1); 3294 /* check for wrap */ 3295 if ((dump_current + EL_BUFFER_RESERVE) >= trace_end) { 3296 mdb_printf("Wraping %x\n", dump_current); 3297 dump_current = trace_start; 3298 wrapped = 1; 3299 } else if (wrapped) { 3300 /* Don't go past next. */ 3301 if ((trace_start + trace_desc->next) <= dump_current) { 3302 mdb_printf("Done %x", dump_current); 3303 break; 3304 } 3305 } else if (*dump_current == '\0') { 3306 mdb_printf("Done %x(null)", dump_current); 3307 break; 3308 } 3309 } 3310 3311 mdb_free(ha, sizeof (ql_adapter_state_t)); 3312 mdb_free(trace_start, trace_desc->trace_buffer_size); 3313 mdb_free(trace_desc, sizeof (el_trace_desc_t)); 3314 3315 return (DCMD_OK); 3316 } 3317 /* 3318 * ql_doprint 3319 * ql generic function to call the print dcmd 3320 * 3321 * Input: 3322 * addr - address to struct 3323 * prtsting - address to string 3324 * 3325 * Returns: 3326 * WALK_DONE 3327 * 3328 * Context: 3329 * User context. 3330 * 3331 */ 3332 static int32_t 3333 ql_doprint(uintptr_t addr, int8_t *prtstring) 3334 { 3335 struct mdb_arg printarg; 3336 3337 printarg.a_un.a_str = (int8_t *)(mdb_zalloc(strlen(prtstring), 3338 UM_SLEEP)); 3339 printarg.a_type = MDB_TYPE_STRING; 3340 (void) strcpy((int8_t *)(printarg.a_un.a_str), prtstring); 3341 3342 if ((mdb_call_dcmd("print", addr, DCMD_ADDRSPEC, 1, 3343 &printarg)) == -1) { 3344 mdb_warn("ql_doprint: failed print dcmd: %s" 3345 "at addr: %llxh", prtstring, addr); 3346 } 3347 3348 mdb_free((void *)(printarg.a_un.a_str), strlen(prtstring)); 3349 return (WALK_DONE); 3350 } 3351 3352 /* 3353 * ql_dump_flags 3354 * mdb utility to print the flag string 3355 * 3356 * Input: 3357 * flags - flags to print 3358 * strings - text to print when flag is set 3359 * 3360 * Returns: 3361 * 3362 * 3363 * Context: 3364 * User context. 3365 * 3366 */ 3367 static void 3368 ql_dump_flags(uint64_t flags, int8_t **strings) 3369 { 3370 int i, linel, first = 1; 3371 uint64_t mask = 1; 3372 3373 linel = 8; 3374 mdb_printf("\t"); 3375 for (i = 0; i < 64; i++) { 3376 if (strings[i] == NULL) 3377 break; 3378 if (flags & mask) { 3379 if (!first) { 3380 mdb_printf(" | "); 3381 } else { 3382 first = 0; 3383 } 3384 linel += (int32_t)strlen(strings[i]) + 3; 3385 if (linel > 80) { 3386 mdb_printf("\n\t"); 3387 linel = (int32_t)strlen(strings[i]) + 1 + 8; 3388 } 3389 mdb_printf("%s", strings[i]); 3390 } 3391 mask <<= 1; 3392 } 3393 mdb_printf("\n"); 3394 } 3395 3396 /* 3397 * MDB module linkage information 3398 * 3399 * 3400 * dcmd structures for the _mdb_init function 3401 */ 3402 static const mdb_dcmd_t dcmds[] = { 3403 { "qlclinks", NULL, "Prints qlc link information", qlclinks_dcmd }, 3404 { "qlcosc", NULL, "Prints outstanding cmd info", qlc_osc_dcmd }, 3405 { "qlcver", NULL, "Prints driver/mdb version", qlcver_dcmd }, 3406 { "qlc_elog", "[on|off] [<inst #>|all]", "Turns qlc extended logging " 3407 "on / off", qlc_el_dcmd }, 3408 { "qlcstate", ":[-v]", "Prints qlc adapter state information", 3409 qlcstate_dcmd }, 3410 { "qlctgtq", NULL, "Prints qlc target queues", qltgtq_dcmd }, 3411 { "qlcwdog", NULL, "Prints out watchdog linked list", qlc_wdog_dcmd}, 3412 { "qlcgetdump", ":[-v]", "Retrieves the ASCII f/w dump", 3413 qlc_getdump_dcmd }, 3414 { "qlcgettrace", ":[-v]", "Retrieves the ASCII Extended Logging trace", 3415 qlc_gettrace_dcmd }, 3416 { NULL } 3417 }; 3418 3419 /* 3420 * walker structures for the _mdb_init function 3421 */ 3422 static const mdb_walker_t walkers[] = { 3423 { "qlcstates", "walk list of qlc ql_state_t structures", 3424 qlstates_walk_init, qlstates_walk_step, qlstates_walk_fini }, 3425 { "qlcsrbs", "walk list of qlc ql_srb_t strctures", 3426 qlsrb_walk_init, qlsrb_walk_step, qlsrb_walk_fini }, 3427 { "qlclunq", "walk list of qlc ql_lun_t strctures", 3428 qllunq_walk_init, qllunq_walk_step, qllunq_walk_fini }, 3429 { NULL } 3430 }; 3431 3432 static const mdb_modinfo_t ql_mdb_modinfo = { 3433 MDB_API_VERSION, dcmds, walkers 3434 }; 3435 3436 /* 3437 * Registration function which lists the dcmds and walker structures 3438 */ 3439 const mdb_modinfo_t * 3440 _mdb_init(void) 3441 { 3442 return (&ql_mdb_modinfo); 3443 } 3444