1 /* 2 * 3 * CDDL HEADER START 4 * 5 * The contents of this file are subject to the terms of the 6 * Common Development and Distribution License (the "License"). 7 * You may not use this file except in compliance with the License. 8 * 9 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 10 * or http://www.opensolaris.org/os/licensing. 11 * See the License for the specific language governing permissions 12 * and limitations under the License. 13 * 14 * When distributing Covered Code, include this CDDL HEADER in each 15 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 16 * If applicable, add the following below this CDDL HEADER, with the 17 * fields enclosed by brackets "[]" replaced with your own identifying 18 * information: Portions Copyright [yyyy] [name of copyright owner] 19 * 20 * CDDL HEADER END 21 */ 22 /* 23 * Copyright (c) 2003, 2010, Oracle and/or its affiliates. All rights reserved. 24 * Copyright 2017 Joyent, Inc. 25 */ 26 27 /* 28 * Copyright (c) 2010, Intel Corporation. 29 * All rights reserved. 30 */ 31 32 /* Copyright (c) 1988 AT&T */ 33 /* All Rights Reserved */ 34 35 #include "dis_tables.h" 36 37 /* BEGIN CSTYLED */ 38 39 /* 40 * Disassembly begins in dis_distable, which is equivalent to the One-byte 41 * Opcode Map in the Intel IA32 ISA Reference (page A-6 in my copy). The 42 * decoding loops then traverse out through the other tables as necessary to 43 * decode a given instruction. 44 * 45 * The behavior of this file can be controlled by one of the following flags: 46 * 47 * DIS_TEXT Include text for disassembly 48 * DIS_MEM Include memory-size calculations 49 * 50 * Either or both of these can be defined. 51 * 52 * This file is not, and will never be, cstyled. If anything, the tables should 53 * be taken out another tab stop or two so nothing overlaps. 54 */ 55 56 /* 57 * These functions must be provided for the consumer to do disassembly. 58 */ 59 #ifdef DIS_TEXT 60 extern char *strncpy(char *, const char *, size_t); 61 extern size_t strlen(const char *); 62 extern int strcmp(const char *, const char *); 63 extern int strncmp(const char *, const char *, size_t); 64 extern size_t strlcat(char *, const char *, size_t); 65 #endif 66 67 68 #define TERM 0 /* used to indicate that the 'indirect' */ 69 /* field terminates - no pointer. */ 70 71 /* Used to decode instructions. */ 72 typedef struct instable { 73 struct instable *it_indirect; /* for decode op codes */ 74 uchar_t it_adrmode; 75 #ifdef DIS_TEXT 76 char it_name[NCPS]; 77 uint_t it_suffix:1; /* mnem + "w", "l", or "d" */ 78 #endif 79 #ifdef DIS_MEM 80 uint_t it_size:16; 81 #endif 82 uint_t it_invalid64:1; /* opcode invalid in amd64 */ 83 uint_t it_always64:1; /* 64 bit when in 64 bit mode */ 84 uint_t it_invalid32:1; /* invalid in IA32 */ 85 uint_t it_stackop:1; /* push/pop stack operation */ 86 uint_t it_vexwoxmm:1; /* VEX instructions that don't use XMM/YMM */ 87 uint_t it_avxsuf:1; /* AVX suffix required */ 88 uint_t it_vexopmask:1; /* VEX inst. that use opmask */ 89 } instable_t; 90 91 /* 92 * Instruction formats. 93 */ 94 enum { 95 UNKNOWN, 96 MRw, 97 IMlw, 98 IMw, 99 IR, 100 OA, 101 AO, 102 MS, 103 SM, 104 Mv, 105 Mw, 106 M, /* register or memory */ 107 MG9, /* register or memory in group 9 (prefix optional) */ 108 Mb, /* register or memory, always byte sized */ 109 MO, /* memory only (no registers) */ 110 PREF, 111 SWAPGS_RDTSCP, 112 MONITOR_MWAIT, 113 R, 114 RA, 115 SEG, 116 MR, 117 RM, 118 RM_66r, /* RM, but with a required 0x66 prefix */ 119 IA, 120 MA, 121 SD, 122 AD, 123 SA, 124 D, 125 INM, 126 SO, 127 BD, 128 I, 129 P, 130 V, 131 DSHIFT, /* for double shift that has an 8-bit immediate */ 132 U, 133 OVERRIDE, 134 NORM, /* instructions w/o ModR/M byte, no memory access */ 135 IMPLMEM, /* instructions w/o ModR/M byte, implicit mem access */ 136 O, /* for call */ 137 JTAB, /* jump table */ 138 IMUL, /* for 186 iimul instr */ 139 CBW, /* so data16 can be evaluated for cbw and variants */ 140 MvI, /* for 186 logicals */ 141 ENTER, /* for 186 enter instr */ 142 RMw, /* for 286 arpl instr */ 143 Ib, /* for push immediate byte */ 144 F, /* for 287 instructions */ 145 FF, /* for 287 instructions */ 146 FFC, /* for 287 instructions */ 147 DM, /* 16-bit data */ 148 AM, /* 16-bit addr */ 149 LSEG, /* for 3-bit seg reg encoding */ 150 MIb, /* for 386 logicals */ 151 SREG, /* for 386 special registers */ 152 PREFIX, /* a REP instruction prefix */ 153 LOCK, /* a LOCK instruction prefix */ 154 INT3, /* The int 3 instruction, which has a fake operand */ 155 INTx, /* The normal int instruction, with explicit int num */ 156 DSHIFTcl, /* for double shift that implicitly uses %cl */ 157 CWD, /* so data16 can be evaluated for cwd and variants */ 158 RET, /* single immediate 16-bit operand */ 159 MOVZ, /* for movs and movz, with different size operands */ 160 CRC32, /* for crc32, with different size operands */ 161 XADDB, /* for xaddb */ 162 MOVSXZ, /* AMD64 mov sign extend 32 to 64 bit instruction */ 163 MOVBE, /* movbe instruction */ 164 165 /* 166 * MMX/SIMD addressing modes. 167 */ 168 169 MMO, /* Prefixable MMX/SIMD-Int mm/mem -> mm */ 170 MMOIMPL, /* Prefixable MMX/SIMD-Int mm -> mm (mem) */ 171 MMO3P, /* Prefixable MMX/SIMD-Int mm -> r32,imm8 */ 172 MMOM3, /* Prefixable MMX/SIMD-Int mm -> r32 */ 173 MMOS, /* Prefixable MMX/SIMD-Int mm -> mm/mem */ 174 MMOMS, /* Prefixable MMX/SIMD-Int mm -> mem */ 175 MMOPM, /* MMX/SIMD-Int mm/mem -> mm,imm8 */ 176 MMOPM_66o, /* MMX/SIMD-Int 0x66 optional mm/mem -> mm,imm8 */ 177 MMOPRM, /* Prefixable MMX/SIMD-Int r32/mem -> mm,imm8 */ 178 MMOSH, /* Prefixable MMX mm,imm8 */ 179 MM, /* MMX/SIMD-Int mm/mem -> mm */ 180 MMS, /* MMX/SIMD-Int mm -> mm/mem */ 181 MMSH, /* MMX mm,imm8 */ 182 XMMO, /* Prefixable SIMD xmm/mem -> xmm */ 183 XMMOS, /* Prefixable SIMD xmm -> xmm/mem */ 184 XMMOPM, /* Prefixable SIMD xmm/mem w/to xmm,imm8 */ 185 XMMOMX, /* Prefixable SIMD mm/mem -> xmm */ 186 XMMOX3, /* Prefixable SIMD xmm -> r32 */ 187 XMMOXMM, /* Prefixable SIMD xmm/mem -> mm */ 188 XMMOM, /* Prefixable SIMD xmm -> mem */ 189 XMMOMS, /* Prefixable SIMD mem -> xmm */ 190 XMM, /* SIMD xmm/mem -> xmm */ 191 XMM_66r, /* SIMD 0x66 prefix required xmm/mem -> xmm */ 192 XMM_66o, /* SIMD 0x66 prefix optional xmm/mem -> xmm */ 193 XMMXIMPL, /* SIMD xmm -> xmm (mem) */ 194 XMM3P, /* SIMD xmm -> r32,imm8 */ 195 XMM3PM_66r, /* SIMD 0x66 prefix required xmm -> r32/mem,imm8 */ 196 XMMP, /* SIMD xmm/mem w/to xmm,imm8 */ 197 XMMP_66o, /* SIMD 0x66 prefix optional xmm/mem w/to xmm,imm8 */ 198 XMMP_66r, /* SIMD 0x66 prefix required xmm/mem w/to xmm,imm8 */ 199 XMMPRM, /* SIMD r32/mem -> xmm,imm8 */ 200 XMMPRM_66r, /* SIMD 0x66 prefix required r32/mem -> xmm,imm8 */ 201 XMMS, /* SIMD xmm -> xmm/mem */ 202 XMMM, /* SIMD mem -> xmm */ 203 XMMM_66r, /* SIMD 0x66 prefix required mem -> xmm */ 204 XMMMS, /* SIMD xmm -> mem */ 205 XMM3MX, /* SIMD r32/mem -> xmm */ 206 XMM3MXS, /* SIMD xmm -> r32/mem */ 207 XMMSH, /* SIMD xmm,imm8 */ 208 XMMXM3, /* SIMD xmm/mem -> r32 */ 209 XMMX3, /* SIMD xmm -> r32 */ 210 XMMXMM, /* SIMD xmm/mem -> mm */ 211 XMMMX, /* SIMD mm -> xmm */ 212 XMMXM, /* SIMD xmm -> mm */ 213 XMMX2I, /* SIMD xmm -> xmm, imm, imm */ 214 XMM2I, /* SIMD xmm, imm, imm */ 215 XMMFENCE, /* SIMD lfence or mfence */ 216 XMMSFNC, /* SIMD sfence (none or mem) */ 217 XGETBV_XSETBV, 218 VEX_NONE, /* VEX no operand */ 219 VEX_MO, /* VEX mod_rm -> implicit reg */ 220 VEX_RMrX, /* VEX VEX.vvvv, mod_rm -> mod_reg */ 221 VEX_VRMrX, /* VEX mod_rm, VEX.vvvv -> mod_rm */ 222 VEX_RRX, /* VEX VEX.vvvv, mod_reg -> mod_rm */ 223 VEX_RMRX, /* VEX VEX.vvvv, mod_rm, imm8[7:4] -> mod_reg */ 224 VEX_MX, /* VEX mod_rm -> mod_reg */ 225 VEX_MXI, /* VEX mod_rm, imm8 -> mod_reg */ 226 VEX_XXI, /* VEX mod_rm, imm8 -> VEX.vvvv */ 227 VEX_MR, /* VEX mod_rm -> mod_reg */ 228 VEX_RRI, /* VEX mod_reg, mod_rm -> implicit(eflags/r32) */ 229 VEX_RX, /* VEX mod_reg -> mod_rm */ 230 VEX_KRR, /* VEX mod_rm -> mod_reg */ 231 VEX_KMR, /* VEX mod_reg -> mod_rm */ 232 VEX_KRM, /* VEX mod_rm -> mod_reg */ 233 VEX_RR, /* VEX mod_rm -> mod_reg */ 234 VEX_RRi, /* VEX mod_rm, imm8 -> mod_reg */ 235 VEX_RM, /* VEX mod_reg -> mod_rm */ 236 VEX_RIM, /* VEX mod_reg, imm8 -> mod_rm */ 237 VEX_RRM, /* VEX VEX.vvvv, mod_reg -> mod_rm */ 238 VEX_RMX, /* VEX VEX.vvvv, mod_rm -> mod_reg */ 239 VEX_SbVM, /* VEX SIB, VEX.vvvv -> mod_rm */ 240 VMx, /* vmcall/vmlaunch/vmresume/vmxoff */ 241 VMxo, /* VMx instruction with optional prefix */ 242 SVM, /* AMD SVM instructions */ 243 BLS, /* BLSR, BLSMSK, BLSI */ 244 FMA, /* FMA instructions, all VEX_RMrX */ 245 ADX, /* ADX instructions, support REX.w, mod_rm->mod_reg */ 246 EVEX_RX, /* EVEX mod_reg -> mod_rm */ 247 EVEX_MX, /* EVEX mod_rm -> mod_reg */ 248 EVEX_RMrX /* EVEX EVEX.vvvv, mod_rm -> mod_reg */ 249 }; 250 251 /* 252 * VEX prefixes 253 */ 254 #define VEX_2bytes 0xC5 /* the first byte of two-byte form */ 255 #define VEX_3bytes 0xC4 /* the first byte of three-byte form */ 256 257 #define FILL 0x90 /* Fill byte used for alignment (nop) */ 258 259 /* 260 ** Register numbers for the i386 261 */ 262 #define EAX_REGNO 0 263 #define ECX_REGNO 1 264 #define EDX_REGNO 2 265 #define EBX_REGNO 3 266 #define ESP_REGNO 4 267 #define EBP_REGNO 5 268 #define ESI_REGNO 6 269 #define EDI_REGNO 7 270 271 /* 272 * modes for immediate values 273 */ 274 #define MODE_NONE 0 275 #define MODE_IPREL 1 /* signed IP relative value */ 276 #define MODE_SIGNED 2 /* sign extended immediate */ 277 #define MODE_IMPLIED 3 /* constant value implied from opcode */ 278 #define MODE_OFFSET 4 /* offset part of an address */ 279 #define MODE_RIPREL 5 /* like IPREL, but from %rip (amd64) */ 280 281 /* 282 * The letters used in these macros are: 283 * IND - indirect to another to another table 284 * "T" - means to Terminate indirections (this is the final opcode) 285 * "S" - means "operand length suffix required" 286 * "Sa" - means AVX2 suffix (d/q) required 287 * "NS" - means "no suffix" which is the operand length suffix of the opcode 288 * "Z" - means instruction size arg required 289 * "u" - means the opcode is invalid in IA32 but valid in amd64 290 * "x" - means the opcode is invalid in amd64, but not IA32 291 * "y" - means the operand size is always 64 bits in 64 bit mode 292 * "p" - means push/pop stack operation 293 * "vr" - means VEX instruction that operates on normal registers, not fpu 294 * "vo" - means VEX instruction that operates on opmask registers, not fpu 295 */ 296 297 #if defined(DIS_TEXT) && defined(DIS_MEM) 298 #define IND(table) {(instable_t *)table, 0, "", 0, 0, 0, 0, 0, 0} 299 #define INDx(table) {(instable_t *)table, 0, "", 0, 0, 1, 0, 0, 0} 300 #define TNS(name, amode) {TERM, amode, name, 0, 0, 0, 0, 0, 0} 301 #define TNSu(name, amode) {TERM, amode, name, 0, 0, 0, 0, 1, 0} 302 #define TNSx(name, amode) {TERM, amode, name, 0, 0, 1, 0, 0, 0} 303 #define TNSy(name, amode) {TERM, amode, name, 0, 0, 0, 1, 0, 0} 304 #define TNSyp(name, amode) {TERM, amode, name, 0, 0, 0, 1, 0, 1} 305 #define TNSZ(name, amode, sz) {TERM, amode, name, 0, sz, 0, 0, 0, 0} 306 #define TNSZy(name, amode, sz) {TERM, amode, name, 0, sz, 0, 1, 0, 0} 307 #define TNSZvr(name, amode, sz) {TERM, amode, name, 0, sz, 0, 0, 0, 0, 1} 308 #define TSavo(name, amode) {TERM, amode, name, 1, 0, 0, 0, 0, 0, 0, 1, 1} 309 #define TSvo(name, amode) {TERM, amode, name, 1, 0, 0, 0, 0, 0, 0, 0, 1} 310 #define TS(name, amode) {TERM, amode, name, 1, 0, 0, 0, 0, 0} 311 #define TSx(name, amode) {TERM, amode, name, 1, 0, 1, 0, 0, 0} 312 #define TSy(name, amode) {TERM, amode, name, 1, 0, 0, 1, 0, 0} 313 #define TSp(name, amode) {TERM, amode, name, 1, 0, 0, 0, 0, 1} 314 #define TSZ(name, amode, sz) {TERM, amode, name, 1, sz, 0, 0, 0, 0} 315 #define TSaZ(name, amode, sz) {TERM, amode, name, 1, sz, 0, 0, 0, 0, 0, 1} 316 #define TSZx(name, amode, sz) {TERM, amode, name, 1, sz, 1, 0, 0, 0} 317 #define TSZy(name, amode, sz) {TERM, amode, name, 1, sz, 0, 1, 0, 0} 318 #define INVALID {TERM, UNKNOWN, "", 0, 0, 0, 0, 0} 319 #elif defined(DIS_TEXT) 320 #define IND(table) {(instable_t *)table, 0, "", 0, 0, 0, 0, 0} 321 #define INDx(table) {(instable_t *)table, 0, "", 0, 1, 0, 0, 0} 322 #define TNS(name, amode) {TERM, amode, name, 0, 0, 0, 0, 0} 323 #define TNSu(name, amode) {TERM, amode, name, 0, 0, 0, 1, 0} 324 #define TNSx(name, amode) {TERM, amode, name, 0, 1, 0, 0, 0} 325 #define TNSy(name, amode) {TERM, amode, name, 0, 0, 1, 0, 0} 326 #define TNSyp(name, amode) {TERM, amode, name, 0, 0, 1, 0, 1} 327 #define TNSZ(name, amode, sz) {TERM, amode, name, 0, 0, 0, 0, 0} 328 #define TNSZy(name, amode, sz) {TERM, amode, name, 0, 0, 1, 0, 0} 329 #define TNSZvr(name, amode, sz) {TERM, amode, name, 0, 0, 0, 0, 0, 1} 330 #define TSvo(name, amode) {TERM, amode, name, 1, 0, 0, 0, 0, 0, 0, 1} 331 #define TS(name, amode) {TERM, amode, name, 1, 0, 0, 0, 0} 332 #define TSx(name, amode) {TERM, amode, name, 1, 1, 0, 0, 0} 333 #define TSy(name, amode) {TERM, amode, name, 1, 0, 1, 0, 0} 334 #define TSp(name, amode) {TERM, amode, name, 1, 0, 0, 0, 1} 335 #define TSZ(name, amode, sz) {TERM, amode, name, 1, 0, 0, 0, 0} 336 #define TSaZ(name, amode, sz) {TERM, amode, name, 1, 0, 0, 0, 0, 0, 1} 337 #define TSZx(name, amode, sz) {TERM, amode, name, 1, 1, 0, 0, 0} 338 #define TSZy(name, amode, sz) {TERM, amode, name, 1, 0, 1, 0, 0} 339 #define INVALID {TERM, UNKNOWN, "", 0, 0, 0, 0, 0} 340 #elif defined(DIS_MEM) 341 #define IND(table) {(instable_t *)table, 0, 0, 0, 0, 0, 0} 342 #define INDx(table) {(instable_t *)table, 0, 0, 1, 0, 0, 0} 343 #define TNS(name, amode) {TERM, amode, 0, 0, 0, 0, 0} 344 #define TNSu(name, amode) {TERM, amode, 0, 0, 0, 1, 0} 345 #define TNSy(name, amode) {TERM, amode, 0, 0, 1, 0, 0} 346 #define TNSyp(name, amode) {TERM, amode, 0, 0, 1, 0, 1} 347 #define TNSx(name, amode) {TERM, amode, 0, 1, 0, 0, 0} 348 #define TNSZ(name, amode, sz) {TERM, amode, sz, 0, 0, 0, 0} 349 #define TNSZy(name, amode, sz) {TERM, amode, sz, 0, 1, 0, 0} 350 #define TNSZvr(name, amode, sz) {TERM, amode, sz, 0, 0, 0, 0, 1} 351 #define TSvo(name, amode) {TERM, amode, 0, 0, 0, 0, 0, 0, 0, 1} 352 #define TS(name, amode) {TERM, amode, 0, 0, 0, 0, 0} 353 #define TSx(name, amode) {TERM, amode, 0, 1, 0, 0, 0} 354 #define TSy(name, amode) {TERM, amode, 0, 0, 1, 0, 0} 355 #define TSp(name, amode) {TERM, amode, 0, 0, 0, 0, 1} 356 #define TSZ(name, amode, sz) {TERM, amode, sz, 0, 0, 0, 0} 357 #define TSaZ(name, amode, sz) {TERM, amode, sz, 0, 0, 0, 0, 0, 1} 358 #define TSZx(name, amode, sz) {TERM, amode, sz, 1, 0, 0, 0} 359 #define TSZy(name, amode, sz) {TERM, amode, sz, 0, 1, 0, 0} 360 #define INVALID {TERM, UNKNOWN, 0, 0, 0, 0, 0} 361 #else 362 #define IND(table) {(instable_t *)table, 0, 0, 0, 0, 0} 363 #define INDx(table) {(instable_t *)table, 0, 1, 0, 0, 0} 364 #define TNS(name, amode) {TERM, amode, 0, 0, 0, 0} 365 #define TNSu(name, amode) {TERM, amode, 0, 0, 1, 0} 366 #define TNSy(name, amode) {TERM, amode, 0, 1, 0, 0} 367 #define TNSyp(name, amode) {TERM, amode, 0, 1, 0, 1} 368 #define TNSx(name, amode) {TERM, amode, 1, 0, 0, 0} 369 #define TNSZ(name, amode, sz) {TERM, amode, 0, 0, 0, 0} 370 #define TNSZy(name, amode, sz) {TERM, amode, 0, 1, 0, 0} 371 #define TNSZvr(name, amode, sz) {TERM, amode, 0, 0, 0, 0, 1} 372 #define TSvo(name, amode) {TERM, amode, 0, 0, 0, 0, 0, 0, 1} 373 #define TS(name, amode) {TERM, amode, 0, 0, 0, 0} 374 #define TSx(name, amode) {TERM, amode, 1, 0, 0, 0} 375 #define TSy(name, amode) {TERM, amode, 0, 1, 0, 0} 376 #define TSp(name, amode) {TERM, amode, 0, 0, 0, 1} 377 #define TSZ(name, amode, sz) {TERM, amode, 0, 0, 0, 0} 378 #define TSaZ(name, amode, sz) {TERM, amode, 0, 0, 0, 0, 0, 1} 379 #define TSZx(name, amode, sz) {TERM, amode, 1, 0, 0, 0} 380 #define TSZy(name, amode, sz) {TERM, amode, 0, 1, 0, 0} 381 #define INVALID {TERM, UNKNOWN, 0, 0, 0, 0} 382 #endif 383 384 #ifdef DIS_TEXT 385 /* 386 * this decodes the r_m field for mode's 0, 1, 2 in 16 bit mode 387 */ 388 const char *const dis_addr16[3][8] = { 389 "(%bx,%si)", "(%bx,%di)", "(%bp,%si)", "(%bp,%di)", "(%si)", "(%di)", "", 390 "(%bx)", 391 "(%bx,%si)", "(%bx,%di)", "(%bp,%si)", "(%bp,%di)", "(%si)", "(%di", "(%bp)", 392 "(%bx)", 393 "(%bx,%si)", "(%bx,%di)", "(%bp,%si)", "(%bp,%di)", "(%si)", "(%di)", "(%bp)", 394 "(%bx)", 395 }; 396 397 398 /* 399 * This decodes 32 bit addressing mode r_m field for modes 0, 1, 2 400 */ 401 const char *const dis_addr32_mode0[16] = { 402 "(%eax)", "(%ecx)", "(%edx)", "(%ebx)", "", "", "(%esi)", "(%edi)", 403 "(%r8d)", "(%r9d)", "(%r10d)", "(%r11d)", "", "", "(%r14d)", "(%r15d)" 404 }; 405 406 const char *const dis_addr32_mode12[16] = { 407 "(%eax)", "(%ecx)", "(%edx)", "(%ebx)", "", "(%ebp)", "(%esi)", "(%edi)", 408 "(%r8d)", "(%r9d)", "(%r10d)", "(%r11d)", "", "(%r13d)", "(%r14d)", "(%r15d)" 409 }; 410 411 /* 412 * This decodes 64 bit addressing mode r_m field for modes 0, 1, 2 413 */ 414 const char *const dis_addr64_mode0[16] = { 415 "(%rax)", "(%rcx)", "(%rdx)", "(%rbx)", "", "(%rip)", "(%rsi)", "(%rdi)", 416 "(%r8)", "(%r9)", "(%r10)", "(%r11)", "(%r12)", "(%rip)", "(%r14)", "(%r15)" 417 }; 418 const char *const dis_addr64_mode12[16] = { 419 "(%rax)", "(%rcx)", "(%rdx)", "(%rbx)", "", "(%rbp)", "(%rsi)", "(%rdi)", 420 "(%r8)", "(%r9)", "(%r10)", "(%r11)", "(%r12)", "(%r13)", "(%r14)", "(%r15)" 421 }; 422 423 /* 424 * decode for scale from SIB byte 425 */ 426 const char *const dis_scale_factor[4] = { ")", ",2)", ",4)", ",8)" }; 427 428 /* 429 * decode for scale from VSIB byte, note that we always include the scale factor 430 * to match gas. 431 */ 432 const char *const dis_vscale_factor[4] = { ",1)", ",2)", ",4)", ",8)" }; 433 434 /* 435 * register decoding for normal references to registers (ie. not addressing) 436 */ 437 const char *const dis_REG8[16] = { 438 "%al", "%cl", "%dl", "%bl", "%ah", "%ch", "%dh", "%bh", 439 "%r8b", "%r9b", "%r10b", "%r11b", "%r12b", "%r13b", "%r14b", "%r15b" 440 }; 441 442 const char *const dis_REG8_REX[16] = { 443 "%al", "%cl", "%dl", "%bl", "%spl", "%bpl", "%sil", "%dil", 444 "%r8b", "%r9b", "%r10b", "%r11b", "%r12b", "%r13b", "%r14b", "%r15b" 445 }; 446 447 const char *const dis_REG16[16] = { 448 "%ax", "%cx", "%dx", "%bx", "%sp", "%bp", "%si", "%di", 449 "%r8w", "%r9w", "%r10w", "%r11w", "%r12w", "%r13w", "%r14w", "%r15w" 450 }; 451 452 const char *const dis_REG32[16] = { 453 "%eax", "%ecx", "%edx", "%ebx", "%esp", "%ebp", "%esi", "%edi", 454 "%r8d", "%r9d", "%r10d", "%r11d", "%r12d", "%r13d", "%r14d", "%r15d" 455 }; 456 457 const char *const dis_REG64[16] = { 458 "%rax", "%rcx", "%rdx", "%rbx", "%rsp", "%rbp", "%rsi", "%rdi", 459 "%r8", "%r9", "%r10", "%r11", "%r12", "%r13", "%r14", "%r15" 460 }; 461 462 const char *const dis_DEBUGREG[16] = { 463 "%db0", "%db1", "%db2", "%db3", "%db4", "%db5", "%db6", "%db7", 464 "%db8", "%db9", "%db10", "%db11", "%db12", "%db13", "%db14", "%db15" 465 }; 466 467 const char *const dis_CONTROLREG[16] = { 468 "%cr0", "%cr1", "%cr2", "%cr3", "%cr4", "%cr5?", "%cr6?", "%cr7?", 469 "%cr8", "%cr9?", "%cr10?", "%cr11?", "%cr12?", "%cr13?", "%cr14?", "%cr15?" 470 }; 471 472 const char *const dis_TESTREG[16] = { 473 "%tr0?", "%tr1?", "%tr2?", "%tr3", "%tr4", "%tr5", "%tr6", "%tr7", 474 "%tr0?", "%tr1?", "%tr2?", "%tr3", "%tr4", "%tr5", "%tr6", "%tr7" 475 }; 476 477 const char *const dis_MMREG[16] = { 478 "%mm0", "%mm1", "%mm2", "%mm3", "%mm4", "%mm5", "%mm6", "%mm7", 479 "%mm0", "%mm1", "%mm2", "%mm3", "%mm4", "%mm5", "%mm6", "%mm7" 480 }; 481 482 const char *const dis_XMMREG[32] = { 483 "%xmm0", "%xmm1", "%xmm2", "%xmm3", 484 "%xmm4", "%xmm5", "%xmm6", "%xmm7", 485 "%xmm8", "%xmm9", "%xmm10", "%xmm11", 486 "%xmm12", "%xmm13", "%xmm14", "%xmm15", 487 "%xmm16", "%xmm17", "%xmm18", "%xmm19", 488 "%xmm20", "%xmm21", "%xmm22", "%xmm23", 489 "%xmm24", "%xmm25", "%xmm26", "%xmm27", 490 "%xmm28", "%xmm29", "%xmm30", "%xmm31", 491 }; 492 493 const char *const dis_YMMREG[32] = { 494 "%ymm0", "%ymm1", "%ymm2", "%ymm3", 495 "%ymm4", "%ymm5", "%ymm6", "%ymm7", 496 "%ymm8", "%ymm9", "%ymm10", "%ymm11", 497 "%ymm12", "%ymm13", "%ymm14", "%ymm15", 498 "%ymm16", "%ymm17", "%ymm18", "%ymm19", 499 "%ymm20", "%ymm21", "%ymm22", "%ymm23", 500 "%ymm24", "%ymm25", "%ymm26", "%ymm27", 501 "%ymm28", "%ymm29", "%ymm30", "%ymm31", 502 }; 503 504 const char *const dis_ZMMREG[32] = { 505 "%zmm0", "%zmm1", "%zmm2", "%zmm3", 506 "%zmm4", "%zmm5", "%zmm6", "%zmm7", 507 "%zmm8", "%zmm9", "%zmm10", "%zmm11", 508 "%zmm12", "%zmm13", "%zmm14", "%zmm15", 509 "%zmm16", "%zmm17", "%zmm18", "%zmm19", 510 "%zmm20", "%zmm21", "%zmm22", "%zmm23", 511 "%zmm24", "%zmm25", "%zmm26", "%zmm27", 512 "%zmm28", "%zmm29", "%zmm30", "%zmm31", 513 }; 514 515 const char *const dis_KOPMASKREG[8] = { 516 "%k0", "%k1", "%k2", "%k3", "%k4", "%k5", "%k6", "%k7" 517 }; 518 519 const char *const dis_SEGREG[16] = { 520 "%es", "%cs", "%ss", "%ds", "%fs", "%gs", "<reserved>", "<reserved>", 521 "%es", "%cs", "%ss", "%ds", "%fs", "%gs", "<reserved>", "<reserved>" 522 }; 523 524 /* 525 * SIMD predicate suffixes 526 */ 527 const char *const dis_PREDSUFFIX[8] = { 528 "eq", "lt", "le", "unord", "neq", "nlt", "nle", "ord" 529 }; 530 531 const char *const dis_AVXvgrp7[3][8] = { 532 /*0 1 2 3 4 5 6 7*/ 533 /*71*/ {"", "", "vpsrlw", "", "vpsraw", "", "vpsllw", ""}, 534 /*72*/ {"", "", "vpsrld", "", "vpsrad", "", "vpslld", ""}, 535 /*73*/ {"", "", "vpsrlq", "vpsrldq", "", "", "vpsllq", "vpslldq"} 536 }; 537 538 #endif /* DIS_TEXT */ 539 540 /* 541 * "decode table" for 64 bit mode MOVSXD instruction (opcode 0x63) 542 */ 543 const instable_t dis_opMOVSLD = TNS("movslq",MOVSXZ); 544 545 /* 546 * "decode table" for pause and clflush instructions 547 */ 548 const instable_t dis_opPause = TNS("pause", NORM); 549 550 /* 551 * Decode table for 0x0F00 opcodes 552 */ 553 const instable_t dis_op0F00[8] = { 554 555 /* [0] */ TNS("sldt",M), TNS("str",M), TNSy("lldt",M), TNSy("ltr",M), 556 /* [4] */ TNSZ("verr",M,2), TNSZ("verw",M,2), INVALID, INVALID, 557 }; 558 559 560 /* 561 * Decode table for 0x0F01 opcodes 562 */ 563 const instable_t dis_op0F01[8] = { 564 565 /* [0] */ TNSZ("sgdt",VMx,6), TNSZ("sidt",MONITOR_MWAIT,6), TNSZ("lgdt",XGETBV_XSETBV,6), TNSZ("lidt",SVM,6), 566 /* [4] */ TNSZ("smsw",M,2), INVALID, TNSZ("lmsw",M,2), TNS("invlpg",SWAPGS_RDTSCP), 567 }; 568 569 /* 570 * Decode table for 0x0F18 opcodes -- SIMD prefetch 571 */ 572 const instable_t dis_op0F18[8] = { 573 574 /* [0] */ TNS("prefetchnta",PREF),TNS("prefetcht0",PREF), TNS("prefetcht1",PREF), TNS("prefetcht2",PREF), 575 /* [4] */ INVALID, INVALID, INVALID, INVALID, 576 }; 577 578 /* 579 * Decode table for 0x0FAE opcodes -- SIMD state save/restore 580 */ 581 const instable_t dis_op0FAE[8] = { 582 /* [0] */ TNSZ("fxsave",M,512), TNSZ("fxrstor",M,512), TNS("ldmxcsr",M), TNS("stmxcsr",M), 583 /* [4] */ TNSZ("xsave",M,512), TNS("lfence",XMMFENCE), TNS("mfence",XMMFENCE), TNS("sfence",XMMSFNC), 584 }; 585 586 /* 587 * Decode table for 0x0FBA opcodes 588 */ 589 590 const instable_t dis_op0FBA[8] = { 591 592 /* [0] */ INVALID, INVALID, INVALID, INVALID, 593 /* [4] */ TS("bt",MIb), TS("bts",MIb), TS("btr",MIb), TS("btc",MIb), 594 }; 595 596 /* 597 * Decode table for 0x0FC7 opcode (group 9) 598 */ 599 600 const instable_t dis_op0FC7[8] = { 601 602 /* [0] */ INVALID, TNS("cmpxchg8b",M), INVALID, TNS("xrstors",MG9), 603 /* [4] */ TNS("xsavec",MG9), TNS("xsaves",MG9), TNS("vmptrld",MG9), TNS("vmptrst",MG9), 604 }; 605 606 /* 607 * Decode table for 0x0FC7 opcode (group 9) mode 3 608 */ 609 610 const instable_t dis_op0FC7m3[8] = { 611 612 /* [0] */ INVALID, INVALID, INVALID, INVALID, 613 /* [4] */ INVALID, INVALID, TNS("rdrand",MG9), TNS("rdseed", MG9), 614 }; 615 616 /* 617 * Decode table for 0x0FC7 opcode with 0x66 prefix 618 */ 619 620 const instable_t dis_op660FC7[8] = { 621 622 /* [0] */ INVALID, INVALID, INVALID, INVALID, 623 /* [4] */ INVALID, INVALID, TNS("vmclear",M), INVALID, 624 }; 625 626 /* 627 * Decode table for 0x0FC7 opcode with 0xF3 prefix 628 */ 629 630 const instable_t dis_opF30FC7[8] = { 631 632 /* [0] */ INVALID, INVALID, INVALID, INVALID, 633 /* [4] */ INVALID, INVALID, TNS("vmxon",M), INVALID, 634 }; 635 636 /* 637 * Decode table for 0x0FC8 opcode -- 486 bswap instruction 638 * 639 *bit pattern: 0000 1111 1100 1reg 640 */ 641 const instable_t dis_op0FC8[4] = { 642 /* [0] */ TNS("bswap",R), INVALID, INVALID, INVALID, 643 }; 644 645 /* 646 * Decode table for 0x0F71, 0x0F72, and 0x0F73 opcodes -- MMX instructions 647 */ 648 const instable_t dis_op0F7123[4][8] = { 649 { 650 /* [70].0 */ INVALID, INVALID, INVALID, INVALID, 651 /* .4 */ INVALID, INVALID, INVALID, INVALID, 652 }, { 653 /* [71].0 */ INVALID, INVALID, TNS("psrlw",MMOSH), INVALID, 654 /* .4 */ TNS("psraw",MMOSH), INVALID, TNS("psllw",MMOSH), INVALID, 655 }, { 656 /* [72].0 */ INVALID, INVALID, TNS("psrld",MMOSH), INVALID, 657 /* .4 */ TNS("psrad",MMOSH), INVALID, TNS("pslld",MMOSH), INVALID, 658 }, { 659 /* [73].0 */ INVALID, INVALID, TNS("psrlq",MMOSH), TNS("INVALID",MMOSH), 660 /* .4 */ INVALID, INVALID, TNS("psllq",MMOSH), TNS("INVALID",MMOSH), 661 } }; 662 663 /* 664 * Decode table for SIMD extensions to above 0x0F71-0x0F73 opcodes. 665 */ 666 const instable_t dis_opSIMD7123[32] = { 667 /* [70].0 */ INVALID, INVALID, INVALID, INVALID, 668 /* .4 */ INVALID, INVALID, INVALID, INVALID, 669 670 /* [71].0 */ INVALID, INVALID, TNS("psrlw",XMMSH), INVALID, 671 /* .4 */ TNS("psraw",XMMSH), INVALID, TNS("psllw",XMMSH), INVALID, 672 673 /* [72].0 */ INVALID, INVALID, TNS("psrld",XMMSH), INVALID, 674 /* .4 */ TNS("psrad",XMMSH), INVALID, TNS("pslld",XMMSH), INVALID, 675 676 /* [73].0 */ INVALID, INVALID, TNS("psrlq",XMMSH), TNS("psrldq",XMMSH), 677 /* .4 */ INVALID, INVALID, TNS("psllq",XMMSH), TNS("pslldq",XMMSH), 678 }; 679 680 /* 681 * SIMD instructions have been wedged into the existing IA32 instruction 682 * set through the use of prefixes. That is, while 0xf0 0x58 may be 683 * addps, 0xf3 0xf0 0x58 (literally, repz addps) is a completely different 684 * instruction - addss. At present, three prefixes have been coopted in 685 * this manner - address size (0x66), repnz (0xf2) and repz (0xf3). The 686 * following tables are used to provide the prefixed instruction names. 687 * The arrays are sparse, but they're fast. 688 */ 689 690 /* 691 * Decode table for SIMD instructions with the address size (0x66) prefix. 692 */ 693 const instable_t dis_opSIMDdata16[256] = { 694 /* [00] */ INVALID, INVALID, INVALID, INVALID, 695 /* [04] */ INVALID, INVALID, INVALID, INVALID, 696 /* [08] */ INVALID, INVALID, INVALID, INVALID, 697 /* [0C] */ INVALID, INVALID, INVALID, INVALID, 698 699 /* [10] */ TNSZ("movupd",XMM,16), TNSZ("movupd",XMMS,16), TNSZ("movlpd",XMMM,8), TNSZ("movlpd",XMMMS,8), 700 /* [14] */ TNSZ("unpcklpd",XMM,16),TNSZ("unpckhpd",XMM,16),TNSZ("movhpd",XMMM,8), TNSZ("movhpd",XMMMS,8), 701 /* [18] */ INVALID, INVALID, INVALID, INVALID, 702 /* [1C] */ INVALID, INVALID, INVALID, INVALID, 703 704 /* [20] */ INVALID, INVALID, INVALID, INVALID, 705 /* [24] */ INVALID, INVALID, INVALID, INVALID, 706 /* [28] */ TNSZ("movapd",XMM,16), TNSZ("movapd",XMMS,16), TNSZ("cvtpi2pd",XMMOMX,8),TNSZ("movntpd",XMMOMS,16), 707 /* [2C] */ TNSZ("cvttpd2pi",XMMXMM,16),TNSZ("cvtpd2pi",XMMXMM,16),TNSZ("ucomisd",XMM,8),TNSZ("comisd",XMM,8), 708 709 /* [30] */ INVALID, INVALID, INVALID, INVALID, 710 /* [34] */ INVALID, INVALID, INVALID, INVALID, 711 /* [38] */ INVALID, INVALID, INVALID, INVALID, 712 /* [3C] */ INVALID, INVALID, INVALID, INVALID, 713 714 /* [40] */ INVALID, INVALID, INVALID, INVALID, 715 /* [44] */ INVALID, INVALID, INVALID, INVALID, 716 /* [48] */ INVALID, INVALID, INVALID, INVALID, 717 /* [4C] */ INVALID, INVALID, INVALID, INVALID, 718 719 /* [50] */ TNS("movmskpd",XMMOX3), TNSZ("sqrtpd",XMM,16), INVALID, INVALID, 720 /* [54] */ TNSZ("andpd",XMM,16), TNSZ("andnpd",XMM,16), TNSZ("orpd",XMM,16), TNSZ("xorpd",XMM,16), 721 /* [58] */ TNSZ("addpd",XMM,16), TNSZ("mulpd",XMM,16), TNSZ("cvtpd2ps",XMM,16),TNSZ("cvtps2dq",XMM,16), 722 /* [5C] */ TNSZ("subpd",XMM,16), TNSZ("minpd",XMM,16), TNSZ("divpd",XMM,16), TNSZ("maxpd",XMM,16), 723 724 /* [60] */ TNSZ("punpcklbw",XMM,16),TNSZ("punpcklwd",XMM,16),TNSZ("punpckldq",XMM,16),TNSZ("packsswb",XMM,16), 725 /* [64] */ TNSZ("pcmpgtb",XMM,16), TNSZ("pcmpgtw",XMM,16), TNSZ("pcmpgtd",XMM,16), TNSZ("packuswb",XMM,16), 726 /* [68] */ TNSZ("punpckhbw",XMM,16),TNSZ("punpckhwd",XMM,16),TNSZ("punpckhdq",XMM,16),TNSZ("packssdw",XMM,16), 727 /* [6C] */ TNSZ("punpcklqdq",XMM,16),TNSZ("punpckhqdq",XMM,16),TNSZ("movd",XMM3MX,4),TNSZ("movdqa",XMM,16), 728 729 /* [70] */ TNSZ("pshufd",XMMP,16), INVALID, INVALID, INVALID, 730 /* [74] */ TNSZ("pcmpeqb",XMM,16), TNSZ("pcmpeqw",XMM,16), TNSZ("pcmpeqd",XMM,16), INVALID, 731 /* [78] */ TNSZ("extrq",XMM2I,16), TNSZ("extrq",XMM,16), INVALID, INVALID, 732 /* [7C] */ TNSZ("haddpd",XMM,16), TNSZ("hsubpd",XMM,16), TNSZ("movd",XMM3MXS,4), TNSZ("movdqa",XMMS,16), 733 734 /* [80] */ INVALID, INVALID, INVALID, INVALID, 735 /* [84] */ INVALID, INVALID, INVALID, INVALID, 736 /* [88] */ INVALID, INVALID, INVALID, INVALID, 737 /* [8C] */ INVALID, INVALID, INVALID, INVALID, 738 739 /* [90] */ INVALID, INVALID, INVALID, INVALID, 740 /* [94] */ INVALID, INVALID, INVALID, INVALID, 741 /* [98] */ INVALID, INVALID, INVALID, INVALID, 742 /* [9C] */ INVALID, INVALID, INVALID, INVALID, 743 744 /* [A0] */ INVALID, INVALID, INVALID, INVALID, 745 /* [A4] */ INVALID, INVALID, INVALID, INVALID, 746 /* [A8] */ INVALID, INVALID, INVALID, INVALID, 747 /* [AC] */ INVALID, INVALID, INVALID, INVALID, 748 749 /* [B0] */ INVALID, INVALID, INVALID, INVALID, 750 /* [B4] */ INVALID, INVALID, INVALID, INVALID, 751 /* [B8] */ INVALID, INVALID, INVALID, INVALID, 752 /* [BC] */ INVALID, INVALID, INVALID, INVALID, 753 754 /* [C0] */ INVALID, INVALID, TNSZ("cmppd",XMMP,16), INVALID, 755 /* [C4] */ TNSZ("pinsrw",XMMPRM,2),TNS("pextrw",XMM3P), TNSZ("shufpd",XMMP,16), INVALID, 756 /* [C8] */ INVALID, INVALID, INVALID, INVALID, 757 /* [CC] */ INVALID, INVALID, INVALID, INVALID, 758 759 /* [D0] */ TNSZ("addsubpd",XMM,16),TNSZ("psrlw",XMM,16), TNSZ("psrld",XMM,16), TNSZ("psrlq",XMM,16), 760 /* [D4] */ TNSZ("paddq",XMM,16), TNSZ("pmullw",XMM,16), TNSZ("movq",XMMS,8), TNS("pmovmskb",XMMX3), 761 /* [D8] */ TNSZ("psubusb",XMM,16), TNSZ("psubusw",XMM,16), TNSZ("pminub",XMM,16), TNSZ("pand",XMM,16), 762 /* [DC] */ TNSZ("paddusb",XMM,16), TNSZ("paddusw",XMM,16), TNSZ("pmaxub",XMM,16), TNSZ("pandn",XMM,16), 763 764 /* [E0] */ TNSZ("pavgb",XMM,16), TNSZ("psraw",XMM,16), TNSZ("psrad",XMM,16), TNSZ("pavgw",XMM,16), 765 /* [E4] */ TNSZ("pmulhuw",XMM,16), TNSZ("pmulhw",XMM,16), TNSZ("cvttpd2dq",XMM,16),TNSZ("movntdq",XMMS,16), 766 /* [E8] */ TNSZ("psubsb",XMM,16), TNSZ("psubsw",XMM,16), TNSZ("pminsw",XMM,16), TNSZ("por",XMM,16), 767 /* [EC] */ TNSZ("paddsb",XMM,16), TNSZ("paddsw",XMM,16), TNSZ("pmaxsw",XMM,16), TNSZ("pxor",XMM,16), 768 769 /* [F0] */ INVALID, TNSZ("psllw",XMM,16), TNSZ("pslld",XMM,16), TNSZ("psllq",XMM,16), 770 /* [F4] */ TNSZ("pmuludq",XMM,16), TNSZ("pmaddwd",XMM,16), TNSZ("psadbw",XMM,16), TNSZ("maskmovdqu", XMMXIMPL,16), 771 /* [F8] */ TNSZ("psubb",XMM,16), TNSZ("psubw",XMM,16), TNSZ("psubd",XMM,16), TNSZ("psubq",XMM,16), 772 /* [FC] */ TNSZ("paddb",XMM,16), TNSZ("paddw",XMM,16), TNSZ("paddd",XMM,16), INVALID, 773 }; 774 775 const instable_t dis_opAVX660F[256] = { 776 /* [00] */ INVALID, INVALID, INVALID, INVALID, 777 /* [04] */ INVALID, INVALID, INVALID, INVALID, 778 /* [08] */ INVALID, INVALID, INVALID, INVALID, 779 /* [0C] */ INVALID, INVALID, INVALID, INVALID, 780 781 /* [10] */ TNSZ("vmovupd",VEX_MX,16), TNSZ("vmovupd",VEX_RX,16), TNSZ("vmovlpd",VEX_RMrX,8), TNSZ("vmovlpd",VEX_RM,8), 782 /* [14] */ TNSZ("vunpcklpd",VEX_RMrX,16),TNSZ("vunpckhpd",VEX_RMrX,16),TNSZ("vmovhpd",VEX_RMrX,8), TNSZ("vmovhpd",VEX_RM,8), 783 /* [18] */ INVALID, INVALID, INVALID, INVALID, 784 /* [1C] */ INVALID, INVALID, INVALID, INVALID, 785 786 /* [20] */ INVALID, INVALID, INVALID, INVALID, 787 /* [24] */ INVALID, INVALID, INVALID, INVALID, 788 /* [28] */ TNSZ("vmovapd",VEX_MX,16), TNSZ("vmovapd",VEX_RX,16), INVALID, TNSZ("vmovntpd",VEX_RM,16), 789 /* [2C] */ INVALID, INVALID, TNSZ("vucomisd",VEX_MX,8),TNSZ("vcomisd",VEX_MX,8), 790 791 /* [30] */ INVALID, INVALID, INVALID, INVALID, 792 /* [34] */ INVALID, INVALID, INVALID, INVALID, 793 /* [38] */ INVALID, INVALID, INVALID, INVALID, 794 /* [3C] */ INVALID, INVALID, INVALID, INVALID, 795 796 /* [40] */ INVALID, TSvo("kand",VEX_RMX), TSvo("kandn",VEX_RMX), INVALID, 797 /* [44] */ TSvo("knot",VEX_MX), TSvo("kor",VEX_RMX), TSvo("kxnor",VEX_RMX), TSvo("kxor",VEX_RMX), 798 /* [48] */ INVALID, INVALID, TSvo("kadd",VEX_RMX), TSvo("kunpck",VEX_RMX), 799 /* [4C] */ INVALID, INVALID, INVALID, INVALID, 800 801 /* [50] */ TNS("vmovmskpd",VEX_MR), TNSZ("vsqrtpd",VEX_MX,16), INVALID, INVALID, 802 /* [54] */ TNSZ("vandpd",VEX_RMrX,16), TNSZ("vandnpd",VEX_RMrX,16), TNSZ("vorpd",VEX_RMrX,16), TNSZ("vxorpd",VEX_RMrX,16), 803 /* [58] */ TNSZ("vaddpd",VEX_RMrX,16), TNSZ("vmulpd",VEX_RMrX,16), TNSZ("vcvtpd2ps",VEX_MX,16),TNSZ("vcvtps2dq",VEX_MX,16), 804 /* [5C] */ TNSZ("vsubpd",VEX_RMrX,16), TNSZ("vminpd",VEX_RMrX,16), TNSZ("vdivpd",VEX_RMrX,16), TNSZ("vmaxpd",VEX_RMrX,16), 805 806 /* [60] */ TNSZ("vpunpcklbw",VEX_RMrX,16),TNSZ("vpunpcklwd",VEX_RMrX,16),TNSZ("vpunpckldq",VEX_RMrX,16),TNSZ("vpacksswb",VEX_RMrX,16), 807 /* [64] */ TNSZ("vpcmpgtb",VEX_RMrX,16), TNSZ("vpcmpgtw",VEX_RMrX,16), TNSZ("vpcmpgtd",VEX_RMrX,16), TNSZ("vpackuswb",VEX_RMrX,16), 808 /* [68] */ TNSZ("vpunpckhbw",VEX_RMrX,16),TNSZ("vpunpckhwd",VEX_RMrX,16),TNSZ("vpunpckhdq",VEX_RMrX,16),TNSZ("vpackssdw",VEX_RMrX,16), 809 /* [6C] */ TNSZ("vpunpcklqdq",VEX_RMrX,16),TNSZ("vpunpckhqdq",VEX_RMrX,16),TNSZ("vmovd",VEX_MX,4),TNSZ("vmovdqa",VEX_MX,16), 810 811 /* [70] */ TNSZ("vpshufd",VEX_MXI,16), TNSZ("vgrp71",VEX_XXI,16), TNSZ("vgrp72",VEX_XXI,16), TNSZ("vgrp73",VEX_XXI,16), 812 /* [74] */ TNSZ("vpcmpeqb",VEX_RMrX,16), TNSZ("vpcmpeqw",VEX_RMrX,16), TNSZ("vpcmpeqd",VEX_RMrX,16), INVALID, 813 /* [78] */ INVALID, INVALID, INVALID, INVALID, 814 /* [7C] */ TNSZ("vhaddpd",VEX_RMrX,16), TNSZ("vhsubpd",VEX_RMrX,16), TNSZ("vmovd",VEX_RR,4), TNSZ("vmovdqa",VEX_RX,16), 815 816 /* [80] */ INVALID, INVALID, INVALID, INVALID, 817 /* [84] */ INVALID, INVALID, INVALID, INVALID, 818 /* [88] */ INVALID, INVALID, INVALID, INVALID, 819 /* [8C] */ INVALID, INVALID, INVALID, INVALID, 820 821 /* [90] */ TSvo("kmov",VEX_KRM), TSvo("kmov",VEX_KMR), TSvo("kmov",VEX_KRR), TSvo("kmov",VEX_MR), 822 /* [94] */ INVALID, INVALID, INVALID, INVALID, 823 /* [98] */ TSvo("kortest",VEX_MX), TSvo("ktest",VEX_MX), INVALID, INVALID, 824 /* [9C] */ INVALID, INVALID, INVALID, INVALID, 825 826 /* [A0] */ INVALID, INVALID, INVALID, INVALID, 827 /* [A4] */ INVALID, INVALID, INVALID, INVALID, 828 /* [A8] */ INVALID, INVALID, INVALID, INVALID, 829 /* [AC] */ INVALID, INVALID, INVALID, INVALID, 830 831 /* [B0] */ INVALID, INVALID, INVALID, INVALID, 832 /* [B4] */ INVALID, INVALID, INVALID, INVALID, 833 /* [B8] */ INVALID, INVALID, INVALID, INVALID, 834 /* [BC] */ INVALID, INVALID, INVALID, INVALID, 835 836 /* [C0] */ INVALID, INVALID, TNSZ("vcmppd",VEX_RMRX,16), INVALID, 837 /* [C4] */ TNSZ("vpinsrw",VEX_RMRX,2),TNS("vpextrw",VEX_MR), TNSZ("vshufpd",VEX_RMRX,16), INVALID, 838 /* [C8] */ INVALID, INVALID, INVALID, INVALID, 839 /* [CC] */ INVALID, INVALID, INVALID, INVALID, 840 841 /* [D0] */ TNSZ("vaddsubpd",VEX_RMrX,16),TNSZ("vpsrlw",VEX_RMrX,16), TNSZ("vpsrld",VEX_RMrX,16), TNSZ("vpsrlq",VEX_RMrX,16), 842 /* [D4] */ TNSZ("vpaddq",VEX_RMrX,16), TNSZ("vpmullw",VEX_RMrX,16), TNSZ("vmovq",VEX_RX,8), TNS("vpmovmskb",VEX_MR), 843 /* [D8] */ TNSZ("vpsubusb",VEX_RMrX,16), TNSZ("vpsubusw",VEX_RMrX,16), TNSZ("vpminub",VEX_RMrX,16), TNSZ("vpand",VEX_RMrX,16), 844 /* [DC] */ TNSZ("vpaddusb",VEX_RMrX,16), TNSZ("vpaddusw",VEX_RMrX,16), TNSZ("vpmaxub",VEX_RMrX,16), TNSZ("vpandn",VEX_RMrX,16), 845 846 /* [E0] */ TNSZ("vpavgb",VEX_RMrX,16), TNSZ("vpsraw",VEX_RMrX,16), TNSZ("vpsrad",VEX_RMrX,16), TNSZ("vpavgw",VEX_RMrX,16), 847 /* [E4] */ TNSZ("vpmulhuw",VEX_RMrX,16), TNSZ("vpmulhw",VEX_RMrX,16), TNSZ("vcvttpd2dq",VEX_MX,16),TNSZ("vmovntdq",VEX_RM,16), 848 /* [E8] */ TNSZ("vpsubsb",VEX_RMrX,16), TNSZ("vpsubsw",VEX_RMrX,16), TNSZ("vpminsw",VEX_RMrX,16), TNSZ("vpor",VEX_RMrX,16), 849 /* [EC] */ TNSZ("vpaddsb",VEX_RMrX,16), TNSZ("vpaddsw",VEX_RMrX,16), TNSZ("vpmaxsw",VEX_RMrX,16), TNSZ("vpxor",VEX_RMrX,16), 850 851 /* [F0] */ INVALID, TNSZ("vpsllw",VEX_RMrX,16), TNSZ("vpslld",VEX_RMrX,16), TNSZ("vpsllq",VEX_RMrX,16), 852 /* [F4] */ TNSZ("vpmuludq",VEX_RMrX,16), TNSZ("vpmaddwd",VEX_RMrX,16), TNSZ("vpsadbw",VEX_RMrX,16), TNS("vmaskmovdqu",VEX_MX), 853 /* [F8] */ TNSZ("vpsubb",VEX_RMrX,16), TNSZ("vpsubw",VEX_RMrX,16), TNSZ("vpsubd",VEX_RMrX,16), TNSZ("vpsubq",VEX_RMrX,16), 854 /* [FC] */ TNSZ("vpaddb",VEX_RMrX,16), TNSZ("vpaddw",VEX_RMrX,16), TNSZ("vpaddd",VEX_RMrX,16), INVALID, 855 }; 856 857 /* 858 * Decode table for SIMD instructions with the repnz (0xf2) prefix. 859 */ 860 const instable_t dis_opSIMDrepnz[256] = { 861 /* [00] */ INVALID, INVALID, INVALID, INVALID, 862 /* [04] */ INVALID, INVALID, INVALID, INVALID, 863 /* [08] */ INVALID, INVALID, INVALID, INVALID, 864 /* [0C] */ INVALID, INVALID, INVALID, INVALID, 865 866 /* [10] */ TNSZ("movsd",XMM,8), TNSZ("movsd",XMMS,8), TNSZ("movddup",XMM,8), INVALID, 867 /* [14] */ INVALID, INVALID, INVALID, INVALID, 868 /* [18] */ INVALID, INVALID, INVALID, INVALID, 869 /* [1C] */ INVALID, INVALID, INVALID, INVALID, 870 871 /* [20] */ INVALID, INVALID, INVALID, INVALID, 872 /* [24] */ INVALID, INVALID, INVALID, INVALID, 873 /* [28] */ INVALID, INVALID, TNSZ("cvtsi2sd",XMM3MX,4),TNSZ("movntsd",XMMMS,8), 874 /* [2C] */ TNSZ("cvttsd2si",XMMXM3,8),TNSZ("cvtsd2si",XMMXM3,8),INVALID, INVALID, 875 876 /* [30] */ INVALID, INVALID, INVALID, INVALID, 877 /* [34] */ INVALID, INVALID, INVALID, INVALID, 878 /* [38] */ INVALID, INVALID, INVALID, INVALID, 879 /* [3C] */ INVALID, INVALID, INVALID, INVALID, 880 881 /* [40] */ INVALID, INVALID, INVALID, INVALID, 882 /* [44] */ INVALID, INVALID, INVALID, INVALID, 883 /* [48] */ INVALID, INVALID, INVALID, INVALID, 884 /* [4C] */ INVALID, INVALID, INVALID, INVALID, 885 886 /* [50] */ INVALID, TNSZ("sqrtsd",XMM,8), INVALID, INVALID, 887 /* [54] */ INVALID, INVALID, INVALID, INVALID, 888 /* [58] */ TNSZ("addsd",XMM,8), TNSZ("mulsd",XMM,8), TNSZ("cvtsd2ss",XMM,8), INVALID, 889 /* [5C] */ TNSZ("subsd",XMM,8), TNSZ("minsd",XMM,8), TNSZ("divsd",XMM,8), TNSZ("maxsd",XMM,8), 890 891 /* [60] */ INVALID, INVALID, INVALID, INVALID, 892 /* [64] */ INVALID, INVALID, INVALID, INVALID, 893 /* [68] */ INVALID, INVALID, INVALID, INVALID, 894 /* [6C] */ INVALID, INVALID, INVALID, INVALID, 895 896 /* [70] */ TNSZ("pshuflw",XMMP,16),INVALID, INVALID, INVALID, 897 /* [74] */ INVALID, INVALID, INVALID, INVALID, 898 /* [78] */ TNSZ("insertq",XMMX2I,16),TNSZ("insertq",XMM,8),INVALID, INVALID, 899 /* [7C] */ TNSZ("haddps",XMM,16), TNSZ("hsubps",XMM,16), INVALID, INVALID, 900 901 /* [80] */ INVALID, INVALID, INVALID, INVALID, 902 /* [84] */ INVALID, INVALID, INVALID, INVALID, 903 /* [88] */ INVALID, INVALID, INVALID, INVALID, 904 /* [0C] */ INVALID, INVALID, INVALID, INVALID, 905 906 /* [90] */ INVALID, INVALID, INVALID, INVALID, 907 /* [94] */ INVALID, INVALID, INVALID, INVALID, 908 /* [98] */ INVALID, INVALID, INVALID, INVALID, 909 /* [9C] */ INVALID, INVALID, INVALID, INVALID, 910 911 /* [A0] */ INVALID, INVALID, INVALID, INVALID, 912 /* [A4] */ INVALID, INVALID, INVALID, INVALID, 913 /* [A8] */ INVALID, INVALID, INVALID, INVALID, 914 /* [AC] */ INVALID, INVALID, INVALID, INVALID, 915 916 /* [B0] */ INVALID, INVALID, INVALID, INVALID, 917 /* [B4] */ INVALID, INVALID, INVALID, INVALID, 918 /* [B8] */ INVALID, INVALID, INVALID, INVALID, 919 /* [BC] */ INVALID, INVALID, INVALID, INVALID, 920 921 /* [C0] */ INVALID, INVALID, TNSZ("cmpsd",XMMP,8), INVALID, 922 /* [C4] */ INVALID, INVALID, INVALID, INVALID, 923 /* [C8] */ INVALID, INVALID, INVALID, INVALID, 924 /* [CC] */ INVALID, INVALID, INVALID, INVALID, 925 926 /* [D0] */ TNSZ("addsubps",XMM,16),INVALID, INVALID, INVALID, 927 /* [D4] */ INVALID, INVALID, TNS("movdq2q",XMMXM), INVALID, 928 /* [D8] */ INVALID, INVALID, INVALID, INVALID, 929 /* [DC] */ INVALID, INVALID, INVALID, INVALID, 930 931 /* [E0] */ INVALID, INVALID, INVALID, INVALID, 932 /* [E4] */ INVALID, INVALID, TNSZ("cvtpd2dq",XMM,16),INVALID, 933 /* [E8] */ INVALID, INVALID, INVALID, INVALID, 934 /* [EC] */ INVALID, INVALID, INVALID, INVALID, 935 936 /* [F0] */ TNS("lddqu",XMMM), INVALID, INVALID, INVALID, 937 /* [F4] */ INVALID, INVALID, INVALID, INVALID, 938 /* [F8] */ INVALID, INVALID, INVALID, INVALID, 939 /* [FC] */ INVALID, INVALID, INVALID, INVALID, 940 }; 941 942 const instable_t dis_opAVXF20F[256] = { 943 /* [00] */ INVALID, INVALID, INVALID, INVALID, 944 /* [04] */ INVALID, INVALID, INVALID, INVALID, 945 /* [08] */ INVALID, INVALID, INVALID, INVALID, 946 /* [0C] */ INVALID, INVALID, INVALID, INVALID, 947 948 /* [10] */ TNSZ("vmovsd",VEX_RMrX,8), TNSZ("vmovsd",VEX_RRX,8), TNSZ("vmovddup",VEX_MX,8), INVALID, 949 /* [14] */ INVALID, INVALID, INVALID, INVALID, 950 /* [18] */ INVALID, INVALID, INVALID, INVALID, 951 /* [1C] */ INVALID, INVALID, INVALID, INVALID, 952 953 /* [20] */ INVALID, INVALID, INVALID, INVALID, 954 /* [24] */ INVALID, INVALID, INVALID, INVALID, 955 /* [28] */ INVALID, INVALID, TNSZ("vcvtsi2sd",VEX_RMrX,4),INVALID, 956 /* [2C] */ TNSZ("vcvttsd2si",VEX_MR,8),TNSZ("vcvtsd2si",VEX_MR,8),INVALID, INVALID, 957 958 /* [30] */ INVALID, INVALID, INVALID, INVALID, 959 /* [34] */ INVALID, INVALID, INVALID, INVALID, 960 /* [38] */ INVALID, INVALID, INVALID, INVALID, 961 /* [3C] */ INVALID, INVALID, INVALID, INVALID, 962 963 /* [40] */ INVALID, INVALID, INVALID, INVALID, 964 /* [44] */ INVALID, INVALID, INVALID, INVALID, 965 /* [48] */ INVALID, INVALID, INVALID, INVALID, 966 /* [4C] */ INVALID, INVALID, INVALID, INVALID, 967 968 /* [50] */ INVALID, TNSZ("vsqrtsd",VEX_RMrX,8), INVALID, INVALID, 969 /* [54] */ INVALID, INVALID, INVALID, INVALID, 970 /* [58] */ TNSZ("vaddsd",VEX_RMrX,8), TNSZ("vmulsd",VEX_RMrX,8), TNSZ("vcvtsd2ss",VEX_RMrX,8), INVALID, 971 /* [5C] */ TNSZ("vsubsd",VEX_RMrX,8), TNSZ("vminsd",VEX_RMrX,8), TNSZ("vdivsd",VEX_RMrX,8), TNSZ("vmaxsd",VEX_RMrX,8), 972 973 /* [60] */ INVALID, INVALID, INVALID, INVALID, 974 /* [64] */ INVALID, INVALID, INVALID, INVALID, 975 /* [68] */ INVALID, INVALID, INVALID, INVALID, 976 /* [6C] */ INVALID, INVALID, INVALID, INVALID, 977 978 /* [70] */ TNSZ("vpshuflw",VEX_MXI,16),INVALID, INVALID, INVALID, 979 /* [74] */ INVALID, INVALID, INVALID, INVALID, 980 /* [78] */ INVALID, INVALID, INVALID, INVALID, 981 /* [7C] */ TNSZ("vhaddps",VEX_RMrX,8), TNSZ("vhsubps",VEX_RMrX,8), INVALID, INVALID, 982 983 /* [80] */ INVALID, INVALID, INVALID, INVALID, 984 /* [84] */ INVALID, INVALID, INVALID, INVALID, 985 /* [88] */ INVALID, INVALID, INVALID, INVALID, 986 /* [0C] */ INVALID, INVALID, INVALID, INVALID, 987 988 /* [90] */ INVALID, INVALID, TSvo("kmov",VEX_KRR), TSvo("kmov",VEX_MR), 989 /* [94] */ INVALID, INVALID, INVALID, INVALID, 990 /* [98] */ INVALID, INVALID, INVALID, INVALID, 991 /* [9C] */ INVALID, INVALID, INVALID, INVALID, 992 993 /* [A0] */ INVALID, INVALID, INVALID, INVALID, 994 /* [A4] */ INVALID, INVALID, INVALID, INVALID, 995 /* [A8] */ INVALID, INVALID, INVALID, INVALID, 996 /* [AC] */ INVALID, INVALID, INVALID, INVALID, 997 998 /* [B0] */ INVALID, INVALID, INVALID, INVALID, 999 /* [B4] */ INVALID, INVALID, INVALID, INVALID, 1000 /* [B8] */ INVALID, INVALID, INVALID, INVALID, 1001 /* [BC] */ INVALID, INVALID, INVALID, INVALID, 1002 1003 /* [C0] */ INVALID, INVALID, TNSZ("vcmpsd",VEX_RMRX,8), INVALID, 1004 /* [C4] */ INVALID, INVALID, INVALID, INVALID, 1005 /* [C8] */ INVALID, INVALID, INVALID, INVALID, 1006 /* [CC] */ INVALID, INVALID, INVALID, INVALID, 1007 1008 /* [D0] */ TNSZ("vaddsubps",VEX_RMrX,8), INVALID, INVALID, INVALID, 1009 /* [D4] */ INVALID, INVALID, INVALID, INVALID, 1010 /* [D8] */ INVALID, INVALID, INVALID, INVALID, 1011 /* [DC] */ INVALID, INVALID, INVALID, INVALID, 1012 1013 /* [E0] */ INVALID, INVALID, INVALID, INVALID, 1014 /* [E4] */ INVALID, INVALID, TNSZ("vcvtpd2dq",VEX_MX,16),INVALID, 1015 /* [E8] */ INVALID, INVALID, INVALID, INVALID, 1016 /* [EC] */ INVALID, INVALID, INVALID, INVALID, 1017 1018 /* [F0] */ TNSZ("vlddqu",VEX_MX,16), INVALID, INVALID, INVALID, 1019 /* [F4] */ INVALID, INVALID, INVALID, INVALID, 1020 /* [F8] */ INVALID, INVALID, INVALID, INVALID, 1021 /* [FC] */ INVALID, INVALID, INVALID, INVALID, 1022 }; 1023 1024 const instable_t dis_opAVXF20F3A[256] = { 1025 /* [00] */ INVALID, INVALID, INVALID, INVALID, 1026 /* [04] */ INVALID, INVALID, INVALID, INVALID, 1027 /* [08] */ INVALID, INVALID, INVALID, INVALID, 1028 /* [0C] */ INVALID, INVALID, INVALID, INVALID, 1029 1030 /* [10] */ INVALID, INVALID, INVALID, INVALID, 1031 /* [14] */ INVALID, INVALID, INVALID, INVALID, 1032 /* [18] */ INVALID, INVALID, INVALID, INVALID, 1033 /* [1C] */ INVALID, INVALID, INVALID, INVALID, 1034 1035 /* [20] */ INVALID, INVALID, INVALID, INVALID, 1036 /* [24] */ INVALID, INVALID, INVALID, INVALID, 1037 /* [28] */ INVALID, INVALID, INVALID, INVALID, 1038 /* [2C] */ INVALID, INVALID, INVALID, INVALID, 1039 1040 /* [30] */ INVALID, INVALID, INVALID, INVALID, 1041 /* [34] */ INVALID, INVALID, INVALID, INVALID, 1042 /* [38] */ INVALID, INVALID, INVALID, INVALID, 1043 /* [3C] */ INVALID, INVALID, INVALID, INVALID, 1044 1045 /* [40] */ INVALID, INVALID, INVALID, INVALID, 1046 /* [44] */ INVALID, INVALID, INVALID, INVALID, 1047 /* [48] */ INVALID, INVALID, INVALID, INVALID, 1048 /* [4C] */ INVALID, INVALID, INVALID, INVALID, 1049 1050 /* [50] */ INVALID, INVALID, INVALID, INVALID, 1051 /* [54] */ INVALID, INVALID, INVALID, INVALID, 1052 /* [58] */ INVALID, INVALID, INVALID, INVALID, 1053 /* [5C] */ INVALID, INVALID, INVALID, INVALID, 1054 1055 /* [60] */ INVALID, INVALID, INVALID, INVALID, 1056 /* [64] */ INVALID, INVALID, INVALID, INVALID, 1057 /* [68] */ INVALID, INVALID, INVALID, INVALID, 1058 /* [6C] */ INVALID, INVALID, INVALID, INVALID, 1059 1060 /* [70] */ INVALID, INVALID, INVALID, INVALID, 1061 /* [74] */ INVALID, INVALID, INVALID, INVALID, 1062 /* [78] */ INVALID, INVALID, INVALID, INVALID, 1063 /* [7C] */ INVALID, INVALID, INVALID, INVALID, 1064 1065 /* [80] */ INVALID, INVALID, INVALID, INVALID, 1066 /* [84] */ INVALID, INVALID, INVALID, INVALID, 1067 /* [88] */ INVALID, INVALID, INVALID, INVALID, 1068 /* [0C] */ INVALID, INVALID, INVALID, INVALID, 1069 1070 /* [90] */ INVALID, INVALID, INVALID, INVALID, 1071 /* [94] */ INVALID, INVALID, INVALID, INVALID, 1072 /* [98] */ INVALID, INVALID, INVALID, INVALID, 1073 /* [9C] */ INVALID, INVALID, INVALID, INVALID, 1074 1075 /* [A0] */ INVALID, INVALID, INVALID, INVALID, 1076 /* [A4] */ INVALID, INVALID, INVALID, INVALID, 1077 /* [A8] */ INVALID, INVALID, INVALID, INVALID, 1078 /* [AC] */ INVALID, INVALID, INVALID, INVALID, 1079 1080 /* [B0] */ INVALID, INVALID, INVALID, INVALID, 1081 /* [B4] */ INVALID, INVALID, INVALID, INVALID, 1082 /* [B8] */ INVALID, INVALID, INVALID, INVALID, 1083 /* [BC] */ INVALID, INVALID, INVALID, INVALID, 1084 1085 /* [C0] */ INVALID, INVALID, INVALID, INVALID, 1086 /* [C4] */ INVALID, INVALID, INVALID, INVALID, 1087 /* [C8] */ INVALID, INVALID, INVALID, INVALID, 1088 /* [CC] */ INVALID, INVALID, INVALID, INVALID, 1089 1090 /* [D0] */ INVALID, INVALID, INVALID, INVALID, 1091 /* [D4] */ INVALID, INVALID, INVALID, INVALID, 1092 /* [D8] */ INVALID, INVALID, INVALID, INVALID, 1093 /* [DC] */ INVALID, INVALID, INVALID, INVALID, 1094 1095 /* [E0] */ INVALID, INVALID, INVALID, INVALID, 1096 /* [E4] */ INVALID, INVALID, INVALID, INVALID, 1097 /* [E8] */ INVALID, INVALID, INVALID, INVALID, 1098 /* [EC] */ INVALID, INVALID, INVALID, INVALID, 1099 1100 /* [F0] */ TNSZvr("rorx",VEX_MXI,6),INVALID, INVALID, INVALID, 1101 /* [F4] */ INVALID, INVALID, INVALID, INVALID, 1102 /* [F8] */ INVALID, INVALID, INVALID, INVALID, 1103 /* [FC] */ INVALID, INVALID, INVALID, INVALID, 1104 }; 1105 1106 const instable_t dis_opAVXF20F38[256] = { 1107 /* [00] */ INVALID, INVALID, INVALID, INVALID, 1108 /* [04] */ INVALID, INVALID, INVALID, INVALID, 1109 /* [08] */ INVALID, INVALID, INVALID, INVALID, 1110 /* [0C] */ INVALID, INVALID, INVALID, INVALID, 1111 1112 /* [10] */ INVALID, INVALID, INVALID, INVALID, 1113 /* [14] */ INVALID, INVALID, INVALID, INVALID, 1114 /* [18] */ INVALID, INVALID, INVALID, INVALID, 1115 /* [1C] */ INVALID, INVALID, INVALID, INVALID, 1116 1117 /* [20] */ INVALID, INVALID, INVALID, INVALID, 1118 /* [24] */ INVALID, INVALID, INVALID, INVALID, 1119 /* [28] */ INVALID, INVALID, INVALID, INVALID, 1120 /* [2C] */ INVALID, INVALID, INVALID, INVALID, 1121 1122 /* [30] */ INVALID, INVALID, INVALID, INVALID, 1123 /* [34] */ INVALID, INVALID, INVALID, INVALID, 1124 /* [38] */ INVALID, INVALID, INVALID, INVALID, 1125 /* [3C] */ INVALID, INVALID, INVALID, INVALID, 1126 1127 /* [40] */ INVALID, INVALID, INVALID, INVALID, 1128 /* [44] */ INVALID, INVALID, INVALID, INVALID, 1129 /* [48] */ INVALID, INVALID, INVALID, INVALID, 1130 /* [4C] */ INVALID, INVALID, INVALID, INVALID, 1131 1132 /* [50] */ INVALID, INVALID, INVALID, INVALID, 1133 /* [54] */ INVALID, INVALID, INVALID, INVALID, 1134 /* [58] */ INVALID, INVALID, INVALID, INVALID, 1135 /* [5C] */ INVALID, INVALID, INVALID, INVALID, 1136 1137 /* [60] */ INVALID, INVALID, INVALID, INVALID, 1138 /* [64] */ INVALID, INVALID, INVALID, INVALID, 1139 /* [68] */ INVALID, INVALID, INVALID, INVALID, 1140 /* [6C] */ INVALID, INVALID, INVALID, INVALID, 1141 1142 /* [70] */ INVALID, INVALID, INVALID, INVALID, 1143 /* [74] */ INVALID, INVALID, INVALID, INVALID, 1144 /* [78] */ INVALID, INVALID, INVALID, INVALID, 1145 /* [7C] */ INVALID, INVALID, INVALID, INVALID, 1146 1147 /* [80] */ INVALID, INVALID, INVALID, INVALID, 1148 /* [84] */ INVALID, INVALID, INVALID, INVALID, 1149 /* [88] */ INVALID, INVALID, INVALID, INVALID, 1150 /* [0C] */ INVALID, INVALID, INVALID, INVALID, 1151 1152 /* [90] */ INVALID, INVALID, INVALID, INVALID, 1153 /* [94] */ INVALID, INVALID, INVALID, INVALID, 1154 /* [98] */ INVALID, INVALID, INVALID, INVALID, 1155 /* [9C] */ INVALID, INVALID, INVALID, INVALID, 1156 1157 /* [A0] */ INVALID, INVALID, INVALID, INVALID, 1158 /* [A4] */ INVALID, INVALID, INVALID, INVALID, 1159 /* [A8] */ INVALID, INVALID, INVALID, INVALID, 1160 /* [AC] */ INVALID, INVALID, INVALID, INVALID, 1161 1162 /* [B0] */ INVALID, INVALID, INVALID, INVALID, 1163 /* [B4] */ INVALID, INVALID, INVALID, INVALID, 1164 /* [B8] */ INVALID, INVALID, INVALID, INVALID, 1165 /* [BC] */ INVALID, INVALID, INVALID, INVALID, 1166 1167 /* [C0] */ INVALID, INVALID, INVALID, INVALID, 1168 /* [C4] */ INVALID, INVALID, INVALID, INVALID, 1169 /* [C8] */ INVALID, INVALID, INVALID, INVALID, 1170 /* [CC] */ INVALID, INVALID, INVALID, INVALID, 1171 1172 /* [D0] */ INVALID, INVALID, INVALID, INVALID, 1173 /* [D4] */ INVALID, INVALID, INVALID, INVALID, 1174 /* [D8] */ INVALID, INVALID, INVALID, INVALID, 1175 /* [DC] */ INVALID, INVALID, INVALID, INVALID, 1176 1177 /* [E0] */ INVALID, INVALID, INVALID, INVALID, 1178 /* [E4] */ INVALID, INVALID, INVALID, INVALID, 1179 /* [E8] */ INVALID, INVALID, INVALID, INVALID, 1180 /* [EC] */ INVALID, INVALID, INVALID, INVALID, 1181 1182 /* [F0] */ INVALID, INVALID, INVALID, INVALID, 1183 /* [F4] */ INVALID, TNSZvr("pdep",VEX_RMrX,5),TNSZvr("mulx",VEX_RMrX,5),TNSZvr("shrx",VEX_VRMrX,5), 1184 /* [F8] */ INVALID, INVALID, INVALID, INVALID, 1185 /* [FC] */ INVALID, INVALID, INVALID, INVALID, 1186 }; 1187 1188 const instable_t dis_opAVXF30F38[256] = { 1189 /* [00] */ INVALID, INVALID, INVALID, INVALID, 1190 /* [04] */ INVALID, INVALID, INVALID, INVALID, 1191 /* [08] */ INVALID, INVALID, INVALID, INVALID, 1192 /* [0C] */ INVALID, INVALID, INVALID, INVALID, 1193 1194 /* [10] */ INVALID, INVALID, INVALID, INVALID, 1195 /* [14] */ INVALID, INVALID, INVALID, INVALID, 1196 /* [18] */ INVALID, INVALID, INVALID, INVALID, 1197 /* [1C] */ INVALID, INVALID, INVALID, INVALID, 1198 1199 /* [20] */ INVALID, INVALID, INVALID, INVALID, 1200 /* [24] */ INVALID, INVALID, INVALID, INVALID, 1201 /* [28] */ INVALID, INVALID, INVALID, INVALID, 1202 /* [2C] */ INVALID, INVALID, INVALID, INVALID, 1203 1204 /* [30] */ INVALID, INVALID, INVALID, INVALID, 1205 /* [34] */ INVALID, INVALID, INVALID, INVALID, 1206 /* [38] */ INVALID, INVALID, INVALID, INVALID, 1207 /* [3C] */ INVALID, INVALID, INVALID, INVALID, 1208 1209 /* [40] */ INVALID, INVALID, INVALID, INVALID, 1210 /* [44] */ INVALID, INVALID, INVALID, INVALID, 1211 /* [48] */ INVALID, INVALID, INVALID, INVALID, 1212 /* [4C] */ INVALID, INVALID, INVALID, INVALID, 1213 1214 /* [50] */ INVALID, INVALID, INVALID, INVALID, 1215 /* [54] */ INVALID, INVALID, INVALID, INVALID, 1216 /* [58] */ INVALID, INVALID, INVALID, INVALID, 1217 /* [5C] */ INVALID, INVALID, INVALID, INVALID, 1218 1219 /* [60] */ INVALID, INVALID, INVALID, INVALID, 1220 /* [64] */ INVALID, INVALID, INVALID, INVALID, 1221 /* [68] */ INVALID, INVALID, INVALID, INVALID, 1222 /* [6C] */ INVALID, INVALID, INVALID, INVALID, 1223 1224 /* [70] */ INVALID, INVALID, INVALID, INVALID, 1225 /* [74] */ INVALID, INVALID, INVALID, INVALID, 1226 /* [78] */ INVALID, INVALID, INVALID, INVALID, 1227 /* [7C] */ INVALID, INVALID, INVALID, INVALID, 1228 1229 /* [80] */ INVALID, INVALID, INVALID, INVALID, 1230 /* [84] */ INVALID, INVALID, INVALID, INVALID, 1231 /* [88] */ INVALID, INVALID, INVALID, INVALID, 1232 /* [0C] */ INVALID, INVALID, INVALID, INVALID, 1233 1234 /* [90] */ INVALID, INVALID, INVALID, INVALID, 1235 /* [94] */ INVALID, INVALID, INVALID, INVALID, 1236 /* [98] */ INVALID, INVALID, INVALID, INVALID, 1237 /* [9C] */ INVALID, INVALID, INVALID, INVALID, 1238 1239 /* [A0] */ INVALID, INVALID, INVALID, INVALID, 1240 /* [A4] */ INVALID, INVALID, INVALID, INVALID, 1241 /* [A8] */ INVALID, INVALID, INVALID, INVALID, 1242 /* [AC] */ INVALID, INVALID, INVALID, INVALID, 1243 1244 /* [B0] */ INVALID, INVALID, INVALID, INVALID, 1245 /* [B4] */ INVALID, INVALID, INVALID, INVALID, 1246 /* [B8] */ INVALID, INVALID, INVALID, INVALID, 1247 /* [BC] */ INVALID, INVALID, INVALID, INVALID, 1248 1249 /* [C0] */ INVALID, INVALID, INVALID, INVALID, 1250 /* [C4] */ INVALID, INVALID, INVALID, INVALID, 1251 /* [C8] */ INVALID, INVALID, INVALID, INVALID, 1252 /* [CC] */ INVALID, INVALID, INVALID, INVALID, 1253 1254 /* [D0] */ INVALID, INVALID, INVALID, INVALID, 1255 /* [D4] */ INVALID, INVALID, INVALID, INVALID, 1256 /* [D8] */ INVALID, INVALID, INVALID, INVALID, 1257 /* [DC] */ INVALID, INVALID, INVALID, INVALID, 1258 1259 /* [E0] */ INVALID, INVALID, INVALID, INVALID, 1260 /* [E4] */ INVALID, INVALID, INVALID, INVALID, 1261 /* [E8] */ INVALID, INVALID, INVALID, INVALID, 1262 /* [EC] */ INVALID, INVALID, INVALID, INVALID, 1263 1264 /* [F0] */ INVALID, INVALID, INVALID, INVALID, 1265 /* [F4] */ INVALID, TNSZvr("pext",VEX_RMrX,5),INVALID, TNSZvr("sarx",VEX_VRMrX,5), 1266 /* [F8] */ INVALID, INVALID, INVALID, INVALID, 1267 /* [FC] */ INVALID, INVALID, INVALID, INVALID, 1268 }; 1269 /* 1270 * Decode table for SIMD instructions with the repz (0xf3) prefix. 1271 */ 1272 const instable_t dis_opSIMDrepz[256] = { 1273 /* [00] */ INVALID, INVALID, INVALID, INVALID, 1274 /* [04] */ INVALID, INVALID, INVALID, INVALID, 1275 /* [08] */ INVALID, INVALID, INVALID, INVALID, 1276 /* [0C] */ INVALID, INVALID, INVALID, INVALID, 1277 1278 /* [10] */ TNSZ("movss",XMM,4), TNSZ("movss",XMMS,4), TNSZ("movsldup",XMM,16),INVALID, 1279 /* [14] */ INVALID, INVALID, TNSZ("movshdup",XMM,16),INVALID, 1280 /* [18] */ INVALID, INVALID, INVALID, INVALID, 1281 /* [1C] */ INVALID, INVALID, INVALID, INVALID, 1282 1283 /* [20] */ INVALID, INVALID, INVALID, INVALID, 1284 /* [24] */ INVALID, INVALID, INVALID, INVALID, 1285 /* [28] */ INVALID, INVALID, TNSZ("cvtsi2ss",XMM3MX,4),TNSZ("movntss",XMMMS,4), 1286 /* [2C] */ TNSZ("cvttss2si",XMMXM3,4),TNSZ("cvtss2si",XMMXM3,4),INVALID, INVALID, 1287 1288 /* [30] */ INVALID, INVALID, INVALID, INVALID, 1289 /* [34] */ INVALID, INVALID, INVALID, INVALID, 1290 /* [38] */ INVALID, INVALID, INVALID, INVALID, 1291 /* [3C] */ INVALID, INVALID, INVALID, INVALID, 1292 1293 /* [40] */ INVALID, INVALID, INVALID, INVALID, 1294 /* [44] */ INVALID, INVALID, INVALID, INVALID, 1295 /* [48] */ INVALID, INVALID, INVALID, INVALID, 1296 /* [4C] */ INVALID, INVALID, INVALID, INVALID, 1297 1298 /* [50] */ INVALID, TNSZ("sqrtss",XMM,4), TNSZ("rsqrtss",XMM,4), TNSZ("rcpss",XMM,4), 1299 /* [54] */ INVALID, INVALID, INVALID, INVALID, 1300 /* [58] */ TNSZ("addss",XMM,4), TNSZ("mulss",XMM,4), TNSZ("cvtss2sd",XMM,4), TNSZ("cvttps2dq",XMM,16), 1301 /* [5C] */ TNSZ("subss",XMM,4), TNSZ("minss",XMM,4), TNSZ("divss",XMM,4), TNSZ("maxss",XMM,4), 1302 1303 /* [60] */ INVALID, INVALID, INVALID, INVALID, 1304 /* [64] */ INVALID, INVALID, INVALID, INVALID, 1305 /* [68] */ INVALID, INVALID, INVALID, INVALID, 1306 /* [6C] */ INVALID, INVALID, INVALID, TNSZ("movdqu",XMM,16), 1307 1308 /* [70] */ TNSZ("pshufhw",XMMP,16),INVALID, INVALID, INVALID, 1309 /* [74] */ INVALID, INVALID, INVALID, INVALID, 1310 /* [78] */ INVALID, INVALID, INVALID, INVALID, 1311 /* [7C] */ INVALID, INVALID, TNSZ("movq",XMM,8), TNSZ("movdqu",XMMS,16), 1312 1313 /* [80] */ INVALID, INVALID, INVALID, INVALID, 1314 /* [84] */ INVALID, INVALID, INVALID, INVALID, 1315 /* [88] */ INVALID, INVALID, INVALID, INVALID, 1316 /* [0C] */ INVALID, INVALID, INVALID, INVALID, 1317 1318 /* [90] */ INVALID, INVALID, INVALID, INVALID, 1319 /* [94] */ INVALID, INVALID, INVALID, INVALID, 1320 /* [98] */ INVALID, INVALID, INVALID, INVALID, 1321 /* [9C] */ INVALID, INVALID, INVALID, INVALID, 1322 1323 /* [A0] */ INVALID, INVALID, INVALID, INVALID, 1324 /* [A4] */ INVALID, INVALID, INVALID, INVALID, 1325 /* [A8] */ INVALID, INVALID, INVALID, INVALID, 1326 /* [AC] */ INVALID, INVALID, INVALID, INVALID, 1327 1328 /* [B0] */ INVALID, INVALID, INVALID, INVALID, 1329 /* [B4] */ INVALID, INVALID, INVALID, INVALID, 1330 /* [B8] */ TS("popcnt",MRw), INVALID, INVALID, INVALID, 1331 /* [BC] */ TNSZ("tzcnt",MRw,5), TS("lzcnt",MRw), INVALID, INVALID, 1332 1333 /* [C0] */ INVALID, INVALID, TNSZ("cmpss",XMMP,4), INVALID, 1334 /* [C4] */ INVALID, INVALID, INVALID, INVALID, 1335 /* [C8] */ INVALID, INVALID, INVALID, INVALID, 1336 /* [CC] */ INVALID, INVALID, INVALID, INVALID, 1337 1338 /* [D0] */ INVALID, INVALID, INVALID, INVALID, 1339 /* [D4] */ INVALID, INVALID, TNS("movq2dq",XMMMX), INVALID, 1340 /* [D8] */ INVALID, INVALID, INVALID, INVALID, 1341 /* [DC] */ INVALID, INVALID, INVALID, INVALID, 1342 1343 /* [E0] */ INVALID, INVALID, INVALID, INVALID, 1344 /* [E4] */ INVALID, INVALID, TNSZ("cvtdq2pd",XMM,8), INVALID, 1345 /* [E8] */ INVALID, INVALID, INVALID, INVALID, 1346 /* [EC] */ INVALID, INVALID, INVALID, INVALID, 1347 1348 /* [F0] */ INVALID, INVALID, INVALID, INVALID, 1349 /* [F4] */ INVALID, INVALID, INVALID, INVALID, 1350 /* [F8] */ INVALID, INVALID, INVALID, INVALID, 1351 /* [FC] */ INVALID, INVALID, INVALID, INVALID, 1352 }; 1353 1354 const instable_t dis_opAVXF30F[256] = { 1355 /* [00] */ INVALID, INVALID, INVALID, INVALID, 1356 /* [04] */ INVALID, INVALID, INVALID, INVALID, 1357 /* [08] */ INVALID, INVALID, INVALID, INVALID, 1358 /* [0C] */ INVALID, INVALID, INVALID, INVALID, 1359 1360 /* [10] */ TNSZ("vmovss",VEX_RMrX,4), TNSZ("vmovss",VEX_RRX,4), TNSZ("vmovsldup",VEX_MX,4), INVALID, 1361 /* [14] */ INVALID, INVALID, TNSZ("vmovshdup",VEX_MX,4), INVALID, 1362 /* [18] */ INVALID, INVALID, INVALID, INVALID, 1363 /* [1C] */ INVALID, INVALID, INVALID, INVALID, 1364 1365 /* [20] */ INVALID, INVALID, INVALID, INVALID, 1366 /* [24] */ INVALID, INVALID, INVALID, INVALID, 1367 /* [28] */ INVALID, INVALID, TNSZ("vcvtsi2ss",VEX_RMrX,4),INVALID, 1368 /* [2C] */ TNSZ("vcvttss2si",VEX_MR,4),TNSZ("vcvtss2si",VEX_MR,4),INVALID, INVALID, 1369 1370 /* [30] */ INVALID, INVALID, INVALID, INVALID, 1371 /* [34] */ INVALID, INVALID, INVALID, INVALID, 1372 /* [38] */ INVALID, INVALID, INVALID, INVALID, 1373 /* [3C] */ INVALID, INVALID, INVALID, INVALID, 1374 1375 /* [40] */ INVALID, INVALID, INVALID, INVALID, 1376 /* [44] */ INVALID, INVALID, INVALID, INVALID, 1377 /* [48] */ INVALID, INVALID, INVALID, INVALID, 1378 /* [4C] */ INVALID, INVALID, INVALID, INVALID, 1379 1380 /* [50] */ INVALID, TNSZ("vsqrtss",VEX_RMrX,4), TNSZ("vrsqrtss",VEX_RMrX,4), TNSZ("vrcpss",VEX_RMrX,4), 1381 /* [54] */ INVALID, INVALID, INVALID, INVALID, 1382 /* [58] */ TNSZ("vaddss",VEX_RMrX,4), TNSZ("vmulss",VEX_RMrX,4), TNSZ("vcvtss2sd",VEX_RMrX,4), TNSZ("vcvttps2dq",VEX_MX,16), 1383 /* [5C] */ TNSZ("vsubss",VEX_RMrX,4), TNSZ("vminss",VEX_RMrX,4), TNSZ("vdivss",VEX_RMrX,4), TNSZ("vmaxss",VEX_RMrX,4), 1384 1385 /* [60] */ INVALID, INVALID, INVALID, INVALID, 1386 /* [64] */ INVALID, INVALID, INVALID, INVALID, 1387 /* [68] */ INVALID, INVALID, INVALID, INVALID, 1388 /* [6C] */ INVALID, INVALID, INVALID, TNSZ("vmovdqu",VEX_MX,16), 1389 1390 /* [70] */ TNSZ("vpshufhw",VEX_MXI,16),INVALID, INVALID, INVALID, 1391 /* [74] */ INVALID, INVALID, INVALID, INVALID, 1392 /* [78] */ INVALID, INVALID, INVALID, INVALID, 1393 /* [7C] */ INVALID, INVALID, TNSZ("vmovq",VEX_MX,8), TNSZ("vmovdqu",VEX_RX,16), 1394 1395 /* [80] */ INVALID, INVALID, INVALID, INVALID, 1396 /* [84] */ INVALID, INVALID, INVALID, INVALID, 1397 /* [88] */ INVALID, INVALID, INVALID, INVALID, 1398 /* [0C] */ INVALID, INVALID, INVALID, INVALID, 1399 1400 /* [90] */ INVALID, INVALID, INVALID, INVALID, 1401 /* [94] */ INVALID, INVALID, INVALID, INVALID, 1402 /* [98] */ INVALID, INVALID, INVALID, INVALID, 1403 /* [9C] */ INVALID, INVALID, INVALID, INVALID, 1404 1405 /* [A0] */ INVALID, INVALID, INVALID, INVALID, 1406 /* [A4] */ INVALID, INVALID, INVALID, INVALID, 1407 /* [A8] */ INVALID, INVALID, INVALID, INVALID, 1408 /* [AC] */ INVALID, INVALID, INVALID, INVALID, 1409 1410 /* [B0] */ INVALID, INVALID, INVALID, INVALID, 1411 /* [B4] */ INVALID, INVALID, INVALID, INVALID, 1412 /* [B8] */ INVALID, INVALID, INVALID, INVALID, 1413 /* [BC] */ INVALID, INVALID, INVALID, INVALID, 1414 1415 /* [C0] */ INVALID, INVALID, TNSZ("vcmpss",VEX_RMRX,4), INVALID, 1416 /* [C4] */ INVALID, INVALID, INVALID, INVALID, 1417 /* [C8] */ INVALID, INVALID, INVALID, INVALID, 1418 /* [CC] */ INVALID, INVALID, INVALID, INVALID, 1419 1420 /* [D0] */ INVALID, INVALID, INVALID, INVALID, 1421 /* [D4] */ INVALID, INVALID, INVALID, INVALID, 1422 /* [D8] */ INVALID, INVALID, INVALID, INVALID, 1423 /* [DC] */ INVALID, INVALID, INVALID, INVALID, 1424 1425 /* [E0] */ INVALID, INVALID, INVALID, INVALID, 1426 /* [E4] */ INVALID, INVALID, TNSZ("vcvtdq2pd",VEX_MX,8), INVALID, 1427 /* [E8] */ INVALID, INVALID, INVALID, INVALID, 1428 /* [EC] */ INVALID, INVALID, INVALID, INVALID, 1429 1430 /* [F0] */ INVALID, INVALID, INVALID, INVALID, 1431 /* [F4] */ INVALID, INVALID, INVALID, INVALID, 1432 /* [F8] */ INVALID, INVALID, INVALID, INVALID, 1433 /* [FC] */ INVALID, INVALID, INVALID, INVALID, 1434 }; 1435 1436 /* 1437 * Table for instructions with an EVEX prefix. 1438 */ 1439 const instable_t dis_opAVX62[256] = { 1440 /* [00] */ INVALID, INVALID, INVALID, INVALID, 1441 /* [04] */ INVALID, INVALID, INVALID, INVALID, 1442 /* [08] */ INVALID, INVALID, INVALID, INVALID, 1443 /* [0C] */ INVALID, INVALID, INVALID, INVALID, 1444 1445 /* [10] */ TNS("vmovup",EVEX_MX), TNS("vmovup",EVEX_RX), INVALID, INVALID, 1446 /* [14] */ INVALID, INVALID, INVALID, INVALID, 1447 /* [18] */ INVALID, INVALID, INVALID, INVALID, 1448 /* [1C] */ INVALID, INVALID, INVALID, INVALID, 1449 1450 /* [20] */ INVALID, INVALID, INVALID, INVALID, 1451 /* [24] */ INVALID, INVALID, INVALID, INVALID, 1452 /* [28] */ TNS("vmovap",EVEX_MX), TNS("vmovap",EVEX_RX), INVALID, INVALID, 1453 /* [2C] */ INVALID, INVALID, INVALID, INVALID, 1454 1455 /* [30] */ INVALID, INVALID, INVALID, INVALID, 1456 /* [34] */ INVALID, INVALID, INVALID, INVALID, 1457 /* [38] */ INVALID, INVALID, INVALID, INVALID, 1458 /* [3C] */ INVALID, INVALID, INVALID, INVALID, 1459 1460 /* [40] */ INVALID, INVALID, INVALID, INVALID, 1461 /* [44] */ INVALID, INVALID, INVALID, INVALID, 1462 /* [48] */ INVALID, INVALID, INVALID, INVALID, 1463 /* [4C] */ INVALID, INVALID, INVALID, INVALID, 1464 1465 /* [50] */ INVALID, INVALID, INVALID, INVALID, 1466 /* [54] */ INVALID, INVALID, INVALID, INVALID, 1467 /* [58] */ INVALID, INVALID, INVALID, INVALID, 1468 /* [5C] */ INVALID, INVALID, INVALID, INVALID, 1469 1470 /* [60] */ INVALID, INVALID, INVALID, INVALID, 1471 /* [64] */ INVALID, INVALID, INVALID, INVALID, 1472 /* [68] */ INVALID, INVALID, INVALID, INVALID, 1473 /* [6C] */ INVALID, INVALID, INVALID, TNS("vmovdq",EVEX_MX), 1474 1475 /* [70] */ INVALID, INVALID, INVALID, INVALID, 1476 /* [74] */ INVALID, INVALID, INVALID, INVALID, 1477 /* [78] */ INVALID, INVALID, INVALID, INVALID, 1478 /* [7C] */ INVALID, INVALID, INVALID, TNS("vmovdq",EVEX_RX), 1479 1480 /* [80] */ INVALID, INVALID, INVALID, INVALID, 1481 /* [84] */ INVALID, INVALID, INVALID, INVALID, 1482 /* [88] */ INVALID, INVALID, INVALID, INVALID, 1483 /* [0C] */ INVALID, INVALID, INVALID, INVALID, 1484 1485 /* [90] */ INVALID, INVALID, INVALID, INVALID, 1486 /* [94] */ INVALID, INVALID, INVALID, INVALID, 1487 /* [98] */ INVALID, INVALID, INVALID, INVALID, 1488 /* [9C] */ INVALID, INVALID, INVALID, INVALID, 1489 1490 /* [A0] */ INVALID, INVALID, INVALID, INVALID, 1491 /* [A4] */ INVALID, INVALID, INVALID, INVALID, 1492 /* [A8] */ INVALID, INVALID, INVALID, INVALID, 1493 /* [AC] */ INVALID, INVALID, INVALID, INVALID, 1494 1495 /* [B0] */ INVALID, INVALID, INVALID, INVALID, 1496 /* [B4] */ INVALID, INVALID, INVALID, INVALID, 1497 /* [B8] */ INVALID, INVALID, INVALID, INVALID, 1498 /* [BC] */ INVALID, INVALID, INVALID, INVALID, 1499 1500 /* [C0] */ INVALID, INVALID, INVALID, INVALID, 1501 /* [C4] */ INVALID, INVALID, INVALID, INVALID, 1502 /* [C8] */ INVALID, INVALID, INVALID, INVALID, 1503 /* [CC] */ INVALID, INVALID, INVALID, INVALID, 1504 1505 /* [D0] */ INVALID, INVALID, INVALID, INVALID, 1506 /* [D4] */ INVALID, INVALID, INVALID, INVALID, 1507 /* [D8] */ INVALID, INVALID, INVALID, INVALID, 1508 /* [DC] */ INVALID, INVALID, INVALID, INVALID, 1509 1510 /* [E0] */ INVALID, INVALID, INVALID, INVALID, 1511 /* [E4] */ INVALID, INVALID, INVALID, INVALID, 1512 /* [E8] */ INVALID, INVALID, INVALID, INVALID, 1513 /* [EC] */ INVALID, INVALID, INVALID, INVALID, 1514 1515 /* [F0] */ INVALID, INVALID, INVALID, INVALID, 1516 /* [F4] */ INVALID, INVALID, INVALID, INVALID, 1517 /* [F8] */ INVALID, INVALID, INVALID, INVALID, 1518 /* [FC] */ INVALID, INVALID, INVALID, INVALID, 1519 }; 1520 1521 /* 1522 * The following two tables are used to encode crc32 and movbe 1523 * since they share the same opcodes. 1524 */ 1525 const instable_t dis_op0F38F0[2] = { 1526 /* [00] */ TNS("crc32b",CRC32), 1527 TS("movbe",MOVBE), 1528 }; 1529 1530 const instable_t dis_op0F38F1[2] = { 1531 /* [00] */ TS("crc32",CRC32), 1532 TS("movbe",MOVBE), 1533 }; 1534 1535 /* 1536 * The following table is used to distinguish between adox and adcx which share 1537 * the same opcodes. 1538 */ 1539 const instable_t dis_op0F38F6[2] = { 1540 /* [00] */ TNS("adcx",ADX), 1541 TNS("adox",ADX), 1542 }; 1543 1544 const instable_t dis_op0F38[256] = { 1545 /* [00] */ TNSZ("pshufb",XMM_66o,16),TNSZ("phaddw",XMM_66o,16),TNSZ("phaddd",XMM_66o,16),TNSZ("phaddsw",XMM_66o,16), 1546 /* [04] */ TNSZ("pmaddubsw",XMM_66o,16),TNSZ("phsubw",XMM_66o,16), TNSZ("phsubd",XMM_66o,16),TNSZ("phsubsw",XMM_66o,16), 1547 /* [08] */ TNSZ("psignb",XMM_66o,16),TNSZ("psignw",XMM_66o,16),TNSZ("psignd",XMM_66o,16),TNSZ("pmulhrsw",XMM_66o,16), 1548 /* [0C] */ INVALID, INVALID, INVALID, INVALID, 1549 1550 /* [10] */ TNSZ("pblendvb",XMM_66r,16),INVALID, INVALID, INVALID, 1551 /* [14] */ TNSZ("blendvps",XMM_66r,16),TNSZ("blendvpd",XMM_66r,16),INVALID, TNSZ("ptest",XMM_66r,16), 1552 /* [18] */ INVALID, INVALID, INVALID, INVALID, 1553 /* [1C] */ TNSZ("pabsb",XMM_66o,16),TNSZ("pabsw",XMM_66o,16),TNSZ("pabsd",XMM_66o,16),INVALID, 1554 1555 /* [20] */ TNSZ("pmovsxbw",XMM_66r,16),TNSZ("pmovsxbd",XMM_66r,16),TNSZ("pmovsxbq",XMM_66r,16),TNSZ("pmovsxwd",XMM_66r,16), 1556 /* [24] */ TNSZ("pmovsxwq",XMM_66r,16),TNSZ("pmovsxdq",XMM_66r,16),INVALID, INVALID, 1557 /* [28] */ TNSZ("pmuldq",XMM_66r,16),TNSZ("pcmpeqq",XMM_66r,16),TNSZ("movntdqa",XMMM_66r,16),TNSZ("packusdw",XMM_66r,16), 1558 /* [2C] */ INVALID, INVALID, INVALID, INVALID, 1559 1560 /* [30] */ TNSZ("pmovzxbw",XMM_66r,16),TNSZ("pmovzxbd",XMM_66r,16),TNSZ("pmovzxbq",XMM_66r,16),TNSZ("pmovzxwd",XMM_66r,16), 1561 /* [34] */ TNSZ("pmovzxwq",XMM_66r,16),TNSZ("pmovzxdq",XMM_66r,16),INVALID, TNSZ("pcmpgtq",XMM_66r,16), 1562 /* [38] */ TNSZ("pminsb",XMM_66r,16),TNSZ("pminsd",XMM_66r,16),TNSZ("pminuw",XMM_66r,16),TNSZ("pminud",XMM_66r,16), 1563 /* [3C] */ TNSZ("pmaxsb",XMM_66r,16),TNSZ("pmaxsd",XMM_66r,16),TNSZ("pmaxuw",XMM_66r,16),TNSZ("pmaxud",XMM_66r,16), 1564 1565 /* [40] */ TNSZ("pmulld",XMM_66r,16),TNSZ("phminposuw",XMM_66r,16),INVALID, INVALID, 1566 /* [44] */ INVALID, INVALID, INVALID, INVALID, 1567 /* [48] */ INVALID, INVALID, INVALID, INVALID, 1568 /* [4C] */ INVALID, INVALID, INVALID, INVALID, 1569 1570 /* [50] */ INVALID, INVALID, INVALID, INVALID, 1571 /* [54] */ INVALID, INVALID, INVALID, INVALID, 1572 /* [58] */ INVALID, INVALID, INVALID, INVALID, 1573 /* [5C] */ INVALID, INVALID, INVALID, INVALID, 1574 1575 /* [60] */ INVALID, INVALID, INVALID, INVALID, 1576 /* [64] */ INVALID, INVALID, INVALID, INVALID, 1577 /* [68] */ INVALID, INVALID, INVALID, INVALID, 1578 /* [6C] */ INVALID, INVALID, INVALID, INVALID, 1579 1580 /* [70] */ INVALID, INVALID, INVALID, INVALID, 1581 /* [74] */ INVALID, INVALID, INVALID, INVALID, 1582 /* [78] */ INVALID, INVALID, INVALID, INVALID, 1583 /* [7C] */ INVALID, INVALID, INVALID, INVALID, 1584 1585 /* [80] */ TNSy("invept", RM_66r), TNSy("invvpid", RM_66r),TNSy("invpcid", RM_66r),INVALID, 1586 /* [84] */ INVALID, INVALID, INVALID, INVALID, 1587 /* [88] */ INVALID, INVALID, INVALID, INVALID, 1588 /* [8C] */ INVALID, INVALID, INVALID, INVALID, 1589 1590 /* [90] */ INVALID, INVALID, INVALID, INVALID, 1591 /* [94] */ INVALID, INVALID, INVALID, INVALID, 1592 /* [98] */ INVALID, INVALID, INVALID, INVALID, 1593 /* [9C] */ INVALID, INVALID, INVALID, INVALID, 1594 1595 /* [A0] */ INVALID, INVALID, INVALID, INVALID, 1596 /* [A4] */ INVALID, INVALID, INVALID, INVALID, 1597 /* [A8] */ INVALID, INVALID, INVALID, INVALID, 1598 /* [AC] */ INVALID, INVALID, INVALID, INVALID, 1599 1600 /* [B0] */ INVALID, INVALID, INVALID, INVALID, 1601 /* [B4] */ INVALID, INVALID, INVALID, INVALID, 1602 /* [B8] */ INVALID, INVALID, INVALID, INVALID, 1603 /* [BC] */ INVALID, INVALID, INVALID, INVALID, 1604 1605 /* [C0] */ INVALID, INVALID, INVALID, INVALID, 1606 /* [C4] */ INVALID, INVALID, INVALID, INVALID, 1607 /* [C8] */ TNSZ("sha1nexte",XMM,16),TNSZ("sha1msg1",XMM,16),TNSZ("sha1msg2",XMM,16),TNSZ("sha256rnds2",XMM,16), 1608 /* [CC] */ TNSZ("sha256msg1",XMM,16),TNSZ("sha256msg2",XMM,16),INVALID, INVALID, 1609 1610 /* [D0] */ INVALID, INVALID, INVALID, INVALID, 1611 /* [D4] */ INVALID, INVALID, INVALID, INVALID, 1612 /* [D8] */ INVALID, INVALID, INVALID, TNSZ("aesimc",XMM_66r,16), 1613 /* [DC] */ TNSZ("aesenc",XMM_66r,16),TNSZ("aesenclast",XMM_66r,16),TNSZ("aesdec",XMM_66r,16),TNSZ("aesdeclast",XMM_66r,16), 1614 1615 /* [E0] */ INVALID, INVALID, INVALID, INVALID, 1616 /* [E4] */ INVALID, INVALID, INVALID, INVALID, 1617 /* [E8] */ INVALID, INVALID, INVALID, INVALID, 1618 /* [EC] */ INVALID, INVALID, INVALID, INVALID, 1619 /* [F0] */ IND(dis_op0F38F0), IND(dis_op0F38F1), INVALID, INVALID, 1620 /* [F4] */ INVALID, INVALID, IND(dis_op0F38F6), INVALID, 1621 /* [F8] */ INVALID, INVALID, INVALID, INVALID, 1622 /* [FC] */ INVALID, INVALID, INVALID, INVALID, 1623 }; 1624 1625 const instable_t dis_opAVX660F38[256] = { 1626 /* [00] */ TNSZ("vpshufb",VEX_RMrX,16),TNSZ("vphaddw",VEX_RMrX,16),TNSZ("vphaddd",VEX_RMrX,16),TNSZ("vphaddsw",VEX_RMrX,16), 1627 /* [04] */ TNSZ("vpmaddubsw",VEX_RMrX,16),TNSZ("vphsubw",VEX_RMrX,16), TNSZ("vphsubd",VEX_RMrX,16),TNSZ("vphsubsw",VEX_RMrX,16), 1628 /* [08] */ TNSZ("vpsignb",VEX_RMrX,16),TNSZ("vpsignw",VEX_RMrX,16),TNSZ("vpsignd",VEX_RMrX,16),TNSZ("vpmulhrsw",VEX_RMrX,16), 1629 /* [0C] */ TNSZ("vpermilps",VEX_RMrX,8),TNSZ("vpermilpd",VEX_RMrX,16),TNSZ("vtestps",VEX_RRI,8), TNSZ("vtestpd",VEX_RRI,16), 1630 1631 /* [10] */ INVALID, INVALID, INVALID, TNSZ("vcvtph2ps",VEX_MX,16), 1632 /* [14] */ INVALID, INVALID, TNSZ("vpermps",VEX_RMrX,16),TNSZ("vptest",VEX_RRI,16), 1633 /* [18] */ TNSZ("vbroadcastss",VEX_MX,4),TNSZ("vbroadcastsd",VEX_MX,8),TNSZ("vbroadcastf128",VEX_MX,16),INVALID, 1634 /* [1C] */ TNSZ("vpabsb",VEX_MX,16),TNSZ("vpabsw",VEX_MX,16),TNSZ("vpabsd",VEX_MX,16),INVALID, 1635 1636 /* [20] */ TNSZ("vpmovsxbw",VEX_MX,16),TNSZ("vpmovsxbd",VEX_MX,16),TNSZ("vpmovsxbq",VEX_MX,16),TNSZ("vpmovsxwd",VEX_MX,16), 1637 /* [24] */ TNSZ("vpmovsxwq",VEX_MX,16),TNSZ("vpmovsxdq",VEX_MX,16),INVALID, INVALID, 1638 /* [28] */ TNSZ("vpmuldq",VEX_RMrX,16),TNSZ("vpcmpeqq",VEX_RMrX,16),TNSZ("vmovntdqa",VEX_MX,16),TNSZ("vpackusdw",VEX_RMrX,16), 1639 /* [2C] */ TNSZ("vmaskmovps",VEX_RMrX,8),TNSZ("vmaskmovpd",VEX_RMrX,16),TNSZ("vmaskmovps",VEX_RRM,8),TNSZ("vmaskmovpd",VEX_RRM,16), 1640 1641 /* [30] */ TNSZ("vpmovzxbw",VEX_MX,16),TNSZ("vpmovzxbd",VEX_MX,16),TNSZ("vpmovzxbq",VEX_MX,16),TNSZ("vpmovzxwd",VEX_MX,16), 1642 /* [34] */ TNSZ("vpmovzxwq",VEX_MX,16),TNSZ("vpmovzxdq",VEX_MX,16),TNSZ("vpermd",VEX_RMrX,16),TNSZ("vpcmpgtq",VEX_RMrX,16), 1643 /* [38] */ TNSZ("vpminsb",VEX_RMrX,16),TNSZ("vpminsd",VEX_RMrX,16),TNSZ("vpminuw",VEX_RMrX,16),TNSZ("vpminud",VEX_RMrX,16), 1644 /* [3C] */ TNSZ("vpmaxsb",VEX_RMrX,16),TNSZ("vpmaxsd",VEX_RMrX,16),TNSZ("vpmaxuw",VEX_RMrX,16),TNSZ("vpmaxud",VEX_RMrX,16), 1645 1646 /* [40] */ TNSZ("vpmulld",VEX_RMrX,16),TNSZ("vphminposuw",VEX_MX,16),INVALID, INVALID, 1647 /* [44] */ INVALID, TSaZ("vpsrlv",VEX_RMrX,16),TNSZ("vpsravd",VEX_RMrX,16),TSaZ("vpsllv",VEX_RMrX,16), 1648 /* [48] */ INVALID, INVALID, INVALID, INVALID, 1649 /* [4C] */ INVALID, INVALID, INVALID, INVALID, 1650 1651 /* [50] */ INVALID, INVALID, INVALID, INVALID, 1652 /* [54] */ INVALID, INVALID, INVALID, INVALID, 1653 /* [58] */ TNSZ("vpbroadcastd",VEX_MX,16),TNSZ("vpbroadcastq",VEX_MX,16),TNSZ("vbroadcasti128",VEX_MX,16),INVALID, 1654 /* [5C] */ INVALID, INVALID, INVALID, INVALID, 1655 1656 /* [60] */ INVALID, INVALID, INVALID, INVALID, 1657 /* [64] */ INVALID, INVALID, INVALID, INVALID, 1658 /* [68] */ INVALID, INVALID, INVALID, INVALID, 1659 /* [6C] */ INVALID, INVALID, INVALID, INVALID, 1660 1661 /* [70] */ INVALID, INVALID, INVALID, INVALID, 1662 /* [74] */ INVALID, INVALID, INVALID, INVALID, 1663 /* [78] */ TNSZ("vpbroadcastb",VEX_MX,16),TNSZ("vpbroadcastw",VEX_MX,16),INVALID, INVALID, 1664 /* [7C] */ INVALID, INVALID, INVALID, INVALID, 1665 1666 /* [80] */ INVALID, INVALID, INVALID, INVALID, 1667 /* [84] */ INVALID, INVALID, INVALID, INVALID, 1668 /* [88] */ INVALID, INVALID, INVALID, INVALID, 1669 /* [8C] */ TSaZ("vpmaskmov",VEX_RMrX,16),INVALID, TSaZ("vpmaskmov",VEX_RRM,16),INVALID, 1670 1671 /* [90] */ TNSZ("vpgatherd",VEX_SbVM,16),TNSZ("vpgatherq",VEX_SbVM,16),TNSZ("vgatherdp",VEX_SbVM,16),TNSZ("vgatherqp",VEX_SbVM,16), 1672 /* [94] */ INVALID, INVALID, TNSZ("vfmaddsub132p",FMA,16),TNSZ("vfmsubadd132p",FMA,16), 1673 /* [98] */ TNSZ("vfmadd132p",FMA,16),TNSZ("vfmadd132s",FMA,16),TNSZ("vfmsub132p",FMA,16),TNSZ("vfmsub132s",FMA,16), 1674 /* [9C] */ TNSZ("vfnmadd132p",FMA,16),TNSZ("vfnmadd132s",FMA,16),TNSZ("vfnmsub132p",FMA,16),TNSZ("vfnmsub132s",FMA,16), 1675 1676 /* [A0] */ INVALID, INVALID, INVALID, INVALID, 1677 /* [A4] */ INVALID, INVALID, TNSZ("vfmaddsub213p",FMA,16),TNSZ("vfmsubadd213p",FMA,16), 1678 /* [A8] */ TNSZ("vfmadd213p",FMA,16),TNSZ("vfmadd213s",FMA,16),TNSZ("vfmsub213p",FMA,16),TNSZ("vfmsub213s",FMA,16), 1679 /* [AC] */ TNSZ("vfnmadd213p",FMA,16),TNSZ("vfnmadd213s",FMA,16),TNSZ("vfnmsub213p",FMA,16),TNSZ("vfnmsub213s",FMA,16), 1680 1681 /* [B0] */ INVALID, INVALID, INVALID, INVALID, 1682 /* [B4] */ INVALID, INVALID, TNSZ("vfmaddsub231p",FMA,16),TNSZ("vfmsubadd231p",FMA,16), 1683 /* [B8] */ TNSZ("vfmadd231p",FMA,16),TNSZ("vfmadd231s",FMA,16),TNSZ("vfmsub231p",FMA,16),TNSZ("vfmsub231s",FMA,16), 1684 /* [BC] */ TNSZ("vfnmadd231p",FMA,16),TNSZ("vfnmadd231s",FMA,16),TNSZ("vfnmsub231p",FMA,16),TNSZ("vfnmsub231s",FMA,16), 1685 1686 /* [C0] */ INVALID, INVALID, INVALID, INVALID, 1687 /* [C4] */ INVALID, INVALID, INVALID, INVALID, 1688 /* [C8] */ INVALID, INVALID, INVALID, INVALID, 1689 /* [CC] */ INVALID, INVALID, INVALID, INVALID, 1690 1691 /* [D0] */ INVALID, INVALID, INVALID, INVALID, 1692 /* [D4] */ INVALID, INVALID, INVALID, INVALID, 1693 /* [D8] */ INVALID, INVALID, INVALID, TNSZ("vaesimc",VEX_MX,16), 1694 /* [DC] */ TNSZ("vaesenc",VEX_RMrX,16),TNSZ("vaesenclast",VEX_RMrX,16),TNSZ("vaesdec",VEX_RMrX,16),TNSZ("vaesdeclast",VEX_RMrX,16), 1695 1696 /* [E0] */ INVALID, INVALID, INVALID, INVALID, 1697 /* [E4] */ INVALID, INVALID, INVALID, INVALID, 1698 /* [E8] */ INVALID, INVALID, INVALID, INVALID, 1699 /* [EC] */ INVALID, INVALID, INVALID, INVALID, 1700 /* [F0] */ IND(dis_op0F38F0), IND(dis_op0F38F1), INVALID, INVALID, 1701 /* [F4] */ INVALID, INVALID, INVALID, TNSZvr("shlx",VEX_VRMrX,5), 1702 /* [F8] */ INVALID, INVALID, INVALID, INVALID, 1703 /* [FC] */ INVALID, INVALID, INVALID, INVALID, 1704 }; 1705 1706 const instable_t dis_op0F3A[256] = { 1707 /* [00] */ INVALID, INVALID, INVALID, INVALID, 1708 /* [04] */ INVALID, INVALID, INVALID, INVALID, 1709 /* [08] */ TNSZ("roundps",XMMP_66r,16),TNSZ("roundpd",XMMP_66r,16),TNSZ("roundss",XMMP_66r,16),TNSZ("roundsd",XMMP_66r,16), 1710 /* [0C] */ TNSZ("blendps",XMMP_66r,16),TNSZ("blendpd",XMMP_66r,16),TNSZ("pblendw",XMMP_66r,16),TNSZ("palignr",XMMP_66o,16), 1711 1712 /* [10] */ INVALID, INVALID, INVALID, INVALID, 1713 /* [14] */ TNSZ("pextrb",XMM3PM_66r,8),TNSZ("pextrw",XMM3PM_66r,16),TSZ("pextr",XMM3PM_66r,16),TNSZ("extractps",XMM3PM_66r,16), 1714 /* [18] */ INVALID, INVALID, INVALID, INVALID, 1715 /* [1C] */ INVALID, INVALID, INVALID, INVALID, 1716 1717 /* [20] */ TNSZ("pinsrb",XMMPRM_66r,8),TNSZ("insertps",XMMP_66r,16),TSZ("pinsr",XMMPRM_66r,16),INVALID, 1718 /* [24] */ INVALID, INVALID, INVALID, INVALID, 1719 /* [28] */ INVALID, INVALID, INVALID, INVALID, 1720 /* [2C] */ INVALID, INVALID, INVALID, INVALID, 1721 1722 /* [30] */ INVALID, INVALID, INVALID, INVALID, 1723 /* [34] */ INVALID, INVALID, INVALID, INVALID, 1724 /* [38] */ INVALID, INVALID, INVALID, INVALID, 1725 /* [3C] */ INVALID, INVALID, INVALID, INVALID, 1726 1727 /* [40] */ TNSZ("dpps",XMMP_66r,16),TNSZ("dppd",XMMP_66r,16),TNSZ("mpsadbw",XMMP_66r,16),INVALID, 1728 /* [44] */ TNSZ("pclmulqdq",XMMP_66r,16),INVALID, INVALID, INVALID, 1729 /* [48] */ INVALID, INVALID, INVALID, INVALID, 1730 /* [4C] */ INVALID, INVALID, INVALID, INVALID, 1731 1732 /* [50] */ INVALID, INVALID, INVALID, INVALID, 1733 /* [54] */ INVALID, INVALID, INVALID, INVALID, 1734 /* [58] */ INVALID, INVALID, INVALID, INVALID, 1735 /* [5C] */ INVALID, INVALID, INVALID, INVALID, 1736 1737 /* [60] */ TNSZ("pcmpestrm",XMMP_66r,16),TNSZ("pcmpestri",XMMP_66r,16),TNSZ("pcmpistrm",XMMP_66r,16),TNSZ("pcmpistri",XMMP_66r,16), 1738 /* [64] */ INVALID, INVALID, INVALID, INVALID, 1739 /* [68] */ INVALID, INVALID, INVALID, INVALID, 1740 /* [6C] */ INVALID, INVALID, INVALID, INVALID, 1741 1742 /* [70] */ INVALID, INVALID, INVALID, INVALID, 1743 /* [74] */ INVALID, INVALID, INVALID, INVALID, 1744 /* [78] */ INVALID, INVALID, INVALID, INVALID, 1745 /* [7C] */ INVALID, INVALID, INVALID, INVALID, 1746 1747 /* [80] */ INVALID, INVALID, INVALID, INVALID, 1748 /* [84] */ INVALID, INVALID, INVALID, INVALID, 1749 /* [88] */ INVALID, INVALID, INVALID, INVALID, 1750 /* [8C] */ INVALID, INVALID, INVALID, INVALID, 1751 1752 /* [90] */ INVALID, INVALID, INVALID, INVALID, 1753 /* [94] */ INVALID, INVALID, INVALID, INVALID, 1754 /* [98] */ INVALID, INVALID, INVALID, INVALID, 1755 /* [9C] */ INVALID, INVALID, INVALID, INVALID, 1756 1757 /* [A0] */ INVALID, INVALID, INVALID, INVALID, 1758 /* [A4] */ INVALID, INVALID, INVALID, INVALID, 1759 /* [A8] */ INVALID, INVALID, INVALID, INVALID, 1760 /* [AC] */ INVALID, INVALID, INVALID, INVALID, 1761 1762 /* [B0] */ INVALID, INVALID, INVALID, INVALID, 1763 /* [B4] */ INVALID, INVALID, INVALID, INVALID, 1764 /* [B8] */ INVALID, INVALID, INVALID, INVALID, 1765 /* [BC] */ INVALID, INVALID, INVALID, INVALID, 1766 1767 /* [C0] */ INVALID, INVALID, INVALID, INVALID, 1768 /* [C4] */ INVALID, INVALID, INVALID, INVALID, 1769 /* [C8] */ INVALID, INVALID, INVALID, INVALID, 1770 /* [CC] */ TNSZ("sha1rnds4",XMMP,16),INVALID, INVALID, INVALID, 1771 1772 /* [D0] */ INVALID, INVALID, INVALID, INVALID, 1773 /* [D4] */ INVALID, INVALID, INVALID, INVALID, 1774 /* [D8] */ INVALID, INVALID, INVALID, INVALID, 1775 /* [DC] */ INVALID, INVALID, INVALID, TNSZ("aeskeygenassist",XMMP_66r,16), 1776 1777 /* [E0] */ INVALID, INVALID, INVALID, INVALID, 1778 /* [E4] */ INVALID, INVALID, INVALID, INVALID, 1779 /* [E8] */ INVALID, INVALID, INVALID, INVALID, 1780 /* [EC] */ INVALID, INVALID, INVALID, INVALID, 1781 1782 /* [F0] */ INVALID, INVALID, INVALID, INVALID, 1783 /* [F4] */ INVALID, INVALID, INVALID, INVALID, 1784 /* [F8] */ INVALID, INVALID, INVALID, INVALID, 1785 /* [FC] */ INVALID, INVALID, INVALID, INVALID, 1786 }; 1787 1788 const instable_t dis_opAVX660F3A[256] = { 1789 /* [00] */ TNSZ("vpermq",VEX_MXI,16),TNSZ("vpermpd",VEX_MXI,16),TNSZ("vpblendd",VEX_RMRX,16),INVALID, 1790 /* [04] */ TNSZ("vpermilps",VEX_MXI,8),TNSZ("vpermilpd",VEX_MXI,16),TNSZ("vperm2f128",VEX_RMRX,16),INVALID, 1791 /* [08] */ TNSZ("vroundps",VEX_MXI,16),TNSZ("vroundpd",VEX_MXI,16),TNSZ("vroundss",VEX_RMRX,16),TNSZ("vroundsd",VEX_RMRX,16), 1792 /* [0C] */ TNSZ("vblendps",VEX_RMRX,16),TNSZ("vblendpd",VEX_RMRX,16),TNSZ("vpblendw",VEX_RMRX,16),TNSZ("vpalignr",VEX_RMRX,16), 1793 1794 /* [10] */ INVALID, INVALID, INVALID, INVALID, 1795 /* [14] */ TNSZ("vpextrb",VEX_RRi,8),TNSZ("vpextrw",VEX_RRi,16),TNSZ("vpextrd",VEX_RRi,16),TNSZ("vextractps",VEX_RM,16), 1796 /* [18] */ TNSZ("vinsertf128",VEX_RMRX,16),TNSZ("vextractf128",VEX_RX,16),INVALID, INVALID, 1797 /* [1C] */ INVALID, TNSZ("vcvtps2ph",VEX_RX,16), INVALID, INVALID, 1798 1799 /* [20] */ TNSZ("vpinsrb",VEX_RMRX,8),TNSZ("vinsertps",VEX_RMRX,16),TNSZ("vpinsrd",VEX_RMRX,16),INVALID, 1800 /* [24] */ INVALID, INVALID, INVALID, INVALID, 1801 /* [28] */ INVALID, INVALID, INVALID, INVALID, 1802 /* [2C] */ INVALID, INVALID, INVALID, INVALID, 1803 1804 /* [30] */ TSvo("kshiftr",VEX_MXI), TSvo("kshiftr",VEX_MXI), TSvo("kshiftl",VEX_MXI), TSvo("kshiftl",VEX_MXI), 1805 /* [34] */ INVALID, INVALID, INVALID, INVALID, 1806 /* [38] */ TNSZ("vinserti128",VEX_RMRX,16),TNSZ("vextracti128",VEX_RIM,16),INVALID, INVALID, 1807 /* [3C] */ INVALID, INVALID, INVALID, INVALID, 1808 1809 /* [40] */ TNSZ("vdpps",VEX_RMRX,16),TNSZ("vdppd",VEX_RMRX,16),TNSZ("vmpsadbw",VEX_RMRX,16),INVALID, 1810 /* [44] */ TNSZ("vpclmulqdq",VEX_RMRX,16),INVALID, TNSZ("vperm2i128",VEX_RMRX,16),INVALID, 1811 /* [48] */ INVALID, INVALID, TNSZ("vblendvps",VEX_RMRX,8), TNSZ("vblendvpd",VEX_RMRX,16), 1812 /* [4C] */ TNSZ("vpblendvb",VEX_RMRX,16),INVALID, INVALID, INVALID, 1813 1814 /* [50] */ INVALID, INVALID, INVALID, INVALID, 1815 /* [54] */ INVALID, INVALID, INVALID, INVALID, 1816 /* [58] */ INVALID, INVALID, INVALID, INVALID, 1817 /* [5C] */ INVALID, INVALID, INVALID, INVALID, 1818 1819 /* [60] */ TNSZ("vpcmpestrm",VEX_MXI,16),TNSZ("vpcmpestri",VEX_MXI,16),TNSZ("vpcmpistrm",VEX_MXI,16),TNSZ("vpcmpistri",VEX_MXI,16), 1820 /* [64] */ INVALID, INVALID, INVALID, INVALID, 1821 /* [68] */ INVALID, INVALID, INVALID, INVALID, 1822 /* [6C] */ INVALID, INVALID, INVALID, INVALID, 1823 1824 /* [70] */ INVALID, INVALID, INVALID, INVALID, 1825 /* [74] */ INVALID, INVALID, INVALID, INVALID, 1826 /* [78] */ INVALID, INVALID, INVALID, INVALID, 1827 /* [7C] */ INVALID, INVALID, INVALID, INVALID, 1828 1829 /* [80] */ INVALID, INVALID, INVALID, INVALID, 1830 /* [84] */ INVALID, INVALID, INVALID, INVALID, 1831 /* [88] */ INVALID, INVALID, INVALID, INVALID, 1832 /* [8C] */ INVALID, INVALID, INVALID, INVALID, 1833 1834 /* [90] */ INVALID, INVALID, INVALID, INVALID, 1835 /* [94] */ INVALID, INVALID, INVALID, INVALID, 1836 /* [98] */ INVALID, INVALID, INVALID, INVALID, 1837 /* [9C] */ INVALID, INVALID, INVALID, INVALID, 1838 1839 /* [A0] */ INVALID, INVALID, INVALID, INVALID, 1840 /* [A4] */ INVALID, INVALID, INVALID, INVALID, 1841 /* [A8] */ INVALID, INVALID, INVALID, INVALID, 1842 /* [AC] */ INVALID, INVALID, INVALID, INVALID, 1843 1844 /* [B0] */ INVALID, INVALID, INVALID, INVALID, 1845 /* [B4] */ INVALID, INVALID, INVALID, INVALID, 1846 /* [B8] */ INVALID, INVALID, INVALID, INVALID, 1847 /* [BC] */ INVALID, INVALID, INVALID, INVALID, 1848 1849 /* [C0] */ INVALID, INVALID, INVALID, INVALID, 1850 /* [C4] */ INVALID, INVALID, INVALID, INVALID, 1851 /* [C8] */ INVALID, INVALID, INVALID, INVALID, 1852 /* [CC] */ INVALID, INVALID, INVALID, INVALID, 1853 1854 /* [D0] */ INVALID, INVALID, INVALID, INVALID, 1855 /* [D4] */ INVALID, INVALID, INVALID, INVALID, 1856 /* [D8] */ INVALID, INVALID, INVALID, INVALID, 1857 /* [DC] */ INVALID, INVALID, INVALID, TNSZ("vaeskeygenassist",VEX_MXI,16), 1858 1859 /* [E0] */ INVALID, INVALID, INVALID, INVALID, 1860 /* [E4] */ INVALID, INVALID, INVALID, INVALID, 1861 /* [E8] */ INVALID, INVALID, INVALID, INVALID, 1862 /* [EC] */ INVALID, INVALID, INVALID, INVALID, 1863 1864 /* [F0] */ INVALID, INVALID, INVALID, INVALID, 1865 /* [F4] */ INVALID, INVALID, INVALID, INVALID, 1866 /* [F8] */ INVALID, INVALID, INVALID, INVALID, 1867 /* [FC] */ INVALID, INVALID, INVALID, INVALID, 1868 }; 1869 1870 /* 1871 * Decode table for 0x0F0D which uses the first byte of the mod_rm to 1872 * indicate a sub-code. 1873 */ 1874 const instable_t dis_op0F0D[8] = { 1875 /* [00] */ INVALID, TNS("prefetchw",PREF), TNS("prefetchwt1",PREF),INVALID, 1876 /* [04] */ INVALID, INVALID, INVALID, INVALID, 1877 }; 1878 1879 /* 1880 * Decode table for 0x0F opcodes 1881 */ 1882 1883 const instable_t dis_op0F[16][16] = { 1884 { 1885 /* [00] */ IND(dis_op0F00), IND(dis_op0F01), TNS("lar",MR), TNS("lsl",MR), 1886 /* [04] */ INVALID, TNS("syscall",NORM), TNS("clts",NORM), TNS("sysret",NORM), 1887 /* [08] */ TNS("invd",NORM), TNS("wbinvd",NORM), INVALID, TNS("ud2",NORM), 1888 /* [0C] */ INVALID, IND(dis_op0F0D), INVALID, INVALID, 1889 }, { 1890 /* [10] */ TNSZ("movups",XMMO,16), TNSZ("movups",XMMOS,16),TNSZ("movlps",XMMO,8), TNSZ("movlps",XMMOS,8), 1891 /* [14] */ TNSZ("unpcklps",XMMO,16),TNSZ("unpckhps",XMMO,16),TNSZ("movhps",XMMOM,8),TNSZ("movhps",XMMOMS,8), 1892 /* [18] */ IND(dis_op0F18), INVALID, INVALID, INVALID, 1893 /* [1C] */ INVALID, INVALID, INVALID, TS("nop",Mw), 1894 }, { 1895 /* [20] */ TSy("mov",SREG), TSy("mov",SREG), TSy("mov",SREG), TSy("mov",SREG), 1896 /* [24] */ TSx("mov",SREG), INVALID, TSx("mov",SREG), INVALID, 1897 /* [28] */ TNSZ("movaps",XMMO,16), TNSZ("movaps",XMMOS,16),TNSZ("cvtpi2ps",XMMOMX,8),TNSZ("movntps",XMMOS,16), 1898 /* [2C] */ TNSZ("cvttps2pi",XMMOXMM,8),TNSZ("cvtps2pi",XMMOXMM,8),TNSZ("ucomiss",XMMO,4),TNSZ("comiss",XMMO,4), 1899 }, { 1900 /* [30] */ TNS("wrmsr",NORM), TNS("rdtsc",NORM), TNS("rdmsr",NORM), TNS("rdpmc",NORM), 1901 /* [34] */ TNS("sysenter",NORM), TNS("sysexit",NORM), INVALID, INVALID, 1902 /* [38] */ INVALID, INVALID, INVALID, INVALID, 1903 /* [3C] */ INVALID, INVALID, INVALID, INVALID, 1904 }, { 1905 /* [40] */ TS("cmovx.o",MR), TS("cmovx.no",MR), TS("cmovx.b",MR), TS("cmovx.ae",MR), 1906 /* [44] */ TS("cmovx.e",MR), TS("cmovx.ne",MR), TS("cmovx.be",MR), TS("cmovx.a",MR), 1907 /* [48] */ TS("cmovx.s",MR), TS("cmovx.ns",MR), TS("cmovx.pe",MR), TS("cmovx.po",MR), 1908 /* [4C] */ TS("cmovx.l",MR), TS("cmovx.ge",MR), TS("cmovx.le",MR), TS("cmovx.g",MR), 1909 }, { 1910 /* [50] */ TNS("movmskps",XMMOX3), TNSZ("sqrtps",XMMO,16), TNSZ("rsqrtps",XMMO,16),TNSZ("rcpps",XMMO,16), 1911 /* [54] */ TNSZ("andps",XMMO,16), TNSZ("andnps",XMMO,16), TNSZ("orps",XMMO,16), TNSZ("xorps",XMMO,16), 1912 /* [58] */ TNSZ("addps",XMMO,16), TNSZ("mulps",XMMO,16), TNSZ("cvtps2pd",XMMO,8),TNSZ("cvtdq2ps",XMMO,16), 1913 /* [5C] */ TNSZ("subps",XMMO,16), TNSZ("minps",XMMO,16), TNSZ("divps",XMMO,16), TNSZ("maxps",XMMO,16), 1914 }, { 1915 /* [60] */ TNSZ("punpcklbw",MMO,4),TNSZ("punpcklwd",MMO,4),TNSZ("punpckldq",MMO,4),TNSZ("packsswb",MMO,8), 1916 /* [64] */ TNSZ("pcmpgtb",MMO,8), TNSZ("pcmpgtw",MMO,8), TNSZ("pcmpgtd",MMO,8), TNSZ("packuswb",MMO,8), 1917 /* [68] */ TNSZ("punpckhbw",MMO,8),TNSZ("punpckhwd",MMO,8),TNSZ("punpckhdq",MMO,8),TNSZ("packssdw",MMO,8), 1918 /* [6C] */ TNSZ("INVALID",MMO,0), TNSZ("INVALID",MMO,0), TNSZ("movd",MMO,4), TNSZ("movq",MMO,8), 1919 }, { 1920 /* [70] */ TNSZ("pshufw",MMOPM,8), TNS("psrXXX",MR), TNS("psrXXX",MR), TNS("psrXXX",MR), 1921 /* [74] */ TNSZ("pcmpeqb",MMO,8), TNSZ("pcmpeqw",MMO,8), TNSZ("pcmpeqd",MMO,8), TNS("emms",NORM), 1922 /* [78] */ TNSy("vmread",RM), TNSy("vmwrite",MR), INVALID, INVALID, 1923 /* [7C] */ INVALID, INVALID, TNSZ("movd",MMOS,4), TNSZ("movq",MMOS,8), 1924 }, { 1925 /* [80] */ TNS("jo",D), TNS("jno",D), TNS("jb",D), TNS("jae",D), 1926 /* [84] */ TNS("je",D), TNS("jne",D), TNS("jbe",D), TNS("ja",D), 1927 /* [88] */ TNS("js",D), TNS("jns",D), TNS("jp",D), TNS("jnp",D), 1928 /* [8C] */ TNS("jl",D), TNS("jge",D), TNS("jle",D), TNS("jg",D), 1929 }, { 1930 /* [90] */ TNS("seto",Mb), TNS("setno",Mb), TNS("setb",Mb), TNS("setae",Mb), 1931 /* [94] */ TNS("sete",Mb), TNS("setne",Mb), TNS("setbe",Mb), TNS("seta",Mb), 1932 /* [98] */ TNS("sets",Mb), TNS("setns",Mb), TNS("setp",Mb), TNS("setnp",Mb), 1933 /* [9C] */ TNS("setl",Mb), TNS("setge",Mb), TNS("setle",Mb), TNS("setg",Mb), 1934 }, { 1935 /* [A0] */ TSp("push",LSEG), TSp("pop",LSEG), TNS("cpuid",NORM), TS("bt",RMw), 1936 /* [A4] */ TS("shld",DSHIFT), TS("shld",DSHIFTcl), INVALID, INVALID, 1937 /* [A8] */ TSp("push",LSEG), TSp("pop",LSEG), TNS("rsm",NORM), TS("bts",RMw), 1938 /* [AC] */ TS("shrd",DSHIFT), TS("shrd",DSHIFTcl), IND(dis_op0FAE), TS("imul",MRw), 1939 }, { 1940 /* [B0] */ TNS("cmpxchgb",RMw), TS("cmpxchg",RMw), TS("lss",MR), TS("btr",RMw), 1941 /* [B4] */ TS("lfs",MR), TS("lgs",MR), TS("movzb",MOVZ), TNS("movzwl",MOVZ), 1942 /* [B8] */ TNS("INVALID",MRw), INVALID, IND(dis_op0FBA), TS("btc",RMw), 1943 /* [BC] */ TS("bsf",MRw), TS("bsr",MRw), TS("movsb",MOVZ), TNS("movswl",MOVZ), 1944 }, { 1945 /* [C0] */ TNS("xaddb",XADDB), TS("xadd",RMw), TNSZ("cmpps",XMMOPM,16),TNS("movnti",RM), 1946 /* [C4] */ TNSZ("pinsrw",MMOPRM,2),TNS("pextrw",MMO3P), TNSZ("shufps",XMMOPM,16),IND(dis_op0FC7), 1947 /* [C8] */ INVALID, INVALID, INVALID, INVALID, 1948 /* [CC] */ INVALID, INVALID, INVALID, INVALID, 1949 }, { 1950 /* [D0] */ INVALID, TNSZ("psrlw",MMO,8), TNSZ("psrld",MMO,8), TNSZ("psrlq",MMO,8), 1951 /* [D4] */ TNSZ("paddq",MMO,8), TNSZ("pmullw",MMO,8), TNSZ("INVALID",MMO,0), TNS("pmovmskb",MMOM3), 1952 /* [D8] */ TNSZ("psubusb",MMO,8), TNSZ("psubusw",MMO,8), TNSZ("pminub",MMO,8), TNSZ("pand",MMO,8), 1953 /* [DC] */ TNSZ("paddusb",MMO,8), TNSZ("paddusw",MMO,8), TNSZ("pmaxub",MMO,8), TNSZ("pandn",MMO,8), 1954 }, { 1955 /* [E0] */ TNSZ("pavgb",MMO,8), TNSZ("psraw",MMO,8), TNSZ("psrad",MMO,8), TNSZ("pavgw",MMO,8), 1956 /* [E4] */ TNSZ("pmulhuw",MMO,8), TNSZ("pmulhw",MMO,8), TNS("INVALID",XMMO), TNSZ("movntq",MMOMS,8), 1957 /* [E8] */ TNSZ("psubsb",MMO,8), TNSZ("psubsw",MMO,8), TNSZ("pminsw",MMO,8), TNSZ("por",MMO,8), 1958 /* [EC] */ TNSZ("paddsb",MMO,8), TNSZ("paddsw",MMO,8), TNSZ("pmaxsw",MMO,8), TNSZ("pxor",MMO,8), 1959 }, { 1960 /* [F0] */ INVALID, TNSZ("psllw",MMO,8), TNSZ("pslld",MMO,8), TNSZ("psllq",MMO,8), 1961 /* [F4] */ TNSZ("pmuludq",MMO,8), TNSZ("pmaddwd",MMO,8), TNSZ("psadbw",MMO,8), TNSZ("maskmovq",MMOIMPL,8), 1962 /* [F8] */ TNSZ("psubb",MMO,8), TNSZ("psubw",MMO,8), TNSZ("psubd",MMO,8), TNSZ("psubq",MMO,8), 1963 /* [FC] */ TNSZ("paddb",MMO,8), TNSZ("paddw",MMO,8), TNSZ("paddd",MMO,8), INVALID, 1964 } }; 1965 1966 const instable_t dis_opAVX0F[16][16] = { 1967 { 1968 /* [00] */ INVALID, INVALID, INVALID, INVALID, 1969 /* [04] */ INVALID, INVALID, INVALID, INVALID, 1970 /* [08] */ INVALID, INVALID, INVALID, INVALID, 1971 /* [0C] */ INVALID, INVALID, INVALID, INVALID, 1972 }, { 1973 /* [10] */ TNSZ("vmovups",VEX_MX,16), TNSZ("vmovups",VEX_RM,16),TNSZ("vmovlps",VEX_RMrX,8), TNSZ("vmovlps",VEX_RM,8), 1974 /* [14] */ TNSZ("vunpcklps",VEX_RMrX,16),TNSZ("vunpckhps",VEX_RMrX,16),TNSZ("vmovhps",VEX_RMrX,8),TNSZ("vmovhps",VEX_RM,8), 1975 /* [18] */ INVALID, INVALID, INVALID, INVALID, 1976 /* [1C] */ INVALID, INVALID, INVALID, INVALID, 1977 }, { 1978 /* [20] */ INVALID, INVALID, INVALID, INVALID, 1979 /* [24] */ INVALID, INVALID, INVALID, INVALID, 1980 /* [28] */ TNSZ("vmovaps",VEX_MX,16), TNSZ("vmovaps",VEX_RX,16),INVALID, TNSZ("vmovntps",VEX_RM,16), 1981 /* [2C] */ INVALID, INVALID, TNSZ("vucomiss",VEX_MX,4),TNSZ("vcomiss",VEX_MX,4), 1982 }, { 1983 /* [30] */ INVALID, INVALID, INVALID, INVALID, 1984 /* [34] */ INVALID, INVALID, INVALID, INVALID, 1985 /* [38] */ INVALID, INVALID, INVALID, INVALID, 1986 /* [3C] */ INVALID, INVALID, INVALID, INVALID, 1987 }, { 1988 /* [40] */ INVALID, TSvo("kand",VEX_RMX), TSvo("kandn",VEX_RMX), INVALID, 1989 /* [44] */ TSvo("knot",VEX_MX), TSvo("kor",VEX_RMX), TSvo("kxnor",VEX_RMX), TSvo("kxor",VEX_RMX), 1990 /* [48] */ INVALID, INVALID, TSvo("kadd",VEX_RMX), TSvo("kunpck",VEX_RMX), 1991 /* [4C] */ INVALID, INVALID, INVALID, INVALID, 1992 }, { 1993 /* [50] */ TNS("vmovmskps",VEX_MR), TNSZ("vsqrtps",VEX_MX,16), TNSZ("vrsqrtps",VEX_MX,16),TNSZ("vrcpps",VEX_MX,16), 1994 /* [54] */ TNSZ("vandps",VEX_RMrX,16), TNSZ("vandnps",VEX_RMrX,16), TNSZ("vorps",VEX_RMrX,16), TNSZ("vxorps",VEX_RMrX,16), 1995 /* [58] */ TNSZ("vaddps",VEX_RMrX,16), TNSZ("vmulps",VEX_RMrX,16), TNSZ("vcvtps2pd",VEX_MX,8),TNSZ("vcvtdq2ps",VEX_MX,16), 1996 /* [5C] */ TNSZ("vsubps",VEX_RMrX,16), TNSZ("vminps",VEX_RMrX,16), TNSZ("vdivps",VEX_RMrX,16), TNSZ("vmaxps",VEX_RMrX,16), 1997 }, { 1998 /* [60] */ INVALID, INVALID, INVALID, INVALID, 1999 /* [64] */ INVALID, INVALID, INVALID, INVALID, 2000 /* [68] */ INVALID, INVALID, INVALID, INVALID, 2001 /* [6C] */ INVALID, INVALID, INVALID, INVALID, 2002 }, { 2003 /* [70] */ INVALID, INVALID, INVALID, INVALID, 2004 /* [74] */ INVALID, INVALID, INVALID, TNS("vzeroupper", VEX_NONE), 2005 /* [78] */ INVALID, INVALID, INVALID, INVALID, 2006 /* [7C] */ INVALID, INVALID, INVALID, INVALID, 2007 }, { 2008 /* [80] */ INVALID, INVALID, INVALID, INVALID, 2009 /* [84] */ INVALID, INVALID, INVALID, INVALID, 2010 /* [88] */ INVALID, INVALID, INVALID, INVALID, 2011 /* [8C] */ INVALID, INVALID, INVALID, INVALID, 2012 }, { 2013 /* [90] */ TSvo("kmov",VEX_KRM), TSvo("kmov",VEX_KMR), TSvo("kmov",VEX_KRR), TSvo("kmov",VEX_MR), 2014 /* [94] */ INVALID, INVALID, INVALID, INVALID, 2015 /* [98] */ TSvo("kortest",VEX_MX), TSvo("ktest",VEX_MX), INVALID, INVALID, 2016 /* [9C] */ INVALID, INVALID, INVALID, INVALID, 2017 }, { 2018 /* [A0] */ INVALID, INVALID, INVALID, INVALID, 2019 /* [A4] */ INVALID, INVALID, INVALID, INVALID, 2020 /* [A8] */ INVALID, INVALID, INVALID, INVALID, 2021 /* [AC] */ INVALID, INVALID, TNSZ("vldmxcsr",VEX_MO,2), INVALID, 2022 }, { 2023 /* [B0] */ INVALID, INVALID, INVALID, INVALID, 2024 /* [B4] */ INVALID, INVALID, INVALID, INVALID, 2025 /* [B8] */ INVALID, INVALID, INVALID, INVALID, 2026 /* [BC] */ INVALID, INVALID, INVALID, INVALID, 2027 }, { 2028 /* [C0] */ INVALID, INVALID, TNSZ("vcmpps",VEX_RMRX,16),INVALID, 2029 /* [C4] */ INVALID, INVALID, TNSZ("vshufps",VEX_RMRX,16),INVALID, 2030 /* [C8] */ INVALID, INVALID, INVALID, INVALID, 2031 /* [CC] */ INVALID, INVALID, INVALID, INVALID, 2032 }, { 2033 /* [D0] */ INVALID, INVALID, INVALID, INVALID, 2034 /* [D4] */ INVALID, INVALID, INVALID, INVALID, 2035 /* [D8] */ INVALID, INVALID, INVALID, INVALID, 2036 /* [DC] */ INVALID, INVALID, INVALID, INVALID, 2037 }, { 2038 /* [E0] */ INVALID, INVALID, INVALID, INVALID, 2039 /* [E4] */ INVALID, INVALID, INVALID, INVALID, 2040 /* [E8] */ INVALID, INVALID, INVALID, INVALID, 2041 /* [EC] */ INVALID, INVALID, INVALID, INVALID, 2042 }, { 2043 /* [F0] */ INVALID, INVALID, TNSZvr("andn",VEX_RMrX,5),TNSZvr("bls",BLS,5), 2044 /* [F4] */ INVALID, TNSZvr("bzhi",VEX_VRMrX,5),INVALID, TNSZvr("bextr",VEX_VRMrX,5), 2045 /* [F8] */ INVALID, INVALID, INVALID, INVALID, 2046 /* [FC] */ INVALID, INVALID, INVALID, INVALID, 2047 } }; 2048 2049 /* 2050 * Decode table for 0x80 opcodes 2051 */ 2052 2053 const instable_t dis_op80[8] = { 2054 2055 /* [0] */ TNS("addb",IMlw), TNS("orb",IMw), TNS("adcb",IMlw), TNS("sbbb",IMlw), 2056 /* [4] */ TNS("andb",IMw), TNS("subb",IMlw), TNS("xorb",IMw), TNS("cmpb",IMlw), 2057 }; 2058 2059 2060 /* 2061 * Decode table for 0x81 opcodes. 2062 */ 2063 2064 const instable_t dis_op81[8] = { 2065 2066 /* [0] */ TS("add",IMlw), TS("or",IMw), TS("adc",IMlw), TS("sbb",IMlw), 2067 /* [4] */ TS("and",IMw), TS("sub",IMlw), TS("xor",IMw), TS("cmp",IMlw), 2068 }; 2069 2070 2071 /* 2072 * Decode table for 0x82 opcodes. 2073 */ 2074 2075 const instable_t dis_op82[8] = { 2076 2077 /* [0] */ TNSx("addb",IMlw), TNSx("orb",IMlw), TNSx("adcb",IMlw), TNSx("sbbb",IMlw), 2078 /* [4] */ TNSx("andb",IMlw), TNSx("subb",IMlw), TNSx("xorb",IMlw), TNSx("cmpb",IMlw), 2079 }; 2080 /* 2081 * Decode table for 0x83 opcodes. 2082 */ 2083 2084 const instable_t dis_op83[8] = { 2085 2086 /* [0] */ TS("add",IMlw), TS("or",IMlw), TS("adc",IMlw), TS("sbb",IMlw), 2087 /* [4] */ TS("and",IMlw), TS("sub",IMlw), TS("xor",IMlw), TS("cmp",IMlw), 2088 }; 2089 2090 /* 2091 * Decode table for 0xC0 opcodes. 2092 */ 2093 2094 const instable_t dis_opC0[8] = { 2095 2096 /* [0] */ TNS("rolb",MvI), TNS("rorb",MvI), TNS("rclb",MvI), TNS("rcrb",MvI), 2097 /* [4] */ TNS("shlb",MvI), TNS("shrb",MvI), INVALID, TNS("sarb",MvI), 2098 }; 2099 2100 /* 2101 * Decode table for 0xD0 opcodes. 2102 */ 2103 2104 const instable_t dis_opD0[8] = { 2105 2106 /* [0] */ TNS("rolb",Mv), TNS("rorb",Mv), TNS("rclb",Mv), TNS("rcrb",Mv), 2107 /* [4] */ TNS("shlb",Mv), TNS("shrb",Mv), TNS("salb",Mv), TNS("sarb",Mv), 2108 }; 2109 2110 /* 2111 * Decode table for 0xC1 opcodes. 2112 * 186 instruction set 2113 */ 2114 2115 const instable_t dis_opC1[8] = { 2116 2117 /* [0] */ TS("rol",MvI), TS("ror",MvI), TS("rcl",MvI), TS("rcr",MvI), 2118 /* [4] */ TS("shl",MvI), TS("shr",MvI), TS("sal",MvI), TS("sar",MvI), 2119 }; 2120 2121 /* 2122 * Decode table for 0xD1 opcodes. 2123 */ 2124 2125 const instable_t dis_opD1[8] = { 2126 2127 /* [0] */ TS("rol",Mv), TS("ror",Mv), TS("rcl",Mv), TS("rcr",Mv), 2128 /* [4] */ TS("shl",Mv), TS("shr",Mv), TS("sal",Mv), TS("sar",Mv), 2129 }; 2130 2131 2132 /* 2133 * Decode table for 0xD2 opcodes. 2134 */ 2135 2136 const instable_t dis_opD2[8] = { 2137 2138 /* [0] */ TNS("rolb",Mv), TNS("rorb",Mv), TNS("rclb",Mv), TNS("rcrb",Mv), 2139 /* [4] */ TNS("shlb",Mv), TNS("shrb",Mv), TNS("salb",Mv), TNS("sarb",Mv), 2140 }; 2141 /* 2142 * Decode table for 0xD3 opcodes. 2143 */ 2144 2145 const instable_t dis_opD3[8] = { 2146 2147 /* [0] */ TS("rol",Mv), TS("ror",Mv), TS("rcl",Mv), TS("rcr",Mv), 2148 /* [4] */ TS("shl",Mv), TS("shr",Mv), TS("salb",Mv), TS("sar",Mv), 2149 }; 2150 2151 2152 /* 2153 * Decode table for 0xF6 opcodes. 2154 */ 2155 2156 const instable_t dis_opF6[8] = { 2157 2158 /* [0] */ TNS("testb",IMw), TNS("testb",IMw), TNS("notb",Mw), TNS("negb",Mw), 2159 /* [4] */ TNS("mulb",MA), TNS("imulb",MA), TNS("divb",MA), TNS("idivb",MA), 2160 }; 2161 2162 2163 /* 2164 * Decode table for 0xF7 opcodes. 2165 */ 2166 2167 const instable_t dis_opF7[8] = { 2168 2169 /* [0] */ TS("test",IMw), TS("test",IMw), TS("not",Mw), TS("neg",Mw), 2170 /* [4] */ TS("mul",MA), TS("imul",MA), TS("div",MA), TS("idiv",MA), 2171 }; 2172 2173 2174 /* 2175 * Decode table for 0xFE opcodes. 2176 */ 2177 2178 const instable_t dis_opFE[8] = { 2179 2180 /* [0] */ TNS("incb",Mw), TNS("decb",Mw), INVALID, INVALID, 2181 /* [4] */ INVALID, INVALID, INVALID, INVALID, 2182 }; 2183 /* 2184 * Decode table for 0xFF opcodes. 2185 */ 2186 2187 const instable_t dis_opFF[8] = { 2188 2189 /* [0] */ TS("inc",Mw), TS("dec",Mw), TNSyp("call",INM), TNS("lcall",INM), 2190 /* [4] */ TNSy("jmp",INM), TNS("ljmp",INM), TSp("push",M), INVALID, 2191 }; 2192 2193 /* for 287 instructions, which are a mess to decode */ 2194 2195 const instable_t dis_opFP1n2[8][8] = { 2196 { 2197 /* bit pattern: 1101 1xxx MODxx xR/M */ 2198 /* [0,0] */ TNS("fadds",M), TNS("fmuls",M), TNS("fcoms",M), TNS("fcomps",M), 2199 /* [0,4] */ TNS("fsubs",M), TNS("fsubrs",M), TNS("fdivs",M), TNS("fdivrs",M), 2200 }, { 2201 /* [1,0] */ TNS("flds",M), INVALID, TNS("fsts",M), TNS("fstps",M), 2202 /* [1,4] */ TNSZ("fldenv",M,28), TNSZ("fldcw",M,2), TNSZ("fnstenv",M,28), TNSZ("fnstcw",M,2), 2203 }, { 2204 /* [2,0] */ TNS("fiaddl",M), TNS("fimull",M), TNS("ficoml",M), TNS("ficompl",M), 2205 /* [2,4] */ TNS("fisubl",M), TNS("fisubrl",M), TNS("fidivl",M), TNS("fidivrl",M), 2206 }, { 2207 /* [3,0] */ TNS("fildl",M), TNSZ("tisttpl",M,4), TNS("fistl",M), TNS("fistpl",M), 2208 /* [3,4] */ INVALID, TNSZ("fldt",M,10), INVALID, TNSZ("fstpt",M,10), 2209 }, { 2210 /* [4,0] */ TNSZ("faddl",M,8), TNSZ("fmull",M,8), TNSZ("fcoml",M,8), TNSZ("fcompl",M,8), 2211 /* [4,1] */ TNSZ("fsubl",M,8), TNSZ("fsubrl",M,8), TNSZ("fdivl",M,8), TNSZ("fdivrl",M,8), 2212 }, { 2213 /* [5,0] */ TNSZ("fldl",M,8), TNSZ("fisttpll",M,8), TNSZ("fstl",M,8), TNSZ("fstpl",M,8), 2214 /* [5,4] */ TNSZ("frstor",M,108), INVALID, TNSZ("fnsave",M,108), TNSZ("fnstsw",M,2), 2215 }, { 2216 /* [6,0] */ TNSZ("fiadd",M,2), TNSZ("fimul",M,2), TNSZ("ficom",M,2), TNSZ("ficomp",M,2), 2217 /* [6,4] */ TNSZ("fisub",M,2), TNSZ("fisubr",M,2), TNSZ("fidiv",M,2), TNSZ("fidivr",M,2), 2218 }, { 2219 /* [7,0] */ TNSZ("fild",M,2), TNSZ("fisttp",M,2), TNSZ("fist",M,2), TNSZ("fistp",M,2), 2220 /* [7,4] */ TNSZ("fbld",M,10), TNSZ("fildll",M,8), TNSZ("fbstp",M,10), TNSZ("fistpll",M,8), 2221 } }; 2222 2223 const instable_t dis_opFP3[8][8] = { 2224 { 2225 /* bit pattern: 1101 1xxx 11xx xREG */ 2226 /* [0,0] */ TNS("fadd",FF), TNS("fmul",FF), TNS("fcom",F), TNS("fcomp",F), 2227 /* [0,4] */ TNS("fsub",FF), TNS("fsubr",FF), TNS("fdiv",FF), TNS("fdivr",FF), 2228 }, { 2229 /* [1,0] */ TNS("fld",F), TNS("fxch",F), TNS("fnop",NORM), TNS("fstp",F), 2230 /* [1,4] */ INVALID, INVALID, INVALID, INVALID, 2231 }, { 2232 /* [2,0] */ INVALID, INVALID, INVALID, INVALID, 2233 /* [2,4] */ INVALID, TNS("fucompp",NORM), INVALID, INVALID, 2234 }, { 2235 /* [3,0] */ INVALID, INVALID, INVALID, INVALID, 2236 /* [3,4] */ INVALID, INVALID, INVALID, INVALID, 2237 }, { 2238 /* [4,0] */ TNS("fadd",FF), TNS("fmul",FF), TNS("fcom",F), TNS("fcomp",F), 2239 /* [4,4] */ TNS("fsub",FF), TNS("fsubr",FF), TNS("fdiv",FF), TNS("fdivr",FF), 2240 }, { 2241 /* [5,0] */ TNS("ffree",F), TNS("fxch",F), TNS("fst",F), TNS("fstp",F), 2242 /* [5,4] */ TNS("fucom",F), TNS("fucomp",F), INVALID, INVALID, 2243 }, { 2244 /* [6,0] */ TNS("faddp",FF), TNS("fmulp",FF), TNS("fcomp",F), TNS("fcompp",NORM), 2245 /* [6,4] */ TNS("fsubp",FF), TNS("fsubrp",FF), TNS("fdivp",FF), TNS("fdivrp",FF), 2246 }, { 2247 /* [7,0] */ TNS("ffreep",F), TNS("fxch",F), TNS("fstp",F), TNS("fstp",F), 2248 /* [7,4] */ TNS("fnstsw",M), TNS("fucomip",FFC), TNS("fcomip",FFC), INVALID, 2249 } }; 2250 2251 const instable_t dis_opFP4[4][8] = { 2252 { 2253 /* bit pattern: 1101 1001 111x xxxx */ 2254 /* [0,0] */ TNS("fchs",NORM), TNS("fabs",NORM), INVALID, INVALID, 2255 /* [0,4] */ TNS("ftst",NORM), TNS("fxam",NORM), TNS("ftstp",NORM), INVALID, 2256 }, { 2257 /* [1,0] */ TNS("fld1",NORM), TNS("fldl2t",NORM), TNS("fldl2e",NORM), TNS("fldpi",NORM), 2258 /* [1,4] */ TNS("fldlg2",NORM), TNS("fldln2",NORM), TNS("fldz",NORM), INVALID, 2259 }, { 2260 /* [2,0] */ TNS("f2xm1",NORM), TNS("fyl2x",NORM), TNS("fptan",NORM), TNS("fpatan",NORM), 2261 /* [2,4] */ TNS("fxtract",NORM), TNS("fprem1",NORM), TNS("fdecstp",NORM), TNS("fincstp",NORM), 2262 }, { 2263 /* [3,0] */ TNS("fprem",NORM), TNS("fyl2xp1",NORM), TNS("fsqrt",NORM), TNS("fsincos",NORM), 2264 /* [3,4] */ TNS("frndint",NORM), TNS("fscale",NORM), TNS("fsin",NORM), TNS("fcos",NORM), 2265 } }; 2266 2267 const instable_t dis_opFP5[8] = { 2268 /* bit pattern: 1101 1011 111x xxxx */ 2269 /* [0] */ TNS("feni",NORM), TNS("fdisi",NORM), TNS("fnclex",NORM), TNS("fninit",NORM), 2270 /* [4] */ TNS("fsetpm",NORM), TNS("frstpm",NORM), INVALID, INVALID, 2271 }; 2272 2273 const instable_t dis_opFP6[8] = { 2274 /* bit pattern: 1101 1011 11yy yxxx */ 2275 /* [00] */ TNS("fcmov.nb",FF), TNS("fcmov.ne",FF), TNS("fcmov.nbe",FF), TNS("fcmov.nu",FF), 2276 /* [04] */ INVALID, TNS("fucomi",F), TNS("fcomi",F), INVALID, 2277 }; 2278 2279 const instable_t dis_opFP7[8] = { 2280 /* bit pattern: 1101 1010 11yy yxxx */ 2281 /* [00] */ TNS("fcmov.b",FF), TNS("fcmov.e",FF), TNS("fcmov.be",FF), TNS("fcmov.u",FF), 2282 /* [04] */ INVALID, INVALID, INVALID, INVALID, 2283 }; 2284 2285 /* 2286 * Main decode table for the op codes. The first two nibbles 2287 * will be used as an index into the table. If there is a 2288 * a need to further decode an instruction, the array to be 2289 * referenced is indicated with the other two entries being 2290 * empty. 2291 */ 2292 2293 const instable_t dis_distable[16][16] = { 2294 { 2295 /* [0,0] */ TNS("addb",RMw), TS("add",RMw), TNS("addb",MRw), TS("add",MRw), 2296 /* [0,4] */ TNS("addb",IA), TS("add",IA), TSx("push",SEG), TSx("pop",SEG), 2297 /* [0,8] */ TNS("orb",RMw), TS("or",RMw), TNS("orb",MRw), TS("or",MRw), 2298 /* [0,C] */ TNS("orb",IA), TS("or",IA), TSx("push",SEG), IND(dis_op0F), 2299 }, { 2300 /* [1,0] */ TNS("adcb",RMw), TS("adc",RMw), TNS("adcb",MRw), TS("adc",MRw), 2301 /* [1,4] */ TNS("adcb",IA), TS("adc",IA), TSx("push",SEG), TSx("pop",SEG), 2302 /* [1,8] */ TNS("sbbb",RMw), TS("sbb",RMw), TNS("sbbb",MRw), TS("sbb",MRw), 2303 /* [1,C] */ TNS("sbbb",IA), TS("sbb",IA), TSx("push",SEG), TSx("pop",SEG), 2304 }, { 2305 /* [2,0] */ TNS("andb",RMw), TS("and",RMw), TNS("andb",MRw), TS("and",MRw), 2306 /* [2,4] */ TNS("andb",IA), TS("and",IA), TNSx("%es:",OVERRIDE), TNSx("daa",NORM), 2307 /* [2,8] */ TNS("subb",RMw), TS("sub",RMw), TNS("subb",MRw), TS("sub",MRw), 2308 /* [2,C] */ TNS("subb",IA), TS("sub",IA), TNS("%cs:",OVERRIDE), TNSx("das",NORM), 2309 }, { 2310 /* [3,0] */ TNS("xorb",RMw), TS("xor",RMw), TNS("xorb",MRw), TS("xor",MRw), 2311 /* [3,4] */ TNS("xorb",IA), TS("xor",IA), TNSx("%ss:",OVERRIDE), TNSx("aaa",NORM), 2312 /* [3,8] */ TNS("cmpb",RMw), TS("cmp",RMw), TNS("cmpb",MRw), TS("cmp",MRw), 2313 /* [3,C] */ TNS("cmpb",IA), TS("cmp",IA), TNSx("%ds:",OVERRIDE), TNSx("aas",NORM), 2314 }, { 2315 /* [4,0] */ TSx("inc",R), TSx("inc",R), TSx("inc",R), TSx("inc",R), 2316 /* [4,4] */ TSx("inc",R), TSx("inc",R), TSx("inc",R), TSx("inc",R), 2317 /* [4,8] */ TSx("dec",R), TSx("dec",R), TSx("dec",R), TSx("dec",R), 2318 /* [4,C] */ TSx("dec",R), TSx("dec",R), TSx("dec",R), TSx("dec",R), 2319 }, { 2320 /* [5,0] */ TSp("push",R), TSp("push",R), TSp("push",R), TSp("push",R), 2321 /* [5,4] */ TSp("push",R), TSp("push",R), TSp("push",R), TSp("push",R), 2322 /* [5,8] */ TSp("pop",R), TSp("pop",R), TSp("pop",R), TSp("pop",R), 2323 /* [5,C] */ TSp("pop",R), TSp("pop",R), TSp("pop",R), TSp("pop",R), 2324 }, { 2325 /* [6,0] */ TSZx("pusha",IMPLMEM,28),TSZx("popa",IMPLMEM,28), TSx("bound",RM), TNS("arpl",RMw), 2326 /* [6,4] */ TNS("%fs:",OVERRIDE), TNS("%gs:",OVERRIDE), TNS("data16",DM), TNS("addr16",AM), 2327 /* [6,8] */ TSp("push",I), TS("imul",IMUL), TSp("push",Ib), TS("imul",IMUL), 2328 /* [6,C] */ TNSZ("insb",IMPLMEM,1), TSZ("ins",IMPLMEM,4), TNSZ("outsb",IMPLMEM,1),TSZ("outs",IMPLMEM,4), 2329 }, { 2330 /* [7,0] */ TNSy("jo",BD), TNSy("jno",BD), TNSy("jb",BD), TNSy("jae",BD), 2331 /* [7,4] */ TNSy("je",BD), TNSy("jne",BD), TNSy("jbe",BD), TNSy("ja",BD), 2332 /* [7,8] */ TNSy("js",BD), TNSy("jns",BD), TNSy("jp",BD), TNSy("jnp",BD), 2333 /* [7,C] */ TNSy("jl",BD), TNSy("jge",BD), TNSy("jle",BD), TNSy("jg",BD), 2334 }, { 2335 /* [8,0] */ IND(dis_op80), IND(dis_op81), INDx(dis_op82), IND(dis_op83), 2336 /* [8,4] */ TNS("testb",RMw), TS("test",RMw), TNS("xchgb",RMw), TS("xchg",RMw), 2337 /* [8,8] */ TNS("movb",RMw), TS("mov",RMw), TNS("movb",MRw), TS("mov",MRw), 2338 /* [8,C] */ TNS("movw",SM), TS("lea",MR), TNS("movw",MS), TSp("pop",M), 2339 }, { 2340 /* [9,0] */ TNS("nop",NORM), TS("xchg",RA), TS("xchg",RA), TS("xchg",RA), 2341 /* [9,4] */ TS("xchg",RA), TS("xchg",RA), TS("xchg",RA), TS("xchg",RA), 2342 /* [9,8] */ TNS("cXtX",CBW), TNS("cXtX",CWD), TNSx("lcall",SO), TNS("fwait",NORM), 2343 /* [9,C] */ TSZy("pushf",IMPLMEM,4),TSZy("popf",IMPLMEM,4), TNS("sahf",NORM), TNS("lahf",NORM), 2344 }, { 2345 /* [A,0] */ TNS("movb",OA), TS("mov",OA), TNS("movb",AO), TS("mov",AO), 2346 /* [A,4] */ TNSZ("movsb",SD,1), TS("movs",SD), TNSZ("cmpsb",SD,1), TS("cmps",SD), 2347 /* [A,8] */ TNS("testb",IA), TS("test",IA), TNS("stosb",AD), TS("stos",AD), 2348 /* [A,C] */ TNS("lodsb",SA), TS("lods",SA), TNS("scasb",AD), TS("scas",AD), 2349 }, { 2350 /* [B,0] */ TNS("movb",IR), TNS("movb",IR), TNS("movb",IR), TNS("movb",IR), 2351 /* [B,4] */ TNS("movb",IR), TNS("movb",IR), TNS("movb",IR), TNS("movb",IR), 2352 /* [B,8] */ TS("mov",IR), TS("mov",IR), TS("mov",IR), TS("mov",IR), 2353 /* [B,C] */ TS("mov",IR), TS("mov",IR), TS("mov",IR), TS("mov",IR), 2354 }, { 2355 /* [C,0] */ IND(dis_opC0), IND(dis_opC1), TNSyp("ret",RET), TNSyp("ret",NORM), 2356 /* [C,4] */ TNSx("les",MR), TNSx("lds",MR), TNS("movb",IMw), TS("mov",IMw), 2357 /* [C,8] */ TNSyp("enter",ENTER), TNSyp("leave",NORM), TNS("lret",RET), TNS("lret",NORM), 2358 /* [C,C] */ TNS("int",INT3), TNS("int",INTx), TNSx("into",NORM), TNS("iret",NORM), 2359 }, { 2360 /* [D,0] */ IND(dis_opD0), IND(dis_opD1), IND(dis_opD2), IND(dis_opD3), 2361 /* [D,4] */ TNSx("aam",U), TNSx("aad",U), TNSx("falc",NORM), TNSZ("xlat",IMPLMEM,1), 2362 2363 /* 287 instructions. Note that although the indirect field */ 2364 /* indicates opFP1n2 for further decoding, this is not necessarily */ 2365 /* the case since the opFP arrays are not partitioned according to key1 */ 2366 /* and key2. opFP1n2 is given only to indicate that we haven't */ 2367 /* finished decoding the instruction. */ 2368 /* [D,8] */ IND(dis_opFP1n2), IND(dis_opFP1n2), IND(dis_opFP1n2), IND(dis_opFP1n2), 2369 /* [D,C] */ IND(dis_opFP1n2), IND(dis_opFP1n2), IND(dis_opFP1n2), IND(dis_opFP1n2), 2370 }, { 2371 /* [E,0] */ TNSy("loopnz",BD), TNSy("loopz",BD), TNSy("loop",BD), TNSy("jcxz",BD), 2372 /* [E,4] */ TNS("inb",P), TS("in",P), TNS("outb",P), TS("out",P), 2373 /* [E,8] */ TNSyp("call",D), TNSy("jmp",D), TNSx("ljmp",SO), TNSy("jmp",BD), 2374 /* [E,C] */ TNS("inb",V), TS("in",V), TNS("outb",V), TS("out",V), 2375 }, { 2376 /* [F,0] */ TNS("lock",LOCK), TNS("icebp", NORM), TNS("repnz",PREFIX), TNS("repz",PREFIX), 2377 /* [F,4] */ TNS("hlt",NORM), TNS("cmc",NORM), IND(dis_opF6), IND(dis_opF7), 2378 /* [F,8] */ TNS("clc",NORM), TNS("stc",NORM), TNS("cli",NORM), TNS("sti",NORM), 2379 /* [F,C] */ TNS("cld",NORM), TNS("std",NORM), IND(dis_opFE), IND(dis_opFF), 2380 } }; 2381 2382 /* END CSTYLED */ 2383 2384 /* 2385 * common functions to decode and disassemble an x86 or amd64 instruction 2386 */ 2387 2388 /* 2389 * These are the individual fields of a REX prefix. Note that a REX 2390 * prefix with none of these set is still needed to: 2391 * - use the MOVSXD (sign extend 32 to 64 bits) instruction 2392 * - access the %sil, %dil, %bpl, %spl registers 2393 */ 2394 #define REX_W 0x08 /* 64 bit operand size when set */ 2395 #define REX_R 0x04 /* high order bit extension of ModRM reg field */ 2396 #define REX_X 0x02 /* high order bit extension of SIB index field */ 2397 #define REX_B 0x01 /* extends ModRM r_m, SIB base, or opcode reg */ 2398 2399 /* 2400 * These are the individual fields of a VEX/EVEX prefix. 2401 */ 2402 #define VEX_R 0x08 /* REX.R in 1's complement form */ 2403 #define VEX_X 0x04 /* REX.X in 1's complement form */ 2404 #define VEX_B 0x02 /* REX.B in 1's complement form */ 2405 2406 /* Additional EVEX prefix definitions */ 2407 #define EVEX_R 0x01 /* REX.R' in 1's complement form */ 2408 #define EVEX_OPREG_MASK 0x7 /* bit mask for selecting opmask register number */ 2409 #define EVEX_ZERO_MASK 0x80 /* bit mask for selecting zeroing */ 2410 2411 /* Vector Length, 0: scalar or 128-bit vector, 1: 256-bit vector */ 2412 #define VEX_L 0x04 2413 /* Vector Length, 0: scalar or 128-bit vector, 1: 256-bit vector, 2: 512-bit */ 2414 #define EVEX_L 0x06 /* bit mask for EVEX.L'L vector length/RC */ 2415 #define VEX_W 0x08 /* opcode specific, use like REX.W */ 2416 #define VEX_m 0x1F /* VEX m-mmmm field */ 2417 #define EVEX_m 0x3 /* EVEX mm field */ 2418 #define VEX_v 0x78 /* VEX/EVEX register specifier */ 2419 #define VEX_p 0x03 /* VEX pp field, opcode extension */ 2420 2421 /* VEX m-mmmm field, only used by three bytes prefix */ 2422 #define VEX_m_0F 0x01 /* implied 0F leading opcode byte */ 2423 #define VEX_m_0F38 0x02 /* implied 0F 38 leading opcode byte */ 2424 #define VEX_m_0F3A 0x03 /* implied 0F 3A leading opcode byte */ 2425 2426 /* VEX pp field, providing equivalent functionality of a SIMD prefix */ 2427 #define VEX_p_66 0x01 2428 #define VEX_p_F3 0x02 2429 #define VEX_p_F2 0x03 2430 2431 /* 2432 * Even in 64 bit mode, usually only 4 byte immediate operands are supported. 2433 */ 2434 static int isize[] = {1, 2, 4, 4}; 2435 static int isize64[] = {1, 2, 4, 8}; 2436 2437 /* 2438 * Just a bunch of useful macros. 2439 */ 2440 #define WBIT(x) (x & 0x1) /* to get w bit */ 2441 #define REGNO(x) (x & 0x7) /* to get 3 bit register */ 2442 #define VBIT(x) ((x)>>1 & 0x1) /* to get 'v' bit */ 2443 #define OPSIZE(osize, wbit) ((wbit) ? isize[osize] : 1) 2444 #define OPSIZE64(osize, wbit) ((wbit) ? isize64[osize] : 1) 2445 2446 #define REG_ONLY 3 /* mode to indicate a register operand (not memory) */ 2447 2448 #define BYTE_OPND 0 /* w-bit value indicating byte register */ 2449 #define LONG_OPND 1 /* w-bit value indicating opnd_size register */ 2450 #define MM_OPND 2 /* "value" used to indicate a mmx reg */ 2451 #define XMM_OPND 3 /* "value" used to indicate a xmm reg */ 2452 #define SEG_OPND 4 /* "value" used to indicate a segment reg */ 2453 #define CONTROL_OPND 5 /* "value" used to indicate a control reg */ 2454 #define DEBUG_OPND 6 /* "value" used to indicate a debug reg */ 2455 #define TEST_OPND 7 /* "value" used to indicate a test reg */ 2456 #define WORD_OPND 8 /* w-bit value indicating word size reg */ 2457 #define YMM_OPND 9 /* "value" used to indicate a ymm reg */ 2458 #define KOPMASK_OPND 10 /* "value" used to indicate an opmask reg */ 2459 #define ZMM_OPND 11 /* "value" used to indicate a zmm reg */ 2460 2461 /* 2462 * The AVX2 gather instructions are a bit of a mess. While there's a pattern, 2463 * there's not really a consistent scheme that we can use to know what the mode 2464 * is supposed to be for a given type. Various instructions, like VPGATHERDD, 2465 * always match the value of VEX_L. Other instructions like VPGATHERDQ, have 2466 * some registers match VEX_L, but the VSIB is always XMM. 2467 * 2468 * The simplest way to deal with this is to just define a table based on the 2469 * instruction opcodes, which are 0x90-0x93, so we subtract 0x90 to index into 2470 * them. 2471 * 2472 * We further have to subdivide this based on the value of VEX_W and the value 2473 * of VEX_L. The array is constructed to be indexed as: 2474 * [opcode - 0x90][VEX_W][VEX_L]. 2475 */ 2476 /* w = 0, 0x90 */ 2477 typedef struct dis_gather_regs { 2478 uint_t dgr_arg0; /* src reg */ 2479 uint_t dgr_arg1; /* vsib reg */ 2480 uint_t dgr_arg2; /* dst reg */ 2481 char *dgr_suffix; /* suffix to append */ 2482 } dis_gather_regs_t; 2483 2484 static dis_gather_regs_t dis_vgather[4][2][2] = { 2485 { 2486 /* op 0x90, W.0 */ 2487 { 2488 { XMM_OPND, XMM_OPND, XMM_OPND, "d" }, 2489 { YMM_OPND, YMM_OPND, YMM_OPND, "d" } 2490 }, 2491 /* op 0x90, W.1 */ 2492 { 2493 { XMM_OPND, XMM_OPND, XMM_OPND, "q" }, 2494 { YMM_OPND, XMM_OPND, YMM_OPND, "q" } 2495 } 2496 }, 2497 { 2498 /* op 0x91, W.0 */ 2499 { 2500 { XMM_OPND, XMM_OPND, XMM_OPND, "d" }, 2501 { XMM_OPND, YMM_OPND, XMM_OPND, "d" }, 2502 }, 2503 /* op 0x91, W.1 */ 2504 { 2505 { XMM_OPND, XMM_OPND, XMM_OPND, "q" }, 2506 { YMM_OPND, YMM_OPND, YMM_OPND, "q" }, 2507 } 2508 }, 2509 { 2510 /* op 0x92, W.0 */ 2511 { 2512 { XMM_OPND, XMM_OPND, XMM_OPND, "s" }, 2513 { YMM_OPND, YMM_OPND, YMM_OPND, "s" } 2514 }, 2515 /* op 0x92, W.1 */ 2516 { 2517 { XMM_OPND, XMM_OPND, XMM_OPND, "d" }, 2518 { YMM_OPND, XMM_OPND, YMM_OPND, "d" } 2519 } 2520 }, 2521 { 2522 /* op 0x93, W.0 */ 2523 { 2524 { XMM_OPND, XMM_OPND, XMM_OPND, "s" }, 2525 { XMM_OPND, YMM_OPND, XMM_OPND, "s" } 2526 }, 2527 /* op 0x93, W.1 */ 2528 { 2529 { XMM_OPND, XMM_OPND, XMM_OPND, "d" }, 2530 { YMM_OPND, YMM_OPND, YMM_OPND, "d" } 2531 } 2532 } 2533 }; 2534 2535 /* 2536 * Get the next byte and separate the op code into the high and low nibbles. 2537 */ 2538 static int 2539 dtrace_get_opcode(dis86_t *x, uint_t *high, uint_t *low) 2540 { 2541 int byte; 2542 2543 /* 2544 * x86 instructions have a maximum length of 15 bytes. Bail out if 2545 * we try to read more. 2546 */ 2547 if (x->d86_len >= 15) 2548 return (x->d86_error = 1); 2549 2550 if (x->d86_error) 2551 return (1); 2552 byte = x->d86_get_byte(x->d86_data); 2553 if (byte < 0) 2554 return (x->d86_error = 1); 2555 x->d86_bytes[x->d86_len++] = byte; 2556 *low = byte & 0xf; /* ----xxxx low 4 bits */ 2557 *high = byte >> 4 & 0xf; /* xxxx---- bits 7 to 4 */ 2558 return (0); 2559 } 2560 2561 /* 2562 * Get and decode an SIB (scaled index base) byte 2563 */ 2564 static void 2565 dtrace_get_SIB(dis86_t *x, uint_t *ss, uint_t *index, uint_t *base) 2566 { 2567 int byte; 2568 2569 if (x->d86_error) 2570 return; 2571 2572 byte = x->d86_get_byte(x->d86_data); 2573 if (byte < 0) { 2574 x->d86_error = 1; 2575 return; 2576 } 2577 x->d86_bytes[x->d86_len++] = byte; 2578 2579 *base = byte & 0x7; 2580 *index = (byte >> 3) & 0x7; 2581 *ss = (byte >> 6) & 0x3; 2582 } 2583 2584 /* 2585 * Get the byte following the op code and separate it into the 2586 * mode, register, and r/m fields. 2587 */ 2588 static void 2589 dtrace_get_modrm(dis86_t *x, uint_t *mode, uint_t *reg, uint_t *r_m) 2590 { 2591 if (x->d86_got_modrm == 0) { 2592 if (x->d86_rmindex == -1) 2593 x->d86_rmindex = x->d86_len; 2594 dtrace_get_SIB(x, mode, reg, r_m); 2595 x->d86_got_modrm = 1; 2596 } 2597 } 2598 2599 /* 2600 * Adjust register selection based on any REX prefix bits present. 2601 */ 2602 /*ARGSUSED*/ 2603 static void 2604 dtrace_rex_adjust(uint_t rex_prefix, uint_t mode, uint_t *reg, uint_t *r_m) 2605 { 2606 if (reg != NULL && r_m == NULL) { 2607 if (rex_prefix & REX_B) 2608 *reg += 8; 2609 } else { 2610 if (reg != NULL && (REX_R & rex_prefix) != 0) 2611 *reg += 8; 2612 if (r_m != NULL && (REX_B & rex_prefix) != 0) 2613 *r_m += 8; 2614 } 2615 } 2616 2617 /* 2618 * Adjust register selection based on any VEX prefix bits present. 2619 * Notes: VEX.R, VEX.X and VEX.B use the inverted form compared with REX prefix 2620 */ 2621 /*ARGSUSED*/ 2622 static void 2623 dtrace_vex_adjust(uint_t vex_byte1, uint_t mode, uint_t *reg, uint_t *r_m) 2624 { 2625 if (reg != NULL && r_m == NULL) { 2626 if (!(vex_byte1 & VEX_B)) 2627 *reg += 8; 2628 } else { 2629 if (reg != NULL && ((VEX_R & vex_byte1) == 0)) 2630 *reg += 8; 2631 if (r_m != NULL && ((VEX_B & vex_byte1) == 0)) 2632 *r_m += 8; 2633 } 2634 } 2635 2636 /* 2637 * Adjust the instruction mnemonic with the appropriate suffix. 2638 */ 2639 /* ARGSUSED */ 2640 static void 2641 dtrace_evex_mnem_adjust(dis86_t *x, instable_t *dp, uint_t vex_W, 2642 uint_t evex_byte2) 2643 { 2644 #ifdef DIS_TEXT 2645 if (dp == &dis_opAVX62[0x7f] || /* vmovdq */ 2646 dp == &dis_opAVX62[0x6f]) { 2647 /* Aligned or Unaligned? */ 2648 if ((evex_byte2 & 0x3) == 0x01) { 2649 (void) strlcat(x->d86_mnem, "a", OPLEN); 2650 (void) strlcat(x->d86_mnem, vex_W != 0 ? "64" : "32", 2651 OPLEN); 2652 } else { 2653 (void) strlcat(x->d86_mnem, "u", OPLEN); 2654 switch (evex_byte2 & 0x81) { 2655 case 0x0: 2656 (void) strlcat(x->d86_mnem, "32", OPLEN); 2657 break; 2658 case 0x1: 2659 (void) strlcat(x->d86_mnem, "8", OPLEN); 2660 break; 2661 case 0x80: 2662 (void) strlcat(x->d86_mnem, "64", OPLEN); 2663 break; 2664 case 0x81: 2665 (void) strlcat(x->d86_mnem, "16", OPLEN); 2666 break; 2667 } 2668 } 2669 2670 } else { 2671 (void) strlcat(x->d86_mnem, vex_W != 0 ? "d" : "s", OPLEN); 2672 } 2673 #endif 2674 } 2675 2676 /* 2677 * The following three functions adjust the register selection based on any 2678 * EVEX prefix bits present. See Intel 64 and IA-32 Architectures Software 2679 * Developer’s Manual Volume 2 (IASDv2), section 2.6.1 Table 2-30 and 2680 * section 2.6.2 Table 2-31. 2681 */ 2682 static void 2683 dtrace_evex_adjust_reg(uint_t evex_byte1, uint_t *reg) 2684 { 2685 if (reg != NULL) { 2686 if ((VEX_R & evex_byte1) == 0) { 2687 *reg += 8; 2688 } 2689 if ((EVEX_R & evex_byte1) == 0) { 2690 *reg += 16; 2691 } 2692 } 2693 } 2694 2695 static void 2696 dtrace_evex_adjust_rm(uint_t evex_byte1, uint_t *r_m) 2697 { 2698 if (r_m != NULL) { 2699 if ((VEX_B & evex_byte1) == 0) { 2700 *r_m += 8; 2701 } 2702 if ((VEX_X & evex_byte1) == 0) { 2703 *r_m += 16; 2704 } 2705 } 2706 } 2707 2708 /* 2709 * Use evex_L to set wbit. See IASDv2 Section 2.6.10 and Table 2-36. 2710 */ 2711 static void 2712 dtrace_evex_adjust_reg_name(uint_t evex_L, uint_t *wbitp) 2713 { 2714 switch (evex_L) { 2715 case 0x0: 2716 *wbitp = XMM_OPND; 2717 break; 2718 case 0x1: 2719 *wbitp = YMM_OPND; 2720 break; 2721 case 0x2: 2722 *wbitp = ZMM_OPND; 2723 break; 2724 } 2725 } 2726 2727 /* 2728 * Adjust operand value for disp8*N immediate. See IASDv2 Section 2.6.5. 2729 * This currently only handles a subset of the possibilities. 2730 */ 2731 static void 2732 dtrace_evex_adjust_disp8_n(dis86_t *x, int opindex, uint_t L, uint_t modrm) 2733 { 2734 d86opnd_t *opnd = &x->d86_opnd[opindex]; 2735 2736 if (x->d86_error) 2737 return; 2738 2739 /* Check disp8 bit in the ModR/M byte */ 2740 if ((modrm & 0x80) == 0x80) 2741 return; 2742 2743 /* use evex_L to adjust the value */ 2744 switch (L) { 2745 case 0x0: 2746 opnd->d86_value *= 16; 2747 break; 2748 case 0x1: 2749 opnd->d86_value *= 32; 2750 break; 2751 case 0x2: 2752 opnd->d86_value *= 64; 2753 break; 2754 } 2755 } 2756 2757 /* 2758 * Adjust target for opmask and zeroing. See IASDv2 Section 2.6.1 Table 2-30. 2759 */ 2760 /* ARGSUSED */ 2761 static void 2762 dtrace_evex_adjust_z_opmask(dis86_t *x, uint_t evex_byte3) 2763 { 2764 #ifdef DIS_TEXT 2765 char *opnd = x->d86_opnd[1].d86_opnd; 2766 int opmask_reg = evex_byte3 & EVEX_OPREG_MASK; 2767 #endif 2768 if (x->d86_error) 2769 return; 2770 2771 #ifdef DIS_TEXT 2772 if (opmask_reg != 0) { 2773 /* Append the opmask register to operand 1 */ 2774 (void) strlcat(opnd, "{", OPLEN); 2775 (void) strlcat(opnd, dis_KOPMASKREG[opmask_reg], OPLEN); 2776 (void) strlcat(opnd, "}", OPLEN); 2777 } 2778 if ((evex_byte3 & EVEX_ZERO_MASK) != 0) { 2779 /* Append the 'zeroing' modifier to operand 1 */ 2780 (void) strlcat(opnd, "{z}", OPLEN); 2781 } 2782 #endif /* DIS_TEXT */ 2783 } 2784 2785 /* 2786 * Get an immediate operand of the given size, with sign extension. 2787 */ 2788 static void 2789 dtrace_imm_opnd(dis86_t *x, int wbit, int size, int opindex) 2790 { 2791 int i; 2792 int byte; 2793 int valsize; 2794 2795 if (x->d86_numopnds < opindex + 1) 2796 x->d86_numopnds = opindex + 1; 2797 2798 switch (wbit) { 2799 case BYTE_OPND: 2800 valsize = 1; 2801 break; 2802 case LONG_OPND: 2803 if (x->d86_opnd_size == SIZE16) 2804 valsize = 2; 2805 else if (x->d86_opnd_size == SIZE32) 2806 valsize = 4; 2807 else 2808 valsize = 8; 2809 break; 2810 case MM_OPND: 2811 case XMM_OPND: 2812 case YMM_OPND: 2813 case ZMM_OPND: 2814 case SEG_OPND: 2815 case CONTROL_OPND: 2816 case DEBUG_OPND: 2817 case TEST_OPND: 2818 valsize = size; 2819 break; 2820 case WORD_OPND: 2821 valsize = 2; 2822 break; 2823 } 2824 if (valsize < size) 2825 valsize = size; 2826 2827 if (x->d86_error) 2828 return; 2829 x->d86_opnd[opindex].d86_value = 0; 2830 for (i = 0; i < size; ++i) { 2831 byte = x->d86_get_byte(x->d86_data); 2832 if (byte < 0) { 2833 x->d86_error = 1; 2834 return; 2835 } 2836 x->d86_bytes[x->d86_len++] = byte; 2837 x->d86_opnd[opindex].d86_value |= (uint64_t)byte << (i * 8); 2838 } 2839 /* Do sign extension */ 2840 if (x->d86_bytes[x->d86_len - 1] & 0x80) { 2841 for (; i < sizeof (uint64_t); i++) 2842 x->d86_opnd[opindex].d86_value |= 2843 (uint64_t)0xff << (i * 8); 2844 } 2845 #ifdef DIS_TEXT 2846 x->d86_opnd[opindex].d86_mode = MODE_SIGNED; 2847 x->d86_opnd[opindex].d86_value_size = valsize; 2848 x->d86_imm_bytes += size; 2849 #endif 2850 } 2851 2852 /* 2853 * Get an ip relative operand of the given size, with sign extension. 2854 */ 2855 static void 2856 dtrace_disp_opnd(dis86_t *x, int wbit, int size, int opindex) 2857 { 2858 dtrace_imm_opnd(x, wbit, size, opindex); 2859 #ifdef DIS_TEXT 2860 x->d86_opnd[opindex].d86_mode = MODE_IPREL; 2861 #endif 2862 } 2863 2864 /* 2865 * Check to see if there is a segment override prefix pending. 2866 * If so, print it in the current 'operand' location and set 2867 * the override flag back to false. 2868 */ 2869 /*ARGSUSED*/ 2870 static void 2871 dtrace_check_override(dis86_t *x, int opindex) 2872 { 2873 #ifdef DIS_TEXT 2874 if (x->d86_seg_prefix) { 2875 (void) strlcat(x->d86_opnd[opindex].d86_prefix, 2876 x->d86_seg_prefix, PFIXLEN); 2877 } 2878 #endif 2879 x->d86_seg_prefix = NULL; 2880 } 2881 2882 2883 /* 2884 * Process a single instruction Register or Memory operand. 2885 * 2886 * mode = addressing mode from ModRM byte 2887 * r_m = r_m (or reg if mode == 3) field from ModRM byte 2888 * wbit = indicates which register (8bit, 16bit, ... MMX, etc.) set to use. 2889 * o = index of operand that we are processing (0, 1 or 2) 2890 * 2891 * the value of reg or r_m must have already been adjusted for any REX prefix. 2892 */ 2893 /*ARGSUSED*/ 2894 static void 2895 dtrace_get_operand(dis86_t *x, uint_t mode, uint_t r_m, int wbit, int opindex) 2896 { 2897 int have_SIB = 0; /* flag presence of scale-index-byte */ 2898 uint_t ss; /* scale-factor from opcode */ 2899 uint_t index; /* index register number */ 2900 uint_t base; /* base register number */ 2901 int dispsize; /* size of displacement in bytes */ 2902 #ifdef DIS_TEXT 2903 char *opnd = x->d86_opnd[opindex].d86_opnd; 2904 #endif 2905 2906 if (x->d86_numopnds < opindex + 1) 2907 x->d86_numopnds = opindex + 1; 2908 2909 if (x->d86_error) 2910 return; 2911 2912 /* 2913 * first handle a simple register 2914 */ 2915 if (mode == REG_ONLY) { 2916 #ifdef DIS_TEXT 2917 switch (wbit) { 2918 case MM_OPND: 2919 (void) strlcat(opnd, dis_MMREG[r_m], OPLEN); 2920 break; 2921 case XMM_OPND: 2922 (void) strlcat(opnd, dis_XMMREG[r_m], OPLEN); 2923 break; 2924 case YMM_OPND: 2925 (void) strlcat(opnd, dis_YMMREG[r_m], OPLEN); 2926 break; 2927 case ZMM_OPND: 2928 (void) strlcat(opnd, dis_ZMMREG[r_m], OPLEN); 2929 break; 2930 case KOPMASK_OPND: 2931 (void) strlcat(opnd, dis_KOPMASKREG[r_m], OPLEN); 2932 break; 2933 case SEG_OPND: 2934 (void) strlcat(opnd, dis_SEGREG[r_m], OPLEN); 2935 break; 2936 case CONTROL_OPND: 2937 (void) strlcat(opnd, dis_CONTROLREG[r_m], OPLEN); 2938 break; 2939 case DEBUG_OPND: 2940 (void) strlcat(opnd, dis_DEBUGREG[r_m], OPLEN); 2941 break; 2942 case TEST_OPND: 2943 (void) strlcat(opnd, dis_TESTREG[r_m], OPLEN); 2944 break; 2945 case BYTE_OPND: 2946 if (x->d86_rex_prefix == 0) 2947 (void) strlcat(opnd, dis_REG8[r_m], OPLEN); 2948 else 2949 (void) strlcat(opnd, dis_REG8_REX[r_m], OPLEN); 2950 break; 2951 case WORD_OPND: 2952 (void) strlcat(opnd, dis_REG16[r_m], OPLEN); 2953 break; 2954 case LONG_OPND: 2955 if (x->d86_opnd_size == SIZE16) 2956 (void) strlcat(opnd, dis_REG16[r_m], OPLEN); 2957 else if (x->d86_opnd_size == SIZE32) 2958 (void) strlcat(opnd, dis_REG32[r_m], OPLEN); 2959 else 2960 (void) strlcat(opnd, dis_REG64[r_m], OPLEN); 2961 break; 2962 } 2963 #endif /* DIS_TEXT */ 2964 return; 2965 } 2966 2967 /* 2968 * if symbolic representation, skip override prefix, if any 2969 */ 2970 dtrace_check_override(x, opindex); 2971 2972 /* 2973 * Handle 16 bit memory references first, since they decode 2974 * the mode values more simply. 2975 * mode 1 is r_m + 8 bit displacement 2976 * mode 2 is r_m + 16 bit displacement 2977 * mode 0 is just r_m, unless r_m is 6 which is 16 bit disp 2978 */ 2979 if (x->d86_addr_size == SIZE16) { 2980 if ((mode == 0 && r_m == 6) || mode == 2) 2981 dtrace_imm_opnd(x, WORD_OPND, 2, opindex); 2982 else if (mode == 1) 2983 dtrace_imm_opnd(x, BYTE_OPND, 1, opindex); 2984 #ifdef DIS_TEXT 2985 if (mode == 0 && r_m == 6) 2986 x->d86_opnd[opindex].d86_mode = MODE_SIGNED; 2987 else if (mode == 0) 2988 x->d86_opnd[opindex].d86_mode = MODE_NONE; 2989 else 2990 x->d86_opnd[opindex].d86_mode = MODE_OFFSET; 2991 (void) strlcat(opnd, dis_addr16[mode][r_m], OPLEN); 2992 #endif 2993 return; 2994 } 2995 2996 /* 2997 * 32 and 64 bit addressing modes are more complex since they 2998 * can involve an SIB (scaled index and base) byte to decode. 2999 */ 3000 if (r_m == ESP_REGNO || r_m == ESP_REGNO + 8) { 3001 have_SIB = 1; 3002 dtrace_get_SIB(x, &ss, &index, &base); 3003 if (x->d86_error) 3004 return; 3005 if (base != 5 || mode != 0) 3006 if (x->d86_rex_prefix & REX_B) 3007 base += 8; 3008 if (x->d86_rex_prefix & REX_X) 3009 index += 8; 3010 } else { 3011 base = r_m; 3012 } 3013 3014 /* 3015 * Compute the displacement size and get its bytes 3016 */ 3017 dispsize = 0; 3018 3019 if (mode == 1) 3020 dispsize = 1; 3021 else if (mode == 2) 3022 dispsize = 4; 3023 else if ((r_m & 7) == EBP_REGNO || 3024 (have_SIB && (base & 7) == EBP_REGNO)) 3025 dispsize = 4; 3026 3027 if (dispsize > 0) { 3028 dtrace_imm_opnd(x, dispsize == 4 ? LONG_OPND : BYTE_OPND, 3029 dispsize, opindex); 3030 if (x->d86_error) 3031 return; 3032 } 3033 3034 #ifdef DIS_TEXT 3035 if (dispsize > 0) 3036 x->d86_opnd[opindex].d86_mode = MODE_OFFSET; 3037 3038 if (have_SIB == 0) { 3039 if (x->d86_mode == SIZE32) { 3040 if (mode == 0) 3041 (void) strlcat(opnd, dis_addr32_mode0[r_m], 3042 OPLEN); 3043 else 3044 (void) strlcat(opnd, dis_addr32_mode12[r_m], 3045 OPLEN); 3046 } else { 3047 if (mode == 0) { 3048 (void) strlcat(opnd, dis_addr64_mode0[r_m], 3049 OPLEN); 3050 if (r_m == 5) { 3051 x->d86_opnd[opindex].d86_mode = 3052 MODE_RIPREL; 3053 } 3054 } else { 3055 (void) strlcat(opnd, dis_addr64_mode12[r_m], 3056 OPLEN); 3057 } 3058 } 3059 } else { 3060 uint_t need_paren = 0; 3061 char **regs; 3062 char **bregs; 3063 const char *const *sf; 3064 if (x->d86_mode == SIZE32) /* NOTE this is not addr_size! */ 3065 regs = (char **)dis_REG32; 3066 else 3067 regs = (char **)dis_REG64; 3068 3069 if (x->d86_vsib != 0) { 3070 if (wbit == YMM_OPND) { /* NOTE this is not addr_size */ 3071 bregs = (char **)dis_YMMREG; 3072 } else if (wbit == XMM_OPND) { 3073 bregs = (char **)dis_XMMREG; 3074 } else { 3075 bregs = (char **)dis_ZMMREG; 3076 } 3077 sf = dis_vscale_factor; 3078 } else { 3079 bregs = regs; 3080 sf = dis_scale_factor; 3081 } 3082 3083 /* 3084 * print the base (if any) 3085 */ 3086 if (base == EBP_REGNO && mode == 0) { 3087 if (index != ESP_REGNO || x->d86_vsib != 0) { 3088 (void) strlcat(opnd, "(", OPLEN); 3089 need_paren = 1; 3090 } 3091 } else { 3092 (void) strlcat(opnd, "(", OPLEN); 3093 (void) strlcat(opnd, regs[base], OPLEN); 3094 need_paren = 1; 3095 } 3096 3097 /* 3098 * print the index (if any) 3099 */ 3100 if (index != ESP_REGNO || x->d86_vsib) { 3101 (void) strlcat(opnd, ",", OPLEN); 3102 (void) strlcat(opnd, bregs[index], OPLEN); 3103 (void) strlcat(opnd, sf[ss], OPLEN); 3104 } else 3105 if (need_paren) 3106 (void) strlcat(opnd, ")", OPLEN); 3107 } 3108 #endif 3109 } 3110 3111 /* 3112 * Operand sequence for standard instruction involving one register 3113 * and one register/memory operand. 3114 * wbit indicates a byte(0) or opnd_size(1) operation 3115 * vbit indicates direction (0 for "opcode r,r_m") or (1 for "opcode r_m, r") 3116 */ 3117 #define STANDARD_MODRM(x, mode, reg, r_m, rex_prefix, wbit, vbit) { \ 3118 dtrace_get_modrm(x, &mode, ®, &r_m); \ 3119 dtrace_rex_adjust(rex_prefix, mode, ®, &r_m); \ 3120 dtrace_get_operand(x, mode, r_m, wbit, vbit); \ 3121 dtrace_get_operand(x, REG_ONLY, reg, wbit, 1 - vbit); \ 3122 } 3123 3124 /* 3125 * Similar to above, but allows for the two operands to be of different 3126 * classes (ie. wbit). 3127 * wbit is for the r_m operand 3128 * w2 is for the reg operand 3129 */ 3130 #define MIXED_MM(x, mode, reg, r_m, rex_prefix, wbit, w2, vbit) { \ 3131 dtrace_get_modrm(x, &mode, ®, &r_m); \ 3132 dtrace_rex_adjust(rex_prefix, mode, ®, &r_m); \ 3133 dtrace_get_operand(x, mode, r_m, wbit, vbit); \ 3134 dtrace_get_operand(x, REG_ONLY, reg, w2, 1 - vbit); \ 3135 } 3136 3137 /* 3138 * Similar, but for 2 operands plus an immediate. 3139 * vbit indicates direction 3140 * 0 for "opcode imm, r, r_m" or 3141 * 1 for "opcode imm, r_m, r" 3142 */ 3143 #define THREEOPERAND(x, mode, reg, r_m, rex_prefix, wbit, w2, immsize, vbit) { \ 3144 dtrace_get_modrm(x, &mode, ®, &r_m); \ 3145 dtrace_rex_adjust(rex_prefix, mode, ®, &r_m); \ 3146 dtrace_get_operand(x, mode, r_m, wbit, 2-vbit); \ 3147 dtrace_get_operand(x, REG_ONLY, reg, w2, 1+vbit); \ 3148 dtrace_imm_opnd(x, wbit, immsize, 0); \ 3149 } 3150 3151 /* 3152 * Similar, but for 2 operands plus two immediates. 3153 */ 3154 #define FOUROPERAND(x, mode, reg, r_m, rex_prefix, wbit, w2, immsize) { \ 3155 dtrace_get_modrm(x, &mode, ®, &r_m); \ 3156 dtrace_rex_adjust(rex_prefix, mode, ®, &r_m); \ 3157 dtrace_get_operand(x, mode, r_m, wbit, 2); \ 3158 dtrace_get_operand(x, REG_ONLY, reg, w2, 3); \ 3159 dtrace_imm_opnd(x, wbit, immsize, 1); \ 3160 dtrace_imm_opnd(x, wbit, immsize, 0); \ 3161 } 3162 3163 /* 3164 * 1 operands plus two immediates. 3165 */ 3166 #define ONEOPERAND_TWOIMM(x, mode, reg, r_m, rex_prefix, wbit, immsize) { \ 3167 dtrace_get_modrm(x, &mode, ®, &r_m); \ 3168 dtrace_rex_adjust(rex_prefix, mode, ®, &r_m); \ 3169 dtrace_get_operand(x, mode, r_m, wbit, 2); \ 3170 dtrace_imm_opnd(x, wbit, immsize, 1); \ 3171 dtrace_imm_opnd(x, wbit, immsize, 0); \ 3172 } 3173 3174 /* 3175 * Dissassemble a single x86 or amd64 instruction. 3176 * 3177 * Mode determines the default operating mode (SIZE16, SIZE32 or SIZE64) 3178 * for interpreting instructions. 3179 * 3180 * returns non-zero for bad opcode 3181 */ 3182 int 3183 dtrace_disx86(dis86_t *x, uint_t cpu_mode) 3184 { 3185 instable_t *dp; /* decode table being used */ 3186 #ifdef DIS_TEXT 3187 uint_t i; 3188 #endif 3189 #ifdef DIS_MEM 3190 uint_t nomem = 0; 3191 #define NOMEM (nomem = 1) 3192 #else 3193 #define NOMEM /* nothing */ 3194 #endif 3195 uint_t opnd_size; /* SIZE16, SIZE32 or SIZE64 */ 3196 uint_t addr_size; /* SIZE16, SIZE32 or SIZE64 */ 3197 uint_t wbit; /* opcode wbit, 0 is 8 bit, !0 for opnd_size */ 3198 uint_t w2; /* wbit value for second operand */ 3199 uint_t vbit; 3200 uint_t mode = 0; /* mode value from ModRM byte */ 3201 uint_t reg; /* reg value from ModRM byte */ 3202 uint_t r_m; /* r_m value from ModRM byte */ 3203 3204 uint_t opcode1; /* high nibble of 1st byte */ 3205 uint_t opcode2; /* low nibble of 1st byte */ 3206 uint_t opcode3; /* extra opcode bits usually from ModRM byte */ 3207 uint_t opcode4; /* high nibble of 2nd byte */ 3208 uint_t opcode5; /* low nibble of 2nd byte */ 3209 uint_t opcode6; /* high nibble of 3rd byte */ 3210 uint_t opcode7; /* low nibble of 3rd byte */ 3211 uint_t opcode8; /* high nibble of 4th byte */ 3212 uint_t opcode9; /* low nibble of 4th byte */ 3213 uint_t opcode_bytes = 1; 3214 3215 /* 3216 * legacy prefixes come in 5 flavors, you should have only one of each 3217 */ 3218 uint_t opnd_size_prefix = 0; 3219 uint_t addr_size_prefix = 0; 3220 uint_t segment_prefix = 0; 3221 uint_t lock_prefix = 0; 3222 uint_t rep_prefix = 0; 3223 uint_t rex_prefix = 0; /* amd64 register extension prefix */ 3224 3225 /* 3226 * Intel VEX instruction encoding prefix and fields 3227 */ 3228 3229 /* 0xC4 means 3 bytes prefix, 0xC5 means 2 bytes prefix */ 3230 uint_t vex_prefix = 0; 3231 3232 /* 3233 * VEX prefix byte 1, includes vex.r, vex.x and vex.b 3234 * (for 3 bytes prefix) 3235 */ 3236 uint_t vex_byte1 = 0; 3237 3238 /* 3239 * EVEX prefix byte 1 includes vex.r, vex.x, vex.b and evex.r. 3240 */ 3241 uint_t evex_byte1 = 0; 3242 uint_t evex_byte2 = 0; 3243 uint_t evex_byte3 = 0; 3244 3245 /* 3246 * For 32-bit mode, it should prefetch the next byte to 3247 * distinguish between AVX and les/lds 3248 */ 3249 uint_t vex_prefetch = 0; 3250 3251 uint_t vex_m = 0; 3252 uint_t vex_v = 0; 3253 uint_t vex_p = 0; 3254 uint_t vex_R = 1; 3255 uint_t vex_X = 1; 3256 uint_t vex_B = 1; 3257 uint_t vex_W = 0; 3258 uint_t vex_L; 3259 uint_t evex_L; 3260 uint_t evex_modrm; 3261 dis_gather_regs_t *vreg; 3262 3263 #ifdef DIS_TEXT 3264 /* Instruction name for BLS* family of instructions */ 3265 char *blsinstr; 3266 #endif 3267 3268 size_t off; 3269 3270 instable_t dp_mmx; 3271 3272 x->d86_len = 0; 3273 x->d86_rmindex = -1; 3274 x->d86_error = 0; 3275 #ifdef DIS_TEXT 3276 x->d86_numopnds = 0; 3277 x->d86_seg_prefix = NULL; 3278 x->d86_mnem[0] = 0; 3279 for (i = 0; i < 4; ++i) { 3280 x->d86_opnd[i].d86_opnd[0] = 0; 3281 x->d86_opnd[i].d86_prefix[0] = 0; 3282 x->d86_opnd[i].d86_value_size = 0; 3283 x->d86_opnd[i].d86_value = 0; 3284 x->d86_opnd[i].d86_mode = MODE_NONE; 3285 } 3286 #endif 3287 x->d86_rex_prefix = 0; 3288 x->d86_got_modrm = 0; 3289 x->d86_memsize = 0; 3290 x->d86_vsib = 0; 3291 3292 if (cpu_mode == SIZE16) { 3293 opnd_size = SIZE16; 3294 addr_size = SIZE16; 3295 } else if (cpu_mode == SIZE32) { 3296 opnd_size = SIZE32; 3297 addr_size = SIZE32; 3298 } else { 3299 opnd_size = SIZE32; 3300 addr_size = SIZE64; 3301 } 3302 3303 /* 3304 * Get one opcode byte and check for zero padding that follows 3305 * jump tables. 3306 */ 3307 if (dtrace_get_opcode(x, &opcode1, &opcode2) != 0) 3308 goto error; 3309 3310 if (opcode1 == 0 && opcode2 == 0 && 3311 x->d86_check_func != NULL && x->d86_check_func(x->d86_data)) { 3312 #ifdef DIS_TEXT 3313 (void) strncpy(x->d86_mnem, ".byte\t0", OPLEN); 3314 #endif 3315 goto done; 3316 } 3317 3318 /* 3319 * Gather up legacy x86 prefix bytes. 3320 */ 3321 for (;;) { 3322 uint_t *which_prefix = NULL; 3323 3324 dp = (instable_t *)&dis_distable[opcode1][opcode2]; 3325 3326 switch (dp->it_adrmode) { 3327 case PREFIX: 3328 which_prefix = &rep_prefix; 3329 break; 3330 case LOCK: 3331 which_prefix = &lock_prefix; 3332 break; 3333 case OVERRIDE: 3334 which_prefix = &segment_prefix; 3335 #ifdef DIS_TEXT 3336 x->d86_seg_prefix = (char *)dp->it_name; 3337 #endif 3338 if (dp->it_invalid64 && cpu_mode == SIZE64) 3339 goto error; 3340 break; 3341 case AM: 3342 which_prefix = &addr_size_prefix; 3343 break; 3344 case DM: 3345 which_prefix = &opnd_size_prefix; 3346 break; 3347 } 3348 if (which_prefix == NULL) 3349 break; 3350 *which_prefix = (opcode1 << 4) | opcode2; 3351 if (dtrace_get_opcode(x, &opcode1, &opcode2) != 0) 3352 goto error; 3353 } 3354 3355 /* 3356 * Handle amd64 mode PREFIX values. 3357 * Some of the segment prefixes are no-ops. (only FS/GS actually work) 3358 * We might have a REX prefix (opcodes 0x40-0x4f) 3359 */ 3360 if (cpu_mode == SIZE64) { 3361 if (segment_prefix != 0x64 && segment_prefix != 0x65) 3362 segment_prefix = 0; 3363 3364 if (opcode1 == 0x4) { 3365 rex_prefix = (opcode1 << 4) | opcode2; 3366 if (dtrace_get_opcode(x, &opcode1, &opcode2) != 0) 3367 goto error; 3368 dp = (instable_t *)&dis_distable[opcode1][opcode2]; 3369 } else if (opcode1 == 0xC && 3370 (opcode2 == 0x4 || opcode2 == 0x5)) { 3371 /* AVX instructions */ 3372 vex_prefix = (opcode1 << 4) | opcode2; 3373 x->d86_rex_prefix = 0x40; 3374 } 3375 } else if (opcode1 == 0xC && (opcode2 == 0x4 || opcode2 == 0x5)) { 3376 /* LDS, LES or AVX */ 3377 dtrace_get_modrm(x, &mode, ®, &r_m); 3378 vex_prefetch = 1; 3379 3380 if (mode == REG_ONLY) { 3381 /* AVX */ 3382 vex_prefix = (opcode1 << 4) | opcode2; 3383 x->d86_rex_prefix = 0x40; 3384 opcode3 = (((mode << 3) | reg)>>1) & 0x0F; 3385 opcode4 = ((reg << 3) | r_m) & 0x0F; 3386 } 3387 } 3388 3389 /* 3390 * The EVEX prefix and "bound" instruction share the same first byte. 3391 * "bound" is only valid for 32-bit. For 64-bit this byte begins the 3392 * EVEX prefix and the 2nd byte must have bits 2 & 3 set to 0. 3393 */ 3394 if (opcode1 == 0x6 && opcode2 == 0x2) { 3395 /* 3396 * An EVEX prefix is 4 bytes long, get the next 3 bytes. 3397 */ 3398 if (dtrace_get_opcode(x, &opcode4, &opcode5) != 0) 3399 goto error; 3400 3401 if (addr_size == SIZE32 && (opcode4 & 0xf) == 0) { 3402 /* 3403 * Upper bits in 2nd byte == 0 is 'bound' instn. 3404 * 3405 * We've already read the byte so perform the 3406 * equivalent of dtrace_get_modrm on the byte and set 3407 * the flag to indicate we've already read it. 3408 */ 3409 char b = (opcode4 << 4) | opcode5; 3410 3411 r_m = b & 0x7; 3412 reg = (b >> 3) & 0x7; 3413 mode = (b >> 6) & 0x3; 3414 vex_prefetch = 1; 3415 goto not_avx512; 3416 } 3417 3418 /* check for correct bits being 0 in 2nd byte */ 3419 if ((opcode5 & 0xc) != 0) 3420 goto error; 3421 3422 if (dtrace_get_opcode(x, &opcode6, &opcode7) != 0) 3423 goto error; 3424 /* check for correct bit being 1 in 3rd byte */ 3425 if ((opcode7 & 0x4) == 0) 3426 goto error; 3427 3428 if (dtrace_get_opcode(x, &opcode8, &opcode9) != 0) 3429 goto error; 3430 3431 /* Reuse opcode1 & opcode2 to get the real opcode now */ 3432 if (dtrace_get_opcode(x, &opcode1, &opcode2) != 0) 3433 goto error; 3434 3435 /* 3436 * We only use the high nibble from the 2nd byte of the prefix 3437 * and save it in the low bits of evex_byte1. This is because 3438 * two of the bits in opcode5 are constant 0 (checked above), 3439 * and the other two bits are captured in vex_m. Also, the VEX 3440 * constants we check in evex_byte1 are against the low bits. 3441 */ 3442 evex_byte1 = opcode4; 3443 evex_byte2 = (opcode6 << 4) | opcode7; 3444 evex_byte3 = (opcode8 << 4) | opcode9; 3445 3446 vex_m = opcode5 & EVEX_m; 3447 vex_v = (((opcode6 << 4) | opcode7) & VEX_v) >> 3; 3448 vex_W = (opcode6 & VEX_W) >> 3; 3449 vex_p = opcode7 & VEX_p; 3450 3451 /* Currently only 3 valid values for evex L'L: 00, 01, 10 */ 3452 evex_L = (opcode8 & EVEX_L) >> 1; 3453 3454 dp = (instable_t *)&dis_opAVX62[(opcode1 << 4) | opcode2]; 3455 } 3456 not_avx512: 3457 3458 if (vex_prefix == VEX_2bytes) { 3459 if (!vex_prefetch) { 3460 if (dtrace_get_opcode(x, &opcode3, &opcode4) != 0) 3461 goto error; 3462 } 3463 vex_R = ((opcode3 & VEX_R) & 0x0F) >> 3; 3464 vex_L = ((opcode4 & VEX_L) & 0x0F) >> 2; 3465 vex_v = (((opcode3 << 4) | opcode4) & VEX_v) >> 3; 3466 vex_p = opcode4 & VEX_p; 3467 /* 3468 * The vex.x and vex.b bits are not defined in two bytes 3469 * mode vex prefix, their default values are 1 3470 */ 3471 vex_byte1 = (opcode3 & VEX_R) | VEX_X | VEX_B; 3472 3473 if (vex_R == 0) 3474 x->d86_rex_prefix |= REX_R; 3475 3476 if (dtrace_get_opcode(x, &opcode1, &opcode2) != 0) 3477 goto error; 3478 3479 switch (vex_p) { 3480 case VEX_p_66: 3481 dp = (instable_t *) 3482 &dis_opAVX660F[(opcode1 << 4) | opcode2]; 3483 break; 3484 case VEX_p_F3: 3485 dp = (instable_t *) 3486 &dis_opAVXF30F[(opcode1 << 4) | opcode2]; 3487 break; 3488 case VEX_p_F2: 3489 dp = (instable_t *) 3490 &dis_opAVXF20F [(opcode1 << 4) | opcode2]; 3491 break; 3492 default: 3493 dp = (instable_t *) 3494 &dis_opAVX0F[opcode1][opcode2]; 3495 3496 } 3497 3498 } else if (vex_prefix == VEX_3bytes) { 3499 if (!vex_prefetch) { 3500 if (dtrace_get_opcode(x, &opcode3, &opcode4) != 0) 3501 goto error; 3502 } 3503 vex_R = (opcode3 & VEX_R) >> 3; 3504 vex_X = (opcode3 & VEX_X) >> 2; 3505 vex_B = (opcode3 & VEX_B) >> 1; 3506 vex_m = (((opcode3 << 4) | opcode4) & VEX_m); 3507 vex_byte1 = opcode3 & (VEX_R | VEX_X | VEX_B); 3508 3509 if (vex_R == 0) 3510 x->d86_rex_prefix |= REX_R; 3511 if (vex_X == 0) 3512 x->d86_rex_prefix |= REX_X; 3513 if (vex_B == 0) 3514 x->d86_rex_prefix |= REX_B; 3515 3516 if (dtrace_get_opcode(x, &opcode5, &opcode6) != 0) 3517 goto error; 3518 vex_W = (opcode5 & VEX_W) >> 3; 3519 vex_L = (opcode6 & VEX_L) >> 2; 3520 vex_v = (((opcode5 << 4) | opcode6) & VEX_v) >> 3; 3521 vex_p = opcode6 & VEX_p; 3522 3523 if (vex_W) 3524 x->d86_rex_prefix |= REX_W; 3525 3526 /* Only these three vex_m values valid; others are reserved */ 3527 if ((vex_m != VEX_m_0F) && (vex_m != VEX_m_0F38) && 3528 (vex_m != VEX_m_0F3A)) 3529 goto error; 3530 3531 if (dtrace_get_opcode(x, &opcode1, &opcode2) != 0) 3532 goto error; 3533 3534 switch (vex_p) { 3535 case VEX_p_66: 3536 if (vex_m == VEX_m_0F) { 3537 dp = (instable_t *) 3538 &dis_opAVX660F 3539 [(opcode1 << 4) | opcode2]; 3540 } else if (vex_m == VEX_m_0F38) { 3541 dp = (instable_t *) 3542 &dis_opAVX660F38 3543 [(opcode1 << 4) | opcode2]; 3544 } else if (vex_m == VEX_m_0F3A) { 3545 dp = (instable_t *) 3546 &dis_opAVX660F3A 3547 [(opcode1 << 4) | opcode2]; 3548 } else { 3549 goto error; 3550 } 3551 break; 3552 case VEX_p_F3: 3553 if (vex_m == VEX_m_0F) { 3554 dp = (instable_t *) 3555 &dis_opAVXF30F 3556 [(opcode1 << 4) | opcode2]; 3557 } else if (vex_m == VEX_m_0F38) { 3558 dp = (instable_t *) 3559 &dis_opAVXF30F38 3560 [(opcode1 << 4) | opcode2]; 3561 } else { 3562 goto error; 3563 } 3564 break; 3565 case VEX_p_F2: 3566 if (vex_m == VEX_m_0F) { 3567 dp = (instable_t *) 3568 &dis_opAVXF20F 3569 [(opcode1 << 4) | opcode2]; 3570 } else if (vex_m == VEX_m_0F3A) { 3571 dp = (instable_t *) 3572 &dis_opAVXF20F3A 3573 [(opcode1 << 4) | opcode2]; 3574 } else if (vex_m == VEX_m_0F38) { 3575 dp = (instable_t *) 3576 &dis_opAVXF20F38 3577 [(opcode1 << 4) | opcode2]; 3578 } else { 3579 goto error; 3580 } 3581 break; 3582 default: 3583 dp = (instable_t *) 3584 &dis_opAVX0F[opcode1][opcode2]; 3585 3586 } 3587 } 3588 if (vex_prefix) { 3589 if (dp->it_vexwoxmm) { 3590 wbit = LONG_OPND; 3591 } else if (dp->it_vexopmask) { 3592 wbit = KOPMASK_OPND; 3593 } else { 3594 if (vex_L) { 3595 wbit = YMM_OPND; 3596 } else { 3597 wbit = XMM_OPND; 3598 } 3599 } 3600 } 3601 3602 /* 3603 * Deal with selection of operand and address size now. 3604 * Note that the REX.W bit being set causes opnd_size_prefix to be 3605 * ignored. 3606 */ 3607 if (cpu_mode == SIZE64) { 3608 if ((rex_prefix & REX_W) || vex_W) 3609 opnd_size = SIZE64; 3610 else if (opnd_size_prefix) 3611 opnd_size = SIZE16; 3612 3613 if (addr_size_prefix) 3614 addr_size = SIZE32; 3615 } else if (cpu_mode == SIZE32) { 3616 if (opnd_size_prefix) 3617 opnd_size = SIZE16; 3618 if (addr_size_prefix) 3619 addr_size = SIZE16; 3620 } else { 3621 if (opnd_size_prefix) 3622 opnd_size = SIZE32; 3623 if (addr_size_prefix) 3624 addr_size = SIZE32; 3625 } 3626 /* 3627 * The pause instruction - a repz'd nop. This doesn't fit 3628 * with any of the other prefix goop added for SSE, so we'll 3629 * special-case it here. 3630 */ 3631 if (rep_prefix == 0xf3 && opcode1 == 0x9 && opcode2 == 0x0) { 3632 rep_prefix = 0; 3633 dp = (instable_t *)&dis_opPause; 3634 } 3635 3636 /* 3637 * Some 386 instructions have 2 bytes of opcode before the mod_r/m 3638 * byte so we may need to perform a table indirection. 3639 */ 3640 if (dp->it_indirect == (instable_t *)dis_op0F) { 3641 if (dtrace_get_opcode(x, &opcode4, &opcode5) != 0) 3642 goto error; 3643 opcode_bytes = 2; 3644 if (opcode4 == 0x7 && opcode5 >= 0x1 && opcode5 <= 0x3) { 3645 uint_t subcode; 3646 3647 if (dtrace_get_opcode(x, &opcode6, &opcode7) != 0) 3648 goto error; 3649 opcode_bytes = 3; 3650 subcode = ((opcode6 & 0x3) << 1) | 3651 ((opcode7 & 0x8) >> 3); 3652 dp = (instable_t *)&dis_op0F7123[opcode5][subcode]; 3653 } else if ((opcode4 == 0xc) && (opcode5 >= 0x8)) { 3654 dp = (instable_t *)&dis_op0FC8[0]; 3655 } else if ((opcode4 == 0x3) && (opcode5 == 0xA)) { 3656 opcode_bytes = 3; 3657 if (dtrace_get_opcode(x, &opcode6, &opcode7) != 0) 3658 goto error; 3659 if (opnd_size == SIZE16) 3660 opnd_size = SIZE32; 3661 3662 dp = (instable_t *)&dis_op0F3A[(opcode6<<4)|opcode7]; 3663 #ifdef DIS_TEXT 3664 if (strcmp(dp->it_name, "INVALID") == 0) 3665 goto error; 3666 #endif 3667 switch (dp->it_adrmode) { 3668 case XMMP: 3669 break; 3670 case XMMP_66r: 3671 case XMMPRM_66r: 3672 case XMM3PM_66r: 3673 if (opnd_size_prefix == 0) { 3674 goto error; 3675 } 3676 3677 break; 3678 case XMMP_66o: 3679 if (opnd_size_prefix == 0) { 3680 /* SSSE3 MMX instructions */ 3681 dp_mmx = *dp; 3682 dp = &dp_mmx; 3683 dp->it_adrmode = MMOPM_66o; 3684 #ifdef DIS_MEM 3685 dp->it_size = 8; 3686 #endif 3687 } 3688 break; 3689 default: 3690 goto error; 3691 } 3692 } else if ((opcode4 == 0x3) && (opcode5 == 0x8)) { 3693 opcode_bytes = 3; 3694 if (dtrace_get_opcode(x, &opcode6, &opcode7) != 0) 3695 goto error; 3696 dp = (instable_t *)&dis_op0F38[(opcode6<<4)|opcode7]; 3697 3698 /* 3699 * Both crc32 and movbe have the same 3rd opcode 3700 * byte of either 0xF0 or 0xF1, so we use another 3701 * indirection to distinguish between the two. 3702 */ 3703 if (dp->it_indirect == (instable_t *)dis_op0F38F0 || 3704 dp->it_indirect == (instable_t *)dis_op0F38F1) { 3705 3706 dp = dp->it_indirect; 3707 if (rep_prefix != 0xF2) { 3708 /* It is movbe */ 3709 dp++; 3710 } 3711 } 3712 3713 /* 3714 * The adx family of instructions (adcx and adox) 3715 * continue the classic Intel tradition of abusing 3716 * arbitrary prefixes without actually meaning the 3717 * prefix bit. Therefore, if we find either the 3718 * opnd_size_prefix or rep_prefix we end up zeroing it 3719 * out after making our determination so as to ensure 3720 * that we don't get confused and accidentally print 3721 * repz prefixes and the like on these instructions. 3722 * 3723 * In addition, these instructions are actually much 3724 * closer to AVX instructions in semantics. Importantly, 3725 * they always default to having 32-bit operands. 3726 * However, if the CPU is in 64-bit mode, then and only 3727 * then, does it use REX.w promotes things to 64-bits 3728 * and REX.r allows 64-bit mode to use register r8-r15. 3729 */ 3730 if (dp->it_indirect == (instable_t *)dis_op0F38F6) { 3731 dp = dp->it_indirect; 3732 if (opnd_size_prefix == 0 && 3733 rep_prefix == 0xf3) { 3734 /* It is adox */ 3735 dp++; 3736 } else if (opnd_size_prefix != 0x66 && 3737 rep_prefix != 0) { 3738 /* It isn't adcx */ 3739 goto error; 3740 } 3741 opnd_size_prefix = 0; 3742 rep_prefix = 0; 3743 opnd_size = SIZE32; 3744 if (rex_prefix & REX_W) 3745 opnd_size = SIZE64; 3746 } 3747 3748 #ifdef DIS_TEXT 3749 if (strcmp(dp->it_name, "INVALID") == 0) 3750 goto error; 3751 #endif 3752 switch (dp->it_adrmode) { 3753 case ADX: 3754 case XMM: 3755 break; 3756 case RM_66r: 3757 case XMM_66r: 3758 case XMMM_66r: 3759 if (opnd_size_prefix == 0) { 3760 goto error; 3761 } 3762 break; 3763 case XMM_66o: 3764 if (opnd_size_prefix == 0) { 3765 /* SSSE3 MMX instructions */ 3766 dp_mmx = *dp; 3767 dp = &dp_mmx; 3768 dp->it_adrmode = MM; 3769 #ifdef DIS_MEM 3770 dp->it_size = 8; 3771 #endif 3772 } 3773 break; 3774 case CRC32: 3775 if (rep_prefix != 0xF2) { 3776 goto error; 3777 } 3778 rep_prefix = 0; 3779 break; 3780 case MOVBE: 3781 if (rep_prefix != 0x0) { 3782 goto error; 3783 } 3784 break; 3785 default: 3786 goto error; 3787 } 3788 } else { 3789 dp = (instable_t *)&dis_op0F[opcode4][opcode5]; 3790 } 3791 } 3792 3793 /* 3794 * If still not at a TERM decode entry, then a ModRM byte 3795 * exists and its fields further decode the instruction. 3796 */ 3797 x->d86_got_modrm = 0; 3798 if (dp->it_indirect != TERM) { 3799 dtrace_get_modrm(x, &mode, &opcode3, &r_m); 3800 if (x->d86_error) 3801 goto error; 3802 reg = opcode3; 3803 3804 /* 3805 * decode 287 instructions (D8-DF) from opcodeN 3806 */ 3807 if (opcode1 == 0xD && opcode2 >= 0x8) { 3808 if (opcode2 == 0xB && mode == 0x3 && opcode3 == 4) 3809 dp = (instable_t *)&dis_opFP5[r_m]; 3810 else if (opcode2 == 0xA && mode == 0x3 && opcode3 < 4) 3811 dp = (instable_t *)&dis_opFP7[opcode3]; 3812 else if (opcode2 == 0xB && mode == 0x3) 3813 dp = (instable_t *)&dis_opFP6[opcode3]; 3814 else if (opcode2 == 0x9 && mode == 0x3 && opcode3 >= 4) 3815 dp = (instable_t *)&dis_opFP4[opcode3 - 4][r_m]; 3816 else if (mode == 0x3) 3817 dp = (instable_t *) 3818 &dis_opFP3[opcode2 - 8][opcode3]; 3819 else 3820 dp = (instable_t *) 3821 &dis_opFP1n2[opcode2 - 8][opcode3]; 3822 } else { 3823 dp = (instable_t *)dp->it_indirect + opcode3; 3824 } 3825 } 3826 3827 /* 3828 * In amd64 bit mode, ARPL opcode is changed to MOVSXD 3829 * (sign extend 32bit to 64 bit) 3830 */ 3831 if ((vex_prefix == 0) && cpu_mode == SIZE64 && 3832 opcode1 == 0x6 && opcode2 == 0x3) 3833 dp = (instable_t *)&dis_opMOVSLD; 3834 3835 /* 3836 * at this point we should have a correct (or invalid) opcode 3837 */ 3838 if (cpu_mode == SIZE64 && dp->it_invalid64 || 3839 cpu_mode != SIZE64 && dp->it_invalid32) 3840 goto error; 3841 if (dp->it_indirect != TERM) 3842 goto error; 3843 3844 /* 3845 * Deal with MMX/SSE opcodes which are changed by prefixes. Note, we do 3846 * need to include UNKNOWN below, as we may have instructions that 3847 * actually have a prefix, but don't exist in any other form. 3848 */ 3849 switch (dp->it_adrmode) { 3850 case UNKNOWN: 3851 case MMO: 3852 case MMOIMPL: 3853 case MMO3P: 3854 case MMOM3: 3855 case MMOMS: 3856 case MMOPM: 3857 case MMOPRM: 3858 case MMOS: 3859 case XMMO: 3860 case XMMOM: 3861 case XMMOMS: 3862 case XMMOPM: 3863 case XMMOS: 3864 case XMMOMX: 3865 case XMMOX3: 3866 case XMMOXMM: 3867 /* 3868 * This is horrible. Some SIMD instructions take the 3869 * form 0x0F 0x?? ..., which is easily decoded using the 3870 * existing tables. Other SIMD instructions use various 3871 * prefix bytes to overload existing instructions. For 3872 * Example, addps is F0, 58, whereas addss is F3 (repz), 3873 * F0, 58. Presumably someone got a raise for this. 3874 * 3875 * If we see one of the instructions which can be 3876 * modified in this way (if we've got one of the SIMDO* 3877 * address modes), we'll check to see if the last prefix 3878 * was a repz. If it was, we strip the prefix from the 3879 * mnemonic, and we indirect using the dis_opSIMDrepz 3880 * table. 3881 */ 3882 3883 /* 3884 * Calculate our offset in dis_op0F 3885 */ 3886 if ((uintptr_t)dp - (uintptr_t)dis_op0F > sizeof (dis_op0F)) 3887 goto error; 3888 3889 off = ((uintptr_t)dp - (uintptr_t)dis_op0F) / 3890 sizeof (instable_t); 3891 3892 /* 3893 * Rewrite if this instruction used one of the magic prefixes. 3894 */ 3895 if (rep_prefix) { 3896 if (rep_prefix == 0xf2) 3897 dp = (instable_t *)&dis_opSIMDrepnz[off]; 3898 else 3899 dp = (instable_t *)&dis_opSIMDrepz[off]; 3900 rep_prefix = 0; 3901 } else if (opnd_size_prefix) { 3902 dp = (instable_t *)&dis_opSIMDdata16[off]; 3903 opnd_size_prefix = 0; 3904 if (opnd_size == SIZE16) 3905 opnd_size = SIZE32; 3906 } 3907 break; 3908 3909 case MG9: 3910 /* 3911 * More horribleness: the group 9 (0xF0 0xC7) instructions are 3912 * allowed an optional prefix of 0x66 or 0xF3. This is similar 3913 * to the SIMD business described above, but with a different 3914 * addressing mode (and an indirect table), so we deal with it 3915 * separately (if similarly). 3916 * 3917 * Intel further complicated this with the release of Ivy Bridge 3918 * where they overloaded these instructions based on the ModR/M 3919 * bytes. The VMX instructions have a mode of 0 since they are 3920 * memory instructions but rdrand instructions have a mode of 3921 * 0b11 (REG_ONLY) because they only operate on registers. While 3922 * there are different prefix formats, for now it is sufficient 3923 * to use a single different table. 3924 */ 3925 3926 /* 3927 * Calculate our offset in dis_op0FC7 (the group 9 table) 3928 */ 3929 if ((uintptr_t)dp - (uintptr_t)dis_op0FC7 > sizeof (dis_op0FC7)) 3930 goto error; 3931 3932 off = ((uintptr_t)dp - (uintptr_t)dis_op0FC7) / 3933 sizeof (instable_t); 3934 3935 /* 3936 * If we have a mode of 0b11 then we have to rewrite this. 3937 */ 3938 dtrace_get_modrm(x, &mode, ®, &r_m); 3939 if (mode == REG_ONLY) { 3940 dp = (instable_t *)&dis_op0FC7m3[off]; 3941 break; 3942 } 3943 3944 /* 3945 * Rewrite if this instruction used one of the magic prefixes. 3946 */ 3947 if (rep_prefix) { 3948 if (rep_prefix == 0xf3) 3949 dp = (instable_t *)&dis_opF30FC7[off]; 3950 else 3951 goto error; 3952 rep_prefix = 0; 3953 } else if (opnd_size_prefix) { 3954 dp = (instable_t *)&dis_op660FC7[off]; 3955 opnd_size_prefix = 0; 3956 if (opnd_size == SIZE16) 3957 opnd_size = SIZE32; 3958 } else if (reg == 4 || reg == 5) { 3959 /* 3960 * We have xsavec (4) or xsaves (5), so rewrite. 3961 */ 3962 dp = (instable_t *)&dis_op0FC7[reg]; 3963 break; 3964 } 3965 break; 3966 3967 3968 case MMOSH: 3969 /* 3970 * As with the "normal" SIMD instructions, the MMX 3971 * shuffle instructions are overloaded. These 3972 * instructions, however, are special in that they use 3973 * an extra byte, and thus an extra table. As of this 3974 * writing, they only use the opnd_size prefix. 3975 */ 3976 3977 /* 3978 * Calculate our offset in dis_op0F7123 3979 */ 3980 if ((uintptr_t)dp - (uintptr_t)dis_op0F7123 > 3981 sizeof (dis_op0F7123)) 3982 goto error; 3983 3984 if (opnd_size_prefix) { 3985 off = ((uintptr_t)dp - (uintptr_t)dis_op0F7123) / 3986 sizeof (instable_t); 3987 dp = (instable_t *)&dis_opSIMD7123[off]; 3988 opnd_size_prefix = 0; 3989 if (opnd_size == SIZE16) 3990 opnd_size = SIZE32; 3991 } 3992 break; 3993 case MRw: 3994 if (rep_prefix) { 3995 if (rep_prefix == 0xf3) { 3996 3997 /* 3998 * Calculate our offset in dis_op0F 3999 */ 4000 if ((uintptr_t)dp - (uintptr_t)dis_op0F 4001 > sizeof (dis_op0F)) 4002 goto error; 4003 4004 off = ((uintptr_t)dp - (uintptr_t)dis_op0F) / 4005 sizeof (instable_t); 4006 4007 dp = (instable_t *)&dis_opSIMDrepz[off]; 4008 rep_prefix = 0; 4009 } else { 4010 goto error; 4011 } 4012 } 4013 break; 4014 } 4015 4016 /* 4017 * In 64 bit mode, some opcodes automatically use opnd_size == SIZE64. 4018 */ 4019 if (cpu_mode == SIZE64) 4020 if (dp->it_always64 || (opnd_size == SIZE32 && dp->it_stackop)) 4021 opnd_size = SIZE64; 4022 4023 #ifdef DIS_TEXT 4024 /* 4025 * At this point most instructions can format the opcode mnemonic 4026 * including the prefixes. 4027 */ 4028 if (lock_prefix) 4029 (void) strlcat(x->d86_mnem, "lock ", OPLEN); 4030 4031 if (rep_prefix == 0xf2) 4032 (void) strlcat(x->d86_mnem, "repnz ", OPLEN); 4033 else if (rep_prefix == 0xf3) 4034 (void) strlcat(x->d86_mnem, "repz ", OPLEN); 4035 4036 if (cpu_mode == SIZE64 && addr_size_prefix) 4037 (void) strlcat(x->d86_mnem, "addr32 ", OPLEN); 4038 4039 if (dp->it_adrmode != CBW && 4040 dp->it_adrmode != CWD && 4041 dp->it_adrmode != XMMSFNC) { 4042 if (strcmp(dp->it_name, "INVALID") == 0) 4043 goto error; 4044 (void) strlcat(x->d86_mnem, dp->it_name, OPLEN); 4045 if (dp->it_avxsuf && dp->it_suffix) { 4046 (void) strlcat(x->d86_mnem, vex_W != 0 ? "q" : "d", 4047 OPLEN); 4048 } else if (dp->it_vexopmask && dp->it_suffix) { 4049 /* opmask instructions */ 4050 4051 if (opcode1 == 4 && opcode2 == 0xb) { 4052 /* It's a kunpck. */ 4053 if (vex_prefix == VEX_2bytes) { 4054 (void) strlcat(x->d86_mnem, 4055 vex_p == 0 ? "wd" : "bw", OPLEN); 4056 } else { 4057 /* vex_prefix == VEX_3bytes */ 4058 (void) strlcat(x->d86_mnem, 4059 "dq", OPLEN); 4060 } 4061 } else if (opcode1 == 3) { 4062 /* It's a kshift[l|r]. */ 4063 if (vex_W == 0) { 4064 (void) strlcat(x->d86_mnem, 4065 opcode2 == 2 || 4066 opcode2 == 0 ? 4067 "b" : "d", OPLEN); 4068 } else { 4069 /* W == 1 */ 4070 (void) strlcat(x->d86_mnem, 4071 opcode2 == 3 || opcode2 == 1 ? 4072 "q" : "w", OPLEN); 4073 } 4074 } else { 4075 /* if (vex_prefix == VEX_2bytes) { */ 4076 if ((cpu_mode == SIZE64 && opnd_size == 2) || 4077 vex_prefix == VEX_2bytes) { 4078 (void) strlcat(x->d86_mnem, 4079 vex_p == 0 ? "w" : 4080 vex_p == 1 ? "b" : "d", 4081 OPLEN); 4082 } else { 4083 /* vex_prefix == VEX_3bytes */ 4084 (void) strlcat(x->d86_mnem, 4085 vex_p == 1 ? "d" : "q", OPLEN); 4086 } 4087 } 4088 } else if (dp->it_suffix) { 4089 char *types[] = {"", "w", "l", "q"}; 4090 if (opcode_bytes == 2 && opcode4 == 4) { 4091 /* It's a cmovx.yy. Replace the suffix x */ 4092 for (i = 5; i < OPLEN; i++) { 4093 if (x->d86_mnem[i] == '.') 4094 break; 4095 } 4096 x->d86_mnem[i - 1] = *types[opnd_size]; 4097 } else if ((opnd_size == 2) && (opcode_bytes == 3) && 4098 ((opcode6 == 1 && opcode7 == 6) || 4099 (opcode6 == 2 && opcode7 == 2))) { 4100 /* 4101 * To handle PINSRD and PEXTRD 4102 */ 4103 (void) strlcat(x->d86_mnem, "d", OPLEN); 4104 } else if (dp != &dis_distable[0x6][0x2]) { 4105 /* bound instructions (0x62) have no suffix */ 4106 (void) strlcat(x->d86_mnem, types[opnd_size], 4107 OPLEN); 4108 } 4109 } 4110 } 4111 #endif 4112 4113 /* 4114 * Process operands based on the addressing modes. 4115 */ 4116 x->d86_mode = cpu_mode; 4117 /* 4118 * In vex mode the rex_prefix has no meaning 4119 */ 4120 if (!vex_prefix) 4121 x->d86_rex_prefix = rex_prefix; 4122 x->d86_opnd_size = opnd_size; 4123 x->d86_addr_size = addr_size; 4124 vbit = 0; /* initialize for mem/reg -> reg */ 4125 switch (dp->it_adrmode) { 4126 /* 4127 * amd64 instruction to sign extend 32 bit reg/mem operands 4128 * into 64 bit register values 4129 */ 4130 case MOVSXZ: 4131 #ifdef DIS_TEXT 4132 if (rex_prefix == 0) 4133 (void) strncpy(x->d86_mnem, "movzld", OPLEN); 4134 #endif 4135 dtrace_get_modrm(x, &mode, ®, &r_m); 4136 dtrace_rex_adjust(rex_prefix, mode, ®, &r_m); 4137 x->d86_opnd_size = SIZE64; 4138 dtrace_get_operand(x, REG_ONLY, reg, LONG_OPND, 1); 4139 x->d86_opnd_size = opnd_size = SIZE32; 4140 wbit = LONG_OPND; 4141 dtrace_get_operand(x, mode, r_m, wbit, 0); 4142 break; 4143 4144 /* 4145 * movsbl movsbw movsbq (0x0FBE) or movswl movswq (0x0FBF) 4146 * movzbl movzbw movzbq (0x0FB6) or movzwl movzwq (0x0FB7) 4147 * wbit lives in 2nd byte, note that operands 4148 * are different sized 4149 */ 4150 case MOVZ: 4151 if (rex_prefix & REX_W) { 4152 /* target register size = 64 bit */ 4153 x->d86_mnem[5] = 'q'; 4154 } 4155 dtrace_get_modrm(x, &mode, ®, &r_m); 4156 dtrace_rex_adjust(rex_prefix, mode, ®, &r_m); 4157 dtrace_get_operand(x, REG_ONLY, reg, LONG_OPND, 1); 4158 x->d86_opnd_size = opnd_size = SIZE16; 4159 wbit = WBIT(opcode5); 4160 dtrace_get_operand(x, mode, r_m, wbit, 0); 4161 break; 4162 case CRC32: 4163 opnd_size = SIZE32; 4164 if (rex_prefix & REX_W) 4165 opnd_size = SIZE64; 4166 x->d86_opnd_size = opnd_size; 4167 4168 dtrace_get_modrm(x, &mode, ®, &r_m); 4169 dtrace_rex_adjust(rex_prefix, mode, ®, &r_m); 4170 dtrace_get_operand(x, REG_ONLY, reg, LONG_OPND, 1); 4171 wbit = WBIT(opcode7); 4172 if (opnd_size_prefix) 4173 x->d86_opnd_size = opnd_size = SIZE16; 4174 dtrace_get_operand(x, mode, r_m, wbit, 0); 4175 break; 4176 case MOVBE: 4177 opnd_size = SIZE32; 4178 if (rex_prefix & REX_W) 4179 opnd_size = SIZE64; 4180 x->d86_opnd_size = opnd_size; 4181 4182 dtrace_get_modrm(x, &mode, ®, &r_m); 4183 dtrace_rex_adjust(rex_prefix, mode, ®, &r_m); 4184 wbit = WBIT(opcode7); 4185 if (opnd_size_prefix) 4186 x->d86_opnd_size = opnd_size = SIZE16; 4187 if (wbit) { 4188 /* reg -> mem */ 4189 dtrace_get_operand(x, REG_ONLY, reg, LONG_OPND, 0); 4190 dtrace_get_operand(x, mode, r_m, wbit, 1); 4191 } else { 4192 /* mem -> reg */ 4193 dtrace_get_operand(x, REG_ONLY, reg, LONG_OPND, 1); 4194 dtrace_get_operand(x, mode, r_m, wbit, 0); 4195 } 4196 break; 4197 4198 /* 4199 * imul instruction, with either 8-bit or longer immediate 4200 * opcode 0x6B for byte, sign-extended displacement, 0x69 for word(s) 4201 */ 4202 case IMUL: 4203 wbit = LONG_OPND; 4204 THREEOPERAND(x, mode, reg, r_m, rex_prefix, wbit, LONG_OPND, 4205 OPSIZE(opnd_size, opcode2 == 0x9), 1); 4206 break; 4207 4208 /* memory or register operand to register, with 'w' bit */ 4209 case MRw: 4210 case ADX: 4211 wbit = WBIT(opcode2); 4212 STANDARD_MODRM(x, mode, reg, r_m, rex_prefix, wbit, 0); 4213 break; 4214 4215 /* register to memory or register operand, with 'w' bit */ 4216 /* arpl happens to fit here also because it is odd */ 4217 case RMw: 4218 if (opcode_bytes == 2) 4219 wbit = WBIT(opcode5); 4220 else 4221 wbit = WBIT(opcode2); 4222 STANDARD_MODRM(x, mode, reg, r_m, rex_prefix, wbit, 1); 4223 break; 4224 4225 /* xaddb instruction */ 4226 case XADDB: 4227 wbit = 0; 4228 STANDARD_MODRM(x, mode, reg, r_m, rex_prefix, wbit, 1); 4229 break; 4230 4231 /* MMX register to memory or register operand */ 4232 case MMS: 4233 case MMOS: 4234 #ifdef DIS_TEXT 4235 wbit = strcmp(dp->it_name, "movd") ? MM_OPND : LONG_OPND; 4236 #else 4237 wbit = LONG_OPND; 4238 #endif 4239 MIXED_MM(x, mode, reg, r_m, rex_prefix, wbit, MM_OPND, 1); 4240 break; 4241 4242 /* MMX register to memory */ 4243 case MMOMS: 4244 dtrace_get_modrm(x, &mode, ®, &r_m); 4245 if (mode == REG_ONLY) 4246 goto error; 4247 wbit = MM_OPND; 4248 MIXED_MM(x, mode, reg, r_m, rex_prefix, wbit, MM_OPND, 1); 4249 break; 4250 4251 /* Double shift. Has immediate operand specifying the shift. */ 4252 case DSHIFT: 4253 wbit = LONG_OPND; 4254 dtrace_get_modrm(x, &mode, ®, &r_m); 4255 dtrace_rex_adjust(rex_prefix, mode, ®, &r_m); 4256 dtrace_get_operand(x, mode, r_m, wbit, 2); 4257 dtrace_get_operand(x, REG_ONLY, reg, LONG_OPND, 1); 4258 dtrace_imm_opnd(x, wbit, 1, 0); 4259 break; 4260 4261 /* 4262 * Double shift. With no immediate operand, specifies using %cl. 4263 */ 4264 case DSHIFTcl: 4265 wbit = LONG_OPND; 4266 STANDARD_MODRM(x, mode, reg, r_m, rex_prefix, wbit, 1); 4267 break; 4268 4269 /* immediate to memory or register operand */ 4270 case IMlw: 4271 wbit = WBIT(opcode2); 4272 dtrace_rex_adjust(rex_prefix, mode, NULL, &r_m); 4273 dtrace_get_operand(x, mode, r_m, wbit, 1); 4274 /* 4275 * Have long immediate for opcode 0x81, but not 0x80 nor 0x83 4276 */ 4277 dtrace_imm_opnd(x, wbit, OPSIZE(opnd_size, opcode2 == 1), 0); 4278 break; 4279 4280 /* immediate to memory or register operand with the */ 4281 /* 'w' bit present */ 4282 case IMw: 4283 wbit = WBIT(opcode2); 4284 dtrace_get_modrm(x, &mode, ®, &r_m); 4285 dtrace_rex_adjust(rex_prefix, mode, NULL, &r_m); 4286 dtrace_get_operand(x, mode, r_m, wbit, 1); 4287 dtrace_imm_opnd(x, wbit, OPSIZE(opnd_size, wbit), 0); 4288 break; 4289 4290 /* immediate to register with register in low 3 bits */ 4291 /* of op code */ 4292 case IR: 4293 /* w-bit here (with regs) is bit 3 */ 4294 wbit = opcode2 >>3 & 0x1; 4295 reg = REGNO(opcode2); 4296 dtrace_rex_adjust(rex_prefix, mode, ®, NULL); 4297 mode = REG_ONLY; 4298 r_m = reg; 4299 dtrace_get_operand(x, mode, r_m, wbit, 1); 4300 dtrace_imm_opnd(x, wbit, OPSIZE64(opnd_size, wbit), 0); 4301 break; 4302 4303 /* MMX immediate shift of register */ 4304 case MMSH: 4305 case MMOSH: 4306 wbit = MM_OPND; 4307 goto mm_shift; /* in next case */ 4308 4309 /* SIMD immediate shift of register */ 4310 case XMMSH: 4311 wbit = XMM_OPND; 4312 mm_shift: 4313 reg = REGNO(opcode7); 4314 dtrace_rex_adjust(rex_prefix, mode, ®, NULL); 4315 dtrace_get_operand(x, REG_ONLY, reg, wbit, 1); 4316 dtrace_imm_opnd(x, wbit, 1, 0); 4317 NOMEM; 4318 break; 4319 4320 /* accumulator to memory operand */ 4321 case AO: 4322 vbit = 1; 4323 /*FALLTHROUGH*/ 4324 4325 /* memory operand to accumulator */ 4326 case OA: 4327 wbit = WBIT(opcode2); 4328 dtrace_get_operand(x, REG_ONLY, EAX_REGNO, wbit, 1 - vbit); 4329 dtrace_imm_opnd(x, wbit, OPSIZE64(addr_size, LONG_OPND), vbit); 4330 #ifdef DIS_TEXT 4331 x->d86_opnd[vbit].d86_mode = MODE_OFFSET; 4332 #endif 4333 break; 4334 4335 4336 /* segment register to memory or register operand */ 4337 case SM: 4338 vbit = 1; 4339 /*FALLTHROUGH*/ 4340 4341 /* memory or register operand to segment register */ 4342 case MS: 4343 dtrace_get_modrm(x, &mode, ®, &r_m); 4344 dtrace_rex_adjust(rex_prefix, mode, NULL, &r_m); 4345 dtrace_get_operand(x, mode, r_m, LONG_OPND, vbit); 4346 dtrace_get_operand(x, REG_ONLY, reg, SEG_OPND, 1 - vbit); 4347 break; 4348 4349 /* 4350 * rotate or shift instructions, which may shift by 1 or 4351 * consult the cl register, depending on the 'v' bit 4352 */ 4353 case Mv: 4354 vbit = VBIT(opcode2); 4355 wbit = WBIT(opcode2); 4356 dtrace_rex_adjust(rex_prefix, mode, NULL, &r_m); 4357 dtrace_get_operand(x, mode, r_m, wbit, 1); 4358 #ifdef DIS_TEXT 4359 if (vbit) { 4360 (void) strlcat(x->d86_opnd[0].d86_opnd, "%cl", OPLEN); 4361 } else { 4362 x->d86_opnd[0].d86_mode = MODE_SIGNED; 4363 x->d86_opnd[0].d86_value_size = 1; 4364 x->d86_opnd[0].d86_value = 1; 4365 } 4366 #endif 4367 break; 4368 /* 4369 * immediate rotate or shift instructions 4370 */ 4371 case MvI: 4372 wbit = WBIT(opcode2); 4373 normal_imm_mem: 4374 dtrace_rex_adjust(rex_prefix, mode, NULL, &r_m); 4375 dtrace_get_operand(x, mode, r_m, wbit, 1); 4376 dtrace_imm_opnd(x, wbit, 1, 0); 4377 break; 4378 4379 /* bit test instructions */ 4380 case MIb: 4381 wbit = LONG_OPND; 4382 goto normal_imm_mem; 4383 4384 /* single memory or register operand with 'w' bit present */ 4385 case Mw: 4386 wbit = WBIT(opcode2); 4387 just_mem: 4388 dtrace_get_modrm(x, &mode, ®, &r_m); 4389 dtrace_rex_adjust(rex_prefix, mode, NULL, &r_m); 4390 dtrace_get_operand(x, mode, r_m, wbit, 0); 4391 break; 4392 4393 case SWAPGS_RDTSCP: 4394 if (cpu_mode == SIZE64 && mode == 3 && r_m == 0) { 4395 #ifdef DIS_TEXT 4396 (void) strncpy(x->d86_mnem, "swapgs", OPLEN); 4397 #endif 4398 NOMEM; 4399 break; 4400 } else if (mode == 3 && r_m == 1) { 4401 #ifdef DIS_TEXT 4402 (void) strncpy(x->d86_mnem, "rdtscp", OPLEN); 4403 #endif 4404 NOMEM; 4405 break; 4406 } 4407 4408 /*FALLTHROUGH*/ 4409 4410 /* prefetch instruction - memory operand, but no memory acess */ 4411 case PREF: 4412 NOMEM; 4413 /*FALLTHROUGH*/ 4414 4415 /* single memory or register operand */ 4416 case M: 4417 case MG9: 4418 wbit = LONG_OPND; 4419 goto just_mem; 4420 4421 /* single memory or register byte operand */ 4422 case Mb: 4423 wbit = BYTE_OPND; 4424 goto just_mem; 4425 4426 case VMx: 4427 if (mode == 3) { 4428 #ifdef DIS_TEXT 4429 char *vminstr; 4430 4431 switch (r_m) { 4432 case 1: 4433 vminstr = "vmcall"; 4434 break; 4435 case 2: 4436 vminstr = "vmlaunch"; 4437 break; 4438 case 3: 4439 vminstr = "vmresume"; 4440 break; 4441 case 4: 4442 vminstr = "vmxoff"; 4443 break; 4444 default: 4445 goto error; 4446 } 4447 4448 (void) strncpy(x->d86_mnem, vminstr, OPLEN); 4449 #else 4450 if (r_m < 1 || r_m > 4) 4451 goto error; 4452 #endif 4453 4454 NOMEM; 4455 break; 4456 } 4457 /*FALLTHROUGH*/ 4458 case SVM: 4459 if (mode == 3) { 4460 #if DIS_TEXT 4461 char *vinstr; 4462 4463 switch (r_m) { 4464 case 0: 4465 vinstr = "vmrun"; 4466 break; 4467 case 1: 4468 vinstr = "vmmcall"; 4469 break; 4470 case 2: 4471 vinstr = "vmload"; 4472 break; 4473 case 3: 4474 vinstr = "vmsave"; 4475 break; 4476 case 4: 4477 vinstr = "stgi"; 4478 break; 4479 case 5: 4480 vinstr = "clgi"; 4481 break; 4482 case 6: 4483 vinstr = "skinit"; 4484 break; 4485 case 7: 4486 vinstr = "invlpga"; 4487 break; 4488 } 4489 4490 (void) strncpy(x->d86_mnem, vinstr, OPLEN); 4491 #endif 4492 NOMEM; 4493 break; 4494 } 4495 /*FALLTHROUGH*/ 4496 case MONITOR_MWAIT: 4497 if (mode == 3) { 4498 if (r_m == 0) { 4499 #ifdef DIS_TEXT 4500 (void) strncpy(x->d86_mnem, "monitor", OPLEN); 4501 #endif 4502 NOMEM; 4503 break; 4504 } else if (r_m == 1) { 4505 #ifdef DIS_TEXT 4506 (void) strncpy(x->d86_mnem, "mwait", OPLEN); 4507 #endif 4508 NOMEM; 4509 break; 4510 } else if (r_m == 2) { 4511 #ifdef DIS_TEXT 4512 (void) strncpy(x->d86_mnem, "clac", OPLEN); 4513 #endif 4514 NOMEM; 4515 break; 4516 } else if (r_m == 3) { 4517 #ifdef DIS_TEXT 4518 (void) strncpy(x->d86_mnem, "stac", OPLEN); 4519 #endif 4520 NOMEM; 4521 break; 4522 } else { 4523 goto error; 4524 } 4525 } 4526 /*FALLTHROUGH*/ 4527 case XGETBV_XSETBV: 4528 if (mode == 3) { 4529 if (r_m == 0) { 4530 #ifdef DIS_TEXT 4531 (void) strncpy(x->d86_mnem, "xgetbv", OPLEN); 4532 #endif 4533 NOMEM; 4534 break; 4535 } else if (r_m == 1) { 4536 #ifdef DIS_TEXT 4537 (void) strncpy(x->d86_mnem, "xsetbv", OPLEN); 4538 #endif 4539 NOMEM; 4540 break; 4541 } else { 4542 goto error; 4543 } 4544 4545 } 4546 /*FALLTHROUGH*/ 4547 case MO: 4548 /* Similar to M, but only memory (no direct registers) */ 4549 wbit = LONG_OPND; 4550 dtrace_get_modrm(x, &mode, ®, &r_m); 4551 if (mode == 3) 4552 goto error; 4553 dtrace_rex_adjust(rex_prefix, mode, NULL, &r_m); 4554 dtrace_get_operand(x, mode, r_m, wbit, 0); 4555 break; 4556 4557 /* move special register to register or reverse if vbit */ 4558 case SREG: 4559 switch (opcode5) { 4560 4561 case 2: 4562 vbit = 1; 4563 /*FALLTHROUGH*/ 4564 case 0: 4565 wbit = CONTROL_OPND; 4566 break; 4567 4568 case 3: 4569 vbit = 1; 4570 /*FALLTHROUGH*/ 4571 case 1: 4572 wbit = DEBUG_OPND; 4573 break; 4574 4575 case 6: 4576 vbit = 1; 4577 /*FALLTHROUGH*/ 4578 case 4: 4579 wbit = TEST_OPND; 4580 break; 4581 4582 } 4583 dtrace_get_modrm(x, &mode, ®, &r_m); 4584 dtrace_rex_adjust(rex_prefix, mode, ®, &r_m); 4585 dtrace_get_operand(x, REG_ONLY, reg, wbit, vbit); 4586 dtrace_get_operand(x, REG_ONLY, r_m, LONG_OPND, 1 - vbit); 4587 NOMEM; 4588 break; 4589 4590 /* 4591 * single register operand with register in the low 3 4592 * bits of op code 4593 */ 4594 case R: 4595 if (opcode_bytes == 2) 4596 reg = REGNO(opcode5); 4597 else 4598 reg = REGNO(opcode2); 4599 dtrace_rex_adjust(rex_prefix, mode, ®, NULL); 4600 dtrace_get_operand(x, REG_ONLY, reg, LONG_OPND, 0); 4601 NOMEM; 4602 break; 4603 4604 /* 4605 * register to accumulator with register in the low 3 4606 * bits of op code, xchg instructions 4607 */ 4608 case RA: 4609 NOMEM; 4610 reg = REGNO(opcode2); 4611 dtrace_rex_adjust(rex_prefix, mode, ®, NULL); 4612 dtrace_get_operand(x, REG_ONLY, reg, LONG_OPND, 0); 4613 dtrace_get_operand(x, REG_ONLY, EAX_REGNO, LONG_OPND, 1); 4614 break; 4615 4616 /* 4617 * single segment register operand, with register in 4618 * bits 3-4 of op code byte 4619 */ 4620 case SEG: 4621 NOMEM; 4622 reg = (x->d86_bytes[x->d86_len - 1] >> 3) & 0x3; 4623 dtrace_get_operand(x, REG_ONLY, reg, SEG_OPND, 0); 4624 break; 4625 4626 /* 4627 * single segment register operand, with register in 4628 * bits 3-5 of op code 4629 */ 4630 case LSEG: 4631 NOMEM; 4632 /* long seg reg from opcode */ 4633 reg = (x->d86_bytes[x->d86_len - 1] >> 3) & 0x7; 4634 dtrace_get_operand(x, REG_ONLY, reg, SEG_OPND, 0); 4635 break; 4636 4637 /* memory or register operand to register */ 4638 case MR: 4639 if (vex_prefetch) 4640 x->d86_got_modrm = 1; 4641 wbit = LONG_OPND; 4642 STANDARD_MODRM(x, mode, reg, r_m, rex_prefix, wbit, 0); 4643 break; 4644 4645 case RM: 4646 case RM_66r: 4647 if (vex_prefetch) 4648 x->d86_got_modrm = 1; 4649 wbit = LONG_OPND; 4650 STANDARD_MODRM(x, mode, reg, r_m, rex_prefix, wbit, 1); 4651 break; 4652 4653 /* MMX/SIMD-Int memory or mm reg to mm reg */ 4654 case MM: 4655 case MMO: 4656 #ifdef DIS_TEXT 4657 wbit = strcmp(dp->it_name, "movd") ? MM_OPND : LONG_OPND; 4658 #else 4659 wbit = LONG_OPND; 4660 #endif 4661 MIXED_MM(x, mode, reg, r_m, rex_prefix, wbit, MM_OPND, 0); 4662 break; 4663 4664 case MMOIMPL: 4665 #ifdef DIS_TEXT 4666 wbit = strcmp(dp->it_name, "movd") ? MM_OPND : LONG_OPND; 4667 #else 4668 wbit = LONG_OPND; 4669 #endif 4670 dtrace_get_modrm(x, &mode, ®, &r_m); 4671 if (mode != REG_ONLY) 4672 goto error; 4673 4674 dtrace_rex_adjust(rex_prefix, mode, ®, &r_m); 4675 dtrace_get_operand(x, mode, r_m, wbit, 0); 4676 dtrace_get_operand(x, REG_ONLY, reg, MM_OPND, 1); 4677 mode = 0; /* change for memory access size... */ 4678 break; 4679 4680 /* MMX/SIMD-Int and SIMD-FP predicated mm reg to r32 */ 4681 case MMO3P: 4682 wbit = MM_OPND; 4683 goto xmm3p; 4684 case XMM3P: 4685 wbit = XMM_OPND; 4686 xmm3p: 4687 dtrace_get_modrm(x, &mode, ®, &r_m); 4688 if (mode != REG_ONLY) 4689 goto error; 4690 4691 THREEOPERAND(x, mode, reg, r_m, rex_prefix, wbit, LONG_OPND, 1, 4692 1); 4693 NOMEM; 4694 break; 4695 4696 case XMM3PM_66r: 4697 THREEOPERAND(x, mode, reg, r_m, rex_prefix, LONG_OPND, XMM_OPND, 4698 1, 0); 4699 break; 4700 4701 /* MMX/SIMD-Int predicated r32/mem to mm reg */ 4702 case MMOPRM: 4703 wbit = LONG_OPND; 4704 w2 = MM_OPND; 4705 goto xmmprm; 4706 case XMMPRM: 4707 case XMMPRM_66r: 4708 wbit = LONG_OPND; 4709 w2 = XMM_OPND; 4710 xmmprm: 4711 THREEOPERAND(x, mode, reg, r_m, rex_prefix, wbit, w2, 1, 1); 4712 break; 4713 4714 /* MMX/SIMD-Int predicated mm/mem to mm reg */ 4715 case MMOPM: 4716 case MMOPM_66o: 4717 wbit = w2 = MM_OPND; 4718 goto xmmprm; 4719 4720 /* MMX/SIMD-Int mm reg to r32 */ 4721 case MMOM3: 4722 NOMEM; 4723 dtrace_get_modrm(x, &mode, ®, &r_m); 4724 if (mode != REG_ONLY) 4725 goto error; 4726 wbit = MM_OPND; 4727 MIXED_MM(x, mode, reg, r_m, rex_prefix, wbit, LONG_OPND, 0); 4728 break; 4729 4730 /* SIMD memory or xmm reg operand to xmm reg */ 4731 case XMM: 4732 case XMM_66o: 4733 case XMM_66r: 4734 case XMMO: 4735 case XMMXIMPL: 4736 wbit = XMM_OPND; 4737 STANDARD_MODRM(x, mode, reg, r_m, rex_prefix, wbit, 0); 4738 4739 if (dp->it_adrmode == XMMXIMPL && mode != REG_ONLY) 4740 goto error; 4741 4742 #ifdef DIS_TEXT 4743 /* 4744 * movlps and movhlps share opcodes. They differ in the 4745 * addressing modes allowed for their operands. 4746 * movhps and movlhps behave similarly. 4747 */ 4748 if (mode == REG_ONLY) { 4749 if (strcmp(dp->it_name, "movlps") == 0) 4750 (void) strncpy(x->d86_mnem, "movhlps", OPLEN); 4751 else if (strcmp(dp->it_name, "movhps") == 0) 4752 (void) strncpy(x->d86_mnem, "movlhps", OPLEN); 4753 } 4754 #endif 4755 if (dp->it_adrmode == XMMXIMPL) 4756 mode = 0; /* change for memory access size... */ 4757 break; 4758 4759 /* SIMD xmm reg to memory or xmm reg */ 4760 case XMMS: 4761 case XMMOS: 4762 case XMMMS: 4763 case XMMOMS: 4764 dtrace_get_modrm(x, &mode, ®, &r_m); 4765 #ifdef DIS_TEXT 4766 if ((strcmp(dp->it_name, "movlps") == 0 || 4767 strcmp(dp->it_name, "movhps") == 0 || 4768 strcmp(dp->it_name, "movntps") == 0) && 4769 mode == REG_ONLY) 4770 goto error; 4771 #endif 4772 wbit = XMM_OPND; 4773 MIXED_MM(x, mode, reg, r_m, rex_prefix, wbit, XMM_OPND, 1); 4774 break; 4775 4776 /* SIMD memory to xmm reg */ 4777 case XMMM: 4778 case XMMM_66r: 4779 case XMMOM: 4780 wbit = XMM_OPND; 4781 dtrace_get_modrm(x, &mode, ®, &r_m); 4782 #ifdef DIS_TEXT 4783 if (mode == REG_ONLY) { 4784 if (strcmp(dp->it_name, "movhps") == 0) 4785 (void) strncpy(x->d86_mnem, "movlhps", OPLEN); 4786 else 4787 goto error; 4788 } 4789 #endif 4790 MIXED_MM(x, mode, reg, r_m, rex_prefix, wbit, XMM_OPND, 0); 4791 break; 4792 4793 /* SIMD memory or r32 to xmm reg */ 4794 case XMM3MX: 4795 wbit = LONG_OPND; 4796 MIXED_MM(x, mode, reg, r_m, rex_prefix, wbit, XMM_OPND, 0); 4797 break; 4798 4799 case XMM3MXS: 4800 wbit = LONG_OPND; 4801 MIXED_MM(x, mode, reg, r_m, rex_prefix, wbit, XMM_OPND, 1); 4802 break; 4803 4804 /* SIMD memory or mm reg to xmm reg */ 4805 case XMMOMX: 4806 /* SIMD mm to xmm */ 4807 case XMMMX: 4808 wbit = MM_OPND; 4809 MIXED_MM(x, mode, reg, r_m, rex_prefix, wbit, XMM_OPND, 0); 4810 break; 4811 4812 /* SIMD memory or xmm reg to mm reg */ 4813 case XMMXMM: 4814 case XMMOXMM: 4815 case XMMXM: 4816 wbit = XMM_OPND; 4817 MIXED_MM(x, mode, reg, r_m, rex_prefix, wbit, MM_OPND, 0); 4818 break; 4819 4820 4821 /* SIMD memory or xmm reg to r32 */ 4822 case XMMXM3: 4823 wbit = XMM_OPND; 4824 MIXED_MM(x, mode, reg, r_m, rex_prefix, wbit, LONG_OPND, 0); 4825 break; 4826 4827 /* SIMD xmm to r32 */ 4828 case XMMX3: 4829 case XMMOX3: 4830 dtrace_get_modrm(x, &mode, ®, &r_m); 4831 if (mode != REG_ONLY) 4832 goto error; 4833 dtrace_rex_adjust(rex_prefix, mode, ®, &r_m); 4834 dtrace_get_operand(x, mode, r_m, XMM_OPND, 0); 4835 dtrace_get_operand(x, REG_ONLY, reg, LONG_OPND, 1); 4836 NOMEM; 4837 break; 4838 4839 /* SIMD predicated memory or xmm reg with/to xmm reg */ 4840 case XMMP: 4841 case XMMP_66r: 4842 case XMMP_66o: 4843 case XMMOPM: 4844 wbit = XMM_OPND; 4845 THREEOPERAND(x, mode, reg, r_m, rex_prefix, wbit, XMM_OPND, 1, 4846 1); 4847 4848 #ifdef DIS_TEXT 4849 /* 4850 * cmpps and cmpss vary their instruction name based 4851 * on the value of imm8. Other XMMP instructions, 4852 * such as shufps, require explicit specification of 4853 * the predicate. 4854 */ 4855 if (dp->it_name[0] == 'c' && 4856 dp->it_name[1] == 'm' && 4857 dp->it_name[2] == 'p' && 4858 strlen(dp->it_name) == 5) { 4859 uchar_t pred = x->d86_opnd[0].d86_value & 0xff; 4860 4861 if (pred >= (sizeof (dis_PREDSUFFIX) / sizeof (char *))) 4862 goto error; 4863 4864 (void) strncpy(x->d86_mnem, "cmp", OPLEN); 4865 (void) strlcat(x->d86_mnem, dis_PREDSUFFIX[pred], 4866 OPLEN); 4867 (void) strlcat(x->d86_mnem, 4868 dp->it_name + strlen(dp->it_name) - 2, 4869 OPLEN); 4870 x->d86_opnd[0] = x->d86_opnd[1]; 4871 x->d86_opnd[1] = x->d86_opnd[2]; 4872 x->d86_numopnds = 2; 4873 } 4874 4875 /* 4876 * The pclmulqdq instruction has a series of alternate names for 4877 * various encodings of the immediate byte. As such, if we 4878 * happen to find it and the immediate value matches, we'll 4879 * rewrite the mnemonic. 4880 */ 4881 if (strcmp(dp->it_name, "pclmulqdq") == 0) { 4882 boolean_t changed = B_TRUE; 4883 switch (x->d86_opnd[0].d86_value) { 4884 case 0x00: 4885 (void) strncpy(x->d86_mnem, "pclmullqlqdq", 4886 OPLEN); 4887 break; 4888 case 0x01: 4889 (void) strncpy(x->d86_mnem, "pclmulhqlqdq", 4890 OPLEN); 4891 break; 4892 case 0x10: 4893 (void) strncpy(x->d86_mnem, "pclmullqhqdq", 4894 OPLEN); 4895 break; 4896 case 0x11: 4897 (void) strncpy(x->d86_mnem, "pclmulhqhqdq", 4898 OPLEN); 4899 break; 4900 default: 4901 changed = B_FALSE; 4902 break; 4903 } 4904 4905 if (changed == B_TRUE) { 4906 x->d86_opnd[0].d86_value_size = 0; 4907 x->d86_opnd[0] = x->d86_opnd[1]; 4908 x->d86_opnd[1] = x->d86_opnd[2]; 4909 x->d86_numopnds = 2; 4910 } 4911 } 4912 #endif 4913 break; 4914 4915 case XMMX2I: 4916 FOUROPERAND(x, mode, reg, r_m, rex_prefix, XMM_OPND, XMM_OPND, 4917 1); 4918 NOMEM; 4919 break; 4920 4921 case XMM2I: 4922 ONEOPERAND_TWOIMM(x, mode, reg, r_m, rex_prefix, XMM_OPND, 1); 4923 NOMEM; 4924 break; 4925 4926 /* immediate operand to accumulator */ 4927 case IA: 4928 wbit = WBIT(opcode2); 4929 dtrace_get_operand(x, REG_ONLY, EAX_REGNO, wbit, 1); 4930 dtrace_imm_opnd(x, wbit, OPSIZE(opnd_size, wbit), 0); 4931 NOMEM; 4932 break; 4933 4934 /* memory or register operand to accumulator */ 4935 case MA: 4936 wbit = WBIT(opcode2); 4937 dtrace_rex_adjust(rex_prefix, mode, NULL, &r_m); 4938 dtrace_get_operand(x, mode, r_m, wbit, 0); 4939 break; 4940 4941 /* si register to di register used to reference memory */ 4942 case SD: 4943 #ifdef DIS_TEXT 4944 dtrace_check_override(x, 0); 4945 x->d86_numopnds = 2; 4946 if (addr_size == SIZE64) { 4947 (void) strlcat(x->d86_opnd[0].d86_opnd, "(%rsi)", 4948 OPLEN); 4949 (void) strlcat(x->d86_opnd[1].d86_opnd, "(%rdi)", 4950 OPLEN); 4951 } else if (addr_size == SIZE32) { 4952 (void) strlcat(x->d86_opnd[0].d86_opnd, "(%esi)", 4953 OPLEN); 4954 (void) strlcat(x->d86_opnd[1].d86_opnd, "(%edi)", 4955 OPLEN); 4956 } else { 4957 (void) strlcat(x->d86_opnd[0].d86_opnd, "(%si)", 4958 OPLEN); 4959 (void) strlcat(x->d86_opnd[1].d86_opnd, "(%di)", 4960 OPLEN); 4961 } 4962 #endif 4963 wbit = LONG_OPND; 4964 break; 4965 4966 /* accumulator to di register */ 4967 case AD: 4968 wbit = WBIT(opcode2); 4969 #ifdef DIS_TEXT 4970 dtrace_check_override(x, 1); 4971 x->d86_numopnds = 2; 4972 dtrace_get_operand(x, REG_ONLY, EAX_REGNO, wbit, 0); 4973 if (addr_size == SIZE64) 4974 (void) strlcat(x->d86_opnd[1].d86_opnd, "(%rdi)", 4975 OPLEN); 4976 else if (addr_size == SIZE32) 4977 (void) strlcat(x->d86_opnd[1].d86_opnd, "(%edi)", 4978 OPLEN); 4979 else 4980 (void) strlcat(x->d86_opnd[1].d86_opnd, "(%di)", 4981 OPLEN); 4982 #endif 4983 break; 4984 4985 /* si register to accumulator */ 4986 case SA: 4987 wbit = WBIT(opcode2); 4988 #ifdef DIS_TEXT 4989 dtrace_check_override(x, 0); 4990 x->d86_numopnds = 2; 4991 if (addr_size == SIZE64) 4992 (void) strlcat(x->d86_opnd[0].d86_opnd, "(%rsi)", 4993 OPLEN); 4994 else if (addr_size == SIZE32) 4995 (void) strlcat(x->d86_opnd[0].d86_opnd, "(%esi)", 4996 OPLEN); 4997 else 4998 (void) strlcat(x->d86_opnd[0].d86_opnd, "(%si)", 4999 OPLEN); 5000 dtrace_get_operand(x, REG_ONLY, EAX_REGNO, wbit, 1); 5001 #endif 5002 break; 5003 5004 /* 5005 * single operand, a 16/32 bit displacement 5006 */ 5007 case D: 5008 wbit = LONG_OPND; 5009 dtrace_disp_opnd(x, wbit, OPSIZE(opnd_size, LONG_OPND), 0); 5010 NOMEM; 5011 break; 5012 5013 /* jmp/call indirect to memory or register operand */ 5014 case INM: 5015 #ifdef DIS_TEXT 5016 (void) strlcat(x->d86_opnd[0].d86_prefix, "*", OPLEN); 5017 #endif 5018 dtrace_rex_adjust(rex_prefix, mode, NULL, &r_m); 5019 dtrace_get_operand(x, mode, r_m, LONG_OPND, 0); 5020 wbit = LONG_OPND; 5021 break; 5022 5023 /* 5024 * for long jumps and long calls -- a new code segment 5025 * register and an offset in IP -- stored in object 5026 * code in reverse order. Note - not valid in amd64 5027 */ 5028 case SO: 5029 dtrace_check_override(x, 1); 5030 wbit = LONG_OPND; 5031 dtrace_imm_opnd(x, wbit, OPSIZE(opnd_size, LONG_OPND), 1); 5032 #ifdef DIS_TEXT 5033 x->d86_opnd[1].d86_mode = MODE_SIGNED; 5034 #endif 5035 /* will now get segment operand */ 5036 dtrace_imm_opnd(x, wbit, 2, 0); 5037 break; 5038 5039 /* 5040 * jmp/call. single operand, 8 bit displacement. 5041 * added to current EIP in 'compofff' 5042 */ 5043 case BD: 5044 dtrace_disp_opnd(x, BYTE_OPND, 1, 0); 5045 NOMEM; 5046 break; 5047 5048 /* single 32/16 bit immediate operand */ 5049 case I: 5050 wbit = LONG_OPND; 5051 dtrace_imm_opnd(x, wbit, OPSIZE(opnd_size, LONG_OPND), 0); 5052 break; 5053 5054 /* single 8 bit immediate operand */ 5055 case Ib: 5056 wbit = LONG_OPND; 5057 dtrace_imm_opnd(x, wbit, 1, 0); 5058 break; 5059 5060 case ENTER: 5061 wbit = LONG_OPND; 5062 dtrace_imm_opnd(x, wbit, 2, 0); 5063 dtrace_imm_opnd(x, wbit, 1, 1); 5064 switch (opnd_size) { 5065 case SIZE64: 5066 x->d86_memsize = (x->d86_opnd[1].d86_value + 1) * 8; 5067 break; 5068 case SIZE32: 5069 x->d86_memsize = (x->d86_opnd[1].d86_value + 1) * 4; 5070 break; 5071 case SIZE16: 5072 x->d86_memsize = (x->d86_opnd[1].d86_value + 1) * 2; 5073 break; 5074 } 5075 5076 break; 5077 5078 /* 16-bit immediate operand */ 5079 case RET: 5080 wbit = LONG_OPND; 5081 dtrace_imm_opnd(x, wbit, 2, 0); 5082 break; 5083 5084 /* single 8 bit port operand */ 5085 case P: 5086 dtrace_check_override(x, 0); 5087 dtrace_imm_opnd(x, BYTE_OPND, 1, 0); 5088 NOMEM; 5089 break; 5090 5091 /* single operand, dx register (variable port instruction) */ 5092 case V: 5093 x->d86_numopnds = 1; 5094 dtrace_check_override(x, 0); 5095 #ifdef DIS_TEXT 5096 (void) strlcat(x->d86_opnd[0].d86_opnd, "(%dx)", OPLEN); 5097 #endif 5098 NOMEM; 5099 break; 5100 5101 /* 5102 * The int instruction, which has two forms: 5103 * int 3 (breakpoint) or 5104 * int n, where n is indicated in the subsequent 5105 * byte (format Ib). The int 3 instruction (opcode 0xCC), 5106 * where, although the 3 looks like an operand, 5107 * it is implied by the opcode. It must be converted 5108 * to the correct base and output. 5109 */ 5110 case INT3: 5111 #ifdef DIS_TEXT 5112 x->d86_numopnds = 1; 5113 x->d86_opnd[0].d86_mode = MODE_SIGNED; 5114 x->d86_opnd[0].d86_value_size = 1; 5115 x->d86_opnd[0].d86_value = 3; 5116 #endif 5117 NOMEM; 5118 break; 5119 5120 /* single 8 bit immediate operand */ 5121 case INTx: 5122 dtrace_imm_opnd(x, BYTE_OPND, 1, 0); 5123 NOMEM; 5124 break; 5125 5126 /* an unused byte must be discarded */ 5127 case U: 5128 if (x->d86_get_byte(x->d86_data) < 0) 5129 goto error; 5130 x->d86_len++; 5131 NOMEM; 5132 break; 5133 5134 case CBW: 5135 #ifdef DIS_TEXT 5136 if (opnd_size == SIZE16) 5137 (void) strlcat(x->d86_mnem, "cbtw", OPLEN); 5138 else if (opnd_size == SIZE32) 5139 (void) strlcat(x->d86_mnem, "cwtl", OPLEN); 5140 else 5141 (void) strlcat(x->d86_mnem, "cltq", OPLEN); 5142 #endif 5143 wbit = LONG_OPND; 5144 NOMEM; 5145 break; 5146 5147 case CWD: 5148 #ifdef DIS_TEXT 5149 if (opnd_size == SIZE16) 5150 (void) strlcat(x->d86_mnem, "cwtd", OPLEN); 5151 else if (opnd_size == SIZE32) 5152 (void) strlcat(x->d86_mnem, "cltd", OPLEN); 5153 else 5154 (void) strlcat(x->d86_mnem, "cqtd", OPLEN); 5155 #endif 5156 wbit = LONG_OPND; 5157 NOMEM; 5158 break; 5159 5160 case XMMSFNC: 5161 /* 5162 * sfence is sfence if mode is REG_ONLY. If mode isn't 5163 * REG_ONLY, mnemonic should be 'clflush'. 5164 */ 5165 dtrace_get_modrm(x, &mode, ®, &r_m); 5166 5167 /* sfence doesn't take operands */ 5168 #ifdef DIS_TEXT 5169 if (mode == REG_ONLY) { 5170 (void) strlcat(x->d86_mnem, "sfence", OPLEN); 5171 } else { 5172 (void) strlcat(x->d86_mnem, "clflush", OPLEN); 5173 dtrace_rex_adjust(rex_prefix, mode, ®, &r_m); 5174 dtrace_get_operand(x, mode, r_m, BYTE_OPND, 0); 5175 NOMEM; 5176 } 5177 #else 5178 if (mode != REG_ONLY) { 5179 dtrace_rex_adjust(rex_prefix, mode, ®, &r_m); 5180 dtrace_get_operand(x, mode, r_m, LONG_OPND, 0); 5181 NOMEM; 5182 } 5183 #endif 5184 break; 5185 5186 /* 5187 * no disassembly, the mnemonic was all there was so go on 5188 */ 5189 case NORM: 5190 if (dp->it_invalid32 && cpu_mode != SIZE64) 5191 goto error; 5192 NOMEM; 5193 /*FALLTHROUGH*/ 5194 case IMPLMEM: 5195 break; 5196 5197 case XMMFENCE: 5198 /* 5199 * XRSTOR, XSAVEOPT and LFENCE share the same opcode but 5200 * differ in mode and reg. 5201 */ 5202 dtrace_get_modrm(x, &mode, ®, &r_m); 5203 5204 if (mode == REG_ONLY) { 5205 /* 5206 * Only the following exact byte sequences are allowed: 5207 * 5208 * 0f ae e8 lfence 5209 * 0f ae f0 mfence 5210 */ 5211 if ((uint8_t)x->d86_bytes[x->d86_len - 1] != 0xe8 && 5212 (uint8_t)x->d86_bytes[x->d86_len - 1] != 0xf0) 5213 goto error; 5214 } else { 5215 #ifdef DIS_TEXT 5216 if (reg == 5) { 5217 (void) strncpy(x->d86_mnem, "xrstor", OPLEN); 5218 } else if (reg == 6) { 5219 (void) strncpy(x->d86_mnem, "xsaveopt", OPLEN); 5220 } else { 5221 goto error; 5222 } 5223 #endif 5224 dtrace_rex_adjust(rex_prefix, mode, ®, &r_m); 5225 dtrace_get_operand(x, mode, r_m, BYTE_OPND, 0); 5226 } 5227 break; 5228 5229 /* float reg */ 5230 case F: 5231 #ifdef DIS_TEXT 5232 x->d86_numopnds = 1; 5233 (void) strlcat(x->d86_opnd[0].d86_opnd, "%st(X)", OPLEN); 5234 x->d86_opnd[0].d86_opnd[4] = r_m + '0'; 5235 #endif 5236 NOMEM; 5237 break; 5238 5239 /* float reg to float reg, with ret bit present */ 5240 case FF: 5241 vbit = opcode2 >> 2 & 0x1; /* vbit = 1: st -> st(i) */ 5242 /*FALLTHROUGH*/ 5243 case FFC: /* case for vbit always = 0 */ 5244 #ifdef DIS_TEXT 5245 x->d86_numopnds = 2; 5246 (void) strlcat(x->d86_opnd[1 - vbit].d86_opnd, "%st", OPLEN); 5247 (void) strlcat(x->d86_opnd[vbit].d86_opnd, "%st(X)", OPLEN); 5248 x->d86_opnd[vbit].d86_opnd[4] = r_m + '0'; 5249 #endif 5250 NOMEM; 5251 break; 5252 5253 /* AVX instructions */ 5254 case VEX_MO: 5255 /* op(ModR/M.r/m) */ 5256 x->d86_numopnds = 1; 5257 dtrace_get_modrm(x, &mode, ®, &r_m); 5258 #ifdef DIS_TEXT 5259 if ((dp == &dis_opAVX0F[0xA][0xE]) && (reg == 3)) 5260 (void) strncpy(x->d86_mnem, "vstmxcsr", OPLEN); 5261 #endif 5262 dtrace_vex_adjust(vex_byte1, mode, ®, &r_m); 5263 dtrace_get_operand(x, mode, r_m, wbit, 0); 5264 break; 5265 case VEX_RMrX: 5266 case FMA: 5267 /* ModR/M.reg := op(VEX.vvvv, ModR/M.r/m) */ 5268 x->d86_numopnds = 3; 5269 dtrace_get_modrm(x, &mode, ®, &r_m); 5270 dtrace_vex_adjust(vex_byte1, mode, ®, &r_m); 5271 5272 /* 5273 * In classic Intel fashion, the opcodes for all of the FMA 5274 * instructions all have two possible mnemonics which vary by 5275 * one letter, which is selected based on the value of the wbit. 5276 * When wbit is one, they have the 'd' suffix and when 'wbit' is 5277 * 0, they have the 's' suffix. Otherwise, the FMA instructions 5278 * are all a standard VEX_RMrX. 5279 */ 5280 #ifdef DIS_TEXT 5281 if (dp->it_adrmode == FMA) { 5282 size_t len = strlen(dp->it_name); 5283 (void) strncpy(x->d86_mnem, dp->it_name, OPLEN); 5284 if (len + 1 < OPLEN) { 5285 (void) strncpy(x->d86_mnem + len, 5286 vex_W != 0 ? "d" : "s", OPLEN - len); 5287 } 5288 } 5289 #endif 5290 5291 if (mode != REG_ONLY) { 5292 if ((dp == &dis_opAVXF20F[0x10]) || 5293 (dp == &dis_opAVXF30F[0x10])) { 5294 /* vmovsd <m64>, <xmm> */ 5295 /* or vmovss <m64>, <xmm> */ 5296 x->d86_numopnds = 2; 5297 goto L_VEX_MX; 5298 } 5299 } 5300 5301 dtrace_get_operand(x, REG_ONLY, reg, wbit, 2); 5302 /* 5303 * VEX prefix uses the 1's complement form to encode the 5304 * XMM/YMM regs 5305 */ 5306 dtrace_get_operand(x, REG_ONLY, (0xF - vex_v), wbit, 1); 5307 5308 if ((dp == &dis_opAVXF20F[0x2A]) || 5309 (dp == &dis_opAVXF30F[0x2A])) { 5310 /* 5311 * vcvtsi2si </r,m>, <xmm>, <xmm> or vcvtsi2ss </r,m>, 5312 * <xmm>, <xmm> 5313 */ 5314 wbit = LONG_OPND; 5315 } 5316 #ifdef DIS_TEXT 5317 else if ((mode == REG_ONLY) && 5318 (dp == &dis_opAVX0F[0x1][0x6])) { /* vmovlhps */ 5319 (void) strncpy(x->d86_mnem, "vmovlhps", OPLEN); 5320 } else if ((mode == REG_ONLY) && 5321 (dp == &dis_opAVX0F[0x1][0x2])) { /* vmovhlps */ 5322 (void) strncpy(x->d86_mnem, "vmovhlps", OPLEN); 5323 } 5324 #endif 5325 dtrace_get_operand(x, mode, r_m, wbit, 0); 5326 5327 break; 5328 5329 case VEX_VRMrX: 5330 /* ModR/M.reg := op(MODR/M.r/m, VEX.vvvv) */ 5331 x->d86_numopnds = 3; 5332 dtrace_get_modrm(x, &mode, ®, &r_m); 5333 dtrace_vex_adjust(vex_byte1, mode, ®, &r_m); 5334 5335 dtrace_get_operand(x, REG_ONLY, reg, wbit, 2); 5336 /* 5337 * VEX prefix uses the 1's complement form to encode the 5338 * XMM/YMM regs 5339 */ 5340 dtrace_get_operand(x, REG_ONLY, (0xF - vex_v), wbit, 0); 5341 5342 dtrace_get_operand(x, mode, r_m, wbit, 1); 5343 break; 5344 5345 case VEX_SbVM: 5346 /* ModR/M.reg := op(MODR/M.r/m, VSIB, VEX.vvvv) */ 5347 x->d86_numopnds = 3; 5348 x->d86_vsib = 1; 5349 5350 /* 5351 * All instructions that use VSIB are currently a mess. See the 5352 * comment around the dis_gather_regs_t structure definition. 5353 */ 5354 5355 vreg = &dis_vgather[opcode2][vex_W][vex_L]; 5356 5357 #ifdef DIS_TEXT 5358 (void) strncpy(x->d86_mnem, dp->it_name, OPLEN); 5359 (void) strlcat(x->d86_mnem + strlen(dp->it_name), 5360 vreg->dgr_suffix, OPLEN - strlen(dp->it_name)); 5361 #endif 5362 5363 dtrace_get_modrm(x, &mode, ®, &r_m); 5364 dtrace_vex_adjust(vex_byte1, mode, ®, &r_m); 5365 5366 dtrace_get_operand(x, REG_ONLY, reg, vreg->dgr_arg2, 2); 5367 /* 5368 * VEX prefix uses the 1's complement form to encode the 5369 * XMM/YMM regs 5370 */ 5371 dtrace_get_operand(x, REG_ONLY, (0xF - vex_v), vreg->dgr_arg0, 5372 0); 5373 dtrace_get_operand(x, mode, r_m, vreg->dgr_arg1, 1); 5374 break; 5375 5376 case VEX_RRX: 5377 /* ModR/M.rm := op(VEX.vvvv, ModR/M.reg) */ 5378 x->d86_numopnds = 3; 5379 5380 dtrace_get_modrm(x, &mode, ®, &r_m); 5381 dtrace_vex_adjust(vex_byte1, mode, ®, &r_m); 5382 5383 if (mode != REG_ONLY) { 5384 if ((dp == &dis_opAVXF20F[0x11]) || 5385 (dp == &dis_opAVXF30F[0x11])) { 5386 /* vmovsd <xmm>, <m64> */ 5387 /* or vmovss <xmm>, <m64> */ 5388 x->d86_numopnds = 2; 5389 goto L_VEX_RM; 5390 } 5391 } 5392 5393 dtrace_get_operand(x, mode, r_m, wbit, 2); 5394 dtrace_get_operand(x, REG_ONLY, (0xF - vex_v), wbit, 1); 5395 dtrace_get_operand(x, REG_ONLY, reg, wbit, 0); 5396 break; 5397 5398 case VEX_RMRX: 5399 /* ModR/M.reg := op(VEX.vvvv, ModR/M.r_m, imm8[7:4]) */ 5400 x->d86_numopnds = 4; 5401 5402 dtrace_get_modrm(x, &mode, ®, &r_m); 5403 dtrace_vex_adjust(vex_byte1, mode, ®, &r_m); 5404 dtrace_get_operand(x, REG_ONLY, reg, wbit, 3); 5405 dtrace_get_operand(x, REG_ONLY, (0xF - vex_v), wbit, 2); 5406 if (dp == &dis_opAVX660F3A[0x18]) { 5407 /* vinsertf128 <imm8>, <xmm>, <ymm>, <ymm> */ 5408 dtrace_get_operand(x, mode, r_m, XMM_OPND, 1); 5409 } else if ((dp == &dis_opAVX660F3A[0x20]) || 5410 (dp == & dis_opAVX660F[0xC4])) { 5411 /* vpinsrb <imm8>, <reg/mm>, <xmm>, <xmm> */ 5412 /* or vpinsrw <imm8>, <reg/mm>, <xmm>, <xmm> */ 5413 dtrace_get_operand(x, mode, r_m, LONG_OPND, 1); 5414 } else if (dp == &dis_opAVX660F3A[0x22]) { 5415 /* vpinsrd/q <imm8>, <reg/mm>, <xmm>, <xmm> */ 5416 #ifdef DIS_TEXT 5417 if (vex_W) 5418 x->d86_mnem[6] = 'q'; 5419 #endif 5420 dtrace_get_operand(x, mode, r_m, LONG_OPND, 1); 5421 } else { 5422 dtrace_get_operand(x, mode, r_m, wbit, 1); 5423 } 5424 5425 /* one byte immediate number */ 5426 dtrace_imm_opnd(x, wbit, 1, 0); 5427 5428 /* vblendvpd, vblendvps, vblendvb use the imm encode the regs */ 5429 if ((dp == &dis_opAVX660F3A[0x4A]) || 5430 (dp == &dis_opAVX660F3A[0x4B]) || 5431 (dp == &dis_opAVX660F3A[0x4C])) { 5432 #ifdef DIS_TEXT 5433 int regnum = (x->d86_opnd[0].d86_value & 0xF0) >> 4; 5434 #endif 5435 x->d86_opnd[0].d86_mode = MODE_NONE; 5436 #ifdef DIS_TEXT 5437 if (vex_L) 5438 (void) strncpy(x->d86_opnd[0].d86_opnd, 5439 dis_YMMREG[regnum], OPLEN); 5440 else 5441 (void) strncpy(x->d86_opnd[0].d86_opnd, 5442 dis_XMMREG[regnum], OPLEN); 5443 #endif 5444 } 5445 break; 5446 5447 case VEX_MX: 5448 /* ModR/M.reg := op(ModR/M.rm) */ 5449 x->d86_numopnds = 2; 5450 5451 dtrace_get_modrm(x, &mode, ®, &r_m); 5452 dtrace_vex_adjust(vex_byte1, mode, ®, &r_m); 5453 L_VEX_MX: 5454 5455 if ((dp == &dis_opAVXF20F[0xE6]) || 5456 (dp == &dis_opAVX660F[0x5A]) || 5457 (dp == &dis_opAVX660F[0xE6])) { 5458 /* vcvtpd2dq <ymm>, <xmm> */ 5459 /* or vcvtpd2ps <ymm>, <xmm> */ 5460 /* or vcvttpd2dq <ymm>, <xmm> */ 5461 dtrace_get_operand(x, REG_ONLY, reg, XMM_OPND, 1); 5462 dtrace_get_operand(x, mode, r_m, wbit, 0); 5463 } else if ((dp == &dis_opAVXF30F[0xE6]) || 5464 (dp == &dis_opAVX0F[0x5][0xA]) || 5465 (dp == &dis_opAVX660F38[0x13]) || 5466 (dp == &dis_opAVX660F38[0x18]) || 5467 (dp == &dis_opAVX660F38[0x19]) || 5468 (dp == &dis_opAVX660F38[0x58]) || 5469 (dp == &dis_opAVX660F38[0x78]) || 5470 (dp == &dis_opAVX660F38[0x79]) || 5471 (dp == &dis_opAVX660F38[0x59])) { 5472 /* vcvtdq2pd <xmm>, <ymm> */ 5473 /* or vcvtps2pd <xmm>, <ymm> */ 5474 /* or vcvtph2ps <xmm>, <ymm> */ 5475 /* or vbroadcasts* <xmm>, <ymm> */ 5476 dtrace_get_operand(x, REG_ONLY, reg, wbit, 1); 5477 dtrace_get_operand(x, mode, r_m, XMM_OPND, 0); 5478 } else if (dp == &dis_opAVX660F[0x6E]) { 5479 /* vmovd/q <reg/mem 32/64>, <xmm> */ 5480 #ifdef DIS_TEXT 5481 if (vex_W) 5482 x->d86_mnem[4] = 'q'; 5483 #endif 5484 dtrace_get_operand(x, REG_ONLY, reg, wbit, 1); 5485 dtrace_get_operand(x, mode, r_m, LONG_OPND, 0); 5486 } else { 5487 dtrace_get_operand(x, REG_ONLY, reg, wbit, 1); 5488 dtrace_get_operand(x, mode, r_m, wbit, 0); 5489 } 5490 5491 break; 5492 5493 case VEX_MXI: 5494 /* ModR/M.reg := op(ModR/M.rm, imm8) */ 5495 x->d86_numopnds = 3; 5496 5497 dtrace_get_modrm(x, &mode, ®, &r_m); 5498 dtrace_vex_adjust(vex_byte1, mode, ®, &r_m); 5499 5500 dtrace_get_operand(x, REG_ONLY, reg, wbit, 2); 5501 dtrace_get_operand(x, mode, r_m, wbit, 1); 5502 5503 /* one byte immediate number */ 5504 dtrace_imm_opnd(x, wbit, 1, 0); 5505 break; 5506 5507 case VEX_XXI: 5508 /* VEX.vvvv := op(ModR/M.rm, imm8) */ 5509 x->d86_numopnds = 3; 5510 5511 dtrace_get_modrm(x, &mode, ®, &r_m); 5512 #ifdef DIS_TEXT 5513 (void) strncpy(x->d86_mnem, dis_AVXvgrp7[opcode2 - 1][reg], 5514 OPLEN); 5515 #endif 5516 dtrace_vex_adjust(vex_byte1, mode, ®, &r_m); 5517 5518 dtrace_get_operand(x, REG_ONLY, (0xF - vex_v), wbit, 2); 5519 dtrace_get_operand(x, REG_ONLY, r_m, wbit, 1); 5520 5521 /* one byte immediate number */ 5522 dtrace_imm_opnd(x, wbit, 1, 0); 5523 break; 5524 5525 case VEX_MR: 5526 /* ModR/M.reg (reg32/64) := op(ModR/M.rm) */ 5527 if (dp == &dis_opAVX660F[0xC5]) { 5528 /* vpextrw <imm8>, <xmm>, <reg> */ 5529 x->d86_numopnds = 2; 5530 vbit = 2; 5531 } else { 5532 x->d86_numopnds = 2; 5533 vbit = 1; 5534 } 5535 5536 dtrace_get_modrm(x, &mode, ®, &r_m); 5537 dtrace_vex_adjust(vex_byte1, mode, ®, &r_m); 5538 dtrace_get_operand(x, REG_ONLY, reg, LONG_OPND, vbit); 5539 dtrace_get_operand(x, mode, r_m, wbit, vbit - 1); 5540 5541 if (vbit == 2) 5542 dtrace_imm_opnd(x, wbit, 1, 0); 5543 5544 break; 5545 5546 case VEX_KMR: 5547 /* opmask: mod_rm := %k */ 5548 x->d86_numopnds = 2; 5549 dtrace_get_modrm(x, &mode, ®, &r_m); 5550 dtrace_vex_adjust(vex_byte1, mode, ®, &r_m); 5551 dtrace_get_operand(x, mode, r_m, LONG_OPND, 1); 5552 dtrace_get_operand(x, REG_ONLY, reg, wbit, 0); 5553 break; 5554 5555 case VEX_KRM: 5556 /* opmask: mod_reg := mod_rm */ 5557 x->d86_numopnds = 2; 5558 dtrace_get_modrm(x, &mode, ®, &r_m); 5559 dtrace_vex_adjust(vex_byte1, mode, ®, &r_m); 5560 dtrace_get_operand(x, REG_ONLY, reg, wbit, 1); 5561 if (mode == REG_ONLY) { 5562 dtrace_get_operand(x, mode, r_m, KOPMASK_OPND, 0); 5563 } else { 5564 dtrace_get_operand(x, mode, r_m, LONG_OPND, 0); 5565 } 5566 break; 5567 5568 case VEX_KRR: 5569 /* opmask: mod_reg := mod_rm */ 5570 x->d86_numopnds = 2; 5571 dtrace_get_modrm(x, &mode, ®, &r_m); 5572 dtrace_vex_adjust(vex_byte1, mode, ®, &r_m); 5573 dtrace_get_operand(x, mode, reg, wbit, 1); 5574 dtrace_get_operand(x, REG_ONLY, r_m, LONG_OPND, 0); 5575 break; 5576 5577 case VEX_RRI: 5578 /* implicit(eflags/r32) := op(ModR/M.reg, ModR/M.rm) */ 5579 x->d86_numopnds = 2; 5580 5581 dtrace_get_modrm(x, &mode, ®, &r_m); 5582 dtrace_vex_adjust(vex_byte1, mode, ®, &r_m); 5583 dtrace_get_operand(x, REG_ONLY, reg, wbit, 1); 5584 dtrace_get_operand(x, mode, r_m, wbit, 0); 5585 break; 5586 5587 case VEX_RX: 5588 /* ModR/M.rm := op(ModR/M.reg) */ 5589 /* vextractf128 || vcvtps2ph */ 5590 if (dp == &dis_opAVX660F3A[0x19] || 5591 dp == &dis_opAVX660F3A[0x1d]) { 5592 x->d86_numopnds = 3; 5593 5594 dtrace_get_modrm(x, &mode, ®, &r_m); 5595 dtrace_vex_adjust(vex_byte1, mode, ®, &r_m); 5596 5597 dtrace_get_operand(x, mode, r_m, XMM_OPND, 2); 5598 dtrace_get_operand(x, REG_ONLY, reg, wbit, 1); 5599 5600 /* one byte immediate number */ 5601 dtrace_imm_opnd(x, wbit, 1, 0); 5602 break; 5603 } 5604 5605 x->d86_numopnds = 2; 5606 5607 dtrace_get_modrm(x, &mode, ®, &r_m); 5608 dtrace_vex_adjust(vex_byte1, mode, ®, &r_m); 5609 dtrace_get_operand(x, mode, r_m, wbit, 1); 5610 dtrace_get_operand(x, REG_ONLY, reg, wbit, 0); 5611 break; 5612 5613 case VEX_RR: 5614 /* ModR/M.rm := op(ModR/M.reg) */ 5615 x->d86_numopnds = 2; 5616 5617 dtrace_get_modrm(x, &mode, ®, &r_m); 5618 dtrace_vex_adjust(vex_byte1, mode, ®, &r_m); 5619 5620 if (dp == &dis_opAVX660F[0x7E]) { 5621 /* vmovd/q <reg/mem 32/64>, <xmm> */ 5622 #ifdef DIS_TEXT 5623 if (vex_W) 5624 x->d86_mnem[4] = 'q'; 5625 #endif 5626 dtrace_get_operand(x, mode, r_m, LONG_OPND, 1); 5627 } else 5628 dtrace_get_operand(x, mode, r_m, wbit, 1); 5629 5630 dtrace_get_operand(x, REG_ONLY, reg, wbit, 0); 5631 break; 5632 5633 case VEX_RRi: 5634 /* ModR/M.rm := op(ModR/M.reg, imm) */ 5635 x->d86_numopnds = 3; 5636 5637 dtrace_get_modrm(x, &mode, ®, &r_m); 5638 dtrace_vex_adjust(vex_byte1, mode, ®, &r_m); 5639 5640 #ifdef DIS_TEXT 5641 if (dp == &dis_opAVX660F3A[0x16]) { 5642 /* vpextrd/q <imm>, <xmm>, <reg/mem 32/64> */ 5643 if (vex_W) 5644 x->d86_mnem[6] = 'q'; 5645 } 5646 #endif 5647 dtrace_get_operand(x, mode, r_m, LONG_OPND, 2); 5648 dtrace_get_operand(x, REG_ONLY, reg, wbit, 1); 5649 5650 /* one byte immediate number */ 5651 dtrace_imm_opnd(x, wbit, 1, 0); 5652 break; 5653 case VEX_RIM: 5654 /* ModR/M.rm := op(ModR/M.reg, imm) */ 5655 x->d86_numopnds = 3; 5656 5657 dtrace_get_modrm(x, &mode, ®, &r_m); 5658 dtrace_vex_adjust(vex_byte1, mode, ®, &r_m); 5659 5660 dtrace_get_operand(x, mode, r_m, XMM_OPND, 2); 5661 dtrace_get_operand(x, REG_ONLY, reg, wbit, 1); 5662 /* one byte immediate number */ 5663 dtrace_imm_opnd(x, wbit, 1, 0); 5664 break; 5665 5666 case VEX_RM: 5667 /* ModR/M.rm := op(ModR/M.reg) */ 5668 if (dp == &dis_opAVX660F3A[0x17]) { /* vextractps */ 5669 x->d86_numopnds = 3; 5670 5671 dtrace_get_modrm(x, &mode, ®, &r_m); 5672 dtrace_vex_adjust(vex_byte1, mode, ®, &r_m); 5673 5674 dtrace_get_operand(x, mode, r_m, LONG_OPND, 2); 5675 dtrace_get_operand(x, REG_ONLY, reg, wbit, 1); 5676 /* one byte immediate number */ 5677 dtrace_imm_opnd(x, wbit, 1, 0); 5678 break; 5679 } 5680 x->d86_numopnds = 2; 5681 5682 dtrace_get_modrm(x, &mode, ®, &r_m); 5683 dtrace_vex_adjust(vex_byte1, mode, ®, &r_m); 5684 L_VEX_RM: 5685 vbit = 1; 5686 dtrace_get_operand(x, mode, r_m, wbit, vbit); 5687 dtrace_get_operand(x, REG_ONLY, reg, wbit, vbit - 1); 5688 5689 break; 5690 5691 case VEX_RRM: 5692 /* ModR/M.rm := op(VEX.vvvv, ModR/M.reg) */ 5693 x->d86_numopnds = 3; 5694 5695 dtrace_get_modrm(x, &mode, ®, &r_m); 5696 dtrace_vex_adjust(vex_byte1, mode, ®, &r_m); 5697 dtrace_get_operand(x, mode, r_m, wbit, 2); 5698 /* VEX use the 1's complement form encode the XMM/YMM regs */ 5699 dtrace_get_operand(x, REG_ONLY, (0xF - vex_v), wbit, 1); 5700 dtrace_get_operand(x, REG_ONLY, reg, wbit, 0); 5701 break; 5702 5703 case VEX_RMX: 5704 /* ModR/M.reg := op(VEX.vvvv, ModR/M.rm) */ 5705 x->d86_numopnds = 3; 5706 5707 dtrace_get_modrm(x, &mode, ®, &r_m); 5708 dtrace_vex_adjust(vex_byte1, mode, ®, &r_m); 5709 dtrace_get_operand(x, REG_ONLY, reg, wbit, 2); 5710 dtrace_get_operand(x, REG_ONLY, (0xF - vex_v), wbit, 1); 5711 dtrace_get_operand(x, REG_ONLY, r_m, wbit, 0); 5712 break; 5713 5714 case VEX_NONE: 5715 #ifdef DIS_TEXT 5716 if (vex_L) 5717 (void) strncpy(x->d86_mnem, "vzeroall", OPLEN); 5718 #endif 5719 break; 5720 case BLS: { 5721 5722 /* 5723 * The BLS instructions are VEX instructions that are based on 5724 * VEX.0F38.F3; however, they are considered special group 17 5725 * and like everything else, they use the bits in 3-5 of the 5726 * MOD R/M to determine the sub instruction. Unlike many others 5727 * like the VMX instructions, these are valid both for memory 5728 * and register forms. 5729 */ 5730 5731 dtrace_get_modrm(x, &mode, ®, &r_m); 5732 dtrace_vex_adjust(vex_byte1, mode, ®, &r_m); 5733 5734 switch (reg) { 5735 case 1: 5736 #ifdef DIS_TEXT 5737 blsinstr = "blsr"; 5738 #endif 5739 break; 5740 case 2: 5741 #ifdef DIS_TEXT 5742 blsinstr = "blsmsk"; 5743 #endif 5744 break; 5745 case 3: 5746 #ifdef DIS_TEXT 5747 blsinstr = "blsi"; 5748 #endif 5749 break; 5750 default: 5751 goto error; 5752 } 5753 5754 x->d86_numopnds = 2; 5755 #ifdef DIS_TEXT 5756 (void) strncpy(x->d86_mnem, blsinstr, OPLEN); 5757 #endif 5758 dtrace_get_operand(x, REG_ONLY, (0xF - vex_v), wbit, 1); 5759 dtrace_get_operand(x, mode, r_m, wbit, 0); 5760 break; 5761 } 5762 case EVEX_MX: 5763 /* ModR/M.reg := op(ModR/M.rm) */ 5764 x->d86_numopnds = 2; 5765 dtrace_evex_mnem_adjust(x, dp, vex_W, evex_byte2); 5766 dtrace_get_modrm(x, &mode, ®, &r_m); 5767 evex_modrm = x->d86_bytes[x->d86_len - 1] & 0xff; 5768 dtrace_evex_adjust_reg(evex_byte1, ®); 5769 dtrace_evex_adjust_rm(evex_byte1, &r_m); 5770 dtrace_evex_adjust_reg_name(evex_L, &wbit); 5771 dtrace_get_operand(x, REG_ONLY, reg, wbit, 1); 5772 dtrace_evex_adjust_z_opmask(x, evex_byte3); 5773 dtrace_get_operand(x, mode, r_m, wbit, 0); 5774 dtrace_evex_adjust_disp8_n(x, 0, evex_L, evex_modrm); 5775 break; 5776 case EVEX_RX: 5777 /* ModR/M.rm := op(ModR/M.reg) */ 5778 x->d86_numopnds = 2; 5779 dtrace_evex_mnem_adjust(x, dp, vex_W, evex_byte2); 5780 dtrace_get_modrm(x, &mode, ®, &r_m); 5781 evex_modrm = x->d86_bytes[x->d86_len - 1] & 0xff; 5782 dtrace_evex_adjust_reg(evex_byte1, ®); 5783 dtrace_evex_adjust_rm(evex_byte1, &r_m); 5784 dtrace_evex_adjust_reg_name(evex_L, &wbit); 5785 dtrace_get_operand(x, mode, r_m, wbit, 1); 5786 dtrace_evex_adjust_disp8_n(x, 1, evex_L, evex_modrm); 5787 dtrace_evex_adjust_z_opmask(x, evex_byte3); 5788 dtrace_get_operand(x, REG_ONLY, reg, wbit, 0); 5789 break; 5790 /* an invalid op code */ 5791 case AM: 5792 case DM: 5793 case OVERRIDE: 5794 case PREFIX: 5795 case UNKNOWN: 5796 NOMEM; 5797 default: 5798 goto error; 5799 } /* end switch */ 5800 if (x->d86_error) 5801 goto error; 5802 5803 done: 5804 #ifdef DIS_MEM 5805 /* 5806 * compute the size of any memory accessed by the instruction 5807 */ 5808 if (x->d86_memsize != 0) { 5809 return (0); 5810 } else if (dp->it_stackop) { 5811 switch (opnd_size) { 5812 case SIZE16: 5813 x->d86_memsize = 2; 5814 break; 5815 case SIZE32: 5816 x->d86_memsize = 4; 5817 break; 5818 case SIZE64: 5819 x->d86_memsize = 8; 5820 break; 5821 } 5822 } else if (nomem || mode == REG_ONLY) { 5823 x->d86_memsize = 0; 5824 5825 } else if (dp->it_size != 0) { 5826 /* 5827 * In 64 bit mode descriptor table entries 5828 * go up to 10 bytes and popf/pushf are always 8 bytes 5829 */ 5830 if (x->d86_mode == SIZE64 && dp->it_size == 6) 5831 x->d86_memsize = 10; 5832 else if (x->d86_mode == SIZE64 && opcode1 == 0x9 && 5833 (opcode2 == 0xc || opcode2 == 0xd)) 5834 x->d86_memsize = 8; 5835 else 5836 x->d86_memsize = dp->it_size; 5837 5838 } else if (wbit == 0) { 5839 x->d86_memsize = 1; 5840 5841 } else if (wbit == LONG_OPND) { 5842 if (opnd_size == SIZE64) 5843 x->d86_memsize = 8; 5844 else if (opnd_size == SIZE32) 5845 x->d86_memsize = 4; 5846 else 5847 x->d86_memsize = 2; 5848 5849 } else if (wbit == SEG_OPND) { 5850 x->d86_memsize = 4; 5851 5852 } else { 5853 x->d86_memsize = 8; 5854 } 5855 #endif 5856 return (0); 5857 5858 error: 5859 #ifdef DIS_TEXT 5860 (void) strlcat(x->d86_mnem, "undef", OPLEN); 5861 #endif 5862 return (1); 5863 } 5864 5865 #ifdef DIS_TEXT 5866 5867 /* 5868 * Some instructions should have immediate operands printed 5869 * as unsigned integers. We compare against this table. 5870 */ 5871 static char *unsigned_ops[] = { 5872 "or", "and", "xor", "test", "in", "out", "lcall", "ljmp", 5873 "rcr", "rcl", "ror", "rol", "shl", "shr", "sal", "psr", "psl", 5874 0 5875 }; 5876 5877 5878 static int 5879 isunsigned_op(char *opcode) 5880 { 5881 char *where; 5882 int i; 5883 int is_unsigned = 0; 5884 5885 /* 5886 * Work back to start of last mnemonic, since we may have 5887 * prefixes on some opcodes. 5888 */ 5889 where = opcode + strlen(opcode) - 1; 5890 while (where > opcode && *where != ' ') 5891 --where; 5892 if (*where == ' ') 5893 ++where; 5894 5895 for (i = 0; unsigned_ops[i]; ++i) { 5896 if (strncmp(where, unsigned_ops[i], 5897 strlen(unsigned_ops[i]))) 5898 continue; 5899 is_unsigned = 1; 5900 break; 5901 } 5902 return (is_unsigned); 5903 } 5904 5905 /* 5906 * Print a numeric immediate into end of buf, maximum length buflen. 5907 * The immediate may be an address or a displacement. Mask is set 5908 * for address size. If the immediate is a "small negative", or 5909 * if it's a negative displacement of any magnitude, print as -<absval>. 5910 * Respect the "octal" flag. "Small negative" is defined as "in the 5911 * interval [NEG_LIMIT, 0)". 5912 * 5913 * Also, "isunsigned_op()" instructions never print negatives. 5914 * 5915 * Return whether we decided to print a negative value or not. 5916 */ 5917 5918 #define NEG_LIMIT -255 5919 enum {IMM, DISP}; 5920 enum {POS, TRY_NEG}; 5921 5922 static int 5923 print_imm(dis86_t *dis, uint64_t usv, uint64_t mask, char *buf, 5924 size_t buflen, int disp, int try_neg) 5925 { 5926 int curlen; 5927 int64_t sv = (int64_t)usv; 5928 int octal = dis->d86_flags & DIS_F_OCTAL; 5929 5930 curlen = strlen(buf); 5931 5932 if (try_neg == TRY_NEG && sv < 0 && 5933 (disp || sv >= NEG_LIMIT) && 5934 !isunsigned_op(dis->d86_mnem)) { 5935 dis->d86_sprintf_func(buf + curlen, buflen - curlen, 5936 octal ? "-0%llo" : "-0x%llx", (-sv) & mask); 5937 return (1); 5938 } else { 5939 if (disp == DISP) 5940 dis->d86_sprintf_func(buf + curlen, buflen - curlen, 5941 octal ? "+0%llo" : "+0x%llx", usv & mask); 5942 else 5943 dis->d86_sprintf_func(buf + curlen, buflen - curlen, 5944 octal ? "0%llo" : "0x%llx", usv & mask); 5945 return (0); 5946 5947 } 5948 } 5949 5950 5951 static int 5952 log2(int size) 5953 { 5954 switch (size) { 5955 case 1: return (0); 5956 case 2: return (1); 5957 case 4: return (2); 5958 case 8: return (3); 5959 } 5960 return (0); 5961 } 5962 5963 /* ARGSUSED */ 5964 void 5965 dtrace_disx86_str(dis86_t *dis, uint_t mode, uint64_t pc, char *buf, 5966 size_t buflen) 5967 { 5968 uint64_t reltgt = 0; 5969 uint64_t tgt = 0; 5970 int curlen; 5971 int (*lookup)(void *, uint64_t, char *, size_t); 5972 int i; 5973 int64_t sv; 5974 uint64_t usv, mask, save_mask, save_usv; 5975 static uint64_t masks[] = 5976 {0xffU, 0xffffU, 0xffffffffU, 0xffffffffffffffffULL}; 5977 save_usv = 0; 5978 5979 dis->d86_sprintf_func(buf, buflen, "%-6s ", dis->d86_mnem); 5980 5981 /* 5982 * For PC-relative jumps, the pc is really the next pc after executing 5983 * this instruction, so increment it appropriately. 5984 */ 5985 pc += dis->d86_len; 5986 5987 for (i = 0; i < dis->d86_numopnds; i++) { 5988 d86opnd_t *op = &dis->d86_opnd[i]; 5989 5990 if (i != 0) 5991 (void) strlcat(buf, ",", buflen); 5992 5993 (void) strlcat(buf, op->d86_prefix, buflen); 5994 5995 /* 5996 * sv is for the signed, possibly-truncated immediate or 5997 * displacement; usv retains the original size and 5998 * unsignedness for symbol lookup. 5999 */ 6000 6001 sv = usv = op->d86_value; 6002 6003 /* 6004 * About masks: for immediates that represent 6005 * addresses, the appropriate display size is 6006 * the effective address size of the instruction. 6007 * This includes MODE_OFFSET, MODE_IPREL, and 6008 * MODE_RIPREL. Immediates that are simply 6009 * immediate values should display in the operand's 6010 * size, however, since they don't represent addresses. 6011 */ 6012 6013 /* d86_addr_size is SIZEnn, which is log2(real size) */ 6014 mask = masks[dis->d86_addr_size]; 6015 6016 /* d86_value_size and d86_imm_bytes are in bytes */ 6017 if (op->d86_mode == MODE_SIGNED || 6018 op->d86_mode == MODE_IMPLIED) 6019 mask = masks[log2(op->d86_value_size)]; 6020 6021 switch (op->d86_mode) { 6022 6023 case MODE_NONE: 6024 6025 (void) strlcat(buf, op->d86_opnd, buflen); 6026 break; 6027 6028 case MODE_SIGNED: 6029 case MODE_IMPLIED: 6030 case MODE_OFFSET: 6031 6032 tgt = usv; 6033 6034 if (dis->d86_seg_prefix) 6035 (void) strlcat(buf, dis->d86_seg_prefix, 6036 buflen); 6037 6038 if (op->d86_mode == MODE_SIGNED || 6039 op->d86_mode == MODE_IMPLIED) { 6040 (void) strlcat(buf, "$", buflen); 6041 } 6042 6043 if (print_imm(dis, usv, mask, buf, buflen, 6044 IMM, TRY_NEG) && 6045 (op->d86_mode == MODE_SIGNED || 6046 op->d86_mode == MODE_IMPLIED)) { 6047 6048 /* 6049 * We printed a negative value for an 6050 * immediate that wasn't a 6051 * displacement. Note that fact so we can 6052 * print the positive value as an 6053 * annotation. 6054 */ 6055 6056 save_usv = usv; 6057 save_mask = mask; 6058 } 6059 (void) strlcat(buf, op->d86_opnd, buflen); 6060 6061 break; 6062 6063 case MODE_IPREL: 6064 case MODE_RIPREL: 6065 6066 reltgt = pc + sv; 6067 6068 switch (mode) { 6069 case SIZE16: 6070 reltgt = (uint16_t)reltgt; 6071 break; 6072 case SIZE32: 6073 reltgt = (uint32_t)reltgt; 6074 break; 6075 } 6076 6077 (void) print_imm(dis, usv, mask, buf, buflen, 6078 DISP, TRY_NEG); 6079 6080 if (op->d86_mode == MODE_RIPREL) 6081 (void) strlcat(buf, "(%rip)", buflen); 6082 break; 6083 } 6084 } 6085 6086 /* 6087 * The symbol lookups may result in false positives, 6088 * particularly on object files, where small numbers may match 6089 * the 0-relative non-relocated addresses of symbols. 6090 */ 6091 6092 lookup = dis->d86_sym_lookup; 6093 if (tgt != 0) { 6094 if ((dis->d86_flags & DIS_F_NOIMMSYM) == 0 && 6095 lookup(dis->d86_data, tgt, NULL, 0) == 0) { 6096 (void) strlcat(buf, "\t<", buflen); 6097 curlen = strlen(buf); 6098 lookup(dis->d86_data, tgt, buf + curlen, 6099 buflen - curlen); 6100 (void) strlcat(buf, ">", buflen); 6101 } 6102 6103 /* 6104 * If we printed a negative immediate above, print the 6105 * positive in case our heuristic was unhelpful 6106 */ 6107 if (save_usv) { 6108 (void) strlcat(buf, "\t<", buflen); 6109 (void) print_imm(dis, save_usv, save_mask, buf, buflen, 6110 IMM, POS); 6111 (void) strlcat(buf, ">", buflen); 6112 } 6113 } 6114 6115 if (reltgt != 0) { 6116 /* Print symbol or effective address for reltgt */ 6117 6118 (void) strlcat(buf, "\t<", buflen); 6119 curlen = strlen(buf); 6120 lookup(dis->d86_data, reltgt, buf + curlen, 6121 buflen - curlen); 6122 (void) strlcat(buf, ">", buflen); 6123 } 6124 } 6125 6126 #endif /* DIS_TEXT */ 6127