1[ 2 { 3 "Unit": "CHA", 4 "EventCode": "0x00", 5 "UMask": "0x00", 6 "PortMask": "0x00", 7 "FCMask": "0x00", 8 "UMaskExt": "0x00", 9 "EventName": "UNC_CHA_CLOCKTICKS", 10 "BriefDescription": "Clockticks of the uncore caching and home agent (CHA)", 11 "PublicDescription": "Clockticks of the uncore caching and home agent (CHA)", 12 "Counter": "0,1,2,3", 13 "MSRValue": "0x00", 14 "ELLC": "0", 15 "Filter": "na", 16 "ExtSel": "0", 17 "Deprecated": "0", 18 "FILTER_VALUE": "0", 19 "CounterType": "PGMABLE" 20 }, 21 { 22 "Unit": "CHA", 23 "EventCode": "0x35", 24 "UMask": "0x01", 25 "PortMask": "0x00", 26 "FCMask": "0x00", 27 "UMaskExt": "0xC001FE", 28 "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS", 29 "BriefDescription": "TOR Inserts : All requests from iA Cores that Missed the LLC", 30 "PublicDescription": "TOR Inserts : All requests from iA Cores that Missed the LLC : Counts the number of entries successfuly inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", 31 "Counter": "0,1,2,3", 32 "MSRValue": "0x00", 33 "ELLC": "0", 34 "Filter": "na", 35 "ExtSel": "0", 36 "Deprecated": "0", 37 "FILTER_VALUE": "0", 38 "CounterType": "PGMABLE" 39 }, 40 { 41 "Unit": "CHA", 42 "EventCode": "0x35", 43 "UMask": "0x01", 44 "PortMask": "0x00", 45 "FCMask": "0x00", 46 "UMaskExt": "0xC80FFE", 47 "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_CRD", 48 "BriefDescription": "TOR Inserts : CRds issued by iA Cores that Missed the LLC", 49 "PublicDescription": "TOR Inserts : CRds issued by iA Cores that Missed the LLC : Counts the number of entries successfuly inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", 50 "Counter": "0,1,2,3", 51 "MSRValue": "0x00", 52 "ELLC": "0", 53 "Filter": "na", 54 "ExtSel": "0", 55 "Deprecated": "0", 56 "FILTER_VALUE": "0", 57 "CounterType": "PGMABLE" 58 }, 59 { 60 "Unit": "CHA", 61 "EventCode": "0x35", 62 "UMask": "0x01", 63 "PortMask": "0x00", 64 "FCMask": "0x00", 65 "UMaskExt": "0xC807FE", 66 "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_RFO", 67 "BriefDescription": "TOR Inserts : RFOs issued by iA Cores that Missed the LLC", 68 "PublicDescription": "TOR Inserts : RFOs issued by iA Cores that Missed the LLC : Counts the number of entries successfuly inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", 69 "Counter": "0,1,2,3", 70 "MSRValue": "0x00", 71 "ELLC": "0", 72 "Filter": "na", 73 "ExtSel": "0", 74 "Deprecated": "0", 75 "FILTER_VALUE": "0", 76 "CounterType": "PGMABLE" 77 }, 78 { 79 "Unit": "CHA", 80 "EventCode": "0x35", 81 "UMask": "0x01", 82 "PortMask": "0x00", 83 "FCMask": "0x00", 84 "UMaskExt": "0xC88FFE", 85 "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_CRD_PREF", 86 "BriefDescription": "TOR Inserts : CRd_Prefs issued by iA Cores that Missed the LLC", 87 "PublicDescription": "TOR Inserts : CRd_Prefs issued by iA Cores that Missed the LLC : Counts the number of entries successfuly inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", 88 "Counter": "0,1,2,3", 89 "MSRValue": "0x00", 90 "ELLC": "0", 91 "Filter": "na", 92 "ExtSel": "0", 93 "Deprecated": "0", 94 "FILTER_VALUE": "0", 95 "CounterType": "PGMABLE" 96 }, 97 { 98 "Unit": "CHA", 99 "EventCode": "0x35", 100 "UMask": "0x01", 101 "PortMask": "0x00", 102 "FCMask": "0x00", 103 "UMaskExt": "0xC827FE", 104 "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_DRD_OPT", 105 "BriefDescription": "TOR Inserts : DRd_Opt issued by iA Cores that missed the LLC", 106 "PublicDescription": "TOR Inserts : DRd_Opt issued by iA Cores that missed the LLC : Counts the number of entries successfuly inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", 107 "Counter": "0,1,2,3", 108 "MSRValue": "0x00", 109 "ELLC": "0", 110 "Filter": "na", 111 "ExtSel": "0", 112 "Deprecated": "0", 113 "FILTER_VALUE": "0", 114 "CounterType": "PGMABLE" 115 }, 116 { 117 "Unit": "CHA", 118 "EventCode": "0x35", 119 "UMask": "0x01", 120 "PortMask": "0x00", 121 "FCMask": "0x00", 122 "UMaskExt": "0xC8A7FE", 123 "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_DRD_OPT_PREF", 124 "BriefDescription": "TOR Inserts : DRd_Opt_Prefs issued by iA Cores that missed the LLC", 125 "PublicDescription": "TOR Inserts : DRd_Opt_Prefs issued by iA Cores that missed the LLC : Counts the number of entries successfuly inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", 126 "Counter": "0,1,2,3", 127 "MSRValue": "0x00", 128 "ELLC": "0", 129 "Filter": "na", 130 "ExtSel": "0", 131 "Deprecated": "0", 132 "FILTER_VALUE": "0", 133 "CounterType": "PGMABLE" 134 }, 135 { 136 "Unit": "CHA", 137 "EventCode": "0x35", 138 "UMask": "0x01", 139 "PortMask": "0x00", 140 "FCMask": "0x00", 141 "UMaskExt": "0xC887FE", 142 "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_RFO_PREF", 143 "BriefDescription": "TOR Inserts : RFO_Prefs issued by iA Cores that Missed the LLC", 144 "PublicDescription": "TOR Inserts : RFO_Prefs issued by iA Cores that Missed the LLC : Counts the number of entries successfuly inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", 145 "Counter": "0,1,2,3", 146 "MSRValue": "0x00", 147 "ELLC": "0", 148 "Filter": "na", 149 "ExtSel": "0", 150 "Deprecated": "0", 151 "FILTER_VALUE": "0", 152 "CounterType": "PGMABLE" 153 }, 154 { 155 "Unit": "CHA", 156 "EventCode": "0x35", 157 "UMask": "0x01", 158 "PortMask": "0x00", 159 "FCMask": "0x00", 160 "UMaskExt": "0xC86FFE", 161 "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_WCIL", 162 "BriefDescription": "TOR Inserts : WCiLs issued by iA Cores that Missed the LLC", 163 "PublicDescription": "TOR Inserts : WCiLs issued by iA Cores that Missed the LLC : Counts the number of entries successfuly inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", 164 "Counter": "0,1,2,3", 165 "MSRValue": "0x00", 166 "ELLC": "0", 167 "Filter": "na", 168 "ExtSel": "0", 169 "Deprecated": "0", 170 "FILTER_VALUE": "0", 171 "CounterType": "PGMABLE" 172 }, 173 { 174 "Unit": "CHA", 175 "EventCode": "0x35", 176 "UMask": "0x01", 177 "PortMask": "0x00", 178 "FCMask": "0x00", 179 "UMaskExt": "0xC867FE", 180 "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_WCILF", 181 "BriefDescription": "TOR Inserts : WCiLF issued by iA Cores that Missed the LLC", 182 "PublicDescription": "TOR Inserts : WCiLF issued by iA Cores that Missed the LLC : Counts the number of entries successfuly inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", 183 "Counter": "0,1,2,3", 184 "MSRValue": "0x00", 185 "ELLC": "0", 186 "Filter": "na", 187 "ExtSel": "0", 188 "Deprecated": "0", 189 "FILTER_VALUE": "0", 190 "CounterType": "PGMABLE" 191 }, 192 { 193 "Unit": "IIO", 194 "EventCode": "0x01", 195 "UMask": "0x00", 196 "PortMask": "0x00", 197 "FCMask": "0x00", 198 "UMaskExt": "0x00", 199 "EventName": "UNC_IIO_CLOCKTICKS", 200 "BriefDescription": "Clockticks of the integrated IO (IIO) traffic controller", 201 "PublicDescription": "Clockticks of the integrated IO (IIO) traffic controller", 202 "Counter": "0,1,2,3", 203 "MSRValue": "0x00", 204 "ELLC": "0", 205 "Filter": "na", 206 "ExtSel": "0", 207 "Deprecated": "0", 208 "FILTER_VALUE": "0", 209 "CounterType": "PGMABLE" 210 }, 211 { 212 "Unit": "IIO", 213 "EventCode": "0x83", 214 "UMask": "0x01", 215 "PortMask": "0x01", 216 "FCMask": "0x07", 217 "UMaskExt": "0x00", 218 "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.PART0", 219 "BriefDescription": "Four byte data request of the CPU : Card writing to DRAM", 220 "PublicDescription": "Data requested of the CPU : Card writing to DRAM : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 0", 221 "Counter": "0,1", 222 "MSRValue": "0x00", 223 "ELLC": "0", 224 "Filter": "na", 225 "ExtSel": "0", 226 "Deprecated": "0", 227 "FILTER_VALUE": "0", 228 "CounterType": "PGMABLE" 229 }, 230 { 231 "Unit": "IIO", 232 "EventCode": "0x83", 233 "UMask": "0x01", 234 "PortMask": "0x02", 235 "FCMask": "0x07", 236 "UMaskExt": "0x00", 237 "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.PART1", 238 "BriefDescription": "Four byte data request of the CPU : Card writing to DRAM", 239 "PublicDescription": "Data requested of the CPU : Card writing to DRAM : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 1", 240 "Counter": "0,1", 241 "MSRValue": "0x00", 242 "ELLC": "0", 243 "Filter": "na", 244 "ExtSel": "0", 245 "Deprecated": "0", 246 "FILTER_VALUE": "0", 247 "CounterType": "PGMABLE" 248 }, 249 { 250 "Unit": "IIO", 251 "EventCode": "0x83", 252 "UMask": "0x01", 253 "PortMask": "0x04", 254 "FCMask": "0x07", 255 "UMaskExt": "0x00", 256 "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.PART2", 257 "BriefDescription": "Four byte data request of the CPU : Card writing to DRAM", 258 "PublicDescription": "Data requested of the CPU : Card writing to DRAM : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x8 card plugged in to Lane 2/3, Or x4 card is plugged in to slot 2", 259 "Counter": "0,1", 260 "MSRValue": "0x00", 261 "ELLC": "0", 262 "Filter": "na", 263 "ExtSel": "0", 264 "Deprecated": "0", 265 "FILTER_VALUE": "0", 266 "CounterType": "PGMABLE" 267 }, 268 { 269 "Unit": "IIO", 270 "EventCode": "0x83", 271 "UMask": "0x01", 272 "PortMask": "0x08", 273 "FCMask": "0x07", 274 "UMaskExt": "0x00", 275 "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.PART3", 276 "BriefDescription": "Four byte data request of the CPU : Card writing to DRAM", 277 "PublicDescription": "Data requested of the CPU : Card writing to DRAM : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 3", 278 "Counter": "0,1", 279 "MSRValue": "0x00", 280 "ELLC": "0", 281 "Filter": "na", 282 "ExtSel": "0", 283 "Deprecated": "0", 284 "FILTER_VALUE": "0", 285 "CounterType": "PGMABLE" 286 }, 287 { 288 "Unit": "IIO", 289 "EventCode": "0x83", 290 "UMask": "0x04", 291 "PortMask": "0x01", 292 "FCMask": "0x07", 293 "UMaskExt": "0x00", 294 "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART0", 295 "BriefDescription": "Four byte data request of the CPU : Card reading from DRAM", 296 "PublicDescription": "Data requested of the CPU : Card reading from DRAM : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 0", 297 "Counter": "0,1", 298 "MSRValue": "0x00", 299 "ELLC": "0", 300 "Filter": "na", 301 "ExtSel": "0", 302 "Deprecated": "0", 303 "FILTER_VALUE": "0", 304 "CounterType": "PGMABLE" 305 }, 306 { 307 "Unit": "IIO", 308 "EventCode": "0x83", 309 "UMask": "0x04", 310 "PortMask": "0x02", 311 "FCMask": "0x07", 312 "UMaskExt": "0x00", 313 "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART1", 314 "BriefDescription": "Four byte data request of the CPU : Card reading from DRAM", 315 "PublicDescription": "Data requested of the CPU : Card reading from DRAM : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 1", 316 "Counter": "0,1", 317 "MSRValue": "0x00", 318 "ELLC": "0", 319 "Filter": "na", 320 "ExtSel": "0", 321 "Deprecated": "0", 322 "FILTER_VALUE": "0", 323 "CounterType": "PGMABLE" 324 }, 325 { 326 "Unit": "IIO", 327 "EventCode": "0x83", 328 "UMask": "0x04", 329 "PortMask": "0x04", 330 "FCMask": "0x07", 331 "UMaskExt": "0x00", 332 "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART2", 333 "BriefDescription": "Four byte data request of the CPU : Card reading from DRAM", 334 "PublicDescription": "Data requested of the CPU : Card reading from DRAM : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x8 card plugged in to Lane 2/3, Or x4 card is plugged in to slot 2", 335 "Counter": "0,1", 336 "MSRValue": "0x00", 337 "ELLC": "0", 338 "Filter": "na", 339 "ExtSel": "0", 340 "Deprecated": "0", 341 "FILTER_VALUE": "0", 342 "CounterType": "PGMABLE" 343 }, 344 { 345 "Unit": "IIO", 346 "EventCode": "0x83", 347 "UMask": "0x04", 348 "PortMask": "0x08", 349 "FCMask": "0x07", 350 "UMaskExt": "0x00", 351 "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART3", 352 "BriefDescription": "Four byte data request of the CPU : Card reading from DRAM", 353 "PublicDescription": "Data requested of the CPU : Card reading from DRAM : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 3", 354 "Counter": "0,1", 355 "MSRValue": "0x00", 356 "ELLC": "0", 357 "Filter": "na", 358 "ExtSel": "0", 359 "Deprecated": "0", 360 "FILTER_VALUE": "0", 361 "CounterType": "PGMABLE" 362 }, 363 { 364 "Unit": "IIO", 365 "EventCode": "0x83", 366 "UMask": "0x01", 367 "PortMask": "0x10", 368 "FCMask": "0x07", 369 "UMaskExt": "0x00", 370 "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.PART4", 371 "BriefDescription": "Four byte data request of the CPU : Card writing to DRAM", 372 "PublicDescription": "Data requested of the CPU : Card writing to DRAM : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x16 card plugged in to Lane 4/5/6/7, Or x8 card plugged in to Lane 4/5, Or x4 card is plugged in to slot 4", 373 "Counter": "0,1", 374 "MSRValue": "0x00", 375 "ELLC": "0", 376 "Filter": "na", 377 "ExtSel": "0", 378 "Deprecated": "0", 379 "FILTER_VALUE": "0", 380 "CounterType": "PGMABLE" 381 }, 382 { 383 "Unit": "IIO", 384 "EventCode": "0x83", 385 "UMask": "0x01", 386 "PortMask": "0x20", 387 "FCMask": "0x07", 388 "UMaskExt": "0x00", 389 "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.PART5", 390 "BriefDescription": "Four byte data request of the CPU : Card writing to DRAM", 391 "PublicDescription": "Data requested of the CPU : Card writing to DRAM : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 5", 392 "Counter": "0,1", 393 "MSRValue": "0x00", 394 "ELLC": "0", 395 "Filter": "na", 396 "ExtSel": "0", 397 "Deprecated": "0", 398 "FILTER_VALUE": "0", 399 "CounterType": "PGMABLE" 400 }, 401 { 402 "Unit": "IIO", 403 "EventCode": "0x83", 404 "UMask": "0x01", 405 "PortMask": "0x40", 406 "FCMask": "0x07", 407 "UMaskExt": "0x00", 408 "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.PART6", 409 "BriefDescription": "Four byte data request of the CPU : Card writing to DRAM", 410 "PublicDescription": "Data requested of the CPU : Card writing to DRAM : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x8 card plugged in to Lane 6/7, Or x4 card is plugged in to slot 6", 411 "Counter": "0,1", 412 "MSRValue": "0x00", 413 "ELLC": "0", 414 "Filter": "na", 415 "ExtSel": "0", 416 "Deprecated": "0", 417 "FILTER_VALUE": "0", 418 "CounterType": "PGMABLE" 419 }, 420 { 421 "Unit": "IIO", 422 "EventCode": "0x83", 423 "UMask": "0x01", 424 "PortMask": "0x80", 425 "FCMask": "0x07", 426 "UMaskExt": "0x00", 427 "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.PART7", 428 "BriefDescription": "Four byte data request of the CPU : Card writing to DRAM", 429 "PublicDescription": "Data requested of the CPU : Card writing to DRAM : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 7", 430 "Counter": "0,1", 431 "MSRValue": "0x00", 432 "ELLC": "0", 433 "Filter": "na", 434 "ExtSel": "0", 435 "Deprecated": "0", 436 "FILTER_VALUE": "0", 437 "CounterType": "PGMABLE" 438 }, 439 { 440 "Unit": "IIO", 441 "EventCode": "0x83", 442 "UMask": "0x04", 443 "PortMask": "0x10", 444 "FCMask": "0x07", 445 "UMaskExt": "0x00", 446 "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART4", 447 "BriefDescription": "Four byte data request of the CPU : Card reading from DRAM", 448 "PublicDescription": "Data requested of the CPU : Card reading from DRAM : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x16 card plugged in to Lane 4/5/6/7, Or x8 card plugged in to Lane 4/5, Or x4 card is plugged in to slot 4", 449 "Counter": "0,1", 450 "MSRValue": "0x00", 451 "ELLC": "0", 452 "Filter": "na", 453 "ExtSel": "0", 454 "Deprecated": "0", 455 "FILTER_VALUE": "0", 456 "CounterType": "PGMABLE" 457 }, 458 { 459 "Unit": "IIO", 460 "EventCode": "0x83", 461 "UMask": "0x04", 462 "PortMask": "0x20", 463 "FCMask": "0x07", 464 "UMaskExt": "0x00", 465 "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART5", 466 "BriefDescription": "Four byte data request of the CPU : Card reading from DRAM", 467 "PublicDescription": "Data requested of the CPU : Card reading from DRAM : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 5", 468 "Counter": "0,1", 469 "MSRValue": "0x00", 470 "ELLC": "0", 471 "Filter": "na", 472 "ExtSel": "0", 473 "Deprecated": "0", 474 "FILTER_VALUE": "0", 475 "CounterType": "PGMABLE" 476 }, 477 { 478 "Unit": "IIO", 479 "EventCode": "0x83", 480 "UMask": "0x04", 481 "PortMask": "0x40", 482 "FCMask": "0x07", 483 "UMaskExt": "0x00", 484 "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART6", 485 "BriefDescription": "Four byte data request of the CPU : Card reading from DRAM", 486 "PublicDescription": "Data requested of the CPU : Card reading from DRAM : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x8 card plugged in to Lane 6/7, Or x4 card is plugged in to slot 6", 487 "Counter": "0,1", 488 "MSRValue": "0x00", 489 "ELLC": "0", 490 "Filter": "na", 491 "ExtSel": "0", 492 "Deprecated": "0", 493 "FILTER_VALUE": "0", 494 "CounterType": "PGMABLE" 495 }, 496 { 497 "Unit": "IIO", 498 "EventCode": "0x83", 499 "UMask": "0x04", 500 "PortMask": "0x80", 501 "FCMask": "0x07", 502 "UMaskExt": "0x00", 503 "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART7", 504 "BriefDescription": "Four byte data request of the CPU : Card reading from DRAM", 505 "PublicDescription": "Data requested of the CPU : Card reading from DRAM : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 7", 506 "Counter": "0,1", 507 "MSRValue": "0x00", 508 "ELLC": "0", 509 "Filter": "na", 510 "ExtSel": "0", 511 "Deprecated": "0", 512 "FILTER_VALUE": "0", 513 "CounterType": "PGMABLE" 514 }, 515 { 516 "Unit": "IRP", 517 "EventCode": "0x01", 518 "UMask": "0x00", 519 "PortMask": "0x00", 520 "FCMask": "0x00", 521 "UMaskExt": "0x00", 522 "EventName": "UNC_I_CLOCKTICKS", 523 "BriefDescription": "Clockticks of the IO coherency tracker (IRP)", 524 "PublicDescription": "Clockticks of the IO coherency tracker (IRP)", 525 "Counter": "0,1", 526 "MSRValue": "0x00", 527 "ELLC": "0", 528 "Filter": "na", 529 "ExtSel": "0", 530 "Deprecated": "0", 531 "FILTER_VALUE": "0", 532 "CounterType": "PGMABLE" 533 }, 534 { 535 "Unit": "iMC", 536 "EventCode": "0x02", 537 "UMask": "0x04", 538 "PortMask": "0x00", 539 "FCMask": "0x00", 540 "UMaskExt": "0x00", 541 "EventName": "UNC_M_PRE_COUNT.RD", 542 "BriefDescription": "DRAM Precharge commands. : Precharge due to read", 543 "PublicDescription": "DRAM Precharge commands. : Precharge due to read : Counts the number of DRAM Precharge commands sent on this channel. : Precharge from read bank scheduler", 544 "Counter": "0,1,2,3", 545 "MSRValue": "0x00", 546 "ELLC": "0", 547 "Filter": "na", 548 "ExtSel": "0", 549 "Deprecated": "0", 550 "FILTER_VALUE": "0", 551 "CounterType": "PGMABLE" 552 }, 553 { 554 "Unit": "iMC", 555 "EventCode": "0x02", 556 "UMask": "0x08", 557 "PortMask": "0x00", 558 "FCMask": "0x00", 559 "UMaskExt": "0x00", 560 "EventName": "UNC_M_PRE_COUNT.WR", 561 "BriefDescription": "DRAM Precharge commands. : Precharge due to write", 562 "PublicDescription": "DRAM Precharge commands. : Precharge due to write : Counts the number of DRAM Precharge commands sent on this channel. : Precharge from write bank scheduler", 563 "Counter": "0,1,2,3", 564 "MSRValue": "0x00", 565 "ELLC": "0", 566 "Filter": "na", 567 "ExtSel": "0", 568 "Deprecated": "0", 569 "FILTER_VALUE": "0", 570 "CounterType": "PGMABLE" 571 }, 572 { 573 "Unit": "iMC", 574 "EventCode": "0x04", 575 "UMask": "0x0f", 576 "PortMask": "0x00", 577 "FCMask": "0x00", 578 "UMaskExt": "0x00", 579 "EventName": "UNC_M_CAS_COUNT.RD", 580 "BriefDescription": "All DRAM read CAS commands issued (including underfills)", 581 "PublicDescription": "Counts the total number of DRAM Read CAS commands, w/ and w/o auto-pre, issued on this channel. This includes underfills.", 582 "Counter": "0,1,2,3", 583 "MSRValue": "0x00", 584 "ELLC": "0", 585 "Filter": "na", 586 "ExtSel": "0", 587 "Deprecated": "0", 588 "FILTER_VALUE": "0", 589 "CounterType": "PGMABLE" 590 }, 591 { 592 "Unit": "iMC", 593 "EventCode": "0x04", 594 "UMask": "0x30", 595 "PortMask": "0x00", 596 "FCMask": "0x00", 597 "UMaskExt": "0x00", 598 "EventName": "UNC_M_CAS_COUNT.WR", 599 "BriefDescription": "All DRAM write CAS commands issued", 600 "PublicDescription": "Counts the total number of DRAM Write CAS commands issued, w/ and w/o auto-pre, on this channel.", 601 "Counter": "0,1,2,3", 602 "MSRValue": "0x00", 603 "ELLC": "0", 604 "Filter": "na", 605 "ExtSel": "0", 606 "Deprecated": "0", 607 "FILTER_VALUE": "0", 608 "CounterType": "PGMABLE" 609 }, 610 { 611 "Unit": "iMC", 612 "EventCode": "0x02", 613 "UMask": "0x10", 614 "PortMask": "0x00", 615 "FCMask": "0x00", 616 "UMaskExt": "0x00", 617 "EventName": "UNC_M_PRE_COUNT.PGT", 618 "BriefDescription": "DRAM Precharge commands. : Precharge due to page table", 619 "PublicDescription": "DRAM Precharge commands. : Precharge due to page table : Counts the number of DRAM Precharge commands sent on this channel. : Prechages from Page Table", 620 "Counter": "0,1,2,3", 621 "MSRValue": "0x00", 622 "ELLC": "0", 623 "Filter": "na", 624 "ExtSel": "0", 625 "Deprecated": "0", 626 "FILTER_VALUE": "0", 627 "CounterType": "PGMABLE" 628 }, 629 { 630 "Unit": "iMC", 631 "EventCode": "0x00", 632 "UMask": "0x00", 633 "PortMask": "0x00", 634 "FCMask": "0x00", 635 "UMaskExt": "0x00", 636 "EventName": "UNC_M_CLOCKTICKS", 637 "BriefDescription": "DRAM Clockticks", 638 "PublicDescription": "Clockticks of the integrated memory controller (IMC)", 639 "Counter": "0,1,2,3", 640 "MSRValue": "0x00", 641 "ELLC": "0", 642 "Filter": "na", 643 "ExtSel": "0", 644 "Deprecated": "0", 645 "FILTER_VALUE": "0", 646 "CounterType": "PGMABLE" 647 }, 648 { 649 "Unit": "iMC", 650 "EventCode": "0x02", 651 "UMask": "0x1C", 652 "PortMask": "0x00", 653 "FCMask": "0x00", 654 "UMaskExt": "0x00", 655 "EventName": "UNC_M_PRE_COUNT.ALL", 656 "BriefDescription": "DRAM Precharge commands.", 657 "PublicDescription": "DRAM Precharge commands. : Counts the number of DRAM Precharge commands sent on this channel.", 658 "Counter": "0,1,2,3", 659 "MSRValue": "0x00", 660 "ELLC": "0", 661 "Filter": "na", 662 "ExtSel": "0", 663 "Deprecated": "0", 664 "FILTER_VALUE": "0", 665 "CounterType": "PGMABLE" 666 }, 667 { 668 "Unit": "M2M", 669 "EventCode": "0x00", 670 "UMask": "0x00", 671 "PortMask": "0x00", 672 "FCMask": "0x00", 673 "UMaskExt": "0x00", 674 "EventName": "UNC_M2M_CLOCKTICKS", 675 "BriefDescription": "Clockticks of the mesh to memory (M2M)", 676 "PublicDescription": "Clockticks of the mesh to memory (M2M)", 677 "Counter": "0,1,2,3", 678 "MSRValue": "0x00", 679 "ELLC": "0", 680 "Filter": "na", 681 "ExtSel": "0", 682 "Deprecated": "0", 683 "FILTER_VALUE": "0", 684 "CounterType": "PGMABLE" 685 }, 686 { 687 "Unit": "M2PCIe", 688 "EventCode": "0x01", 689 "UMask": "0x00", 690 "PortMask": "0x00", 691 "FCMask": "0x00", 692 "UMaskExt": "0x00", 693 "EventName": "UNC_M2P_CLOCKTICKS", 694 "BriefDescription": "Clockticks of the mesh to PCI (M2P)", 695 "PublicDescription": "Clockticks of the mesh to PCI (M2P)", 696 "Counter": "0,1,2,3", 697 "MSRValue": "0x00", 698 "ELLC": "0", 699 "Filter": "na", 700 "ExtSel": "0", 701 "Deprecated": "0", 702 "FILTER_VALUE": "0", 703 "CounterType": "PGMABLE" 704 }, 705 { 706 "Unit": "UBOX", 707 "EventCode": "0x00", 708 "UMask": "0x01", 709 "PortMask": "0x00", 710 "FCMask": "0x00", 711 "UMaskExt": "0x00", 712 "EventName": "UNC_U_CLOCKTICKS", 713 "BriefDescription": "Clockticks in the UBOX using a dedicated 48-bit Fixed Counter", 714 "PublicDescription": "Clockticks in the UBOX using a dedicated 48-bit Fixed Counter", 715 "Counter": "FIXED", 716 "MSRValue": "0x00", 717 "ELLC": "0", 718 "Filter": "na", 719 "ExtSel": "0", 720 "Deprecated": "0", 721 "FILTER_VALUE": "0", 722 "CounterType": "FIXED" 723 }, 724 { 725 "Unit": "PCU", 726 "EventCode": "0x00", 727 "UMask": "0x00", 728 "PortMask": "0x00", 729 "FCMask": "0x00", 730 "UMaskExt": "0x00", 731 "EventName": "UNC_P_CLOCKTICKS", 732 "BriefDescription": "Clockticks of the power control unit (PCU)", 733 "PublicDescription": "Clockticks of the power control unit (PCU)", 734 "Counter": "0,1,2,3", 735 "MSRValue": "0x00", 736 "ELLC": "0", 737 "Filter": "na", 738 "ExtSel": "0", 739 "Deprecated": "0", 740 "FILTER_VALUE": "0", 741 "CounterType": "PGMABLE" 742 } 743]