1*7e3dbbacSRobert Mustacchi--------------------- 2*7e3dbbacSRobert MustacchiThis package contains performance monitoring event lists for Intel processors, as well as a mapping file 3*7e3dbbacSRobert Mustacchito help match event lists to processor Family/Model/Stepping codes. 4*7e3dbbacSRobert Mustacchi--------------------- 5*7e3dbbacSRobert Mustacchi 6*7e3dbbacSRobert MustacchiThe event lists are available in 2 formats: 7*7e3dbbacSRobert Mustacchi Tab delimited (.tsv) 8*7e3dbbacSRobert Mustacchi Json (.json) 9*7e3dbbacSRobert Mustacchi 10*7e3dbbacSRobert MustacchiEvent lists are created per microarchitecture, and each has a version. Versions are listed in the event list 11*7e3dbbacSRobert Mustacchiname as well as the header for each file. For some microarchitectures, up to three different event lists will 12*7e3dbbacSRobert Mustacchibe available. These event lists correspond to the types of events that can be collected: 13*7e3dbbacSRobert Mustacchi 14*7e3dbbacSRobert Mustacchicore - Contains events counted from within a logical processor core. 15*7e3dbbacSRobert Mustacchioffcore - Contains matrix events counted from the core, but measuring responses that come from offcore. 16*7e3dbbacSRobert Mustacchi 17*7e3dbbacSRobert MustacchiThe event list filename indicates which type of list it contains, and follows this format: 18*7e3dbbacSRobert Mustacchi<microarchitecture-codename>_<core/offcore>_<version> 19*7e3dbbacSRobert Mustacchi 20*7e3dbbacSRobert MustacchiNew version releases will be announced in the mail list perfmon-announce@lists.01.org 21*7e3dbbacSRobert Mustacchi 22*7e3dbbacSRobert MustacchiDifferent microarchitectures provide different performance monitoring capabilities, so field names and categories 23*7e3dbbacSRobert Mustacchiof events may vary. 24*7e3dbbacSRobert Mustacchi 25*7e3dbbacSRobert Mustacchi--------------------- 26*7e3dbbacSRobert MustacchiEvent List Field Defitions: 27*7e3dbbacSRobert Mustacchi--------------------- 28*7e3dbbacSRobert MustacchiBelow is a list of the fields/headers in the event files and a description of how SW tools should 29*7e3dbbacSRobert Mustacchiinterpret these values. A particular event list from this package may not contain all the fields described 30*7e3dbbacSRobert Mustacchibelow. For more detailed information of the Performance monitoring unit please refer to chapters 18 and 19 31*7e3dbbacSRobert Mustacchiof Intel� 64 and IA-32 Architectures Software Developer's Manual Volume 3B: System Programming Guide, Part 2. 32*7e3dbbacSRobert Mustacchi 33*7e3dbbacSRobert Mustacchihttp://www.intel.com/content/www/us/en/processors/architectures-software-developer-manuals.html 34*7e3dbbacSRobert Mustacchi 35*7e3dbbacSRobert Mustacchi 36*7e3dbbacSRobert Mustacchi----EventCode---- 37*7e3dbbacSRobert MustacchiThis field maps to the Event Select field in the IA32_PERFEVTSELx[7:0]MSRs. The set of values for this field 38*7e3dbbacSRobert Mustacchiis defined architecturally. Each value corresponds to an event logic unit and should be used with a unit 39*7e3dbbacSRobert Mustacchimask value to obtain an architectural performance event. 40*7e3dbbacSRobert Mustacchi 41*7e3dbbacSRobert Mustacchi----UMask---- 42*7e3dbbacSRobert MustacchiThis field maps to the Unit Mask filed in the IA32_PERFEVTSELx[15:8] MSRs. It further qualifies the event logic 43*7e3dbbacSRobert Mustacchiunit selected in the event select field to detect a specific micro-architectural condition. 44*7e3dbbacSRobert Mustacchi 45*7e3dbbacSRobert Mustacchi----EventName---- 46*7e3dbbacSRobert MustacchiIt is a string of characters to identify the programming of an event. 47*7e3dbbacSRobert Mustacchi 48*7e3dbbacSRobert Mustacchi----BriefDescription---- 49*7e3dbbacSRobert MustacchiThis field contains a description of what is being counted by a particular event. 50*7e3dbbacSRobert Mustacchi 51*7e3dbbacSRobert Mustacchi----PublicDescription---- 52*7e3dbbacSRobert MustacchiIn some cases, this field will contain a more detailed description of what is counted by an event. 53*7e3dbbacSRobert Mustacchi 54*7e3dbbacSRobert Mustacchi----Counter---- 55*7e3dbbacSRobert MustacchiThis field lists the fixed (PERF_FIXED_CTRX) or programmable (IA32_PMCX) counters that can be used to count the event. 56*7e3dbbacSRobert Mustacchi 57*7e3dbbacSRobert Mustacchi----CounterHTOff---- 58*7e3dbbacSRobert MustacchiThis field lists the counters where this event can be sampled when Intel� Hyper-Threading Technology (Intel� HT Technology) is 59*7e3dbbacSRobert Mustacchidisabled. When Intel� HT Technology is disabled, some processor cores gain access to the programmable counters of the second 60*7e3dbbacSRobert Mustacchithread, making a total of eight programmable counters available. The additional counters will be numbered 4,5,6,7. Fixed counter 61*7e3dbbacSRobert Mustacchibehavior remains unaffected. 62*7e3dbbacSRobert Mustacchi 63*7e3dbbacSRobert Mustacchi----PEBScounters---- 64*7e3dbbacSRobert MustacchiThis field is only relevant to PEBS events. It lists the counters where the event can be sampled when it is programmed as a PEBS event. 65*7e3dbbacSRobert Mustacchi 66*7e3dbbacSRobert Mustacchi----SampleAfterValue---- 67*7e3dbbacSRobert MustacchiSample After Value (SAV) is the value that can be pre-loaded into the counter registers to set the point at which they will overflow. 68*7e3dbbacSRobert MustacchiTo make the counter overflow after N occurrences of the event, it should be loaded with (0xFF..FF � N) or �(N-1). On overflow a 69*7e3dbbacSRobert Mustacchihardware interrupt is generated through the Local APIC and additional architectural state can be collected in the interrupt handler. 70*7e3dbbacSRobert MustacchiThis is useful in event-based sampling. This field gives a recommended default overflow value, which may be adjusted based on 71*7e3dbbacSRobert Mustacchiworkload or tool preference. 72*7e3dbbacSRobert Mustacchi 73*7e3dbbacSRobert Mustacchi----MSRIndex---- 74*7e3dbbacSRobert MustacchiAdditional MSRs may be required for programming certain events. This field gives the address of such MSRS. 75*7e3dbbacSRobert MustacchiPotential values are: 76*7e3dbbacSRobert Mustacchi0x3F6: MSR_PEBS_LD_LAT - used to configure the Load Latency Perforamnce Monitoring Facility 77*7e3dbbacSRobert Mustacchi0x1A6/0x1A7: MSR_OFFCORE_RSP_X - used to configure the offcore response events 78*7e3dbbacSRobert Mustacchi 79*7e3dbbacSRobert Mustacchi----MSRValue---- 80*7e3dbbacSRobert MustacchiWhen an MSRIndex is used (indicated by the MSRIndex column), this field will contain the value that needs to be loaded into the 81*7e3dbbacSRobert Mustacchiregister whose address is given in MSRIndex column. For example, in the case of the load latency events, MSRValue defines the 82*7e3dbbacSRobert Mustacchilatency threshold value to write into the MSR defined in MSRIndex (0x3F6). 83*7e3dbbacSRobert Mustacchi 84*7e3dbbacSRobert Mustacchi----CollectPEBSRecord---- 85*7e3dbbacSRobert MustacchiApplies to processors that support both precise and non-precise events in Processor Event Based Sampling, such as Goldmont. 86*7e3dbbacSRobert Mustacchi0: The event cannot be programmed to collect a PEBS record. 87*7e3dbbacSRobert Mustacchi1: The event may be programmed to collect a PEBS record, but caution is advised. 88*7e3dbbacSRobert MustacchiFor instance, PEBS collection of this event may consume limited PEBS resources whereas interrupt-based sampling may be sufficient for the usage model. 89*7e3dbbacSRobert Mustacchi2: The event may programmed to collect a PEBS record, and due to the nature of the event, PEBS collection may be preferred. For instance, 90*7e3dbbacSRobert MustacchiPEBS collection of Goldmont�s HW_INTERUPTS.RECIEVED event is recommended because the hardware interrupt being counted may lead to the masking of 91*7e3dbbacSRobert Mustacchiinterrupts which would interfere with interrupt-based sampling. 92*7e3dbbacSRobert Mustacchi 93*7e3dbbacSRobert Mustacchi 94*7e3dbbacSRobert Mustacchi ----TakenAlone---- 95*7e3dbbacSRobert MustacchiThis field is set for an event which can only be sampled or counted by itself, meaning that when this event is being collected, 96*7e3dbbacSRobert Mustacchithe remaining programmable counters are not available to count any other events. 97*7e3dbbacSRobert Mustacchi 98*7e3dbbacSRobert Mustacchi----CounterMask---- 99*7e3dbbacSRobert MustacchiThis field maps to the Counter Mask (CMASK) field in IA32_PERFEVTSELx[31:24] MSR. 100*7e3dbbacSRobert Mustacchi 101*7e3dbbacSRobert Mustacchi----Invert---- 102*7e3dbbacSRobert MustacchiThis field corresponds to the Invert Counter Mask (INV) field in IA32_PERFEVTSELx[23] MSR. 103*7e3dbbacSRobert Mustacchi 104*7e3dbbacSRobert Mustacchi----AnyThread---- 105*7e3dbbacSRobert MustacchiThis field corresponds to the Any Thread (ANY) bit of IA32_PERFEVTSELx[21] MSR. 106*7e3dbbacSRobert Mustacchi 107*7e3dbbacSRobert Mustacchi----EdgeDetect---- 108*7e3dbbacSRobert MustacchiThis field corresponds to the Edge Detect (E) bit of IA32_PERFEVTSELx[18] MSR. 109*7e3dbbacSRobert Mustacchi 110*7e3dbbacSRobert Mustacchi----PEBS---- 111*7e3dbbacSRobert MustacchiA '0' in this field means that the event cannot collect a PEBS record with a Precise IP. A '1' in this field means that the event is a 112*7e3dbbacSRobert Mustacchiprecise event and can be programmed in one of two ways � as a regular event or as a PEBS event. And a '2' in this field means 113*7e3dbbacSRobert Mustacchithat the event can only be programmed as a PEBS event. 114*7e3dbbacSRobert Mustacchi 115*7e3dbbacSRobert Mustacchi----PRECISE_STORE---- 116*7e3dbbacSRobert MustacchiA '1' in this field means the event uses the Precise Store feature and Bit 3 and bit 63 in IA32_PEBS_ENABLE MSR must be set 117*7e3dbbacSRobert Mustacchito enable IA32_PMC3 as a PEBS counter and enable the precise store facility respectively. Processors based on SandyBridge and 118*7e3dbbacSRobert MustacchiIvyBridge micro-architecture offer a precise store capability that provides a means to profile store memory references in 119*7e3dbbacSRobert Mustacchithe system. 120*7e3dbbacSRobert Mustacchi 121*7e3dbbacSRobert Mustacchi----DATA_LA---- 122*7e3dbbacSRobert MustacchiA '1' in this field means that when the event is configured as a PEBS event, the Data Linear Address facility is supported. 123*7e3dbbacSRobert MustacchiThe Data Linear Address facility is a new feature added to Haswell as a replacement or extension of the precise store facility 124*7e3dbbacSRobert Mustacchiin SNB. 125*7e3dbbacSRobert Mustacchi 126*7e3dbbacSRobert Mustacchi----L1_HIT_INDICATION---- 127*7e3dbbacSRobert MustacchiA '1' in this field means that when the event is configured as a PEBS event, the DCU hit field of the PEBS record is set to 1 128*7e3dbbacSRobert Mustacchiwhen the store hits in the L1 cache and 0 when it misses. 129*7e3dbbacSRobert Mustacchi 130*7e3dbbacSRobert Mustacchi----Errata---- 131*7e3dbbacSRobert MustacchiThis field lists the known bugs that apply to the events. For the latest, up to date errata refer to 132*7e3dbbacSRobert Mustacchi 133*7e3dbbacSRobert MustacchiHaswell: 134*7e3dbbacSRobert Mustacchihttp://www.intel.com/content/dam/www/public/us/en/documents/specification-updates/4th-gen-core-family-mobile-specification-update.pdf 135*7e3dbbacSRobert Mustacchi 136*7e3dbbacSRobert MustacchiIvyBridge: 137*7e3dbbacSRobert Mustacchihttps://www-ssl.intel.com/content/dam/www/public/us/en/documents/specification-updates/3rd-gen-core-desktop-specification-update.pdf 138*7e3dbbacSRobert Mustacchi 139*7e3dbbacSRobert MustacchiSandyBridge: 140*7e3dbbacSRobert Mustacchihttps://www-ssl.intel.com/content/dam/www/public/us/en/documents/specification-updates/2nd-gen-core-family-mobile-specification-update.pdf 141*7e3dbbacSRobert Mustacchi 142*7e3dbbacSRobert Mustacchi----offcore---- 143*7e3dbbacSRobert MustacchiThis field is specific to the json format. There is only 1 file for core and offcore events in this format. This field is set to 1 for offcore events 144*7e3dbbacSRobert Mustacchiand 0 for core events. 145*7e3dbbacSRobert Mustacchi 146*7e3dbbacSRobert Mustacchi--------------------- 147*7e3dbbacSRobert MustacchiFor additional information: 148*7e3dbbacSRobert Mustacchi--------------------- 149*7e3dbbacSRobert MustacchiIntel Platform Monitoring Homepage 150*7e3dbbacSRobert Mustacchihttp://software.intel.com/en-us/platform-monitoring/ 151*7e3dbbacSRobert Mustacchi 152*7e3dbbacSRobert Mustacchihttp://software.intel.com/en-us/articles/performance-monitoring-on-intel-xeon-processor-e5-family 153*7e3dbbacSRobert Mustacchi 154*7e3dbbacSRobert Mustacchihttp://software.intel.com/en-us/articles/monitoring-integrated-memory-controller-requests-in-the-2nd-3rd-and-4th-generation-intel 155*7e3dbbacSRobert Mustacchi 156*7e3dbbacSRobert Mustacchihttp://www.intel.com/content/dam/www/public/us/en/documents/specification-updates/4th-gen-core-family-desktop-specification-update.pdf 157*7e3dbbacSRobert Mustacchi 158*7e3dbbacSRobert Mustacchi--------------------- 159*7e3dbbacSRobert MustacchiFor questions: 160*7e3dbbacSRobert Mustacchi--------------------- 161*7e3dbbacSRobert Mustacchiemail perfmon-discuss@lists.01.org 162*7e3dbbacSRobert Mustacchi 163*7e3dbbacSRobert Mustacchi--------------------- 164*7e3dbbacSRobert MustacchiNotices: 165*7e3dbbacSRobert Mustacchi--------------------- 166*7e3dbbacSRobert MustacchiINFORMATION IN THIS DOCUMENT IS PROVIDED IN CONNECTION WITH INTEL PRODUCTS. NO LICENSE, EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE, 167*7e3dbbacSRobert MustacchiTO ANY INTELLECTUAL PROPERTY RIGHTS IS GRANTED BY THIS DOCUMENT. EXCEPT AS PROVIDED IN INTEL'S TERMS AND CONDITIONS OF SALE FOR SUCH 168*7e3dbbacSRobert MustacchiPRODUCTS, INTEL ASSUMES NO LIABILITY WHATSOEVER AND INTEL DISCLAIMS ANY EXPRESS OR IMPLIED WARRANTY, RELATING TO SALE AND/OR USE OF 169*7e3dbbacSRobert MustacchiINTEL PRODUCTS INCLUDING LIABILITY OR WARRANTIES RELATING TO FITNESS FOR A PARTICULAR PURPOSE, MERCHANTABILITY, OR INFRINGEMENT OF ANY 170*7e3dbbacSRobert MustacchiPATENT, COPYRIGHT OR OTHER INTELLECTUAL PROPERTY RIGHT. 171*7e3dbbacSRobert Mustacchi 172*7e3dbbacSRobert MustacchiA "Mission Critical Application" is any application in which failure of the Intel Product could result, directly or indirectly, in 173*7e3dbbacSRobert Mustacchipersonal injury or death. SHOULD YOU PURCHASE OR USE INTEL'S PRODUCTS FOR ANY SUCH MISSION CRITICAL APPLICATION, YOU SHALL INDEMNIFY 174*7e3dbbacSRobert MustacchiAND HOLD INTEL AND ITS SUBSIDIARIES, SUBCONTRACTORS AND AFFILIATES, AND THE DIRECTORS, OFFICERS, AND EMPLOYEES OF EACH, HARMLESS AGAINST 175*7e3dbbacSRobert MustacchiALL CLAIMS COSTS, DAMAGES, AND EXPENSES AND REASONABLE ATTORNEYS' FEES ARISING OUT OF, DIRECTLY OR INDIRECTLY, ANY CLAIM OF PRODUCT 176*7e3dbbacSRobert MustacchiLIABILITY, PERSONAL INJURY, OR DEATH ARISING IN ANY WAY OUT OF SUCH MISSION CRITICAL APPLICATION, WHETHER OR NOT INTEL OR ITS SUBCONTRACTOR 177*7e3dbbacSRobert MustacchiWAS NEGLIGENT IN THE DESIGN, MANUFACTURE, OR WARNING OF THE INTEL PRODUCT OR ANY OF ITS PARTS. 178*7e3dbbacSRobert Mustacchi 179*7e3dbbacSRobert MustacchiIntel may make changes to specifications and product descriptions at any time, without notice. Designers must not rely on the absence or 180*7e3dbbacSRobert Mustacchicharacteristics of any features or instructions marked "reserved" or "undefined". Intel reserves these for future definition and shall have 181*7e3dbbacSRobert Mustacchino responsibility whatsoever for conflicts or incompatibilities arising from future changes to them. The information here is subject to 182*7e3dbbacSRobert Mustacchichange without notice. Do not finalize a design with this information. 183*7e3dbbacSRobert Mustacchi 184*7e3dbbacSRobert MustacchiThe products described in this document may contain design defects or errors known as errata which may cause the product to deviate from 185*7e3dbbacSRobert Mustacchipublished specifications. Current characterized errata are available on request. 186*7e3dbbacSRobert Mustacchi 187*7e3dbbacSRobert MustacchiContact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order. 188*7e3dbbacSRobert Mustacchi 189*7e3dbbacSRobert MustacchiCopies of documents which have an order number and are referenced in this document, or other Intel literature, may be obtained by calling 190*7e3dbbacSRobert Mustacchi1-800-548-4725, or go to: http://www.intel.com/design/literature.htm 191*7e3dbbacSRobert Mustacchi 192*7e3dbbacSRobert MustacchiCopyright � 2014 Intel Corporation. All rights reserved.