1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License (the "License"). 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9 * or http://www.opensolaris.org/os/licensing. 10 * See the License for the specific language governing permissions 11 * and limitations under the License. 12 * 13 * When distributing Covered Code, include this CDDL HEADER in each 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15 * If applicable, add the following below this CDDL HEADER, with the 16 * fields enclosed by brackets "[]" replaced with your own identifying 17 * information: Portions Copyright [yyyy] [name of copyright owner] 18 * 19 * CDDL HEADER END 20 */ 21 /* 22 * Copyright 2009 Sun Microsystems, Inc. All rights reserved. 23 * Use is subject to license terms. 24 */ 25 #ifndef _SYS_AUDIOHD_IMPL_H_ 26 #define _SYS_AUDIOHD_IMPL_H_ 27 28 #ifdef __cplusplus 29 extern "C" { 30 #endif 31 32 /* 33 * vendor IDs of PCI audio controllers 34 */ 35 #define AUDIOHD_VID_INTEL 0x8086 36 #define AUDIOHD_VID_ATI 0x1002 37 #define AUDIOHD_VID_CIRRUS 0x1013 38 #define AUDIOHD_VID_NVIDIA 0x10de 39 #define AUDIOHD_VID_REALTEK 0x10ec 40 #define AUDIOHD_VID_ANALOG 0x11d4 41 #define AUDIOHD_VID_CONEXANT 0x14f1 42 #define AUDIOHD_VID_SIGMATEL 0x8384 43 44 /* 45 * specific audiohd controller device id 46 */ 47 #define AUDIOHD_CONTROLLER_MCP51 0x10de026c 48 49 /* 50 * specific codec id used by specific vendors 51 */ 52 #define AUDIOHD_CODEC_IDT7608 0x111d7608 53 #define AUDIOHD_CODEC_IDT76B2 0x111d76b2 54 #define AUDIOHD_CODEC_AD1981 0x11d41981 55 #define AUDIOHD_CODEC_ALC272 0x10ec0272 56 #define AUDIOHD_CODEC_ALC885 0x10ec0885 57 #define AUDIOHD_CODECID_ALC888 0x10ec0888 58 #define AUDIOHD_CODECID_SONY1 0x10ec0260 59 #define AUDIOHD_CODECID_SONY2 0x10ec0262 60 #define AUDIOHD_CODEC_CX20549 0x14f15045 61 62 #define AUDIOHD_INTS 50 63 #define AUDIOHD_MAX_INTS 1500 64 #define AUDIOHD_MIN_INTS 32 65 66 #define AUDIOHD_DEV_CONFIG "onboard1" 67 #define AUDIOHD_DEV_VERSION "a" 68 69 #define AUDIOHD_FMT_PCM 0x001 70 /* 71 * Only for Intel hardware: 72 * PCI Express traffic class select register in PCI configure space 73 */ 74 #define AUDIOHD_INTEL_PCI_TCSEL 0x44 75 76 /* 77 * Only for ATI SB450: 78 * MISC control register 2 79 */ 80 #define AUDIOHD_ATI_PCI_MISC2 0x42 81 #define AUDIOHD_ATI_MISC2_SNOOP 0x02 82 #define AUDIOHDC_NID(x) x 83 #define AUDIOHDC_NULL_NODE -1 84 #define AUDIOHD_NULL_CONN ((uint_t)(-1)) 85 /* 86 * currently, only the format of 48K sample rate, 16-bit 87 * 2-channel is supported. 88 */ 89 #define AUDIOHD_FMT_PCMOUT 0x0011 90 #define AUDIOHD_FMT_PCMIN 0x0011 91 92 #define AUDIOHD_EXT_AMP_MASK 0x00010000 93 #define AUDIOHD_EXT_AMP_ENABLE 0x02 94 /* NVIDIA snoop */ 95 #define AUDIOHD_NVIDIA_SNOOP 0x0f 96 97 /* Power On/Off */ 98 #define AUDIOHD_PW_OFF 1 99 #define AUDIOHD_PW_ON 0 100 #define AUDIOHD_PW_D0 0 101 #define AUDIOHD_PW_D2 2 102 103 #define AUDIOHD_INTEL_TCS_MASK 0xf8 104 #define AUDIOHD_ATI_MISC2_MASK 0xf8 105 106 /* Pin speaker On/Off */ 107 #define AUDIOHD_SP_ON 1 108 #define AUDIOHD_SP_OFF 0 109 110 #define AUDIOHD_PORT_MAX 15 111 #define AUDIOHD_CODEC_MAX 16 112 #define AUDIOHD_MEMIO_LEN 0x4000 113 114 #define AUDIOHD_RETRY_TIMES 60 115 #define AUDIOHD_TEST_TIMES 500 116 #define AUDIOHD_OUTSTR_NUM_OFF 12 117 #define AUDIOHD_INSTR_NUM_OFF 8 118 119 #define AUDIOHD_CORB_SIZE_OFF 0x4e 120 121 #define AUDIOHD_URCAP_MASK 0x80 122 #define AUDIOHD_DTCCAP_MASK 0x4 123 #define AUDIOHD_UR_ENABLE_OFF 8 124 #define AUDIOHD_UR_TAG_MASK 0x1f 125 126 #define AUDIOHD_CIS_MASK 0x40000000 127 128 #define AUDIOHD_RIRB_UR_MASK 0x10 129 #define AUDIOHD_RIRB_CODEC_MASK 0xf 130 #define AUDIOHD_RIRB_WID_OFF 27 131 #define AUDIOHD_RIRB_INTRCNT 0x0 132 #define AUDIOHD_RIRB_WPMASK 0xff 133 134 #define AUDIOHD_FORM_MASK 0x0080 135 #define AUDIOHD_LEN_MASK 0x007f 136 #define AUDIOHD_PIN_CAP_MASK 0x00000010 137 #define AUDIOHD_PIN_CONF_MASK 0xc0000000 138 #define AUDIOHD_PIN_CON_MASK 3 139 #define AUDIOHD_PIN_CON_STEP 30 140 #define AUDIOHD_PIN_IO_MASK 0X0018 141 #define AUDIOHD_PIN_SEQ_MASK 0x0000000f 142 #define AUDIOHD_PIN_ASO_MASK 0x000000f0 143 #define AUDIOHD_PIN_ASO_OFF 0x4 144 #define AUDIOHD_PIN_DEV_MASK 0x00f00000 145 #define AUDIOHD_PIN_DEV_OFF 20 146 #define AUDIOHD_PIN_NUMS 6 147 #define AUDIOHD_PIN_NO_CONN 0x40000000 148 #define AUDIOHD_PIN_IN_ENABLE 0x20 149 #define AUDIOHD_PIN_OUT_ENABLE 0x40 150 #define AUDIOHD_PIN_PRES_OFF 0x20 151 #define AUDIOHD_PIN_CONTP_OFF 0x1e 152 #define AUDIOHD_PIN_CON_JACK 0 153 #define AUDIOHD_PIN_CON_FIXED 0x2 154 #define AUDIOHD_PIN_CONTP_MASK 0x3 155 #define AUDIOHD_PIN_VREF_L1 0x20 156 #define AUDIOHD_PIN_VREF_L2 0x10 157 #define AUDIOHD_PIN_VREF_L3 0x04 158 #define AUDIOHD_PIN_VREF_L4 0x02 159 #define AUDIOHD_PIN_VREF_OFF 8 160 #define AUDIOHD_PIN_VREF_MASK 0xff 161 #define AUDIOHD_PIN_CLR_MASK 0xf 162 #define AUDIOHD_PIN_CLR_OFF 12 163 164 165 #define AUDIOHD_VERB_ADDR_OFF 28 166 #define AUDIOHD_VERB_NID_OFF 20 167 #define AUDIOHD_VERB_CMD_OFF 8 168 #define AUDIOHD_VERB_CMD16_OFF 16 169 170 #define AUDIOHD_RING_MAX_SIZE 0x00ff 171 #define AUDIOHD_REC_TAG_OFF 4 172 #define AUDIOHD_PLAY_TAG_OFF 4 173 #define AUDIOHD_PLAY_CTL_OFF 2 174 #define AUDIOHD_REC_CTL_OFF 2 175 176 #define AUDIOHD_SPDIF_ON 1 177 #define AUDIOHD_SPDIF_MASK 0x00ff 178 179 #define AUDIOHD_GAIN_OFF 8 180 181 #define AUDIOHD_CODEC_STR_OFF 16 182 #define AUDIOHD_CODEC_STR_MASK 0x000000ff 183 #define AUDIOHD_CODEC_NUM_MASK 0x000000ff 184 #define AUDIOHD_CODEC_TYPE_MASK 0x000000ff 185 186 #define AUDIOHD_ROUNDUP(x, algn) (((x) + ((algn) - 1)) & ~((algn) - 1)) 187 #define AUDIOHD_FRAGFR_ALIGN 64 188 #define AUDIOHD_BDLE_BUF_ALIGN 128 189 #define AUDIOHD_CMDIO_ENT_MASK 0x00ff /* 256 entries for CORB/RIRB */ 190 #define AUDIOHD_CDBIO_CORB_LEN 1024 /* 256 entries for CORB, 1024B */ 191 #define AUDIOHD_CDBIO_RIRB_LEN 2048 /* 256 entries for RIRB, 2048B */ 192 #define AUDIOHD_BDLE_NUMS 4 /* 4 entires for record/play BD list */ 193 194 #define AUDIOHD_PORT_UNMUTE (0xffffffff) 195 196 /* 197 * Audio registers of high definition 198 */ 199 #define AUDIOHD_REG_GCAP 0x00 200 #define AUDIOHDR_GCAP_OUTSTREAMS 0xf000 201 #define AUDIOHDR_GCAP_INSTREAMS 0x0f00 202 #define AUDIOHDR_GCAP_BSTREAMS 0x00f8 203 #define AUDIOHDR_GCAP_NSDO 0x0006 204 #define AUDIOHDR_GCAP_64OK 0x0001 205 206 #define AUDIOHD_REG_VMIN 0x02 207 #define AUDIOHD_REG_VMAJ 0x03 208 #define AUDIOHD_REG_OUTPAY 0x04 209 #define AUDIOHD_REG_INPAY 0x06 210 #define AUDIOHD_REG_GCTL 0x08 211 #define AUDIOHD_REG_WAKEEN 0x0C 212 #define AUDIOHD_REG_STATESTS 0x0E 213 #define AUDIOHD_STATESTS_BIT_SDINS 0x7F 214 215 #define AUDIOHD_REG_GSTS 0x10 216 #define AUDIOHD_REG_INTCTL 0x20 217 #define AUDIOHD_INTCTL_BIT_GIE 0x80000000 218 #define AUDIOHD_INTCTL_BIT_CIE 0x40000000 219 #define AUDIOHD_INTCTL_BIT_SIE 0x3FFFFFFF 220 221 222 #define AUDIOHD_REG_INTSTS 0x24 223 #define AUDIOHD_INTSTS_BIT_GIS 0x80000000 224 #define AUDIOHD_INTSTS_BIT_CIS 0x40000000 225 #define AUDIOHD_INTSTS_BIT_SINTS (0x3fffffff) 226 227 #define AUDIOHD_REG_WALCLK 0x30 228 #define AUDIOHD_REG_SYNC 0x38 229 230 #define AUDIOHD_REG_CORBLBASE 0x40 231 #define AUDIOHD_REG_CORBUBASE 0x44 232 #define AUDIOHD_REG_CORBWP 0x48 233 #define AUDIOHD_REG_CORBRP 0x4A 234 #define AUDIOHD_REG_CORBCTL 0x4C 235 #define AUDIOHD_REG_CORBST 0x4D 236 #define AUDIOHD_REG_CORBSIZE 0x4E 237 238 #define AUDIOHD_REG_RIRBLBASE 0x50 239 #define AUDIOHD_REG_RIRBUBASE 0x54 240 #define AUDIOHD_REG_RIRBWP 0x58 241 #define AUDIOHD_REG_RINTCNT 0x5A 242 #define AUDIOHD_REG_RIRBCTL 0x5C 243 #define AUDIOHD_REG_RIRBSTS 0x5D 244 #define AUDIOHD_REG_RIRBSIZE 0x5E 245 246 #define AUDIOHD_REG_IC 0x60 247 #define AUDIOHD_REG_IR 0x64 248 #define AUDIOHD_REG_IRS 0x68 249 #define AUDIOHD_REG_DPLBASE 0x70 250 #define AUDIOHD_REG_DPUBASE 0x74 251 252 #define AUDIOHD_REG_SD_BASE 0x80 253 #define AUDIOHD_REG_SD_LEN 0x20 254 255 /* 256 * Offset of Stream Descriptor Registers 257 */ 258 #define AUDIOHD_SDREG_OFFSET_CTL 0x00 259 #define AUDIOHD_SDREG_OFFSET_STS 0x03 260 #define AUDIOHD_SDREG_OFFSET_LPIB 0x04 261 #define AUDIOHD_SDREG_OFFSET_CBL 0x08 262 #define AUDIOHD_SDREG_OFFSET_LVI 0x0c 263 #define AUDIOHD_SDREG_OFFSET_FIFOW 0x0e 264 #define AUDIOHD_SDREG_OFFSET_FIFOSIZE 0x10 265 #define AUDIOHD_SDREG_OFFSET_FORMAT 0x12 266 #define AUDIOHD_SDREG_OFFSET_BDLPL 0x18 267 #define AUDIOHD_SDREG_OFFSET_BDLPU 0x1c 268 269 /* bits for stream descriptor control reg */ 270 #define AUDIOHDR_SD_CTL_DEIE 0x000010 271 #define AUDIOHDR_SD_CTL_FEIE 0x000008 272 #define AUDIOHDR_SD_CTL_IOCE 0x000004 273 #define AUDIOHDR_SD_CTL_SRUN 0x000002 274 #define AUDIOHDR_SD_CTL_SRST 0x000001 275 #define AUDIOHDR_SD_CTL_INTS \ 276 (AUDIOHDR_SD_CTL_DEIE | \ 277 AUDIOHDR_SD_CTL_FEIE | \ 278 AUDIOHDR_SD_CTL_IOCE) 279 280 281 /* bits for stream descriptor status register */ 282 #define AUDIOHDR_SD_STS_BCIS 0x0004 283 #define AUDIOHDR_SD_STS_FIFOE 0x0008 284 #define AUDIOHDR_SD_STS_DESE 0x0010 285 #define AUDIOHDR_SD_STS_FIFORY 0x0020 286 #define AUDIOHDR_SD_STS_INTRS \ 287 (AUDIOHDR_SD_STS_BCIS | \ 288 AUDIOHDR_SD_STS_FIFOE | \ 289 AUDIOHDR_SD_STS_DESE) 290 291 292 /* bits for GCTL register */ 293 #define AUDIOHDR_GCTL_CRST 0x00000001 294 #define AUDIOHDR_GCTL_URESPE 0x00000100 295 296 /* bits for CORBRP register */ 297 #define AUDIOHDR_CORBRP_RESET 0x8000 298 #define AUDIOHDR_CORBRP_WPTR 0x00ff 299 300 /* bits for CORBCTL register */ 301 #define AUDIOHDR_CORBCTL_CMEIE 0x01 302 #define AUDIOHDR_CORBCTL_DMARUN 0x02 303 304 /* bits for CORB SIZE register */ 305 #define AUDIOHDR_CORBSZ_8 0 306 #define AUDIOHDR_CORBSZ_16 1 307 #define AUDIOHDR_CORBSZ_256 2 308 309 /* bits for RIRBCTL register */ 310 #define AUDIOHDR_RIRBCTL_RINTCTL 0x01 311 #define AUDIOHDR_RIRBCTL_DMARUN 0x02 312 #define AUDIOHDR_RIRBCTL_RIRBOIC 0x04 313 #define AUDIOHDR_RIRBCTL_RSTINT 0xfe 314 315 /* bits for RIRBWP register */ 316 #define AUDIOHDR_RIRBWP_RESET 0x8000 317 #define AUDIOHDR_RIRBWP_WPTR 0x00ff 318 319 /* bits for RIRB SIZE register */ 320 #define AUDIOHDR_RIRBSZ_8 0 321 #define AUDIOHDR_RIRBSZ_16 1 322 #define AUDIOHDR_RIRBSZ_256 2 323 324 #define AUDIOHD_BDLE_RIRB_SDI 0x0000000f 325 #define AUDIOHD_BDLE_RIRB_UNSOLICIT 0x00000010 326 327 /* HD spec: ID of Root node is 0 */ 328 #define AUDIOHDC_NODE_ROOT 0x00 329 330 /* HD spec: ID of audio function group is "1" */ 331 #define AUDIOHDC_AUDIO_FUNC_GROUP 1 332 333 /* 334 * HD audio verbs can be either 12-bit or 4-bit in length. 335 */ 336 #define AUDIOHDC_12BIT_VERB_MASK 0xfffff000 337 #define AUDIOHDC_4BIT_VERB_MASK 0xfffffff0 338 339 #define AUDIOHDC_SAMPR48000 48000 340 #define AUDIOHDC_MAX_BEEP_GEN 12000 341 #define AUDIOHDC_MIX_BEEP_GEN 47 342 #define AUDIOHDC_MUTE_BEEP_GEN 0x0 343 344 /* 345 * 12-bit verbs 346 */ 347 #define AUDIOHDC_VERB_GET_PARAM 0xf00 348 349 #define AUDIOHDC_VERB_GET_CONN_SEL 0xf01 350 #define AUDIOHDC_VERB_SET_CONN_SEL 0x701 351 352 #define AUDIOHDC_VERB_GET_CONN_LIST_ENT 0xf02 353 #define AUDIOHDC_VERB_GET_PROCESS_STATE 0xf03 354 #define AUDIOHDC_VERB_GET_SDI_SEL 0xf04 355 356 #define AUDIOHDC_VERB_GET_POWER_STATE 0xf05 357 #define AUDIOHDC_VERB_SET_POWER_STATE 0x705 358 359 #define AUDIOHDC_VERB_GET_STREAM_CHANN 0xf06 360 #define AUDIOHDC_VERB_SET_STREAM_CHANN 0x706 361 362 #define AUDIOHDC_VERB_GET_PIN_CTRL 0xf07 363 #define AUDIOHDC_VERB_SET_PIN_CTRL 0x707 364 365 #define AUDIOHDC_VERB_GET_UNS_ENABLE 0xf08 366 367 #define AUDIOHDC_VERB_GET_PIN_SENSE 0xf09 368 #define AUDIOHDC_VERB_EXEC_PIN_SENSE 0x709 369 370 #define AUDIOHDC_VERB_GET_BEEP_GEN 0xf0a 371 #define AUDIOHDC_VERB_SET_BEEP_GEN 0x70a 372 373 #define AUDIOHDC_VERB_GET_EAPD 0xf0c 374 #define AUDIOHDC_VERB_SET_EAPD 0x70c 375 376 #define AUDIOHDC_VERB_GET_DEFAULT_CONF 0xf1c 377 #define AUDIOHDC_VERB_GET_SPDIF_CTL 0xf0d 378 #define AUDIOHDC_VERB_SET_SPDIF_LCL 0x70d 379 380 #define AUDIOHDC_VERB_SET_URCTRL 0x708 381 #define AUDIOHDC_VERB_GET_PIN_SENSE 0xf09 382 383 #define AUDIOHDC_VERB_GET_GPIO_MASK 0xf16 384 #define AUDIOHDC_VERB_SET_GPIO_MASK 0x716 385 386 #define AUDIOHDC_VERB_GET_GPIO_DIREC 0xf17 387 #define AUDIOHDC_VERB_SET_GPIO_DIREC 0x717 388 389 #define AUDIOHDC_VERB_GET_GPIO_DATA 0xf15 390 #define AUDIOHDC_VERB_SET_GPIO_DATA 0x715 391 392 #define AUDIOHDC_VERB_GET_GPIO_STCK 0xf1a 393 #define AUDIOHDC_VERB_SET_GPIO_STCK 0x71a 394 395 #define AUDIOHDC_GPIO_ENABLE 0xff 396 #define AUDIOHDC_GPIO_DIRECT 0xf1 397 398 #define AUDIOHDC_GPIO_DATA_CTRL 0xff 399 #define AUDIOHDC_GPIO_STCK_CTRL 0xff 400 /* 401 * 4-bit verbs 402 */ 403 #define AUDIOHDC_VERB_GET_CONV_FMT 0xa 404 #define AUDIOHDC_VERB_SET_CONV_FMT 0x2 405 406 #define AUDIOHDC_VERB_GET_AMP_MUTE 0xb 407 #define AUDIOHDC_VERB_SET_AMP_MUTE 0x3 408 #define AUDIOHDC_VERB_SET_BEEP_VOL 0x3A0 409 410 /* 411 * parameters of nodes 412 */ 413 #define AUDIOHDC_PAR_VENDOR_ID 0x00 414 #define AUDIOHDC_PAR_SUBSYS_ID 0x01 415 #define AUDIOHDC_PAR_REV_ID 0x02 416 #define AUDIOHDC_PAR_NODE_COUNT 0x04 417 #define AUDIOHDC_PAR_FUNCTION_TYPE 0x05 418 #define AUDIOHDC_PAR_AUDIO_FG_CAP 0x08 419 #define AUDIOHDC_PAR_AUDIO_WID_CAP 0x09 420 #define AUDIOHDC_PAR_PCM 0x0a 421 #define AUDIOHDC_PAR_STREAM 0x0b 422 #define AUDIOHDC_PAR_PIN_CAP 0x0c 423 #define AUDIOHDC_PAR_INAMP_CAP 0x0d 424 #define AUDIOHDC_PAR_CONNLIST_LEN 0x0e 425 #define AUDIOHDC_PAR_POWER_STATE 0x0f 426 #define AUDIOHDC_PAR_PROC_CAP 0x10 427 #define AUDIOHDC_PAR_GPIO_CAP 0x11 428 #define AUDIOHDC_PAR_OUTAMP_CAP 0x12 429 430 /* 431 * bits for get/set amplifier gain/mute 432 */ 433 #define AUDIOHDC_AMP_SET_OUTPUT 0x8000 434 #define AUDIOHDC_AMP_SET_INPUT 0x4000 435 #define AUDIOHDC_AMP_SET_LEFT 0x2000 436 #define AUDIOHDC_AMP_SET_RIGHT 0x1000 437 #define AUDIOHDC_AMP_SET_MUTE 0x0080 438 #define AUDIOHDC_AMP_SET_LNR 0x3000 439 #define AUDIOHDC_AMP_SET_LR_INPUT 0x7000 440 #define AUDIOHDC_AMP_SET_LR_OUTPUT 0xb000 441 #define AUDIOHDC_AMP_SET_INDEX_OFFSET 8 442 #define AUDIOHDC_AMP_SET_GAIN_MASK 0x007f 443 #define AUDIOHDC_GAIN_MAX 0x7f 444 #define AUDIOHDC_GAIN_BITS 7 445 #define AUDIOHDC_GAIN_DEFAULT 0x0f 446 447 #define AUDIOHDC_AMP_GET_OUTPUT 0x8000 448 #define AUDIOHDC_AMP_GET_INPUT 0x0000 449 450 /* value used to set max volume for left output */ 451 #define AUDIOHDC_AMP_LOUT_MAX \ 452 (AUDIOHDC_AMP_SET_OUTPUT | \ 453 AUDIOHDC_AMP_SET_LEFT | \ 454 AUDIOHDC_GAIN_MAX) 455 456 /* value used to set max volume for right output */ 457 #define AUDIOHDC_AMP_ROUT_MAX \ 458 (AUDIOHDC_AMP_SET_OUTPUT | \ 459 AUDIOHDC_AMP_SET_RIGHT | \ 460 AUDIOHDC_GAIN_MAX) 461 462 463 /* 464 * Bits for pin widget control verb 465 */ 466 #define AUDIOHDC_PIN_CONTROL_HP_ENABLE 0x80 467 #define AUDIOHDC_PIN_CONTROL_OUT_ENABLE 0x40 468 #define AUDIOHDC_PIN_CONTROL_IN_ENABLE 0x20 469 470 /* 471 * Bits for Amplifier capabilities 472 */ 473 #define AUDIOHDC_AMP_CAP_MUTE_CAP 0x80000000 474 #define AUDIOHDC_AMP_CAP_STEP_SIZE 0x007f0000 475 #define AUDIOHDC_AMP_CAP_STEP_NUMS 0x00007f00 476 #define AUDIOHDC_AMP_CAP_0DB_OFFSET 0x0000007f 477 478 479 /* 480 * Bits for Audio Widget Capabilities 481 */ 482 #define AUDIOHD_WIDCAP_STEREO 0x00000001 483 #define AUDIOHD_WIDCAP_INAMP 0x00000002 484 #define AUDIOHD_WIDCAP_OUTAMP 0x00000004 485 #define AUDIOHD_WIDCAP_AMP_OVRIDE 0x00000008 486 #define AUDIOHD_WIDCAP_FMT_OVRIDE 0x00000010 487 #define AUDIOHD_WIDCAP_STRIP 0x00000020 488 #define AUDIOHD_WIDCAP_PROC_WID 0x00000040 489 #define AUDIOHD_WIDCAP_UNSOL 0x00000080 490 #define AUDIOHD_WIDCAP_CONNLIST 0x00000100 491 #define AUDIOHD_WIDCAP_DIGIT 0x00000200 492 #define AUDIOHD_WIDCAP_PWRCTRL 0x00000400 493 #define AUDIOHD_WIDCAP_LRSWAP 0x00000800 494 #define AUDIOHD_WIDCAP_TYPE 0x00f00000 495 #define AUDIOHD_WIDCAP_TO_WIDTYPE(wcap) \ 496 ((wcap & AUDIOHD_WIDCAP_TYPE) >> 20) 497 498 499 #define AUDIOHD_CODEC_FAILURE (uint32_t)(-1) 500 501 /* 502 * buffer descriptor list entry of stream descriptor 503 */ 504 typedef struct { 505 uint64_t sbde_addr; 506 uint32_t sbde_len; 507 uint32_t 508 sbde_ioc: 1, 509 reserved: 31; 510 }sd_bdle_t; 511 512 513 #define AUDIOHD_PLAY_STARTED 0x00000001 514 #define AUDIOHD_PLAY_EMPTY 0x00000002 515 #define AUDIOHD_PLAY_PAUSED 0x00000004 516 #define AUDIOHD_RECORD_STARTED 0x00000008 517 518 enum audiohda_widget_type { 519 WTYPE_AUDIO_OUT = 0, 520 WTYPE_AUDIO_IN, 521 WTYPE_AUDIO_MIX, 522 WTYPE_AUDIO_SEL, 523 WTYPE_PIN, 524 WTYPE_POWER, 525 WTYPE_VOL_KNOB, 526 WTYPE_BEEP, 527 WTYPE_VENDOR = 0xf 528 }; 529 530 enum audiohda_device_type { 531 DTYPE_LINEOUT = 0, 532 DTYPE_SPEAKER, 533 DTYPE_HP_OUT, 534 DTYPE_CD, 535 DTYPE_SPDIF_OUT, 536 DTYPE_DIGIT_OUT, 537 DTYPE_MODEM_SIDE, 538 DTYPE_MODEM_HNAD_SIDE, 539 DTYPE_LINE_IN, 540 DTYPE_AUX, 541 DTYPE_MIC_IN, 542 DTYPE_TEL, 543 DTYPE_SPDIF_IN, 544 DTYPE_DIGIT_IN, 545 DTYPE_OTHER = 0x0f, 546 }; 547 548 enum audiohd_pin_color { 549 AUDIOHD_PIN_UNKNOWN = 0, 550 AUDIOHD_PIN_BLACK, 551 AUDIOHD_PIN_GREY, 552 AUDIOHD_PIN_BLUE, 553 AUDIOHD_PIN_GREEN, 554 AUDIOHD_PIN_RED, 555 AUDIOHD_PIN_ORANGE, 556 AUDIOHD_PIN_YELLOW, 557 AUDIOHD_PIN_PURPLE, 558 AUDIOHD_PIN_PINK, 559 AUDIOHD_PIN_WHITE = 0xe, 560 AUDIOHD_PIN_OTHER = 0xf, 561 }; 562 563 #define CTRL_NUM 16 564 565 /* values for audiohd_widget.path_flags */ 566 #define AUDIOHD_PATH_DAC (1 << 0) 567 #define AUDIOHD_PATH_ADC (1 << 1) 568 #define AUDIOHD_PATH_MON (1 << 2) 569 #define AUDIOHD_PATH_NOMON (1 << 3) 570 #define AUDIOHD_PATH_BEEP (1 << 4) 571 572 typedef struct audiohd_path audiohd_path_t; 573 typedef struct audiohd_widget audiohd_widget_t; 574 typedef struct audiohd_state audiohd_state_t; 575 typedef struct audiohd_pin audiohd_pin_t; 576 typedef struct hda_codec hda_codec_t; 577 typedef uint32_t wid_t; /* id of widget */ 578 typedef struct audiohd_entry_prop audiohd_entry_prop_t; 579 typedef enum audiohda_device_type audiohda_device_type_t; 580 typedef enum audiohd_pin_color audiohd_pin_color_t; 581 582 #define AUDIOHD_MAX_WIDGET 128 583 #define AUDIOHD_MAX_CONN 16 584 #define AUDIOHD_MAX_PINS 16 585 #define AUDIOHD_MAX_DEPTH 8 586 587 struct audiohd_entry_prop { 588 uint32_t conn_len; 589 uint32_t mask_range; 590 uint32_t mask_wid; 591 wid_t input_wid; 592 int conns_per_entry; 593 int bits_per_conn; 594 }; 595 struct audiohd_widget { 596 wid_t wid_wid; 597 hda_codec_t *codec; 598 enum audiohda_widget_type type; 599 600 uint32_t widget_cap; 601 uint32_t pcm_format; 602 uint32_t inamp_cap; 603 uint32_t outamp_cap; 604 605 uint32_t path_flags; 606 607 int out_weight; 608 int in_weight; 609 int finish; 610 611 /* 612 * wid of possible & selected input connections 613 */ 614 wid_t avail_conn[AUDIOHD_MAX_CONN]; 615 wid_t selconn; 616 /* 617 * for monitor path 618 */ 619 wid_t selmon[AUDIOHD_MAX_CONN]; 620 uint16_t used; 621 622 /* 623 * available (input) connections. 0 means this widget 624 * has fixed connection 625 */ 626 int nconns; 627 628 /* 629 * pointer to struct depending on widget type: 630 * 1. DAC audiohd_ostream_t 631 * 2. ADC audiohd_istream_t 632 * 3. PIN audiohd_pin_t 633 */ 634 void *priv; 635 }; 636 637 #define AUDIOHD_FLAG_LINEOUT (1 << 0) 638 #define AUDIOHD_FLAG_SPEAKER (1 << 1) 639 #define AUDIOHD_FLAG_HP (1 << 2) 640 #define AUDIOHD_FLAG_MONO (1 << 3) 641 642 #define AUDIOHD_MAX_MIXER 5 643 #define AUDIOHD_MAX_PIN 4 644 645 #define PORT_DAC 0 646 #define PORT_ADC 1 647 #define PORT_MAX 2 648 typedef enum { 649 PLAY = 0, 650 RECORD = 1, 651 BEEP = 2, 652 } path_type_t; 653 654 struct audiohd_path { 655 wid_t adda_wid; 656 wid_t beep_wid; 657 658 wid_t pin_wid[AUDIOHD_MAX_PINS]; 659 int sum_selconn[AUDIOHD_MAX_PINS]; 660 int mon_wid[AUDIOHD_MAX_PIN][AUDIOHD_MAX_MIXER]; 661 int pin_nums; 662 int maxmixer[AUDIOHD_MAX_PINS]; 663 664 path_type_t path_type; 665 666 wid_t mute_wid; 667 int mute_dir; 668 wid_t gain_wid; 669 int gain_dir; 670 uint32_t gain_bits; 671 672 uint32_t pin_outputs; 673 uint8_t tag; 674 675 hda_codec_t *codec; 676 677 wid_t sum_wid; 678 679 audiohd_state_t *statep; 680 }; 681 682 typedef struct audiohd_port 683 { 684 uint8_t nchan; 685 int index; 686 uint16_t regoff; 687 boolean_t started; 688 boolean_t triggered; 689 690 unsigned fragfr; 691 unsigned nframes; 692 uint64_t count; 693 int curpos; 694 int intrs; 695 696 uint_t format; 697 unsigned sync_dir; 698 699 ddi_dma_handle_t samp_dmah; 700 ddi_acc_handle_t samp_acch; 701 size_t samp_size; 702 caddr_t samp_kaddr; 703 uint64_t samp_paddr; 704 705 ddi_dma_handle_t bdl_dmah; 706 ddi_acc_handle_t bdl_acch; 707 size_t bdl_size; 708 caddr_t bdl_kaddr; 709 uint64_t bdl_paddr; 710 711 audio_engine_t *engine; 712 audiohd_state_t *statep; 713 }audiohd_port_t; 714 715 typedef struct audiohd_ctrl 716 { 717 audiohd_state_t *statep; 718 audio_ctrl_t *ctrl; 719 uint32_t num; 720 uint64_t val; 721 } audiohd_ctrl_t; 722 723 struct audiohd_pin { 724 audiohd_pin_t *next; 725 wid_t wid; 726 wid_t mute_wid; /* node used to mute this pin */ 727 int mute_dir; /* 1: input, 2: output */ 728 wid_t gain_wid; /* node for gain control */ 729 int gain_dir; /* _OUTPUT/_INPUT */ 730 uint32_t gain_bits; 731 732 uint8_t vrefvalue; /* value of VRef */ 733 734 uint32_t cap; 735 uint32_t config; 736 uint32_t ctrl; 737 uint32_t assoc; 738 uint32_t seq; 739 wid_t adc_dac_wid; /* AD/DA wid which can route to this pin */ 740 wid_t beep_wid; 741 int no_phys_conn; 742 enum audiohda_device_type device; 743 744 /* 745 * mg_dir, mg_gain, mg_wid are used to store the monitor gain control 746 * widget wid. 747 */ 748 int mg_dir[AUDIOHD_MAX_CONN]; 749 int mg_gain[AUDIOHD_MAX_CONN]; 750 int mg_wid[AUDIOHD_MAX_CONN]; 751 int num; 752 int finish; 753 754 }; 755 756 typedef struct { 757 ddi_dma_handle_t ad_dmahdl; 758 ddi_acc_handle_t ad_acchdl; 759 caddr_t ad_vaddr; /* virtual addr */ 760 uint64_t ad_paddr; /* physical addr */ 761 size_t ad_req_sz; /* required size of memory */ 762 size_t ad_real_sz; /* real size of memory */ 763 } audiohd_dma_t; 764 765 struct hda_codec { 766 uint8_t index; /* codec address */ 767 uint32_t vid; /* vendor id and device id */ 768 uint32_t revid; /* revision id */ 769 wid_t wid_afg; /* id of AFG */ 770 wid_t first_wid; /* wid of 1st subnode of AFG */ 771 wid_t last_wid; /* wid of the last subnode of AFG */ 772 int nnodes; /* # of subnodes of AFG */ 773 uint8_t nistream; 774 775 uint32_t outamp_cap; 776 uint32_t inamp_cap; 777 uint32_t stream_format; 778 uint32_t pcm_format; 779 780 audiohd_state_t *soft_statep; 781 782 /* use wid as index to the array of widget pointers */ 783 audiohd_widget_t *widget[AUDIOHD_MAX_WIDGET]; 784 785 786 audiohd_port_t *port[AUDIOHD_PORT_MAX]; 787 uint8_t portnum; 788 audiohd_pin_t *first_pin; 789 }; 790 791 #define AUDIOHD_MAX_ASSOC 15 792 struct audiohd_state { 793 dev_info_t *hda_dip; 794 kstat_t *hda_ksp; 795 kmutex_t hda_mutex; 796 uint32_t hda_flags; 797 798 boolean_t soft_volume; 799 800 caddr_t hda_reg_base; 801 ddi_acc_handle_t hda_pci_handle; 802 ddi_acc_handle_t hda_reg_handle; 803 804 ddi_intr_handle_t *htable; /* For array of interrupts */ 805 boolean_t intr_added; 806 int intr_type; /* What type of interrupt */ 807 int intr_rqst; /* # of request intrs count */ 808 int intr_cnt; /* # of intrs count returned */ 809 uint_t intr_pri; /* Interrupt priority */ 810 int intr_cap; /* Interrupt capabilities */ 811 boolean_t msi_enable; 812 813 audiohd_dma_t hda_dma_corb; 814 audiohd_dma_t hda_dma_rirb; 815 816 817 uint8_t hda_rirb_rp; /* read pointer for rirb */ 818 uint16_t hda_codec_mask; 819 820 821 audio_dev_t *adev; 822 uint32_t devid; 823 824 825 int hda_pint_freq; /* play intr frequence */ 826 int hda_rint_freq; /* record intr frequence */ 827 828 int hda_input_streams; /* # of input stream */ 829 int hda_output_streams; /* # of output stream */ 830 int hda_streams_nums; /* # of stream */ 831 832 uint_t hda_play_regbase; 833 uint_t hda_record_regbase; 834 835 uint_t hda_play_stag; /* tag of playback stream */ 836 uint_t hda_record_stag; /* tag of record stream */ 837 uint_t hda_play_lgain; /* left gain for playback */ 838 uint_t hda_play_rgain; /* right gain for playback */ 839 840 /* 841 * Now, for the time being, we add some fields 842 * for parsing codec topology 843 */ 844 hda_codec_t *codec[AUDIOHD_CODEC_MAX]; 845 /* 846 * Suspend/Resume used fields 847 */ 848 boolean_t suspended; 849 boolean_t monitor_unsupported; 850 851 audiohd_path_t *path[AUDIOHD_PORT_MAX]; 852 uint8_t pathnum; 853 audiohd_port_t *port[PORT_MAX]; 854 uint8_t pchan; 855 uint8_t rchan; 856 857 uint64_t inmask; 858 859 uint_t hda_out_ports; 860 uint_t in_port; 861 862 /* 863 * Controls 864 */ 865 audiohd_ctrl_t *controls[CTRL_NUM]; 866 867 /* for multichannel */ 868 uint8_t chann[AUDIOHD_MAX_ASSOC]; 869 uint8_t assoc; 870 871 }; 872 873 874 /* 875 * Operation for high definition audio control system bus 876 * interface registers 877 */ 878 #define AUDIOHD_REG_GET8(reg) \ 879 ddi_get8(statep->hda_reg_handle, \ 880 (void *)((char *)statep->hda_reg_base + (reg))) 881 882 #define AUDIOHD_REG_GET16(reg) \ 883 ddi_get16(statep->hda_reg_handle, \ 884 (void *)((char *)statep->hda_reg_base + (reg))) 885 886 #define AUDIOHD_REG_GET32(reg) \ 887 ddi_get32(statep->hda_reg_handle, \ 888 (void *)((char *)statep->hda_reg_base + (reg))) 889 890 #define AUDIOHD_REG_GET64(reg) \ 891 ddi_get64(statep->hda_reg_handle, \ 892 (void *)((char *)statep->hda_reg_base + (reg))) 893 894 #define AUDIOHD_REG_SET8(reg, val) \ 895 ddi_put8(statep->hda_reg_handle, \ 896 (void *)((char *)statep->hda_reg_base + (reg)), (val)) 897 898 #define AUDIOHD_REG_SET16(reg, val) \ 899 ddi_put16(statep->hda_reg_handle, \ 900 (void *)((char *)statep->hda_reg_base + (reg)), (val)) 901 902 #define AUDIOHD_REG_SET32(reg, val) \ 903 ddi_put32(statep->hda_reg_handle, \ 904 (void *)((char *)statep->hda_reg_base + (reg)), (val)) 905 906 #define AUDIOHD_REG_SET64(reg, val) \ 907 ddi_put64(statep->hda_reg_handle, \ 908 (void *)((char *)statep->hda_reg_base + (reg)), (val)) 909 910 911 /* 912 * enable a pin widget to output 913 */ 914 #define AUDIOHD_ENABLE_PIN_OUT(statep, caddr, wid) \ 915 { \ 916 uint32_t lTmp; \ 917 \ 918 lTmp = audioha_codec_verb_get(statep, caddr, wid, \ 919 AUDIOHDC_VERB_GET_PIN_CTRL, 0); \ 920 if (lTmp == AUDIOHD_CODEC_FAILURE) \ 921 return (DDI_FAILURE); \ 922 lTmp = audioha_codec_verb_get(statep, caddr, wid, \ 923 AUDIOHDC_VERB_SET_PIN_CTRL, \ 924 (lTmp | AUDIOHDC_PIN_CONTROL_OUT_ENABLE | \ 925 AUDIOHDC_PIN_CONTROL_HP_ENABLE)); \ 926 if (lTmp == AUDIOHD_CODEC_FAILURE) \ 927 return (DDI_FAILURE); \ 928 } 929 930 /* 931 * disable output pin 932 */ 933 #define AUDIOHD_DISABLE_PIN_OUT(statep, caddr, wid) \ 934 { \ 935 uint32_t lTmp; \ 936 \ 937 lTmp = audioha_codec_verb_get(statep, caddr, wid, \ 938 AUDIOHDC_VERB_GET_PIN_CTRL, 0); \ 939 if (lTmp == AUDIOHD_CODEC_FAILURE) \ 940 return (DDI_FAILURE); \ 941 lTmp = audioha_codec_verb_get(statep, caddr, wid, \ 942 AUDIOHDC_VERB_SET_PIN_CTRL, \ 943 (lTmp & ~AUDIOHDC_PIN_CONTROL_OUT_ENABLE)); \ 944 if (lTmp == AUDIOHD_CODEC_FAILURE) \ 945 return (DDI_FAILURE); \ 946 } 947 948 /* 949 * enable a pin widget to input 950 */ 951 #define AUDIOHD_ENABLE_PIN_IN(statep, caddr, wid) \ 952 { \ 953 (void) audioha_codec_verb_get(statep, caddr, wid, \ 954 AUDIOHDC_VERB_SET_PIN_CTRL, AUDIOHDC_PIN_CONTROL_IN_ENABLE | 4); \ 955 } 956 957 958 /* 959 * disable input pin 960 */ 961 #define AUDIOHD_DISABLE_PIN_IN(statep, caddr, wid) \ 962 { \ 963 uint32_t lTmp; \ 964 \ 965 lTmp = audioha_codec_verb_get(statep, caddr, wid, \ 966 AUDIOHDC_VERB_GET_PIN_CTRL, 0); \ 967 if (lTmp == AUDIOHD_CODEC_FAILURE) \ 968 return (DDI_FAILURE); \ 969 lTmp = audioha_codec_verb_get(statep, caddr, wid, \ 970 AUDIOHDC_VERB_SET_PIN_CTRL, \ 971 (lTmp & ~AUDIOHDC_PIN_CONTROL_IN_ENABLE)); \ 972 if (lTmp == AUDIOHD_CODEC_FAILURE) \ 973 return (DDI_FAILURE); \ 974 } 975 976 /* 977 * unmute an output pin 978 */ 979 #define AUDIOHD_NODE_UNMUTE_OUT(statep, caddr, wid) \ 980 { \ 981 if (audioha_codec_4bit_verb_get(statep, \ 982 caddr, wid, AUDIOHDC_VERB_SET_AMP_MUTE, \ 983 AUDIOHDC_AMP_SET_LR_OUTPUT | AUDIOHDC_GAIN_MAX) == \ 984 AUDIOHD_CODEC_FAILURE) \ 985 return (DDI_FAILURE); \ 986 } 987 988 /* 989 * check volume adjust value of 2 channels control 990 */ 991 #define AUDIOHD_CHECK_2CHANNELS_VOLUME(value) \ 992 { \ 993 if ((value) & ~0xffff) \ 994 return (EINVAL); \ 995 if ((((value) & 0xff00) >> 8) > 100 || \ 996 ((value) & 0xff) > 100) \ 997 return (EINVAL); \ 998 } 999 1000 /* 1001 * check volume adjust value of mono channel control 1002 */ 1003 #define AUDIOHD_CHECK_CHANNEL_VOLUME(value) \ 1004 { \ 1005 if ((value) & ~0xff) \ 1006 return (EINVAL); \ 1007 if (((value) & 0xff) > 100) \ 1008 return (EINVAL); \ 1009 } 1010 1011 #ifdef __cplusplus 1012 } 1013 #endif 1014 1015 #endif /* _SYS_AUDIOHD_IMPL_H_ */ 1016