1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License (the "License"). 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9 * or http://www.opensolaris.org/os/licensing. 10 * See the License for the specific language governing permissions 11 * and limitations under the License. 12 * 13 * When distributing Covered Code, include this CDDL HEADER in each 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15 * If applicable, add the following below this CDDL HEADER, with the 16 * fields enclosed by brackets "[]" replaced with your own identifying 17 * information: Portions Copyright [yyyy] [name of copyright owner] 18 * 19 * CDDL HEADER END 20 */ 21 /* 22 * Copyright 2009 Sun Microsystems, Inc. All rights reserved. 23 * Use is subject to license terms. 24 */ 25 #ifndef _SYS_AUDIOHD_IMPL_H_ 26 #define _SYS_AUDIOHD_IMPL_H_ 27 28 #ifdef __cplusplus 29 extern "C" { 30 #endif 31 32 /* 33 * vendor IDs of PCI audio controllers 34 */ 35 #define AUDIOHD_VID_INTEL 0x8086 36 #define AUDIOHD_VID_ATI 0x1002 37 #define AUDIOHD_VID_NVIDIA 0x10de 38 #define AUDIOHD_VID_SIGMATEL 0x8384 39 40 /* 41 * specific codec id used by specific vendors 42 */ 43 #define AUDIOHD_CODEC_IDT7608 0x111d7608 44 #define AUDIOHD_CODEC_IDT76B2 0x111d76b2 45 #define AUDIOHD_CODECID_ALC888 0x10ec0888 46 #define AUDIOHD_CODECID_SONY1 0x10ec0260 47 #define AUDIOHD_CODECID_SONY2 0x10ec0262 48 49 #define AUDIOHD_INTS 50 50 #define AUDIOHD_MAX_INTS 1500 51 #define AUDIOHD_MIN_INTS 32 52 53 #define AUDIOHD_DEV_CONFIG "onboard1" 54 #define AUDIOHD_DEV_VERSION "a" 55 56 #define AUDIOHD_FMT_PCM 0x001 57 /* 58 * Only for Intel hardware: 59 * PCI Express traffic class select register in PCI configure space 60 */ 61 #define AUDIOHD_INTEL_PCI_TCSEL 0x44 62 63 /* 64 * Only for ATI SB450: 65 * MISC control register 2 66 */ 67 #define AUDIOHD_ATI_PCI_MISC2 0x42 68 #define AUDIOHD_ATI_MISC2_SNOOP 0x02 69 #define AUDIOHDC_NID(x) x 70 #define AUDIOHDC_NULL_NODE -1 71 #define AUDIOHD_NULL_CONN ((uint_t)(-1)) 72 /* 73 * currently, only the format of 48K sample rate, 16-bit 74 * 2-channel is supported. 75 */ 76 #define AUDIOHD_FMT_PCMOUT 0x0011 77 #define AUDIOHD_FMT_PCMIN 0x0011 78 79 #define AUDIOHD_EXT_AMP_MASK 0x00010000 80 #define AUDIOHD_EXT_AMP_ENABLE 0x02 81 /* NVIDIA snoop */ 82 #define AUDIOHD_NVIDIA_SNOOP 0x0f 83 84 /* Power On/Off */ 85 #define AUDIOHD_PW_OFF 1 86 #define AUDIOHD_PW_ON 0 87 #define AUDIOHD_PW_D0 0 88 #define AUDIOHD_PW_D2 2 89 90 #define AUDIOHD_INTEL_TCS_MASK 0xf8 91 #define AUDIOHD_ATI_MISC2_MASK 0xf8 92 93 /* Pin speaker On/Off */ 94 #define AUDIOHD_SP_ON 1 95 #define AUDIOHD_SP_OFF 0 96 97 #define AUDIOHD_PORT_MAX 15 98 #define AUDIOHD_CODEC_MAX 16 99 #define AUDIOHD_MEMIO_LEN 0x4000 100 101 #define AUDIOHD_RETRY_TIMES 60 102 #define AUDIOHD_TEST_TIMES 500 103 #define AUDIOHD_OUTSTR_NUM_OFF 12 104 #define AUDIOHD_INSTR_NUM_OFF 8 105 106 #define AUDIOHD_CORB_SIZE_OFF 0x4e 107 108 #define AUDIOHD_URCAP_MASK 0x80 109 #define AUDIOHD_DTCCAP_MASK 0x4 110 #define AUDIOHD_UR_ENABLE_OFF 8 111 #define AUDIOHD_UR_TAG_MASK 0x1f 112 113 #define AUDIOHD_CIS_MASK 0x40000000 114 115 #define AUDIOHD_RIRB_UR_MASK 0x10 116 #define AUDIOHD_RIRB_CODEC_MASK 0xf 117 #define AUDIOHD_RIRB_WID_OFF 27 118 #define AUDIOHD_RIRB_INTRCNT 0x0 119 #define AUDIOHD_RIRB_WPMASK 0xff 120 121 #define AUDIOHD_FORM_MASK 0x0080 122 #define AUDIOHD_LEN_MASK 0x007f 123 #define AUDIOHD_PIN_CAP_MASK 0x00000010 124 #define AUDIOHD_PIN_CONF_MASK 0xc0000000 125 #define AUDIOHD_PIN_CON_MASK 3 126 #define AUDIOHD_PIN_CON_STEP 30 127 #define AUDIOHD_PIN_IO_MASK 0X0018 128 #define AUDIOHD_PIN_SEQ_MASK 0x0000000f 129 #define AUDIOHD_PIN_ASO_MASK 0x000000f0 130 #define AUDIOHD_PIN_ASO_OFF 0x4 131 #define AUDIOHD_PIN_DEV_MASK 0x00f00000 132 #define AUDIOHD_PIN_DEV_OFF 20 133 #define AUDIOHD_PIN_NUMS 6 134 #define AUDIOHD_PIN_NO_CONN 0x40000000 135 #define AUDIOHD_PIN_IN_ENABLE 0x20 136 #define AUDIOHD_PIN_OUT_ENABLE 0x40 137 #define AUDIOHD_PIN_PRES_OFF 0x20 138 #define AUDIOHD_PIN_CONTP_OFF 0x1e 139 #define AUDIOHD_PIN_CON_JACK 0 140 #define AUDIOHD_PIN_CON_FIXED 0x2 141 #define AUDIOHD_PIN_CONTP_MASK 0x3 142 #define AUDIOHD_PIN_VREF_L1 0x20 143 #define AUDIOHD_PIN_VREF_L2 0x10 144 #define AUDIOHD_PIN_VREF_L3 0x04 145 #define AUDIOHD_PIN_VREF_L4 0x02 146 #define AUDIOHD_PIN_VREF_OFF 8 147 #define AUDIOHD_PIN_VREF_MASK 0xff 148 #define AUDIOHD_PIN_CLR_MASK 0xf 149 #define AUDIOHD_PIN_CLR_OFF 12 150 151 152 #define AUDIOHD_VERB_ADDR_OFF 28 153 #define AUDIOHD_VERB_NID_OFF 20 154 #define AUDIOHD_VERB_CMD_OFF 8 155 #define AUDIOHD_VERB_CMD16_OFF 16 156 157 #define AUDIOHD_RING_MAX_SIZE 0x00ff 158 #define AUDIOHD_POS_MASK ~0x00000003 159 #define AUDIOHD_REC_TAG_OFF 4 160 #define AUDIOHD_PLAY_TAG_OFF 4 161 #define AUDIOHD_PLAY_CTL_OFF 2 162 #define AUDIOHD_REC_CTL_OFF 2 163 164 #define AUDIOHD_SPDIF_ON 1 165 #define AUDIOHD_SPDIF_MASK 0x00ff 166 167 #define AUDIOHD_GAIN_OFF 8 168 169 #define AUDIOHD_CODEC_STR_OFF 16 170 #define AUDIOHD_CODEC_STR_MASK 0x000000ff 171 #define AUDIOHD_CODEC_NUM_MASK 0x000000ff 172 #define AUDIOHD_CODEC_TYPE_MASK 0x000000ff 173 174 #define AUDIOHD_FRAGFR_ALIGN 16 175 #define AUDIOHD_BDLE_BUF_ALIGN 128 176 #define AUDIOHD_CMDIO_ENT_MASK 0x00ff /* 256 entries for CORB/RIRB */ 177 #define AUDIOHD_CDBIO_CORB_LEN 1024 /* 256 entries for CORB, 1024B */ 178 #define AUDIOHD_CDBIO_RIRB_LEN 2048 /* 256 entries for RIRB, 2048B */ 179 #define AUDIOHD_BDLE_NUMS 4 /* 4 entires for record/play BD list */ 180 181 #define AUDIOHD_PORT_UNMUTE (0xffffffff) 182 183 /* 184 * Audio registers of high definition 185 */ 186 #define AUDIOHD_REG_GCAP 0x00 187 #define AUDIOHDR_GCAP_OUTSTREAMS 0xf000 188 #define AUDIOHDR_GCAP_INSTREAMS 0x0f00 189 #define AUDIOHDR_GCAP_BSTREAMS 0x00f8 190 #define AUDIOHDR_GCAP_NSDO 0x0006 191 #define AUDIOHDR_GCAP_64OK 0x0001 192 193 #define AUDIOHD_REG_VMIN 0x02 194 #define AUDIOHD_REG_VMAJ 0x03 195 #define AUDIOHD_REG_OUTPAY 0x04 196 #define AUDIOHD_REG_INPAY 0x06 197 #define AUDIOHD_REG_GCTL 0x08 198 #define AUDIOHD_REG_WAKEEN 0x0C 199 #define AUDIOHD_REG_STATESTS 0x0E 200 #define AUDIOHD_STATESTS_BIT_SDINS 0x7F 201 202 #define AUDIOHD_REG_GSTS 0x10 203 #define AUDIOHD_REG_INTCTL 0x20 204 #define AUDIOHD_INTCTL_BIT_GIE 0x80000000 205 #define AUDIOHD_INTCTL_BIT_CIE 0x40000000 206 #define AUDIOHD_INTCTL_BIT_SIE 0x3FFFFFFF 207 208 209 #define AUDIOHD_REG_INTSTS 0x24 210 #define AUDIOHD_INTSTS_BIT_GIS 0x80000000 211 #define AUDIOHD_INTSTS_BIT_CIS 0x40000000 212 #define AUDIOHD_INTSTS_BIT_SINTS (0x3fffffff) 213 214 #define AUDIOHD_REG_WALCLK 0x30 215 #define AUDIOHD_REG_SYNC 0x38 216 217 #define AUDIOHD_REG_CORBLBASE 0x40 218 #define AUDIOHD_REG_CORBUBASE 0x44 219 #define AUDIOHD_REG_CORBWP 0x48 220 #define AUDIOHD_REG_CORBRP 0x4A 221 #define AUDIOHD_REG_CORBCTL 0x4C 222 #define AUDIOHD_REG_CORBST 0x4D 223 #define AUDIOHD_REG_CORBSIZE 0x4E 224 225 #define AUDIOHD_REG_RIRBLBASE 0x50 226 #define AUDIOHD_REG_RIRBUBASE 0x54 227 #define AUDIOHD_REG_RIRBWP 0x58 228 #define AUDIOHD_REG_RINTCNT 0x5A 229 #define AUDIOHD_REG_RIRBCTL 0x5C 230 #define AUDIOHD_REG_RIRBSTS 0x5D 231 #define AUDIOHD_REG_RIRBSIZE 0x5E 232 233 #define AUDIOHD_REG_IC 0x60 234 #define AUDIOHD_REG_IR 0x64 235 #define AUDIOHD_REG_IRS 0x68 236 #define AUDIOHD_REG_DPLBASE 0x70 237 #define AUDIOHD_REG_DPUBASE 0x74 238 239 #define AUDIOHD_REG_SD_BASE 0x80 240 #define AUDIOHD_REG_SD_LEN 0x20 241 242 /* 243 * Offset of Stream Descriptor Registers 244 */ 245 #define AUDIOHD_SDREG_OFFSET_CTL 0x00 246 #define AUDIOHD_SDREG_OFFSET_STS 0x03 247 #define AUDIOHD_SDREG_OFFSET_LPIB 0x04 248 #define AUDIOHD_SDREG_OFFSET_CBL 0x08 249 #define AUDIOHD_SDREG_OFFSET_LVI 0x0c 250 #define AUDIOHD_SDREG_OFFSET_FIFOW 0x0e 251 #define AUDIOHD_SDREG_OFFSET_FIFOSIZE 0x10 252 #define AUDIOHD_SDREG_OFFSET_FORMAT 0x12 253 #define AUDIOHD_SDREG_OFFSET_BDLPL 0x18 254 #define AUDIOHD_SDREG_OFFSET_BDLPU 0x1c 255 256 /* bits for stream descriptor control reg */ 257 #define AUDIOHDR_SD_CTL_DEIE 0x000010 258 #define AUDIOHDR_SD_CTL_FEIE 0x000008 259 #define AUDIOHDR_SD_CTL_IOCE 0x000004 260 #define AUDIOHDR_SD_CTL_SRUN 0x000002 261 #define AUDIOHDR_SD_CTL_SRST 0x000001 262 #define AUDIOHDR_SD_CTL_INTS \ 263 (AUDIOHDR_SD_CTL_DEIE | \ 264 AUDIOHDR_SD_CTL_FEIE | \ 265 AUDIOHDR_SD_CTL_IOCE) 266 267 268 /* bits for stream descriptor status register */ 269 #define AUDIOHDR_SD_STS_BCIS 0x0004 270 #define AUDIOHDR_SD_STS_FIFOE 0x0008 271 #define AUDIOHDR_SD_STS_DESE 0x0010 272 #define AUDIOHDR_SD_STS_FIFORY 0x0020 273 #define AUDIOHDR_SD_STS_INTRS \ 274 (AUDIOHDR_SD_STS_BCIS | \ 275 AUDIOHDR_SD_STS_FIFOE | \ 276 AUDIOHDR_SD_STS_DESE) 277 278 279 /* bits for GCTL register */ 280 #define AUDIOHDR_GCTL_CRST 0x00000001 281 #define AUDIOHDR_GCTL_URESPE 0x00000100 282 283 /* bits for CORBRP register */ 284 #define AUDIOHDR_CORBRP_RESET 0x8000 285 #define AUDIOHDR_CORBRP_WPTR 0x00ff 286 287 /* bits for CORBCTL register */ 288 #define AUDIOHDR_CORBCTL_CMEIE 0x01 289 #define AUDIOHDR_CORBCTL_DMARUN 0x02 290 291 /* bits for CORB SIZE register */ 292 #define AUDIOHDR_CORBSZ_8 0 293 #define AUDIOHDR_CORBSZ_16 1 294 #define AUDIOHDR_CORBSZ_256 2 295 296 /* bits for RIRBCTL register */ 297 #define AUDIOHDR_RIRBCTL_RINTCTL 0x01 298 #define AUDIOHDR_RIRBCTL_DMARUN 0x02 299 #define AUDIOHDR_RIRBCTL_RIRBOIC 0x04 300 #define AUDIOHDR_RIRBCTL_RSTINT 0xfe 301 302 /* bits for RIRBWP register */ 303 #define AUDIOHDR_RIRBWP_RESET 0x8000 304 #define AUDIOHDR_RIRBWP_WPTR 0x00ff 305 306 /* bits for RIRB SIZE register */ 307 #define AUDIOHDR_RIRBSZ_8 0 308 #define AUDIOHDR_RIRBSZ_16 1 309 #define AUDIOHDR_RIRBSZ_256 2 310 311 #define AUDIOHD_BDLE_RIRB_SDI 0x0000000f 312 #define AUDIOHD_BDLE_RIRB_UNSOLICIT 0x00000010 313 314 /* HD spec: ID of Root node is 0 */ 315 #define AUDIOHDC_NODE_ROOT 0x00 316 317 /* HD spec: ID of audio function group is "1" */ 318 #define AUDIOHDC_AUDIO_FUNC_GROUP 1 319 320 /* 321 * HD audio verbs can be either 12-bit or 4-bit in length. 322 */ 323 #define AUDIOHDC_12BIT_VERB_MASK 0xfffff000 324 #define AUDIOHDC_4BIT_VERB_MASK 0xfffffff0 325 326 #define AUDIOHDC_SAMPR48000 48000 327 #define AUDIOHDC_MAX_BEEP_GEN 12000 328 #define AUDIOHDC_MIX_BEEP_GEN 47 329 #define AUDIOHDC_MUTE_BEEP_GEN 0x0 330 331 /* 332 * 12-bit verbs 333 */ 334 #define AUDIOHDC_VERB_GET_PARAM 0xf00 335 336 #define AUDIOHDC_VERB_GET_CONN_SEL 0xf01 337 #define AUDIOHDC_VERB_SET_CONN_SEL 0x701 338 339 #define AUDIOHDC_VERB_GET_CONN_LIST_ENT 0xf02 340 #define AUDIOHDC_VERB_GET_PROCESS_STATE 0xf03 341 #define AUDIOHDC_VERB_GET_SDI_SEL 0xf04 342 343 #define AUDIOHDC_VERB_GET_POWER_STATE 0xf05 344 #define AUDIOHDC_VERB_SET_POWER_STATE 0x705 345 346 #define AUDIOHDC_VERB_GET_STREAM_CHANN 0xf06 347 #define AUDIOHDC_VERB_SET_STREAM_CHANN 0x706 348 349 #define AUDIOHDC_VERB_GET_PIN_CTRL 0xf07 350 #define AUDIOHDC_VERB_SET_PIN_CTRL 0x707 351 352 #define AUDIOHDC_VERB_GET_UNS_ENABLE 0xf08 353 354 #define AUDIOHDC_VERB_GET_PIN_SENSE 0xf09 355 #define AUDIOHDC_VERB_EXEC_PIN_SENSE 0x709 356 357 #define AUDIOHDC_VERB_GET_BEEP_GEN 0xf0a 358 #define AUDIOHDC_VERB_SET_BEEP_GEN 0x70a 359 360 #define AUDIOHDC_VERB_GET_EAPD 0xf0c 361 #define AUDIOHDC_VERB_SET_EAPD 0x70c 362 363 #define AUDIOHDC_VERB_GET_DEFAULT_CONF 0xf1c 364 #define AUDIOHDC_VERB_GET_SPDIF_CTL 0xf0d 365 #define AUDIOHDC_VERB_SET_SPDIF_LCL 0x70d 366 367 #define AUDIOHDC_VERB_SET_URCTRL 0x708 368 #define AUDIOHDC_VERB_GET_PIN_SENSE 0xf09 369 370 #define AUDIOHDC_VERB_GET_GPIO_MASK 0xf16 371 #define AUDIOHDC_VERB_SET_GPIO_MASK 0x716 372 373 #define AUDIOHDC_VERB_GET_GPIO_DIREC 0xf17 374 #define AUDIOHDC_VERB_SET_GPIO_DIREC 0x717 375 376 #define AUDIOHDC_VERB_GET_GPIO_DATA 0xf15 377 #define AUDIOHDC_VERB_SET_GPIO_DATA 0x715 378 379 #define AUDIOHDC_VERB_GET_GPIO_STCK 0xf1a 380 #define AUDIOHDC_VERB_SET_GPIO_STCK 0x71a 381 382 #define AUDIOHDC_GPIO_ENABLE 0xff 383 #define AUDIOHDC_GPIO_DIRECT 0xf1 384 385 #define AUDIOHDC_GPIO_DATA_CTRL 0xff 386 #define AUDIOHDC_GPIO_STCK_CTRL 0xff 387 /* 388 * 4-bit verbs 389 */ 390 #define AUDIOHDC_VERB_GET_CONV_FMT 0xa 391 #define AUDIOHDC_VERB_SET_CONV_FMT 0x2 392 393 #define AUDIOHDC_VERB_GET_AMP_MUTE 0xb 394 #define AUDIOHDC_VERB_SET_AMP_MUTE 0x3 395 #define AUDIOHDC_VERB_SET_BEEP_VOL 0x3A0 396 397 /* 398 * parameters of nodes 399 */ 400 #define AUDIOHDC_PAR_VENDOR_ID 0x00 401 #define AUDIOHDC_PAR_SUBSYS_ID 0x01 402 #define AUDIOHDC_PAR_REV_ID 0x02 403 #define AUDIOHDC_PAR_NODE_COUNT 0x04 404 #define AUDIOHDC_PAR_FUNCTION_TYPE 0x05 405 #define AUDIOHDC_PAR_AUDIO_FG_CAP 0x08 406 #define AUDIOHDC_PAR_AUDIO_WID_CAP 0x09 407 #define AUDIOHDC_PAR_PCM 0x0a 408 #define AUDIOHDC_PAR_STREAM 0x0b 409 #define AUDIOHDC_PAR_PIN_CAP 0x0c 410 #define AUDIOHDC_PAR_INAMP_CAP 0x0d 411 #define AUDIOHDC_PAR_CONNLIST_LEN 0x0e 412 #define AUDIOHDC_PAR_POWER_STATE 0x0f 413 #define AUDIOHDC_PAR_PROC_CAP 0x10 414 #define AUDIOHDC_PAR_GPIO_CAP 0x11 415 #define AUDIOHDC_PAR_OUTAMP_CAP 0x12 416 417 /* 418 * bits for get/set amplifier gain/mute 419 */ 420 #define AUDIOHDC_AMP_SET_OUTPUT 0x8000 421 #define AUDIOHDC_AMP_SET_INPUT 0x4000 422 #define AUDIOHDC_AMP_SET_LEFT 0x2000 423 #define AUDIOHDC_AMP_SET_RIGHT 0x1000 424 #define AUDIOHDC_AMP_SET_MUTE 0x0080 425 #define AUDIOHDC_AMP_SET_LNR 0x3000 426 #define AUDIOHDC_AMP_SET_LR_INPUT 0x7000 427 #define AUDIOHDC_AMP_SET_LR_OUTPUT 0xb000 428 #define AUDIOHDC_AMP_SET_INDEX_OFFSET 8 429 #define AUDIOHDC_AMP_SET_GAIN_MASK 0x007f 430 #define AUDIOHDC_GAIN_MAX 0x7f 431 #define AUDIOHDC_GAIN_BITS 7 432 #define AUDIOHDC_GAIN_DEFAULT 0x0f 433 434 #define AUDIOHDC_AMP_GET_OUTPUT 0x8000 435 #define AUDIOHDC_AMP_GET_INPUT 0x0000 436 437 /* value used to set max volume for left output */ 438 #define AUDIOHDC_AMP_LOUT_MAX \ 439 (AUDIOHDC_AMP_SET_OUTPUT | \ 440 AUDIOHDC_AMP_SET_LEFT | \ 441 AUDIOHDC_GAIN_MAX) 442 443 /* value used to set max volume for right output */ 444 #define AUDIOHDC_AMP_ROUT_MAX \ 445 (AUDIOHDC_AMP_SET_OUTPUT | \ 446 AUDIOHDC_AMP_SET_RIGHT | \ 447 AUDIOHDC_GAIN_MAX) 448 449 450 /* 451 * Bits for pin widget control verb 452 */ 453 #define AUDIOHDC_PIN_CONTROL_HP_ENABLE 0x80 454 #define AUDIOHDC_PIN_CONTROL_OUT_ENABLE 0x40 455 #define AUDIOHDC_PIN_CONTROL_IN_ENABLE 0x20 456 457 /* 458 * Bits for Amplifier capabilities 459 */ 460 #define AUDIOHDC_AMP_CAP_MUTE_CAP 0x80000000 461 #define AUDIOHDC_AMP_CAP_STEP_SIZE 0x007f0000 462 #define AUDIOHDC_AMP_CAP_STEP_NUMS 0x00007f00 463 #define AUDIOHDC_AMP_CAP_0DB_OFFSET 0x0000007f 464 465 466 /* 467 * Bits for Audio Widget Capabilities 468 */ 469 #define AUDIOHD_WIDCAP_STEREO 0x00000001 470 #define AUDIOHD_WIDCAP_INAMP 0x00000002 471 #define AUDIOHD_WIDCAP_OUTAMP 0x00000004 472 #define AUDIOHD_WIDCAP_AMP_OVRIDE 0x00000008 473 #define AUDIOHD_WIDCAP_FMT_OVRIDE 0x00000010 474 #define AUDIOHD_WIDCAP_STRIP 0x00000020 475 #define AUDIOHD_WIDCAP_PROC_WID 0x00000040 476 #define AUDIOHD_WIDCAP_UNSOL 0x00000080 477 #define AUDIOHD_WIDCAP_CONNLIST 0x00000100 478 #define AUDIOHD_WIDCAP_DIGIT 0x00000200 479 #define AUDIOHD_WIDCAP_PWRCTRL 0x00000400 480 #define AUDIOHD_WIDCAP_LRSWAP 0x00000800 481 #define AUDIOHD_WIDCAP_TYPE 0x00f00000 482 #define AUDIOHD_WIDCAP_TO_WIDTYPE(wcap) \ 483 ((wcap & AUDIOHD_WIDCAP_TYPE) >> 20) 484 485 486 #define AUDIOHD_CODEC_FAILURE (uint32_t)(-1) 487 488 /* 489 * buffer descriptor list entry of stream descriptor 490 */ 491 typedef struct { 492 uint64_t sbde_addr; 493 uint32_t sbde_len; 494 uint32_t 495 sbde_ioc: 1, 496 reserved: 31; 497 }sd_bdle_t; 498 499 500 #define AUDIOHD_PLAY_STARTED 0x00000001 501 #define AUDIOHD_PLAY_EMPTY 0x00000002 502 #define AUDIOHD_PLAY_PAUSED 0x00000004 503 #define AUDIOHD_RECORD_STARTED 0x00000008 504 505 enum audiohda_widget_type { 506 WTYPE_AUDIO_OUT = 0, 507 WTYPE_AUDIO_IN, 508 WTYPE_AUDIO_MIX, 509 WTYPE_AUDIO_SEL, 510 WTYPE_PIN, 511 WTYPE_POWER, 512 WTYPE_VOL_KNOB, 513 WTYPE_BEEP, 514 WTYPE_VENDOR = 0xf 515 }; 516 517 enum audiohda_device_type { 518 DTYPE_LINEOUT = 0, 519 DTYPE_SPEAKER, 520 DTYPE_HP_OUT, 521 DTYPE_CD, 522 DTYPE_SPDIF_OUT, 523 DTYPE_DIGIT_OUT, 524 DTYPE_MODEM_SIDE, 525 DTYPE_MODEM_HNAD_SIDE, 526 DTYPE_LINE_IN, 527 DTYPE_AUX, 528 DTYPE_MIC_IN, 529 DTYPE_TEL, 530 DTYPE_SPDIF_IN, 531 DTYPE_DIGIT_IN, 532 DTYPE_OTHER = 0x0f, 533 }; 534 535 enum audiohd_pin_color { 536 AUDIOHD_PIN_UNKNOWN = 0, 537 AUDIOHD_PIN_BLACK, 538 AUDIOHD_PIN_GREY, 539 AUDIOHD_PIN_BLUE, 540 AUDIOHD_PIN_GREEN, 541 AUDIOHD_PIN_RED, 542 AUDIOHD_PIN_ORANGE, 543 AUDIOHD_PIN_YELLOW, 544 AUDIOHD_PIN_PURPLE, 545 AUDIOHD_PIN_PINK, 546 AUDIOHD_PIN_WHITE = 0xe, 547 AUDIOHD_PIN_OTHER = 0xf, 548 }; 549 550 #define CTRL_NUM 16 551 552 /* values for audiohd_widget.path_flags */ 553 #define AUDIOHD_PATH_DAC (1 << 0) 554 #define AUDIOHD_PATH_ADC (1 << 1) 555 #define AUDIOHD_PATH_MON (1 << 2) 556 #define AUDIOHD_PATH_NOMON (1 << 3) 557 #define AUDIOHD_PATH_BEEP (1 << 4) 558 559 typedef struct audiohd_path audiohd_path_t; 560 typedef struct audiohd_widget audiohd_widget_t; 561 typedef struct audiohd_state audiohd_state_t; 562 typedef struct audiohd_pin audiohd_pin_t; 563 typedef struct hda_codec hda_codec_t; 564 typedef uint32_t wid_t; /* id of widget */ 565 typedef struct audiohd_entry_prop audiohd_entry_prop_t; 566 typedef enum audiohda_device_type audiohda_device_type_t; 567 typedef enum audiohd_pin_color audiohd_pin_color_t; 568 569 #define AUDIOHD_MAX_WIDGET 128 570 #define AUDIOHD_MAX_CONN 16 571 #define AUDIOHD_MAX_PINS 16 572 #define AUDIOHD_MAX_DEPTH 8 573 574 struct audiohd_entry_prop { 575 uint32_t conn_len; 576 uint32_t mask_range; 577 uint32_t mask_wid; 578 wid_t input_wid; 579 int conns_per_entry; 580 int bits_per_conn; 581 }; 582 struct audiohd_widget { 583 wid_t wid_wid; 584 hda_codec_t *codec; 585 enum audiohda_widget_type type; 586 587 uint32_t widget_cap; 588 uint32_t pcm_format; 589 uint32_t inamp_cap; 590 uint32_t outamp_cap; 591 592 uint32_t path_flags; 593 594 int out_weight; 595 int in_weight; 596 int finish; 597 598 /* 599 * wid of possible & selected input connections 600 */ 601 wid_t avail_conn[AUDIOHD_MAX_CONN]; 602 wid_t selconn; 603 /* 604 * for monitor path 605 */ 606 wid_t selmon[AUDIOHD_MAX_CONN]; 607 uint16_t used; 608 609 /* 610 * available (input) connections. 0 means this widget 611 * has fixed connection 612 */ 613 int nconns; 614 615 /* 616 * pointer to struct depending on widget type: 617 * 1. DAC audiohd_ostream_t 618 * 2. ADC audiohd_istream_t 619 * 3. PIN audiohd_pin_t 620 */ 621 void *priv; 622 }; 623 624 #define AUDIOHD_FLAG_LINEOUT (1 << 0) 625 #define AUDIOHD_FLAG_SPEAKER (1 << 1) 626 #define AUDIOHD_FLAG_HP (1 << 2) 627 #define AUDIOHD_FLAG_MONO (1 << 3) 628 629 #define AUDIOHD_MAX_MIXER 5 630 #define AUDIOHD_MAX_PIN 4 631 632 #define PORT_DAC 0 633 #define PORT_ADC 1 634 #define PORT_MAX 2 635 typedef enum { 636 PLAY = 0, 637 RECORD = 1, 638 BEEP = 2, 639 } path_type_t; 640 641 struct audiohd_path { 642 wid_t adda_wid; 643 wid_t beep_wid; 644 645 wid_t pin_wid[AUDIOHD_MAX_PINS]; 646 int sum_selconn[AUDIOHD_MAX_PINS]; 647 int mon_wid[AUDIOHD_MAX_PIN][AUDIOHD_MAX_MIXER]; 648 int pin_nums; 649 int maxmixer[AUDIOHD_MAX_PINS]; 650 651 path_type_t path_type; 652 653 wid_t mute_wid; 654 int mute_dir; 655 wid_t gain_wid; 656 int gain_dir; 657 uint32_t gain_bits; 658 659 uint32_t pin_outputs; 660 uint8_t tag; 661 662 hda_codec_t *codec; 663 664 wid_t sum_wid; 665 666 audiohd_state_t *statep; 667 }; 668 669 typedef struct audiohd_port 670 { 671 uint8_t nchan; 672 int index; 673 uint16_t regoff; 674 boolean_t started; 675 boolean_t triggered; 676 677 unsigned fragfr; 678 unsigned nframes; 679 uint64_t count; 680 int curpos; 681 int len; 682 int intrs; 683 684 uint_t format; 685 unsigned sync_dir; 686 687 ddi_dma_handle_t samp_dmah; 688 ddi_acc_handle_t samp_acch; 689 size_t samp_size; 690 caddr_t samp_kaddr; 691 uint64_t samp_paddr; 692 693 ddi_dma_handle_t bdl_dmah; 694 ddi_acc_handle_t bdl_acch; 695 size_t bdl_size; 696 caddr_t bdl_kaddr; 697 uint64_t bdl_paddr; 698 699 audio_engine_t *engine; 700 audiohd_state_t *statep; 701 }audiohd_port_t; 702 703 typedef struct audiohd_ctrl 704 { 705 audiohd_state_t *statep; 706 audio_ctrl_t *ctrl; 707 uint32_t num; 708 uint64_t val; 709 } audiohd_ctrl_t; 710 711 struct audiohd_pin { 712 audiohd_pin_t *next; 713 wid_t wid; 714 wid_t mute_wid; /* node used to mute this pin */ 715 int mute_dir; /* 1: input, 2: output */ 716 wid_t gain_wid; /* node for gain control */ 717 int gain_dir; /* _OUTPUT/_INPUT */ 718 uint32_t gain_bits; 719 720 uint8_t vrefvalue; /* value of VRef */ 721 722 uint32_t cap; 723 uint32_t config; 724 uint32_t ctrl; 725 uint32_t assoc; 726 uint32_t seq; 727 wid_t adc_dac_wid; /* AD/DA wid which can route to this pin */ 728 wid_t beep_wid; 729 int no_phys_conn; 730 enum audiohda_device_type device; 731 732 /* 733 * mg_dir, mg_gain, mg_wid are used to store the monitor gain control 734 * widget wid. 735 */ 736 int mg_dir[AUDIOHD_MAX_CONN]; 737 int mg_gain[AUDIOHD_MAX_CONN]; 738 int mg_wid[AUDIOHD_MAX_CONN]; 739 int num; 740 int finish; 741 742 }; 743 744 typedef struct { 745 ddi_dma_handle_t ad_dmahdl; 746 ddi_acc_handle_t ad_acchdl; 747 caddr_t ad_vaddr; /* virtual addr */ 748 uint64_t ad_paddr; /* physical addr */ 749 size_t ad_req_sz; /* required size of memory */ 750 size_t ad_real_sz; /* real size of memory */ 751 } audiohd_dma_t; 752 753 struct hda_codec { 754 uint8_t index; /* codec address */ 755 uint32_t vid; /* vendor id and device id */ 756 uint32_t revid; /* revision id */ 757 wid_t wid_afg; /* id of AFG */ 758 wid_t first_wid; /* wid of 1st subnode of AFG */ 759 wid_t last_wid; /* wid of the last subnode of AFG */ 760 int nnodes; /* # of subnodes of AFG */ 761 uint8_t nistream; 762 763 uint32_t outamp_cap; 764 uint32_t inamp_cap; 765 uint32_t stream_format; 766 uint32_t pcm_format; 767 768 audiohd_state_t *soft_statep; 769 770 /* use wid as index to the array of widget pointers */ 771 audiohd_widget_t *widget[AUDIOHD_MAX_WIDGET]; 772 773 774 audiohd_port_t *port[AUDIOHD_PORT_MAX]; 775 uint8_t portnum; 776 audiohd_pin_t *first_pin; 777 }; 778 779 #define AUDIOHD_MAX_ASSOC 15 780 struct audiohd_state { 781 dev_info_t *hda_dip; 782 kstat_t *hda_ksp; 783 kmutex_t hda_mutex; 784 uint32_t hda_flags; 785 786 boolean_t soft_volume; 787 boolean_t intr_added; 788 789 caddr_t hda_reg_base; 790 ddi_acc_handle_t hda_pci_handle; 791 ddi_acc_handle_t hda_reg_handle; 792 ddi_iblock_cookie_t hda_intr_cookie; 793 794 audiohd_dma_t hda_dma_corb; 795 audiohd_dma_t hda_dma_rirb; 796 797 798 uint8_t hda_rirb_rp; /* read pointer for rirb */ 799 uint16_t hda_codec_mask; 800 801 802 audio_dev_t *adev; 803 804 805 int hda_pint_freq; /* play intr frequence */ 806 int hda_rint_freq; /* record intr frequence */ 807 808 int hda_input_streams; /* # of input stream */ 809 int hda_output_streams; /* # of output stream */ 810 int hda_streams_nums; /* # of stream */ 811 812 uint_t hda_play_regbase; 813 uint_t hda_record_regbase; 814 815 uint_t hda_play_stag; /* tag of playback stream */ 816 uint_t hda_record_stag; /* tag of record stream */ 817 uint_t hda_play_lgain; /* left gain for playback */ 818 uint_t hda_play_rgain; /* right gain for playback */ 819 820 /* 821 * Now, for the time being, we add some fields 822 * for parsing codec topology 823 */ 824 hda_codec_t *codec[AUDIOHD_CODEC_MAX]; 825 /* 826 * Suspend/Resume used fields 827 */ 828 boolean_t suspended; 829 boolean_t monitor_unsupported; 830 831 audiohd_path_t *path[AUDIOHD_PORT_MAX]; 832 uint8_t pathnum; 833 audiohd_port_t *port[PORT_MAX]; 834 uint8_t pchan; 835 uint8_t rchan; 836 837 uint64_t inmask; 838 839 uint_t hda_out_ports; 840 uint_t in_port; 841 842 /* 843 * Controls 844 */ 845 audiohd_ctrl_t *controls[CTRL_NUM]; 846 847 /* for multichannel */ 848 uint8_t chann[AUDIOHD_MAX_ASSOC]; 849 uint8_t assoc; 850 851 }; 852 853 854 /* 855 * Operation for high definition audio control system bus 856 * interface registers 857 */ 858 #define AUDIOHD_REG_GET8(reg) \ 859 ddi_get8(statep->hda_reg_handle, \ 860 (void *)((char *)statep->hda_reg_base + (reg))) 861 862 #define AUDIOHD_REG_GET16(reg) \ 863 ddi_get16(statep->hda_reg_handle, \ 864 (void *)((char *)statep->hda_reg_base + (reg))) 865 866 #define AUDIOHD_REG_GET32(reg) \ 867 ddi_get32(statep->hda_reg_handle, \ 868 (void *)((char *)statep->hda_reg_base + (reg))) 869 870 #define AUDIOHD_REG_GET64(reg) \ 871 ddi_get64(statep->hda_reg_handle, \ 872 (void *)((char *)statep->hda_reg_base + (reg))) 873 874 #define AUDIOHD_REG_SET8(reg, val) \ 875 ddi_put8(statep->hda_reg_handle, \ 876 (void *)((char *)statep->hda_reg_base + (reg)), (val)) 877 878 #define AUDIOHD_REG_SET16(reg, val) \ 879 ddi_put16(statep->hda_reg_handle, \ 880 (void *)((char *)statep->hda_reg_base + (reg)), (val)) 881 882 #define AUDIOHD_REG_SET32(reg, val) \ 883 ddi_put32(statep->hda_reg_handle, \ 884 (void *)((char *)statep->hda_reg_base + (reg)), (val)) 885 886 #define AUDIOHD_REG_SET64(reg, val) \ 887 ddi_put64(statep->hda_reg_handle, \ 888 (void *)((char *)statep->hda_reg_base + (reg)), (val)) 889 890 891 /* 892 * enable a pin widget to output 893 */ 894 #define AUDIOHD_ENABLE_PIN_OUT(statep, caddr, wid) \ 895 { \ 896 uint32_t lTmp; \ 897 \ 898 lTmp = audioha_codec_verb_get(statep, caddr, wid, \ 899 AUDIOHDC_VERB_GET_PIN_CTRL, 0); \ 900 if (lTmp == AUDIOHD_CODEC_FAILURE) \ 901 return (DDI_FAILURE); \ 902 lTmp = audioha_codec_verb_get(statep, caddr, wid, \ 903 AUDIOHDC_VERB_SET_PIN_CTRL, \ 904 (lTmp | AUDIOHDC_PIN_CONTROL_OUT_ENABLE | \ 905 AUDIOHDC_PIN_CONTROL_HP_ENABLE)); \ 906 if (lTmp == AUDIOHD_CODEC_FAILURE) \ 907 return (DDI_FAILURE); \ 908 } 909 910 /* 911 * disable output pin 912 */ 913 #define AUDIOHD_DISABLE_PIN_OUT(statep, caddr, wid) \ 914 { \ 915 uint32_t lTmp; \ 916 \ 917 lTmp = audioha_codec_verb_get(statep, caddr, wid, \ 918 AUDIOHDC_VERB_GET_PIN_CTRL, 0); \ 919 if (lTmp == AUDIOHD_CODEC_FAILURE) \ 920 return (DDI_FAILURE); \ 921 lTmp = audioha_codec_verb_get(statep, caddr, wid, \ 922 AUDIOHDC_VERB_SET_PIN_CTRL, \ 923 (lTmp & ~AUDIOHDC_PIN_CONTROL_OUT_ENABLE)); \ 924 if (lTmp == AUDIOHD_CODEC_FAILURE) \ 925 return (DDI_FAILURE); \ 926 } 927 928 /* 929 * enable a pin widget to input 930 */ 931 #define AUDIOHD_ENABLE_PIN_IN(statep, caddr, wid) \ 932 { \ 933 (void) audioha_codec_verb_get(statep, caddr, wid, \ 934 AUDIOHDC_VERB_SET_PIN_CTRL, AUDIOHDC_PIN_CONTROL_IN_ENABLE | 4); \ 935 } 936 937 938 /* 939 * disable input pin 940 */ 941 #define AUDIOHD_DISABLE_PIN_IN(statep, caddr, wid) \ 942 { \ 943 uint32_t lTmp; \ 944 \ 945 lTmp = audioha_codec_verb_get(statep, caddr, wid, \ 946 AUDIOHDC_VERB_GET_PIN_CTRL, 0); \ 947 if (lTmp == AUDIOHD_CODEC_FAILURE) \ 948 return (DDI_FAILURE); \ 949 lTmp = audioha_codec_verb_get(statep, caddr, wid, \ 950 AUDIOHDC_VERB_SET_PIN_CTRL, \ 951 (lTmp & ~AUDIOHDC_PIN_CONTROL_IN_ENABLE)); \ 952 if (lTmp == AUDIOHD_CODEC_FAILURE) \ 953 return (DDI_FAILURE); \ 954 } 955 956 /* 957 * unmute an output pin 958 */ 959 #define AUDIOHD_NODE_UNMUTE_OUT(statep, caddr, wid) \ 960 { \ 961 if (audioha_codec_4bit_verb_get(statep, \ 962 caddr, wid, AUDIOHDC_VERB_SET_AMP_MUTE, \ 963 AUDIOHDC_AMP_SET_LR_OUTPUT | AUDIOHDC_GAIN_MAX) == \ 964 AUDIOHD_CODEC_FAILURE) \ 965 return (DDI_FAILURE); \ 966 } 967 968 #ifdef __cplusplus 969 } 970 #endif 971 972 #endif /* _SYS_AUDIOHD_IMPL_H_ */ 973