1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License (the "License"). 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9 * or http://www.opensolaris.org/os/licensing. 10 * See the License for the specific language governing permissions 11 * and limitations under the License. 12 * 13 * When distributing Covered Code, include this CDDL HEADER in each 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15 * If applicable, add the following below this CDDL HEADER, with the 16 * fields enclosed by brackets "[]" replaced with your own identifying 17 * information: Portions Copyright [yyyy] [name of copyright owner] 18 * 19 * CDDL HEADER END 20 */ 21 /* 22 * Copyright 2010 Sun Microsystems, Inc. All rights reserved. 23 * Use is subject to license terms. 24 */ 25 #ifndef _SYS_AUDIOHD_IMPL_H_ 26 #define _SYS_AUDIOHD_IMPL_H_ 27 28 #ifdef __cplusplus 29 extern "C" { 30 #endif 31 32 /* 33 * vendor IDs of PCI audio controllers 34 */ 35 #define AUDIOHD_VID_ATI 0x1002 36 #define AUDIOHD_VID_CIRRUS 0x1013 37 #define AUDIOHD_VID_NVIDIA 0x10de 38 #define AUDIOHD_VID_REALTEK 0x10ec 39 #define AUDIOHD_VID_CREATIVE 0x1102 40 #define AUDIOHD_VID_IDT 0x111d 41 #define AUDIOHD_VID_ANALOG 0x11d4 42 #define AUDIOHD_VID_CONEXANT 0x14f1 43 #define AUDIOHD_VID_SIGMATEL 0x8384 44 #define AUDIOHD_VID_INTEL 0x8086 45 46 /* 47 * specific audiohd controller device id 48 */ 49 #define AUDIOHD_CONTROLLER_MCP51 0x10de026c 50 51 /* 52 * codec special initial flags 53 */ 54 #define NO_GPIO 0x00000001 55 #define NO_MIXER 0x00000002 56 #define NO_SPDIF 0x00000004 57 58 #define AUDIOHD_INTS 50 59 #define AUDIOHD_MAX_INTS 1500 60 #define AUDIOHD_MIN_INTS 32 61 62 #define AUDIOHD_DEV_CONFIG "onboard1" 63 #define AUDIOHD_DEV_VERSION "a" 64 65 #define AUDIOHD_FMT_PCM 0x001 66 /* 67 * Only for Intel hardware: 68 * PCI Express traffic class select register in PCI configure space 69 */ 70 #define AUDIOHD_INTEL_PCI_TCSEL 0x44 71 72 /* 73 * Only for ATI SB450: 74 * MISC control register 2 75 */ 76 #define AUDIOHD_ATI_PCI_MISC2 0x42 77 #define AUDIOHD_ATI_MISC2_SNOOP 0x02 78 #define AUDIOHDC_NID(x) x 79 #define AUDIOHDC_NULL_NODE -1 80 #define AUDIOHD_NULL_CONN ((uint_t)(-1)) 81 /* 82 * currently, only the format of 48K sample rate, 16-bit 83 * 2-channel is supported. 84 */ 85 #define AUDIOHD_FMT_PCMOUT 0x0011 86 #define AUDIOHD_FMT_PCMIN 0x0011 87 88 #define AUDIOHD_EXT_AMP_MASK 0x00010000 89 #define AUDIOHD_EXT_AMP_ENABLE 0x02 90 /* NVIDIA snoop */ 91 #define AUDIOHD_NVIDIA_SNOOP 0x0f 92 93 /* Power On/Off */ 94 #define AUDIOHD_PW_D0 0 95 #define AUDIOHD_PW_D2 2 96 97 #define AUDIOHD_INTEL_TCS_MASK 0xf8 98 #define AUDIOHD_ATI_MISC2_MASK 0xf8 99 100 /* Pin speaker On/Off */ 101 #define AUDIOHD_SP_ON 1 102 #define AUDIOHD_SP_OFF 0 103 104 #define AUDIOHD_PORT_MAX 15 105 #define AUDIOHD_CODEC_MAX 16 106 #define AUDIOHD_MEMIO_LEN 0x4000 107 108 #define AUDIOHD_RETRY_TIMES 60 109 #define AUDIOHD_TEST_TIMES 500 110 #define AUDIOHD_OUTSTR_NUM_OFF 12 111 #define AUDIOHD_INSTR_NUM_OFF 8 112 113 #define AUDIOHD_CORB_SIZE_OFF 0x4e 114 115 #define AUDIOHD_URCAP_MASK 0x80 116 #define AUDIOHD_DTCCAP_MASK 0x4 117 #define AUDIOHD_UR_ENABLE_OFF 8 118 #define AUDIOHD_UR_TAG_MASK 0x1f 119 120 #define AUDIOHD_CIS_MASK 0x40000000 121 122 #define AUDIOHD_RIRB_UR_MASK 0x10 123 #define AUDIOHD_RIRB_CODEC_MASK 0xf 124 #define AUDIOHD_RIRB_WID_OFF 27 125 #define AUDIOHD_RIRB_INTRCNT 0x0 126 #define AUDIOHD_RIRB_WPMASK 0xff 127 128 #define AUDIOHD_FORM_MASK 0x0080 129 #define AUDIOHD_LEN_MASK 0x007f 130 #define AUDIOHD_PIN_CAP_MASK 0x00000010 131 #define AUDIOHD_PIN_CONF_MASK 0xc0000000 132 #define AUDIOHD_PIN_CON_MASK 3 133 #define AUDIOHD_PIN_CON_STEP 30 134 #define AUDIOHD_PIN_IO_MASK 0X0018 135 #define AUDIOHD_PIN_SEQ_MASK 0x0000000f 136 #define AUDIOHD_PIN_ASO_MASK 0x000000f0 137 #define AUDIOHD_PIN_ASO_OFF 0x4 138 #define AUDIOHD_PIN_DEV_MASK 0x00f00000 139 #define AUDIOHD_PIN_DEV_OFF 20 140 #define AUDIOHD_PIN_NUMS 6 141 #define AUDIOHD_PIN_NO_CONN 0x40000000 142 #define AUDIOHD_PIN_IN_ENABLE 0x20 143 #define AUDIOHD_PIN_OUT_ENABLE 0x40 144 #define AUDIOHD_PIN_PRES_OFF 0x20 145 #define AUDIOHD_PIN_CONTP_OFF 0x1e 146 #define AUDIOHD_PIN_CON_JACK 0 147 #define AUDIOHD_PIN_CON_FIXED 0x2 148 #define AUDIOHD_PIN_CONTP_MASK 0x3 149 #define AUDIOHD_PIN_VREF_L1 0x20 150 #define AUDIOHD_PIN_VREF_L2 0x10 151 #define AUDIOHD_PIN_VREF_L3 0x04 152 #define AUDIOHD_PIN_VREF_L4 0x02 153 #define AUDIOHD_PIN_VREF_OFF 8 154 #define AUDIOHD_PIN_VREF_MASK 0xff 155 #define AUDIOHD_PIN_CLR_MASK 0xf 156 #define AUDIOHD_PIN_CLR_OFF 12 157 158 159 #define AUDIOHD_VERB_ADDR_OFF 28 160 #define AUDIOHD_VERB_NID_OFF 20 161 #define AUDIOHD_VERB_CMD_OFF 8 162 #define AUDIOHD_VERB_CMD16_OFF 16 163 164 #define AUDIOHD_RING_MAX_SIZE 0x00ff 165 #define AUDIOHD_REC_TAG_OFF 4 166 #define AUDIOHD_PLAY_TAG_OFF 4 167 #define AUDIOHD_PLAY_CTL_OFF 2 168 #define AUDIOHD_REC_CTL_OFF 2 169 170 #define AUDIOHD_SPDIF_ON 1 171 #define AUDIOHD_SPDIF_MASK 0x00ff 172 173 #define AUDIOHD_GAIN_OFF 8 174 175 #define AUDIOHD_CODEC_STR_OFF 16 176 #define AUDIOHD_CODEC_STR_MASK 0x000000ff 177 #define AUDIOHD_CODEC_NUM_MASK 0x000000ff 178 #define AUDIOHD_CODEC_TYPE_MASK 0x000000ff 179 180 #define AUDIOHD_ROUNDUP(x, algn) (((x) + ((algn) - 1)) & ~((algn) - 1)) 181 #define AUDIOHD_FRAGFR_ALIGN 64 182 #define AUDIOHD_BDLE_BUF_ALIGN 128 183 #define AUDIOHD_CMDIO_ENT_MASK 0x00ff /* 256 entries for CORB/RIRB */ 184 #define AUDIOHD_CDBIO_CORB_LEN 1024 /* 256 entries for CORB, 1024B */ 185 #define AUDIOHD_CDBIO_RIRB_LEN 2048 /* 256 entries for RIRB, 2048B */ 186 #define AUDIOHD_BDLE_NUMS 4 /* 4 entires for record/play BD list */ 187 188 #define AUDIOHD_PORT_UNMUTE (0xffffffff) 189 190 /* 191 * Audio registers of high definition 192 */ 193 #define AUDIOHD_REG_GCAP 0x00 194 #define AUDIOHDR_GCAP_OUTSTREAMS 0xf000 195 #define AUDIOHDR_GCAP_INSTREAMS 0x0f00 196 #define AUDIOHDR_GCAP_BSTREAMS 0x00f8 197 #define AUDIOHDR_GCAP_NSDO 0x0006 198 #define AUDIOHDR_GCAP_64OK 0x0001 199 200 #define AUDIOHD_REG_VMIN 0x02 201 #define AUDIOHD_REG_VMAJ 0x03 202 #define AUDIOHD_REG_OUTPAY 0x04 203 #define AUDIOHD_REG_INPAY 0x06 204 #define AUDIOHD_REG_GCTL 0x08 205 #define AUDIOHD_REG_WAKEEN 0x0C 206 #define AUDIOHD_REG_STATESTS 0x0E 207 #define AUDIOHD_STATESTS_BIT_SDINS 0x7F 208 209 #define AUDIOHD_REG_GSTS 0x10 210 #define AUDIOHD_REG_INTCTL 0x20 211 #define AUDIOHD_INTCTL_BIT_GIE 0x80000000 212 #define AUDIOHD_INTCTL_BIT_CIE 0x40000000 213 #define AUDIOHD_INTCTL_BIT_SIE 0x3FFFFFFF 214 215 216 #define AUDIOHD_REG_INTSTS 0x24 217 #define AUDIOHD_INTSTS_BIT_GIS 0x80000000 218 #define AUDIOHD_INTSTS_BIT_CIS 0x40000000 219 #define AUDIOHD_INTSTS_BIT_SINTS (0x3fffffff) 220 221 #define AUDIOHD_REG_WALCLK 0x30 222 #define AUDIOHD_REG_SYNC 0x38 223 224 #define AUDIOHD_REG_CORBLBASE 0x40 225 #define AUDIOHD_REG_CORBUBASE 0x44 226 #define AUDIOHD_REG_CORBWP 0x48 227 #define AUDIOHD_REG_CORBRP 0x4A 228 #define AUDIOHD_REG_CORBCTL 0x4C 229 #define AUDIOHD_REG_CORBST 0x4D 230 #define AUDIOHD_REG_CORBSIZE 0x4E 231 232 #define AUDIOHD_REG_RIRBLBASE 0x50 233 #define AUDIOHD_REG_RIRBUBASE 0x54 234 #define AUDIOHD_REG_RIRBWP 0x58 235 #define AUDIOHD_REG_RINTCNT 0x5A 236 #define AUDIOHD_REG_RIRBCTL 0x5C 237 #define AUDIOHD_REG_RIRBSTS 0x5D 238 #define AUDIOHD_REG_RIRBSIZE 0x5E 239 240 #define AUDIOHD_REG_IC 0x60 241 #define AUDIOHD_REG_IR 0x64 242 #define AUDIOHD_REG_IRS 0x68 243 #define AUDIOHD_REG_DPLBASE 0x70 244 #define AUDIOHD_REG_DPUBASE 0x74 245 246 #define AUDIOHD_REG_SD_BASE 0x80 247 #define AUDIOHD_REG_SD_LEN 0x20 248 249 /* 250 * Offset of Stream Descriptor Registers 251 */ 252 #define AUDIOHD_SDREG_OFFSET_CTL 0x00 253 #define AUDIOHD_SDREG_OFFSET_STS 0x03 254 #define AUDIOHD_SDREG_OFFSET_LPIB 0x04 255 #define AUDIOHD_SDREG_OFFSET_CBL 0x08 256 #define AUDIOHD_SDREG_OFFSET_LVI 0x0c 257 #define AUDIOHD_SDREG_OFFSET_FIFOW 0x0e 258 #define AUDIOHD_SDREG_OFFSET_FIFOSIZE 0x10 259 #define AUDIOHD_SDREG_OFFSET_FORMAT 0x12 260 #define AUDIOHD_SDREG_OFFSET_BDLPL 0x18 261 #define AUDIOHD_SDREG_OFFSET_BDLPU 0x1c 262 263 /* bits for stream descriptor control reg */ 264 #define AUDIOHDR_SD_CTL_DEIE 0x000010 265 #define AUDIOHDR_SD_CTL_FEIE 0x000008 266 #define AUDIOHDR_SD_CTL_IOCE 0x000004 267 #define AUDIOHDR_SD_CTL_SRUN 0x000002 268 #define AUDIOHDR_SD_CTL_SRST 0x000001 269 #define AUDIOHDR_SD_CTL_INTS \ 270 (AUDIOHDR_SD_CTL_DEIE | \ 271 AUDIOHDR_SD_CTL_FEIE | \ 272 AUDIOHDR_SD_CTL_IOCE) 273 274 275 /* bits for stream descriptor status register */ 276 #define AUDIOHDR_SD_STS_BCIS 0x0004 277 #define AUDIOHDR_SD_STS_FIFOE 0x0008 278 #define AUDIOHDR_SD_STS_DESE 0x0010 279 #define AUDIOHDR_SD_STS_FIFORY 0x0020 280 #define AUDIOHDR_SD_STS_INTRS \ 281 (AUDIOHDR_SD_STS_BCIS | \ 282 AUDIOHDR_SD_STS_FIFOE | \ 283 AUDIOHDR_SD_STS_DESE) 284 285 286 /* bits for GCTL register */ 287 #define AUDIOHDR_GCTL_CRST 0x00000001 288 #define AUDIOHDR_GCTL_URESPE 0x00000100 289 290 /* bits for CORBRP register */ 291 #define AUDIOHDR_CORBRP_RESET 0x8000 292 #define AUDIOHDR_CORBRP_WPTR 0x00ff 293 294 /* bits for CORBCTL register */ 295 #define AUDIOHDR_CORBCTL_CMEIE 0x01 296 #define AUDIOHDR_CORBCTL_DMARUN 0x02 297 298 /* bits for CORB SIZE register */ 299 #define AUDIOHDR_CORBSZ_8 0 300 #define AUDIOHDR_CORBSZ_16 1 301 #define AUDIOHDR_CORBSZ_256 2 302 303 /* bits for RIRBCTL register */ 304 #define AUDIOHDR_RIRBCTL_RINTCTL 0x01 305 #define AUDIOHDR_RIRBCTL_DMARUN 0x02 306 #define AUDIOHDR_RIRBCTL_RIRBOIC 0x04 307 #define AUDIOHDR_RIRBCTL_RSTINT 0xfe 308 309 /* bits for RIRBWP register */ 310 #define AUDIOHDR_RIRBWP_RESET 0x8000 311 #define AUDIOHDR_RIRBWP_WPTR 0x00ff 312 313 /* bits for RIRB SIZE register */ 314 #define AUDIOHDR_RIRBSZ_8 0 315 #define AUDIOHDR_RIRBSZ_16 1 316 #define AUDIOHDR_RIRBSZ_256 2 317 318 #define AUDIOHD_BDLE_RIRB_SDI 0x0000000f 319 #define AUDIOHD_BDLE_RIRB_UNSOLICIT 0x00000010 320 321 /* HD spec: ID of Root node is 0 */ 322 #define AUDIOHDC_NODE_ROOT 0x00 323 324 /* HD spec: ID of audio function group is "1" */ 325 #define AUDIOHDC_AUDIO_FUNC_GROUP 1 326 327 /* 328 * HD audio verbs can be either 12-bit or 4-bit in length. 329 */ 330 #define AUDIOHDC_12BIT_VERB_MASK 0xfffff000 331 #define AUDIOHDC_4BIT_VERB_MASK 0xfffffff0 332 333 #define AUDIOHDC_SAMPR48000 48000 334 #define AUDIOHDC_MAX_BEEP_GEN 12000 335 #define AUDIOHDC_MIX_BEEP_GEN 47 336 #define AUDIOHDC_MUTE_BEEP_GEN 0x0 337 338 /* 339 * 12-bit verbs 340 */ 341 #define AUDIOHDC_VERB_GET_PARAM 0xf00 342 343 #define AUDIOHDC_VERB_GET_CONN_SEL 0xf01 344 #define AUDIOHDC_VERB_SET_CONN_SEL 0x701 345 346 #define AUDIOHDC_VERB_GET_CONN_LIST_ENT 0xf02 347 #define AUDIOHDC_VERB_GET_PROCESS_STATE 0xf03 348 #define AUDIOHDC_VERB_GET_SDI_SEL 0xf04 349 350 #define AUDIOHDC_VERB_GET_POWER_STATE 0xf05 351 #define AUDIOHDC_VERB_SET_POWER_STATE 0x705 352 353 #define AUDIOHDC_VERB_GET_STREAM_CHANN 0xf06 354 #define AUDIOHDC_VERB_SET_STREAM_CHANN 0x706 355 356 #define AUDIOHDC_VERB_GET_PIN_CTRL 0xf07 357 #define AUDIOHDC_VERB_SET_PIN_CTRL 0x707 358 359 #define AUDIOHDC_VERB_GET_UNS_ENABLE 0xf08 360 361 #define AUDIOHDC_VERB_GET_PIN_SENSE 0xf09 362 #define AUDIOHDC_VERB_EXEC_PIN_SENSE 0x709 363 364 #define AUDIOHDC_VERB_GET_BEEP_GEN 0xf0a 365 #define AUDIOHDC_VERB_SET_BEEP_GEN 0x70a 366 367 #define AUDIOHDC_VERB_GET_EAPD 0xf0c 368 #define AUDIOHDC_VERB_SET_EAPD 0x70c 369 370 #define AUDIOHDC_VERB_GET_DEFAULT_CONF 0xf1c 371 #define AUDIOHDC_VERB_GET_SPDIF_CTL 0xf0d 372 #define AUDIOHDC_VERB_SET_SPDIF_LCL 0x70d 373 374 #define AUDIOHDC_VERB_SET_URCTRL 0x708 375 #define AUDIOHDC_VERB_GET_PIN_SENSE 0xf09 376 377 #define AUDIOHDC_VERB_GET_GPIO_MASK 0xf16 378 #define AUDIOHDC_VERB_SET_GPIO_MASK 0x716 379 380 #define AUDIOHDC_VERB_GET_GPIO_DIREC 0xf17 381 #define AUDIOHDC_VERB_SET_GPIO_DIREC 0x717 382 383 #define AUDIOHDC_VERB_GET_GPIO_DATA 0xf15 384 #define AUDIOHDC_VERB_SET_GPIO_DATA 0x715 385 386 #define AUDIOHDC_VERB_GET_GPIO_STCK 0xf1a 387 #define AUDIOHDC_VERB_SET_GPIO_STCK 0x71a 388 389 #define AUDIOHDC_GPIO_ENABLE 0xff 390 #define AUDIOHDC_GPIO_DIRECT 0xf1 391 392 #define AUDIOHDC_GPIO_DATA_CTRL 0xff 393 #define AUDIOHDC_GPIO_STCK_CTRL 0xff 394 /* 395 * 4-bit verbs 396 */ 397 #define AUDIOHDC_VERB_GET_CONV_FMT 0xa 398 #define AUDIOHDC_VERB_SET_CONV_FMT 0x2 399 400 #define AUDIOHDC_VERB_GET_AMP_MUTE 0xb 401 #define AUDIOHDC_VERB_SET_AMP_MUTE 0x3 402 #define AUDIOHDC_VERB_SET_BEEP_VOL 0x3A0 403 404 /* 405 * parameters of nodes 406 */ 407 #define AUDIOHDC_PAR_VENDOR_ID 0x00 408 #define AUDIOHDC_PAR_SUBSYS_ID 0x01 409 #define AUDIOHDC_PAR_REV_ID 0x02 410 #define AUDIOHDC_PAR_NODE_COUNT 0x04 411 #define AUDIOHDC_PAR_FUNCTION_TYPE 0x05 412 #define AUDIOHDC_PAR_AUDIO_FG_CAP 0x08 413 #define AUDIOHDC_PAR_AUDIO_WID_CAP 0x09 414 #define AUDIOHDC_PAR_PCM 0x0a 415 #define AUDIOHDC_PAR_STREAM 0x0b 416 #define AUDIOHDC_PAR_PIN_CAP 0x0c 417 #define AUDIOHDC_PAR_INAMP_CAP 0x0d 418 #define AUDIOHDC_PAR_CONNLIST_LEN 0x0e 419 #define AUDIOHDC_PAR_POWER_STATE 0x0f 420 #define AUDIOHDC_PAR_PROC_CAP 0x10 421 #define AUDIOHDC_PAR_GPIO_CAP 0x11 422 #define AUDIOHDC_PAR_OUTAMP_CAP 0x12 423 424 /* 425 * bits for get/set amplifier gain/mute 426 */ 427 #define AUDIOHDC_AMP_SET_OUTPUT 0x8000 428 #define AUDIOHDC_AMP_SET_INPUT 0x4000 429 #define AUDIOHDC_AMP_SET_LEFT 0x2000 430 #define AUDIOHDC_AMP_SET_RIGHT 0x1000 431 #define AUDIOHDC_AMP_SET_MUTE 0x0080 432 #define AUDIOHDC_AMP_SET_LNR 0x3000 433 #define AUDIOHDC_AMP_SET_LR_INPUT 0x7000 434 #define AUDIOHDC_AMP_SET_LR_OUTPUT 0xb000 435 #define AUDIOHDC_AMP_SET_INDEX_OFFSET 8 436 #define AUDIOHDC_AMP_SET_GAIN_MASK 0x007f 437 #define AUDIOHDC_GAIN_MAX 0x7f 438 #define AUDIOHDC_GAIN_BITS 7 439 #define AUDIOHDC_GAIN_DEFAULT 0x0f 440 441 #define AUDIOHDC_AMP_GET_OUTPUT 0x8000 442 #define AUDIOHDC_AMP_GET_INPUT 0x0000 443 444 /* value used to set max volume for left output */ 445 #define AUDIOHDC_AMP_LOUT_MAX \ 446 (AUDIOHDC_AMP_SET_OUTPUT | \ 447 AUDIOHDC_AMP_SET_LEFT | \ 448 AUDIOHDC_GAIN_MAX) 449 450 /* value used to set max volume for right output */ 451 #define AUDIOHDC_AMP_ROUT_MAX \ 452 (AUDIOHDC_AMP_SET_OUTPUT | \ 453 AUDIOHDC_AMP_SET_RIGHT | \ 454 AUDIOHDC_GAIN_MAX) 455 456 457 /* 458 * Bits for pin widget control verb 459 */ 460 #define AUDIOHDC_PIN_CONTROL_HP_ENABLE 0x80 461 #define AUDIOHDC_PIN_CONTROL_OUT_ENABLE 0x40 462 #define AUDIOHDC_PIN_CONTROL_IN_ENABLE 0x20 463 464 /* 465 * Bits for Amplifier capabilities 466 */ 467 #define AUDIOHDC_AMP_CAP_MUTE_CAP 0x80000000 468 #define AUDIOHDC_AMP_CAP_STEP_SIZE 0x007f0000 469 #define AUDIOHDC_AMP_CAP_STEP_NUMS 0x00007f00 470 #define AUDIOHDC_AMP_CAP_0DB_OFFSET 0x0000007f 471 472 473 /* 474 * Bits for Audio Widget Capabilities 475 */ 476 #define AUDIOHD_WIDCAP_STEREO 0x00000001 477 #define AUDIOHD_WIDCAP_INAMP 0x00000002 478 #define AUDIOHD_WIDCAP_OUTAMP 0x00000004 479 #define AUDIOHD_WIDCAP_AMP_OVRIDE 0x00000008 480 #define AUDIOHD_WIDCAP_FMT_OVRIDE 0x00000010 481 #define AUDIOHD_WIDCAP_STRIP 0x00000020 482 #define AUDIOHD_WIDCAP_PROC_WID 0x00000040 483 #define AUDIOHD_WIDCAP_UNSOL 0x00000080 484 #define AUDIOHD_WIDCAP_CONNLIST 0x00000100 485 #define AUDIOHD_WIDCAP_DIGIT 0x00000200 486 #define AUDIOHD_WIDCAP_PWRCTRL 0x00000400 487 #define AUDIOHD_WIDCAP_LRSWAP 0x00000800 488 #define AUDIOHD_WIDCAP_TYPE 0x00f00000 489 #define AUDIOHD_WIDCAP_TO_WIDTYPE(wcap) \ 490 ((wcap & AUDIOHD_WIDCAP_TYPE) >> 20) 491 492 493 #define AUDIOHD_CODEC_FAILURE (uint32_t)(-1) 494 495 /* 496 * buffer descriptor list entry of stream descriptor 497 */ 498 typedef struct { 499 uint64_t sbde_addr; 500 uint32_t sbde_len; 501 uint32_t 502 sbde_ioc: 1, 503 reserved: 31; 504 }sd_bdle_t; 505 506 507 #define AUDIOHD_PLAY_STARTED 0x00000001 508 #define AUDIOHD_PLAY_EMPTY 0x00000002 509 #define AUDIOHD_PLAY_PAUSED 0x00000004 510 #define AUDIOHD_RECORD_STARTED 0x00000008 511 512 enum audiohda_widget_type { 513 WTYPE_AUDIO_OUT = 0, 514 WTYPE_AUDIO_IN, 515 WTYPE_AUDIO_MIX, 516 WTYPE_AUDIO_SEL, 517 WTYPE_PIN, 518 WTYPE_POWER, 519 WTYPE_VOL_KNOB, 520 WTYPE_BEEP, 521 WTYPE_VENDOR = 0xf 522 }; 523 524 enum audiohda_device_type { 525 DTYPE_LINEOUT = 0, 526 DTYPE_SPEAKER, 527 DTYPE_HP_OUT, 528 DTYPE_CD, 529 DTYPE_SPDIF_OUT, 530 DTYPE_DIGIT_OUT, 531 DTYPE_MODEM_SIDE, 532 DTYPE_MODEM_HNAD_SIDE, 533 DTYPE_LINE_IN, 534 DTYPE_AUX, 535 DTYPE_MIC_IN, 536 DTYPE_TEL, 537 DTYPE_SPDIF_IN, 538 DTYPE_DIGIT_IN, 539 DTYPE_OTHER = 0x0f, 540 }; 541 542 enum audiohd_pin_color { 543 AUDIOHD_PIN_UNKNOWN = 0, 544 AUDIOHD_PIN_BLACK, 545 AUDIOHD_PIN_GREY, 546 AUDIOHD_PIN_BLUE, 547 AUDIOHD_PIN_GREEN, 548 AUDIOHD_PIN_RED, 549 AUDIOHD_PIN_ORANGE, 550 AUDIOHD_PIN_YELLOW, 551 AUDIOHD_PIN_PURPLE, 552 AUDIOHD_PIN_PINK, 553 AUDIOHD_PIN_WHITE = 0xe, 554 AUDIOHD_PIN_OTHER = 0xf, 555 }; 556 557 #define CTRL_NUM 16 558 559 /* values for audiohd_widget.path_flags */ 560 #define AUDIOHD_PATH_DAC (1 << 0) 561 #define AUDIOHD_PATH_ADC (1 << 1) 562 #define AUDIOHD_PATH_MON (1 << 2) 563 #define AUDIOHD_PATH_NOMON (1 << 3) 564 #define AUDIOHD_PATH_BEEP (1 << 4) 565 566 typedef struct audiohd_path audiohd_path_t; 567 typedef struct audiohd_widget audiohd_widget_t; 568 typedef struct audiohd_state audiohd_state_t; 569 typedef struct audiohd_codec_info audiohd_codec_info_t; 570 typedef struct audiohd_pin audiohd_pin_t; 571 typedef struct hda_codec hda_codec_t; 572 typedef uint32_t wid_t; /* id of widget */ 573 typedef struct audiohd_entry_prop audiohd_entry_prop_t; 574 typedef enum audiohda_device_type audiohda_device_type_t; 575 typedef enum audiohd_pin_color audiohd_pin_color_t; 576 577 #define AUDIOHD_MAX_WIDGET 128 578 #define AUDIOHD_MAX_CONN 16 579 #define AUDIOHD_MAX_PINS 16 580 #define AUDIOHD_MAX_DEPTH 8 581 582 struct audiohd_entry_prop { 583 uint32_t conn_len; 584 uint32_t mask_range; 585 uint32_t mask_wid; 586 wid_t input_wid; 587 int conns_per_entry; 588 int bits_per_conn; 589 }; 590 struct audiohd_widget { 591 wid_t wid_wid; 592 hda_codec_t *codec; 593 enum audiohda_widget_type type; 594 595 uint32_t widget_cap; 596 uint32_t pcm_format; 597 uint32_t inamp_cap; 598 uint32_t outamp_cap; 599 600 uint32_t path_flags; 601 602 int out_weight; 603 int in_weight; 604 int finish; 605 606 /* 607 * wid of possible & selected input connections 608 */ 609 wid_t avail_conn[AUDIOHD_MAX_CONN]; 610 wid_t selconn; 611 /* 612 * for monitor path 613 */ 614 wid_t selmon[AUDIOHD_MAX_CONN]; 615 uint16_t used; 616 617 /* 618 * available (input) connections. 0 means this widget 619 * has fixed connection 620 */ 621 int nconns; 622 623 /* 624 * pointer to struct depending on widget type: 625 * 1. DAC audiohd_ostream_t 626 * 2. ADC audiohd_istream_t 627 * 3. PIN audiohd_pin_t 628 */ 629 void *priv; 630 }; 631 632 #define AUDIOHD_FLAG_LINEOUT (1 << 0) 633 #define AUDIOHD_FLAG_SPEAKER (1 << 1) 634 #define AUDIOHD_FLAG_HP (1 << 2) 635 #define AUDIOHD_FLAG_MONO (1 << 3) 636 637 #define AUDIOHD_MAX_MIXER 5 638 #define AUDIOHD_MAX_PIN 4 639 640 #define PORT_DAC 0 641 #define PORT_ADC 1 642 #define PORT_MAX 2 643 typedef enum { 644 PLAY = 0, 645 RECORD = 1, 646 BEEP = 2, 647 } path_type_t; 648 649 struct audiohd_path { 650 wid_t adda_wid; 651 wid_t beep_wid; 652 653 wid_t pin_wid[AUDIOHD_MAX_PINS]; 654 int sum_selconn[AUDIOHD_MAX_PINS]; 655 int mon_wid[AUDIOHD_MAX_PIN][AUDIOHD_MAX_MIXER]; 656 int pin_nums; 657 int maxmixer[AUDIOHD_MAX_PINS]; 658 659 path_type_t path_type; 660 661 wid_t mute_wid; 662 int mute_dir; 663 wid_t gain_wid; 664 int gain_dir; 665 uint32_t gain_bits; 666 667 uint32_t pin_outputs; 668 uint8_t tag; 669 670 hda_codec_t *codec; 671 672 wid_t sum_wid; 673 674 audiohd_state_t *statep; 675 }; 676 677 typedef struct audiohd_port 678 { 679 uint8_t nchan; 680 int index; 681 uint16_t regoff; 682 boolean_t started; 683 boolean_t triggered; 684 685 unsigned fragfr; 686 unsigned nframes; 687 uint64_t count; 688 int curpos; 689 int intrs; 690 691 uint_t format; 692 unsigned sync_dir; 693 694 ddi_dma_handle_t samp_dmah; 695 ddi_acc_handle_t samp_acch; 696 size_t samp_size; 697 caddr_t samp_kaddr; 698 uint64_t samp_paddr; 699 700 ddi_dma_handle_t bdl_dmah; 701 ddi_acc_handle_t bdl_acch; 702 size_t bdl_size; 703 caddr_t bdl_kaddr; 704 uint64_t bdl_paddr; 705 706 audio_engine_t *engine; 707 audiohd_state_t *statep; 708 }audiohd_port_t; 709 710 typedef struct audiohd_ctrl 711 { 712 audiohd_state_t *statep; 713 audio_ctrl_t *ctrl; 714 uint32_t num; 715 uint64_t val; 716 } audiohd_ctrl_t; 717 718 struct audiohd_pin { 719 audiohd_pin_t *next; 720 wid_t wid; 721 wid_t mute_wid; /* node used to mute this pin */ 722 int mute_dir; /* 1: input, 2: output */ 723 wid_t gain_wid; /* node for gain control */ 724 int gain_dir; /* _OUTPUT/_INPUT */ 725 uint32_t gain_bits; 726 727 uint8_t vrefvalue; /* value of VRef */ 728 729 uint32_t cap; 730 uint32_t config; 731 uint32_t ctrl; 732 uint32_t assoc; 733 uint32_t seq; 734 wid_t adc_dac_wid; /* AD/DA wid which can route to this pin */ 735 wid_t beep_wid; 736 int no_phys_conn; 737 enum audiohda_device_type device; 738 739 /* 740 * mg_dir, mg_gain, mg_wid are used to store the monitor gain control 741 * widget wid. 742 */ 743 int mg_dir[AUDIOHD_MAX_CONN]; 744 int mg_gain[AUDIOHD_MAX_CONN]; 745 int mg_wid[AUDIOHD_MAX_CONN]; 746 int num; 747 int finish; 748 749 }; 750 751 typedef struct { 752 ddi_dma_handle_t ad_dmahdl; 753 ddi_acc_handle_t ad_acchdl; 754 caddr_t ad_vaddr; /* virtual addr */ 755 uint64_t ad_paddr; /* physical addr */ 756 size_t ad_req_sz; /* required size of memory */ 757 size_t ad_real_sz; /* real size of memory */ 758 } audiohd_dma_t; 759 760 struct hda_codec { 761 uint8_t index; /* codec address */ 762 uint32_t vid; /* vendor id and device id */ 763 uint32_t revid; /* revision id */ 764 wid_t wid_afg; /* id of AFG */ 765 wid_t first_wid; /* wid of 1st subnode of AFG */ 766 wid_t last_wid; /* wid of the last subnode of AFG */ 767 int nnodes; /* # of subnodes of AFG */ 768 uint8_t nistream; 769 770 uint32_t outamp_cap; 771 uint32_t inamp_cap; 772 uint32_t stream_format; 773 uint32_t pcm_format; 774 775 audiohd_state_t *soft_statep; 776 audiohd_codec_info_t *codec_info; 777 778 /* use wid as index to the array of widget pointers */ 779 audiohd_widget_t *widget[AUDIOHD_MAX_WIDGET]; 780 781 audiohd_port_t *port[AUDIOHD_PORT_MAX]; 782 uint8_t portnum; 783 audiohd_pin_t *first_pin; 784 }; 785 786 #define AUDIOHD_MAX_ASSOC 15 787 struct audiohd_state { 788 dev_info_t *hda_dip; 789 kstat_t *hda_ksp; 790 kmutex_t hda_mutex; 791 uint32_t hda_flags; 792 793 boolean_t soft_volume; 794 795 caddr_t hda_reg_base; 796 ddi_acc_handle_t hda_pci_handle; 797 ddi_acc_handle_t hda_reg_handle; 798 799 ddi_intr_handle_t *htable; /* For array of interrupts */ 800 boolean_t intr_added; 801 int intr_type; /* What type of interrupt */ 802 int intr_rqst; /* # of request intrs count */ 803 int intr_cnt; /* # of intrs count returned */ 804 uint_t intr_pri; /* Interrupt priority */ 805 int intr_cap; /* Interrupt capabilities */ 806 boolean_t msi_enable; 807 808 audiohd_dma_t hda_dma_corb; 809 audiohd_dma_t hda_dma_rirb; 810 811 812 uint8_t hda_rirb_rp; /* read pointer for rirb */ 813 uint16_t hda_codec_mask; 814 815 816 audio_dev_t *adev; 817 uint32_t devid; 818 819 820 int hda_pint_freq; /* play intr frequence */ 821 int hda_rint_freq; /* record intr frequence */ 822 823 int hda_input_streams; /* # of input stream */ 824 int hda_output_streams; /* # of output stream */ 825 int hda_streams_nums; /* # of stream */ 826 827 uint_t hda_play_regbase; 828 uint_t hda_record_regbase; 829 830 uint_t hda_play_stag; /* tag of playback stream */ 831 uint_t hda_record_stag; /* tag of record stream */ 832 uint_t hda_play_lgain; /* left gain for playback */ 833 uint_t hda_play_rgain; /* right gain for playback */ 834 835 /* 836 * Now, for the time being, we add some fields 837 * for parsing codec topology 838 */ 839 hda_codec_t *codec[AUDIOHD_CODEC_MAX]; 840 /* 841 * Suspend/Resume used fields 842 */ 843 boolean_t suspended; 844 boolean_t monitor_unsupported; 845 846 audiohd_path_t *path[AUDIOHD_PORT_MAX]; 847 uint8_t pathnum; 848 audiohd_port_t *port[PORT_MAX]; 849 uint8_t pchan; 850 uint8_t rchan; 851 852 uint64_t inmask; 853 854 uint_t hda_out_ports; 855 uint_t in_port; 856 857 /* 858 * Controls 859 */ 860 audiohd_ctrl_t *controls[CTRL_NUM]; 861 862 /* for multichannel */ 863 uint8_t chann[AUDIOHD_MAX_ASSOC]; 864 uint8_t assoc; 865 866 }; 867 868 struct audiohd_codec_info { 869 uint32_t devid; 870 const char *buf; 871 uint32_t flags; 872 }; 873 874 /* 875 * Operation for high definition audio control system bus 876 * interface registers 877 */ 878 #define AUDIOHD_REG_GET8(reg) \ 879 ddi_get8(statep->hda_reg_handle, \ 880 (void *)((char *)statep->hda_reg_base + (reg))) 881 882 #define AUDIOHD_REG_GET16(reg) \ 883 ddi_get16(statep->hda_reg_handle, \ 884 (void *)((char *)statep->hda_reg_base + (reg))) 885 886 #define AUDIOHD_REG_GET32(reg) \ 887 ddi_get32(statep->hda_reg_handle, \ 888 (void *)((char *)statep->hda_reg_base + (reg))) 889 890 #define AUDIOHD_REG_GET64(reg) \ 891 ddi_get64(statep->hda_reg_handle, \ 892 (void *)((char *)statep->hda_reg_base + (reg))) 893 894 #define AUDIOHD_REG_SET8(reg, val) \ 895 ddi_put8(statep->hda_reg_handle, \ 896 (void *)((char *)statep->hda_reg_base + (reg)), (val)) 897 898 #define AUDIOHD_REG_SET16(reg, val) \ 899 ddi_put16(statep->hda_reg_handle, \ 900 (void *)((char *)statep->hda_reg_base + (reg)), (val)) 901 902 #define AUDIOHD_REG_SET32(reg, val) \ 903 ddi_put32(statep->hda_reg_handle, \ 904 (void *)((char *)statep->hda_reg_base + (reg)), (val)) 905 906 #define AUDIOHD_REG_SET64(reg, val) \ 907 ddi_put64(statep->hda_reg_handle, \ 908 (void *)((char *)statep->hda_reg_base + (reg)), (val)) 909 910 911 /* 912 * enable a pin widget to output 913 */ 914 #define AUDIOHD_ENABLE_PIN_OUT(statep, caddr, wid) \ 915 { \ 916 uint32_t lTmp; \ 917 \ 918 lTmp = audioha_codec_verb_get(statep, caddr, wid, \ 919 AUDIOHDC_VERB_GET_PIN_CTRL, 0); \ 920 if (lTmp == AUDIOHD_CODEC_FAILURE) \ 921 return (DDI_FAILURE); \ 922 lTmp = audioha_codec_verb_get(statep, caddr, wid, \ 923 AUDIOHDC_VERB_SET_PIN_CTRL, \ 924 (lTmp | AUDIOHDC_PIN_CONTROL_OUT_ENABLE | \ 925 AUDIOHDC_PIN_CONTROL_HP_ENABLE)); \ 926 if (lTmp == AUDIOHD_CODEC_FAILURE) \ 927 return (DDI_FAILURE); \ 928 } 929 930 /* 931 * disable output pin 932 */ 933 #define AUDIOHD_DISABLE_PIN_OUT(statep, caddr, wid) \ 934 { \ 935 uint32_t lTmp; \ 936 \ 937 lTmp = audioha_codec_verb_get(statep, caddr, wid, \ 938 AUDIOHDC_VERB_GET_PIN_CTRL, 0); \ 939 if (lTmp == AUDIOHD_CODEC_FAILURE) \ 940 return (DDI_FAILURE); \ 941 lTmp = audioha_codec_verb_get(statep, caddr, wid, \ 942 AUDIOHDC_VERB_SET_PIN_CTRL, \ 943 (lTmp & ~AUDIOHDC_PIN_CONTROL_OUT_ENABLE)); \ 944 if (lTmp == AUDIOHD_CODEC_FAILURE) \ 945 return (DDI_FAILURE); \ 946 } 947 948 /* 949 * enable a pin widget to input 950 */ 951 #define AUDIOHD_ENABLE_PIN_IN(statep, caddr, wid) \ 952 { \ 953 (void) audioha_codec_verb_get(statep, caddr, wid, \ 954 AUDIOHDC_VERB_SET_PIN_CTRL, AUDIOHDC_PIN_CONTROL_IN_ENABLE | 4); \ 955 } 956 957 958 /* 959 * disable input pin 960 */ 961 #define AUDIOHD_DISABLE_PIN_IN(statep, caddr, wid) \ 962 { \ 963 uint32_t lTmp; \ 964 \ 965 lTmp = audioha_codec_verb_get(statep, caddr, wid, \ 966 AUDIOHDC_VERB_GET_PIN_CTRL, 0); \ 967 if (lTmp == AUDIOHD_CODEC_FAILURE) \ 968 return (DDI_FAILURE); \ 969 lTmp = audioha_codec_verb_get(statep, caddr, wid, \ 970 AUDIOHDC_VERB_SET_PIN_CTRL, \ 971 (lTmp & ~AUDIOHDC_PIN_CONTROL_IN_ENABLE)); \ 972 if (lTmp == AUDIOHD_CODEC_FAILURE) \ 973 return (DDI_FAILURE); \ 974 } 975 976 /* 977 * unmute an output pin 978 */ 979 #define AUDIOHD_NODE_UNMUTE_OUT(statep, caddr, wid) \ 980 { \ 981 if (audioha_codec_4bit_verb_get(statep, \ 982 caddr, wid, AUDIOHDC_VERB_SET_AMP_MUTE, \ 983 AUDIOHDC_AMP_SET_LR_OUTPUT | AUDIOHDC_GAIN_MAX) == \ 984 AUDIOHD_CODEC_FAILURE) \ 985 return (DDI_FAILURE); \ 986 } 987 988 /* 989 * check volume adjust value of 2 channels control 990 */ 991 #define AUDIOHD_CHECK_2CHANNELS_VOLUME(value) \ 992 { \ 993 if ((value) & ~0xffff) \ 994 return (EINVAL); \ 995 if ((((value) & 0xff00) >> 8) > 100 || \ 996 ((value) & 0xff) > 100) \ 997 return (EINVAL); \ 998 } 999 1000 /* 1001 * check volume adjust value of mono channel control 1002 */ 1003 #define AUDIOHD_CHECK_CHANNEL_VOLUME(value) \ 1004 { \ 1005 if ((value) & ~0xff) \ 1006 return (EINVAL); \ 1007 if (((value) & 0xff) > 100) \ 1008 return (EINVAL); \ 1009 } 1010 1011 #ifdef __cplusplus 1012 } 1013 #endif 1014 1015 #endif /* _SYS_AUDIOHD_IMPL_H_ */ 1016