1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License (the "License"). 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9 * or http://www.opensolaris.org/os/licensing. 10 * See the License for the specific language governing permissions 11 * and limitations under the License. 12 * 13 * When distributing Covered Code, include this CDDL HEADER in each 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15 * If applicable, add the following below this CDDL HEADER, with the 16 * fields enclosed by brackets "[]" replaced with your own identifying 17 * information: Portions Copyright [yyyy] [name of copyright owner] 18 * 19 * CDDL HEADER END 20 */ 21 /* 22 * Copyright (c) 2006, 2010, Oracle and/or its affiliates. All rights reserved. 23 */ 24 #ifndef _SYS_AUDIOHD_IMPL_H_ 25 #define _SYS_AUDIOHD_IMPL_H_ 26 27 #ifdef __cplusplus 28 extern "C" { 29 #endif 30 31 /* 32 * vendor IDs of PCI audio controllers 33 */ 34 #define AUDIOHD_VID_ATI 0x1002 35 #define AUDIOHD_VID_CIRRUS 0x1013 36 #define AUDIOHD_VID_NVIDIA 0x10de 37 #define AUDIOHD_VID_REALTEK 0x10ec 38 #define AUDIOHD_VID_CREATIVE 0x1102 39 #define AUDIOHD_VID_IDT 0x111d 40 #define AUDIOHD_VID_ANALOG 0x11d4 41 #define AUDIOHD_VID_CONEXANT 0x14f1 42 #define AUDIOHD_VID_SIGMATEL 0x8384 43 #define AUDIOHD_VID_INTEL 0x8086 44 45 /* 46 * specific audiohd controller device id 47 */ 48 #define AUDIOHD_CONTROLLER_MCP51 0x10de026c 49 50 /* 51 * codec special initial flags 52 */ 53 #define NO_GPIO 0x00000001 54 #define NO_MIXER 0x00000002 55 #define NO_SPDIF 0x00000004 56 #define EN_PIN_BEEP 0x00000008 57 58 #define AUDIOHD_DEV_CONFIG "onboard1" 59 #define AUDIOHD_DEV_VERSION "a" 60 61 #define AUDIOHD_FMT_PCM 0x001 62 /* 63 * Only for Intel hardware: 64 * PCI Express traffic class select register in PCI configure space 65 */ 66 #define AUDIOHD_INTEL_PCI_TCSEL 0x44 67 #define AUDIOHD_INTEL_TCS_MASK 0xf8 68 69 /* 70 * Only for ATI SB450: 71 * MISC control register 2 72 */ 73 #define AUDIOHD_ATI_PCI_MISC2 0x42 74 #define AUDIOHD_ATI_MISC2_MASK 0xf8 75 #define AUDIOHD_ATI_MISC2_SNOOP 0x02 76 77 /* NVIDIA snoop */ 78 #define AUDIOHD_NVIDIA_SNOOP 0x0f 79 80 #define AUDIOHDC_NID(x) x 81 #define AUDIOHDC_NULL_NODE -1 82 #define AUDIOHD_NULL_CONN ((uint_t)(-1)) 83 84 #define AUDIOHD_EXT_AMP_MASK 0x00010000 85 #define AUDIOHD_EXT_AMP_ENABLE 0x02 86 87 /* Power On/Off */ 88 #define AUDIOHD_PW_D0 0 89 #define AUDIOHD_PW_D2 2 90 91 /* Pin speaker On/Off */ 92 #define AUDIOHD_SP_ON 1 93 #define AUDIOHD_SP_OFF 0 94 95 #define AUDIOHD_PORT_MAX 15 96 #define AUDIOHD_CODEC_MAX 16 97 #define AUDIOHD_MEMIO_LEN 0x4000 98 99 #define AUDIOHD_RETRY_TIMES 60 100 #define AUDIOHD_TEST_TIMES 500 101 #define AUDIOHD_OUTSTR_NUM_OFF 12 102 #define AUDIOHD_INSTR_NUM_OFF 8 103 104 #define AUDIOHD_CORB_SIZE_OFF 0x4e 105 106 #define AUDIOHD_URCAP_MASK 0x80 107 #define AUDIOHD_DTCCAP_MASK 0x4 108 #define AUDIOHD_UR_ENABLE_OFF 8 109 #define AUDIOHD_UR_TAG_MASK 0x3f 110 111 #define AUDIOHD_CIS_MASK 0x40000000 112 113 #define AUDIOHD_RIRB_UR_MASK 0x10 114 #define AUDIOHD_RIRB_CODEC_MASK 0xf 115 #define AUDIOHD_RIRB_WID_OFF 27 116 #define AUDIOHD_RIRB_INTRCNT 0x0 117 #define AUDIOHD_RIRB_WPMASK 0xff 118 119 #define AUDIOHD_FORM_MASK 0x0080 120 #define AUDIOHD_LEN_MASK 0x007f 121 #define AUDIOHD_PIN_CAP_MASK 0x00000010 122 #define AUDIOHD_PIN_CONF_MASK 0xc0000000 123 #define AUDIOHD_PIN_CON_MASK 3 124 #define AUDIOHD_PIN_CON_STEP 30 125 #define AUDIOHD_PIN_IO_MASK 0X0018 126 #define AUDIOHD_PIN_SEQ_MASK 0x0000000f 127 #define AUDIOHD_PIN_ASO_MASK 0x000000f0 128 #define AUDIOHD_PIN_ASO_OFF 0x4 129 #define AUDIOHD_PIN_DEV_MASK 0x00f00000 130 #define AUDIOHD_PIN_DEV_OFF 20 131 #define AUDIOHD_PIN_NUMS 6 132 #define AUDIOHD_PIN_NO_CONN 0x40000000 133 #define AUDIOHD_PIN_IN_ENABLE 0x20 134 #define AUDIOHD_PIN_OUT_ENABLE 0x40 135 #define AUDIOHD_PIN_PRES_MASK 0x80000000 136 #define AUDIOHD_PIN_CONTP_OFF 0x1e 137 #define AUDIOHD_PIN_CON_JACK 0 138 #define AUDIOHD_PIN_CON_FIXED 0x2 139 #define AUDIOHD_PIN_CONTP_MASK 0x3 140 #define AUDIOHD_PIN_VREF_L1 0x20 141 #define AUDIOHD_PIN_VREF_L2 0x10 142 #define AUDIOHD_PIN_VREF_L3 0x04 143 #define AUDIOHD_PIN_VREF_L4 0x02 144 #define AUDIOHD_PIN_VREF_OFF 8 145 #define AUDIOHD_PIN_VREF_MASK 0xff 146 #define AUDIOHD_PIN_CLR_MASK 0xf 147 #define AUDIOHD_PIN_CLR_OFF 12 148 149 #define AUDIOHD_VERB_ADDR_OFF 28 150 #define AUDIOHD_VERB_NID_OFF 20 151 #define AUDIOHD_VERB_CMD_OFF 8 152 #define AUDIOHD_VERB_CMD16_OFF 16 153 154 #define AUDIOHD_RING_MAX_SIZE 0x00ff 155 #define AUDIOHD_REC_TAG_OFF 4 156 #define AUDIOHD_PLAY_TAG_OFF 4 157 #define AUDIOHD_PLAY_CTL_OFF 2 158 #define AUDIOHD_REC_CTL_OFF 2 159 160 #define AUDIOHD_SPDIF_ON 1 161 #define AUDIOHD_SPDIF_MASK 0x00ff 162 163 #define AUDIOHD_GAIN_OFF 8 164 165 #define AUDIOHD_CODEC_STR_OFF 16 166 #define AUDIOHD_CODEC_STR_MASK 0x000000ff 167 #define AUDIOHD_CODEC_NUM_MASK 0x000000ff 168 #define AUDIOHD_CODEC_TYPE_MASK 0x000000ff 169 170 #define AUDIOHD_ROUNDUP(x, algn) (((x) + ((algn) - 1)) & ~((algn) - 1)) 171 #define AUDIOHD_BDLE_BUF_ALIGN 128 172 #define AUDIOHD_CMDIO_ENT_MASK 0x00ff /* 256 entries for CORB/RIRB */ 173 #define AUDIOHD_CDBIO_CORB_LEN 1024 /* 256 entries for CORB, 1024B */ 174 #define AUDIOHD_CDBIO_RIRB_LEN 2048 /* 256 entries for RIRB, 2048B */ 175 #define AUDIOHD_BDLE_NUMS 4 /* 4 entires for record/play BD list */ 176 177 #define AUDIOHD_PORT_UNMUTE (0xffffffff) 178 179 /* 180 * Audio registers of high definition 181 */ 182 #define AUDIOHD_REG_GCAP 0x00 183 #define AUDIOHDR_GCAP_OUTSTREAMS 0xf000 184 #define AUDIOHDR_GCAP_INSTREAMS 0x0f00 185 #define AUDIOHDR_GCAP_BSTREAMS 0x00f8 186 #define AUDIOHDR_GCAP_NSDO 0x0006 187 #define AUDIOHDR_GCAP_64OK 0x0001 188 189 #define AUDIOHD_REG_VMIN 0x02 190 #define AUDIOHD_REG_VMAJ 0x03 191 #define AUDIOHD_REG_OUTPAY 0x04 192 #define AUDIOHD_REG_INPAY 0x06 193 #define AUDIOHD_REG_GCTL 0x08 194 #define AUDIOHD_REG_WAKEEN 0x0C 195 #define AUDIOHD_REG_STATESTS 0x0E 196 #define AUDIOHD_STATESTS_BIT_SDINS 0x7F 197 198 #define AUDIOHD_REG_GSTS 0x10 199 #define AUDIOHD_REG_INTCTL 0x20 200 #define AUDIOHD_INTCTL_BIT_GIE 0x80000000 201 #define AUDIOHD_INTCTL_BIT_CIE 0x40000000 202 #define AUDIOHD_INTCTL_BIT_SIE 0x3FFFFFFF 203 204 205 #define AUDIOHD_REG_INTSTS 0x24 206 #define AUDIOHD_INTSTS_BIT_GIS 0x80000000 207 #define AUDIOHD_INTSTS_BIT_CIS 0x40000000 208 #define AUDIOHD_INTSTS_BIT_SINTS (0x3fffffff) 209 210 #define AUDIOHD_REG_WALCLK 0x30 211 #define AUDIOHD_REG_SYNC 0x38 212 213 #define AUDIOHD_REG_CORBLBASE 0x40 214 #define AUDIOHD_REG_CORBUBASE 0x44 215 #define AUDIOHD_REG_CORBWP 0x48 216 #define AUDIOHD_REG_CORBRP 0x4A 217 #define AUDIOHD_REG_CORBCTL 0x4C 218 #define AUDIOHD_REG_CORBST 0x4D 219 #define AUDIOHD_REG_CORBSIZE 0x4E 220 221 #define AUDIOHD_REG_RIRBLBASE 0x50 222 #define AUDIOHD_REG_RIRBUBASE 0x54 223 #define AUDIOHD_REG_RIRBWP 0x58 224 #define AUDIOHD_REG_RINTCNT 0x5A 225 #define AUDIOHD_REG_RIRBCTL 0x5C 226 #define AUDIOHD_REG_RIRBSTS 0x5D 227 #define AUDIOHD_REG_RIRBSIZE 0x5E 228 229 #define AUDIOHD_REG_IC 0x60 230 #define AUDIOHD_REG_IR 0x64 231 #define AUDIOHD_REG_IRS 0x68 232 #define AUDIOHD_REG_DPLBASE 0x70 233 #define AUDIOHD_REG_DPUBASE 0x74 234 235 #define AUDIOHD_REG_SD_BASE 0x80 236 #define AUDIOHD_REG_SD_LEN 0x20 237 238 /* 239 * Offset of Stream Descriptor Registers 240 */ 241 #define AUDIOHD_SDREG_OFFSET_CTL 0x00 242 #define AUDIOHD_SDREG_OFFSET_STS 0x03 243 #define AUDIOHD_SDREG_OFFSET_LPIB 0x04 244 #define AUDIOHD_SDREG_OFFSET_CBL 0x08 245 #define AUDIOHD_SDREG_OFFSET_LVI 0x0c 246 #define AUDIOHD_SDREG_OFFSET_FIFOW 0x0e 247 #define AUDIOHD_SDREG_OFFSET_FIFOSIZE 0x10 248 #define AUDIOHD_SDREG_OFFSET_FORMAT 0x12 249 #define AUDIOHD_SDREG_OFFSET_BDLPL 0x18 250 #define AUDIOHD_SDREG_OFFSET_BDLPU 0x1c 251 252 /* bits for stream descriptor control reg */ 253 #define AUDIOHDR_SD_CTL_DEIE 0x000010 254 #define AUDIOHDR_SD_CTL_FEIE 0x000008 255 #define AUDIOHDR_SD_CTL_IOCE 0x000004 256 #define AUDIOHDR_SD_CTL_SRUN 0x000002 257 #define AUDIOHDR_SD_CTL_SRST 0x000001 258 259 /* bits for stream descriptor status register */ 260 #define AUDIOHDR_SD_STS_BCIS 0x0004 261 #define AUDIOHDR_SD_STS_FIFOE 0x0008 262 #define AUDIOHDR_SD_STS_DESE 0x0010 263 #define AUDIOHDR_SD_STS_FIFORY 0x0020 264 #define AUDIOHDR_SD_STS_INTRS \ 265 (AUDIOHDR_SD_STS_BCIS | \ 266 AUDIOHDR_SD_STS_FIFOE | \ 267 AUDIOHDR_SD_STS_DESE) 268 269 /* bits for GCTL register */ 270 #define AUDIOHDR_GCTL_CRST 0x00000001 271 #define AUDIOHDR_GCTL_URESPE 0x00000100 272 273 /* bits for CORBRP register */ 274 #define AUDIOHDR_CORBRP_RESET 0x8000 275 #define AUDIOHDR_CORBRP_WPTR 0x00ff 276 277 /* bits for CORBCTL register */ 278 #define AUDIOHDR_CORBCTL_CMEIE 0x01 279 #define AUDIOHDR_CORBCTL_DMARUN 0x02 280 281 /* bits for CORB SIZE register */ 282 #define AUDIOHDR_CORBSZ_8 0 283 #define AUDIOHDR_CORBSZ_16 1 284 #define AUDIOHDR_CORBSZ_256 2 285 286 /* bits for RIRBCTL register */ 287 #define AUDIOHDR_RIRBCTL_RINTCTL 0x01 288 #define AUDIOHDR_RIRBCTL_DMARUN 0x02 289 #define AUDIOHDR_RIRBCTL_RIRBOIC 0x04 290 #define AUDIOHDR_RIRBCTL_RSTINT 0xfe 291 292 /* bits for RIRBWP register */ 293 #define AUDIOHDR_RIRBWP_RESET 0x8000 294 #define AUDIOHDR_RIRBWP_WPTR 0x00ff 295 296 /* bits for RIRB SIZE register */ 297 #define AUDIOHDR_RIRBSZ_8 0 298 #define AUDIOHDR_RIRBSZ_16 1 299 #define AUDIOHDR_RIRBSZ_256 2 300 301 #define AUDIOHD_BDLE_RIRB_SDI 0x0000000f 302 #define AUDIOHD_BDLE_RIRB_UNSOLICIT 0x00000010 303 304 /* HD spec: ID of Root node is 0 */ 305 #define AUDIOHDC_NODE_ROOT 0x00 306 307 /* HD spec: ID of audio function group is "1" */ 308 #define AUDIOHDC_AUDIO_FUNC_GROUP 1 309 310 /* 311 * HD audio verbs can be either 12-bit or 4-bit in length. 312 */ 313 #define AUDIOHDC_12BIT_VERB_MASK 0xfffff000 314 #define AUDIOHDC_4BIT_VERB_MASK 0xfffffff0 315 316 #define AUDIOHDC_SAMPR48000 48000 317 #define AUDIOHDC_MAX_BEEP_GEN 12000 318 #define AUDIOHDC_MIX_BEEP_GEN 47 319 #define AUDIOHDC_MUTE_BEEP_GEN 0x0 320 321 /* 322 * 12-bit verbs 323 */ 324 #define AUDIOHDC_VERB_GET_PARAM 0xf00 325 326 #define AUDIOHDC_VERB_GET_CONN_SEL 0xf01 327 #define AUDIOHDC_VERB_SET_CONN_SEL 0x701 328 329 #define AUDIOHDC_VERB_GET_CONN_LIST_ENT 0xf02 330 #define AUDIOHDC_VERB_GET_PROCESS_STATE 0xf03 331 #define AUDIOHDC_VERB_GET_SDI_SEL 0xf04 332 333 #define AUDIOHDC_VERB_GET_POWER_STATE 0xf05 334 #define AUDIOHDC_VERB_SET_POWER_STATE 0x705 335 336 #define AUDIOHDC_VERB_GET_STREAM_CHANN 0xf06 337 #define AUDIOHDC_VERB_SET_STREAM_CHANN 0x706 338 339 #define AUDIOHDC_VERB_GET_PIN_CTRL 0xf07 340 #define AUDIOHDC_VERB_SET_PIN_CTRL 0x707 341 342 #define AUDIOHDC_VERB_GET_UNS_ENABLE 0xf08 343 #define AUDIOHDC_VERB_SET_UNS_ENABLE 0x708 344 345 #define AUDIOHDC_VERB_GET_PIN_SENSE 0xf09 346 #define AUDIOHDC_VERB_GET_PIN_SENSE 0xf09 347 #define AUDIOHDC_VERB_EXEC_PIN_SENSE 0x709 348 349 #define AUDIOHDC_VERB_GET_BEEP_GEN 0xf0a 350 #define AUDIOHDC_VERB_SET_BEEP_GEN 0x70a 351 352 #define AUDIOHDC_VERB_GET_EAPD 0xf0c 353 #define AUDIOHDC_VERB_SET_EAPD 0x70c 354 355 #define AUDIOHDC_VERB_GET_DEFAULT_CONF 0xf1c 356 #define AUDIOHDC_VERB_GET_SPDIF_CTL 0xf0d 357 #define AUDIOHDC_VERB_SET_SPDIF_LCL 0x70d 358 359 #define AUDIOHDC_VERB_GET_GPIO_MASK 0xf16 360 #define AUDIOHDC_VERB_SET_GPIO_MASK 0x716 361 362 #define AUDIOHDC_VERB_GET_UNSOL_ENABLE_MASK 0xf19 363 #define AUDIOHDC_VERB_SET_UNSOL_ENABLE_MASK 0x719 364 365 #define AUDIOHDC_VERB_GET_GPIO_DIREC 0xf17 366 #define AUDIOHDC_VERB_SET_GPIO_DIREC 0x717 367 368 #define AUDIOHDC_VERB_GET_GPIO_DATA 0xf15 369 #define AUDIOHDC_VERB_SET_GPIO_DATA 0x715 370 371 #define AUDIOHDC_VERB_GET_GPIO_STCK 0xf1a 372 #define AUDIOHDC_VERB_SET_GPIO_STCK 0x71a 373 374 #define AUDIOHDC_GPIO_ENABLE 0xff 375 #define AUDIOHDC_GPIO_DIRECT 0xf1 376 377 #define AUDIOHDC_GPIO_DATA_CTRL 0xff 378 #define AUDIOHDC_GPIO_STCK_CTRL 0xff 379 /* 380 * 4-bit verbs 381 */ 382 #define AUDIOHDC_VERB_GET_CONV_FMT 0xa 383 #define AUDIOHDC_VERB_SET_CONV_FMT 0x2 384 385 #define AUDIOHDC_VERB_GET_AMP_MUTE 0xb 386 #define AUDIOHDC_VERB_SET_AMP_MUTE 0x3 387 #define AUDIOHDC_VERB_SET_BEEP_VOL 0x3A0 388 389 /* 390 * parameters of nodes 391 */ 392 #define AUDIOHDC_PAR_VENDOR_ID 0x00 393 #define AUDIOHDC_PAR_SUBSYS_ID 0x01 394 #define AUDIOHDC_PAR_REV_ID 0x02 395 #define AUDIOHDC_PAR_NODE_COUNT 0x04 396 #define AUDIOHDC_PAR_FUNCTION_TYPE 0x05 397 #define AUDIOHDC_PAR_AUDIO_FG_CAP 0x08 398 #define AUDIOHDC_PAR_AUDIO_WID_CAP 0x09 399 #define AUDIOHDC_PAR_PCM 0x0a 400 #define AUDIOHDC_PAR_STREAM 0x0b 401 #define AUDIOHDC_PAR_PIN_CAP 0x0c 402 #define AUDIOHDC_PAR_INAMP_CAP 0x0d 403 #define AUDIOHDC_PAR_CONNLIST_LEN 0x0e 404 #define AUDIOHDC_PAR_POWER_STATE 0x0f 405 #define AUDIOHDC_PAR_PROC_CAP 0x10 406 #define AUDIOHDC_PAR_GPIO_CAP 0x11 407 #define AUDIOHDC_PAR_OUTAMP_CAP 0x12 408 409 /* 410 * bits for get/set amplifier gain/mute 411 */ 412 #define AUDIOHDC_AMP_SET_OUTPUT 0x8000 413 #define AUDIOHDC_AMP_SET_INPUT 0x4000 414 #define AUDIOHDC_AMP_SET_LEFT 0x2000 415 #define AUDIOHDC_AMP_SET_RIGHT 0x1000 416 #define AUDIOHDC_AMP_SET_MUTE 0x0080 417 #define AUDIOHDC_AMP_SET_LNR 0x3000 418 #define AUDIOHDC_AMP_SET_LR_INPUT 0x7000 419 #define AUDIOHDC_AMP_SET_LR_OUTPUT 0xb000 420 #define AUDIOHDC_AMP_SET_INDEX_OFFSET 8 421 #define AUDIOHDC_AMP_SET_GAIN_MASK 0x007f 422 #define AUDIOHDC_GAIN_MAX 0x7f 423 #define AUDIOHDC_GAIN_BITS 7 424 #define AUDIOHDC_GAIN_DEFAULT 0x0f 425 426 #define AUDIOHDC_AMP_GET_OUTPUT 0x8000 427 #define AUDIOHDC_AMP_GET_INPUT 0x0000 428 429 /* value used to set max volume for left output */ 430 #define AUDIOHDC_AMP_LOUT_MAX \ 431 (AUDIOHDC_AMP_SET_OUTPUT | \ 432 AUDIOHDC_AMP_SET_LEFT | \ 433 AUDIOHDC_GAIN_MAX) 434 435 /* value used to set max volume for right output */ 436 #define AUDIOHDC_AMP_ROUT_MAX \ 437 (AUDIOHDC_AMP_SET_OUTPUT | \ 438 AUDIOHDC_AMP_SET_RIGHT | \ 439 AUDIOHDC_GAIN_MAX) 440 441 442 /* 443 * Bits for pin widget control verb 444 */ 445 #define AUDIOHDC_PIN_CONTROL_HP_ENABLE 0x80 446 #define AUDIOHDC_PIN_CONTROL_OUT_ENABLE 0x40 447 #define AUDIOHDC_PIN_CONTROL_IN_ENABLE 0x20 448 449 /* 450 * Bits for Amplifier capabilities 451 */ 452 #define AUDIOHDC_AMP_CAP_MUTE_CAP 0x80000000 453 #define AUDIOHDC_AMP_CAP_STEP_SIZE 0x007f0000 454 #define AUDIOHDC_AMP_CAP_STEP_NUMS 0x00007f00 455 #define AUDIOHDC_AMP_CAP_0DB_OFFSET 0x0000007f 456 457 458 /* 459 * Bits for Audio Widget Capabilities 460 */ 461 #define AUDIOHD_WIDCAP_STEREO 0x00000001 462 #define AUDIOHD_WIDCAP_INAMP 0x00000002 463 #define AUDIOHD_WIDCAP_OUTAMP 0x00000004 464 #define AUDIOHD_WIDCAP_AMP_OVRIDE 0x00000008 465 #define AUDIOHD_WIDCAP_FMT_OVRIDE 0x00000010 466 #define AUDIOHD_WIDCAP_STRIP 0x00000020 467 #define AUDIOHD_WIDCAP_PROC_WID 0x00000040 468 #define AUDIOHD_WIDCAP_UNSOL 0x00000080 469 #define AUDIOHD_WIDCAP_CONNLIST 0x00000100 470 #define AUDIOHD_WIDCAP_DIGIT 0x00000200 471 #define AUDIOHD_WIDCAP_PWRCTRL 0x00000400 472 #define AUDIOHD_WIDCAP_LRSWAP 0x00000800 473 #define AUDIOHD_WIDCAP_TYPE 0x00f00000 474 #define AUDIOHD_WIDCAP_TO_WIDTYPE(wcap) \ 475 ((wcap & AUDIOHD_WIDCAP_TYPE) >> 20) 476 477 #define AUDIOHD_CODEC_FAILURE (uint32_t)(-1) 478 479 /* 480 * buffer descriptor list entry of stream descriptor 481 */ 482 typedef struct { 483 uint64_t sbde_addr; 484 uint32_t sbde_len; 485 uint32_t 486 sbde_ioc: 1, 487 reserved: 31; 488 }sd_bdle_t; 489 490 491 #define AUDIOHD_PLAY_STARTED 0x00000001 492 #define AUDIOHD_PLAY_EMPTY 0x00000002 493 #define AUDIOHD_PLAY_PAUSED 0x00000004 494 #define AUDIOHD_RECORD_STARTED 0x00000008 495 496 enum audiohda_widget_type { 497 WTYPE_AUDIO_OUT = 0, 498 WTYPE_AUDIO_IN, 499 WTYPE_AUDIO_MIX, 500 WTYPE_AUDIO_SEL, 501 WTYPE_PIN, 502 WTYPE_POWER, 503 WTYPE_VOL_KNOB, 504 WTYPE_BEEP, 505 WTYPE_VENDOR = 0xf 506 }; 507 508 enum audiohda_device_type { 509 DTYPE_LINEOUT = 0, 510 DTYPE_SPEAKER, 511 DTYPE_HP_OUT, 512 DTYPE_CD, 513 DTYPE_SPDIF_OUT, 514 DTYPE_DIGIT_OUT, 515 DTYPE_MODEM_SIDE, 516 DTYPE_MODEM_HNAD_SIDE, 517 DTYPE_LINE_IN, 518 DTYPE_AUX, 519 DTYPE_MIC_IN, 520 DTYPE_TEL, 521 DTYPE_SPDIF_IN, 522 DTYPE_DIGIT_IN, 523 DTYPE_OTHER = 0x0f, 524 }; 525 526 enum audiohd_pin_color { 527 AUDIOHD_PIN_UNKNOWN = 0, 528 AUDIOHD_PIN_BLACK, 529 AUDIOHD_PIN_GREY, 530 AUDIOHD_PIN_BLUE, 531 AUDIOHD_PIN_GREEN, 532 AUDIOHD_PIN_RED, 533 AUDIOHD_PIN_ORANGE, 534 AUDIOHD_PIN_YELLOW, 535 AUDIOHD_PIN_PURPLE, 536 AUDIOHD_PIN_PINK, 537 AUDIOHD_PIN_WHITE = 0xe, 538 AUDIOHD_PIN_OTHER = 0xf, 539 }; 540 541 /* values for audiohd_widget.path_flags */ 542 #define AUDIOHD_PATH_DAC (1 << 0) 543 #define AUDIOHD_PATH_ADC (1 << 1) 544 #define AUDIOHD_PATH_MON (1 << 2) 545 #define AUDIOHD_PATH_NOMON (1 << 3) 546 #define AUDIOHD_PATH_BEEP (1 << 4) 547 548 typedef struct audiohd_path audiohd_path_t; 549 typedef struct audiohd_widget audiohd_widget_t; 550 typedef struct audiohd_state audiohd_state_t; 551 typedef struct audiohd_codec_info audiohd_codec_info_t; 552 typedef struct audiohd_pin audiohd_pin_t; 553 typedef struct hda_codec hda_codec_t; 554 typedef uint32_t wid_t; /* id of widget */ 555 typedef struct audiohd_entry_prop audiohd_entry_prop_t; 556 typedef enum audiohda_device_type audiohda_device_type_t; 557 typedef enum audiohd_pin_color audiohd_pin_color_t; 558 559 #define AUDIOHD_MAX_WIDGET 128 560 #define AUDIOHD_MAX_CONN 16 561 #define AUDIOHD_MAX_PINS 16 562 #define AUDIOHD_MAX_DEPTH 8 563 564 struct audiohd_entry_prop { 565 uint32_t conn_len; 566 uint32_t mask_range; 567 uint32_t mask_wid; 568 wid_t input_wid; 569 int conns_per_entry; 570 int bits_per_conn; 571 }; 572 struct audiohd_widget { 573 wid_t wid_wid; 574 hda_codec_t *codec; 575 enum audiohda_widget_type type; 576 577 uint32_t widget_cap; 578 uint32_t pcm_format; 579 uint32_t inamp_cap; 580 uint32_t outamp_cap; 581 582 uint32_t path_flags; 583 584 int out_weight; 585 int in_weight; 586 int finish; 587 588 /* 589 * available (input) connections. 0 means this widget 590 * has fixed connection 591 */ 592 int nconns; 593 594 /* 595 * wid of possible & selected input & output connections 596 */ 597 wid_t avail_conn[AUDIOHD_MAX_CONN]; 598 wid_t output_path_next; /* output pin -> DAC */ 599 wid_t input_path_next; /* ADC -> input pin */ 600 wid_t monitor_path_next[AUDIOHD_MAX_CONN]; 601 /* output pin -> input pin */ 602 wid_t beep_path_next; /* output pin -> beep widget */ 603 604 uint16_t used; 605 606 /* 607 * pointer to struct depending on widget type: 608 * 1. DAC audiohd_ostream_t 609 * 2. ADC audiohd_istream_t 610 * 3. PIN audiohd_pin_t 611 */ 612 void *priv; 613 }; 614 615 #define AUDIOHD_FLAG_LINEOUT (1 << 0) 616 #define AUDIOHD_FLAG_SPEAKER (1 << 1) 617 #define AUDIOHD_FLAG_HP (1 << 2) 618 #define AUDIOHD_FLAG_MONO (1 << 3) 619 620 #define AUDIOHD_MAX_MIXER 5 621 #define AUDIOHD_MAX_PIN 4 622 623 #define PORT_DAC 0 624 #define PORT_ADC 1 625 #define PORT_MAX 2 626 typedef enum { 627 PLAY = 0, 628 RECORD = 1, 629 BEEP = 2, 630 } path_type_t; 631 632 struct audiohd_path { 633 wid_t adda_wid; 634 wid_t beep_wid; 635 636 wid_t pin_wid[AUDIOHD_MAX_PINS]; 637 int sum_selconn[AUDIOHD_MAX_PINS]; 638 int mon_wid[AUDIOHD_MAX_PIN][AUDIOHD_MAX_MIXER]; 639 int pin_nums; 640 int maxmixer[AUDIOHD_MAX_PINS]; 641 642 path_type_t path_type; 643 644 wid_t mute_wid; 645 int mute_dir; 646 wid_t gain_wid; 647 int gain_dir; 648 uint32_t gain_bits; 649 650 uint32_t pin_outputs; 651 uint8_t tag; 652 653 hda_codec_t *codec; 654 655 wid_t sum_wid; 656 657 audiohd_state_t *statep; 658 }; 659 660 typedef struct audiohd_port 661 { 662 uint8_t nchan; 663 int index; 664 uint16_t regoff; 665 666 unsigned nframes; 667 size_t bufsize; 668 size_t fragsize; 669 uint64_t count; 670 int curpos; 671 672 uint_t format; 673 unsigned sync_dir; 674 675 ddi_dma_handle_t samp_dmah; 676 ddi_acc_handle_t samp_acch; 677 caddr_t samp_kaddr; 678 uint64_t samp_paddr; 679 680 ddi_dma_handle_t bdl_dmah; 681 ddi_acc_handle_t bdl_acch; 682 size_t bdl_size; 683 caddr_t bdl_kaddr; 684 uint64_t bdl_paddr; 685 686 audio_engine_t *engine; 687 audiohd_state_t *statep; 688 }audiohd_port_t; 689 690 enum { 691 CTL_VOLUME = 0, 692 CTL_FRONT, 693 CTL_SPEAKER, 694 CTL_HEADPHONE, 695 CTL_REAR, 696 CTL_CENTER, 697 CTL_SURROUND, 698 CTL_LFE, 699 CTL_IGAIN, 700 CTL_LINEIN, 701 CTL_MIC, 702 CTL_CD, 703 CTL_MONGAIN, 704 CTL_MONSRC, 705 CTL_RECSRC, 706 CTL_BEEP, 707 708 /* this one must be last */ 709 CTL_MAX 710 }; 711 712 typedef struct audiohd_ctrl 713 { 714 audiohd_state_t *statep; 715 audio_ctrl_t *ctrl; 716 int num; 717 uint64_t val; 718 } audiohd_ctrl_t; 719 720 struct audiohd_pin { 721 audiohd_pin_t *next; 722 wid_t wid; 723 wid_t mute_wid; /* node used to mute this pin */ 724 int mute_dir; /* 1: input, 2: output */ 725 wid_t gain_wid; /* node for gain control */ 726 int gain_dir; /* _OUTPUT/_INPUT */ 727 uint32_t gain_bits; 728 729 uint8_t vrefvalue; /* value of VRef */ 730 731 uint32_t cap; 732 uint32_t config; 733 uint32_t ctrl; 734 uint32_t assoc; 735 uint32_t seq; 736 wid_t adc_dac_wid; /* AD/DA wid which can route to this pin */ 737 wid_t beep_wid; 738 int no_phys_conn; 739 enum audiohda_device_type device; 740 741 /* 742 * mg_dir, mg_gain, mg_wid are used to store the monitor gain control 743 * widget wid. 744 */ 745 int mg_dir[AUDIOHD_MAX_CONN]; 746 int mg_gain[AUDIOHD_MAX_CONN]; 747 int mg_wid[AUDIOHD_MAX_CONN]; 748 int num; 749 int finish; 750 751 }; 752 753 typedef struct { 754 ddi_dma_handle_t ad_dmahdl; 755 ddi_acc_handle_t ad_acchdl; 756 caddr_t ad_vaddr; /* virtual addr */ 757 uint64_t ad_paddr; /* physical addr */ 758 size_t ad_req_sz; /* required size of memory */ 759 size_t ad_real_sz; /* real size of memory */ 760 } audiohd_dma_t; 761 762 struct hda_codec { 763 uint8_t index; /* codec address */ 764 uint32_t vid; /* vendor id and device id */ 765 uint32_t revid; /* revision id */ 766 wid_t wid_afg; /* id of AFG */ 767 wid_t first_wid; /* wid of 1st subnode of AFG */ 768 wid_t last_wid; /* wid of the last subnode of AFG */ 769 int nnodes; /* # of subnodes of AFG */ 770 uint8_t nistream; 771 772 uint32_t outamp_cap; 773 uint32_t inamp_cap; 774 uint32_t stream_format; 775 uint32_t pcm_format; 776 777 audiohd_state_t *soft_statep; 778 audiohd_codec_info_t *codec_info; 779 780 /* use wid as index to the array of widget pointers */ 781 audiohd_widget_t *widget[AUDIOHD_MAX_WIDGET]; 782 783 audiohd_port_t *port[AUDIOHD_PORT_MAX]; 784 uint8_t portnum; 785 audiohd_pin_t *first_pin; 786 }; 787 788 #define AUDIOHD_MAX_ASSOC 15 789 struct audiohd_state { 790 dev_info_t *hda_dip; 791 kstat_t *hda_ksp; 792 kmutex_t hda_mutex; 793 uint32_t hda_flags; 794 795 caddr_t hda_reg_base; 796 ddi_acc_handle_t hda_pci_handle; 797 ddi_acc_handle_t hda_reg_handle; 798 799 audiohd_dma_t hda_dma_corb; 800 audiohd_dma_t hda_dma_rirb; 801 802 uint8_t hda_rirb_rp; /* read pointer for rirb */ 803 uint16_t hda_codec_mask; 804 805 audio_dev_t *adev; 806 uint32_t devid; 807 808 int hda_input_streams; /* # of input stream */ 809 int hda_output_streams; /* # of output stream */ 810 int hda_streams_nums; /* # of stream */ 811 812 uint_t hda_play_regbase; 813 uint_t hda_record_regbase; 814 815 uint_t hda_play_stag; /* tag of playback stream */ 816 uint_t hda_record_stag; /* tag of record stream */ 817 uint_t hda_play_lgain; /* left gain for playback */ 818 uint_t hda_play_rgain; /* right gain for playback */ 819 820 /* 821 * Now, for the time being, we add some fields 822 * for parsing codec topology 823 */ 824 hda_codec_t *codec[AUDIOHD_CODEC_MAX]; 825 826 /* 827 * Suspend/Resume used fields 828 */ 829 boolean_t suspended; 830 831 audiohd_path_t *path[AUDIOHD_PORT_MAX]; 832 uint8_t pathnum; 833 audiohd_port_t *port[PORT_MAX]; 834 uint8_t pchan; 835 uint8_t rchan; 836 837 uint64_t inmask; 838 839 uint_t hda_out_ports; 840 uint_t in_port; 841 842 /* 843 * Controls 844 */ 845 audiohd_ctrl_t ctrls[CTL_MAX]; 846 boolean_t monitor_unsupported; 847 848 /* for multichannel */ 849 uint8_t chann[AUDIOHD_MAX_ASSOC]; 850 uint8_t assoc; 851 852 }; 853 854 struct audiohd_codec_info { 855 uint32_t devid; 856 const char *buf; 857 uint32_t flags; 858 }; 859 860 /* 861 * Operation for high definition audio control system bus 862 * interface registers 863 */ 864 #define AUDIOHD_REG_GET8(reg) \ 865 ddi_get8(statep->hda_reg_handle, \ 866 (void *)((char *)statep->hda_reg_base + (reg))) 867 868 #define AUDIOHD_REG_GET16(reg) \ 869 ddi_get16(statep->hda_reg_handle, \ 870 (void *)((char *)statep->hda_reg_base + (reg))) 871 872 #define AUDIOHD_REG_GET32(reg) \ 873 ddi_get32(statep->hda_reg_handle, \ 874 (void *)((char *)statep->hda_reg_base + (reg))) 875 876 #define AUDIOHD_REG_GET64(reg) \ 877 ddi_get64(statep->hda_reg_handle, \ 878 (void *)((char *)statep->hda_reg_base + (reg))) 879 880 #define AUDIOHD_REG_SET8(reg, val) \ 881 ddi_put8(statep->hda_reg_handle, \ 882 (void *)((char *)statep->hda_reg_base + (reg)), (val)) 883 884 #define AUDIOHD_REG_SET16(reg, val) \ 885 ddi_put16(statep->hda_reg_handle, \ 886 (void *)((char *)statep->hda_reg_base + (reg)), (val)) 887 888 #define AUDIOHD_REG_SET32(reg, val) \ 889 ddi_put32(statep->hda_reg_handle, \ 890 (void *)((char *)statep->hda_reg_base + (reg)), (val)) 891 892 #define AUDIOHD_REG_SET64(reg, val) \ 893 ddi_put64(statep->hda_reg_handle, \ 894 (void *)((char *)statep->hda_reg_base + (reg)), (val)) 895 896 897 /* 898 * enable a pin widget to input 899 */ 900 #define AUDIOHD_ENABLE_PIN_IN(statep, caddr, wid) \ 901 { \ 902 (void) audioha_codec_verb_get(statep, caddr, wid, \ 903 AUDIOHDC_VERB_SET_PIN_CTRL, AUDIOHDC_PIN_CONTROL_IN_ENABLE | 4); \ 904 } 905 906 907 /* 908 * disable input pin 909 */ 910 #define AUDIOHD_DISABLE_PIN_IN(statep, caddr, wid) \ 911 { \ 912 uint32_t lTmp; \ 913 \ 914 lTmp = audioha_codec_verb_get(statep, caddr, wid, \ 915 AUDIOHDC_VERB_GET_PIN_CTRL, 0); \ 916 if (lTmp == AUDIOHD_CODEC_FAILURE) \ 917 return (DDI_FAILURE); \ 918 lTmp = audioha_codec_verb_get(statep, caddr, wid, \ 919 AUDIOHDC_VERB_SET_PIN_CTRL, \ 920 (lTmp & ~AUDIOHDC_PIN_CONTROL_IN_ENABLE)); \ 921 if (lTmp == AUDIOHD_CODEC_FAILURE) \ 922 return (DDI_FAILURE); \ 923 } 924 925 /* 926 * unmute an output pin 927 */ 928 #define AUDIOHD_NODE_UNMUTE_OUT(statep, caddr, wid) \ 929 { \ 930 if (audioha_codec_4bit_verb_get(statep, \ 931 caddr, wid, AUDIOHDC_VERB_SET_AMP_MUTE, \ 932 AUDIOHDC_AMP_SET_LR_OUTPUT | AUDIOHDC_GAIN_MAX) == \ 933 AUDIOHD_CODEC_FAILURE) \ 934 return (DDI_FAILURE); \ 935 } 936 937 /* 938 * check volume adjust value of 2 channels control 939 */ 940 #define AUDIOHD_CHECK_2CHANNELS_VOLUME(value) \ 941 { \ 942 if ((value) & ~0xffff) \ 943 return (EINVAL); \ 944 if ((((value) & 0xff00) >> 8) > 100 || \ 945 ((value) & 0xff) > 100) \ 946 return (EINVAL); \ 947 } 948 949 /* 950 * check volume adjust value of mono channel control 951 */ 952 #define AUDIOHD_CHECK_CHANNEL_VOLUME(value) \ 953 { \ 954 if ((value) & ~0xff) \ 955 return (EINVAL); \ 956 if (((value) & 0xff) > 100) \ 957 return (EINVAL); \ 958 } 959 960 #ifdef __cplusplus 961 } 962 #endif 963 964 #endif /* _SYS_AUDIOHD_IMPL_H_ */ 965