1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License (the "License"). 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9 * or http://www.opensolaris.org/os/licensing. 10 * See the License for the specific language governing permissions 11 * and limitations under the License. 12 * 13 * When distributing Covered Code, include this CDDL HEADER in each 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15 * If applicable, add the following below this CDDL HEADER, with the 16 * fields enclosed by brackets "[]" replaced with your own identifying 17 * information: Portions Copyright [yyyy] [name of copyright owner] 18 * 19 * CDDL HEADER END 20 */ 21 /* 22 * Copyright 2009 Sun Microsystems, Inc. All rights reserved. 23 * Use is subject to license terms. 24 */ 25 #ifndef _SYS_AUDIOHD_IMPL_H_ 26 #define _SYS_AUDIOHD_IMPL_H_ 27 28 #ifdef __cplusplus 29 extern "C" { 30 #endif 31 32 /* 33 * vendor IDs of PCI audio controllers 34 */ 35 #define AUDIOHD_VID_INTEL 0x8086 36 #define AUDIOHD_VID_ATI 0x1002 37 #define AUDIOHD_VID_NVIDIA 0x10de 38 39 /* 40 * specific codec id used by specific vendors 41 */ 42 #define AUDIOHD_CODECID_HP 0x111d7608 43 #define AUDIOHD_CODECID_ALC888 0x10ec0888 44 #define AUDIOHD_CODECID_SONY1 0x10ec0260 45 #define AUDIOHD_CODECID_SONY2 0x10ec0262 46 47 #define AUDIO_SUCCESS (0) 48 #define AUDIO_FAILURE (-1) 49 50 #define AUDIOHD_INTS 50 51 #define AUDIOHD_MAX_INTS 1500 52 #define AUDIOHD_MIN_INTS 32 53 54 #define AUDIOHD_DEV_CONFIG "onboard1" 55 #define AUDIOHD_DEV_VERSION "a" 56 57 #define AUDIOHD_FMT_PCM 0x001 58 /* 59 * Only for Intel hardware: 60 * PCI Express traffic class select register in PCI configure space 61 */ 62 #define AUDIOHD_INTEL_PCI_TCSEL 0x44 63 64 /* 65 * Only for ATI SB450: 66 * MISC control register 2 67 */ 68 #define AUDIOHD_ATI_PCI_MISC2 0x42 69 #define AUDIOHD_ATI_MISC2_SNOOP 0x02 70 #define AUDIOHDC_NID(x) x 71 #define AUDIOHDC_NULL_NODE -1 72 #define AUDIOHD_NULL_CONN ((uint_t)(-1)) 73 /* 74 * currently, only the format of 48K sample rate, 16-bit 75 * 2-channel is supported. 76 */ 77 #define AUDIOHD_FMT_PCMOUT 0x0011 78 #define AUDIOHD_FMT_PCMIN 0x0011 79 80 #define AUDIOHD_EXT_AMP_MASK 0x00010000 81 #define AUDIOHD_EXT_AMP_ENABLE 0x02 82 /* NVIDIA snoop */ 83 #define AUDIOHD_NVIDIA_SNOOP 0x0f 84 85 /* Power On/Off */ 86 #define AUDIOHD_PW_OFF 1 87 #define AUDIOHD_PW_ON 0 88 #define AUDIOHD_PW_D0 0 89 #define AUDIOHD_PW_D2 2 90 91 #define AUDIOHD_INTEL_TCS_MASK 0xf8 92 #define AUDIOHD_ATI_MISC2_MASK 0xf8 93 94 /* Pin speaker On/Off */ 95 #define AUDIOHD_SP_ON 1 96 #define AUDIOHD_SP_OFF 0 97 98 #define AUDIOHD_PORT_MAX 15 99 #define AUDIOHD_CODEC_MAX 16 100 #define AUDIOHD_MEMIO_LEN 0x4000 101 102 #define AUDIOHD_RETRY_TIMES 60 103 #define AUDIOHD_TEST_TIMES 500 104 #define AUDIOHD_OUTSTR_NUM_OFF 12 105 #define AUDIOHD_INSTR_NUM_OFF 8 106 107 #define AUDIOHD_CORB_SIZE_OFF 0x4e 108 109 #define AUDIOHD_URCAP_MASK 0x80 110 #define AUDIOHD_DTCCAP_MASK 0x4 111 #define AUDIOHD_UR_ENABLE_OFF 8 112 #define AUDIOHD_UR_TAG_MASK 0x1f 113 114 #define AUDIOHD_CIS_MASK 0x40000000 115 116 #define AUDIOHD_RIRB_UR_MASK 0x10 117 #define AUDIOHD_RIRB_CODEC_MASK 0xf 118 #define AUDIOHD_RIRB_WID_OFF 27 119 #define AUDIOHD_RIRB_INTRCNT 0x0 120 #define AUDIOHD_RIRB_WPMASK 0xff 121 122 #define AUDIOHD_FORM_MASK 0x0080 123 #define AUDIOHD_LEN_MASK 0x007f 124 #define AUDIOHD_PIN_CAP_MASK 0x00000010 125 #define AUDIOHD_PIN_CONF_MASK 0xc0000000 126 #define AUDIOHD_PIN_CON_MASK 3 127 #define AUDIOHD_PIN_CON_STEP 30 128 #define AUDIOHD_PIN_IO_MASK 0X0018 129 #define AUDIOHD_PIN_SEQ_MASK 0x0000000f 130 #define AUDIOHD_PIN_ASO_MASK 0x000000f0 131 #define AUDIOHD_PIN_ASO_OFF 0x4 132 #define AUDIOHD_PIN_DEV_MASK 0x00f00000 133 #define AUDIOHD_PIN_DEV_OFF 20 134 #define AUDIOHD_PIN_NUMS 6 135 #define AUDIOHD_PIN_NO_CONN 0x40000000 136 #define AUDIOHD_PIN_IN_ENABLE 0x20 137 #define AUDIOHD_PIN_OUT_ENABLE 0x40 138 #define AUDIOHD_PIN_PRES_OFF 0x20 139 #define AUDIOHD_PIN_CONTP_OFF 0x1e 140 #define AUDIOHD_PIN_CON_JACK 0 141 #define AUDIOHD_PIN_CON_FIXED 0x2 142 #define AUDIOHD_PIN_CONTP_MASK 0x3 143 #define AUDIOHD_PIN_VREF_L1 0x20 144 #define AUDIOHD_PIN_VREF_L2 0x10 145 #define AUDIOHD_PIN_VREF_L3 0x04 146 #define AUDIOHD_PIN_VREF_L4 0x02 147 #define AUDIOHD_PIN_VREF_OFF 8 148 #define AUDIOHD_PIN_VREF_MASK 0xff 149 #define AUDIOHD_PIN_CLR_MASK 0xf 150 #define AUDIOHD_PIN_CLR_OFF 12 151 152 153 #define AUDIOHD_VERB_ADDR_OFF 28 154 #define AUDIOHD_VERB_NID_OFF 20 155 #define AUDIOHD_VERB_CMD_OFF 8 156 #define AUDIOHD_VERB_CMD16_OFF 16 157 158 #define AUDIOHD_RING_MAX_SIZE 0x00ff 159 #define AUDIOHD_POS_MASK ~0x00000003 160 #define AUDIOHD_REC_TAG_OFF 4 161 #define AUDIOHD_PLAY_TAG_OFF 4 162 #define AUDIOHD_PLAY_CTL_OFF 2 163 #define AUDIOHD_REC_CTL_OFF 2 164 165 #define AUDIOHD_SPDIF_ON 1 166 #define AUDIOHD_SPDIF_MASK 0x00ff 167 168 #define AUDIOHD_GAIN_OFF 8 169 170 #define AUDIOHD_CODEC_STR_OFF 16 171 #define AUDIOHD_CODEC_STR_MASK 0x000000ff 172 #define AUDIOHD_CODEC_NUM_MASK 0x000000ff 173 #define AUDIOHD_CODEC_TYPE_MASK 0x000000ff 174 175 #define AUDIOHD_FRAGFR_ALIGN 16 176 #define AUDIOHD_BDLE_BUF_ALIGN 128 177 #define AUDIOHD_CMDIO_ENT_MASK 0x00ff /* 256 entries for CORB/RIRB */ 178 #define AUDIOHD_CDBIO_CORB_LEN 1024 /* 256 entries for CORB, 1024B */ 179 #define AUDIOHD_CDBIO_RIRB_LEN 2048 /* 256 entries for RIRB, 2048B */ 180 #define AUDIOHD_BDLE_NUMS 4 /* 4 entires for record/play BD list */ 181 182 #define AUDIOHD_PORT_UNMUTE (0xffffffff) 183 184 /* 185 * Audio registers of high definition 186 */ 187 #define AUDIOHD_REG_GCAP 0x00 188 #define AUDIOHDR_GCAP_OUTSTREAMS 0xf000 189 #define AUDIOHDR_GCAP_INSTREAMS 0x0f00 190 #define AUDIOHDR_GCAP_BSTREAMS 0x00f8 191 #define AUDIOHDR_GCAP_NSDO 0x0006 192 #define AUDIOHDR_GCAP_64OK 0x0001 193 194 #define AUDIOHD_REG_VMIN 0x02 195 #define AUDIOHD_REG_VMAJ 0x03 196 #define AUDIOHD_REG_OUTPAY 0x04 197 #define AUDIOHD_REG_INPAY 0x06 198 #define AUDIOHD_REG_GCTL 0x08 199 #define AUDIOHD_REG_WAKEEN 0x0C 200 #define AUDIOHD_REG_STATESTS 0x0E 201 #define AUDIOHD_STATESTS_BIT_SDINS 0x7F 202 203 #define AUDIOHD_REG_GSTS 0x10 204 #define AUDIOHD_REG_INTCTL 0x20 205 #define AUDIOHD_INTCTL_BIT_GIE 0x80000000 206 #define AUDIOHD_INTCTL_BIT_CIE 0x40000000 207 #define AUDIOHD_INTCTL_BIT_SIE 0x3FFFFFFF 208 209 210 #define AUDIOHD_REG_INTSTS 0x24 211 #define AUDIOHD_INTSTS_BIT_GIS 0x80000000 212 #define AUDIOHD_INTSTS_BIT_CIS 0x40000000 213 #define AUDIOHD_INTSTS_BIT_SINTS (0x3fffffff) 214 215 #define AUDIOHD_REG_WALCLK 0x30 216 #define AUDIOHD_REG_SYNC 0x38 217 218 #define AUDIOHD_REG_CORBLBASE 0x40 219 #define AUDIOHD_REG_CORBUBASE 0x44 220 #define AUDIOHD_REG_CORBWP 0x48 221 #define AUDIOHD_REG_CORBRP 0x4A 222 #define AUDIOHD_REG_CORBCTL 0x4C 223 #define AUDIOHD_REG_CORBST 0x4D 224 #define AUDIOHD_REG_CORBSIZE 0x4E 225 226 #define AUDIOHD_REG_RIRBLBASE 0x50 227 #define AUDIOHD_REG_RIRBUBASE 0x54 228 #define AUDIOHD_REG_RIRBWP 0x58 229 #define AUDIOHD_REG_RINTCNT 0x5A 230 #define AUDIOHD_REG_RIRBCTL 0x5C 231 #define AUDIOHD_REG_RIRBSTS 0x5D 232 #define AUDIOHD_REG_RIRBSIZE 0x5E 233 234 #define AUDIOHD_REG_IC 0x60 235 #define AUDIOHD_REG_IR 0x64 236 #define AUDIOHD_REG_IRS 0x68 237 #define AUDIOHD_REG_DPLBASE 0x70 238 #define AUDIOHD_REG_DPUBASE 0x74 239 240 #define AUDIOHD_REG_SD_BASE 0x80 241 #define AUDIOHD_REG_SD_LEN 0x20 242 243 /* 244 * Offset of Stream Descriptor Registers 245 */ 246 #define AUDIOHD_SDREG_OFFSET_CTL 0x00 247 #define AUDIOHD_SDREG_OFFSET_STS 0x03 248 #define AUDIOHD_SDREG_OFFSET_LPIB 0x04 249 #define AUDIOHD_SDREG_OFFSET_CBL 0x08 250 #define AUDIOHD_SDREG_OFFSET_LVI 0x0c 251 #define AUDIOHD_SDREG_OFFSET_FIFOW 0x0e 252 #define AUDIOHD_SDREG_OFFSET_FIFOSIZE 0x10 253 #define AUDIOHD_SDREG_OFFSET_FORMAT 0x12 254 #define AUDIOHD_SDREG_OFFSET_BDLPL 0x18 255 #define AUDIOHD_SDREG_OFFSET_BDLPU 0x1c 256 257 /* bits for stream descriptor control reg */ 258 #define AUDIOHDR_SD_CTL_DEIE 0x000010 259 #define AUDIOHDR_SD_CTL_FEIE 0x000008 260 #define AUDIOHDR_SD_CTL_IOCE 0x000004 261 #define AUDIOHDR_SD_CTL_SRUN 0x000002 262 #define AUDIOHDR_SD_CTL_SRST 0x000001 263 #define AUDIOHDR_SD_CTL_INTS \ 264 (AUDIOHDR_SD_CTL_DEIE | \ 265 AUDIOHDR_SD_CTL_FEIE | \ 266 AUDIOHDR_SD_CTL_IOCE) 267 268 269 /* bits for stream descriptor status register */ 270 #define AUDIOHDR_SD_STS_BCIS 0x0004 271 #define AUDIOHDR_SD_STS_FIFOE 0x0008 272 #define AUDIOHDR_SD_STS_DESE 0x0010 273 #define AUDIOHDR_SD_STS_FIFORY 0x0020 274 #define AUDIOHDR_SD_STS_INTRS \ 275 (AUDIOHDR_SD_STS_BCIS | \ 276 AUDIOHDR_SD_STS_FIFOE | \ 277 AUDIOHDR_SD_STS_DESE) 278 279 280 /* bits for GCTL register */ 281 #define AUDIOHDR_GCTL_CRST 0x00000001 282 #define AUDIOHDR_GCTL_URESPE 0x00000100 283 284 /* bits for CORBRP register */ 285 #define AUDIOHDR_CORBRP_RESET 0x8000 286 #define AUDIOHDR_CORBRP_WPTR 0x00ff 287 288 /* bits for CORBCTL register */ 289 #define AUDIOHDR_CORBCTL_CMEIE 0x01 290 #define AUDIOHDR_CORBCTL_DMARUN 0x02 291 292 /* bits for CORB SIZE register */ 293 #define AUDIOHDR_CORBSZ_8 0 294 #define AUDIOHDR_CORBSZ_16 1 295 #define AUDIOHDR_CORBSZ_256 2 296 297 /* bits for RIRBCTL register */ 298 #define AUDIOHDR_RIRBCTL_RINTCTL 0x01 299 #define AUDIOHDR_RIRBCTL_DMARUN 0x02 300 #define AUDIOHDR_RIRBCTL_RIRBOIC 0x04 301 #define AUDIOHDR_RIRBCTL_RSTINT 0xfe 302 303 /* bits for RIRBWP register */ 304 #define AUDIOHDR_RIRBWP_RESET 0x8000 305 #define AUDIOHDR_RIRBWP_WPTR 0x00ff 306 307 /* bits for RIRB SIZE register */ 308 #define AUDIOHDR_RIRBSZ_8 0 309 #define AUDIOHDR_RIRBSZ_16 1 310 #define AUDIOHDR_RIRBSZ_256 2 311 312 #define AUDIOHD_BDLE_RIRB_SDI 0x0000000f 313 #define AUDIOHD_BDLE_RIRB_UNSOLICIT 0x00000010 314 315 /* HD spec: ID of Root node is 0 */ 316 #define AUDIOHDC_NODE_ROOT 0x00 317 318 /* HD spec: ID of audio function group is "1" */ 319 #define AUDIOHDC_AUDIO_FUNC_GROUP 1 320 321 /* 322 * HD audio verbs can be either 12-bit or 4-bit in length. 323 */ 324 #define AUDIOHDC_12BIT_VERB_MASK 0xfffff000 325 #define AUDIOHDC_4BIT_VERB_MASK 0xfffffff0 326 327 /* 328 * 12-bit verbs 329 */ 330 #define AUDIOHDC_VERB_GET_PARAM 0xf00 331 332 #define AUDIOHDC_VERB_GET_CONN_SEL 0xf01 333 #define AUDIOHDC_VERB_SET_CONN_SEL 0x701 334 335 #define AUDIOHDC_VERB_GET_CONN_LIST_ENT 0xf02 336 #define AUDIOHDC_VERB_GET_PROCESS_STATE 0xf03 337 #define AUDIOHDC_VERB_GET_SDI_SEL 0xf04 338 339 #define AUDIOHDC_VERB_GET_POWER_STATE 0xf05 340 #define AUDIOHDC_VERB_SET_POWER_STATE 0x705 341 342 #define AUDIOHDC_VERB_GET_STREAM_CHANN 0xf06 343 #define AUDIOHDC_VERB_SET_STREAM_CHANN 0x706 344 345 #define AUDIOHDC_VERB_GET_PIN_CTRL 0xf07 346 #define AUDIOHDC_VERB_SET_PIN_CTRL 0x707 347 348 #define AUDIOHDC_VERB_GET_UNS_ENABLE 0xf08 349 350 #define AUDIOHDC_VERB_GET_PIN_SENSE 0xf09 351 #define AUDIOHDC_VERB_EXEC_PIN_SENSE 0x709 352 353 #define AUDIOHDC_VERB_GET_BEEP_GEN 0xf0a 354 355 #define AUDIOHDC_VERB_GET_EAPD 0xf0c 356 #define AUDIOHDC_VERB_SET_EAPD 0x70c 357 358 #define AUDIOHDC_VERB_GET_DEFAULT_CONF 0xf1c 359 #define AUDIOHDC_VERB_GET_SPDIF_CTL 0xf0d 360 #define AUDIOHDC_VERB_SET_SPDIF_LCL 0x70d 361 362 #define AUDIOHDC_VERB_SET_URCTRL 0x708 363 #define AUDIOHDC_VERB_GET_PIN_SENSE 0xf09 364 365 #define AUDIOHDC_VERB_GET_GPIO_MASK 0xf16 366 #define AUDIOHDC_VERB_SET_GPIO_MASK 0x716 367 368 #define AUDIOHDC_VERB_GET_GPIO_DIREC 0xf17 369 #define AUDIOHDC_VERB_SET_GPIO_DIREC 0x717 370 371 #define AUDIOHDC_VERB_GET_GPIO_DATA 0xf15 372 #define AUDIOHDC_VERB_SET_GPIO_DATA 0x715 373 374 #define AUDIOHDC_VERB_GET_GPIO_STCK 0xf1a 375 #define AUDIOHDC_VERB_SET_GPIO_STCK 0x71a 376 377 #define AUDIOHDC_GPIO_ENABLE 0xff 378 #define AUDIOHDC_GPIO_DIRECT 0xf1 379 380 #define AUDIOHDC_GPIO_DATA_CTRL 0xff 381 #define AUDIOHDC_GPIO_STCK_CTRL 0xff 382 /* 383 * 4-bit verbs 384 */ 385 #define AUDIOHDC_VERB_GET_CONV_FMT 0xa 386 #define AUDIOHDC_VERB_SET_CONV_FMT 0x2 387 388 #define AUDIOHDC_VERB_GET_AMP_MUTE 0xb 389 #define AUDIOHDC_VERB_SET_AMP_MUTE 0x3 390 391 /* 392 * parameters of nodes 393 */ 394 #define AUDIOHDC_PAR_VENDOR_ID 0x00 395 #define AUDIOHDC_PAR_SUBSYS_ID 0x01 396 #define AUDIOHDC_PAR_REV_ID 0x02 397 #define AUDIOHDC_PAR_NODE_COUNT 0x04 398 #define AUDIOHDC_PAR_FUNCTION_TYPE 0x05 399 #define AUDIOHDC_PAR_AUDIO_FG_CAP 0x08 400 #define AUDIOHDC_PAR_AUDIO_WID_CAP 0x09 401 #define AUDIOHDC_PAR_PCM 0x0a 402 #define AUDIOHDC_PAR_STREAM 0x0b 403 #define AUDIOHDC_PAR_PIN_CAP 0x0c 404 #define AUDIOHDC_PAR_INAMP_CAP 0x0d 405 #define AUDIOHDC_PAR_CONNLIST_LEN 0x0e 406 #define AUDIOHDC_PAR_POWER_STATE 0x0f 407 #define AUDIOHDC_PAR_PROC_CAP 0x10 408 #define AUDIOHDC_PAR_GPIO_CAP 0x11 409 #define AUDIOHDC_PAR_OUTAMP_CAP 0x12 410 411 /* 412 * bits for get/set amplifier gain/mute 413 */ 414 #define AUDIOHDC_AMP_SET_OUTPUT 0x8000 415 #define AUDIOHDC_AMP_SET_INPUT 0x4000 416 #define AUDIOHDC_AMP_SET_LEFT 0x2000 417 #define AUDIOHDC_AMP_SET_RIGHT 0x1000 418 #define AUDIOHDC_AMP_SET_MUTE 0x0080 419 #define AUDIOHDC_AMP_SET_LNR 0x3000 420 #define AUDIOHDC_AMP_SET_LR_INPUT 0x7000 421 #define AUDIOHDC_AMP_SET_LR_OUTPUT 0xb000 422 #define AUDIOHDC_AMP_SET_INDEX_OFFSET 8 423 #define AUDIOHDC_AMP_SET_GAIN_MASK 0x007f 424 #define AUDIOHDC_GAIN_MAX 0x7f 425 #define AUDIOHDC_GAIN_BITS 7 426 #define AUDIOHDC_GAIN_DEFAULT 0x0f 427 428 #define AUDIOHDC_AMP_GET_OUTPUT 0x8000 429 #define AUDIOHDC_AMP_GET_INPUT 0x0000 430 431 /* value used to set max volume for left output */ 432 #define AUDIOHDC_AMP_LOUT_MAX \ 433 (AUDIOHDC_AMP_SET_OUTPUT | \ 434 AUDIOHDC_AMP_SET_LEFT | \ 435 AUDIOHDC_GAIN_MAX) 436 437 /* value used to set max volume for right output */ 438 #define AUDIOHDC_AMP_ROUT_MAX \ 439 (AUDIOHDC_AMP_SET_OUTPUT | \ 440 AUDIOHDC_AMP_SET_RIGHT | \ 441 AUDIOHDC_GAIN_MAX) 442 443 444 /* 445 * Bits for pin widget control verb 446 */ 447 #define AUDIOHDC_PIN_CONTROL_HP_ENABLE 0x80 448 #define AUDIOHDC_PIN_CONTROL_OUT_ENABLE 0x40 449 #define AUDIOHDC_PIN_CONTROL_IN_ENABLE 0x20 450 451 /* 452 * Bits for Amplifier capabilities 453 */ 454 #define AUDIOHDC_AMP_CAP_MUTE_CAP 0x80000000 455 #define AUDIOHDC_AMP_CAP_STEP_SIZE 0x007f0000 456 #define AUDIOHDC_AMP_CAP_STEP_NUMS 0x00007f00 457 #define AUDIOHDC_AMP_CAP_0DB_OFFSET 0x0000007f 458 459 460 /* 461 * Bits for Audio Widget Capabilities 462 */ 463 #define AUDIOHD_WIDCAP_STEREO 0x00000001 464 #define AUDIOHD_WIDCAP_INAMP 0x00000002 465 #define AUDIOHD_WIDCAP_OUTAMP 0x00000004 466 #define AUDIOHD_WIDCAP_AMP_OVRIDE 0x00000008 467 #define AUDIOHD_WIDCAP_FMT_OVRIDE 0x00000010 468 #define AUDIOHD_WIDCAP_STRIP 0x00000020 469 #define AUDIOHD_WIDCAP_PROC_WID 0x00000040 470 #define AUDIOHD_WIDCAP_UNSOL 0x00000080 471 #define AUDIOHD_WIDCAP_CONNLIST 0x00000100 472 #define AUDIOHD_WIDCAP_DIGIT 0x00000200 473 #define AUDIOHD_WIDCAP_PWRCTRL 0x00000400 474 #define AUDIOHD_WIDCAP_LRSWAP 0x00000800 475 #define AUDIOHD_WIDCAP_TYPE 0x00f00000 476 #define AUDIOHD_WIDCAP_TO_WIDTYPE(wcap) \ 477 ((wcap & AUDIOHD_WIDCAP_TYPE) >> 20) 478 479 480 #define AUDIOHD_CODEC_FAILURE (uint32_t)(-1) 481 482 /* 483 * buffer descriptor list entry of stream descriptor 484 */ 485 typedef struct { 486 uint64_t sbde_addr; 487 uint32_t sbde_len; 488 uint32_t 489 sbde_ioc: 1, 490 reserved: 31; 491 }sd_bdle_t; 492 493 494 #define AUDIOHD_PLAY_STARTED 0x00000001 495 #define AUDIOHD_PLAY_EMPTY 0x00000002 496 #define AUDIOHD_PLAY_PAUSED 0x00000004 497 #define AUDIOHD_RECORD_STARTED 0x00000008 498 499 enum audiohda_widget_type { 500 WTYPE_AUDIO_OUT = 0, 501 WTYPE_AUDIO_IN, 502 WTYPE_AUDIO_MIX, 503 WTYPE_AUDIO_SEL, 504 WTYPE_PIN, 505 WTYPE_POWER, 506 WTYPE_VOL_KNOB, 507 WTYPE_BEEP, 508 WTYPE_VENDOR = 0xf 509 }; 510 511 enum audiohda_device_type { 512 DTYPE_LINEOUT = 0, 513 DTYPE_SPEAKER, 514 DTYPE_HP_OUT, 515 DTYPE_CD, 516 DTYPE_SPDIF_OUT, 517 DTYPE_DIGIT_OUT, 518 DTYPE_MODEM_SIDE, 519 DTYPE_MODEM_HNAD_SIDE, 520 DTYPE_LINE_IN, 521 DTYPE_AUX, 522 DTYPE_MIC_IN, 523 DTYPE_TEL, 524 DTYPE_SPDIF_IN, 525 DTYPE_DIGIT_IN, 526 DTYPE_OTHER = 0x0f, 527 }; 528 529 enum audiohd_pin_color { 530 AUDIOHD_PIN_UNKNOWN = 0, 531 AUDIOHD_PIN_BLACK, 532 AUDIOHD_PIN_GREY, 533 AUDIOHD_PIN_BLUE, 534 AUDIOHD_PIN_GREEN, 535 AUDIOHD_PIN_RED, 536 AUDIOHD_PIN_ORANGE, 537 AUDIOHD_PIN_YELLOW, 538 AUDIOHD_PIN_PURPLE, 539 AUDIOHD_PIN_PINK, 540 AUDIOHD_PIN_WHITE = 0xe, 541 AUDIOHD_PIN_OTHER = 0xf, 542 }; 543 544 #define CTRL_NUM 15 545 546 /* values for audiohd_widget.path_flags */ 547 #define AUDIOHD_PATH_DAC (1 << 0) 548 #define AUDIOHD_PATH_ADC (1 << 1) 549 #define AUDIOHD_PATH_MON (1 << 2) 550 #define AUDIOHD_PATH_NOMON (1 << 3) 551 552 typedef struct audiohd_path audiohd_path_t; 553 typedef struct audiohd_widget audiohd_widget_t; 554 typedef struct audiohd_state audiohd_state_t; 555 typedef struct audiohd_pin audiohd_pin_t; 556 typedef struct hda_codec hda_codec_t; 557 typedef uint32_t wid_t; /* id of widget */ 558 typedef struct audiohd_entry_prop audiohd_entry_prop_t; 559 typedef enum audiohda_device_type audiohda_device_type_t; 560 typedef enum audiohd_pin_color audiohd_pin_color_t; 561 562 #define AUDIOHD_MAX_WIDGET 128 563 #define AUDIOHD_MAX_CONN 16 564 #define AUDIOHD_MAX_PINS 16 565 #define AUDIOHD_MAX_DEPTH 8 566 567 struct audiohd_entry_prop { 568 uint32_t conn_len; 569 uint32_t mask_range; 570 uint32_t mask_wid; 571 wid_t input_wid; 572 int conns_per_entry; 573 int bits_per_conn; 574 }; 575 struct audiohd_widget { 576 wid_t wid_wid; 577 hda_codec_t *codec; 578 enum audiohda_widget_type type; 579 580 uint32_t widget_cap; 581 uint32_t pcm_format; 582 uint32_t inamp_cap; 583 uint32_t outamp_cap; 584 585 uint32_t path_flags; 586 587 int out_weight; 588 int in_weight; 589 int finish; 590 591 /* 592 * wid of possible & selected input connections 593 */ 594 wid_t avail_conn[AUDIOHD_MAX_CONN]; 595 wid_t selconn; 596 /* 597 * for monitor path 598 */ 599 wid_t selmon[AUDIOHD_MAX_CONN]; 600 uint16_t used; 601 602 /* 603 * available (input) connections. 0 means this widget 604 * has fixed connection 605 */ 606 int nconns; 607 608 /* 609 * pointer to struct depending on widget type: 610 * 1. DAC audiohd_ostream_t 611 * 2. ADC audiohd_istream_t 612 * 3. PIN audiohd_pin_t 613 */ 614 void *priv; 615 }; 616 617 #define AUDIOHD_FLAG_LINEOUT (1 << 0) 618 #define AUDIOHD_FLAG_SPEAKER (1 << 1) 619 #define AUDIOHD_FLAG_HP (1 << 2) 620 #define AUDIOHD_FLAG_MONO (1 << 3) 621 622 #define AUDIOHD_MAX_MIXER 5 623 #define AUDIOHD_MAX_PIN 4 624 625 #define PORT_DAC 0 626 #define PORT_ADC 1 627 #define PORT_MAX 2 628 typedef enum { 629 PLAY = 0, 630 RECORD = 1, 631 } path_type_t; 632 633 struct audiohd_path { 634 wid_t adda_wid; 635 636 wid_t pin_wid[AUDIOHD_MAX_PINS]; 637 int sum_selconn[AUDIOHD_MAX_PINS]; 638 int mon_wid[AUDIOHD_MAX_PIN][AUDIOHD_MAX_MIXER]; 639 int pin_nums; 640 int maxmixer[AUDIOHD_MAX_PINS]; 641 642 path_type_t path_type; 643 644 wid_t mute_wid; 645 int mute_dir; 646 wid_t gain_wid; 647 int gain_dir; 648 uint32_t gain_bits; 649 650 uint32_t pin_outputs; 651 uint8_t tag; 652 653 hda_codec_t *codec; 654 655 wid_t sum_wid; 656 657 audiohd_state_t *statep; 658 }; 659 660 typedef struct audiohd_port 661 { 662 uint8_t nchan; 663 int index; 664 uint16_t regoff; 665 boolean_t started; 666 boolean_t triggered; 667 668 unsigned fragfr; 669 unsigned nframes; 670 uint64_t count; 671 int curpos; 672 int len; 673 int intrs; 674 675 uint_t format; 676 unsigned sync_dir; 677 678 ddi_dma_handle_t samp_dmah; 679 ddi_acc_handle_t samp_acch; 680 size_t samp_size; 681 caddr_t samp_kaddr; 682 uint64_t samp_paddr; 683 684 ddi_dma_handle_t bdl_dmah; 685 ddi_acc_handle_t bdl_acch; 686 size_t bdl_size; 687 caddr_t bdl_kaddr; 688 uint64_t bdl_paddr; 689 690 audio_engine_t *engine; 691 audiohd_state_t *statep; 692 }audiohd_port_t; 693 694 typedef struct audiohd_ctrl 695 { 696 audiohd_state_t *statep; 697 audio_ctrl_t *ctrl; 698 uint32_t num; 699 uint64_t val; 700 } audiohd_ctrl_t; 701 702 struct audiohd_pin { 703 audiohd_pin_t *next; 704 wid_t wid; 705 wid_t mute_wid; /* node used to mute this pin */ 706 int mute_dir; /* 1: input, 2: output */ 707 wid_t gain_wid; /* node for gain control */ 708 int gain_dir; /* _OUTPUT/_INPUT */ 709 uint32_t gain_bits; 710 711 uint8_t vrefvalue; /* value of VRef */ 712 713 uint32_t cap; 714 uint32_t config; 715 uint32_t ctrl; 716 uint32_t assoc; 717 uint32_t seq; 718 wid_t adc_dac_wid; /* AD/DA wid which can route to this pin */ 719 int no_phys_conn; 720 enum audiohda_device_type device; 721 722 /* 723 * mg_dir, mg_gain, mg_wid are used to store the monitor gain control 724 * widget wid. 725 */ 726 int mg_dir[AUDIOHD_MAX_CONN]; 727 int mg_gain[AUDIOHD_MAX_CONN]; 728 int mg_wid[AUDIOHD_MAX_CONN]; 729 int num; 730 int finish; 731 732 }; 733 734 typedef struct { 735 ddi_dma_handle_t ad_dmahdl; 736 ddi_acc_handle_t ad_acchdl; 737 caddr_t ad_vaddr; /* virtual addr */ 738 uint64_t ad_paddr; /* physical addr */ 739 size_t ad_req_sz; /* required size of memory */ 740 size_t ad_real_sz; /* real size of memory */ 741 } audiohd_dma_t; 742 743 struct hda_codec { 744 uint8_t index; /* codec address */ 745 uint32_t vid; /* vendor id and device id */ 746 uint32_t revid; /* revision id */ 747 wid_t wid_afg; /* id of AFG */ 748 wid_t first_wid; /* wid of 1st subnode of AFG */ 749 wid_t last_wid; /* wid of the last subnode of AFG */ 750 int nnodes; /* # of subnodes of AFG */ 751 uint8_t nistream; 752 753 uint32_t outamp_cap; 754 uint32_t inamp_cap; 755 uint32_t stream_format; 756 uint32_t pcm_format; 757 758 audiohd_state_t *soft_statep; 759 760 /* use wid as index to the array of widget pointers */ 761 audiohd_widget_t *widget[AUDIOHD_MAX_WIDGET]; 762 763 764 audiohd_port_t *port[AUDIOHD_PORT_MAX]; 765 uint8_t portnum; 766 audiohd_pin_t *first_pin; 767 }; 768 769 #define AUDIOHD_MAX_ASSOC 15 770 struct audiohd_state { 771 dev_info_t *hda_dip; 772 kstat_t *hda_ksp; 773 kmutex_t hda_mutex; 774 uint32_t hda_flags; 775 776 boolean_t soft_volume; 777 778 caddr_t hda_reg_base; 779 ddi_acc_handle_t hda_pci_handle; 780 ddi_acc_handle_t hda_reg_handle; 781 ddi_iblock_cookie_t hda_intr_cookie; 782 783 audiohd_dma_t hda_dma_corb; 784 audiohd_dma_t hda_dma_rirb; 785 786 787 uint8_t hda_rirb_rp; /* read pointer for rirb */ 788 uint16_t hda_codec_mask; 789 790 791 audio_dev_t *adev; 792 793 794 int hda_pint_freq; /* play intr frequence */ 795 int hda_rint_freq; /* record intr frequence */ 796 797 int hda_input_streams; /* # of input stream */ 798 int hda_output_streams; /* # of output stream */ 799 int hda_streams_nums; /* # of stream */ 800 801 uint_t hda_play_regbase; 802 uint_t hda_record_regbase; 803 804 uint_t hda_play_stag; /* tag of playback stream */ 805 uint_t hda_record_stag; /* tag of record stream */ 806 uint_t hda_play_lgain; /* left gain for playback */ 807 uint_t hda_play_rgain; /* right gain for playback */ 808 809 /* 810 * Now, for the time being, we add some fields 811 * for parsing codec topology 812 */ 813 hda_codec_t *codec[AUDIOHD_CODEC_MAX]; 814 /* 815 * Suspend/Resume used fields 816 */ 817 boolean_t suspended; 818 boolean_t monitor_unsupported; 819 820 audiohd_path_t *path[AUDIOHD_PORT_MAX]; 821 uint8_t pathnum; 822 audiohd_port_t *port[PORT_MAX]; 823 uint8_t pchan; 824 uint8_t rchan; 825 826 uint64_t inmask; 827 828 uint_t hda_out_ports; 829 uint_t in_port; 830 831 /* 832 * Controls 833 */ 834 audiohd_ctrl_t *controls[CTRL_NUM]; 835 836 /* for multichannel */ 837 uint8_t chann[AUDIOHD_MAX_ASSOC]; 838 uint8_t assoc; 839 840 }; 841 842 843 /* 844 * Operation for high definition audio control system bus 845 * interface registers 846 */ 847 #define AUDIOHD_REG_GET8(reg) \ 848 ddi_get8(statep->hda_reg_handle, \ 849 (void *)((char *)statep->hda_reg_base + (reg))) 850 851 #define AUDIOHD_REG_GET16(reg) \ 852 ddi_get16(statep->hda_reg_handle, \ 853 (void *)((char *)statep->hda_reg_base + (reg))) 854 855 #define AUDIOHD_REG_GET32(reg) \ 856 ddi_get32(statep->hda_reg_handle, \ 857 (void *)((char *)statep->hda_reg_base + (reg))) 858 859 #define AUDIOHD_REG_GET64(reg) \ 860 ddi_get64(statep->hda_reg_handle, \ 861 (void *)((char *)statep->hda_reg_base + (reg))) 862 863 #define AUDIOHD_REG_SET8(reg, val) \ 864 ddi_put8(statep->hda_reg_handle, \ 865 (void *)((char *)statep->hda_reg_base + (reg)), (val)) 866 867 #define AUDIOHD_REG_SET16(reg, val) \ 868 ddi_put16(statep->hda_reg_handle, \ 869 (void *)((char *)statep->hda_reg_base + (reg)), (val)) 870 871 #define AUDIOHD_REG_SET32(reg, val) \ 872 ddi_put32(statep->hda_reg_handle, \ 873 (void *)((char *)statep->hda_reg_base + (reg)), (val)) 874 875 #define AUDIOHD_REG_SET64(reg, val) \ 876 ddi_put64(statep->hda_reg_handle, \ 877 (void *)((char *)statep->hda_reg_base + (reg)), (val)) 878 879 880 /* 881 * enable a pin widget to output 882 */ 883 #define AUDIOHD_ENABLE_PIN_OUT(statep, caddr, wid) \ 884 { \ 885 uint32_t lTmp; \ 886 \ 887 lTmp = audioha_codec_verb_get(statep, caddr, wid, \ 888 AUDIOHDC_VERB_GET_PIN_CTRL, 0); \ 889 if (lTmp == AUDIOHD_CODEC_FAILURE) \ 890 return (AUDIO_FAILURE); \ 891 lTmp = audioha_codec_verb_get(statep, caddr, wid, \ 892 AUDIOHDC_VERB_SET_PIN_CTRL, \ 893 (lTmp | AUDIOHDC_PIN_CONTROL_OUT_ENABLE | \ 894 AUDIOHDC_PIN_CONTROL_HP_ENABLE)); \ 895 if (lTmp == AUDIOHD_CODEC_FAILURE) \ 896 return (AUDIO_FAILURE); \ 897 } 898 899 /* 900 * disable output pin 901 */ 902 #define AUDIOHD_DISABLE_PIN_OUT(statep, caddr, wid) \ 903 { \ 904 uint32_t lTmp; \ 905 \ 906 lTmp = audioha_codec_verb_get(statep, caddr, wid, \ 907 AUDIOHDC_VERB_GET_PIN_CTRL, 0); \ 908 if (lTmp == AUDIOHD_CODEC_FAILURE) \ 909 return (AUDIO_FAILURE); \ 910 lTmp = audioha_codec_verb_get(statep, caddr, wid, \ 911 AUDIOHDC_VERB_SET_PIN_CTRL, \ 912 (lTmp & ~AUDIOHDC_PIN_CONTROL_OUT_ENABLE)); \ 913 if (lTmp == AUDIOHD_CODEC_FAILURE) \ 914 return (AUDIO_FAILURE); \ 915 } 916 917 /* 918 * enable a pin widget to input 919 */ 920 #define AUDIOHD_ENABLE_PIN_IN(statep, caddr, wid) \ 921 { \ 922 (void) audioha_codec_verb_get(statep, caddr, wid, \ 923 AUDIOHDC_VERB_SET_PIN_CTRL, AUDIOHDC_PIN_CONTROL_IN_ENABLE | 4); \ 924 } 925 926 927 /* 928 * disable input pin 929 */ 930 #define AUDIOHD_DISABLE_PIN_IN(statep, caddr, wid) \ 931 { \ 932 uint32_t lTmp; \ 933 \ 934 lTmp = audioha_codec_verb_get(statep, caddr, wid, \ 935 AUDIOHDC_VERB_GET_PIN_CTRL, 0); \ 936 if (lTmp == AUDIOHD_CODEC_FAILURE) \ 937 return (AUDIO_FAILURE); \ 938 lTmp = audioha_codec_verb_get(statep, caddr, wid, \ 939 AUDIOHDC_VERB_SET_PIN_CTRL, \ 940 (lTmp & ~AUDIOHDC_PIN_CONTROL_IN_ENABLE)); \ 941 if (lTmp == AUDIOHD_CODEC_FAILURE) \ 942 return (AUDIO_FAILURE); \ 943 } 944 945 /* 946 * unmute an output pin 947 */ 948 #define AUDIOHD_NODE_UNMUTE_OUT(statep, caddr, wid) \ 949 { \ 950 if (audioha_codec_4bit_verb_get(statep, \ 951 caddr, wid, AUDIOHDC_VERB_SET_AMP_MUTE, \ 952 AUDIOHDC_AMP_SET_LR_OUTPUT | AUDIOHDC_GAIN_MAX) == \ 953 AUDIOHD_CODEC_FAILURE) \ 954 return (AUDIO_FAILURE); \ 955 } 956 957 #ifdef __cplusplus 958 } 959 #endif 960 961 #endif /* _SYS_AUDIOHD_IMPL_H_ */ 962