1 /*
2  * CDDL HEADER START
3  *
4  * The contents of this file are subject to the terms of the
5  * Common Development and Distribution License (the "License").
6  * You may not use this file except in compliance with the License.
7  *
8  * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
9  * or http://www.opensolaris.org/os/licensing.
10  * See the License for the specific language governing permissions
11  * and limitations under the License.
12  *
13  * When distributing Covered Code, include this CDDL HEADER in each
14  * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
15  * If applicable, add the following below this CDDL HEADER, with the
16  * fields enclosed by brackets "[]" replaced with your own identifying
17  * information: Portions Copyright [yyyy] [name of copyright owner]
18  *
19  * CDDL HEADER END
20  */
21 
22 /*
23  * Copyright 2009 Sun Microsystems, Inc.  All rights reserved.
24  * Use is subject to license terms.
25  */
26 
27 /*
28  * Purpose: Definitions for the CS 4281 AC97 driver
29  */
30 /*
31  * This file is part of Open Sound System
32  *
33  * Copyright (C) 4Front Technologies 1996-2009.
34  *
35  * This software is released under CDDL 1.0 source license.
36  * See the COPYING file included in the main directory of this source
37  * distribution for the license terms and conditions.
38  */
39 #ifndef	AUDIOP16X_H
40 #define	AUDIOP16X_H
41 
42 #define	P16X_NAME		"audiop16x"
43 
44 #define	P16X_NUM_PORT	2
45 
46 #define	CREATIVE_VENDOR_ID	0x1102
47 #define	SB_P16X_ID		0x0006
48 
49 #define	P16X_MAX_INTRS	256
50 #define	P16X_MIN_INTRS	24
51 #define	P16X_DEF_INTRS	175
52 
53 typedef struct _p16x_dev_t p16x_dev_t;
54 typedef struct _p16x_port_t p16x_port_t;
55 
56 struct _p16x_port_t
57 {
58 	p16x_dev_t 		*dev;
59 	audio_engine_t 		*engine;
60 
61 	unsigned		intrs;
62 	caddr_t			base;
63 	boolean_t		started;
64 	boolean_t		suspended;
65 
66 	int			port_num;
67 #define	P16X_PLAY		0
68 #define	P16X_REC		1
69 	ddi_dma_handle_t	buf_dmah;	/* dma for buffers */
70 	ddi_acc_handle_t	buf_acch;
71 	uint32_t		buf_paddr;
72 	caddr_t			buf_kaddr;
73 	size_t			buf_size;
74 	uint32_t		buf_frames;
75 	int			syncdir;
76 	int			nchan;
77 	unsigned		fragfr;
78 	unsigned		nfrags;
79 	unsigned		fragsz;
80 	unsigned		nframes;
81 	uint64_t		count;
82 	uint32_t		offset;
83 };
84 
85 struct _p16x_dev_t
86 {
87 	dev_info_t		*dip;
88 	audio_dev_t		*adev;
89 	ac97_t			*ac97;
90 	kstat_t			*ksp;
91 	ddi_iblock_cookie_t	iblock;
92 	boolean_t		suspended;
93 	boolean_t		intr_added;
94 	ddi_acc_handle_t	pcih;
95 	ddi_acc_handle_t	regsh;
96 	caddr_t			base;
97 	kmutex_t		mutex;		/* For normal locking */
98 	kmutex_t		low_mutex;	/* For low level routines */
99 	ddi_intr_handle_t	ih;
100 
101 	p16x_port_t 		*port[P16X_NUM_PORT];
102 };
103 
104 #define	INL(dev, reg)	\
105 	ddi_get32(dev->regsh, (void *)((char *)dev->base+(reg)))
106 #define	INW(dev, reg)	\
107 	ddi_get16(dev->regsh, (void *)((char *)dev->base+(reg)))
108 #define	INB(dev, reg)	\
109 	ddi_get8(dev->regsh, (void *)((char *)dev->base+(reg)))
110 
111 #define	OUTL(dev, val, reg)	\
112 	ddi_put32(dev->regsh, (void *)((char *)dev->base+(reg)), (val))
113 #define	OUTW(dev, val, reg)	\
114 	ddi_put16(dev->regsh, (void *)((char *)dev->base+(reg)), (val))
115 #define	OUTB(dev, val, reg)	\
116 	ddi_put8(dev->regsh, (void *)((char *)dev->base+(reg)), (val))
117 
118 #define	P16X_KIOP(X)	((kstat_intr_t *)(X->ksp->ks_data))
119 
120 /*
121  * SB P16X Registers
122  */
123 
124 #define	PTR 	0x00
125 #define	DR	0x04
126 #define	IP	0x08
127 #define	IE	0x0C
128 #define	HC	0x14
129 #define	GPIO	0x18
130 #define	AC97D	0x1C
131 #define	AC97A	0x1E
132 
133 /*
134  * Indirect registers
135  */
136 
137 #define	PTBA	0x000
138 #define	PTBS	0x001
139 #define	PTCA	0x002
140 #define	PFBA	0x004
141 #define	PFBS	0x005
142 #define	CPFA	0x006
143 #define	PFEA	0x007
144 #define	CPCAV	0x008
145 #define	RFBA	0x010
146 #define	RFBS	0x011
147 #define	CRFA	0x012
148 #define	CRCAV	0x013
149 #define	CDL	0x020
150 #define	CDR	0x030
151 #define	SA	0x040
152 #define	EA_aux	0x041
153 #define	SCS0	0x042
154 #define	SCS1	0x043
155 #define	SCS2	0x044
156 #define	SPC	0x045
157 #define	WMARK	0x046
158 #define	MUDAT	0x047
159 #define	MUCMD	0x048
160 #define	RCD	0x050
161 
162 /*
163  * Interrupt bits
164  */
165 
166 #define	INTR_RFF	(1<<19)
167 #define	INTR_RFH	(1<<16)
168 #define	INTR_PFF	(3<<11)
169 #define	INTR_PFH	(3<<8)
170 #define	INTR_EAI	(1<<29)
171 #define	INTR_PCI	1
172 #define	INTR_UART_RX	2
173 #define	INTR_UART_TX	4
174 #define	INTR_AC97	0x10
175 #define	INTR_GPIO	0x40
176 #define	INTR_PLAY	(INTR_PFF | INTR_PFH)
177 #define	INTR_REC	(INTR_RFF | INTR_RFH)
178 #define	INTR_ALL	(INTR_PLAY | INTR_REC | INTR_PCI)
179 
180 #endif /* AUDIOP16X_H */
181