1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License, Version 1.0 only 6 * (the "License"). You may not use this file except in compliance 7 * with the License. 8 * 9 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 10 * or http://www.opensolaris.org/os/licensing. 11 * See the License for the specific language governing permissions 12 * and limitations under the License. 13 * 14 * When distributing Covered Code, include this CDDL HEADER in each 15 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 16 * If applicable, add the following below this CDDL HEADER, with the 17 * fields enclosed by brackets "[]" replaced with your own identifying 18 * information: Portions Copyright [yyyy] [name of copyright owner] 19 * 20 * CDDL HEADER END 21 */ 22 /* 23 * Copyright 2005 Sun Microsystems, Inc. All rights reserved. 24 * Use is subject to license terms. 25 */ 26 27 #pragma ident "%Z%%M% %I% %E% SMI" 28 29 #include "sys/bge_impl.h" 30 31 /* 32 * Bit test macros, returning boolean_t values 33 */ 34 #define BIS(w, b) (((w) & (b)) ? B_TRUE : B_FALSE) 35 #define BIC(w, b) (((w) & (b)) ? B_FALSE : B_TRUE) 36 #define UPORDOWN(x) ((x) ? "up" : "down") 37 38 /* 39 * ========== Copper (PHY) support ========== 40 */ 41 42 #define BGE_DBG BGE_DBG_PHY /* debug flag for this code */ 43 44 /* 45 * #defines: 46 * BGE_COPPER_WIRESPEED controls whether the Broadcom WireSpeed(tm) 47 * feature is enabled. We need to recheck whether this can be 48 * enabled; at one time it seemed to interact unpleasantly with the 49 * loopback modes. 50 * 51 * BGE_COPPER_IDLEOFF controls whether the (copper) PHY power is 52 * turned off when the PHY is idled i.e. during driver suspend(). 53 * For now this is disabled because the chip doesn't seem to 54 * resume cleanly if the PHY power is turned off. 55 */ 56 #define BGE_COPPER_WIRESPEED B_TRUE 57 #define BGE_COPPER_IDLEOFF B_FALSE 58 59 /* 60 * The arrays below can be indexed by the MODE bits from the Auxiliary 61 * Status register to determine the current speed/duplex settings. 62 */ 63 static const int16_t bge_copper_link_speed[] = { 64 0, /* MII_AUX_STATUS_MODE_NONE */ 65 10, /* MII_AUX_STATUS_MODE_10_H */ 66 10, /* MII_AUX_STATUS_MODE_10_F */ 67 100, /* MII_AUX_STATUS_MODE_100_H */ 68 0, /* MII_AUX_STATUS_MODE_100_4 */ 69 100, /* MII_AUX_STATUS_MODE_100_F */ 70 1000, /* MII_AUX_STATUS_MODE_1000_H */ 71 1000 /* MII_AUX_STATUS_MODE_1000_F */ 72 }; 73 74 static const int8_t bge_copper_link_duplex[] = { 75 LINK_DUPLEX_UNKNOWN, /* MII_AUX_STATUS_MODE_NONE */ 76 LINK_DUPLEX_HALF, /* MII_AUX_STATUS_MODE_10_H */ 77 LINK_DUPLEX_FULL, /* MII_AUX_STATUS_MODE_10_F */ 78 LINK_DUPLEX_HALF, /* MII_AUX_STATUS_MODE_100_H */ 79 LINK_DUPLEX_UNKNOWN, /* MII_AUX_STATUS_MODE_100_4 */ 80 LINK_DUPLEX_FULL, /* MII_AUX_STATUS_MODE_100_F */ 81 LINK_DUPLEX_HALF, /* MII_AUX_STATUS_MODE_1000_H */ 82 LINK_DUPLEX_FULL /* MII_AUX_STATUS_MODE_1000_F */ 83 }; 84 85 static const char * const bge_copper_link_text[] = { 86 "down", /* MII_AUX_STATUS_MODE_NONE */ 87 "up 10Mbps Half-Duplex", /* MII_AUX_STATUS_MODE_10_H */ 88 "up 10Mbps Full-Duplex", /* MII_AUX_STATUS_MODE_10_F */ 89 "up 100Mbps Half-Duplex", /* MII_AUX_STATUS_MODE_100_H */ 90 "down", /* MII_AUX_STATUS_MODE_100_4 */ 91 "up 100Mbps Full-Duplex", /* MII_AUX_STATUS_MODE_100_F */ 92 "up 1000Mbps Half-Duplex", /* MII_AUX_STATUS_MODE_1000_H */ 93 "up 1000Mbps Full-Duplex" /* MII_AUX_STATUS_MODE_1000_F */ 94 }; 95 96 #if BGE_DEBUGGING 97 98 static void 99 bge_phydump(bge_t *bgep, uint16_t mii_status, uint16_t aux) 100 { 101 uint16_t regs[32]; 102 int i; 103 104 ASSERT(mutex_owned(bgep->genlock)); 105 106 for (i = 0; i < 32; ++i) 107 switch (i) { 108 default: 109 regs[i] = bge_mii_get16(bgep, i); 110 break; 111 112 case MII_STATUS: 113 regs[i] = mii_status; 114 break; 115 116 case MII_AUX_STATUS: 117 regs[i] = aux; 118 break; 119 120 case 0x0b: case 0x0c: case 0x0d: case 0x0e: 121 case 0x15: case 0x16: case 0x17: 122 case 0x1c: 123 case 0x1f: 124 /* reserved registers -- don't read these */ 125 regs[i] = 0; 126 break; 127 } 128 129 for (i = 0; i < 32; i += 8) 130 BGE_DEBUG(("bge_phydump: " 131 "0x%04x %04x %04x %04x %04x %04x %04x %04x", 132 regs[i+0], regs[i+1], regs[i+2], regs[i+3], 133 regs[i+4], regs[i+5], regs[i+6], regs[i+7])); 134 } 135 136 #endif /* BGE_DEBUGGING */ 137 138 /* 139 * Basic low-level function to probe for a PHY 140 * 141 * Returns TRUE if the PHY responds with valid data, FALSE otherwise 142 */ 143 static boolean_t 144 bge_phy_probe(bge_t *bgep) 145 { 146 uint16_t phy_status; 147 148 BGE_TRACE(("bge_phy_probe($%p)", (void *)bgep)); 149 150 ASSERT(mutex_owned(bgep->genlock)); 151 152 /* 153 * Read the MII_STATUS register twice, in 154 * order to clear any sticky bits (but they should 155 * have been cleared by the RESET, I think). 156 */ 157 phy_status = bge_mii_get16(bgep, MII_STATUS); 158 phy_status = bge_mii_get16(bgep, MII_STATUS); 159 BGE_DEBUG(("bge_phy_probe: status 0x%x", phy_status)); 160 161 /* 162 * Now check the value read; it should have at least one bit set 163 * (for the device capabilities) and at least one clear (one of 164 * the error bits). So if we see all 0s or all 1s, there's a 165 * problem. In particular, bge_mii_get16() returns all 1s if 166 * communications fails ... 167 */ 168 switch (phy_status) { 169 case 0x0000: 170 case 0xffff: 171 return (B_FALSE); 172 173 default : 174 return (B_TRUE); 175 } 176 } 177 178 /* 179 * Basic low-level function to reset the PHY. 180 * Doesn't incorporate any special-case workarounds. 181 * 182 * Returns TRUE on success, FALSE if the RESET bit doesn't clear 183 */ 184 static boolean_t 185 bge_phy_reset(bge_t *bgep) 186 { 187 uint16_t control; 188 uint_t count; 189 190 BGE_TRACE(("bge_phy_reset($%p)", (void *)bgep)); 191 192 ASSERT(mutex_owned(bgep->genlock)); 193 194 /* 195 * Set the PHY RESET bit, then wait up to 5 ms for it to self-clear 196 */ 197 bge_mii_put16(bgep, MII_CONTROL, MII_CONTROL_RESET); 198 for (count = 0; ++count < 1000; ) { 199 drv_usecwait(5); 200 control = bge_mii_get16(bgep, MII_CONTROL); 201 if (BIC(control, MII_CONTROL_RESET)) 202 return (B_TRUE); 203 } 204 205 BGE_DEBUG(("bge_phy_reset: FAILED, control now 0x%x", control)); 206 207 return (B_FALSE); 208 } 209 210 /* 211 * Basic low-level function to powerdown the PHY, if supported 212 * If powerdown support is compiled out, this function does nothing. 213 */ 214 static void 215 bge_phy_powerdown(bge_t *bgep) 216 { 217 BGE_TRACE(("bge_phy_powerdown")); 218 #if BGE_COPPER_IDLEOFF 219 bge_mii_put16(bgep, MII_CONTROL, MII_CONTROL_PWRDN); 220 #endif /* BGE_COPPER_IDLEOFF */ 221 } 222 223 /* 224 * The following functions are based on sample code provided by 225 * Broadcom (20-June-2003), and implement workarounds said to be 226 * required on the early revisions of the BCM5703/4C. 227 * 228 * The registers and values used are mostly UNDOCUMENTED, and 229 * therefore don't have symbolic names ;-( 230 * 231 * Many of the comments are straight out of the Broadcom code: 232 * even where the code has been restructured, the original 233 * comments have been preserved in order to explain what these 234 * undocumented registers & values are all about ... 235 */ 236 237 static void 238 bge_phy_macro_wait(bge_t *bgep) 239 { 240 uint_t count; 241 242 for (count = 100; --count; ) 243 if ((bge_mii_get16(bgep, 0x16) & 0x1000) == 0) 244 break; 245 } 246 247 /* 248 * PHY test data pattern: 249 * 250 * For 5703/04, each DFE TAP has 21-bits (low word 15, hi word 6) 251 * For 5705, each DFE TAP has 19-bits (low word 15, hi word 4) 252 * For simplicity, we check only 19-bits, so we don't have to 253 * distinguish which chip it is. 254 * the LO word contains 15 bits, make sure pattern data is < 0x7fff 255 * the HI word contains 6 bits, make sure pattern data is < 0x003f 256 */ 257 #define N_CHANNELS 4 258 #define N_TAPS 3 259 260 static struct { 261 uint16_t lo; 262 uint16_t hi; 263 } tap_data[N_CHANNELS][N_TAPS] = { 264 { 265 { 0x5555, 0x0005 }, /* ch0, TAP 0, LO/HI pattern */ 266 { 0x2aaa, 0x000a }, /* ch0, TAP 1, LO/HI pattern */ 267 { 0x3456, 0x0003 } /* ch0, TAP 2, LO/HI pattern */ 268 }, 269 { 270 { 0x2aaa, 0x000a }, /* ch1, TAP 0, LO/HI pattern */ 271 { 0x3333, 0x0003 }, /* ch1, TAP 1, LO/HI pattern */ 272 { 0x789a, 0x0005 } /* ch1, TAP 2, LO/HI pattern */ 273 }, 274 { 275 { 0x5a5a, 0x0005 }, /* ch2, TAP 0, LO/HI pattern */ 276 { 0x2a6a, 0x000a }, /* ch2, TAP 1, LO/HI pattern */ 277 { 0x1bcd, 0x0003 } /* ch2, TAP 2, LO/HI pattern */ 278 }, 279 { 280 { 0x2a5a, 0x000a }, /* ch3, TAP 0, LO/HI pattern */ 281 { 0x33c3, 0x0003 }, /* ch3, TAP 1, LO/HI pattern */ 282 { 0x2ef1, 0x0005 } /* ch3, TAP 2, LO/HI pattern */ 283 } 284 }; 285 286 /* 287 * Check whether the PHY has locked up after a RESET. 288 * 289 * Returns TRUE if it did, FALSE is it's OK ;-) 290 */ 291 static boolean_t 292 bge_phy_locked_up(bge_t *bgep) 293 { 294 uint16_t dataLo; 295 uint16_t dataHi; 296 uint_t chan; 297 uint_t tap; 298 299 /* 300 * Check TAPs for all 4 channels, as soon as we see a lockup 301 * we'll stop checking. 302 */ 303 for (chan = 0; chan < N_CHANNELS; ++chan) { 304 /* Select channel and set TAP index to 0 */ 305 bge_mii_put16(bgep, 0x17, (chan << 13) | 0x0200); 306 /* Freeze filter again just to be safe */ 307 bge_mii_put16(bgep, 0x16, 0x0002); 308 309 /* 310 * Write fixed pattern to the RAM, 3 TAPs for 311 * each channel, each TAP have 2 WORDs (LO/HI) 312 */ 313 for (tap = 0; tap < N_TAPS; ++tap) { 314 bge_mii_put16(bgep, 0x15, tap_data[chan][tap].lo); 315 bge_mii_put16(bgep, 0x15, tap_data[chan][tap].hi); 316 } 317 318 /* 319 * Active PHY's Macro operation to write DFE 320 * TAP from RAM, and wait for Macro to complete. 321 */ 322 bge_mii_put16(bgep, 0x16, 0x0202); 323 bge_phy_macro_wait(bgep); 324 325 /* 326 * Done with write phase, now begin read phase. 327 */ 328 329 /* Select channel and set TAP index to 0 */ 330 bge_mii_put16(bgep, 0x17, (chan << 13) | 0x0200); 331 332 /* 333 * Active PHY's Macro operation to load DFE 334 * TAP to RAM, and wait for Macro to complete 335 */ 336 bge_mii_put16(bgep, 0x16, 0x0082); 337 bge_phy_macro_wait(bgep); 338 339 /* Enable "pre-fetch" */ 340 bge_mii_put16(bgep, 0x16, 0x0802); 341 bge_phy_macro_wait(bgep); 342 343 /* 344 * Read back the TAP values. 3 TAPs for each 345 * channel, each TAP have 2 WORDs (LO/HI) 346 */ 347 for (tap = 0; tap < N_TAPS; ++tap) { 348 /* 349 * Read Lo/Hi then wait for 'done' is faster. 350 * For DFE TAP, the HI word contains 6 bits, 351 * LO word contains 15 bits 352 */ 353 dataLo = bge_mii_get16(bgep, 0x15) & 0x7fff; 354 dataHi = bge_mii_get16(bgep, 0x15) & 0x003f; 355 bge_phy_macro_wait(bgep); 356 357 /* 358 * Check if what we wrote is what we read back. 359 * If failed, then the PHY is locked up, we need 360 * to do PHY reset again 361 */ 362 if (dataLo != tap_data[chan][tap].lo) 363 return (B_TRUE); /* wedged! */ 364 365 if (dataHi != tap_data[chan][tap].hi) 366 return (B_TRUE); /* wedged! */ 367 } 368 } 369 370 /* 371 * The PHY isn't locked up ;-) 372 */ 373 return (B_FALSE); 374 } 375 376 /* 377 * Special-case code to reset the PHY on the 5702/5703/5704C/5705/5782. 378 * Tries up to 5 times to recover from failure to reset or PHY lockup. 379 * 380 * Returns TRUE on success, FALSE if there's an unrecoverable problem 381 */ 382 static boolean_t 383 bge_phy_reset_and_check(bge_t *bgep) 384 { 385 boolean_t reset_success; 386 boolean_t phy_locked; 387 uint16_t extctrl; 388 uint_t retries; 389 390 for (retries = 0; retries < 5; ++retries) { 391 /* Issue a phy reset, and wait for reset to complete */ 392 /* Assuming reset is successful first */ 393 reset_success = bge_phy_reset(bgep); 394 395 /* 396 * Now go check the DFE TAPs to see if locked up, but 397 * first, we need to set up PHY so we can read DFE 398 * TAPs. 399 */ 400 401 /* 402 * Disable Transmitter and Interrupt, while we play 403 * with the PHY registers, so the link partner won't 404 * see any strange data and the Driver won't see any 405 * interrupts. 406 */ 407 extctrl = bge_mii_get16(bgep, 0x10); 408 bge_mii_put16(bgep, 0x10, extctrl | 0x3000); 409 410 /* Setup Full-Duplex, 1000 mbps */ 411 bge_mii_put16(bgep, 0x0, 0x0140); 412 413 /* Set to Master mode */ 414 bge_mii_put16(bgep, 0x9, 0x1800); 415 416 /* Enable SM_DSP_CLOCK & 6dB */ 417 bge_mii_put16(bgep, 0x18, 0x0c00); /* "the ADC fix" */ 418 419 /* Work-arounds */ 420 bge_mii_put16(bgep, 0x17, 0x201f); 421 bge_mii_put16(bgep, 0x15, 0x2aaa); 422 423 /* More workarounds */ 424 bge_mii_put16(bgep, 0x17, 0x000a); 425 bge_mii_put16(bgep, 0x15, 0x0323); /* "the Gamma fix" */ 426 427 /* Blocks the PHY control access */ 428 bge_mii_put16(bgep, 0x17, 0x8005); 429 bge_mii_put16(bgep, 0x15, 0x0800); 430 431 /* Test whether PHY locked up ;-( */ 432 phy_locked = bge_phy_locked_up(bgep); 433 if (reset_success && !phy_locked) 434 break; 435 436 /* 437 * Some problem here ... log it & retry 438 */ 439 if (!reset_success) 440 BGE_REPORT((bgep, "PHY didn't reset!")); 441 if (phy_locked) 442 BGE_REPORT((bgep, "PHY locked up!")); 443 } 444 445 /* Remove block phy control */ 446 bge_mii_put16(bgep, 0x17, 0x8005); 447 bge_mii_put16(bgep, 0x15, 0x0000); 448 449 /* Unfreeze DFE TAP filter for all channels */ 450 bge_mii_put16(bgep, 0x17, 0x8200); 451 bge_mii_put16(bgep, 0x16, 0x0000); 452 453 /* Restore PHY back to operating state */ 454 bge_mii_put16(bgep, 0x18, 0x0400); 455 456 /* Enable transmitter and interrupt */ 457 extctrl = bge_mii_get16(bgep, 0x10); 458 bge_mii_put16(bgep, 0x10, extctrl & ~0x3000); 459 460 return (reset_success && !phy_locked); 461 } 462 463 static void 464 bge_phy_tweak_gmii(bge_t *bgep) 465 { 466 /* Tweak GMII timing */ 467 bge_mii_put16(bgep, 0x1c, 0x8d68); 468 bge_mii_put16(bgep, 0x1c, 0x8d68); 469 } 470 471 /* 472 * End of Broadcom-derived workaround code * 473 */ 474 475 static void 476 bge_restart_copper(bge_t *bgep, boolean_t powerdown) 477 { 478 uint16_t phy_status; 479 boolean_t reset_ok; 480 481 BGE_TRACE(("bge_restart_copper($%p, %d)", (void *)bgep, powerdown)); 482 483 ASSERT(mutex_owned(bgep->genlock)); 484 485 switch (MHCR_CHIP_ASIC_REV(bgep->chipid.asic_rev)) { 486 default: 487 /* 488 * Shouldn't happen; it means we don't recognise this chip. 489 * It's probably a new one, so we'll try our best anyway ... 490 */ 491 case MHCR_CHIP_ASIC_REV_5703: 492 case MHCR_CHIP_ASIC_REV_5704: 493 case MHCR_CHIP_ASIC_REV_5705: 494 case MHCR_CHIP_ASIC_REV_5721_5751: 495 case MHCR_CHIP_ASIC_REV_5714: 496 case MHCR_CHIP_ASIC_REV_5715: 497 reset_ok = bge_phy_reset_and_check(bgep); 498 break; 499 500 case MHCR_CHIP_ASIC_REV_5700: 501 case MHCR_CHIP_ASIC_REV_5701: 502 /* 503 * Just a plain reset; the "check" code breaks these chips 504 */ 505 reset_ok = bge_phy_reset(bgep); 506 break; 507 } 508 if (!reset_ok) 509 bge_problem(bgep, "PHY failed to reset correctly"); 510 511 /* 512 * Step 5: disable WOL (not required after RESET) 513 * 514 * Step 6: refer to errata 515 */ 516 switch (bgep->chipid.asic_rev) { 517 default: 518 break; 519 520 case MHCR_CHIP_REV_5704_A0: 521 bge_phy_tweak_gmii(bgep); 522 break; 523 } 524 525 /* 526 * Step 7: read the MII_INTR_STATUS register twice, 527 * in order to clear any sticky bits (but they should 528 * have been cleared by the RESET, I think), and we're 529 * not using PHY interrupts anyway. 530 * 531 * Step 8: enable the PHY to interrupt on link status 532 * change (not required) 533 * 534 * Step 9: configure PHY LED Mode - not applicable? 535 * 536 * Step 10: read the MII_STATUS register twice, in 537 * order to clear any sticky bits (but they should 538 * have been cleared by the RESET, I think). 539 */ 540 phy_status = bge_mii_get16(bgep, MII_STATUS); 541 phy_status = bge_mii_get16(bgep, MII_STATUS); 542 BGE_DEBUG(("bge_restart_copper: status 0x%x", phy_status)); 543 544 /* 545 * Finally, shut down the PHY, if required 546 */ 547 if (powerdown) 548 bge_phy_powerdown(bgep); 549 } 550 551 /* 552 * Synchronise the (copper) PHY's speed/duplex/autonegotiation capabilities 553 * and advertisements with the required settings as specified by the various 554 * param_* variables that can be poked via the NDD interface. 555 * 556 * We always reset the PHY and reprogram *all* the relevant registers, 557 * not just those changed. This should cause the link to go down, and then 558 * back up again once the link is stable and autonegotiation (if enabled) 559 * is complete. We should get a link state change interrupt somewhere along 560 * the way ... 561 * 562 * NOTE: <genlock> must already be held by the caller 563 */ 564 static void 565 bge_update_copper(bge_t *bgep) 566 { 567 boolean_t adv_autoneg; 568 boolean_t adv_pause; 569 boolean_t adv_asym_pause; 570 boolean_t adv_1000fdx; 571 boolean_t adv_1000hdx; 572 boolean_t adv_100fdx; 573 boolean_t adv_100hdx; 574 boolean_t adv_10fdx; 575 boolean_t adv_10hdx; 576 577 uint16_t control; 578 uint16_t gigctrl; 579 uint16_t auxctrl; 580 uint16_t anar; 581 582 BGE_TRACE(("bge_update_copper($%p)", (void *)bgep)); 583 584 ASSERT(mutex_owned(bgep->genlock)); 585 586 BGE_DEBUG(("bge_update_copper: autoneg %d " 587 "pause %d asym_pause %d " 588 "1000fdx %d 1000hdx %d " 589 "100fdx %d 100hdx %d " 590 "10fdx %d 10hdx %d ", 591 bgep->param_adv_autoneg, 592 bgep->param_adv_pause, bgep->param_adv_asym_pause, 593 bgep->param_adv_1000fdx, bgep->param_adv_1000hdx, 594 bgep->param_adv_100fdx, bgep->param_adv_100hdx, 595 bgep->param_adv_10fdx, bgep->param_adv_10hdx)); 596 597 control = gigctrl = auxctrl = anar = 0; 598 599 /* 600 * PHY settings are normally based on the param_* variables, 601 * but if any loopback mode is in effect, that takes precedence. 602 * 603 * BGE supports MAC-internal loopback, PHY-internal loopback, 604 * and External loopback at a variety of speeds (with a special 605 * cable). In all cases, autoneg is turned OFF, full-duplex 606 * is turned ON, and the speed/mastership is forced. 607 */ 608 switch (bgep->param_loop_mode) { 609 case BGE_LOOP_NONE: 610 default: 611 adv_autoneg = bgep->param_adv_autoneg; 612 adv_pause = bgep->param_adv_pause; 613 adv_asym_pause = bgep->param_adv_asym_pause; 614 adv_1000fdx = bgep->param_adv_1000fdx; 615 adv_1000hdx = bgep->param_adv_1000hdx; 616 adv_100fdx = bgep->param_adv_100fdx; 617 adv_100hdx = bgep->param_adv_100hdx; 618 adv_10fdx = bgep->param_adv_10fdx; 619 adv_10hdx = bgep->param_adv_10hdx; 620 break; 621 622 case BGE_LOOP_EXTERNAL_1000: 623 case BGE_LOOP_EXTERNAL_100: 624 case BGE_LOOP_EXTERNAL_10: 625 case BGE_LOOP_INTERNAL_PHY: 626 case BGE_LOOP_INTERNAL_MAC: 627 adv_autoneg = adv_pause = adv_asym_pause = B_FALSE; 628 adv_1000fdx = adv_100fdx = adv_10fdx = B_FALSE; 629 adv_1000hdx = adv_100hdx = adv_10hdx = B_FALSE; 630 bgep->param_link_duplex = LINK_DUPLEX_FULL; 631 632 switch (bgep->param_loop_mode) { 633 case BGE_LOOP_EXTERNAL_1000: 634 bgep->param_link_speed = 1000; 635 adv_1000fdx = B_TRUE; 636 auxctrl = MII_AUX_CTRL_NORM_EXT_LOOPBACK; 637 gigctrl |= MII_1000BT_CTL_MASTER_CFG; 638 gigctrl |= MII_1000BT_CTL_MASTER_SEL; 639 break; 640 641 case BGE_LOOP_EXTERNAL_100: 642 bgep->param_link_speed = 100; 643 adv_100fdx = B_TRUE; 644 auxctrl = MII_AUX_CTRL_NORM_EXT_LOOPBACK; 645 break; 646 647 case BGE_LOOP_EXTERNAL_10: 648 bgep->param_link_speed = 10; 649 adv_10fdx = B_TRUE; 650 auxctrl = MII_AUX_CTRL_NORM_EXT_LOOPBACK; 651 break; 652 653 case BGE_LOOP_INTERNAL_PHY: 654 bgep->param_link_speed = 1000; 655 adv_1000fdx = B_TRUE; 656 control = MII_CONTROL_LOOPBACK; 657 break; 658 659 case BGE_LOOP_INTERNAL_MAC: 660 bgep->param_link_speed = 1000; 661 adv_1000fdx = B_TRUE; 662 break; 663 } 664 } 665 666 BGE_DEBUG(("bge_update_copper: autoneg %d " 667 "pause %d asym_pause %d " 668 "1000fdx %d 1000hdx %d " 669 "100fdx %d 100hdx %d " 670 "10fdx %d 10hdx %d ", 671 adv_autoneg, 672 adv_pause, adv_asym_pause, 673 adv_1000fdx, adv_1000hdx, 674 adv_100fdx, adv_100hdx, 675 adv_10fdx, adv_10hdx)); 676 677 /* 678 * We should have at least one technology capability set; 679 * if not, we select a default of 1000Mb/s full-duplex 680 */ 681 if (!adv_1000fdx && !adv_100fdx && !adv_10fdx && 682 !adv_1000hdx && !adv_100hdx && !adv_10hdx) 683 adv_1000fdx = B_TRUE; 684 685 /* 686 * Now transform the adv_* variables into the proper settings 687 * of the PHY registers ... 688 * 689 * If autonegotiation is (now) enabled, we want to trigger 690 * a new autonegotiation cycle once the PHY has been 691 * programmed with the capabilities to be advertised. 692 */ 693 if (adv_autoneg) 694 control |= MII_CONTROL_ANE|MII_CONTROL_RSAN; 695 696 if (adv_1000fdx) 697 control |= MII_CONTROL_1000MB|MII_CONTROL_FDUPLEX; 698 else if (adv_1000hdx) 699 control |= MII_CONTROL_1000MB; 700 else if (adv_100fdx) 701 control |= MII_CONTROL_100MB|MII_CONTROL_FDUPLEX; 702 else if (adv_100hdx) 703 control |= MII_CONTROL_100MB; 704 else if (adv_10fdx) 705 control |= MII_CONTROL_FDUPLEX; 706 else if (adv_10hdx) 707 control |= 0; 708 else 709 { _NOTE(EMPTY); } /* Can't get here anyway ... */ 710 711 if (adv_1000fdx) 712 gigctrl |= MII_1000BT_CTL_ADV_FDX; 713 if (adv_1000hdx) 714 gigctrl |= MII_1000BT_CTL_ADV_HDX; 715 716 if (adv_100fdx) 717 anar |= MII_ABILITY_100BASE_TX_FD; 718 if (adv_100hdx) 719 anar |= MII_ABILITY_100BASE_TX; 720 if (adv_10fdx) 721 anar |= MII_ABILITY_10BASE_T_FD; 722 if (adv_10hdx) 723 anar |= MII_ABILITY_10BASE_T; 724 725 if (adv_pause) 726 anar |= MII_ABILITY_PAUSE; 727 if (adv_asym_pause) 728 anar |= MII_ABILITY_ASYM_PAUSE; 729 730 /* 731 * Munge in any other fixed bits we require ... 732 */ 733 anar |= MII_AN_SELECTOR_8023; 734 auxctrl |= MII_AUX_CTRL_NORM_TX_MODE; 735 auxctrl |= MII_AUX_CTRL_NORMAL; 736 737 /* 738 * Restart the PHY and write the new values. Note the 739 * time, so that we can say whether subsequent link state 740 * changes can be attributed to our reprogramming the PHY 741 */ 742 bgep->phys_write_time = gethrtime(); 743 (*bgep->physops->phys_restart)(bgep, B_FALSE); 744 bge_mii_put16(bgep, MII_AN_ADVERT, anar); 745 bge_mii_put16(bgep, MII_CONTROL, control); 746 bge_mii_put16(bgep, MII_AUX_CONTROL, auxctrl); 747 bge_mii_put16(bgep, MII_1000BASE_T_CONTROL, gigctrl); 748 749 BGE_DEBUG(("bge_update_copper: anar <- 0x%x", anar)); 750 BGE_DEBUG(("bge_update_copper: control <- 0x%x", control)); 751 BGE_DEBUG(("bge_update_copper: auxctrl <- 0x%x", auxctrl)); 752 BGE_DEBUG(("bge_update_copper: gigctrl <- 0x%x", gigctrl)); 753 754 #if BGE_COPPER_WIRESPEED 755 /* 756 * Enable the 'wire-speed' feature, if the chip supports it 757 * and we haven't got (any) loopback mode selected. 758 */ 759 switch (bgep->chipid.device) { 760 case DEVICE_ID_5700: 761 case DEVICE_ID_5700x: 762 case DEVICE_ID_5705C: 763 case DEVICE_ID_5782: 764 /* 765 * These chips are known or assumed not to support it 766 */ 767 break; 768 769 default: 770 /* 771 * All other Broadcom chips are expected to support it. 772 */ 773 if (bgep->param_loop_mode == BGE_LOOP_NONE) 774 bge_mii_put16(bgep, MII_AUX_CONTROL, 775 MII_AUX_CTRL_MISC_WRITE_ENABLE | 776 MII_AUX_CTRL_MISC_WIRE_SPEED | 777 MII_AUX_CTRL_MISC); 778 break; 779 } 780 #endif /* BGE_COPPER_WIRESPEED */ 781 } 782 783 static boolean_t 784 bge_check_copper(bge_t *bgep, boolean_t recheck) 785 { 786 uint32_t emac_status; 787 uint16_t mii_status; 788 uint16_t aux; 789 uint_t mode; 790 boolean_t linkup; 791 792 /* 793 * Step 10: read the status from the PHY (which is self-clearing 794 * on read!); also read & clear the main (Ethernet) MAC status 795 * (the relevant bits of this are write-one-to-clear). 796 */ 797 mii_status = bge_mii_get16(bgep, MII_STATUS); 798 emac_status = bge_reg_get32(bgep, ETHERNET_MAC_STATUS_REG); 799 bge_reg_put32(bgep, ETHERNET_MAC_STATUS_REG, emac_status); 800 801 BGE_DEBUG(("bge_check_copper: link %d/%s, MII status 0x%x " 802 "(was 0x%x), Ethernet MAC status 0x%x", 803 bgep->link_state, UPORDOWN(bgep->param_link_up), mii_status, 804 bgep->phy_gen_status, emac_status)); 805 806 /* 807 * If the PHY status hasn't changed since last we looked, and 808 * we not forcing a recheck (i.e. the link state was already 809 * known), there's nothing to do. 810 */ 811 if (mii_status == bgep->phy_gen_status && !recheck) 812 return (B_FALSE); 813 814 do { 815 /* 816 * If the PHY status changed, record the time 817 */ 818 if (mii_status != bgep->phy_gen_status) 819 bgep->phys_event_time = gethrtime(); 820 821 /* 822 * Step 11: read AUX STATUS register to find speed/duplex 823 */ 824 aux = bge_mii_get16(bgep, MII_AUX_STATUS); 825 BGE_CDB(bge_phydump, (bgep, mii_status, aux)); 826 827 /* 828 * We will only consider the link UP if all the readings 829 * are consistent and give meaningful results ... 830 */ 831 mode = aux & MII_AUX_STATUS_MODE_MASK; 832 mode >>= MII_AUX_STATUS_MODE_SHIFT; 833 linkup = bge_copper_link_speed[mode] > 0; 834 linkup &= bge_copper_link_duplex[mode] != LINK_DUPLEX_UNKNOWN; 835 linkup &= BIS(aux, MII_AUX_STATUS_LINKUP); 836 linkup &= BIS(mii_status, MII_STATUS_LINKUP); 837 838 BGE_DEBUG(("bge_check_copper: MII status 0x%x aux 0x%x " 839 "=> mode %d (%s)", 840 mii_status, aux, 841 mode, UPORDOWN(linkup))); 842 843 /* 844 * Record current register values, then reread status 845 * register & loop until it stabilises ... 846 */ 847 bgep->phy_aux_status = aux; 848 bgep->phy_gen_status = mii_status; 849 mii_status = bge_mii_get16(bgep, MII_STATUS); 850 } while (mii_status != bgep->phy_gen_status); 851 852 /* 853 * Assume very little ... 854 */ 855 bgep->param_lp_autoneg = B_FALSE; 856 bgep->param_lp_1000fdx = B_FALSE; 857 bgep->param_lp_1000hdx = B_FALSE; 858 bgep->param_lp_100fdx = B_FALSE; 859 bgep->param_lp_100hdx = B_FALSE; 860 bgep->param_lp_10fdx = B_FALSE; 861 bgep->param_lp_10hdx = B_FALSE; 862 bgep->param_lp_pause = B_FALSE; 863 bgep->param_lp_asym_pause = B_FALSE; 864 bgep->param_link_autoneg = B_FALSE; 865 bgep->param_link_tx_pause = B_FALSE; 866 if (bgep->param_adv_autoneg) 867 bgep->param_link_rx_pause = B_FALSE; 868 else 869 bgep->param_link_rx_pause = bgep->param_adv_pause; 870 871 /* 872 * Discover all the link partner's abilities. 873 * These are scattered through various registters ... 874 */ 875 if (BIS(aux, MII_AUX_STATUS_LP_ANEG_ABLE)) { 876 bgep->param_lp_autoneg = B_TRUE; 877 bgep->param_link_autoneg = B_TRUE; 878 bgep->param_link_tx_pause = BIS(aux, MII_AUX_STATUS_TX_PAUSE); 879 bgep->param_link_rx_pause = BIS(aux, MII_AUX_STATUS_RX_PAUSE); 880 881 aux = bge_mii_get16(bgep, MII_1000BASE_T_STATUS); 882 bgep->param_lp_1000fdx = BIS(aux, MII_1000BT_STAT_LP_FDX_CAP); 883 bgep->param_lp_1000hdx = BIS(aux, MII_1000BT_STAT_LP_HDX_CAP); 884 885 aux = bge_mii_get16(bgep, MII_AN_LPABLE); 886 bgep->param_lp_100fdx = BIS(aux, MII_ABILITY_100BASE_TX_FD); 887 bgep->param_lp_100hdx = BIS(aux, MII_ABILITY_100BASE_TX); 888 bgep->param_lp_10fdx = BIS(aux, MII_ABILITY_10BASE_T_FD); 889 bgep->param_lp_10hdx = BIS(aux, MII_ABILITY_10BASE_T); 890 bgep->param_lp_pause = BIS(aux, MII_ABILITY_PAUSE); 891 bgep->param_lp_asym_pause = BIS(aux, MII_ABILITY_ASYM_PAUSE); 892 } 893 894 /* 895 * Step 12: update ndd-visible state parameters, BUT! 896 * we don't transfer the new state to <link_state> just yet; 897 * instead we mark the <link_state> as UNKNOWN, and our caller 898 * will resolve it once the status has stopped changing and 899 * been stable for several seconds. 900 */ 901 BGE_DEBUG(("bge_check_copper: link was %s speed %d duplex %d", 902 UPORDOWN(bgep->param_link_up), 903 bgep->param_link_speed, 904 bgep->param_link_duplex)); 905 906 if (!linkup) 907 mode = MII_AUX_STATUS_MODE_NONE; 908 bgep->param_link_up = linkup; 909 bgep->param_link_speed = bge_copper_link_speed[mode]; 910 bgep->param_link_duplex = bge_copper_link_duplex[mode]; 911 bgep->link_mode_msg = bge_copper_link_text[mode]; 912 bgep->link_state = LINK_STATE_UNKNOWN; 913 914 BGE_DEBUG(("bge_check_copper: link now %s speed %d duplex %d", 915 UPORDOWN(bgep->param_link_up), 916 bgep->param_link_speed, 917 bgep->param_link_duplex)); 918 919 return (B_TRUE); 920 } 921 922 static const phys_ops_t copper_ops = { 923 bge_restart_copper, 924 bge_update_copper, 925 bge_check_copper 926 }; 927 928 929 /* 930 * ========== SerDes support ========== 931 */ 932 933 #undef BGE_DBG 934 #define BGE_DBG BGE_DBG_SERDES /* debug flag for this code */ 935 936 /* 937 * Reinitialise the SerDes interface. Note that it normally powers 938 * up in the disabled state, so we need to explicitly activate it. 939 */ 940 static void 941 bge_restart_serdes(bge_t *bgep, boolean_t powerdown) 942 { 943 uint32_t macmode; 944 945 BGE_TRACE(("bge_restart_serdes($%p, %d)", (void *)bgep, powerdown)); 946 947 ASSERT(mutex_owned(bgep->genlock)); 948 949 /* 950 * Ensure that the main Ethernet MAC mode register is programmed 951 * appropriately for the SerDes interface ... 952 */ 953 macmode = bge_reg_get32(bgep, ETHERNET_MAC_MODE_REG); 954 macmode &= ~ETHERNET_MODE_LINK_POLARITY; 955 macmode &= ~ETHERNET_MODE_PORTMODE_MASK; 956 macmode |= ETHERNET_MODE_PORTMODE_TBI; 957 bge_reg_put32(bgep, ETHERNET_MAC_MODE_REG, macmode); 958 959 /* 960 * Ensure that loopback is OFF and comma detection is enabled. Then 961 * disable the SerDes output (the first time through, it may/will 962 * already be disabled). If we're shutting down, leave it disabled. 963 */ 964 bge_reg_clr32(bgep, SERDES_CONTROL_REG, SERDES_CONTROL_TBI_LOOPBACK); 965 bge_reg_set32(bgep, SERDES_CONTROL_REG, SERDES_CONTROL_COMMA_DETECT); 966 bge_reg_set32(bgep, SERDES_CONTROL_REG, SERDES_CONTROL_TX_DISABLE); 967 if (powerdown) 968 return; 969 970 /* 971 * Otherwise, pause, (re-)enable the SerDes output, and send 972 * all-zero config words in order to force autoneg restart. 973 * Invalidate the saved "link partners received configs", as 974 * we're starting over ... 975 */ 976 drv_usecwait(10000); 977 bge_reg_clr32(bgep, SERDES_CONTROL_REG, SERDES_CONTROL_TX_DISABLE); 978 bge_reg_put32(bgep, TX_1000BASEX_AUTONEG_REG, 0); 979 bge_reg_set32(bgep, ETHERNET_MAC_MODE_REG, ETHERNET_MODE_SEND_CFGS); 980 drv_usecwait(10); 981 bge_reg_clr32(bgep, ETHERNET_MAC_MODE_REG, ETHERNET_MODE_SEND_CFGS); 982 bgep->serdes_lpadv = AUTONEG_CODE_FAULT_ANEG_ERR; 983 bgep->serdes_status = ~0U; 984 } 985 986 /* 987 * Synchronise the SerDes speed/duplex/autonegotiation capabilities and 988 * advertisements with the required settings as specified by the various 989 * param_* variables that can be poked via the NDD interface. 990 * 991 * We always reinitalise the SerDes; this should cause the link to go down, 992 * and then back up again once the link is stable and autonegotiation 993 * (if enabled) is complete. We should get a link state change interrupt 994 * somewhere along the way ... 995 * 996 * NOTE: SerDes only supports 1000FDX/HDX (with or without pause) so the 997 * param_* variables relating to lower speeds are ignored. 998 * 999 * NOTE: <genlock> must already be held by the caller 1000 */ 1001 static void 1002 bge_update_serdes(bge_t *bgep) 1003 { 1004 boolean_t adv_autoneg; 1005 boolean_t adv_pause; 1006 boolean_t adv_asym_pause; 1007 boolean_t adv_1000fdx; 1008 boolean_t adv_1000hdx; 1009 1010 uint32_t serdes; 1011 uint32_t advert; 1012 1013 BGE_TRACE(("bge_update_serdes($%p)", (void *)bgep)); 1014 1015 ASSERT(mutex_owned(bgep->genlock)); 1016 1017 BGE_DEBUG(("bge_update_serdes: autoneg %d " 1018 "pause %d asym_pause %d " 1019 "1000fdx %d 1000hdx %d " 1020 "100fdx %d 100hdx %d " 1021 "10fdx %d 10hdx %d ", 1022 bgep->param_adv_autoneg, 1023 bgep->param_adv_pause, bgep->param_adv_asym_pause, 1024 bgep->param_adv_1000fdx, bgep->param_adv_1000hdx, 1025 bgep->param_adv_100fdx, bgep->param_adv_100hdx, 1026 bgep->param_adv_10fdx, bgep->param_adv_10hdx)); 1027 1028 serdes = advert = 0; 1029 1030 /* 1031 * SerDes settings are normally based on the param_* variables, 1032 * but if any loopback mode is in effect, that takes precedence. 1033 * 1034 * BGE supports MAC-internal loopback, PHY-internal loopback, 1035 * and External loopback at a variety of speeds (with a special 1036 * cable). In all cases, autoneg is turned OFF, full-duplex 1037 * is turned ON, and the speed/mastership is forced. 1038 * 1039 * Note: for the SerDes interface, "PHY" internal loopback is 1040 * interpreted as SerDes internal loopback, and all external 1041 * loopback modes are treated equivalently, as 1Gb/external. 1042 */ 1043 switch (bgep->param_loop_mode) { 1044 case BGE_LOOP_NONE: 1045 default: 1046 adv_autoneg = bgep->param_adv_autoneg; 1047 adv_pause = bgep->param_adv_pause; 1048 adv_asym_pause = bgep->param_adv_asym_pause; 1049 adv_1000fdx = bgep->param_adv_1000fdx; 1050 adv_1000hdx = bgep->param_adv_1000hdx; 1051 break; 1052 1053 case BGE_LOOP_INTERNAL_PHY: 1054 serdes |= SERDES_CONTROL_TBI_LOOPBACK; 1055 /* FALLTHRU */ 1056 case BGE_LOOP_INTERNAL_MAC: 1057 case BGE_LOOP_EXTERNAL_1000: 1058 case BGE_LOOP_EXTERNAL_100: 1059 case BGE_LOOP_EXTERNAL_10: 1060 adv_autoneg = adv_pause = adv_asym_pause = B_FALSE; 1061 adv_1000fdx = B_TRUE; 1062 adv_1000hdx = B_FALSE; 1063 break; 1064 } 1065 1066 BGE_DEBUG(("bge_update_serdes: autoneg %d " 1067 "pause %d asym_pause %d " 1068 "1000fdx %d 1000hdx %d ", 1069 adv_autoneg, 1070 adv_pause, adv_asym_pause, 1071 adv_1000fdx, adv_1000hdx)); 1072 1073 /* 1074 * We should have at least one gigabit technology capability 1075 * set; if not, we select a default of 1000Mb/s full-duplex 1076 */ 1077 if (!adv_1000fdx && !adv_1000hdx) 1078 adv_1000fdx = B_TRUE; 1079 1080 /* 1081 * Now transform the adv_* variables into the proper settings 1082 * of the SerDes registers ... 1083 * 1084 * If autonegotiation is (now) not enabled, pretend it's been 1085 * done and failed ... 1086 */ 1087 if (!adv_autoneg) 1088 advert |= AUTONEG_CODE_FAULT_ANEG_ERR; 1089 1090 if (adv_1000fdx) { 1091 advert |= AUTONEG_CODE_FULL_DUPLEX; 1092 bgep->param_adv_1000fdx = adv_1000fdx; 1093 bgep->param_link_duplex = LINK_DUPLEX_FULL; 1094 bgep->param_link_speed = 1000; 1095 } 1096 if (adv_1000hdx) { 1097 advert |= AUTONEG_CODE_HALF_DUPLEX; 1098 bgep->param_adv_1000hdx = adv_1000hdx; 1099 bgep->param_link_duplex = LINK_DUPLEX_HALF; 1100 bgep->param_link_speed = 1000; 1101 } 1102 1103 if (adv_pause) 1104 advert |= AUTONEG_CODE_PAUSE; 1105 if (adv_asym_pause) 1106 advert |= AUTONEG_CODE_ASYM_PAUSE; 1107 1108 /* 1109 * Restart the SerDes and write the new values. Note the 1110 * time, so that we can say whether subsequent link state 1111 * changes can be attributed to our reprogramming the SerDes 1112 */ 1113 bgep->serdes_advert = advert; 1114 bgep->phys_write_time = gethrtime(); 1115 bge_restart_serdes(bgep, B_FALSE); 1116 bge_reg_set32(bgep, SERDES_CONTROL_REG, serdes); 1117 1118 BGE_DEBUG(("bge_update_serdes: serdes |= 0x%x, advert 0x%x", 1119 serdes, advert)); 1120 } 1121 1122 /* 1123 * Bare-minimum autoneg protocol 1124 * 1125 * This code is only called when the link is up and we're receiving config 1126 * words, which implies that the link partner wants to autonegotiate 1127 * (otherwise, we wouldn't see configs and wouldn't reach this code). 1128 */ 1129 static void 1130 bge_autoneg_serdes(bge_t *bgep) 1131 { 1132 boolean_t ack; 1133 1134 bgep->serdes_lpadv = bge_reg_get32(bgep, RX_1000BASEX_AUTONEG_REG); 1135 ack = BIS(bgep->serdes_lpadv, AUTONEG_CODE_ACKNOWLEDGE); 1136 1137 if (!ack) { 1138 /* 1139 * Phase 1: after SerDes reset, we send a few zero configs 1140 * but then stop. Here the partner is sending configs, but 1141 * not ACKing ours; we assume that's 'cos we're not sending 1142 * any. So here we send ours, with ACK already set. 1143 */ 1144 bge_reg_put32(bgep, TX_1000BASEX_AUTONEG_REG, 1145 bgep->serdes_advert | AUTONEG_CODE_ACKNOWLEDGE); 1146 bge_reg_set32(bgep, ETHERNET_MAC_MODE_REG, 1147 ETHERNET_MODE_SEND_CFGS); 1148 } else { 1149 /* 1150 * Phase 2: partner has ACKed our configs, so now we can 1151 * stop sending; once our partner also stops sending, we 1152 * can resolve the Tx/Rx configs. 1153 */ 1154 bge_reg_clr32(bgep, ETHERNET_MAC_MODE_REG, 1155 ETHERNET_MODE_SEND_CFGS); 1156 } 1157 1158 BGE_DEBUG(("bge_autoneg_serdes: Rx 0x%x %s Tx 0x%x", 1159 bgep->serdes_lpadv, 1160 ack ? "stop" : "send", 1161 bgep->serdes_advert)); 1162 } 1163 1164 static boolean_t 1165 bge_check_serdes(bge_t *bgep, boolean_t recheck) 1166 { 1167 uint32_t emac_status; 1168 uint32_t lpadv; 1169 boolean_t linkup; 1170 1171 for (;;) { 1172 /* 1173 * Step 10: read & clear the main (Ethernet) MAC status 1174 * (the relevant bits of this are write-one-to-clear). 1175 */ 1176 emac_status = bge_reg_get32(bgep, ETHERNET_MAC_STATUS_REG); 1177 bge_reg_put32(bgep, ETHERNET_MAC_STATUS_REG, emac_status); 1178 1179 BGE_DEBUG(("bge_check_serdes: link %d/%s, " 1180 "MAC status 0x%x (was 0x%x)", 1181 bgep->link_state, UPORDOWN(bgep->param_link_up), 1182 emac_status, bgep->serdes_status)); 1183 1184 /* 1185 * We will only consider the link UP if all the readings 1186 * are consistent and give meaningful results ... 1187 */ 1188 bgep->serdes_status = emac_status; 1189 linkup = BIS(emac_status, ETHERNET_STATUS_SIGNAL_DETECT); 1190 linkup &= BIS(emac_status, ETHERNET_STATUS_PCS_SYNCHED); 1191 1192 /* 1193 * Now some fiddling with the interpretation: 1194 * if there's been an error at the PCS level, treat 1195 * it as a link change (the h/w doesn't do this) 1196 * 1197 * if there's been a change, but it's only a PCS sync 1198 * change (not a config change), AND the link already 1199 * was & is still UP, then ignore the change 1200 */ 1201 if (BIS(emac_status, ETHERNET_STATUS_PCS_ERROR)) 1202 emac_status |= ETHERNET_STATUS_LINK_CHANGED; 1203 else if (BIC(emac_status, ETHERNET_STATUS_CFG_CHANGED)) 1204 if (bgep->param_link_up && linkup) 1205 emac_status &= ~ETHERNET_STATUS_LINK_CHANGED; 1206 1207 BGE_DEBUG(("bge_check_serdes: status 0x%x => 0x%x %s", 1208 bgep->serdes_status, emac_status, UPORDOWN(linkup))); 1209 1210 /* 1211 * If we're receiving configs, run the autoneg protocol 1212 */ 1213 if (linkup && BIS(emac_status, ETHERNET_STATUS_RECEIVING_CFG)) 1214 bge_autoneg_serdes(bgep); 1215 1216 /* 1217 * If the SerDes status hasn't changed, we're done ... 1218 */ 1219 if (BIC(emac_status, ETHERNET_STATUS_LINK_CHANGED)) 1220 break; 1221 1222 /* 1223 * Record when the SerDes status changed, then go 1224 * round again until we no longer see a change ... 1225 */ 1226 bgep->phys_event_time = gethrtime(); 1227 recheck = B_TRUE; 1228 } 1229 1230 /* 1231 * If we're not forcing a recheck (i.e. the link state was already 1232 * known), and we didn't see the hardware flag a change, there's 1233 * no more to do (and we tell the caller nothing happened). 1234 */ 1235 if (!recheck) 1236 return (B_FALSE); 1237 1238 /* 1239 * Don't resolve autoneg until we're no longer receiving configs 1240 */ 1241 if (linkup && BIS(emac_status, ETHERNET_STATUS_RECEIVING_CFG)) 1242 return (B_FALSE); 1243 1244 /* 1245 * Assume very little ... 1246 */ 1247 bgep->param_lp_autoneg = B_FALSE; 1248 bgep->param_lp_1000fdx = B_FALSE; 1249 bgep->param_lp_1000hdx = B_FALSE; 1250 bgep->param_lp_100fdx = B_FALSE; 1251 bgep->param_lp_100hdx = B_FALSE; 1252 bgep->param_lp_10fdx = B_FALSE; 1253 bgep->param_lp_10hdx = B_FALSE; 1254 bgep->param_lp_pause = B_FALSE; 1255 bgep->param_lp_asym_pause = B_FALSE; 1256 bgep->param_link_autoneg = B_FALSE; 1257 bgep->param_link_tx_pause = B_FALSE; 1258 if (bgep->param_adv_autoneg) 1259 bgep->param_link_rx_pause = B_FALSE; 1260 else 1261 bgep->param_link_rx_pause = bgep->param_adv_pause; 1262 1263 /* 1264 * Discover all the link partner's abilities. 1265 */ 1266 lpadv = bgep->serdes_lpadv; 1267 if (lpadv != 0 && BIC(lpadv, AUTONEG_CODE_FAULT_MASK)) { 1268 /* 1269 * No fault, so derive partner's capabilities 1270 */ 1271 bgep->param_lp_autoneg = B_TRUE; 1272 bgep->param_lp_1000fdx = BIS(lpadv, AUTONEG_CODE_FULL_DUPLEX); 1273 bgep->param_lp_1000hdx = BIS(lpadv, AUTONEG_CODE_HALF_DUPLEX); 1274 bgep->param_lp_pause = BIS(lpadv, AUTONEG_CODE_PAUSE); 1275 bgep->param_lp_asym_pause = BIS(lpadv, AUTONEG_CODE_ASYM_PAUSE); 1276 1277 /* 1278 * Pause direction resolution 1279 */ 1280 bgep->param_link_autoneg = B_TRUE; 1281 if (bgep->param_adv_pause && 1282 bgep->param_lp_pause) { 1283 bgep->param_link_tx_pause = B_TRUE; 1284 bgep->param_link_rx_pause = B_TRUE; 1285 } 1286 if (bgep->param_adv_asym_pause && 1287 bgep->param_lp_asym_pause) { 1288 if (bgep->param_adv_pause) 1289 bgep->param_link_rx_pause = B_TRUE; 1290 if (bgep->param_lp_pause) 1291 bgep->param_link_tx_pause = B_TRUE; 1292 } 1293 } 1294 1295 /* 1296 * Step 12: update ndd-visible state parameters, BUT! 1297 * we don't transfer the new state to <link_state> just yet; 1298 * instead we mark the <link_state> as UNKNOWN, and our caller 1299 * will resolve it once the status has stopped changing and 1300 * been stable for several seconds. 1301 */ 1302 BGE_DEBUG(("bge_check_serdes: link was %s speed %d duplex %d", 1303 UPORDOWN(bgep->param_link_up), 1304 bgep->param_link_speed, 1305 bgep->param_link_duplex)); 1306 1307 if (linkup) { 1308 bgep->param_link_up = B_TRUE; 1309 bgep->param_link_speed = 1000; 1310 if (bgep->param_adv_1000fdx) 1311 bgep->param_link_duplex = LINK_DUPLEX_FULL; 1312 else 1313 bgep->param_link_duplex = LINK_DUPLEX_HALF; 1314 if (bgep->param_lp_autoneg && !bgep->param_lp_1000fdx) 1315 bgep->param_link_duplex = LINK_DUPLEX_HALF; 1316 } else { 1317 bgep->param_link_up = B_FALSE; 1318 bgep->param_link_speed = 0; 1319 bgep->param_link_duplex = LINK_DUPLEX_UNKNOWN; 1320 } 1321 switch (bgep->param_link_duplex) { 1322 default: 1323 case LINK_DUPLEX_UNKNOWN: 1324 bgep->link_mode_msg = "down"; 1325 break; 1326 1327 case LINK_DUPLEX_HALF: 1328 bgep->link_mode_msg = "up 1000Mbps Half-Duplex"; 1329 break; 1330 1331 case LINK_DUPLEX_FULL: 1332 bgep->link_mode_msg = "up 1000Mbps Full-Duplex"; 1333 break; 1334 } 1335 bgep->link_state = LINK_STATE_UNKNOWN; 1336 1337 BGE_DEBUG(("bge_check_serdes: link now %s speed %d duplex %d", 1338 UPORDOWN(bgep->param_link_up), 1339 bgep->param_link_speed, 1340 bgep->param_link_duplex)); 1341 1342 return (B_TRUE); 1343 } 1344 1345 static const phys_ops_t serdes_ops = { 1346 bge_restart_serdes, 1347 bge_update_serdes, 1348 bge_check_serdes 1349 }; 1350 1351 /* 1352 * ========== Exported physical layer control routines ========== 1353 */ 1354 1355 #undef BGE_DBG 1356 #define BGE_DBG BGE_DBG_PHYS /* debug flag for this code */ 1357 1358 /* 1359 * Here we have to determine which media we're using (copper or serdes). 1360 * Once that's done, we can initialise the physical layer appropriately. 1361 */ 1362 void 1363 bge_phys_init(bge_t *bgep) 1364 { 1365 BGE_TRACE(("bge_phys_init($%p)", (void *)bgep)); 1366 1367 mutex_enter(bgep->genlock); 1368 1369 /* 1370 * Probe for the (internal) PHY. If it's not there, we'll assume 1371 * that this is a 5703/4S, with a SerDes interface rather than 1372 * a PHY. BCM5714S/BCM5715S are not supported.It are based on 1373 * BCM800x PHY. 1374 */ 1375 bgep->phy_mii_addr = 1; 1376 if (bge_phy_probe(bgep)) { 1377 bgep->chipid.flags &= ~CHIP_FLAG_SERDES; 1378 bgep->phys_delta_time = BGE_PHY_STABLE_TIME; 1379 bgep->physops = &copper_ops; 1380 } else { 1381 bgep->chipid.flags |= CHIP_FLAG_SERDES; 1382 bgep->phys_delta_time = BGE_SERDES_STABLE_TIME; 1383 bgep->physops = &serdes_ops; 1384 } 1385 1386 (*bgep->physops->phys_restart)(bgep, B_FALSE); 1387 mutex_exit(bgep->genlock); 1388 } 1389 1390 /* 1391 * Reset the physical layer 1392 */ 1393 void 1394 bge_phys_reset(bge_t *bgep) 1395 { 1396 BGE_TRACE(("bge_phys_reset($%p)", (void *)bgep)); 1397 1398 mutex_enter(bgep->genlock); 1399 (*bgep->physops->phys_restart)(bgep, B_FALSE); 1400 mutex_exit(bgep->genlock); 1401 } 1402 1403 /* 1404 * Reset and power off the physical layer. 1405 * 1406 * Another RESET should get it back to working, but it may take a few 1407 * seconds it may take a few moments to return to normal operation ... 1408 */ 1409 void 1410 bge_phys_idle(bge_t *bgep) 1411 { 1412 BGE_TRACE(("bge_phys_idle($%p)", (void *)bgep)); 1413 1414 ASSERT(mutex_owned(bgep->genlock)); 1415 (*bgep->physops->phys_restart)(bgep, B_TRUE); 1416 } 1417 1418 /* 1419 * Synchronise the PHYSICAL layer's speed/duplex/autonegotiation capabilities 1420 * and advertisements with the required settings as specified by the various 1421 * param_* variables that can be poked via the NDD interface. 1422 * 1423 * We always reset the PHYSICAL layer and reprogram *all* relevant registers. 1424 * This is expected to cause the link to go down, and then back up again once 1425 * the link is stable and autonegotiation (if enabled) is complete. We should 1426 * get a link state change interrupt somewhere along the way ... 1427 * 1428 * NOTE: <genlock> must already be held by the caller 1429 */ 1430 void 1431 bge_phys_update(bge_t *bgep) 1432 { 1433 BGE_TRACE(("bge_phys_update($%p)", (void *)bgep)); 1434 1435 ASSERT(mutex_owned(bgep->genlock)); 1436 (*bgep->physops->phys_update)(bgep); 1437 } 1438 1439 #undef BGE_DBG 1440 #define BGE_DBG BGE_DBG_LINK /* debug flag for this code */ 1441 1442 /* 1443 * Read the link status and determine whether anything's changed ... 1444 * 1445 * This routine should be called whenever the chip flags a change 1446 * in the hardware link state, and repeatedly for several seconds 1447 * afterwards, until we're sure the state has stabilised (sometimes 1448 * it goes up and down several times during autonegotiation before 1449 * settling on the proper configuration). This routine applies 1450 * timing-based heuristics to determine when the state is stable. 1451 * 1452 * This routine returns B_FALSE if the link state has not changed, 1453 * or if it has changed, but hasn't settled for long enough yet. It 1454 * returns B_TRUE when the change to the new state should be accepted. 1455 * In such a case, the param_* variables give the new hardware state, 1456 * which the caller should use to update link_state etc. 1457 * 1458 * The caller must already hold <genlock> 1459 */ 1460 boolean_t 1461 bge_phys_check(bge_t *bgep) 1462 { 1463 int32_t orig_state; 1464 boolean_t recheck; 1465 boolean_t linkup; 1466 hrtime_t deltat; 1467 hrtime_t now; 1468 1469 BGE_TRACE(("bge_phys_check($%p)", (void *)bgep)); 1470 1471 ASSERT(mutex_owned(bgep->genlock)); 1472 1473 linkup = bgep->param_link_up; 1474 orig_state = bgep->link_state; 1475 recheck = orig_state == LINK_STATE_UNKNOWN; 1476 recheck = (*bgep->physops->phys_check)(bgep, recheck); 1477 if (!recheck) 1478 return (B_FALSE); 1479 1480 /* 1481 * At this point, the check_*_link() function above has detected 1482 * a change and updated the param_* variables to show what the 1483 * latest hardware state seems to be -- but it might still be 1484 * changing. 1485 * 1486 * The link_state must now be UNKNOWN, but if it was previously 1487 * UP, we want to recognise this immediately, whereas in any other 1488 * case (e.g. DOWN->UP) we don't accept it until a few seconds have 1489 * elapsed, to give the hardware time to settle. 1490 */ 1491 now = gethrtime(); 1492 deltat = now - bgep->phys_event_time; 1493 1494 BGE_DEBUG(("bge_phys_check: link was %d/%s now %d/%s", 1495 orig_state, UPORDOWN(linkup), 1496 bgep->link_state, UPORDOWN(bgep->param_link_up))); 1497 BGE_DEBUG(("bge_phys_check: update %lld change %lld " 1498 "now %lld delta %lld", 1499 bgep->phys_write_time, bgep->phys_event_time, now, deltat)); 1500 1501 if (orig_state == LINK_STATE_UP) 1502 return (B_TRUE); 1503 else 1504 return (deltat > bgep->phys_delta_time); 1505 } 1506