1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License (the "License"). 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9 * or http://www.opensolaris.org/os/licensing. 10 * See the License for the specific language governing permissions 11 * and limitations under the License. 12 * 13 * When distributing Covered Code, include this CDDL HEADER in each 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15 * If applicable, add the following below this CDDL HEADER, with the 16 * fields enclosed by brackets "[]" replaced with your own identifying 17 * information: Portions Copyright [yyyy] [name of copyright owner] 18 * 19 * CDDL HEADER END 20 */ 21 22 /* 23 * Copyright 2009 QLogic Corporation. All rights reserved. 24 * Use is subject to license terms. 25 */ 26 27 /* 28 * Copyright 2008 Sun Microsystems, Inc. All rights reserved. 29 * Use is subject to license terms. 30 */ 31 32 #ifndef _QLT_REGS_H 33 #define _QLT_REGS_H 34 35 #include <stmf_defines.h> 36 37 #ifdef __cplusplus 38 extern "C" { 39 #endif 40 41 /* 42 * Register offsets 43 */ 44 #define REG_FLASH_ADDR 0x00 45 #define REG_FLASH_DATA 0x04 46 #define REG_CTRL_STATUS 0x08 47 #define REG_INTR_CTRL 0x0C 48 #define REG_INTR_STATUS 0x10 49 #define REG_REQ_IN_PTR 0x1C 50 #define REG_REQ_OUT_PTR 0x20 51 #define REG_RESP_IN_PTR 0x24 52 #define REG_RESP_OUT_PTR 0x28 53 #define REG_PREQ_IN_PTR 0x2C 54 #define REG_PREQ_OUT_PTR 0x30 55 #define REG_ATIO_IN_PTR 0x3C 56 #define REG_ATIO_OUT_PTR 0x40 57 #define REG_RISC_STATUS 0x44 58 #define REG_HCCR 0x48 59 #define REG_GPIO_DATA 0x4C 60 #define REG_GPIO_ENABLE 0x50 61 #define REG_IOBUS_BASE_ADDR 0x54 62 #define REG_HOST_SEMA 0x58 63 #define REG_MBOX0 0x80 64 65 #define REG_MBOX(n) (REG_MBOX0 + (n << 1)) 66 67 #define MAX_MBOXES 32 68 69 /* 70 * Ctrl Status register definitions 71 */ 72 #define FLASH_ERROR BIT_18 73 #define DMA_ACTIVE_STATUS BIT_17 74 #define DMA_SHUTDOWN_CTRL BIT_16 75 #define FUNCTION_NUMBER BIT_15 76 /* 77 * #define 81XX_FUNCTION_NUMBER BIT_15 | BIT_14 | BIT_13 | BIT_12 78 */ 79 #define PCI_X_BUS_MODE (BIT_8 | BIT_9 | BIT_10 | BIT_11) 80 #define PCI_X_XFER_CTRL (BIT_4 | BIT_5) 81 #define PCI_64_BIT_SLOT BIT_2 82 #define FLASH_WRITE_ENABLE BIT_1 83 #define CHIP_SOFT_RESET BIT_0 84 85 /* 86 * INTR_CTRL register 87 */ 88 #define ENABLE_RISC_INTR BIT_3 89 90 /* 91 * INTR_STATUS register 92 */ 93 #define RISC_INTR_REQUEST BIT_3 94 95 /* 96 * RISC_STATUS register 97 */ 98 #define RISC_HOST_INTR_REQUEST BIT_15 99 #define RISC_PAUSED BIT_08 100 #define FW_INTR_STATUS_MASK (BIT_7 | BIT_6 | BIT_5 | BIT_4 | \ 101 BIT_3 | BIT_2 | BIT_1 | BIT_0) 102 103 /* 104 * HCCR commands 105 */ 106 #define HCCR_CMD_NOP 0 107 #define HCCR_CMD_SET_RISC_RESET 0x10000000 108 #define HCCR_CMD_CLEAR_RISC_RESET 0x20000000 109 #define HCCR_CMD_SET_RISC_PAUSE 0x30000000 110 #define HCCR_CMD_CLEAR_RISC_PAUSE 0x40000000 111 #define HCCR_CMD_SET_HOST_TO_RISC_INTR 0x50000000 112 #define HCCR_CMD_CLEAR_HOST_TO_RISC_INTR 0x60000000 113 #define HCCR_CMD_CLEAR_RISC_TO_PCI_INTR 0xA0000000 114 115 #define MBC_STOP_FIRMWARE 0x14 116 117 /* 118 * Flash/NVRAM definitions 119 */ 120 #define FLASH_DATA_FLAG BIT_31 121 #define FLASH_CONF_ADDR 0x7FFD0000 122 #define FLASH_DATA_ADDR 0x7FF00000 123 #define FLASH_DATA_ADDR_81XX 0x7F8D0000 124 #define NVRAM_CONF_ADDR 0x7FFF0000 125 #define NVRAM_DATA_ADDR 0x7FFE0000 126 127 #define NVRAM_FUNC0_ADDR (NVRAM_DATA_ADDR + 0x80) 128 #define NVRAM_FUNC1_ADDR (NVRAM_DATA_ADDR + 0x180) 129 130 #define QLT25_NVRAM_FUNC0_ADDR (FLASH_DATA_ADDR + 0x48080) 131 #define QLT25_NVRAM_FUNC1_ADDR (FLASH_DATA_ADDR + 0x48180) 132 133 #define QLT81_NVRAM_FUNC0_ADDR (FLASH_DATA_ADDR_81XX + 0x80) 134 #define QLT81_NVRAM_FUNC1_ADDR (FLASH_DATA_ADDR_81XX + 0x180) 135 136 typedef struct qlt_nvram { 137 /* NVRAM header. */ 138 uint8_t id[4]; 139 uint8_t nvram_version[2]; 140 uint8_t reserved_0[2]; 141 142 /* Firmware Initialization Control Block. */ 143 uint8_t version[2]; 144 uint8_t reserved_1[2]; 145 uint8_t max_frame_length[2]; 146 uint8_t execution_throttle[2]; 147 uint8_t exchange_count[2]; 148 uint8_t hard_address[2]; 149 uint8_t port_name[8]; 150 uint8_t node_name[8]; 151 uint8_t login_retry_count[2]; 152 uint8_t link_down_on_nos[2]; 153 uint8_t interrupt_delay_timer[2]; 154 uint8_t login_timeout[2]; 155 156 /* 157 * BIT 0 = Hard Assigned Loop ID 158 * BIT 1 = Enable Fairness 159 * BIT 2 = Enable Full-Duplex 160 * BIT 3 = Reserved 161 * BIT 4 = Target Mode Enable 162 * BIT 5 = Initiator Mode Disable 163 * BIT 6 = Reserved 164 * BIT 7 = Reserved 165 * 166 * BIT 8 = Reserved 167 * BIT 9 = Disable Initial LIP 168 * BIT 10 = Descending Loop ID Search 169 * BIT 11 = Previous Assigned Loop ID 170 * BIT 12 = Reserved 171 * BIT 13 = Full Login after LIP 172 * BIT 14 = Node Name Option 173 * BIT 15-31 = Reserved 174 */ 175 uint8_t firmware_options_1[4]; 176 177 /* 178 * BIT 0 = Operation Mode bit 0 179 * BIT 1 = Operation Mode bit 1 180 * BIT 2 = Operation Mode bit 2 181 * BIT 3 = Operation Mode bit 3 182 * BIT 4 = Connection Options bit 0 183 * BIT 5 = Connection Options bit 1 184 * BIT 6 = Connection Options bit 2 185 * BIT 7 = Enable Non part on LIHA failure 186 * 187 * BIT 8 = Enable Class 2 188 * BIT 9 = Enable ACK0 189 * BIT 10 = Reserved 190 * BIT 11 = Enable FC-SP Security 191 * BIT 12 = FC Tape Enable 192 * BIT 13-31 = Reserved 193 */ 194 uint8_t firmware_options_2[4]; 195 196 /* 197 * BIT 0 = Reserved 198 * BIT 1 = Soft ID only 199 * BIT 2 = Reserved 200 * BIT 3 = Reserved 201 * BIT 4 = FCP RSP Payload bit 0 202 * BIT 5 = FCP RSP Payload bit 1 203 * BIT 6 = Enable Rec Out-of-Order data frame handling 204 * BIT 7 = Disable Automatic PLOGI on Local Loop 205 * 206 * BIT 8 = Reserved 207 * BIT 9 = Enable Out-of-Order FCP_XFER_RDY relative 208 * offset handling 209 * BIT 10 = Reserved 210 * BIT 11 = Reserved 211 * BIT 12 = Reserved 212 * BIT 13 = Data Rate bit 0 213 * BIT 14 = Data Rate bit 1 214 * BIT 15 = Data Rate bit 2 215 * BIT 16 = 75-ohm Termination Select 216 * BIT 17-31 = Reserved 217 */ 218 uint8_t firmware_options_3[4]; 219 220 /* 221 * Serial Link Control (offset 56) 222 * BIT 0 = control enable 223 * BIT 1-15 = Reserved 224 */ 225 uint8_t swing_opt[2]; 226 227 /* 228 * Serial Link Control 1G (offset 58) 229 * BIT 0-7 = Reserved 230 * 231 * BIT 8-10 = output swing 232 * BIT 11-13 = output emphasis 233 * BIT 14-15 = Reserved 234 */ 235 uint8_t swing_1g[2]; 236 237 /* 238 * Serial Link Control 2G (offset 60) 239 * BIT 0-7 = Reserved 240 * 241 * BIT 8-10 = output swing 242 * BIT 11-13 = output emphasis 243 * BIT 14-15 = Reserved 244 */ 245 uint8_t swing_2g[2]; 246 247 /* 248 * Serial Link Control 4G (offset 62) 249 * BIT 0-7 = Reserved 250 * 251 * BIT 8-10 = output swing 252 * BIT 11-13 = output emphasis 253 * BIT 14-15 = Reserved 254 */ 255 uint8_t swing_4g[2]; 256 257 /* Offset 64. */ 258 uint8_t reserved_2[32]; 259 260 /* Offset 96. */ 261 uint8_t reserved_3[32]; 262 263 /* PCIe table entries. */ 264 uint8_t reserved_4[32]; 265 266 /* Offset 160. */ 267 uint8_t reserved_5[32]; 268 269 /* Offset 192. */ 270 uint8_t reserved_6[32]; 271 272 /* Offset 224. */ 273 uint8_t reserved_7[32]; 274 275 /* 276 * BIT 0 = Enable spinup delay 277 * BIT 1 = Disable BIOS 278 * BIT 2 = Enable Memory Map BIOS 279 * BIT 3 = Enable Selectable Boot 280 * BIT 4 = Disable RISC code load 281 * BIT 5 = Disable serdes 282 * BIT 6 = Enable opt boot mode 283 * BIT 7 = Enable int mode BIOS 284 * 285 * BIT 8 = 286 * BIT 9 = 287 * BIT 10 = Enable lip full login 288 * BIT 11 = Enable target reset 289 * BIT 12 = 290 * BIT 13 = Default Node Name Option 291 * BIT 14 = Default valid 292 * BIT 15 = Enable alternate WWN 293 * 294 * BIT 16-31 = 295 */ 296 uint8_t host_p[4]; 297 298 uint8_t alternate_port_name[8]; 299 uint8_t alternate_node_name[8]; 300 301 uint8_t boot_port_name[8]; 302 uint8_t boot_lun_number[2]; 303 uint8_t reserved_8[2]; 304 305 uint8_t alt1_boot_port_name[8]; 306 uint8_t alt1_boot_lun_number[2]; 307 uint8_t reserved_9[2]; 308 309 uint8_t alt2_boot_port_name[8]; 310 uint8_t alt2_boot_lun_number[2]; 311 uint8_t reserved_10[2]; 312 313 uint8_t alt3_boot_port_name[8]; 314 uint8_t alt3_boot_lun_number[2]; 315 uint8_t reserved_11[2]; 316 317 /* 318 * BIT 0 = Selective Login 319 * BIT 1 = Alt-Boot Enable 320 * BIT 2 = Reserved 321 * BIT 3 = Enable Boot Order List 322 * BIT 4 = Reserved 323 * BIT 5 = Enable Selective LUN 324 * BIT 6 = Reserved 325 * BIT 7-31 = 326 */ 327 uint8_t efi_parameters[4]; 328 329 uint8_t reset_delay; 330 uint8_t reserved_12; 331 uint8_t reserved_13[2]; 332 333 uint8_t boot_id_number[2]; 334 uint8_t reserved_14[2]; 335 336 uint8_t max_luns_per_target[2]; 337 uint8_t reserved_15[2]; 338 339 uint8_t port_down_retry_count[2]; 340 uint8_t link_down_timeout[2]; 341 342 /* 343 * FCode parameters word (offset 344) 344 * 345 * BIT 0 = Enable BIOS pathname 346 * BIT 1 = fcode qlc 347 * BIT 2 = fcode host 348 * BIT 3-7 = 349 */ 350 uint8_t fcode_p0; 351 uint8_t reserved_16[7]; 352 353 /* Offset 352. */ 354 uint8_t prev_drv_ver_major; 355 uint8_t prev_drv_ver_submajob; 356 uint8_t prev_drv_ver_minor; 357 uint8_t prev_drv_ver_subminor; 358 359 uint8_t prev_bios_ver_major[2]; 360 uint8_t prev_bios_ver_minor[2]; 361 362 uint8_t prev_efi_ver_major[2]; 363 uint8_t prev_efi_ver_minor[2]; 364 365 uint8_t prev_fw_ver_major[2]; 366 uint8_t prev_fw_ver_minor; 367 uint8_t prev_fw_ver_subminor; 368 369 uint8_t reserved_17[16]; 370 371 /* Offset 384. */ 372 uint8_t def_port_name[8]; 373 uint8_t def_node_name[8]; 374 375 uint8_t reserved_18[16]; 376 377 /* Offset 416. */ 378 uint8_t reserved_19[32]; 379 380 /* Offset 448. */ 381 uint8_t reserved_20[28]; 382 383 /* Offset 476. */ 384 uint8_t fw_table_offset[2]; 385 uint8_t fw_table_sig[2]; 386 387 /* Offset 480. */ 388 uint8_t model_name[8]; 389 390 /* Offset 488. */ 391 uint8_t power_table[16]; 392 393 uint8_t subsystem_vendor_id[2]; 394 uint8_t subsystem_device_id[2]; 395 396 uint8_t checksum[4]; 397 } qlt_nvram_t; 398 399 /* ISP81xx Extended Initialisation Control Block */ 400 typedef struct qlt_ext_icb_81xx { 401 402 uint8_t version[2]; 403 uint8_t fcf_vlan_match; 404 uint8_t reserved_6[3]; 405 uint8_t fcf_vlan_id[2]; 406 uint8_t fcf_fabric_name[8]; 407 uint8_t reserved_7[14]; 408 uint8_t spma_proposed_mac_address[6]; 409 uint8_t reserved_8[28]; 410 411 } qlt_ext_icb_81xx_t; 412 413 typedef struct qlt_nvram_81xx { 414 /* NVRAM header. */ 415 uint8_t id[4]; 416 uint8_t nvram_version[2]; 417 uint8_t reserved_0[2]; 418 419 /* Firmware Initialization Control Block. */ 420 uint8_t version[2]; 421 uint8_t reserved_1[2]; 422 uint8_t max_frame_length[2]; 423 uint8_t execution_throttle[2]; 424 uint8_t exchange_count[2]; 425 uint8_t reserved_2[2]; 426 uint8_t port_name[8]; 427 uint8_t node_name[8]; 428 uint8_t login_retry_count[2]; 429 uint8_t reserved_3[2]; 430 uint8_t interrupt_delay_timer[2]; 431 uint8_t login_timeout[2]; 432 433 /* 434 * BIT 0 = Hard Assigned Loop ID 435 * BIT 1 = Enable Fairness 436 * BIT 2 = Enable Full-Duplex 437 * BIT 3 = Reserved 438 * BIT 4 = Target Mode Enable 439 * BIT 5 = Initiator Mode Disable 440 * BIT 6 = Reserved 441 * BIT 7 = Reserved 442 * 443 * BIT 8 = Reserved 444 * BIT 9 = Reserved 445 * BIT 10 = Reserved 446 * BIT 11 = Reserved 447 * BIT 12 = Reserved 448 * BIT 13 = Reserved 449 * BIT 14 = Node Name Option 450 * BIT 15-31 = Reserved 451 */ 452 uint8_t firmware_options_1[4]; 453 454 /* 455 * BIT 0 = Operation Mode bit 0 456 * BIT 1 = Operation Mode bit 1 457 * BIT 2 = Operation Mode bit 2 458 * BIT 3 = Operation Mode bit 3 459 * BIT 4 = Reserved 460 * BIT 5 = Reserved 461 * BIT 6 = Reserved 462 * BIT 7 = Reserved 463 * 464 * BIT 8 = Enable Class 2 465 * BIT 9 = Enable ACK0 466 * BIT 10 = Reserved 467 * BIT 11 = Enable FC-SP Security 468 * BIT 12 = FC Tape Enable 469 * BIT 13 = Reserved 470 * BIT 14 = Target PRLI Control 471 * BIT 15-31 = Reserved 472 */ 473 uint8_t firmware_options_2[4]; 474 475 /* 476 * BIT 0 = Reserved 477 * BIT 1 = Soft ID only 478 * BIT 2 = Reserved 479 * BIT 3 = Reserved 480 * BIT 4 = FCP RSP Payload bit 0 481 * BIT 5 = FCP RSP Payload bit 1 482 * BIT 6 = Enable Rec Out-of-Order data frame handling 483 * BIT 7 = Reserved 484 * 485 * BIT 8 = Reserved 486 * BIT 9 = Enable Out-of-Order FCP_XFER_RDY relative 487 * offset handling 488 * BIT 10 = Reserved 489 * BIT 11 = Reserved 490 * BIT 12 = Reserved 491 * BIT 13 = Reserved 492 * BIT 14 = Reserved 493 * BIT 15 = Reserved 494 * BIT 16 = Reserved 495 * BIT 17 = Enable Multiple FCFs 496 * BIT 18-20 = MAC Addressing Mode 497 * BIT 21-25 = Ethernet Data Rate 498 * BIT 26 = Enable Ethernet Header Receive ATIO_Q 499 * BIT 27 = Enable Ethernet Header Receive RSP_Q 500 * BIT 28-29 = SPMA Selection 501 * BIT 30-31 = Reserved 502 */ 503 uint8_t firmware_options_3[4]; 504 505 /* Offset 56 (38h). */ 506 uint8_t reserved_4[8]; 507 508 /* Offset 64 (40h). */ 509 uint8_t enode_mac[6]; 510 511 /* Offset 70 (46h). */ 512 uint8_t reserved_5[26]; 513 514 /* Offset 96 (60h). */ 515 uint8_t oem_specific; 516 uint8_t reserved_6[15]; 517 518 /* Offset 112 (70h). */ 519 uint8_t reserved_7[16]; 520 521 /* Offset 128 (80h). */ 522 qlt_ext_icb_81xx_t ext_blk; 523 524 /* Offset 192. */ 525 uint8_t reserved_8[32]; 526 527 /* Offset 224. */ 528 uint8_t reserved_9[32]; 529 530 uint8_t host_p[4]; 531 532 uint8_t alternate_port_name[8]; 533 uint8_t alternate_name_name[8]; 534 535 uint8_t boot_port_name[8]; 536 uint8_t boot_lun_number[2]; 537 uint8_t reserved_10[2]; 538 539 uint8_t alt1_boot_port_name[8]; 540 uint8_t alt1_boot_lun_number[2]; 541 uint8_t reserved_11[2]; 542 543 uint8_t alt2_boot_port_name[8]; 544 uint8_t alt2_boot_lun_number[2]; 545 uint8_t reserved_12[2]; 546 547 uint8_t alt3_boot_port_name[8]; 548 uint8_t alt3_boot_lun_number[2]; 549 uint8_t reserved_13[2]; 550 551 /* 552 * BIT 0 = Selective Login 553 * BIT 1 = Alt-Boot Enable 554 * BIT 2 = Reserved 555 * BIT 3 = Enable Boot Order List 556 * BIT 4 = Reserved 557 * BIT 5 = Enable Selective LUN 558 * BIT 6 = Reserved 559 * BIT 7-31 = 560 */ 561 uint8_t efi_parameters[4]; 562 563 uint8_t reset_delay; 564 uint8_t reserved_14; 565 uint8_t reserved_15[2]; 566 567 uint8_t boot_id_number[2]; 568 uint8_t reserved_16[2]; 569 570 uint8_t max_luns_per_target[2]; 571 uint8_t reserved_17[2]; 572 573 uint8_t port_down_retry_count[2]; 574 uint8_t link_down_timeout[2]; 575 576 /* 577 * FCode parameters word (offset 344) 578 * 579 * BIT 0 = Enable BIOS pathname 580 * BIT 1 = fcode qlc 581 * BIT 2 = fcode host 582 * BIT 3-7 = 583 */ 584 uint8_t fcode_parameter[2]; 585 uint8_t reserved_18[6]; 586 587 /* Offset 352. */ 588 uint8_t reserved_19[4]; 589 uint8_t reserved_20[10]; 590 uint8_t reserved_21[2]; 591 uint8_t reserved_22[16]; 592 593 /* Offset 384. */ 594 uint8_t reserved_23[16]; 595 uint8_t reserved_24[16]; 596 597 /* Offset 416. */ 598 uint8_t reserved_25[64]; 599 600 /* Offset 480. */ 601 uint8_t model_name[16]; 602 603 /* Offset 496. */ 604 uint8_t feature_mask_l[2]; 605 uint8_t feature_mask_h[2]; 606 uint8_t reserved_26[4]; 607 608 uint8_t subsystem_vendor_id[2]; 609 uint8_t subsystem_device_id[2]; 610 611 uint8_t checksum[4]; 612 613 } qlt_nvram_81xx_t; 614 615 #ifdef __cplusplus 616 } 617 #endif 618 619 #endif /* _QLT_REGS_H */ 620