1 /* 2 * This file and its contents are supplied under the terms of the 3 * Common Development and Distribution License ("CDDL"), version 1.0. 4 * You may only use this file in accordance with the terms of version 5 * 1.0 of the CDDL. 6 * 7 * A full copy of the text of the CDDL should have accompanied this 8 * source. A copy of the CDDL is also available via the Internet at 9 * http://www.illumos.org/license/CDDL. 10 */ 11 12 /* 13 * This file is part of the Chelsio T4 support code. 14 * 15 * Copyright (C) 2003-2013 Chelsio Communications. All rights reserved. 16 * 17 * This program is distributed in the hope that it will be useful, but WITHOUT 18 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 19 * FITNESS FOR A PARTICULAR PURPOSE. See the LICENSE file included in this 20 * release for licensing terms and conditions. 21 */ 22 23 #ifndef __T4_REGS_VALUES_H__ 24 #define __T4_REGS_VALUES_H__ 25 26 /* 27 * This file contains definitions for various T4 register value hardware 28 * constants. The types of values encoded here are predominantly those for 29 * register fields which control "modal" behavior. For the most part, we do 30 * not include definitions for register fields which are simple numeric 31 * metrics, etc. 32 * 33 * These new "modal values" use a naming convention which matches the 34 * currently existing macros in t4_reg.h. For register field FOO which would 35 * have S_FOO, M_FOO, V_FOO() and G_FOO() macros, we introduce X_FOO_{MODE} 36 * definitions. These can be used as V_FOO(X_FOO_MODE) or as (G_FOO(x) == 37 * X_FOO_MODE). 38 * 39 * Note that this should all be part of t4_regs.h but the toolset used to 40 * generate that file doesn't [yet] have the capability of collecting these 41 * constants. 42 */ 43 44 /* 45 * SGE definitions. 46 * ================ 47 */ 48 49 /* 50 * SGE register field values. 51 */ 52 53 /* CONTROL register */ 54 #define X_FLSPLITMODE_FLSPLITMIN 0 55 #define X_FLSPLITMODE_ETHHDR 1 56 #define X_FLSPLITMODE_IPHDR 2 57 #define X_FLSPLITMODE_TCPHDR 3 58 59 #define X_DCASYSTYPE_FSB 0 60 #define X_DCASYSTYPE_CSI 1 61 62 #define X_EGSTATPAGESIZE_64B 0 63 #define X_EGSTATPAGESIZE_128B 1 64 65 #define X_RXPKTCPLMODE_DATA 0 66 #define X_RXPKTCPLMODE_SPLIT 1 67 68 #define X_INGPCIEBOUNDARY_SHIFT 5 69 #define X_INGPCIEBOUNDARY_32B 0 70 #define X_INGPCIEBOUNDARY_64B 1 71 #define X_INGPCIEBOUNDARY_128B 2 72 #define X_INGPCIEBOUNDARY_256B 3 73 #define X_INGPCIEBOUNDARY_512B 4 74 #define X_INGPCIEBOUNDARY_1024B 5 75 #define X_INGPCIEBOUNDARY_2048B 6 76 #define X_INGPCIEBOUNDARY_4096B 7 77 78 #define X_INGPADBOUNDARY_SHIFT 5 79 #define X_INGPADBOUNDARY_32B 0 80 #define X_INGPADBOUNDARY_64B 1 81 #define X_INGPADBOUNDARY_128B 2 82 #define X_INGPADBOUNDARY_256B 3 83 #define X_INGPADBOUNDARY_512B 4 84 #define X_INGPADBOUNDARY_1024B 5 85 #define X_INGPADBOUNDARY_2048B 6 86 #define X_INGPADBOUNDARY_4096B 7 87 88 #define X_EGRPCIEBOUNDARY_SHIFT 5 89 #define X_EGRPCIEBOUNDARY_32B 0 90 #define X_EGRPCIEBOUNDARY_64B 1 91 #define X_EGRPCIEBOUNDARY_128B 2 92 #define X_EGRPCIEBOUNDARY_256B 3 93 #define X_EGRPCIEBOUNDARY_512B 4 94 #define X_EGRPCIEBOUNDARY_1024B 5 95 #define X_EGRPCIEBOUNDARY_2048B 6 96 #define X_EGRPCIEBOUNDARY_4096B 7 97 98 /* GTS register */ 99 #define SGE_TIMERREGS 6 100 #define X_TIMERREG_COUNTER0 0 101 #define X_TIMERREG_COUNTER1 1 102 #define X_TIMERREG_COUNTER2 2 103 #define X_TIMERREG_COUNTER3 3 104 #define X_TIMERREG_COUNTER4 4 105 #define X_TIMERREG_COUNTER5 5 106 #define X_TIMERREG_RESTART_COUNTER 6 107 #define X_TIMERREG_UPDATE_CIDX 7 108 109 /* 110 * Egress Context field values 111 */ 112 #define EC_WR_UNITS 16 113 114 #define X_FETCHBURSTMIN_SHIFT 4 115 #define X_FETCHBURSTMIN_16B 0 116 #define X_FETCHBURSTMIN_32B 1 117 #define X_FETCHBURSTMIN_64B 2 118 #define X_FETCHBURSTMIN_128B 3 119 120 #define X_FETCHBURSTMAX_SHIFT 6 121 #define X_FETCHBURSTMAX_64B 0 122 #define X_FETCHBURSTMAX_128B 1 123 #define X_FETCHBURSTMAX_256B 2 124 #define X_FETCHBURSTMAX_512B 3 125 126 #define X_HOSTFCMODE_NONE 0 127 #define X_HOSTFCMODE_INGRESS_QUEUE 1 128 #define X_HOSTFCMODE_STATUS_PAGE 2 129 #define X_HOSTFCMODE_BOTH 3 130 131 #define X_HOSTFCOWNER_UP 0 132 #define X_HOSTFCOWNER_SGE 1 133 134 #define X_CIDXFLUSHTHRESH_1 0 135 #define X_CIDXFLUSHTHRESH_2 1 136 #define X_CIDXFLUSHTHRESH_4 2 137 #define X_CIDXFLUSHTHRESH_8 3 138 #define X_CIDXFLUSHTHRESH_16 4 139 #define X_CIDXFLUSHTHRESH_32 5 140 #define X_CIDXFLUSHTHRESH_64 6 141 #define X_CIDXFLUSHTHRESH_128 7 142 143 #define X_IDXSIZE_UNIT 64 144 145 #define X_BASEADDRESS_ALIGN 512 146 147 /* 148 * Ingress Context field values 149 */ 150 #define X_UPDATESCHEDULING_TIMER 0 151 #define X_UPDATESCHEDULING_COUNTER_OPTTIMER 1 152 153 #define X_UPDATEDELIVERY_NONE 0 154 #define X_UPDATEDELIVERY_INTERRUPT 1 155 #define X_UPDATEDELIVERY_STATUS_PAGE 2 156 #define X_UPDATEDELIVERY_BOTH 3 157 158 #define X_INTERRUPTDESTINATION_PCIE 0 159 #define X_INTERRUPTDESTINATION_IQ 1 160 161 #define X_QUEUEENTRYSIZE_16B 0 162 #define X_QUEUEENTRYSIZE_32B 1 163 #define X_QUEUEENTRYSIZE_64B 2 164 #define X_QUEUEENTRYSIZE_128B 3 165 166 #define IC_SIZE_UNIT 16 167 #define IC_BASEADDRESS_ALIGN 512 168 169 #define X_RSPD_TYPE_FLBUF 0 170 #define X_RSPD_TYPE_CPL 1 171 #define X_RSPD_TYPE_INTR 2 172 173 /* 174 * CIM definitions. 175 * ================ 176 */ 177 178 /* 179 * CIM register field values. 180 */ 181 #define X_MBOWNER_NONE 0 182 #define X_MBOWNER_FW 1 183 #define X_MBOWNER_PL 2 184 185 /* 186 * PCI-E definitions. 187 * ================== 188 */ 189 190 #define X_WINDOW_SHIFT 10 191 #define X_PCIEOFST_SHIFT 10 192 193 /* 194 * TP definitions. 195 * =============== 196 */ 197 198 /* 199 * TP_VLAN_PRI_MAP controls which subset of fields will be present in the 200 * Compressed Filter Tuple for LE filters. Each bit set in TP_VLAN_PRI_MAP 201 * selects for a particular field being present. These fields, when present 202 * in the Compressed Filter Tuple, have the following widths in bits. 203 */ 204 #define W_FT_FCOE 1 205 #define W_FT_PORT 3 206 #define W_FT_VNIC_ID 17 207 #define W_FT_VLAN 17 208 #define W_FT_TOS 8 209 #define W_FT_PROTOCOL 8 210 #define W_FT_ETHERTYPE 16 211 #define W_FT_MACMATCH 9 212 #define W_FT_MPSHITTYPE 3 213 #define W_FT_FRAGMENTATION 1 214 215 /* 216 * Some of the Compressed Filter Tuple fields have internal structure. These 217 * bit shifts/masks describe those structures. All shifts are relative to the 218 * base position of the fields within the Compressed Filter Tuple 219 */ 220 #define S_FT_VLAN_VLD 16 221 #define V_FT_VLAN_VLD(x) ((x) << S_FT_VLAN_VLD) 222 #define F_FT_VLAN_VLD V_FT_VLAN_VLD(1U) 223 224 #define S_FT_VNID_ID_VF 0 225 #define M_FT_VNID_ID_VF 0x7fU 226 #define V_FT_VNID_ID_VF(x) ((x) << S_FT_VNID_ID_VF) 227 #define G_FT_VNID_ID_VF(x) (((x) >> S_FT_VNID_ID_VF) & M_FT_VNID_ID_VF) 228 229 #define S_FT_VNID_ID_PF 7 230 #define M_FT_VNID_ID_PF 0x7U 231 #define V_FT_VNID_ID_PF(x) ((x) << S_FT_VNID_ID_PF) 232 #define G_FT_VNID_ID_PF(x) (((x) >> S_FT_VNID_ID_PF) & M_FT_VNID_ID_PF) 233 234 #define S_FT_VNID_ID_VLD 16 235 #define V_FT_VNID_ID_VLD(x) ((x) << S_FT_VNID_ID_VLD) 236 #define F_FT_VNID_ID_VLD(x) V_FT_VNID_ID_VLD(1U) 237 238 239 #endif /* __T4_REGS_VALUES_H__ */ 240