1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License (the "License"). 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9 * or http://www.opensolaris.org/os/licensing. 10 * See the License for the specific language governing permissions 11 * and limitations under the License. 12 * 13 * When distributing Covered Code, include this CDDL HEADER in each 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15 * If applicable, add the following below this CDDL HEADER, with the 16 * fields enclosed by brackets "[]" replaced with your own identifying 17 * information: Portions Copyright [yyyy] [name of copyright owner] 18 * 19 * CDDL HEADER END 20 */ 21 /* 22 * Copyright 2008 Sun Microsystems, Inc. All rights reserved. 23 * Use is subject to license terms. 24 */ 25 26 #ifndef _SYS_HXGE_HXGE_COMMON_IMPL_H 27 #define _SYS_HXGE_HXGE_COMMON_IMPL_H 28 29 #pragma ident "%Z%%M% %I% %E% SMI" 30 31 #ifdef __cplusplus 32 extern "C" { 33 #endif 34 35 #define HPI_REGH(hpi_handle) (hpi_handle.regh) 36 #define HPI_REGP(hpi_handle) (hpi_handle.regp) 37 38 #define NO_DEBUG 0x0000000000000000ULL 39 #define RX_CTL 0x0000000000000001ULL 40 #define TX_CTL 0x0000000000000002ULL 41 #define OBP_CTL 0x0000000000000004ULL 42 #define VPD_CTL 0x0000000000000008ULL 43 #define DDI_CTL 0x0000000000000010ULL 44 #define MEM_CTL 0x0000000000000020ULL 45 #define IOC_CTL 0x0000000000000040ULL 46 #define MOD_CTL 0x0000000000000080ULL 47 #define DMA_CTL 0x0000000000000100ULL 48 #define STR_CTL 0x0000000000000200ULL 49 #define INT_CTL 0x0000000000000400ULL 50 #define SYSERR_CTL 0x0000000000000800ULL 51 #define KST_CTL 0x0000000000001000ULL 52 #define FCRAM_CTL 0x0000000000002000ULL 53 #define MAC_CTL 0x0000000000004000ULL 54 #define DMA2_CTL 0x0000000000008000ULL 55 #define RX2_CTL 0x0000000000010000ULL 56 #define TX2_CTL 0x0000000000020000ULL 57 #define MEM2_CTL 0x0000000000040000ULL 58 #define MEM3_CTL 0x0000000000080000ULL 59 #define NEMO_CTL 0x0000000000100000ULL 60 #define NDD_CTL 0x0000000000200000ULL 61 #define NDD2_CTL 0x0000000000400000ULL 62 #define PFC_CTL 0x0000000000800000ULL 63 #define CFG_CTL 0x0000000001000000ULL 64 #define CFG2_CTL 0x0000000002000000ULL 65 #define VIR_CTL 0x0000000004000000ULL 66 #define VIR2_CTL 0x0000000008000000ULL 67 #define HXGE_NOTE 0x0000000010000000ULL 68 #define HXGE_ERR_CTL 0x0000000020000000ULL 69 #define MAC_INT_CTL 0x0000000040000000ULL 70 #define RX_INT_CTL 0x0000000080000000ULL 71 #define TX_ERR_CTL 0x0000000100000000ULL 72 #define DDI_INT_CTL 0x0000000200000000ULL 73 #define DUMP_ALWAYS 0x2000000000000000ULL 74 75 /* HPI Debug and Error defines */ 76 #define HPI_RDC_CTL 0x0000000000000001ULL 77 #define HPI_TDC_CTL 0x0000000000000002ULL 78 #define HPI_VMAC_CTL 0x0000000000000004ULL 79 #define HPI_PFC_CTL 0x0000000000000008ULL 80 #define HPI_VIR_CTL 0x0000000000000010ULL 81 #define HPI_PIO_CTL 0x0000000000000020ULL 82 #define HPI_VIO_CTL 0x0000000000000040ULL 83 #define HPI_REG_CTL 0x0000000000000080ULL 84 #define HPI_ERR_CTL 0x0000000000000100ULL 85 86 #include <sys/types.h> 87 #include <sys/ddi.h> 88 #include <sys/sunddi.h> 89 #include <sys/dditypes.h> 90 #include <sys/ethernet.h> 91 92 #ifdef HXGE_DEBUG 93 #define HXGE_DEBUG_MSG(params) hxge_debug_msg params 94 #else 95 #define HXGE_DEBUG_MSG(params) 96 #endif 97 98 #define HXGE_ERROR_MSG(params) hxge_debug_msg params 99 100 typedef kmutex_t hxge_os_mutex_t; 101 typedef krwlock_t hxge_os_rwlock_t; 102 103 typedef dev_info_t hxge_dev_info_t; 104 typedef ddi_iblock_cookie_t hxge_intr_cookie_t; 105 106 typedef ddi_acc_handle_t hxge_os_acc_handle_t; 107 typedef hxge_os_acc_handle_t hpi_reg_handle_t; 108 typedef uint64_t hpi_reg_ptr_t; 109 110 typedef ddi_dma_handle_t hxge_os_dma_handle_t; 111 typedef struct _hxge_dma_common_t hxge_os_dma_common_t; 112 typedef struct _hxge_block_mv_t hxge_os_block_mv_t; 113 typedef frtn_t hxge_os_frtn_t; 114 115 #define HXGE_MUTEX_DRIVER MUTEX_DRIVER 116 #define MUTEX_INIT(lock, name, type, arg) \ 117 mutex_init(lock, name, type, arg) 118 #define MUTEX_ENTER(lock) mutex_enter(lock) 119 #define MUTEX_TRY_ENTER(lock) mutex_tryenter(lock) 120 #define MUTEX_EXIT(lock) mutex_exit(lock) 121 #define MUTEX_DESTROY(lock) mutex_destroy(lock) 122 123 #define RW_INIT(lock, name, type, arg) rw_init(lock, name, type, arg) 124 #define RW_ENTER_WRITER(lock) rw_enter(lock, RW_WRITER) 125 #define RW_ENTER_READER(lock) rw_enter(lock, RW_READER) 126 #define RW_TRY_ENTER(lock, type) rw_tryenter(lock, type) 127 #define RW_EXIT(lock) rw_exit(lock) 128 #define RW_DESTROY(lock) rw_destroy(lock) 129 #define KMEM_ALLOC(size, flag) kmem_alloc(size, flag) 130 #define KMEM_ZALLOC(size, flag) kmem_zalloc(size, flag) 131 #define KMEM_FREE(buf, size) kmem_free(buf, size) 132 133 #define HXGE_DELAY(microseconds) (drv_usecwait(microseconds)) 134 135 #define HXGE_PIO_READ8(handle, devaddr, offset) \ 136 (ddi_get8(handle, (uint8_t *)((caddr_t)devaddr + offset))) 137 138 #define HXGE_PIO_READ16(handle, devaddr, offset) \ 139 (ddi_get16(handle, (uint16_t *)((caddr_t)devaddr + offset))) 140 141 #define HXGE_PIO_READ32(handle, devaddr, offset) \ 142 (ddi_get32(handle, (uint32_t *)((caddr_t)devaddr + offset))) 143 144 #define HXGE_PIO_READ64(handle, devaddr, offset) \ 145 (ddi_get64(handle, (uint64_t *)((caddr_t)devaddr + offset))) 146 147 #define HXGE_PIO_WRITE8(handle, devaddr, offset, data) \ 148 (ddi_put8(handle, (uint8_t *)((caddr_t)devaddr + offset), data)) 149 150 #define HXGE_PIO_WRITE16(handle, devaddr, offset, data) \ 151 (ddi_get16(handle, (uint16_t *)((caddr_t)devaddr + offset), data)) 152 153 #define HXGE_PIO_WRITE32(handle, devaddr, offset, data) \ 154 (ddi_put32(handle, (uint32_t *)((caddr_t)devaddr + offset), data)) 155 156 #define HXGE_PIO_WRITE64(handle, devaddr, offset, data) \ 157 (ddi_put64(handle, (uint64_t *)((caddr_t)devaddr + offset), data)) 158 159 #define HXGE_HPI_PIO_READ8(hpi_handle, offset) \ 160 (ddi_get8(HPI_REGH(hpi_handle), \ 161 (uint8_t *)(HPI_REGP(hpi_handle) + offset))) 162 163 #define HXGE_HPI_PIO_READ16(hpi_handle, offset) \ 164 (ddi_get16(HPI_REGH(hpi_handle), \ 165 (uint16_t *)(HPI_REGP(hpi_handle) + offset))) 166 167 #define HXGE_HPI_PIO_READ32(hpi_handle, offset) \ 168 (ddi_get32(HPI_REGH(hpi_handle), \ 169 (uint32_t *)(HPI_REGP(hpi_handle) + offset))) 170 171 #define HXGE_HPI_PIO_READ64(hpi_handle, offset) \ 172 (ddi_get64(HPI_REGH(hpi_handle), \ 173 (uint64_t *)(HPI_REGP(hpi_handle) + offset))) 174 175 #define HXGE_HPI_PIO_WRITE8(hpi_handle, offset, data) \ 176 (ddi_put8(HPI_REGH(hpi_handle), \ 177 (uint8_t *)(HPI_REGP(hpi_handle) + offset), data)) 178 179 #define HXGE_HPI_PIO_WRITE16(hpi_handle, offset, data) \ 180 (ddi_put16(HPI_REGH(hpi_handle), \ 181 (uint16_t *)(HPI_REGP(hpi_handle) + offset), data)) 182 183 #define HXGE_HPI_PIO_WRITE32(hpi_handle, offset, data) \ 184 (ddi_put32(HPI_REGH(hpi_handle), \ 185 (uint32_t *)(HPI_REGP(hpi_handle) + offset), data)) 186 187 #define HXGE_HPI_PIO_WRITE64(hpi_handle, offset, data) \ 188 (ddi_put64(HPI_REGH(hpi_handle), \ 189 (uint64_t *)(HPI_REGP(hpi_handle) + offset), data)) 190 191 #define HXGE_MEM_PIO_READ8(hpi_handle) \ 192 (ddi_get8(HPI_REGH(hpi_handle), (uint8_t *)HPI_REGP(hpi_handle))) 193 194 #define HXGE_MEM_PIO_READ16(hpi_handle) \ 195 (ddi_get16(HPI_REGH(hpi_handle), (uint16_t *)HPI_REGP(hpi_handle))) 196 197 #define HXGE_MEM_PIO_READ32(hpi_handle) \ 198 (ddi_get32(HPI_REGH(hpi_handle), (uint32_t *)HPI_REGP(hpi_handle))) 199 200 #define HXGE_MEM_PIO_READ64(hpi_handle) \ 201 (ddi_get64(HPI_REGH(hpi_handle), (uint64_t *)HPI_REGP(hpi_handle))) 202 203 #define HXGE_MEM_PIO_WRITE8(hpi_handle, data) \ 204 (ddi_put8(HPI_REGH(hpi_handle), (uint8_t *)HPI_REGP(hpi_handle), data)) 205 206 #define HXGE_MEM_PIO_WRITE16(hpi_handle, data) \ 207 (ddi_put16(HPI_REGH(hpi_handle), \ 208 (uint16_t *)HPI_REGP(hpi_handle), data)) 209 210 #define HXGE_MEM_PIO_WRITE32(hpi_handle, data) \ 211 (ddi_put32(HPI_REGH(hpi_handle), \ 212 (uint32_t *)HPI_REGP(hpi_handle), data)) 213 214 #define HXGE_MEM_PIO_WRITE64(hpi_handle, data) \ 215 (ddi_put64(HPI_REGH(hpi_handle), \ 216 (uint64_t *)HPI_REGP(hpi_handle), data)) 217 218 #define FM_SERVICE_RESTORED(hxgep) \ 219 if (DDI_FM_EREPORT_CAP(hxgep->fm_capabilities)) \ 220 ddi_fm_service_impact(hxgep->dip, DDI_SERVICE_RESTORED) 221 #define HXGE_FM_REPORT_ERROR(hxgep, chan, ereport_id) \ 222 if (DDI_FM_EREPORT_CAP(hxgep->fm_capabilities)) \ 223 hxge_fm_report_error(hxgep, chan, ereport_id) 224 225 226 #if defined(REG_TRACE) 227 #define HXGE_REG_RD64(handle, offset, val_p) {\ 228 *(val_p) = HXGE_HPI_PIO_READ64(handle, offset);\ 229 hpi_rtrace_update(handle, B_FALSE, &hpi_rtracebuf, (uint32_t)offset, \ 230 (uint64_t)(*(val_p)));\ 231 } 232 #define HXGE_REG_WR64(handle, offset, val) {\ 233 HXGE_HPI_PIO_WRITE64(handle, (offset), (val));\ 234 hpi_rtrace_update(handle, B_TRUE, &hpi_rtracebuf, (uint32_t)offset,\ 235 (uint64_t)(val));\ 236 } 237 #elif defined(REG_SHOW) 238 /* 239 * Send 0xbadbad to tell rs_show_reg that we do not have 240 * a valid RTBUF index to pass 241 */ 242 #define HXGE_REG_RD64(handle, offset, val_p) {\ 243 *(val_p) = HXGE_HPI_PIO_READ64(handle, offset);\ 244 rt_show_reg(0xbadbad, B_FALSE, (uint32_t)offset, (uint64_t)(*(val_p)));\ 245 } 246 /* 247 * Send 0xbadbad to tell rs_show_reg that we do not have 248 * a valid RTBUF index to pass 249 */ 250 #define HXGE_REG_WR64(handle, offset, val) {\ 251 HXGE_HPI_PIO_WRITE64(handle, offset, (val));\ 252 rt_show_reg(0xbadbad, B_TRUE, (uint32_t)offset, (uint64_t)(val));\ 253 } 254 #else 255 256 #define HXGE_REG_RD64(handle, offset, val_p) {\ 257 *(val_p) = HXGE_HPI_PIO_READ64(handle, offset);\ 258 } 259 #define HXGE_REG_RD32(handle, offset, val_p) {\ 260 *(val_p) = HXGE_HPI_PIO_READ32(handle, offset);\ 261 } 262 #define HXGE_REG_WR64(handle, offset, val) {\ 263 HXGE_HPI_PIO_WRITE64(handle, (offset), (val));\ 264 } 265 #define HXGE_REG_WR32(handle, offset, val) {\ 266 HXGE_HPI_PIO_WRITE32(handle, (offset), (val));\ 267 } 268 #endif 269 270 #ifdef __cplusplus 271 } 272 #endif 273 274 #endif /* _SYS_HXGE_HXGE_COMMON_IMPL_H */ 275