1 /****************************************************************************** 2 3 Copyright (c) 2013-2015, Intel Corporation 4 All rights reserved. 5 6 Redistribution and use in source and binary forms, with or without 7 modification, are permitted provided that the following conditions are met: 8 9 1. Redistributions of source code must retain the above copyright notice, 10 this list of conditions and the following disclaimer. 11 12 2. Redistributions in binary form must reproduce the above copyright 13 notice, this list of conditions and the following disclaimer in the 14 documentation and/or other materials provided with the distribution. 15 16 3. Neither the name of the Intel Corporation nor the names of its 17 contributors may be used to endorse or promote products derived from 18 this software without specific prior written permission. 19 20 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 21 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 24 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 30 POSSIBILITY OF SUCH DAMAGE. 31 32 ******************************************************************************/ 33 /*$FreeBSD$*/ 34 35 #include "i40e_type.h" 36 #include "i40e_adminq.h" 37 #include "i40e_prototype.h" 38 #include "i40e_virtchnl.h" 39 40 41 /** 42 * i40e_set_mac_type - Sets MAC type 43 * @hw: pointer to the HW structure 44 * 45 * This function sets the mac type of the adapter based on the 46 * vendor ID and device ID stored in the hw structure. 47 **/ 48 static enum i40e_status_code i40e_set_mac_type(struct i40e_hw *hw) 49 { 50 enum i40e_status_code status = I40E_SUCCESS; 51 52 DEBUGFUNC("i40e_set_mac_type\n"); 53 54 if (hw->vendor_id == I40E_INTEL_VENDOR_ID) { 55 switch (hw->device_id) { 56 case I40E_DEV_ID_SFP_XL710: 57 case I40E_DEV_ID_QEMU: 58 case I40E_DEV_ID_KX_B: 59 case I40E_DEV_ID_KX_C: 60 case I40E_DEV_ID_QSFP_A: 61 case I40E_DEV_ID_QSFP_B: 62 case I40E_DEV_ID_QSFP_C: 63 case I40E_DEV_ID_10G_BASE_T: 64 case I40E_DEV_ID_10G_BASE_T4: 65 case I40E_DEV_ID_20G_KR2: 66 case I40E_DEV_ID_20G_KR2_A: 67 case I40E_DEV_ID_25G_B: 68 case I40E_DEV_ID_25G_SFP28: 69 hw->mac.type = I40E_MAC_XL710; 70 break; 71 case I40E_DEV_ID_X722_A0: 72 case I40E_DEV_ID_KX_X722: 73 case I40E_DEV_ID_QSFP_X722: 74 case I40E_DEV_ID_SFP_X722: 75 case I40E_DEV_ID_1G_BASE_T_X722: 76 case I40E_DEV_ID_10G_BASE_T_X722: 77 case I40E_DEV_ID_SFP_I_X722: 78 hw->mac.type = I40E_MAC_X722; 79 break; 80 default: 81 hw->mac.type = I40E_MAC_GENERIC; 82 break; 83 } 84 } else { 85 status = I40E_ERR_DEVICE_NOT_SUPPORTED; 86 } 87 88 DEBUGOUT2("i40e_set_mac_type found mac: %d, returns: %d\n", 89 hw->mac.type, status); 90 return status; 91 } 92 93 /** 94 * i40e_aq_str - convert AQ err code to a string 95 * @hw: pointer to the HW structure 96 * @aq_err: the AQ error code to convert 97 **/ 98 const char *i40e_aq_str(struct i40e_hw *hw, enum i40e_admin_queue_err aq_err) 99 { 100 switch (aq_err) { 101 case I40E_AQ_RC_OK: 102 return "OK"; 103 case I40E_AQ_RC_EPERM: 104 return "I40E_AQ_RC_EPERM"; 105 case I40E_AQ_RC_ENOENT: 106 return "I40E_AQ_RC_ENOENT"; 107 case I40E_AQ_RC_ESRCH: 108 return "I40E_AQ_RC_ESRCH"; 109 case I40E_AQ_RC_EINTR: 110 return "I40E_AQ_RC_EINTR"; 111 case I40E_AQ_RC_EIO: 112 return "I40E_AQ_RC_EIO"; 113 case I40E_AQ_RC_ENXIO: 114 return "I40E_AQ_RC_ENXIO"; 115 case I40E_AQ_RC_E2BIG: 116 return "I40E_AQ_RC_E2BIG"; 117 case I40E_AQ_RC_EAGAIN: 118 return "I40E_AQ_RC_EAGAIN"; 119 case I40E_AQ_RC_ENOMEM: 120 return "I40E_AQ_RC_ENOMEM"; 121 case I40E_AQ_RC_EACCES: 122 return "I40E_AQ_RC_EACCES"; 123 case I40E_AQ_RC_EFAULT: 124 return "I40E_AQ_RC_EFAULT"; 125 case I40E_AQ_RC_EBUSY: 126 return "I40E_AQ_RC_EBUSY"; 127 case I40E_AQ_RC_EEXIST: 128 return "I40E_AQ_RC_EEXIST"; 129 case I40E_AQ_RC_EINVAL: 130 return "I40E_AQ_RC_EINVAL"; 131 case I40E_AQ_RC_ENOTTY: 132 return "I40E_AQ_RC_ENOTTY"; 133 case I40E_AQ_RC_ENOSPC: 134 return "I40E_AQ_RC_ENOSPC"; 135 case I40E_AQ_RC_ENOSYS: 136 return "I40E_AQ_RC_ENOSYS"; 137 case I40E_AQ_RC_ERANGE: 138 return "I40E_AQ_RC_ERANGE"; 139 case I40E_AQ_RC_EFLUSHED: 140 return "I40E_AQ_RC_EFLUSHED"; 141 case I40E_AQ_RC_BAD_ADDR: 142 return "I40E_AQ_RC_BAD_ADDR"; 143 case I40E_AQ_RC_EMODE: 144 return "I40E_AQ_RC_EMODE"; 145 case I40E_AQ_RC_EFBIG: 146 return "I40E_AQ_RC_EFBIG"; 147 } 148 149 snprintf(hw->err_str, sizeof(hw->err_str), "%d", aq_err); 150 return hw->err_str; 151 } 152 153 /** 154 * i40e_stat_str - convert status err code to a string 155 * @hw: pointer to the HW structure 156 * @stat_err: the status error code to convert 157 **/ 158 const char *i40e_stat_str(struct i40e_hw *hw, enum i40e_status_code stat_err) 159 { 160 switch (stat_err) { 161 case I40E_SUCCESS: 162 return "OK"; 163 case I40E_ERR_NVM: 164 return "I40E_ERR_NVM"; 165 case I40E_ERR_NVM_CHECKSUM: 166 return "I40E_ERR_NVM_CHECKSUM"; 167 case I40E_ERR_PHY: 168 return "I40E_ERR_PHY"; 169 case I40E_ERR_CONFIG: 170 return "I40E_ERR_CONFIG"; 171 case I40E_ERR_PARAM: 172 return "I40E_ERR_PARAM"; 173 case I40E_ERR_MAC_TYPE: 174 return "I40E_ERR_MAC_TYPE"; 175 case I40E_ERR_UNKNOWN_PHY: 176 return "I40E_ERR_UNKNOWN_PHY"; 177 case I40E_ERR_LINK_SETUP: 178 return "I40E_ERR_LINK_SETUP"; 179 case I40E_ERR_ADAPTER_STOPPED: 180 return "I40E_ERR_ADAPTER_STOPPED"; 181 case I40E_ERR_INVALID_MAC_ADDR: 182 return "I40E_ERR_INVALID_MAC_ADDR"; 183 case I40E_ERR_DEVICE_NOT_SUPPORTED: 184 return "I40E_ERR_DEVICE_NOT_SUPPORTED"; 185 case I40E_ERR_MASTER_REQUESTS_PENDING: 186 return "I40E_ERR_MASTER_REQUESTS_PENDING"; 187 case I40E_ERR_INVALID_LINK_SETTINGS: 188 return "I40E_ERR_INVALID_LINK_SETTINGS"; 189 case I40E_ERR_AUTONEG_NOT_COMPLETE: 190 return "I40E_ERR_AUTONEG_NOT_COMPLETE"; 191 case I40E_ERR_RESET_FAILED: 192 return "I40E_ERR_RESET_FAILED"; 193 case I40E_ERR_SWFW_SYNC: 194 return "I40E_ERR_SWFW_SYNC"; 195 case I40E_ERR_NO_AVAILABLE_VSI: 196 return "I40E_ERR_NO_AVAILABLE_VSI"; 197 case I40E_ERR_NO_MEMORY: 198 return "I40E_ERR_NO_MEMORY"; 199 case I40E_ERR_BAD_PTR: 200 return "I40E_ERR_BAD_PTR"; 201 case I40E_ERR_RING_FULL: 202 return "I40E_ERR_RING_FULL"; 203 case I40E_ERR_INVALID_PD_ID: 204 return "I40E_ERR_INVALID_PD_ID"; 205 case I40E_ERR_INVALID_QP_ID: 206 return "I40E_ERR_INVALID_QP_ID"; 207 case I40E_ERR_INVALID_CQ_ID: 208 return "I40E_ERR_INVALID_CQ_ID"; 209 case I40E_ERR_INVALID_CEQ_ID: 210 return "I40E_ERR_INVALID_CEQ_ID"; 211 case I40E_ERR_INVALID_AEQ_ID: 212 return "I40E_ERR_INVALID_AEQ_ID"; 213 case I40E_ERR_INVALID_SIZE: 214 return "I40E_ERR_INVALID_SIZE"; 215 case I40E_ERR_INVALID_ARP_INDEX: 216 return "I40E_ERR_INVALID_ARP_INDEX"; 217 case I40E_ERR_INVALID_FPM_FUNC_ID: 218 return "I40E_ERR_INVALID_FPM_FUNC_ID"; 219 case I40E_ERR_QP_INVALID_MSG_SIZE: 220 return "I40E_ERR_QP_INVALID_MSG_SIZE"; 221 case I40E_ERR_QP_TOOMANY_WRS_POSTED: 222 return "I40E_ERR_QP_TOOMANY_WRS_POSTED"; 223 case I40E_ERR_INVALID_FRAG_COUNT: 224 return "I40E_ERR_INVALID_FRAG_COUNT"; 225 case I40E_ERR_QUEUE_EMPTY: 226 return "I40E_ERR_QUEUE_EMPTY"; 227 case I40E_ERR_INVALID_ALIGNMENT: 228 return "I40E_ERR_INVALID_ALIGNMENT"; 229 case I40E_ERR_FLUSHED_QUEUE: 230 return "I40E_ERR_FLUSHED_QUEUE"; 231 case I40E_ERR_INVALID_PUSH_PAGE_INDEX: 232 return "I40E_ERR_INVALID_PUSH_PAGE_INDEX"; 233 case I40E_ERR_INVALID_IMM_DATA_SIZE: 234 return "I40E_ERR_INVALID_IMM_DATA_SIZE"; 235 case I40E_ERR_TIMEOUT: 236 return "I40E_ERR_TIMEOUT"; 237 case I40E_ERR_OPCODE_MISMATCH: 238 return "I40E_ERR_OPCODE_MISMATCH"; 239 case I40E_ERR_CQP_COMPL_ERROR: 240 return "I40E_ERR_CQP_COMPL_ERROR"; 241 case I40E_ERR_INVALID_VF_ID: 242 return "I40E_ERR_INVALID_VF_ID"; 243 case I40E_ERR_INVALID_HMCFN_ID: 244 return "I40E_ERR_INVALID_HMCFN_ID"; 245 case I40E_ERR_BACKING_PAGE_ERROR: 246 return "I40E_ERR_BACKING_PAGE_ERROR"; 247 case I40E_ERR_NO_PBLCHUNKS_AVAILABLE: 248 return "I40E_ERR_NO_PBLCHUNKS_AVAILABLE"; 249 case I40E_ERR_INVALID_PBLE_INDEX: 250 return "I40E_ERR_INVALID_PBLE_INDEX"; 251 case I40E_ERR_INVALID_SD_INDEX: 252 return "I40E_ERR_INVALID_SD_INDEX"; 253 case I40E_ERR_INVALID_PAGE_DESC_INDEX: 254 return "I40E_ERR_INVALID_PAGE_DESC_INDEX"; 255 case I40E_ERR_INVALID_SD_TYPE: 256 return "I40E_ERR_INVALID_SD_TYPE"; 257 case I40E_ERR_MEMCPY_FAILED: 258 return "I40E_ERR_MEMCPY_FAILED"; 259 case I40E_ERR_INVALID_HMC_OBJ_INDEX: 260 return "I40E_ERR_INVALID_HMC_OBJ_INDEX"; 261 case I40E_ERR_INVALID_HMC_OBJ_COUNT: 262 return "I40E_ERR_INVALID_HMC_OBJ_COUNT"; 263 case I40E_ERR_INVALID_SRQ_ARM_LIMIT: 264 return "I40E_ERR_INVALID_SRQ_ARM_LIMIT"; 265 case I40E_ERR_SRQ_ENABLED: 266 return "I40E_ERR_SRQ_ENABLED"; 267 case I40E_ERR_ADMIN_QUEUE_ERROR: 268 return "I40E_ERR_ADMIN_QUEUE_ERROR"; 269 case I40E_ERR_ADMIN_QUEUE_TIMEOUT: 270 return "I40E_ERR_ADMIN_QUEUE_TIMEOUT"; 271 case I40E_ERR_BUF_TOO_SHORT: 272 return "I40E_ERR_BUF_TOO_SHORT"; 273 case I40E_ERR_ADMIN_QUEUE_FULL: 274 return "I40E_ERR_ADMIN_QUEUE_FULL"; 275 case I40E_ERR_ADMIN_QUEUE_NO_WORK: 276 return "I40E_ERR_ADMIN_QUEUE_NO_WORK"; 277 case I40E_ERR_BAD_IWARP_CQE: 278 return "I40E_ERR_BAD_IWARP_CQE"; 279 case I40E_ERR_NVM_BLANK_MODE: 280 return "I40E_ERR_NVM_BLANK_MODE"; 281 case I40E_ERR_NOT_IMPLEMENTED: 282 return "I40E_ERR_NOT_IMPLEMENTED"; 283 case I40E_ERR_PE_DOORBELL_NOT_ENABLED: 284 return "I40E_ERR_PE_DOORBELL_NOT_ENABLED"; 285 case I40E_ERR_DIAG_TEST_FAILED: 286 return "I40E_ERR_DIAG_TEST_FAILED"; 287 case I40E_ERR_NOT_READY: 288 return "I40E_ERR_NOT_READY"; 289 case I40E_NOT_SUPPORTED: 290 return "I40E_NOT_SUPPORTED"; 291 case I40E_ERR_FIRMWARE_API_VERSION: 292 return "I40E_ERR_FIRMWARE_API_VERSION"; 293 } 294 295 snprintf(hw->err_str, sizeof(hw->err_str), "%d", stat_err); 296 return hw->err_str; 297 } 298 299 /** 300 * i40e_debug_aq 301 * @hw: debug mask related to admin queue 302 * @mask: debug mask 303 * @desc: pointer to admin queue descriptor 304 * @buffer: pointer to command buffer 305 * @buf_len: max length of buffer 306 * 307 * Dumps debug log about adminq command with descriptor contents. 308 **/ 309 void i40e_debug_aq(struct i40e_hw *hw, enum i40e_debug_mask mask, void *desc, 310 void *buffer, u16 buf_len) 311 { 312 struct i40e_aq_desc *aq_desc = (struct i40e_aq_desc *)desc; 313 u16 len = LE16_TO_CPU(aq_desc->datalen); 314 u8 *buf = (u8 *)buffer; 315 u16 i = 0; 316 317 if ((!(mask & hw->debug_mask)) || (desc == NULL)) 318 return; 319 320 i40e_debug(hw, mask, 321 "AQ CMD: opcode 0x%04X, flags 0x%04X, datalen 0x%04X, retval 0x%04X\n", 322 LE16_TO_CPU(aq_desc->opcode), 323 LE16_TO_CPU(aq_desc->flags), 324 LE16_TO_CPU(aq_desc->datalen), 325 LE16_TO_CPU(aq_desc->retval)); 326 i40e_debug(hw, mask, "\tcookie (h,l) 0x%08X 0x%08X\n", 327 LE32_TO_CPU(aq_desc->cookie_high), 328 LE32_TO_CPU(aq_desc->cookie_low)); 329 i40e_debug(hw, mask, "\tparam (0,1) 0x%08X 0x%08X\n", 330 LE32_TO_CPU(aq_desc->params.internal.param0), 331 LE32_TO_CPU(aq_desc->params.internal.param1)); 332 i40e_debug(hw, mask, "\taddr (h,l) 0x%08X 0x%08X\n", 333 LE32_TO_CPU(aq_desc->params.external.addr_high), 334 LE32_TO_CPU(aq_desc->params.external.addr_low)); 335 336 if ((buffer != NULL) && (aq_desc->datalen != 0)) { 337 i40e_debug(hw, mask, "AQ CMD Buffer:\n"); 338 if (buf_len < len) 339 len = buf_len; 340 /* write the full 16-byte chunks */ 341 for (i = 0; i < (len - 16); i += 16) 342 i40e_debug(hw, mask, 343 "\t0x%04X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X\n", 344 i, buf[i], buf[i+1], buf[i+2], buf[i+3], 345 buf[i+4], buf[i+5], buf[i+6], buf[i+7], 346 buf[i+8], buf[i+9], buf[i+10], buf[i+11], 347 buf[i+12], buf[i+13], buf[i+14], buf[i+15]); 348 /* the most we could have left is 16 bytes, pad with zeros */ 349 if (i < len) { 350 char d_buf[16]; 351 int j, i_sav; 352 353 i_sav = i; 354 memset(d_buf, 0, sizeof(d_buf)); 355 for (j = 0; i < len; j++, i++) 356 d_buf[j] = buf[i]; 357 i40e_debug(hw, mask, 358 "\t0x%04X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X\n", 359 i_sav, d_buf[0], d_buf[1], d_buf[2], d_buf[3], 360 d_buf[4], d_buf[5], d_buf[6], d_buf[7], 361 d_buf[8], d_buf[9], d_buf[10], d_buf[11], 362 d_buf[12], d_buf[13], d_buf[14], d_buf[15]); 363 } 364 } 365 } 366 367 /** 368 * i40e_check_asq_alive 369 * @hw: pointer to the hw struct 370 * 371 * Returns TRUE if Queue is enabled else FALSE. 372 **/ 373 bool i40e_check_asq_alive(struct i40e_hw *hw) 374 { 375 if (hw->aq.asq.len) 376 return !!(rd32(hw, hw->aq.asq.len) & 377 I40E_PF_ATQLEN_ATQENABLE_MASK); 378 return FALSE; 379 } 380 381 /** 382 * i40e_aq_queue_shutdown 383 * @hw: pointer to the hw struct 384 * @unloading: is the driver unloading itself 385 * 386 * Tell the Firmware that we're shutting down the AdminQ and whether 387 * or not the driver is unloading as well. 388 **/ 389 enum i40e_status_code i40e_aq_queue_shutdown(struct i40e_hw *hw, 390 bool unloading) 391 { 392 struct i40e_aq_desc desc; 393 struct i40e_aqc_queue_shutdown *cmd = 394 (struct i40e_aqc_queue_shutdown *)&desc.params.raw; 395 enum i40e_status_code status; 396 397 i40e_fill_default_direct_cmd_desc(&desc, 398 i40e_aqc_opc_queue_shutdown); 399 400 if (unloading) 401 cmd->driver_unloading = CPU_TO_LE32(I40E_AQ_DRIVER_UNLOADING); 402 status = i40e_asq_send_command(hw, &desc, NULL, 0, NULL); 403 404 return status; 405 } 406 407 /** 408 * i40e_aq_get_set_rss_lut 409 * @hw: pointer to the hardware structure 410 * @vsi_id: vsi fw index 411 * @pf_lut: for PF table set TRUE, for VSI table set FALSE 412 * @lut: pointer to the lut buffer provided by the caller 413 * @lut_size: size of the lut buffer 414 * @set: set TRUE to set the table, FALSE to get the table 415 * 416 * Internal function to get or set RSS look up table 417 **/ 418 static enum i40e_status_code i40e_aq_get_set_rss_lut(struct i40e_hw *hw, 419 u16 vsi_id, bool pf_lut, 420 u8 *lut, u16 lut_size, 421 bool set) 422 { 423 enum i40e_status_code status; 424 struct i40e_aq_desc desc; 425 struct i40e_aqc_get_set_rss_lut *cmd_resp = 426 (struct i40e_aqc_get_set_rss_lut *)&desc.params.raw; 427 428 if (set) 429 i40e_fill_default_direct_cmd_desc(&desc, 430 i40e_aqc_opc_set_rss_lut); 431 else 432 i40e_fill_default_direct_cmd_desc(&desc, 433 i40e_aqc_opc_get_rss_lut); 434 435 /* Indirect command */ 436 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF); 437 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_RD); 438 439 cmd_resp->vsi_id = 440 CPU_TO_LE16((u16)((vsi_id << 441 I40E_AQC_SET_RSS_LUT_VSI_ID_SHIFT) & 442 I40E_AQC_SET_RSS_LUT_VSI_ID_MASK)); 443 cmd_resp->vsi_id |= CPU_TO_LE16((u16)I40E_AQC_SET_RSS_LUT_VSI_VALID); 444 445 if (pf_lut) 446 cmd_resp->flags |= CPU_TO_LE16((u16) 447 ((I40E_AQC_SET_RSS_LUT_TABLE_TYPE_PF << 448 I40E_AQC_SET_RSS_LUT_TABLE_TYPE_SHIFT) & 449 I40E_AQC_SET_RSS_LUT_TABLE_TYPE_MASK)); 450 else 451 cmd_resp->flags |= CPU_TO_LE16((u16) 452 ((I40E_AQC_SET_RSS_LUT_TABLE_TYPE_VSI << 453 I40E_AQC_SET_RSS_LUT_TABLE_TYPE_SHIFT) & 454 I40E_AQC_SET_RSS_LUT_TABLE_TYPE_MASK)); 455 456 status = i40e_asq_send_command(hw, &desc, lut, lut_size, NULL); 457 458 return status; 459 } 460 461 /** 462 * i40e_aq_get_rss_lut 463 * @hw: pointer to the hardware structure 464 * @vsi_id: vsi fw index 465 * @pf_lut: for PF table set TRUE, for VSI table set FALSE 466 * @lut: pointer to the lut buffer provided by the caller 467 * @lut_size: size of the lut buffer 468 * 469 * get the RSS lookup table, PF or VSI type 470 **/ 471 enum i40e_status_code i40e_aq_get_rss_lut(struct i40e_hw *hw, u16 vsi_id, 472 bool pf_lut, u8 *lut, u16 lut_size) 473 { 474 return i40e_aq_get_set_rss_lut(hw, vsi_id, pf_lut, lut, lut_size, 475 FALSE); 476 } 477 478 /** 479 * i40e_aq_set_rss_lut 480 * @hw: pointer to the hardware structure 481 * @vsi_id: vsi fw index 482 * @pf_lut: for PF table set TRUE, for VSI table set FALSE 483 * @lut: pointer to the lut buffer provided by the caller 484 * @lut_size: size of the lut buffer 485 * 486 * set the RSS lookup table, PF or VSI type 487 **/ 488 enum i40e_status_code i40e_aq_set_rss_lut(struct i40e_hw *hw, u16 vsi_id, 489 bool pf_lut, u8 *lut, u16 lut_size) 490 { 491 return i40e_aq_get_set_rss_lut(hw, vsi_id, pf_lut, lut, lut_size, TRUE); 492 } 493 494 /** 495 * i40e_aq_get_set_rss_key 496 * @hw: pointer to the hw struct 497 * @vsi_id: vsi fw index 498 * @key: pointer to key info struct 499 * @set: set TRUE to set the key, FALSE to get the key 500 * 501 * get the RSS key per VSI 502 **/ 503 static enum i40e_status_code i40e_aq_get_set_rss_key(struct i40e_hw *hw, 504 u16 vsi_id, 505 struct i40e_aqc_get_set_rss_key_data *key, 506 bool set) 507 { 508 enum i40e_status_code status; 509 struct i40e_aq_desc desc; 510 struct i40e_aqc_get_set_rss_key *cmd_resp = 511 (struct i40e_aqc_get_set_rss_key *)&desc.params.raw; 512 u16 key_size = sizeof(struct i40e_aqc_get_set_rss_key_data); 513 514 if (set) 515 i40e_fill_default_direct_cmd_desc(&desc, 516 i40e_aqc_opc_set_rss_key); 517 else 518 i40e_fill_default_direct_cmd_desc(&desc, 519 i40e_aqc_opc_get_rss_key); 520 521 /* Indirect command */ 522 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF); 523 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_RD); 524 525 cmd_resp->vsi_id = 526 CPU_TO_LE16((u16)((vsi_id << 527 I40E_AQC_SET_RSS_KEY_VSI_ID_SHIFT) & 528 I40E_AQC_SET_RSS_KEY_VSI_ID_MASK)); 529 cmd_resp->vsi_id |= CPU_TO_LE16((u16)I40E_AQC_SET_RSS_KEY_VSI_VALID); 530 531 status = i40e_asq_send_command(hw, &desc, key, key_size, NULL); 532 533 return status; 534 } 535 536 /** 537 * i40e_aq_get_rss_key 538 * @hw: pointer to the hw struct 539 * @vsi_id: vsi fw index 540 * @key: pointer to key info struct 541 * 542 **/ 543 enum i40e_status_code i40e_aq_get_rss_key(struct i40e_hw *hw, 544 u16 vsi_id, 545 struct i40e_aqc_get_set_rss_key_data *key) 546 { 547 return i40e_aq_get_set_rss_key(hw, vsi_id, key, FALSE); 548 } 549 550 /** 551 * i40e_aq_set_rss_key 552 * @hw: pointer to the hw struct 553 * @vsi_id: vsi fw index 554 * @key: pointer to key info struct 555 * 556 * set the RSS key per VSI 557 **/ 558 enum i40e_status_code i40e_aq_set_rss_key(struct i40e_hw *hw, 559 u16 vsi_id, 560 struct i40e_aqc_get_set_rss_key_data *key) 561 { 562 return i40e_aq_get_set_rss_key(hw, vsi_id, key, TRUE); 563 } 564 565 /* The i40e_ptype_lookup table is used to convert from the 8-bit ptype in the 566 * hardware to a bit-field that can be used by SW to more easily determine the 567 * packet type. 568 * 569 * Macros are used to shorten the table lines and make this table human 570 * readable. 571 * 572 * We store the PTYPE in the top byte of the bit field - this is just so that 573 * we can check that the table doesn't have a row missing, as the index into 574 * the table should be the PTYPE. 575 * 576 * Typical work flow: 577 * 578 * IF NOT i40e_ptype_lookup[ptype].known 579 * THEN 580 * Packet is unknown 581 * ELSE IF i40e_ptype_lookup[ptype].outer_ip == I40E_RX_PTYPE_OUTER_IP 582 * Use the rest of the fields to look at the tunnels, inner protocols, etc 583 * ELSE 584 * Use the enum i40e_rx_l2_ptype to decode the packet type 585 * ENDIF 586 */ 587 588 /* macro to make the table lines short */ 589 #define I40E_PTT(PTYPE, OUTER_IP, OUTER_IP_VER, OUTER_FRAG, T, TE, TEF, I, PL)\ 590 { PTYPE, \ 591 1, \ 592 I40E_RX_PTYPE_OUTER_##OUTER_IP, \ 593 I40E_RX_PTYPE_OUTER_##OUTER_IP_VER, \ 594 I40E_RX_PTYPE_##OUTER_FRAG, \ 595 I40E_RX_PTYPE_TUNNEL_##T, \ 596 I40E_RX_PTYPE_TUNNEL_END_##TE, \ 597 I40E_RX_PTYPE_##TEF, \ 598 I40E_RX_PTYPE_INNER_PROT_##I, \ 599 I40E_RX_PTYPE_PAYLOAD_LAYER_##PL } 600 601 #define I40E_PTT_UNUSED_ENTRY(PTYPE) \ 602 { PTYPE, 0, 0, 0, 0, 0, 0, 0, 0, 0 } 603 604 /* shorter macros makes the table fit but are terse */ 605 #define I40E_RX_PTYPE_NOF I40E_RX_PTYPE_NOT_FRAG 606 #define I40E_RX_PTYPE_FRG I40E_RX_PTYPE_FRAG 607 #define I40E_RX_PTYPE_INNER_PROT_TS I40E_RX_PTYPE_INNER_PROT_TIMESYNC 608 609 /* Lookup table mapping the HW PTYPE to the bit field for decoding */ 610 struct i40e_rx_ptype_decoded i40e_ptype_lookup[] = { 611 /* L2 Packet types */ 612 I40E_PTT_UNUSED_ENTRY(0), 613 I40E_PTT(1, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY2), 614 I40E_PTT(2, L2, NONE, NOF, NONE, NONE, NOF, TS, PAY2), 615 I40E_PTT(3, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY2), 616 I40E_PTT_UNUSED_ENTRY(4), 617 I40E_PTT_UNUSED_ENTRY(5), 618 I40E_PTT(6, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY2), 619 I40E_PTT(7, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY2), 620 I40E_PTT_UNUSED_ENTRY(8), 621 I40E_PTT_UNUSED_ENTRY(9), 622 I40E_PTT(10, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY2), 623 I40E_PTT(11, L2, NONE, NOF, NONE, NONE, NOF, NONE, NONE), 624 I40E_PTT(12, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3), 625 I40E_PTT(13, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3), 626 I40E_PTT(14, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3), 627 I40E_PTT(15, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3), 628 I40E_PTT(16, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3), 629 I40E_PTT(17, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3), 630 I40E_PTT(18, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3), 631 I40E_PTT(19, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3), 632 I40E_PTT(20, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3), 633 I40E_PTT(21, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3), 634 635 /* Non Tunneled IPv4 */ 636 I40E_PTT(22, IP, IPV4, FRG, NONE, NONE, NOF, NONE, PAY3), 637 I40E_PTT(23, IP, IPV4, NOF, NONE, NONE, NOF, NONE, PAY3), 638 I40E_PTT(24, IP, IPV4, NOF, NONE, NONE, NOF, UDP, PAY4), 639 I40E_PTT_UNUSED_ENTRY(25), 640 I40E_PTT(26, IP, IPV4, NOF, NONE, NONE, NOF, TCP, PAY4), 641 I40E_PTT(27, IP, IPV4, NOF, NONE, NONE, NOF, SCTP, PAY4), 642 I40E_PTT(28, IP, IPV4, NOF, NONE, NONE, NOF, ICMP, PAY4), 643 644 /* IPv4 --> IPv4 */ 645 I40E_PTT(29, IP, IPV4, NOF, IP_IP, IPV4, FRG, NONE, PAY3), 646 I40E_PTT(30, IP, IPV4, NOF, IP_IP, IPV4, NOF, NONE, PAY3), 647 I40E_PTT(31, IP, IPV4, NOF, IP_IP, IPV4, NOF, UDP, PAY4), 648 I40E_PTT_UNUSED_ENTRY(32), 649 I40E_PTT(33, IP, IPV4, NOF, IP_IP, IPV4, NOF, TCP, PAY4), 650 I40E_PTT(34, IP, IPV4, NOF, IP_IP, IPV4, NOF, SCTP, PAY4), 651 I40E_PTT(35, IP, IPV4, NOF, IP_IP, IPV4, NOF, ICMP, PAY4), 652 653 /* IPv4 --> IPv6 */ 654 I40E_PTT(36, IP, IPV4, NOF, IP_IP, IPV6, FRG, NONE, PAY3), 655 I40E_PTT(37, IP, IPV4, NOF, IP_IP, IPV6, NOF, NONE, PAY3), 656 I40E_PTT(38, IP, IPV4, NOF, IP_IP, IPV6, NOF, UDP, PAY4), 657 I40E_PTT_UNUSED_ENTRY(39), 658 I40E_PTT(40, IP, IPV4, NOF, IP_IP, IPV6, NOF, TCP, PAY4), 659 I40E_PTT(41, IP, IPV4, NOF, IP_IP, IPV6, NOF, SCTP, PAY4), 660 I40E_PTT(42, IP, IPV4, NOF, IP_IP, IPV6, NOF, ICMP, PAY4), 661 662 /* IPv4 --> GRE/NAT */ 663 I40E_PTT(43, IP, IPV4, NOF, IP_GRENAT, NONE, NOF, NONE, PAY3), 664 665 /* IPv4 --> GRE/NAT --> IPv4 */ 666 I40E_PTT(44, IP, IPV4, NOF, IP_GRENAT, IPV4, FRG, NONE, PAY3), 667 I40E_PTT(45, IP, IPV4, NOF, IP_GRENAT, IPV4, NOF, NONE, PAY3), 668 I40E_PTT(46, IP, IPV4, NOF, IP_GRENAT, IPV4, NOF, UDP, PAY4), 669 I40E_PTT_UNUSED_ENTRY(47), 670 I40E_PTT(48, IP, IPV4, NOF, IP_GRENAT, IPV4, NOF, TCP, PAY4), 671 I40E_PTT(49, IP, IPV4, NOF, IP_GRENAT, IPV4, NOF, SCTP, PAY4), 672 I40E_PTT(50, IP, IPV4, NOF, IP_GRENAT, IPV4, NOF, ICMP, PAY4), 673 674 /* IPv4 --> GRE/NAT --> IPv6 */ 675 I40E_PTT(51, IP, IPV4, NOF, IP_GRENAT, IPV6, FRG, NONE, PAY3), 676 I40E_PTT(52, IP, IPV4, NOF, IP_GRENAT, IPV6, NOF, NONE, PAY3), 677 I40E_PTT(53, IP, IPV4, NOF, IP_GRENAT, IPV6, NOF, UDP, PAY4), 678 I40E_PTT_UNUSED_ENTRY(54), 679 I40E_PTT(55, IP, IPV4, NOF, IP_GRENAT, IPV6, NOF, TCP, PAY4), 680 I40E_PTT(56, IP, IPV4, NOF, IP_GRENAT, IPV6, NOF, SCTP, PAY4), 681 I40E_PTT(57, IP, IPV4, NOF, IP_GRENAT, IPV6, NOF, ICMP, PAY4), 682 683 /* IPv4 --> GRE/NAT --> MAC */ 684 I40E_PTT(58, IP, IPV4, NOF, IP_GRENAT_MAC, NONE, NOF, NONE, PAY3), 685 686 /* IPv4 --> GRE/NAT --> MAC --> IPv4 */ 687 I40E_PTT(59, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, FRG, NONE, PAY3), 688 I40E_PTT(60, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, NOF, NONE, PAY3), 689 I40E_PTT(61, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, NOF, UDP, PAY4), 690 I40E_PTT_UNUSED_ENTRY(62), 691 I40E_PTT(63, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, NOF, TCP, PAY4), 692 I40E_PTT(64, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, NOF, SCTP, PAY4), 693 I40E_PTT(65, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, NOF, ICMP, PAY4), 694 695 /* IPv4 --> GRE/NAT -> MAC --> IPv6 */ 696 I40E_PTT(66, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, FRG, NONE, PAY3), 697 I40E_PTT(67, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, NOF, NONE, PAY3), 698 I40E_PTT(68, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, NOF, UDP, PAY4), 699 I40E_PTT_UNUSED_ENTRY(69), 700 I40E_PTT(70, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, NOF, TCP, PAY4), 701 I40E_PTT(71, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, NOF, SCTP, PAY4), 702 I40E_PTT(72, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, NOF, ICMP, PAY4), 703 704 /* IPv4 --> GRE/NAT --> MAC/VLAN */ 705 I40E_PTT(73, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, NONE, NOF, NONE, PAY3), 706 707 /* IPv4 ---> GRE/NAT -> MAC/VLAN --> IPv4 */ 708 I40E_PTT(74, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, FRG, NONE, PAY3), 709 I40E_PTT(75, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, NONE, PAY3), 710 I40E_PTT(76, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, UDP, PAY4), 711 I40E_PTT_UNUSED_ENTRY(77), 712 I40E_PTT(78, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, TCP, PAY4), 713 I40E_PTT(79, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, SCTP, PAY4), 714 I40E_PTT(80, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, ICMP, PAY4), 715 716 /* IPv4 -> GRE/NAT -> MAC/VLAN --> IPv6 */ 717 I40E_PTT(81, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, FRG, NONE, PAY3), 718 I40E_PTT(82, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, NONE, PAY3), 719 I40E_PTT(83, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, UDP, PAY4), 720 I40E_PTT_UNUSED_ENTRY(84), 721 I40E_PTT(85, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, TCP, PAY4), 722 I40E_PTT(86, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, SCTP, PAY4), 723 I40E_PTT(87, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, ICMP, PAY4), 724 725 /* Non Tunneled IPv6 */ 726 I40E_PTT(88, IP, IPV6, FRG, NONE, NONE, NOF, NONE, PAY3), 727 I40E_PTT(89, IP, IPV6, NOF, NONE, NONE, NOF, NONE, PAY3), 728 I40E_PTT(90, IP, IPV6, NOF, NONE, NONE, NOF, UDP, PAY4), 729 I40E_PTT_UNUSED_ENTRY(91), 730 I40E_PTT(92, IP, IPV6, NOF, NONE, NONE, NOF, TCP, PAY4), 731 I40E_PTT(93, IP, IPV6, NOF, NONE, NONE, NOF, SCTP, PAY4), 732 I40E_PTT(94, IP, IPV6, NOF, NONE, NONE, NOF, ICMP, PAY4), 733 734 /* IPv6 --> IPv4 */ 735 I40E_PTT(95, IP, IPV6, NOF, IP_IP, IPV4, FRG, NONE, PAY3), 736 I40E_PTT(96, IP, IPV6, NOF, IP_IP, IPV4, NOF, NONE, PAY3), 737 I40E_PTT(97, IP, IPV6, NOF, IP_IP, IPV4, NOF, UDP, PAY4), 738 I40E_PTT_UNUSED_ENTRY(98), 739 I40E_PTT(99, IP, IPV6, NOF, IP_IP, IPV4, NOF, TCP, PAY4), 740 I40E_PTT(100, IP, IPV6, NOF, IP_IP, IPV4, NOF, SCTP, PAY4), 741 I40E_PTT(101, IP, IPV6, NOF, IP_IP, IPV4, NOF, ICMP, PAY4), 742 743 /* IPv6 --> IPv6 */ 744 I40E_PTT(102, IP, IPV6, NOF, IP_IP, IPV6, FRG, NONE, PAY3), 745 I40E_PTT(103, IP, IPV6, NOF, IP_IP, IPV6, NOF, NONE, PAY3), 746 I40E_PTT(104, IP, IPV6, NOF, IP_IP, IPV6, NOF, UDP, PAY4), 747 I40E_PTT_UNUSED_ENTRY(105), 748 I40E_PTT(106, IP, IPV6, NOF, IP_IP, IPV6, NOF, TCP, PAY4), 749 I40E_PTT(107, IP, IPV6, NOF, IP_IP, IPV6, NOF, SCTP, PAY4), 750 I40E_PTT(108, IP, IPV6, NOF, IP_IP, IPV6, NOF, ICMP, PAY4), 751 752 /* IPv6 --> GRE/NAT */ 753 I40E_PTT(109, IP, IPV6, NOF, IP_GRENAT, NONE, NOF, NONE, PAY3), 754 755 /* IPv6 --> GRE/NAT -> IPv4 */ 756 I40E_PTT(110, IP, IPV6, NOF, IP_GRENAT, IPV4, FRG, NONE, PAY3), 757 I40E_PTT(111, IP, IPV6, NOF, IP_GRENAT, IPV4, NOF, NONE, PAY3), 758 I40E_PTT(112, IP, IPV6, NOF, IP_GRENAT, IPV4, NOF, UDP, PAY4), 759 I40E_PTT_UNUSED_ENTRY(113), 760 I40E_PTT(114, IP, IPV6, NOF, IP_GRENAT, IPV4, NOF, TCP, PAY4), 761 I40E_PTT(115, IP, IPV6, NOF, IP_GRENAT, IPV4, NOF, SCTP, PAY4), 762 I40E_PTT(116, IP, IPV6, NOF, IP_GRENAT, IPV4, NOF, ICMP, PAY4), 763 764 /* IPv6 --> GRE/NAT -> IPv6 */ 765 I40E_PTT(117, IP, IPV6, NOF, IP_GRENAT, IPV6, FRG, NONE, PAY3), 766 I40E_PTT(118, IP, IPV6, NOF, IP_GRENAT, IPV6, NOF, NONE, PAY3), 767 I40E_PTT(119, IP, IPV6, NOF, IP_GRENAT, IPV6, NOF, UDP, PAY4), 768 I40E_PTT_UNUSED_ENTRY(120), 769 I40E_PTT(121, IP, IPV6, NOF, IP_GRENAT, IPV6, NOF, TCP, PAY4), 770 I40E_PTT(122, IP, IPV6, NOF, IP_GRENAT, IPV6, NOF, SCTP, PAY4), 771 I40E_PTT(123, IP, IPV6, NOF, IP_GRENAT, IPV6, NOF, ICMP, PAY4), 772 773 /* IPv6 --> GRE/NAT -> MAC */ 774 I40E_PTT(124, IP, IPV6, NOF, IP_GRENAT_MAC, NONE, NOF, NONE, PAY3), 775 776 /* IPv6 --> GRE/NAT -> MAC -> IPv4 */ 777 I40E_PTT(125, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, FRG, NONE, PAY3), 778 I40E_PTT(126, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, NOF, NONE, PAY3), 779 I40E_PTT(127, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, NOF, UDP, PAY4), 780 I40E_PTT_UNUSED_ENTRY(128), 781 I40E_PTT(129, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, NOF, TCP, PAY4), 782 I40E_PTT(130, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, NOF, SCTP, PAY4), 783 I40E_PTT(131, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, NOF, ICMP, PAY4), 784 785 /* IPv6 --> GRE/NAT -> MAC -> IPv6 */ 786 I40E_PTT(132, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, FRG, NONE, PAY3), 787 I40E_PTT(133, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, NOF, NONE, PAY3), 788 I40E_PTT(134, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, NOF, UDP, PAY4), 789 I40E_PTT_UNUSED_ENTRY(135), 790 I40E_PTT(136, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, NOF, TCP, PAY4), 791 I40E_PTT(137, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, NOF, SCTP, PAY4), 792 I40E_PTT(138, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, NOF, ICMP, PAY4), 793 794 /* IPv6 --> GRE/NAT -> MAC/VLAN */ 795 I40E_PTT(139, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, NONE, NOF, NONE, PAY3), 796 797 /* IPv6 --> GRE/NAT -> MAC/VLAN --> IPv4 */ 798 I40E_PTT(140, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, FRG, NONE, PAY3), 799 I40E_PTT(141, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, NONE, PAY3), 800 I40E_PTT(142, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, UDP, PAY4), 801 I40E_PTT_UNUSED_ENTRY(143), 802 I40E_PTT(144, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, TCP, PAY4), 803 I40E_PTT(145, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, SCTP, PAY4), 804 I40E_PTT(146, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, ICMP, PAY4), 805 806 /* IPv6 --> GRE/NAT -> MAC/VLAN --> IPv6 */ 807 I40E_PTT(147, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, FRG, NONE, PAY3), 808 I40E_PTT(148, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, NONE, PAY3), 809 I40E_PTT(149, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, UDP, PAY4), 810 I40E_PTT_UNUSED_ENTRY(150), 811 I40E_PTT(151, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, TCP, PAY4), 812 I40E_PTT(152, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, SCTP, PAY4), 813 I40E_PTT(153, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, ICMP, PAY4), 814 815 /* unused entries */ 816 I40E_PTT_UNUSED_ENTRY(154), 817 I40E_PTT_UNUSED_ENTRY(155), 818 I40E_PTT_UNUSED_ENTRY(156), 819 I40E_PTT_UNUSED_ENTRY(157), 820 I40E_PTT_UNUSED_ENTRY(158), 821 I40E_PTT_UNUSED_ENTRY(159), 822 823 I40E_PTT_UNUSED_ENTRY(160), 824 I40E_PTT_UNUSED_ENTRY(161), 825 I40E_PTT_UNUSED_ENTRY(162), 826 I40E_PTT_UNUSED_ENTRY(163), 827 I40E_PTT_UNUSED_ENTRY(164), 828 I40E_PTT_UNUSED_ENTRY(165), 829 I40E_PTT_UNUSED_ENTRY(166), 830 I40E_PTT_UNUSED_ENTRY(167), 831 I40E_PTT_UNUSED_ENTRY(168), 832 I40E_PTT_UNUSED_ENTRY(169), 833 834 I40E_PTT_UNUSED_ENTRY(170), 835 I40E_PTT_UNUSED_ENTRY(171), 836 I40E_PTT_UNUSED_ENTRY(172), 837 I40E_PTT_UNUSED_ENTRY(173), 838 I40E_PTT_UNUSED_ENTRY(174), 839 I40E_PTT_UNUSED_ENTRY(175), 840 I40E_PTT_UNUSED_ENTRY(176), 841 I40E_PTT_UNUSED_ENTRY(177), 842 I40E_PTT_UNUSED_ENTRY(178), 843 I40E_PTT_UNUSED_ENTRY(179), 844 845 I40E_PTT_UNUSED_ENTRY(180), 846 I40E_PTT_UNUSED_ENTRY(181), 847 I40E_PTT_UNUSED_ENTRY(182), 848 I40E_PTT_UNUSED_ENTRY(183), 849 I40E_PTT_UNUSED_ENTRY(184), 850 I40E_PTT_UNUSED_ENTRY(185), 851 I40E_PTT_UNUSED_ENTRY(186), 852 I40E_PTT_UNUSED_ENTRY(187), 853 I40E_PTT_UNUSED_ENTRY(188), 854 I40E_PTT_UNUSED_ENTRY(189), 855 856 I40E_PTT_UNUSED_ENTRY(190), 857 I40E_PTT_UNUSED_ENTRY(191), 858 I40E_PTT_UNUSED_ENTRY(192), 859 I40E_PTT_UNUSED_ENTRY(193), 860 I40E_PTT_UNUSED_ENTRY(194), 861 I40E_PTT_UNUSED_ENTRY(195), 862 I40E_PTT_UNUSED_ENTRY(196), 863 I40E_PTT_UNUSED_ENTRY(197), 864 I40E_PTT_UNUSED_ENTRY(198), 865 I40E_PTT_UNUSED_ENTRY(199), 866 867 I40E_PTT_UNUSED_ENTRY(200), 868 I40E_PTT_UNUSED_ENTRY(201), 869 I40E_PTT_UNUSED_ENTRY(202), 870 I40E_PTT_UNUSED_ENTRY(203), 871 I40E_PTT_UNUSED_ENTRY(204), 872 I40E_PTT_UNUSED_ENTRY(205), 873 I40E_PTT_UNUSED_ENTRY(206), 874 I40E_PTT_UNUSED_ENTRY(207), 875 I40E_PTT_UNUSED_ENTRY(208), 876 I40E_PTT_UNUSED_ENTRY(209), 877 878 I40E_PTT_UNUSED_ENTRY(210), 879 I40E_PTT_UNUSED_ENTRY(211), 880 I40E_PTT_UNUSED_ENTRY(212), 881 I40E_PTT_UNUSED_ENTRY(213), 882 I40E_PTT_UNUSED_ENTRY(214), 883 I40E_PTT_UNUSED_ENTRY(215), 884 I40E_PTT_UNUSED_ENTRY(216), 885 I40E_PTT_UNUSED_ENTRY(217), 886 I40E_PTT_UNUSED_ENTRY(218), 887 I40E_PTT_UNUSED_ENTRY(219), 888 889 I40E_PTT_UNUSED_ENTRY(220), 890 I40E_PTT_UNUSED_ENTRY(221), 891 I40E_PTT_UNUSED_ENTRY(222), 892 I40E_PTT_UNUSED_ENTRY(223), 893 I40E_PTT_UNUSED_ENTRY(224), 894 I40E_PTT_UNUSED_ENTRY(225), 895 I40E_PTT_UNUSED_ENTRY(226), 896 I40E_PTT_UNUSED_ENTRY(227), 897 I40E_PTT_UNUSED_ENTRY(228), 898 I40E_PTT_UNUSED_ENTRY(229), 899 900 I40E_PTT_UNUSED_ENTRY(230), 901 I40E_PTT_UNUSED_ENTRY(231), 902 I40E_PTT_UNUSED_ENTRY(232), 903 I40E_PTT_UNUSED_ENTRY(233), 904 I40E_PTT_UNUSED_ENTRY(234), 905 I40E_PTT_UNUSED_ENTRY(235), 906 I40E_PTT_UNUSED_ENTRY(236), 907 I40E_PTT_UNUSED_ENTRY(237), 908 I40E_PTT_UNUSED_ENTRY(238), 909 I40E_PTT_UNUSED_ENTRY(239), 910 911 I40E_PTT_UNUSED_ENTRY(240), 912 I40E_PTT_UNUSED_ENTRY(241), 913 I40E_PTT_UNUSED_ENTRY(242), 914 I40E_PTT_UNUSED_ENTRY(243), 915 I40E_PTT_UNUSED_ENTRY(244), 916 I40E_PTT_UNUSED_ENTRY(245), 917 I40E_PTT_UNUSED_ENTRY(246), 918 I40E_PTT_UNUSED_ENTRY(247), 919 I40E_PTT_UNUSED_ENTRY(248), 920 I40E_PTT_UNUSED_ENTRY(249), 921 922 I40E_PTT_UNUSED_ENTRY(250), 923 I40E_PTT_UNUSED_ENTRY(251), 924 I40E_PTT_UNUSED_ENTRY(252), 925 I40E_PTT_UNUSED_ENTRY(253), 926 I40E_PTT_UNUSED_ENTRY(254), 927 I40E_PTT_UNUSED_ENTRY(255) 928 }; 929 930 931 /** 932 * i40e_validate_mac_addr - Validate unicast MAC address 933 * @mac_addr: pointer to MAC address 934 * 935 * Tests a MAC address to ensure it is a valid Individual Address 936 **/ 937 enum i40e_status_code i40e_validate_mac_addr(u8 *mac_addr) 938 { 939 enum i40e_status_code status = I40E_SUCCESS; 940 941 DEBUGFUNC("i40e_validate_mac_addr"); 942 943 /* Broadcast addresses ARE multicast addresses 944 * Make sure it is not a multicast address 945 * Reject the zero address 946 */ 947 if (I40E_IS_MULTICAST(mac_addr) || 948 (mac_addr[0] == 0 && mac_addr[1] == 0 && mac_addr[2] == 0 && 949 mac_addr[3] == 0 && mac_addr[4] == 0 && mac_addr[5] == 0)) 950 status = I40E_ERR_INVALID_MAC_ADDR; 951 952 return status; 953 } 954 955 /** 956 * i40e_init_shared_code - Initialize the shared code 957 * @hw: pointer to hardware structure 958 * 959 * This assigns the MAC type and PHY code and inits the NVM. 960 * Does not touch the hardware. This function must be called prior to any 961 * other function in the shared code. The i40e_hw structure should be 962 * memset to 0 prior to calling this function. The following fields in 963 * hw structure should be filled in prior to calling this function: 964 * hw_addr, back, device_id, vendor_id, subsystem_device_id, 965 * subsystem_vendor_id, and revision_id 966 **/ 967 enum i40e_status_code i40e_init_shared_code(struct i40e_hw *hw) 968 { 969 enum i40e_status_code status = I40E_SUCCESS; 970 u32 port, ari, func_rid; 971 972 DEBUGFUNC("i40e_init_shared_code"); 973 974 i40e_set_mac_type(hw); 975 976 switch (hw->mac.type) { 977 case I40E_MAC_XL710: 978 case I40E_MAC_X722: 979 break; 980 default: 981 return I40E_ERR_DEVICE_NOT_SUPPORTED; 982 } 983 984 hw->phy.get_link_info = TRUE; 985 986 /* Determine port number and PF number*/ 987 port = (rd32(hw, I40E_PFGEN_PORTNUM) & I40E_PFGEN_PORTNUM_PORT_NUM_MASK) 988 >> I40E_PFGEN_PORTNUM_PORT_NUM_SHIFT; 989 hw->port = (u8)port; 990 ari = (rd32(hw, I40E_GLPCI_CAPSUP) & I40E_GLPCI_CAPSUP_ARI_EN_MASK) >> 991 I40E_GLPCI_CAPSUP_ARI_EN_SHIFT; 992 func_rid = rd32(hw, I40E_PF_FUNC_RID); 993 if (ari) 994 hw->pf_id = (u8)(func_rid & 0xff); 995 else 996 hw->pf_id = (u8)(func_rid & 0x7); 997 998 if (hw->mac.type == I40E_MAC_X722) 999 hw->flags |= I40E_HW_FLAG_AQ_SRCTL_ACCESS_ENABLE; 1000 1001 status = i40e_init_nvm(hw); 1002 return status; 1003 } 1004 1005 /** 1006 * i40e_aq_mac_address_read - Retrieve the MAC addresses 1007 * @hw: pointer to the hw struct 1008 * @flags: a return indicator of what addresses were added to the addr store 1009 * @addrs: the requestor's mac addr store 1010 * @cmd_details: pointer to command details structure or NULL 1011 **/ 1012 static enum i40e_status_code i40e_aq_mac_address_read(struct i40e_hw *hw, 1013 u16 *flags, 1014 struct i40e_aqc_mac_address_read_data *addrs, 1015 struct i40e_asq_cmd_details *cmd_details) 1016 { 1017 struct i40e_aq_desc desc; 1018 struct i40e_aqc_mac_address_read *cmd_data = 1019 (struct i40e_aqc_mac_address_read *)&desc.params.raw; 1020 enum i40e_status_code status; 1021 1022 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_mac_address_read); 1023 desc.flags |= CPU_TO_LE16(I40E_AQ_FLAG_BUF); 1024 1025 status = i40e_asq_send_command(hw, &desc, addrs, 1026 sizeof(*addrs), cmd_details); 1027 *flags = LE16_TO_CPU(cmd_data->command_flags); 1028 1029 return status; 1030 } 1031 1032 /** 1033 * i40e_aq_mac_address_write - Change the MAC addresses 1034 * @hw: pointer to the hw struct 1035 * @flags: indicates which MAC to be written 1036 * @mac_addr: address to write 1037 * @cmd_details: pointer to command details structure or NULL 1038 **/ 1039 enum i40e_status_code i40e_aq_mac_address_write(struct i40e_hw *hw, 1040 u16 flags, u8 *mac_addr, 1041 struct i40e_asq_cmd_details *cmd_details) 1042 { 1043 struct i40e_aq_desc desc; 1044 struct i40e_aqc_mac_address_write *cmd_data = 1045 (struct i40e_aqc_mac_address_write *)&desc.params.raw; 1046 enum i40e_status_code status; 1047 1048 i40e_fill_default_direct_cmd_desc(&desc, 1049 i40e_aqc_opc_mac_address_write); 1050 cmd_data->command_flags = CPU_TO_LE16(flags); 1051 cmd_data->mac_sah = CPU_TO_LE16((u16)mac_addr[0] << 8 | mac_addr[1]); 1052 cmd_data->mac_sal = CPU_TO_LE32(((u32)mac_addr[2] << 24) | 1053 ((u32)mac_addr[3] << 16) | 1054 ((u32)mac_addr[4] << 8) | 1055 mac_addr[5]); 1056 1057 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 1058 1059 return status; 1060 } 1061 1062 /** 1063 * i40e_get_mac_addr - get MAC address 1064 * @hw: pointer to the HW structure 1065 * @mac_addr: pointer to MAC address 1066 * 1067 * Reads the adapter's MAC address from register 1068 **/ 1069 enum i40e_status_code i40e_get_mac_addr(struct i40e_hw *hw, u8 *mac_addr) 1070 { 1071 struct i40e_aqc_mac_address_read_data addrs; 1072 enum i40e_status_code status; 1073 u16 flags = 0; 1074 1075 status = i40e_aq_mac_address_read(hw, &flags, &addrs, NULL); 1076 1077 if (flags & I40E_AQC_LAN_ADDR_VALID) 1078 i40e_memcpy(mac_addr, &addrs.pf_lan_mac, sizeof(addrs.pf_lan_mac), 1079 I40E_NONDMA_TO_NONDMA); 1080 1081 return status; 1082 } 1083 1084 /** 1085 * i40e_get_port_mac_addr - get Port MAC address 1086 * @hw: pointer to the HW structure 1087 * @mac_addr: pointer to Port MAC address 1088 * 1089 * Reads the adapter's Port MAC address 1090 **/ 1091 enum i40e_status_code i40e_get_port_mac_addr(struct i40e_hw *hw, u8 *mac_addr) 1092 { 1093 struct i40e_aqc_mac_address_read_data addrs; 1094 enum i40e_status_code status; 1095 u16 flags = 0; 1096 1097 status = i40e_aq_mac_address_read(hw, &flags, &addrs, NULL); 1098 if (status) 1099 return status; 1100 1101 if (flags & I40E_AQC_PORT_ADDR_VALID) 1102 i40e_memcpy(mac_addr, &addrs.port_mac, sizeof(addrs.port_mac), 1103 I40E_NONDMA_TO_NONDMA); 1104 else 1105 status = I40E_ERR_INVALID_MAC_ADDR; 1106 1107 return status; 1108 } 1109 1110 /** 1111 * i40e_pre_tx_queue_cfg - pre tx queue configure 1112 * @hw: pointer to the HW structure 1113 * @queue: target pf queue index 1114 * @enable: state change request 1115 * 1116 * Handles hw requirement to indicate intention to enable 1117 * or disable target queue. 1118 **/ 1119 void i40e_pre_tx_queue_cfg(struct i40e_hw *hw, u32 queue, bool enable) 1120 { 1121 u32 abs_queue_idx = hw->func_caps.base_queue + queue; 1122 u32 reg_block = 0; 1123 u32 reg_val; 1124 1125 if (abs_queue_idx >= 128) { 1126 reg_block = abs_queue_idx / 128; 1127 abs_queue_idx %= 128; 1128 } 1129 1130 reg_val = rd32(hw, I40E_GLLAN_TXPRE_QDIS(reg_block)); 1131 reg_val &= ~I40E_GLLAN_TXPRE_QDIS_QINDX_MASK; 1132 reg_val |= (abs_queue_idx << I40E_GLLAN_TXPRE_QDIS_QINDX_SHIFT); 1133 1134 if (enable) 1135 reg_val |= I40E_GLLAN_TXPRE_QDIS_CLEAR_QDIS_MASK; 1136 else 1137 reg_val |= I40E_GLLAN_TXPRE_QDIS_SET_QDIS_MASK; 1138 1139 wr32(hw, I40E_GLLAN_TXPRE_QDIS(reg_block), reg_val); 1140 } 1141 1142 /** 1143 * i40e_read_pba_string - Reads part number string from EEPROM 1144 * @hw: pointer to hardware structure 1145 * @pba_num: stores the part number string from the EEPROM 1146 * @pba_num_size: part number string buffer length 1147 * 1148 * Reads the part number string from the EEPROM. 1149 **/ 1150 enum i40e_status_code i40e_read_pba_string(struct i40e_hw *hw, u8 *pba_num, 1151 u32 pba_num_size) 1152 { 1153 enum i40e_status_code status = I40E_SUCCESS; 1154 u16 pba_word = 0; 1155 u16 pba_size = 0; 1156 u16 pba_ptr = 0; 1157 u16 i = 0; 1158 1159 status = i40e_read_nvm_word(hw, I40E_SR_PBA_FLAGS, &pba_word); 1160 if ((status != I40E_SUCCESS) || (pba_word != 0xFAFA)) { 1161 DEBUGOUT("Failed to read PBA flags or flag is invalid.\n"); 1162 return status; 1163 } 1164 1165 status = i40e_read_nvm_word(hw, I40E_SR_PBA_BLOCK_PTR, &pba_ptr); 1166 if (status != I40E_SUCCESS) { 1167 DEBUGOUT("Failed to read PBA Block pointer.\n"); 1168 return status; 1169 } 1170 1171 status = i40e_read_nvm_word(hw, pba_ptr, &pba_size); 1172 if (status != I40E_SUCCESS) { 1173 DEBUGOUT("Failed to read PBA Block size.\n"); 1174 return status; 1175 } 1176 1177 /* Subtract one to get PBA word count (PBA Size word is included in 1178 * total size) 1179 */ 1180 pba_size--; 1181 if (pba_num_size < (((u32)pba_size * 2) + 1)) { 1182 DEBUGOUT("Buffer to small for PBA data.\n"); 1183 return I40E_ERR_PARAM; 1184 } 1185 1186 for (i = 0; i < pba_size; i++) { 1187 status = i40e_read_nvm_word(hw, (pba_ptr + 1) + i, &pba_word); 1188 if (status != I40E_SUCCESS) { 1189 DEBUGOUT1("Failed to read PBA Block word %d.\n", i); 1190 return status; 1191 } 1192 1193 pba_num[(i * 2)] = (pba_word >> 8) & 0xFF; 1194 pba_num[(i * 2) + 1] = pba_word & 0xFF; 1195 } 1196 pba_num[(pba_size * 2)] = '\0'; 1197 1198 return status; 1199 } 1200 1201 /** 1202 * i40e_get_media_type - Gets media type 1203 * @hw: pointer to the hardware structure 1204 **/ 1205 static enum i40e_media_type i40e_get_media_type(struct i40e_hw *hw) 1206 { 1207 enum i40e_media_type media; 1208 1209 switch (hw->phy.link_info.phy_type) { 1210 case I40E_PHY_TYPE_10GBASE_SR: 1211 case I40E_PHY_TYPE_10GBASE_LR: 1212 case I40E_PHY_TYPE_1000BASE_SX: 1213 case I40E_PHY_TYPE_1000BASE_LX: 1214 case I40E_PHY_TYPE_40GBASE_SR4: 1215 case I40E_PHY_TYPE_40GBASE_LR4: 1216 case I40E_PHY_TYPE_25GBASE_LR: 1217 case I40E_PHY_TYPE_25GBASE_SR: 1218 media = I40E_MEDIA_TYPE_FIBER; 1219 break; 1220 case I40E_PHY_TYPE_100BASE_TX: 1221 case I40E_PHY_TYPE_1000BASE_T: 1222 case I40E_PHY_TYPE_10GBASE_T: 1223 media = I40E_MEDIA_TYPE_BASET; 1224 break; 1225 case I40E_PHY_TYPE_10GBASE_CR1_CU: 1226 case I40E_PHY_TYPE_40GBASE_CR4_CU: 1227 case I40E_PHY_TYPE_10GBASE_CR1: 1228 case I40E_PHY_TYPE_40GBASE_CR4: 1229 case I40E_PHY_TYPE_10GBASE_SFPP_CU: 1230 case I40E_PHY_TYPE_40GBASE_AOC: 1231 case I40E_PHY_TYPE_10GBASE_AOC: 1232 case I40E_PHY_TYPE_25GBASE_CR: 1233 media = I40E_MEDIA_TYPE_DA; 1234 break; 1235 case I40E_PHY_TYPE_1000BASE_KX: 1236 case I40E_PHY_TYPE_10GBASE_KX4: 1237 case I40E_PHY_TYPE_10GBASE_KR: 1238 case I40E_PHY_TYPE_40GBASE_KR4: 1239 case I40E_PHY_TYPE_20GBASE_KR2: 1240 case I40E_PHY_TYPE_25GBASE_KR: 1241 media = I40E_MEDIA_TYPE_BACKPLANE; 1242 break; 1243 case I40E_PHY_TYPE_SGMII: 1244 case I40E_PHY_TYPE_XAUI: 1245 case I40E_PHY_TYPE_XFI: 1246 case I40E_PHY_TYPE_XLAUI: 1247 case I40E_PHY_TYPE_XLPPI: 1248 default: 1249 media = I40E_MEDIA_TYPE_UNKNOWN; 1250 break; 1251 } 1252 1253 return media; 1254 } 1255 1256 #define I40E_PF_RESET_WAIT_COUNT 200 1257 /** 1258 * i40e_pf_reset - Reset the PF 1259 * @hw: pointer to the hardware structure 1260 * 1261 * Assuming someone else has triggered a global reset, 1262 * assure the global reset is complete and then reset the PF 1263 **/ 1264 enum i40e_status_code i40e_pf_reset(struct i40e_hw *hw) 1265 { 1266 u32 cnt = 0; 1267 u32 cnt1 = 0; 1268 u32 reg = 0; 1269 u32 grst_del; 1270 1271 /* Poll for Global Reset steady state in case of recent GRST. 1272 * The grst delay value is in 100ms units, and we'll wait a 1273 * couple counts longer to be sure we don't just miss the end. 1274 */ 1275 grst_del = (rd32(hw, I40E_GLGEN_RSTCTL) & 1276 I40E_GLGEN_RSTCTL_GRSTDEL_MASK) >> 1277 I40E_GLGEN_RSTCTL_GRSTDEL_SHIFT; 1278 1279 grst_del = grst_del * 20; 1280 1281 for (cnt = 0; cnt < grst_del; cnt++) { 1282 reg = rd32(hw, I40E_GLGEN_RSTAT); 1283 if (!(reg & I40E_GLGEN_RSTAT_DEVSTATE_MASK)) 1284 break; 1285 i40e_msec_delay(100); 1286 } 1287 if (reg & I40E_GLGEN_RSTAT_DEVSTATE_MASK) { 1288 DEBUGOUT("Global reset polling failed to complete.\n"); 1289 return I40E_ERR_RESET_FAILED; 1290 } 1291 1292 /* Now Wait for the FW to be ready */ 1293 for (cnt1 = 0; cnt1 < I40E_PF_RESET_WAIT_COUNT; cnt1++) { 1294 reg = rd32(hw, I40E_GLNVM_ULD); 1295 reg &= (I40E_GLNVM_ULD_CONF_CORE_DONE_MASK | 1296 I40E_GLNVM_ULD_CONF_GLOBAL_DONE_MASK); 1297 if (reg == (I40E_GLNVM_ULD_CONF_CORE_DONE_MASK | 1298 I40E_GLNVM_ULD_CONF_GLOBAL_DONE_MASK)) { 1299 DEBUGOUT1("Core and Global modules ready %d\n", cnt1); 1300 break; 1301 } 1302 i40e_msec_delay(10); 1303 } 1304 if (!(reg & (I40E_GLNVM_ULD_CONF_CORE_DONE_MASK | 1305 I40E_GLNVM_ULD_CONF_GLOBAL_DONE_MASK))) { 1306 DEBUGOUT("wait for FW Reset complete timedout\n"); 1307 DEBUGOUT1("I40E_GLNVM_ULD = 0x%x\n", reg); 1308 return I40E_ERR_RESET_FAILED; 1309 } 1310 1311 /* If there was a Global Reset in progress when we got here, 1312 * we don't need to do the PF Reset 1313 */ 1314 if (!cnt) { 1315 reg = rd32(hw, I40E_PFGEN_CTRL); 1316 wr32(hw, I40E_PFGEN_CTRL, 1317 (reg | I40E_PFGEN_CTRL_PFSWR_MASK)); 1318 for (cnt = 0; cnt < I40E_PF_RESET_WAIT_COUNT; cnt++) { 1319 reg = rd32(hw, I40E_PFGEN_CTRL); 1320 if (!(reg & I40E_PFGEN_CTRL_PFSWR_MASK)) 1321 break; 1322 i40e_msec_delay(1); 1323 } 1324 if (reg & I40E_PFGEN_CTRL_PFSWR_MASK) { 1325 DEBUGOUT("PF reset polling failed to complete.\n"); 1326 return I40E_ERR_RESET_FAILED; 1327 } 1328 } 1329 1330 i40e_clear_pxe_mode(hw); 1331 1332 1333 return I40E_SUCCESS; 1334 } 1335 1336 /** 1337 * i40e_clear_hw - clear out any left over hw state 1338 * @hw: pointer to the hw struct 1339 * 1340 * Clear queues and interrupts, typically called at init time, 1341 * but after the capabilities have been found so we know how many 1342 * queues and msix vectors have been allocated. 1343 **/ 1344 void i40e_clear_hw(struct i40e_hw *hw) 1345 { 1346 u32 num_queues, base_queue; 1347 u32 num_pf_int; 1348 u32 num_vf_int; 1349 u32 num_vfs; 1350 u32 i, j; 1351 u32 val; 1352 u32 eol = 0x7ff; 1353 1354 /* get number of interrupts, queues, and vfs */ 1355 val = rd32(hw, I40E_GLPCI_CNF2); 1356 num_pf_int = (val & I40E_GLPCI_CNF2_MSI_X_PF_N_MASK) >> 1357 I40E_GLPCI_CNF2_MSI_X_PF_N_SHIFT; 1358 num_vf_int = (val & I40E_GLPCI_CNF2_MSI_X_VF_N_MASK) >> 1359 I40E_GLPCI_CNF2_MSI_X_VF_N_SHIFT; 1360 1361 val = rd32(hw, I40E_PFLAN_QALLOC); 1362 base_queue = (val & I40E_PFLAN_QALLOC_FIRSTQ_MASK) >> 1363 I40E_PFLAN_QALLOC_FIRSTQ_SHIFT; 1364 j = (val & I40E_PFLAN_QALLOC_LASTQ_MASK) >> 1365 I40E_PFLAN_QALLOC_LASTQ_SHIFT; 1366 if (val & I40E_PFLAN_QALLOC_VALID_MASK) 1367 num_queues = (j - base_queue) + 1; 1368 else 1369 num_queues = 0; 1370 1371 val = rd32(hw, I40E_PF_VT_PFALLOC); 1372 i = (val & I40E_PF_VT_PFALLOC_FIRSTVF_MASK) >> 1373 I40E_PF_VT_PFALLOC_FIRSTVF_SHIFT; 1374 j = (val & I40E_PF_VT_PFALLOC_LASTVF_MASK) >> 1375 I40E_PF_VT_PFALLOC_LASTVF_SHIFT; 1376 if (val & I40E_PF_VT_PFALLOC_VALID_MASK) 1377 num_vfs = (j - i) + 1; 1378 else 1379 num_vfs = 0; 1380 1381 /* stop all the interrupts */ 1382 wr32(hw, I40E_PFINT_ICR0_ENA, 0); 1383 val = 0x3 << I40E_PFINT_DYN_CTLN_ITR_INDX_SHIFT; 1384 for (i = 0; i < num_pf_int - 2; i++) 1385 wr32(hw, I40E_PFINT_DYN_CTLN(i), val); 1386 1387 /* Set the FIRSTQ_INDX field to 0x7FF in PFINT_LNKLSTx */ 1388 val = eol << I40E_PFINT_LNKLST0_FIRSTQ_INDX_SHIFT; 1389 wr32(hw, I40E_PFINT_LNKLST0, val); 1390 for (i = 0; i < num_pf_int - 2; i++) 1391 wr32(hw, I40E_PFINT_LNKLSTN(i), val); 1392 val = eol << I40E_VPINT_LNKLST0_FIRSTQ_INDX_SHIFT; 1393 for (i = 0; i < num_vfs; i++) 1394 wr32(hw, I40E_VPINT_LNKLST0(i), val); 1395 for (i = 0; i < num_vf_int - 2; i++) 1396 wr32(hw, I40E_VPINT_LNKLSTN(i), val); 1397 1398 /* warn the HW of the coming Tx disables */ 1399 for (i = 0; i < num_queues; i++) { 1400 u32 abs_queue_idx = base_queue + i; 1401 u32 reg_block = 0; 1402 1403 if (abs_queue_idx >= 128) { 1404 reg_block = abs_queue_idx / 128; 1405 abs_queue_idx %= 128; 1406 } 1407 1408 val = rd32(hw, I40E_GLLAN_TXPRE_QDIS(reg_block)); 1409 val &= ~I40E_GLLAN_TXPRE_QDIS_QINDX_MASK; 1410 val |= (abs_queue_idx << I40E_GLLAN_TXPRE_QDIS_QINDX_SHIFT); 1411 val |= I40E_GLLAN_TXPRE_QDIS_SET_QDIS_MASK; 1412 1413 wr32(hw, I40E_GLLAN_TXPRE_QDIS(reg_block), val); 1414 } 1415 i40e_usec_delay(400); 1416 1417 /* stop all the queues */ 1418 for (i = 0; i < num_queues; i++) { 1419 wr32(hw, I40E_QINT_TQCTL(i), 0); 1420 wr32(hw, I40E_QTX_ENA(i), 0); 1421 wr32(hw, I40E_QINT_RQCTL(i), 0); 1422 wr32(hw, I40E_QRX_ENA(i), 0); 1423 } 1424 1425 /* short wait for all queue disables to settle */ 1426 i40e_usec_delay(50); 1427 } 1428 1429 /** 1430 * i40e_clear_pxe_mode - clear pxe operations mode 1431 * @hw: pointer to the hw struct 1432 * 1433 * Make sure all PXE mode settings are cleared, including things 1434 * like descriptor fetch/write-back mode. 1435 **/ 1436 void i40e_clear_pxe_mode(struct i40e_hw *hw) 1437 { 1438 if (i40e_check_asq_alive(hw)) 1439 i40e_aq_clear_pxe_mode(hw, NULL); 1440 } 1441 1442 /** 1443 * i40e_led_is_mine - helper to find matching led 1444 * @hw: pointer to the hw struct 1445 * @idx: index into GPIO registers 1446 * 1447 * returns: 0 if no match, otherwise the value of the GPIO_CTL register 1448 */ 1449 static u32 i40e_led_is_mine(struct i40e_hw *hw, int idx) 1450 { 1451 u32 gpio_val = 0; 1452 u32 port; 1453 1454 if (!hw->func_caps.led[idx]) 1455 return 0; 1456 1457 gpio_val = rd32(hw, I40E_GLGEN_GPIO_CTL(idx)); 1458 port = (gpio_val & I40E_GLGEN_GPIO_CTL_PRT_NUM_MASK) >> 1459 I40E_GLGEN_GPIO_CTL_PRT_NUM_SHIFT; 1460 1461 /* if PRT_NUM_NA is 1 then this LED is not port specific, OR 1462 * if it is not our port then ignore 1463 */ 1464 if ((gpio_val & I40E_GLGEN_GPIO_CTL_PRT_NUM_NA_MASK) || 1465 (port != hw->port)) 1466 return 0; 1467 1468 return gpio_val; 1469 } 1470 1471 #define I40E_COMBINED_ACTIVITY 0xA 1472 #define I40E_FILTER_ACTIVITY 0xE 1473 #define I40E_LINK_ACTIVITY 0xC 1474 #define I40E_MAC_ACTIVITY 0xD 1475 #define I40E_LED0 22 1476 1477 /** 1478 * i40e_led_get - return current on/off mode 1479 * @hw: pointer to the hw struct 1480 * 1481 * The value returned is the 'mode' field as defined in the 1482 * GPIO register definitions: 0x0 = off, 0xf = on, and other 1483 * values are variations of possible behaviors relating to 1484 * blink, link, and wire. 1485 **/ 1486 u32 i40e_led_get(struct i40e_hw *hw) 1487 { 1488 u32 current_mode = 0; 1489 u32 mode = 0; 1490 int i; 1491 1492 /* as per the documentation GPIO 22-29 are the LED 1493 * GPIO pins named LED0..LED7 1494 */ 1495 for (i = I40E_LED0; i <= I40E_GLGEN_GPIO_CTL_MAX_INDEX; i++) { 1496 u32 gpio_val = i40e_led_is_mine(hw, i); 1497 1498 if (!gpio_val) 1499 continue; 1500 1501 /* ignore gpio LED src mode entries related to the activity 1502 * LEDs 1503 */ 1504 current_mode = ((gpio_val & I40E_GLGEN_GPIO_CTL_LED_MODE_MASK) 1505 >> I40E_GLGEN_GPIO_CTL_LED_MODE_SHIFT); 1506 switch (current_mode) { 1507 case I40E_COMBINED_ACTIVITY: 1508 case I40E_FILTER_ACTIVITY: 1509 case I40E_MAC_ACTIVITY: 1510 continue; 1511 default: 1512 break; 1513 } 1514 1515 mode = (gpio_val & I40E_GLGEN_GPIO_CTL_LED_MODE_MASK) >> 1516 I40E_GLGEN_GPIO_CTL_LED_MODE_SHIFT; 1517 break; 1518 } 1519 1520 return mode; 1521 } 1522 1523 /** 1524 * i40e_led_set - set new on/off mode 1525 * @hw: pointer to the hw struct 1526 * @mode: 0=off, 0xf=on (else see manual for mode details) 1527 * @blink: TRUE if the LED should blink when on, FALSE if steady 1528 * 1529 * if this function is used to turn on the blink it should 1530 * be used to disable the blink when restoring the original state. 1531 **/ 1532 void i40e_led_set(struct i40e_hw *hw, u32 mode, bool blink) 1533 { 1534 u32 current_mode = 0; 1535 int i; 1536 1537 if (mode & 0xfffffff0) 1538 DEBUGOUT1("invalid mode passed in %X\n", mode); 1539 1540 /* as per the documentation GPIO 22-29 are the LED 1541 * GPIO pins named LED0..LED7 1542 */ 1543 for (i = I40E_LED0; i <= I40E_GLGEN_GPIO_CTL_MAX_INDEX; i++) { 1544 u32 gpio_val = i40e_led_is_mine(hw, i); 1545 1546 if (!gpio_val) 1547 continue; 1548 1549 /* ignore gpio LED src mode entries related to the activity 1550 * LEDs 1551 */ 1552 current_mode = ((gpio_val & I40E_GLGEN_GPIO_CTL_LED_MODE_MASK) 1553 >> I40E_GLGEN_GPIO_CTL_LED_MODE_SHIFT); 1554 switch (current_mode) { 1555 case I40E_COMBINED_ACTIVITY: 1556 case I40E_FILTER_ACTIVITY: 1557 case I40E_MAC_ACTIVITY: 1558 continue; 1559 default: 1560 break; 1561 } 1562 1563 gpio_val &= ~I40E_GLGEN_GPIO_CTL_LED_MODE_MASK; 1564 /* this & is a bit of paranoia, but serves as a range check */ 1565 gpio_val |= ((mode << I40E_GLGEN_GPIO_CTL_LED_MODE_SHIFT) & 1566 I40E_GLGEN_GPIO_CTL_LED_MODE_MASK); 1567 1568 if (mode == I40E_LINK_ACTIVITY) 1569 blink = FALSE; 1570 1571 if (blink) 1572 gpio_val |= BIT(I40E_GLGEN_GPIO_CTL_LED_BLINK_SHIFT); 1573 else 1574 gpio_val &= ~BIT(I40E_GLGEN_GPIO_CTL_LED_BLINK_SHIFT); 1575 1576 wr32(hw, I40E_GLGEN_GPIO_CTL(i), gpio_val); 1577 break; 1578 } 1579 } 1580 1581 /* Admin command wrappers */ 1582 1583 /** 1584 * i40e_aq_get_phy_capabilities 1585 * @hw: pointer to the hw struct 1586 * @abilities: structure for PHY capabilities to be filled 1587 * @qualified_modules: report Qualified Modules 1588 * @report_init: report init capabilities (active are default) 1589 * @cmd_details: pointer to command details structure or NULL 1590 * 1591 * Returns the various PHY abilities supported on the Port. 1592 **/ 1593 enum i40e_status_code i40e_aq_get_phy_capabilities(struct i40e_hw *hw, 1594 bool qualified_modules, bool report_init, 1595 struct i40e_aq_get_phy_abilities_resp *abilities, 1596 struct i40e_asq_cmd_details *cmd_details) 1597 { 1598 struct i40e_aq_desc desc; 1599 enum i40e_status_code status; 1600 u16 abilities_size = sizeof(struct i40e_aq_get_phy_abilities_resp); 1601 1602 if (!abilities) 1603 return I40E_ERR_PARAM; 1604 1605 i40e_fill_default_direct_cmd_desc(&desc, 1606 i40e_aqc_opc_get_phy_abilities); 1607 1608 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF); 1609 if (abilities_size > I40E_AQ_LARGE_BUF) 1610 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB); 1611 1612 if (qualified_modules) 1613 desc.params.external.param0 |= 1614 CPU_TO_LE32(I40E_AQ_PHY_REPORT_QUALIFIED_MODULES); 1615 1616 if (report_init) 1617 desc.params.external.param0 |= 1618 CPU_TO_LE32(I40E_AQ_PHY_REPORT_INITIAL_VALUES); 1619 1620 status = i40e_asq_send_command(hw, &desc, abilities, abilities_size, 1621 cmd_details); 1622 1623 if (hw->aq.asq_last_status == I40E_AQ_RC_EIO) 1624 status = I40E_ERR_UNKNOWN_PHY; 1625 1626 if (report_init) { 1627 hw->phy.phy_types = LE32_TO_CPU(abilities->phy_type); 1628 hw->phy.phy_types |= ((u64)abilities->phy_type_ext << 32); 1629 } 1630 1631 return status; 1632 } 1633 1634 /** 1635 * i40e_aq_set_phy_config 1636 * @hw: pointer to the hw struct 1637 * @config: structure with PHY configuration to be set 1638 * @cmd_details: pointer to command details structure or NULL 1639 * 1640 * Set the various PHY configuration parameters 1641 * supported on the Port.One or more of the Set PHY config parameters may be 1642 * ignored in an MFP mode as the PF may not have the privilege to set some 1643 * of the PHY Config parameters. This status will be indicated by the 1644 * command response. 1645 **/ 1646 enum i40e_status_code i40e_aq_set_phy_config(struct i40e_hw *hw, 1647 struct i40e_aq_set_phy_config *config, 1648 struct i40e_asq_cmd_details *cmd_details) 1649 { 1650 struct i40e_aq_desc desc; 1651 struct i40e_aq_set_phy_config *cmd = 1652 (struct i40e_aq_set_phy_config *)&desc.params.raw; 1653 enum i40e_status_code status; 1654 1655 if (!config) 1656 return I40E_ERR_PARAM; 1657 1658 i40e_fill_default_direct_cmd_desc(&desc, 1659 i40e_aqc_opc_set_phy_config); 1660 1661 *cmd = *config; 1662 1663 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 1664 1665 return status; 1666 } 1667 1668 /** 1669 * i40e_set_fc 1670 * @hw: pointer to the hw struct 1671 * 1672 * Set the requested flow control mode using set_phy_config. 1673 **/ 1674 enum i40e_status_code i40e_set_fc(struct i40e_hw *hw, u8 *aq_failures, 1675 bool atomic_restart) 1676 { 1677 enum i40e_fc_mode fc_mode = hw->fc.requested_mode; 1678 struct i40e_aq_get_phy_abilities_resp abilities; 1679 struct i40e_aq_set_phy_config config; 1680 enum i40e_status_code status; 1681 u8 pause_mask = 0x0; 1682 1683 *aq_failures = 0x0; 1684 1685 switch (fc_mode) { 1686 case I40E_FC_FULL: 1687 pause_mask |= I40E_AQ_PHY_FLAG_PAUSE_TX; 1688 pause_mask |= I40E_AQ_PHY_FLAG_PAUSE_RX; 1689 break; 1690 case I40E_FC_RX_PAUSE: 1691 pause_mask |= I40E_AQ_PHY_FLAG_PAUSE_RX; 1692 break; 1693 case I40E_FC_TX_PAUSE: 1694 pause_mask |= I40E_AQ_PHY_FLAG_PAUSE_TX; 1695 break; 1696 default: 1697 break; 1698 } 1699 1700 /* Get the current phy config */ 1701 status = i40e_aq_get_phy_capabilities(hw, FALSE, false, &abilities, 1702 NULL); 1703 if (status) { 1704 *aq_failures |= I40E_SET_FC_AQ_FAIL_GET; 1705 return status; 1706 } 1707 1708 memset(&config, 0, sizeof(config)); 1709 /* clear the old pause settings */ 1710 config.abilities = abilities.abilities & ~(I40E_AQ_PHY_FLAG_PAUSE_TX) & 1711 ~(I40E_AQ_PHY_FLAG_PAUSE_RX); 1712 /* set the new abilities */ 1713 config.abilities |= pause_mask; 1714 /* If the abilities have changed, then set the new config */ 1715 if (config.abilities != abilities.abilities) { 1716 /* Auto restart link so settings take effect */ 1717 if (atomic_restart) 1718 config.abilities |= I40E_AQ_PHY_ENABLE_ATOMIC_LINK; 1719 /* Copy over all the old settings */ 1720 config.phy_type = abilities.phy_type; 1721 config.phy_type_ext = abilities.phy_type_ext; 1722 config.link_speed = abilities.link_speed; 1723 config.eee_capability = abilities.eee_capability; 1724 config.eeer = abilities.eeer_val; 1725 config.low_power_ctrl = abilities.d3_lpan; 1726 status = i40e_aq_set_phy_config(hw, &config, NULL); 1727 1728 if (status) 1729 *aq_failures |= I40E_SET_FC_AQ_FAIL_SET; 1730 } 1731 /* Update the link info */ 1732 status = i40e_update_link_info(hw); 1733 if (status) { 1734 /* Wait a little bit (on 40G cards it sometimes takes a really 1735 * long time for link to come back from the atomic reset) 1736 * and try once more 1737 */ 1738 i40e_msec_delay(1000); 1739 status = i40e_update_link_info(hw); 1740 } 1741 if (status) 1742 *aq_failures |= I40E_SET_FC_AQ_FAIL_UPDATE; 1743 1744 return status; 1745 } 1746 1747 /** 1748 * i40e_aq_set_mac_config 1749 * @hw: pointer to the hw struct 1750 * @max_frame_size: Maximum Frame Size to be supported by the port 1751 * @crc_en: Tell HW to append a CRC to outgoing frames 1752 * @pacing: Pacing configurations 1753 * @cmd_details: pointer to command details structure or NULL 1754 * 1755 * Configure MAC settings for frame size, jumbo frame support and the 1756 * addition of a CRC by the hardware. 1757 **/ 1758 enum i40e_status_code i40e_aq_set_mac_config(struct i40e_hw *hw, 1759 u16 max_frame_size, 1760 bool crc_en, u16 pacing, 1761 struct i40e_asq_cmd_details *cmd_details) 1762 { 1763 struct i40e_aq_desc desc; 1764 struct i40e_aq_set_mac_config *cmd = 1765 (struct i40e_aq_set_mac_config *)&desc.params.raw; 1766 enum i40e_status_code status; 1767 1768 if (max_frame_size == 0) 1769 return I40E_ERR_PARAM; 1770 1771 i40e_fill_default_direct_cmd_desc(&desc, 1772 i40e_aqc_opc_set_mac_config); 1773 1774 cmd->max_frame_size = CPU_TO_LE16(max_frame_size); 1775 cmd->params = ((u8)pacing & 0x0F) << 3; 1776 if (crc_en) 1777 cmd->params |= I40E_AQ_SET_MAC_CONFIG_CRC_EN; 1778 1779 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 1780 1781 return status; 1782 } 1783 1784 /** 1785 * i40e_aq_clear_pxe_mode 1786 * @hw: pointer to the hw struct 1787 * @cmd_details: pointer to command details structure or NULL 1788 * 1789 * Tell the firmware that the driver is taking over from PXE 1790 **/ 1791 enum i40e_status_code i40e_aq_clear_pxe_mode(struct i40e_hw *hw, 1792 struct i40e_asq_cmd_details *cmd_details) 1793 { 1794 enum i40e_status_code status; 1795 struct i40e_aq_desc desc; 1796 struct i40e_aqc_clear_pxe *cmd = 1797 (struct i40e_aqc_clear_pxe *)&desc.params.raw; 1798 1799 i40e_fill_default_direct_cmd_desc(&desc, 1800 i40e_aqc_opc_clear_pxe_mode); 1801 1802 cmd->rx_cnt = 0x2; 1803 1804 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 1805 1806 wr32(hw, I40E_GLLAN_RCTL_0, 0x1); 1807 1808 return status; 1809 } 1810 1811 /** 1812 * i40e_aq_set_link_restart_an 1813 * @hw: pointer to the hw struct 1814 * @enable_link: if TRUE: enable link, if FALSE: disable link 1815 * @cmd_details: pointer to command details structure or NULL 1816 * 1817 * Sets up the link and restarts the Auto-Negotiation over the link. 1818 **/ 1819 enum i40e_status_code i40e_aq_set_link_restart_an(struct i40e_hw *hw, 1820 bool enable_link, struct i40e_asq_cmd_details *cmd_details) 1821 { 1822 struct i40e_aq_desc desc; 1823 struct i40e_aqc_set_link_restart_an *cmd = 1824 (struct i40e_aqc_set_link_restart_an *)&desc.params.raw; 1825 enum i40e_status_code status; 1826 1827 i40e_fill_default_direct_cmd_desc(&desc, 1828 i40e_aqc_opc_set_link_restart_an); 1829 1830 cmd->command = I40E_AQ_PHY_RESTART_AN; 1831 if (enable_link) 1832 cmd->command |= I40E_AQ_PHY_LINK_ENABLE; 1833 else 1834 cmd->command &= ~I40E_AQ_PHY_LINK_ENABLE; 1835 1836 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 1837 1838 return status; 1839 } 1840 1841 /** 1842 * i40e_aq_get_link_info 1843 * @hw: pointer to the hw struct 1844 * @enable_lse: enable/disable LinkStatusEvent reporting 1845 * @link: pointer to link status structure - optional 1846 * @cmd_details: pointer to command details structure or NULL 1847 * 1848 * Returns the link status of the adapter. 1849 **/ 1850 enum i40e_status_code i40e_aq_get_link_info(struct i40e_hw *hw, 1851 bool enable_lse, struct i40e_link_status *link, 1852 struct i40e_asq_cmd_details *cmd_details) 1853 { 1854 struct i40e_aq_desc desc; 1855 struct i40e_aqc_get_link_status *resp = 1856 (struct i40e_aqc_get_link_status *)&desc.params.raw; 1857 struct i40e_link_status *hw_link_info = &hw->phy.link_info; 1858 enum i40e_status_code status; 1859 bool tx_pause, rx_pause; 1860 u16 command_flags; 1861 1862 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_get_link_status); 1863 1864 if (enable_lse) 1865 command_flags = I40E_AQ_LSE_ENABLE; 1866 else 1867 command_flags = I40E_AQ_LSE_DISABLE; 1868 resp->command_flags = CPU_TO_LE16(command_flags); 1869 1870 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 1871 1872 if (status != I40E_SUCCESS) 1873 goto aq_get_link_info_exit; 1874 1875 /* save off old link status information */ 1876 i40e_memcpy(&hw->phy.link_info_old, hw_link_info, 1877 sizeof(*hw_link_info), I40E_NONDMA_TO_NONDMA); 1878 1879 /* update link status */ 1880 hw_link_info->phy_type = (enum i40e_aq_phy_type)resp->phy_type; 1881 hw->phy.media_type = i40e_get_media_type(hw); 1882 hw_link_info->link_speed = (enum i40e_aq_link_speed)resp->link_speed; 1883 hw_link_info->link_info = resp->link_info; 1884 hw_link_info->an_info = resp->an_info; 1885 hw_link_info->ext_info = resp->ext_info; 1886 hw_link_info->loopback = resp->loopback; 1887 hw_link_info->max_frame_size = LE16_TO_CPU(resp->max_frame_size); 1888 hw_link_info->pacing = resp->config & I40E_AQ_CONFIG_PACING_MASK; 1889 1890 /* update fc info */ 1891 tx_pause = !!(resp->an_info & I40E_AQ_LINK_PAUSE_TX); 1892 rx_pause = !!(resp->an_info & I40E_AQ_LINK_PAUSE_RX); 1893 if (tx_pause & rx_pause) 1894 hw->fc.current_mode = I40E_FC_FULL; 1895 else if (tx_pause) 1896 hw->fc.current_mode = I40E_FC_TX_PAUSE; 1897 else if (rx_pause) 1898 hw->fc.current_mode = I40E_FC_RX_PAUSE; 1899 else 1900 hw->fc.current_mode = I40E_FC_NONE; 1901 1902 if (resp->config & I40E_AQ_CONFIG_CRC_ENA) 1903 hw_link_info->crc_enable = TRUE; 1904 else 1905 hw_link_info->crc_enable = FALSE; 1906 1907 if (resp->command_flags & CPU_TO_LE16(I40E_AQ_LSE_IS_ENABLED)) 1908 hw_link_info->lse_enable = TRUE; 1909 else 1910 hw_link_info->lse_enable = FALSE; 1911 1912 if ((hw->mac.type == I40E_MAC_XL710) && 1913 (hw->aq.fw_maj_ver < 4 || (hw->aq.fw_maj_ver == 4 && 1914 hw->aq.fw_min_ver < 40)) && hw_link_info->phy_type == 0xE) 1915 hw_link_info->phy_type = I40E_PHY_TYPE_10GBASE_SFPP_CU; 1916 1917 /* save link status information */ 1918 if (link) 1919 i40e_memcpy(link, hw_link_info, sizeof(*hw_link_info), 1920 I40E_NONDMA_TO_NONDMA); 1921 1922 /* flag cleared so helper functions don't call AQ again */ 1923 hw->phy.get_link_info = FALSE; 1924 1925 aq_get_link_info_exit: 1926 return status; 1927 } 1928 1929 /** 1930 * i40e_aq_set_phy_int_mask 1931 * @hw: pointer to the hw struct 1932 * @mask: interrupt mask to be set 1933 * @cmd_details: pointer to command details structure or NULL 1934 * 1935 * Set link interrupt mask. 1936 **/ 1937 enum i40e_status_code i40e_aq_set_phy_int_mask(struct i40e_hw *hw, 1938 u16 mask, 1939 struct i40e_asq_cmd_details *cmd_details) 1940 { 1941 struct i40e_aq_desc desc; 1942 struct i40e_aqc_set_phy_int_mask *cmd = 1943 (struct i40e_aqc_set_phy_int_mask *)&desc.params.raw; 1944 enum i40e_status_code status; 1945 1946 i40e_fill_default_direct_cmd_desc(&desc, 1947 i40e_aqc_opc_set_phy_int_mask); 1948 1949 cmd->event_mask = CPU_TO_LE16(mask); 1950 1951 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 1952 1953 return status; 1954 } 1955 1956 /** 1957 * i40e_aq_get_local_advt_reg 1958 * @hw: pointer to the hw struct 1959 * @advt_reg: local AN advertisement register value 1960 * @cmd_details: pointer to command details structure or NULL 1961 * 1962 * Get the Local AN advertisement register value. 1963 **/ 1964 enum i40e_status_code i40e_aq_get_local_advt_reg(struct i40e_hw *hw, 1965 u64 *advt_reg, 1966 struct i40e_asq_cmd_details *cmd_details) 1967 { 1968 struct i40e_aq_desc desc; 1969 struct i40e_aqc_an_advt_reg *resp = 1970 (struct i40e_aqc_an_advt_reg *)&desc.params.raw; 1971 enum i40e_status_code status; 1972 1973 i40e_fill_default_direct_cmd_desc(&desc, 1974 i40e_aqc_opc_get_local_advt_reg); 1975 1976 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 1977 1978 if (status != I40E_SUCCESS) 1979 goto aq_get_local_advt_reg_exit; 1980 1981 *advt_reg = (u64)(LE16_TO_CPU(resp->local_an_reg1)) << 32; 1982 *advt_reg |= LE32_TO_CPU(resp->local_an_reg0); 1983 1984 aq_get_local_advt_reg_exit: 1985 return status; 1986 } 1987 1988 /** 1989 * i40e_aq_set_local_advt_reg 1990 * @hw: pointer to the hw struct 1991 * @advt_reg: local AN advertisement register value 1992 * @cmd_details: pointer to command details structure or NULL 1993 * 1994 * Get the Local AN advertisement register value. 1995 **/ 1996 enum i40e_status_code i40e_aq_set_local_advt_reg(struct i40e_hw *hw, 1997 u64 advt_reg, 1998 struct i40e_asq_cmd_details *cmd_details) 1999 { 2000 struct i40e_aq_desc desc; 2001 struct i40e_aqc_an_advt_reg *cmd = 2002 (struct i40e_aqc_an_advt_reg *)&desc.params.raw; 2003 enum i40e_status_code status; 2004 2005 i40e_fill_default_direct_cmd_desc(&desc, 2006 i40e_aqc_opc_get_local_advt_reg); 2007 2008 cmd->local_an_reg0 = CPU_TO_LE32(I40E_LO_DWORD(advt_reg)); 2009 cmd->local_an_reg1 = CPU_TO_LE16(I40E_HI_DWORD(advt_reg)); 2010 2011 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 2012 2013 return status; 2014 } 2015 2016 /** 2017 * i40e_aq_get_partner_advt 2018 * @hw: pointer to the hw struct 2019 * @advt_reg: AN partner advertisement register value 2020 * @cmd_details: pointer to command details structure or NULL 2021 * 2022 * Get the link partner AN advertisement register value. 2023 **/ 2024 enum i40e_status_code i40e_aq_get_partner_advt(struct i40e_hw *hw, 2025 u64 *advt_reg, 2026 struct i40e_asq_cmd_details *cmd_details) 2027 { 2028 struct i40e_aq_desc desc; 2029 struct i40e_aqc_an_advt_reg *resp = 2030 (struct i40e_aqc_an_advt_reg *)&desc.params.raw; 2031 enum i40e_status_code status; 2032 2033 i40e_fill_default_direct_cmd_desc(&desc, 2034 i40e_aqc_opc_get_partner_advt); 2035 2036 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 2037 2038 if (status != I40E_SUCCESS) 2039 goto aq_get_partner_advt_exit; 2040 2041 *advt_reg = (u64)(LE16_TO_CPU(resp->local_an_reg1)) << 32; 2042 *advt_reg |= LE32_TO_CPU(resp->local_an_reg0); 2043 2044 aq_get_partner_advt_exit: 2045 return status; 2046 } 2047 2048 /** 2049 * i40e_aq_set_lb_modes 2050 * @hw: pointer to the hw struct 2051 * @lb_modes: loopback mode to be set 2052 * @cmd_details: pointer to command details structure or NULL 2053 * 2054 * Sets loopback modes. 2055 **/ 2056 enum i40e_status_code i40e_aq_set_lb_modes(struct i40e_hw *hw, 2057 u16 lb_modes, 2058 struct i40e_asq_cmd_details *cmd_details) 2059 { 2060 struct i40e_aq_desc desc; 2061 struct i40e_aqc_set_lb_mode *cmd = 2062 (struct i40e_aqc_set_lb_mode *)&desc.params.raw; 2063 enum i40e_status_code status; 2064 2065 i40e_fill_default_direct_cmd_desc(&desc, 2066 i40e_aqc_opc_set_lb_modes); 2067 2068 cmd->lb_mode = CPU_TO_LE16(lb_modes); 2069 2070 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 2071 2072 return status; 2073 } 2074 2075 /** 2076 * i40e_aq_set_phy_debug 2077 * @hw: pointer to the hw struct 2078 * @cmd_flags: debug command flags 2079 * @cmd_details: pointer to command details structure or NULL 2080 * 2081 * Reset the external PHY. 2082 **/ 2083 enum i40e_status_code i40e_aq_set_phy_debug(struct i40e_hw *hw, u8 cmd_flags, 2084 struct i40e_asq_cmd_details *cmd_details) 2085 { 2086 struct i40e_aq_desc desc; 2087 struct i40e_aqc_set_phy_debug *cmd = 2088 (struct i40e_aqc_set_phy_debug *)&desc.params.raw; 2089 enum i40e_status_code status; 2090 2091 i40e_fill_default_direct_cmd_desc(&desc, 2092 i40e_aqc_opc_set_phy_debug); 2093 2094 cmd->command_flags = cmd_flags; 2095 2096 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 2097 2098 return status; 2099 } 2100 2101 /** 2102 * i40e_aq_add_vsi 2103 * @hw: pointer to the hw struct 2104 * @vsi_ctx: pointer to a vsi context struct 2105 * @cmd_details: pointer to command details structure or NULL 2106 * 2107 * Add a VSI context to the hardware. 2108 **/ 2109 enum i40e_status_code i40e_aq_add_vsi(struct i40e_hw *hw, 2110 struct i40e_vsi_context *vsi_ctx, 2111 struct i40e_asq_cmd_details *cmd_details) 2112 { 2113 struct i40e_aq_desc desc; 2114 struct i40e_aqc_add_get_update_vsi *cmd = 2115 (struct i40e_aqc_add_get_update_vsi *)&desc.params.raw; 2116 struct i40e_aqc_add_get_update_vsi_completion *resp = 2117 (struct i40e_aqc_add_get_update_vsi_completion *) 2118 &desc.params.raw; 2119 enum i40e_status_code status; 2120 2121 i40e_fill_default_direct_cmd_desc(&desc, 2122 i40e_aqc_opc_add_vsi); 2123 2124 cmd->uplink_seid = CPU_TO_LE16(vsi_ctx->uplink_seid); 2125 cmd->connection_type = vsi_ctx->connection_type; 2126 cmd->vf_id = vsi_ctx->vf_num; 2127 cmd->vsi_flags = CPU_TO_LE16(vsi_ctx->flags); 2128 2129 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD)); 2130 2131 status = i40e_asq_send_command(hw, &desc, &vsi_ctx->info, 2132 sizeof(vsi_ctx->info), cmd_details); 2133 2134 if (status != I40E_SUCCESS) 2135 goto aq_add_vsi_exit; 2136 2137 vsi_ctx->seid = LE16_TO_CPU(resp->seid); 2138 vsi_ctx->vsi_number = LE16_TO_CPU(resp->vsi_number); 2139 vsi_ctx->vsis_allocated = LE16_TO_CPU(resp->vsi_used); 2140 vsi_ctx->vsis_unallocated = LE16_TO_CPU(resp->vsi_free); 2141 2142 aq_add_vsi_exit: 2143 return status; 2144 } 2145 2146 /** 2147 * i40e_aq_set_default_vsi 2148 * @hw: pointer to the hw struct 2149 * @seid: vsi number 2150 * @cmd_details: pointer to command details structure or NULL 2151 **/ 2152 enum i40e_status_code i40e_aq_set_default_vsi(struct i40e_hw *hw, 2153 u16 seid, 2154 struct i40e_asq_cmd_details *cmd_details) 2155 { 2156 struct i40e_aq_desc desc; 2157 struct i40e_aqc_set_vsi_promiscuous_modes *cmd = 2158 (struct i40e_aqc_set_vsi_promiscuous_modes *) 2159 &desc.params.raw; 2160 enum i40e_status_code status; 2161 2162 i40e_fill_default_direct_cmd_desc(&desc, 2163 i40e_aqc_opc_set_vsi_promiscuous_modes); 2164 2165 cmd->promiscuous_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_DEFAULT); 2166 cmd->valid_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_DEFAULT); 2167 cmd->seid = CPU_TO_LE16(seid); 2168 2169 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 2170 2171 return status; 2172 } 2173 2174 /** 2175 * i40e_aq_clear_default_vsi 2176 * @hw: pointer to the hw struct 2177 * @seid: vsi number 2178 * @cmd_details: pointer to command details structure or NULL 2179 **/ 2180 enum i40e_status_code i40e_aq_clear_default_vsi(struct i40e_hw *hw, 2181 u16 seid, 2182 struct i40e_asq_cmd_details *cmd_details) 2183 { 2184 struct i40e_aq_desc desc; 2185 struct i40e_aqc_set_vsi_promiscuous_modes *cmd = 2186 (struct i40e_aqc_set_vsi_promiscuous_modes *) 2187 &desc.params.raw; 2188 enum i40e_status_code status; 2189 2190 i40e_fill_default_direct_cmd_desc(&desc, 2191 i40e_aqc_opc_set_vsi_promiscuous_modes); 2192 2193 cmd->promiscuous_flags = CPU_TO_LE16(0); 2194 cmd->valid_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_DEFAULT); 2195 cmd->seid = CPU_TO_LE16(seid); 2196 2197 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 2198 2199 return status; 2200 } 2201 2202 /** 2203 * i40e_aq_set_vsi_unicast_promiscuous 2204 * @hw: pointer to the hw struct 2205 * @seid: vsi number 2206 * @set: set unicast promiscuous enable/disable 2207 * @cmd_details: pointer to command details structure or NULL 2208 * @rx_only_promisc: flag to decide if egress traffic gets mirrored in promisc 2209 **/ 2210 enum i40e_status_code i40e_aq_set_vsi_unicast_promiscuous(struct i40e_hw *hw, 2211 u16 seid, bool set, 2212 struct i40e_asq_cmd_details *cmd_details, 2213 bool rx_only_promisc) 2214 { 2215 struct i40e_aq_desc desc; 2216 struct i40e_aqc_set_vsi_promiscuous_modes *cmd = 2217 (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw; 2218 enum i40e_status_code status; 2219 u16 flags = 0; 2220 2221 i40e_fill_default_direct_cmd_desc(&desc, 2222 i40e_aqc_opc_set_vsi_promiscuous_modes); 2223 2224 if (set) { 2225 flags |= I40E_AQC_SET_VSI_PROMISC_UNICAST; 2226 if (rx_only_promisc && 2227 (((hw->aq.api_maj_ver == 1) && (hw->aq.api_min_ver >= 5)) || 2228 (hw->aq.api_maj_ver > 1))) 2229 flags |= I40E_AQC_SET_VSI_PROMISC_TX; 2230 } 2231 2232 cmd->promiscuous_flags = CPU_TO_LE16(flags); 2233 2234 cmd->valid_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_PROMISC_UNICAST); 2235 if (((hw->aq.api_maj_ver >= 1) && (hw->aq.api_min_ver >= 5)) || 2236 (hw->aq.api_maj_ver > 1)) 2237 cmd->valid_flags |= CPU_TO_LE16(I40E_AQC_SET_VSI_PROMISC_TX); 2238 2239 cmd->seid = CPU_TO_LE16(seid); 2240 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 2241 2242 return status; 2243 } 2244 2245 /** 2246 * i40e_aq_set_vsi_multicast_promiscuous 2247 * @hw: pointer to the hw struct 2248 * @seid: vsi number 2249 * @set: set multicast promiscuous enable/disable 2250 * @cmd_details: pointer to command details structure or NULL 2251 **/ 2252 enum i40e_status_code i40e_aq_set_vsi_multicast_promiscuous(struct i40e_hw *hw, 2253 u16 seid, bool set, struct i40e_asq_cmd_details *cmd_details) 2254 { 2255 struct i40e_aq_desc desc; 2256 struct i40e_aqc_set_vsi_promiscuous_modes *cmd = 2257 (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw; 2258 enum i40e_status_code status; 2259 u16 flags = 0; 2260 2261 i40e_fill_default_direct_cmd_desc(&desc, 2262 i40e_aqc_opc_set_vsi_promiscuous_modes); 2263 2264 if (set) 2265 flags |= I40E_AQC_SET_VSI_PROMISC_MULTICAST; 2266 2267 cmd->promiscuous_flags = CPU_TO_LE16(flags); 2268 2269 cmd->valid_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_PROMISC_MULTICAST); 2270 2271 cmd->seid = CPU_TO_LE16(seid); 2272 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 2273 2274 return status; 2275 } 2276 2277 /** 2278 * i40e_aq_set_vsi_mc_promisc_on_vlan 2279 * @hw: pointer to the hw struct 2280 * @seid: vsi number 2281 * @enable: set MAC L2 layer unicast promiscuous enable/disable for a given VLAN 2282 * @vid: The VLAN tag filter - capture any multicast packet with this VLAN tag 2283 * @cmd_details: pointer to command details structure or NULL 2284 **/ 2285 enum i40e_status_code i40e_aq_set_vsi_mc_promisc_on_vlan(struct i40e_hw *hw, 2286 u16 seid, bool enable, u16 vid, 2287 struct i40e_asq_cmd_details *cmd_details) 2288 { 2289 struct i40e_aq_desc desc; 2290 struct i40e_aqc_set_vsi_promiscuous_modes *cmd = 2291 (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw; 2292 enum i40e_status_code status; 2293 u16 flags = 0; 2294 2295 i40e_fill_default_direct_cmd_desc(&desc, 2296 i40e_aqc_opc_set_vsi_promiscuous_modes); 2297 2298 if (enable) 2299 flags |= I40E_AQC_SET_VSI_PROMISC_MULTICAST; 2300 2301 cmd->promiscuous_flags = CPU_TO_LE16(flags); 2302 cmd->valid_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_PROMISC_MULTICAST); 2303 cmd->seid = CPU_TO_LE16(seid); 2304 cmd->vlan_tag = CPU_TO_LE16(vid | I40E_AQC_SET_VSI_VLAN_VALID); 2305 2306 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 2307 2308 return status; 2309 } 2310 2311 /** 2312 * i40e_aq_set_vsi_uc_promisc_on_vlan 2313 * @hw: pointer to the hw struct 2314 * @seid: vsi number 2315 * @enable: set MAC L2 layer unicast promiscuous enable/disable for a given VLAN 2316 * @vid: The VLAN tag filter - capture any unicast packet with this VLAN tag 2317 * @cmd_details: pointer to command details structure or NULL 2318 **/ 2319 enum i40e_status_code i40e_aq_set_vsi_uc_promisc_on_vlan(struct i40e_hw *hw, 2320 u16 seid, bool enable, u16 vid, 2321 struct i40e_asq_cmd_details *cmd_details) 2322 { 2323 struct i40e_aq_desc desc; 2324 struct i40e_aqc_set_vsi_promiscuous_modes *cmd = 2325 (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw; 2326 enum i40e_status_code status; 2327 u16 flags = 0; 2328 2329 i40e_fill_default_direct_cmd_desc(&desc, 2330 i40e_aqc_opc_set_vsi_promiscuous_modes); 2331 2332 if (enable) 2333 flags |= I40E_AQC_SET_VSI_PROMISC_UNICAST; 2334 2335 cmd->promiscuous_flags = CPU_TO_LE16(flags); 2336 cmd->valid_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_PROMISC_UNICAST); 2337 cmd->seid = CPU_TO_LE16(seid); 2338 cmd->vlan_tag = CPU_TO_LE16(vid | I40E_AQC_SET_VSI_VLAN_VALID); 2339 2340 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 2341 2342 return status; 2343 } 2344 2345 /** 2346 * i40e_aq_set_vsi_bc_promisc_on_vlan 2347 * @hw: pointer to the hw struct 2348 * @seid: vsi number 2349 * @enable: set broadcast promiscuous enable/disable for a given VLAN 2350 * @vid: The VLAN tag filter - capture any broadcast packet with this VLAN tag 2351 * @cmd_details: pointer to command details structure or NULL 2352 **/ 2353 enum i40e_status_code i40e_aq_set_vsi_bc_promisc_on_vlan(struct i40e_hw *hw, 2354 u16 seid, bool enable, u16 vid, 2355 struct i40e_asq_cmd_details *cmd_details) 2356 { 2357 struct i40e_aq_desc desc; 2358 struct i40e_aqc_set_vsi_promiscuous_modes *cmd = 2359 (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw; 2360 enum i40e_status_code status; 2361 u16 flags = 0; 2362 2363 i40e_fill_default_direct_cmd_desc(&desc, 2364 i40e_aqc_opc_set_vsi_promiscuous_modes); 2365 2366 if (enable) 2367 flags |= I40E_AQC_SET_VSI_PROMISC_BROADCAST; 2368 2369 cmd->promiscuous_flags = CPU_TO_LE16(flags); 2370 cmd->valid_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_PROMISC_BROADCAST); 2371 cmd->seid = CPU_TO_LE16(seid); 2372 cmd->vlan_tag = CPU_TO_LE16(vid | I40E_AQC_SET_VSI_VLAN_VALID); 2373 2374 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 2375 2376 return status; 2377 } 2378 2379 /** 2380 * i40e_aq_set_vsi_broadcast 2381 * @hw: pointer to the hw struct 2382 * @seid: vsi number 2383 * @set_filter: TRUE to set filter, FALSE to clear filter 2384 * @cmd_details: pointer to command details structure or NULL 2385 * 2386 * Set or clear the broadcast promiscuous flag (filter) for a given VSI. 2387 **/ 2388 enum i40e_status_code i40e_aq_set_vsi_broadcast(struct i40e_hw *hw, 2389 u16 seid, bool set_filter, 2390 struct i40e_asq_cmd_details *cmd_details) 2391 { 2392 struct i40e_aq_desc desc; 2393 struct i40e_aqc_set_vsi_promiscuous_modes *cmd = 2394 (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw; 2395 enum i40e_status_code status; 2396 2397 i40e_fill_default_direct_cmd_desc(&desc, 2398 i40e_aqc_opc_set_vsi_promiscuous_modes); 2399 2400 if (set_filter) 2401 cmd->promiscuous_flags 2402 |= CPU_TO_LE16(I40E_AQC_SET_VSI_PROMISC_BROADCAST); 2403 else 2404 cmd->promiscuous_flags 2405 &= CPU_TO_LE16(~I40E_AQC_SET_VSI_PROMISC_BROADCAST); 2406 2407 cmd->valid_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_PROMISC_BROADCAST); 2408 cmd->seid = CPU_TO_LE16(seid); 2409 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 2410 2411 return status; 2412 } 2413 2414 /** 2415 * i40e_aq_set_vsi_vlan_promisc - control the VLAN promiscuous setting 2416 * @hw: pointer to the hw struct 2417 * @seid: vsi number 2418 * @enable: set MAC L2 layer unicast promiscuous enable/disable for a given VLAN 2419 * @cmd_details: pointer to command details structure or NULL 2420 **/ 2421 enum i40e_status_code i40e_aq_set_vsi_vlan_promisc(struct i40e_hw *hw, 2422 u16 seid, bool enable, 2423 struct i40e_asq_cmd_details *cmd_details) 2424 { 2425 struct i40e_aq_desc desc; 2426 struct i40e_aqc_set_vsi_promiscuous_modes *cmd = 2427 (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw; 2428 enum i40e_status_code status; 2429 u16 flags = 0; 2430 2431 i40e_fill_default_direct_cmd_desc(&desc, 2432 i40e_aqc_opc_set_vsi_promiscuous_modes); 2433 if (enable) 2434 flags |= I40E_AQC_SET_VSI_PROMISC_VLAN; 2435 2436 cmd->promiscuous_flags = CPU_TO_LE16(flags); 2437 cmd->valid_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_PROMISC_VLAN); 2438 cmd->seid = CPU_TO_LE16(seid); 2439 2440 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 2441 2442 return status; 2443 } 2444 2445 /** 2446 * i40e_get_vsi_params - get VSI configuration info 2447 * @hw: pointer to the hw struct 2448 * @vsi_ctx: pointer to a vsi context struct 2449 * @cmd_details: pointer to command details structure or NULL 2450 **/ 2451 enum i40e_status_code i40e_aq_get_vsi_params(struct i40e_hw *hw, 2452 struct i40e_vsi_context *vsi_ctx, 2453 struct i40e_asq_cmd_details *cmd_details) 2454 { 2455 struct i40e_aq_desc desc; 2456 struct i40e_aqc_add_get_update_vsi *cmd = 2457 (struct i40e_aqc_add_get_update_vsi *)&desc.params.raw; 2458 struct i40e_aqc_add_get_update_vsi_completion *resp = 2459 (struct i40e_aqc_add_get_update_vsi_completion *) 2460 &desc.params.raw; 2461 enum i40e_status_code status; 2462 2463 i40e_fill_default_direct_cmd_desc(&desc, 2464 i40e_aqc_opc_get_vsi_parameters); 2465 2466 cmd->uplink_seid = CPU_TO_LE16(vsi_ctx->seid); 2467 2468 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF); 2469 2470 status = i40e_asq_send_command(hw, &desc, &vsi_ctx->info, 2471 sizeof(vsi_ctx->info), NULL); 2472 2473 if (status != I40E_SUCCESS) 2474 goto aq_get_vsi_params_exit; 2475 2476 vsi_ctx->seid = LE16_TO_CPU(resp->seid); 2477 vsi_ctx->vsi_number = LE16_TO_CPU(resp->vsi_number); 2478 vsi_ctx->vsis_allocated = LE16_TO_CPU(resp->vsi_used); 2479 vsi_ctx->vsis_unallocated = LE16_TO_CPU(resp->vsi_free); 2480 2481 aq_get_vsi_params_exit: 2482 return status; 2483 } 2484 2485 /** 2486 * i40e_aq_update_vsi_params 2487 * @hw: pointer to the hw struct 2488 * @vsi_ctx: pointer to a vsi context struct 2489 * @cmd_details: pointer to command details structure or NULL 2490 * 2491 * Update a VSI context. 2492 **/ 2493 enum i40e_status_code i40e_aq_update_vsi_params(struct i40e_hw *hw, 2494 struct i40e_vsi_context *vsi_ctx, 2495 struct i40e_asq_cmd_details *cmd_details) 2496 { 2497 struct i40e_aq_desc desc; 2498 struct i40e_aqc_add_get_update_vsi *cmd = 2499 (struct i40e_aqc_add_get_update_vsi *)&desc.params.raw; 2500 struct i40e_aqc_add_get_update_vsi_completion *resp = 2501 (struct i40e_aqc_add_get_update_vsi_completion *) 2502 &desc.params.raw; 2503 enum i40e_status_code status; 2504 2505 i40e_fill_default_direct_cmd_desc(&desc, 2506 i40e_aqc_opc_update_vsi_parameters); 2507 cmd->uplink_seid = CPU_TO_LE16(vsi_ctx->seid); 2508 2509 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD)); 2510 2511 status = i40e_asq_send_command(hw, &desc, &vsi_ctx->info, 2512 sizeof(vsi_ctx->info), cmd_details); 2513 2514 vsi_ctx->vsis_allocated = LE16_TO_CPU(resp->vsi_used); 2515 vsi_ctx->vsis_unallocated = LE16_TO_CPU(resp->vsi_free); 2516 2517 return status; 2518 } 2519 2520 /** 2521 * i40e_aq_get_switch_config 2522 * @hw: pointer to the hardware structure 2523 * @buf: pointer to the result buffer 2524 * @buf_size: length of input buffer 2525 * @start_seid: seid to start for the report, 0 == beginning 2526 * @cmd_details: pointer to command details structure or NULL 2527 * 2528 * Fill the buf with switch configuration returned from AdminQ command 2529 **/ 2530 enum i40e_status_code i40e_aq_get_switch_config(struct i40e_hw *hw, 2531 struct i40e_aqc_get_switch_config_resp *buf, 2532 u16 buf_size, u16 *start_seid, 2533 struct i40e_asq_cmd_details *cmd_details) 2534 { 2535 struct i40e_aq_desc desc; 2536 struct i40e_aqc_switch_seid *scfg = 2537 (struct i40e_aqc_switch_seid *)&desc.params.raw; 2538 enum i40e_status_code status; 2539 2540 i40e_fill_default_direct_cmd_desc(&desc, 2541 i40e_aqc_opc_get_switch_config); 2542 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF); 2543 if (buf_size > I40E_AQ_LARGE_BUF) 2544 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB); 2545 scfg->seid = CPU_TO_LE16(*start_seid); 2546 2547 status = i40e_asq_send_command(hw, &desc, buf, buf_size, cmd_details); 2548 *start_seid = LE16_TO_CPU(scfg->seid); 2549 2550 return status; 2551 } 2552 2553 /** 2554 * i40e_aq_set_switch_config 2555 * @hw: pointer to the hardware structure 2556 * @flags: bit flag values to set 2557 * @valid_flags: which bit flags to set 2558 * @cmd_details: pointer to command details structure or NULL 2559 * 2560 * Set switch configuration bits 2561 **/ 2562 enum i40e_status_code i40e_aq_set_switch_config(struct i40e_hw *hw, 2563 u16 flags, u16 valid_flags, 2564 struct i40e_asq_cmd_details *cmd_details) 2565 { 2566 struct i40e_aq_desc desc; 2567 struct i40e_aqc_set_switch_config *scfg = 2568 (struct i40e_aqc_set_switch_config *)&desc.params.raw; 2569 enum i40e_status_code status; 2570 2571 i40e_fill_default_direct_cmd_desc(&desc, 2572 i40e_aqc_opc_set_switch_config); 2573 scfg->flags = CPU_TO_LE16(flags); 2574 scfg->valid_flags = CPU_TO_LE16(valid_flags); 2575 2576 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 2577 2578 return status; 2579 } 2580 2581 /** 2582 * i40e_aq_get_firmware_version 2583 * @hw: pointer to the hw struct 2584 * @fw_major_version: firmware major version 2585 * @fw_minor_version: firmware minor version 2586 * @fw_build: firmware build number 2587 * @api_major_version: major queue version 2588 * @api_minor_version: minor queue version 2589 * @cmd_details: pointer to command details structure or NULL 2590 * 2591 * Get the firmware version from the admin queue commands 2592 **/ 2593 enum i40e_status_code i40e_aq_get_firmware_version(struct i40e_hw *hw, 2594 u16 *fw_major_version, u16 *fw_minor_version, 2595 u32 *fw_build, 2596 u16 *api_major_version, u16 *api_minor_version, 2597 struct i40e_asq_cmd_details *cmd_details) 2598 { 2599 struct i40e_aq_desc desc; 2600 struct i40e_aqc_get_version *resp = 2601 (struct i40e_aqc_get_version *)&desc.params.raw; 2602 enum i40e_status_code status; 2603 2604 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_get_version); 2605 2606 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 2607 2608 if (status == I40E_SUCCESS) { 2609 if (fw_major_version != NULL) 2610 *fw_major_version = LE16_TO_CPU(resp->fw_major); 2611 if (fw_minor_version != NULL) 2612 *fw_minor_version = LE16_TO_CPU(resp->fw_minor); 2613 if (fw_build != NULL) 2614 *fw_build = LE32_TO_CPU(resp->fw_build); 2615 if (api_major_version != NULL) 2616 *api_major_version = LE16_TO_CPU(resp->api_major); 2617 if (api_minor_version != NULL) 2618 *api_minor_version = LE16_TO_CPU(resp->api_minor); 2619 2620 /* A workaround to fix the API version in SW */ 2621 if (api_major_version && api_minor_version && 2622 fw_major_version && fw_minor_version && 2623 ((*api_major_version == 1) && (*api_minor_version == 1)) && 2624 (((*fw_major_version == 4) && (*fw_minor_version >= 2)) || 2625 (*fw_major_version > 4))) 2626 *api_minor_version = 2; 2627 } 2628 2629 return status; 2630 } 2631 2632 /** 2633 * i40e_aq_send_driver_version 2634 * @hw: pointer to the hw struct 2635 * @dv: driver's major, minor version 2636 * @cmd_details: pointer to command details structure or NULL 2637 * 2638 * Send the driver version to the firmware 2639 **/ 2640 enum i40e_status_code i40e_aq_send_driver_version(struct i40e_hw *hw, 2641 struct i40e_driver_version *dv, 2642 struct i40e_asq_cmd_details *cmd_details) 2643 { 2644 struct i40e_aq_desc desc; 2645 struct i40e_aqc_driver_version *cmd = 2646 (struct i40e_aqc_driver_version *)&desc.params.raw; 2647 enum i40e_status_code status; 2648 u16 len; 2649 2650 if (dv == NULL) 2651 return I40E_ERR_PARAM; 2652 2653 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_driver_version); 2654 2655 desc.flags |= CPU_TO_LE16(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD); 2656 cmd->driver_major_ver = dv->major_version; 2657 cmd->driver_minor_ver = dv->minor_version; 2658 cmd->driver_build_ver = dv->build_version; 2659 cmd->driver_subbuild_ver = dv->subbuild_version; 2660 2661 len = 0; 2662 while (len < sizeof(dv->driver_string) && 2663 (dv->driver_string[len] < 0x80) && 2664 dv->driver_string[len]) 2665 len++; 2666 status = i40e_asq_send_command(hw, &desc, dv->driver_string, 2667 len, cmd_details); 2668 2669 return status; 2670 } 2671 2672 /** 2673 * i40e_get_link_status - get status of the HW network link 2674 * @hw: pointer to the hw struct 2675 * @link_up: pointer to bool (TRUE/FALSE = linkup/linkdown) 2676 * 2677 * Variable link_up TRUE if link is up, FALSE if link is down. 2678 * The variable link_up is invalid if returned value of status != I40E_SUCCESS 2679 * 2680 * Side effect: LinkStatusEvent reporting becomes enabled 2681 **/ 2682 enum i40e_status_code i40e_get_link_status(struct i40e_hw *hw, bool *link_up) 2683 { 2684 enum i40e_status_code status = I40E_SUCCESS; 2685 2686 if (hw->phy.get_link_info) { 2687 status = i40e_update_link_info(hw); 2688 2689 if (status != I40E_SUCCESS) 2690 i40e_debug(hw, I40E_DEBUG_LINK, "get link failed: status %d\n", 2691 status); 2692 } 2693 2694 *link_up = hw->phy.link_info.link_info & I40E_AQ_LINK_UP; 2695 2696 return status; 2697 } 2698 2699 /** 2700 * i40e_updatelink_status - update status of the HW network link 2701 * @hw: pointer to the hw struct 2702 **/ 2703 enum i40e_status_code i40e_update_link_info(struct i40e_hw *hw) 2704 { 2705 struct i40e_aq_get_phy_abilities_resp abilities; 2706 enum i40e_status_code status = I40E_SUCCESS; 2707 2708 status = i40e_aq_get_link_info(hw, TRUE, NULL, NULL); 2709 if (status) 2710 return status; 2711 2712 /* extra checking needed to ensure link info to user is timely */ 2713 if ((hw->phy.link_info.link_info & I40E_AQ_MEDIA_AVAILABLE) && 2714 ((hw->phy.link_info.link_info & I40E_AQ_LINK_UP) || 2715 !(hw->phy.link_info_old.link_info & I40E_AQ_LINK_UP))) { 2716 status = i40e_aq_get_phy_capabilities(hw, FALSE, false, 2717 &abilities, NULL); 2718 if (status) 2719 return status; 2720 2721 i40e_memcpy(hw->phy.link_info.module_type, &abilities.module_type, 2722 sizeof(hw->phy.link_info.module_type), I40E_NONDMA_TO_NONDMA); 2723 } 2724 return status; 2725 } 2726 2727 2728 /** 2729 * i40e_get_link_speed 2730 * @hw: pointer to the hw struct 2731 * 2732 * Returns the link speed of the adapter. 2733 **/ 2734 enum i40e_aq_link_speed i40e_get_link_speed(struct i40e_hw *hw) 2735 { 2736 enum i40e_aq_link_speed speed = I40E_LINK_SPEED_UNKNOWN; 2737 enum i40e_status_code status = I40E_SUCCESS; 2738 2739 if (hw->phy.get_link_info) { 2740 status = i40e_aq_get_link_info(hw, TRUE, NULL, NULL); 2741 2742 if (status != I40E_SUCCESS) 2743 goto i40e_link_speed_exit; 2744 } 2745 2746 speed = hw->phy.link_info.link_speed; 2747 2748 i40e_link_speed_exit: 2749 return speed; 2750 } 2751 2752 /** 2753 * i40e_aq_add_veb - Insert a VEB between the VSI and the MAC 2754 * @hw: pointer to the hw struct 2755 * @uplink_seid: the MAC or other gizmo SEID 2756 * @downlink_seid: the VSI SEID 2757 * @enabled_tc: bitmap of TCs to be enabled 2758 * @default_port: TRUE for default port VSI, FALSE for control port 2759 * @veb_seid: pointer to where to put the resulting VEB SEID 2760 * @enable_stats: TRUE to turn on VEB stats 2761 * @cmd_details: pointer to command details structure or NULL 2762 * 2763 * This asks the FW to add a VEB between the uplink and downlink 2764 * elements. If the uplink SEID is 0, this will be a floating VEB. 2765 **/ 2766 enum i40e_status_code i40e_aq_add_veb(struct i40e_hw *hw, u16 uplink_seid, 2767 u16 downlink_seid, u8 enabled_tc, 2768 bool default_port, u16 *veb_seid, 2769 bool enable_stats, 2770 struct i40e_asq_cmd_details *cmd_details) 2771 { 2772 struct i40e_aq_desc desc; 2773 struct i40e_aqc_add_veb *cmd = 2774 (struct i40e_aqc_add_veb *)&desc.params.raw; 2775 struct i40e_aqc_add_veb_completion *resp = 2776 (struct i40e_aqc_add_veb_completion *)&desc.params.raw; 2777 enum i40e_status_code status; 2778 u16 veb_flags = 0; 2779 2780 /* SEIDs need to either both be set or both be 0 for floating VEB */ 2781 if (!!uplink_seid != !!downlink_seid) 2782 return I40E_ERR_PARAM; 2783 2784 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_add_veb); 2785 2786 cmd->uplink_seid = CPU_TO_LE16(uplink_seid); 2787 cmd->downlink_seid = CPU_TO_LE16(downlink_seid); 2788 cmd->enable_tcs = enabled_tc; 2789 if (!uplink_seid) 2790 veb_flags |= I40E_AQC_ADD_VEB_FLOATING; 2791 if (default_port) 2792 veb_flags |= I40E_AQC_ADD_VEB_PORT_TYPE_DEFAULT; 2793 else 2794 veb_flags |= I40E_AQC_ADD_VEB_PORT_TYPE_DATA; 2795 2796 /* reverse logic here: set the bitflag to disable the stats */ 2797 if (!enable_stats) 2798 veb_flags |= I40E_AQC_ADD_VEB_ENABLE_DISABLE_STATS; 2799 2800 cmd->veb_flags = CPU_TO_LE16(veb_flags); 2801 2802 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 2803 2804 if (!status && veb_seid) 2805 *veb_seid = LE16_TO_CPU(resp->veb_seid); 2806 2807 return status; 2808 } 2809 2810 /** 2811 * i40e_aq_get_veb_parameters - Retrieve VEB parameters 2812 * @hw: pointer to the hw struct 2813 * @veb_seid: the SEID of the VEB to query 2814 * @switch_id: the uplink switch id 2815 * @floating: set to TRUE if the VEB is floating 2816 * @statistic_index: index of the stats counter block for this VEB 2817 * @vebs_used: number of VEB's used by function 2818 * @vebs_free: total VEB's not reserved by any function 2819 * @cmd_details: pointer to command details structure or NULL 2820 * 2821 * This retrieves the parameters for a particular VEB, specified by 2822 * uplink_seid, and returns them to the caller. 2823 **/ 2824 enum i40e_status_code i40e_aq_get_veb_parameters(struct i40e_hw *hw, 2825 u16 veb_seid, u16 *switch_id, 2826 bool *floating, u16 *statistic_index, 2827 u16 *vebs_used, u16 *vebs_free, 2828 struct i40e_asq_cmd_details *cmd_details) 2829 { 2830 struct i40e_aq_desc desc; 2831 struct i40e_aqc_get_veb_parameters_completion *cmd_resp = 2832 (struct i40e_aqc_get_veb_parameters_completion *) 2833 &desc.params.raw; 2834 enum i40e_status_code status; 2835 2836 if (veb_seid == 0) 2837 return I40E_ERR_PARAM; 2838 2839 i40e_fill_default_direct_cmd_desc(&desc, 2840 i40e_aqc_opc_get_veb_parameters); 2841 cmd_resp->seid = CPU_TO_LE16(veb_seid); 2842 2843 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 2844 if (status) 2845 goto get_veb_exit; 2846 2847 if (switch_id) 2848 *switch_id = LE16_TO_CPU(cmd_resp->switch_id); 2849 if (statistic_index) 2850 *statistic_index = LE16_TO_CPU(cmd_resp->statistic_index); 2851 if (vebs_used) 2852 *vebs_used = LE16_TO_CPU(cmd_resp->vebs_used); 2853 if (vebs_free) 2854 *vebs_free = LE16_TO_CPU(cmd_resp->vebs_free); 2855 if (floating) { 2856 u16 flags = LE16_TO_CPU(cmd_resp->veb_flags); 2857 2858 if (flags & I40E_AQC_ADD_VEB_FLOATING) 2859 *floating = TRUE; 2860 else 2861 *floating = FALSE; 2862 } 2863 2864 get_veb_exit: 2865 return status; 2866 } 2867 2868 /** 2869 * i40e_aq_add_macvlan 2870 * @hw: pointer to the hw struct 2871 * @seid: VSI for the mac address 2872 * @mv_list: list of macvlans to be added 2873 * @count: length of the list 2874 * @cmd_details: pointer to command details structure or NULL 2875 * 2876 * Add MAC/VLAN addresses to the HW filtering 2877 **/ 2878 enum i40e_status_code i40e_aq_add_macvlan(struct i40e_hw *hw, u16 seid, 2879 struct i40e_aqc_add_macvlan_element_data *mv_list, 2880 u16 count, struct i40e_asq_cmd_details *cmd_details) 2881 { 2882 struct i40e_aq_desc desc; 2883 struct i40e_aqc_macvlan *cmd = 2884 (struct i40e_aqc_macvlan *)&desc.params.raw; 2885 enum i40e_status_code status; 2886 u16 buf_size; 2887 int i; 2888 2889 if (count == 0 || !mv_list || !hw) 2890 return I40E_ERR_PARAM; 2891 2892 buf_size = count * sizeof(*mv_list); 2893 2894 /* prep the rest of the request */ 2895 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_add_macvlan); 2896 cmd->num_addresses = CPU_TO_LE16(count); 2897 cmd->seid[0] = CPU_TO_LE16(I40E_AQC_MACVLAN_CMD_SEID_VALID | seid); 2898 cmd->seid[1] = 0; 2899 cmd->seid[2] = 0; 2900 2901 for (i = 0; i < count; i++) 2902 if (I40E_IS_MULTICAST(mv_list[i].mac_addr)) 2903 mv_list[i].flags |= 2904 CPU_TO_LE16(I40E_AQC_MACVLAN_ADD_USE_SHARED_MAC); 2905 2906 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD)); 2907 if (buf_size > I40E_AQ_LARGE_BUF) 2908 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB); 2909 2910 status = i40e_asq_send_command(hw, &desc, mv_list, buf_size, 2911 cmd_details); 2912 2913 return status; 2914 } 2915 2916 /** 2917 * i40e_aq_remove_macvlan 2918 * @hw: pointer to the hw struct 2919 * @seid: VSI for the mac address 2920 * @mv_list: list of macvlans to be removed 2921 * @count: length of the list 2922 * @cmd_details: pointer to command details structure or NULL 2923 * 2924 * Remove MAC/VLAN addresses from the HW filtering 2925 **/ 2926 enum i40e_status_code i40e_aq_remove_macvlan(struct i40e_hw *hw, u16 seid, 2927 struct i40e_aqc_remove_macvlan_element_data *mv_list, 2928 u16 count, struct i40e_asq_cmd_details *cmd_details) 2929 { 2930 struct i40e_aq_desc desc; 2931 struct i40e_aqc_macvlan *cmd = 2932 (struct i40e_aqc_macvlan *)&desc.params.raw; 2933 enum i40e_status_code status; 2934 u16 buf_size; 2935 2936 if (count == 0 || !mv_list || !hw) 2937 return I40E_ERR_PARAM; 2938 2939 buf_size = count * sizeof(*mv_list); 2940 2941 /* prep the rest of the request */ 2942 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_remove_macvlan); 2943 cmd->num_addresses = CPU_TO_LE16(count); 2944 cmd->seid[0] = CPU_TO_LE16(I40E_AQC_MACVLAN_CMD_SEID_VALID | seid); 2945 cmd->seid[1] = 0; 2946 cmd->seid[2] = 0; 2947 2948 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD)); 2949 if (buf_size > I40E_AQ_LARGE_BUF) 2950 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB); 2951 2952 status = i40e_asq_send_command(hw, &desc, mv_list, buf_size, 2953 cmd_details); 2954 2955 return status; 2956 } 2957 2958 /** 2959 * i40e_mirrorrule_op - Internal helper function to add/delete mirror rule 2960 * @hw: pointer to the hw struct 2961 * @opcode: AQ opcode for add or delete mirror rule 2962 * @sw_seid: Switch SEID (to which rule refers) 2963 * @rule_type: Rule Type (ingress/egress/VLAN) 2964 * @id: Destination VSI SEID or Rule ID 2965 * @count: length of the list 2966 * @mr_list: list of mirrored VSI SEIDs or VLAN IDs 2967 * @cmd_details: pointer to command details structure or NULL 2968 * @rule_id: Rule ID returned from FW 2969 * @rule_used: Number of rules used in internal switch 2970 * @rule_free: Number of rules free in internal switch 2971 * 2972 * Add/Delete a mirror rule to a specific switch. Mirror rules are supported for 2973 * VEBs/VEPA elements only 2974 **/ 2975 static enum i40e_status_code i40e_mirrorrule_op(struct i40e_hw *hw, 2976 u16 opcode, u16 sw_seid, u16 rule_type, u16 id, 2977 u16 count, __le16 *mr_list, 2978 struct i40e_asq_cmd_details *cmd_details, 2979 u16 *rule_id, u16 *rules_used, u16 *rules_free) 2980 { 2981 struct i40e_aq_desc desc; 2982 struct i40e_aqc_add_delete_mirror_rule *cmd = 2983 (struct i40e_aqc_add_delete_mirror_rule *)&desc.params.raw; 2984 struct i40e_aqc_add_delete_mirror_rule_completion *resp = 2985 (struct i40e_aqc_add_delete_mirror_rule_completion *)&desc.params.raw; 2986 enum i40e_status_code status; 2987 u16 buf_size; 2988 2989 buf_size = count * sizeof(*mr_list); 2990 2991 /* prep the rest of the request */ 2992 i40e_fill_default_direct_cmd_desc(&desc, opcode); 2993 cmd->seid = CPU_TO_LE16(sw_seid); 2994 cmd->rule_type = CPU_TO_LE16(rule_type & 2995 I40E_AQC_MIRROR_RULE_TYPE_MASK); 2996 cmd->num_entries = CPU_TO_LE16(count); 2997 /* Dest VSI for add, rule_id for delete */ 2998 cmd->destination = CPU_TO_LE16(id); 2999 if (mr_list) { 3000 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | 3001 I40E_AQ_FLAG_RD)); 3002 if (buf_size > I40E_AQ_LARGE_BUF) 3003 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB); 3004 } 3005 3006 status = i40e_asq_send_command(hw, &desc, mr_list, buf_size, 3007 cmd_details); 3008 if (status == I40E_SUCCESS || 3009 hw->aq.asq_last_status == I40E_AQ_RC_ENOSPC) { 3010 if (rule_id) 3011 *rule_id = LE16_TO_CPU(resp->rule_id); 3012 if (rules_used) 3013 *rules_used = LE16_TO_CPU(resp->mirror_rules_used); 3014 if (rules_free) 3015 *rules_free = LE16_TO_CPU(resp->mirror_rules_free); 3016 } 3017 return status; 3018 } 3019 3020 /** 3021 * i40e_aq_add_mirrorrule - add a mirror rule 3022 * @hw: pointer to the hw struct 3023 * @sw_seid: Switch SEID (to which rule refers) 3024 * @rule_type: Rule Type (ingress/egress/VLAN) 3025 * @dest_vsi: SEID of VSI to which packets will be mirrored 3026 * @count: length of the list 3027 * @mr_list: list of mirrored VSI SEIDs or VLAN IDs 3028 * @cmd_details: pointer to command details structure or NULL 3029 * @rule_id: Rule ID returned from FW 3030 * @rule_used: Number of rules used in internal switch 3031 * @rule_free: Number of rules free in internal switch 3032 * 3033 * Add mirror rule. Mirror rules are supported for VEBs or VEPA elements only 3034 **/ 3035 enum i40e_status_code i40e_aq_add_mirrorrule(struct i40e_hw *hw, u16 sw_seid, 3036 u16 rule_type, u16 dest_vsi, u16 count, __le16 *mr_list, 3037 struct i40e_asq_cmd_details *cmd_details, 3038 u16 *rule_id, u16 *rules_used, u16 *rules_free) 3039 { 3040 if (!(rule_type == I40E_AQC_MIRROR_RULE_TYPE_ALL_INGRESS || 3041 rule_type == I40E_AQC_MIRROR_RULE_TYPE_ALL_EGRESS)) { 3042 if (count == 0 || !mr_list) 3043 return I40E_ERR_PARAM; 3044 } 3045 3046 return i40e_mirrorrule_op(hw, i40e_aqc_opc_add_mirror_rule, sw_seid, 3047 rule_type, dest_vsi, count, mr_list, 3048 cmd_details, rule_id, rules_used, rules_free); 3049 } 3050 3051 /** 3052 * i40e_aq_delete_mirrorrule - delete a mirror rule 3053 * @hw: pointer to the hw struct 3054 * @sw_seid: Switch SEID (to which rule refers) 3055 * @rule_type: Rule Type (ingress/egress/VLAN) 3056 * @count: length of the list 3057 * @rule_id: Rule ID that is returned in the receive desc as part of 3058 * add_mirrorrule. 3059 * @mr_list: list of mirrored VLAN IDs to be removed 3060 * @cmd_details: pointer to command details structure or NULL 3061 * @rule_used: Number of rules used in internal switch 3062 * @rule_free: Number of rules free in internal switch 3063 * 3064 * Delete a mirror rule. Mirror rules are supported for VEBs/VEPA elements only 3065 **/ 3066 enum i40e_status_code i40e_aq_delete_mirrorrule(struct i40e_hw *hw, u16 sw_seid, 3067 u16 rule_type, u16 rule_id, u16 count, __le16 *mr_list, 3068 struct i40e_asq_cmd_details *cmd_details, 3069 u16 *rules_used, u16 *rules_free) 3070 { 3071 /* Rule ID has to be valid except rule_type: INGRESS VLAN mirroring */ 3072 if (rule_type == I40E_AQC_MIRROR_RULE_TYPE_VLAN) { 3073 /* count and mr_list shall be valid for rule_type INGRESS VLAN 3074 * mirroring. For other rule_type, count and rule_type should 3075 * not matter. 3076 */ 3077 if (count == 0 || !mr_list) 3078 return I40E_ERR_PARAM; 3079 } 3080 3081 return i40e_mirrorrule_op(hw, i40e_aqc_opc_delete_mirror_rule, sw_seid, 3082 rule_type, rule_id, count, mr_list, 3083 cmd_details, NULL, rules_used, rules_free); 3084 } 3085 3086 /** 3087 * i40e_aq_add_vlan - Add VLAN ids to the HW filtering 3088 * @hw: pointer to the hw struct 3089 * @seid: VSI for the vlan filters 3090 * @v_list: list of vlan filters to be added 3091 * @count: length of the list 3092 * @cmd_details: pointer to command details structure or NULL 3093 **/ 3094 enum i40e_status_code i40e_aq_add_vlan(struct i40e_hw *hw, u16 seid, 3095 struct i40e_aqc_add_remove_vlan_element_data *v_list, 3096 u8 count, struct i40e_asq_cmd_details *cmd_details) 3097 { 3098 struct i40e_aq_desc desc; 3099 struct i40e_aqc_macvlan *cmd = 3100 (struct i40e_aqc_macvlan *)&desc.params.raw; 3101 enum i40e_status_code status; 3102 u16 buf_size; 3103 3104 if (count == 0 || !v_list || !hw) 3105 return I40E_ERR_PARAM; 3106 3107 buf_size = count * sizeof(*v_list); 3108 3109 /* prep the rest of the request */ 3110 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_add_vlan); 3111 cmd->num_addresses = CPU_TO_LE16(count); 3112 cmd->seid[0] = CPU_TO_LE16(seid | I40E_AQC_MACVLAN_CMD_SEID_VALID); 3113 cmd->seid[1] = 0; 3114 cmd->seid[2] = 0; 3115 3116 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD)); 3117 if (buf_size > I40E_AQ_LARGE_BUF) 3118 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB); 3119 3120 status = i40e_asq_send_command(hw, &desc, v_list, buf_size, 3121 cmd_details); 3122 3123 return status; 3124 } 3125 3126 /** 3127 * i40e_aq_remove_vlan - Remove VLANs from the HW filtering 3128 * @hw: pointer to the hw struct 3129 * @seid: VSI for the vlan filters 3130 * @v_list: list of macvlans to be removed 3131 * @count: length of the list 3132 * @cmd_details: pointer to command details structure or NULL 3133 **/ 3134 enum i40e_status_code i40e_aq_remove_vlan(struct i40e_hw *hw, u16 seid, 3135 struct i40e_aqc_add_remove_vlan_element_data *v_list, 3136 u8 count, struct i40e_asq_cmd_details *cmd_details) 3137 { 3138 struct i40e_aq_desc desc; 3139 struct i40e_aqc_macvlan *cmd = 3140 (struct i40e_aqc_macvlan *)&desc.params.raw; 3141 enum i40e_status_code status; 3142 u16 buf_size; 3143 3144 if (count == 0 || !v_list || !hw) 3145 return I40E_ERR_PARAM; 3146 3147 buf_size = count * sizeof(*v_list); 3148 3149 /* prep the rest of the request */ 3150 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_remove_vlan); 3151 cmd->num_addresses = CPU_TO_LE16(count); 3152 cmd->seid[0] = CPU_TO_LE16(seid | I40E_AQC_MACVLAN_CMD_SEID_VALID); 3153 cmd->seid[1] = 0; 3154 cmd->seid[2] = 0; 3155 3156 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD)); 3157 if (buf_size > I40E_AQ_LARGE_BUF) 3158 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB); 3159 3160 status = i40e_asq_send_command(hw, &desc, v_list, buf_size, 3161 cmd_details); 3162 3163 return status; 3164 } 3165 3166 /** 3167 * i40e_aq_send_msg_to_vf 3168 * @hw: pointer to the hardware structure 3169 * @vfid: vf id to send msg 3170 * @v_opcode: opcodes for VF-PF communication 3171 * @v_retval: return error code 3172 * @msg: pointer to the msg buffer 3173 * @msglen: msg length 3174 * @cmd_details: pointer to command details 3175 * 3176 * send msg to vf 3177 **/ 3178 enum i40e_status_code i40e_aq_send_msg_to_vf(struct i40e_hw *hw, u16 vfid, 3179 u32 v_opcode, u32 v_retval, u8 *msg, u16 msglen, 3180 struct i40e_asq_cmd_details *cmd_details) 3181 { 3182 struct i40e_aq_desc desc; 3183 struct i40e_aqc_pf_vf_message *cmd = 3184 (struct i40e_aqc_pf_vf_message *)&desc.params.raw; 3185 enum i40e_status_code status; 3186 3187 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_send_msg_to_vf); 3188 cmd->id = CPU_TO_LE32(vfid); 3189 desc.cookie_high = CPU_TO_LE32(v_opcode); 3190 desc.cookie_low = CPU_TO_LE32(v_retval); 3191 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_SI); 3192 if (msglen) { 3193 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | 3194 I40E_AQ_FLAG_RD)); 3195 if (msglen > I40E_AQ_LARGE_BUF) 3196 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB); 3197 desc.datalen = CPU_TO_LE16(msglen); 3198 } 3199 status = i40e_asq_send_command(hw, &desc, msg, msglen, cmd_details); 3200 3201 return status; 3202 } 3203 3204 /** 3205 * i40e_aq_debug_read_register 3206 * @hw: pointer to the hw struct 3207 * @reg_addr: register address 3208 * @reg_val: register value 3209 * @cmd_details: pointer to command details structure or NULL 3210 * 3211 * Read the register using the admin queue commands 3212 **/ 3213 enum i40e_status_code i40e_aq_debug_read_register(struct i40e_hw *hw, 3214 u32 reg_addr, u64 *reg_val, 3215 struct i40e_asq_cmd_details *cmd_details) 3216 { 3217 struct i40e_aq_desc desc; 3218 struct i40e_aqc_debug_reg_read_write *cmd_resp = 3219 (struct i40e_aqc_debug_reg_read_write *)&desc.params.raw; 3220 enum i40e_status_code status; 3221 3222 if (reg_val == NULL) 3223 return I40E_ERR_PARAM; 3224 3225 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_debug_read_reg); 3226 3227 cmd_resp->address = CPU_TO_LE32(reg_addr); 3228 3229 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 3230 3231 if (status == I40E_SUCCESS) { 3232 *reg_val = ((u64)LE32_TO_CPU(cmd_resp->value_high) << 32) | 3233 (u64)LE32_TO_CPU(cmd_resp->value_low); 3234 } 3235 3236 return status; 3237 } 3238 3239 /** 3240 * i40e_aq_debug_write_register 3241 * @hw: pointer to the hw struct 3242 * @reg_addr: register address 3243 * @reg_val: register value 3244 * @cmd_details: pointer to command details structure or NULL 3245 * 3246 * Write to a register using the admin queue commands 3247 **/ 3248 enum i40e_status_code i40e_aq_debug_write_register(struct i40e_hw *hw, 3249 u32 reg_addr, u64 reg_val, 3250 struct i40e_asq_cmd_details *cmd_details) 3251 { 3252 struct i40e_aq_desc desc; 3253 struct i40e_aqc_debug_reg_read_write *cmd = 3254 (struct i40e_aqc_debug_reg_read_write *)&desc.params.raw; 3255 enum i40e_status_code status; 3256 3257 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_debug_write_reg); 3258 3259 cmd->address = CPU_TO_LE32(reg_addr); 3260 cmd->value_high = CPU_TO_LE32((u32)(reg_val >> 32)); 3261 cmd->value_low = CPU_TO_LE32((u32)(reg_val & 0xFFFFFFFF)); 3262 3263 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 3264 3265 return status; 3266 } 3267 3268 /** 3269 * i40e_aq_request_resource 3270 * @hw: pointer to the hw struct 3271 * @resource: resource id 3272 * @access: access type 3273 * @sdp_number: resource number 3274 * @timeout: the maximum time in ms that the driver may hold the resource 3275 * @cmd_details: pointer to command details structure or NULL 3276 * 3277 * requests common resource using the admin queue commands 3278 **/ 3279 enum i40e_status_code i40e_aq_request_resource(struct i40e_hw *hw, 3280 enum i40e_aq_resources_ids resource, 3281 enum i40e_aq_resource_access_type access, 3282 u8 sdp_number, u64 *timeout, 3283 struct i40e_asq_cmd_details *cmd_details) 3284 { 3285 struct i40e_aq_desc desc; 3286 struct i40e_aqc_request_resource *cmd_resp = 3287 (struct i40e_aqc_request_resource *)&desc.params.raw; 3288 enum i40e_status_code status; 3289 3290 DEBUGFUNC("i40e_aq_request_resource"); 3291 3292 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_request_resource); 3293 3294 cmd_resp->resource_id = CPU_TO_LE16(resource); 3295 cmd_resp->access_type = CPU_TO_LE16(access); 3296 cmd_resp->resource_number = CPU_TO_LE32(sdp_number); 3297 3298 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 3299 /* The completion specifies the maximum time in ms that the driver 3300 * may hold the resource in the Timeout field. 3301 * If the resource is held by someone else, the command completes with 3302 * busy return value and the timeout field indicates the maximum time 3303 * the current owner of the resource has to free it. 3304 */ 3305 if (status == I40E_SUCCESS || hw->aq.asq_last_status == I40E_AQ_RC_EBUSY) 3306 *timeout = LE32_TO_CPU(cmd_resp->timeout); 3307 3308 return status; 3309 } 3310 3311 /** 3312 * i40e_aq_release_resource 3313 * @hw: pointer to the hw struct 3314 * @resource: resource id 3315 * @sdp_number: resource number 3316 * @cmd_details: pointer to command details structure or NULL 3317 * 3318 * release common resource using the admin queue commands 3319 **/ 3320 enum i40e_status_code i40e_aq_release_resource(struct i40e_hw *hw, 3321 enum i40e_aq_resources_ids resource, 3322 u8 sdp_number, 3323 struct i40e_asq_cmd_details *cmd_details) 3324 { 3325 struct i40e_aq_desc desc; 3326 struct i40e_aqc_request_resource *cmd = 3327 (struct i40e_aqc_request_resource *)&desc.params.raw; 3328 enum i40e_status_code status; 3329 3330 DEBUGFUNC("i40e_aq_release_resource"); 3331 3332 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_release_resource); 3333 3334 cmd->resource_id = CPU_TO_LE16(resource); 3335 cmd->resource_number = CPU_TO_LE32(sdp_number); 3336 3337 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 3338 3339 return status; 3340 } 3341 3342 /** 3343 * i40e_aq_read_nvm 3344 * @hw: pointer to the hw struct 3345 * @module_pointer: module pointer location in words from the NVM beginning 3346 * @offset: byte offset from the module beginning 3347 * @length: length of the section to be read (in bytes from the offset) 3348 * @data: command buffer (size [bytes] = length) 3349 * @last_command: tells if this is the last command in a series 3350 * @cmd_details: pointer to command details structure or NULL 3351 * 3352 * Read the NVM using the admin queue commands 3353 **/ 3354 enum i40e_status_code i40e_aq_read_nvm(struct i40e_hw *hw, u8 module_pointer, 3355 u32 offset, u16 length, void *data, 3356 bool last_command, 3357 struct i40e_asq_cmd_details *cmd_details) 3358 { 3359 struct i40e_aq_desc desc; 3360 struct i40e_aqc_nvm_update *cmd = 3361 (struct i40e_aqc_nvm_update *)&desc.params.raw; 3362 enum i40e_status_code status; 3363 3364 DEBUGFUNC("i40e_aq_read_nvm"); 3365 3366 /* In offset the highest byte must be zeroed. */ 3367 if (offset & 0xFF000000) { 3368 status = I40E_ERR_PARAM; 3369 goto i40e_aq_read_nvm_exit; 3370 } 3371 3372 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_nvm_read); 3373 3374 /* If this is the last command in a series, set the proper flag. */ 3375 if (last_command) 3376 cmd->command_flags |= I40E_AQ_NVM_LAST_CMD; 3377 cmd->module_pointer = module_pointer; 3378 cmd->offset = CPU_TO_LE32(offset); 3379 cmd->length = CPU_TO_LE16(length); 3380 3381 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF); 3382 if (length > I40E_AQ_LARGE_BUF) 3383 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB); 3384 3385 status = i40e_asq_send_command(hw, &desc, data, length, cmd_details); 3386 3387 i40e_aq_read_nvm_exit: 3388 return status; 3389 } 3390 3391 /** 3392 * i40e_aq_read_nvm_config - read an nvm config block 3393 * @hw: pointer to the hw struct 3394 * @cmd_flags: NVM access admin command bits 3395 * @field_id: field or feature id 3396 * @data: buffer for result 3397 * @buf_size: buffer size 3398 * @element_count: pointer to count of elements read by FW 3399 * @cmd_details: pointer to command details structure or NULL 3400 **/ 3401 enum i40e_status_code i40e_aq_read_nvm_config(struct i40e_hw *hw, 3402 u8 cmd_flags, u32 field_id, void *data, 3403 u16 buf_size, u16 *element_count, 3404 struct i40e_asq_cmd_details *cmd_details) 3405 { 3406 struct i40e_aq_desc desc; 3407 struct i40e_aqc_nvm_config_read *cmd = 3408 (struct i40e_aqc_nvm_config_read *)&desc.params.raw; 3409 enum i40e_status_code status; 3410 3411 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_nvm_config_read); 3412 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF)); 3413 if (buf_size > I40E_AQ_LARGE_BUF) 3414 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB); 3415 3416 cmd->cmd_flags = CPU_TO_LE16(cmd_flags); 3417 cmd->element_id = CPU_TO_LE16((u16)(0xffff & field_id)); 3418 if (cmd_flags & I40E_AQ_ANVM_FEATURE_OR_IMMEDIATE_MASK) 3419 cmd->element_id_msw = CPU_TO_LE16((u16)(field_id >> 16)); 3420 else 3421 cmd->element_id_msw = 0; 3422 3423 status = i40e_asq_send_command(hw, &desc, data, buf_size, cmd_details); 3424 3425 if (!status && element_count) 3426 *element_count = LE16_TO_CPU(cmd->element_count); 3427 3428 return status; 3429 } 3430 3431 /** 3432 * i40e_aq_write_nvm_config - write an nvm config block 3433 * @hw: pointer to the hw struct 3434 * @cmd_flags: NVM access admin command bits 3435 * @data: buffer for result 3436 * @buf_size: buffer size 3437 * @element_count: count of elements to be written 3438 * @cmd_details: pointer to command details structure or NULL 3439 **/ 3440 enum i40e_status_code i40e_aq_write_nvm_config(struct i40e_hw *hw, 3441 u8 cmd_flags, void *data, u16 buf_size, 3442 u16 element_count, 3443 struct i40e_asq_cmd_details *cmd_details) 3444 { 3445 struct i40e_aq_desc desc; 3446 struct i40e_aqc_nvm_config_write *cmd = 3447 (struct i40e_aqc_nvm_config_write *)&desc.params.raw; 3448 enum i40e_status_code status; 3449 3450 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_nvm_config_write); 3451 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD)); 3452 if (buf_size > I40E_AQ_LARGE_BUF) 3453 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB); 3454 3455 cmd->element_count = CPU_TO_LE16(element_count); 3456 cmd->cmd_flags = CPU_TO_LE16(cmd_flags); 3457 status = i40e_asq_send_command(hw, &desc, data, buf_size, cmd_details); 3458 3459 return status; 3460 } 3461 3462 /** 3463 * i40e_aq_oem_post_update - triggers an OEM specific flow after update 3464 * @hw: pointer to the hw struct 3465 * @cmd_details: pointer to command details structure or NULL 3466 **/ 3467 enum i40e_status_code i40e_aq_oem_post_update(struct i40e_hw *hw, 3468 void *buff, u16 buff_size, 3469 struct i40e_asq_cmd_details *cmd_details) 3470 { 3471 struct i40e_aq_desc desc; 3472 enum i40e_status_code status; 3473 3474 3475 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_oem_post_update); 3476 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 3477 if (status && LE16_TO_CPU(desc.retval) == I40E_AQ_RC_ESRCH) 3478 status = I40E_ERR_NOT_IMPLEMENTED; 3479 3480 return status; 3481 } 3482 3483 /** 3484 * i40e_aq_erase_nvm 3485 * @hw: pointer to the hw struct 3486 * @module_pointer: module pointer location in words from the NVM beginning 3487 * @offset: offset in the module (expressed in 4 KB from module's beginning) 3488 * @length: length of the section to be erased (expressed in 4 KB) 3489 * @last_command: tells if this is the last command in a series 3490 * @cmd_details: pointer to command details structure or NULL 3491 * 3492 * Erase the NVM sector using the admin queue commands 3493 **/ 3494 enum i40e_status_code i40e_aq_erase_nvm(struct i40e_hw *hw, u8 module_pointer, 3495 u32 offset, u16 length, bool last_command, 3496 struct i40e_asq_cmd_details *cmd_details) 3497 { 3498 struct i40e_aq_desc desc; 3499 struct i40e_aqc_nvm_update *cmd = 3500 (struct i40e_aqc_nvm_update *)&desc.params.raw; 3501 enum i40e_status_code status; 3502 3503 DEBUGFUNC("i40e_aq_erase_nvm"); 3504 3505 /* In offset the highest byte must be zeroed. */ 3506 if (offset & 0xFF000000) { 3507 status = I40E_ERR_PARAM; 3508 goto i40e_aq_erase_nvm_exit; 3509 } 3510 3511 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_nvm_erase); 3512 3513 /* If this is the last command in a series, set the proper flag. */ 3514 if (last_command) 3515 cmd->command_flags |= I40E_AQ_NVM_LAST_CMD; 3516 cmd->module_pointer = module_pointer; 3517 cmd->offset = CPU_TO_LE32(offset); 3518 cmd->length = CPU_TO_LE16(length); 3519 3520 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 3521 3522 i40e_aq_erase_nvm_exit: 3523 return status; 3524 } 3525 3526 /** 3527 * i40e_parse_discover_capabilities 3528 * @hw: pointer to the hw struct 3529 * @buff: pointer to a buffer containing device/function capability records 3530 * @cap_count: number of capability records in the list 3531 * @list_type_opc: type of capabilities list to parse 3532 * 3533 * Parse the device/function capabilities list. 3534 **/ 3535 static void i40e_parse_discover_capabilities(struct i40e_hw *hw, void *buff, 3536 u32 cap_count, 3537 enum i40e_admin_queue_opc list_type_opc) 3538 { 3539 struct i40e_aqc_list_capabilities_element_resp *cap; 3540 u32 valid_functions, num_functions; 3541 u32 number, logical_id, phys_id; 3542 struct i40e_hw_capabilities *p; 3543 u8 major_rev; 3544 u32 i = 0; 3545 u16 id; 3546 3547 cap = (struct i40e_aqc_list_capabilities_element_resp *) buff; 3548 3549 if (list_type_opc == i40e_aqc_opc_list_dev_capabilities) 3550 p = (struct i40e_hw_capabilities *)&hw->dev_caps; 3551 else if (list_type_opc == i40e_aqc_opc_list_func_capabilities) 3552 p = (struct i40e_hw_capabilities *)&hw->func_caps; 3553 else 3554 return; 3555 3556 for (i = 0; i < cap_count; i++, cap++) { 3557 id = LE16_TO_CPU(cap->id); 3558 number = LE32_TO_CPU(cap->number); 3559 logical_id = LE32_TO_CPU(cap->logical_id); 3560 phys_id = LE32_TO_CPU(cap->phys_id); 3561 major_rev = cap->major_rev; 3562 3563 switch (id) { 3564 case I40E_AQ_CAP_ID_SWITCH_MODE: 3565 p->switch_mode = number; 3566 i40e_debug(hw, I40E_DEBUG_INIT, 3567 "HW Capability: Switch mode = %d\n", 3568 p->switch_mode); 3569 break; 3570 case I40E_AQ_CAP_ID_MNG_MODE: 3571 p->management_mode = number; 3572 if (major_rev > 1) { 3573 p->mng_protocols_over_mctp = logical_id; 3574 i40e_debug(hw, I40E_DEBUG_INIT, 3575 "HW Capability: Protocols over MCTP = %d\n", 3576 p->mng_protocols_over_mctp); 3577 } else { 3578 p->mng_protocols_over_mctp = 0; 3579 } 3580 i40e_debug(hw, I40E_DEBUG_INIT, 3581 "HW Capability: Management Mode = %d\n", 3582 p->management_mode); 3583 break; 3584 case I40E_AQ_CAP_ID_NPAR_ACTIVE: 3585 p->npar_enable = number; 3586 i40e_debug(hw, I40E_DEBUG_INIT, 3587 "HW Capability: NPAR enable = %d\n", 3588 p->npar_enable); 3589 break; 3590 case I40E_AQ_CAP_ID_OS2BMC_CAP: 3591 p->os2bmc = number; 3592 i40e_debug(hw, I40E_DEBUG_INIT, 3593 "HW Capability: OS2BMC = %d\n", p->os2bmc); 3594 break; 3595 case I40E_AQ_CAP_ID_FUNCTIONS_VALID: 3596 p->valid_functions = number; 3597 i40e_debug(hw, I40E_DEBUG_INIT, 3598 "HW Capability: Valid Functions = %d\n", 3599 p->valid_functions); 3600 break; 3601 case I40E_AQ_CAP_ID_SRIOV: 3602 if (number == 1) 3603 p->sr_iov_1_1 = TRUE; 3604 i40e_debug(hw, I40E_DEBUG_INIT, 3605 "HW Capability: SR-IOV = %d\n", 3606 p->sr_iov_1_1); 3607 break; 3608 case I40E_AQ_CAP_ID_VF: 3609 p->num_vfs = number; 3610 p->vf_base_id = logical_id; 3611 i40e_debug(hw, I40E_DEBUG_INIT, 3612 "HW Capability: VF count = %d\n", 3613 p->num_vfs); 3614 i40e_debug(hw, I40E_DEBUG_INIT, 3615 "HW Capability: VF base_id = %d\n", 3616 p->vf_base_id); 3617 break; 3618 case I40E_AQ_CAP_ID_VMDQ: 3619 if (number == 1) 3620 p->vmdq = TRUE; 3621 i40e_debug(hw, I40E_DEBUG_INIT, 3622 "HW Capability: VMDQ = %d\n", p->vmdq); 3623 break; 3624 case I40E_AQ_CAP_ID_8021QBG: 3625 if (number == 1) 3626 p->evb_802_1_qbg = TRUE; 3627 i40e_debug(hw, I40E_DEBUG_INIT, 3628 "HW Capability: 802.1Qbg = %d\n", number); 3629 break; 3630 case I40E_AQ_CAP_ID_8021QBR: 3631 if (number == 1) 3632 p->evb_802_1_qbh = TRUE; 3633 i40e_debug(hw, I40E_DEBUG_INIT, 3634 "HW Capability: 802.1Qbh = %d\n", number); 3635 break; 3636 case I40E_AQ_CAP_ID_VSI: 3637 p->num_vsis = number; 3638 i40e_debug(hw, I40E_DEBUG_INIT, 3639 "HW Capability: VSI count = %d\n", 3640 p->num_vsis); 3641 break; 3642 case I40E_AQ_CAP_ID_DCB: 3643 if (number == 1) { 3644 p->dcb = TRUE; 3645 p->enabled_tcmap = logical_id; 3646 p->maxtc = phys_id; 3647 } 3648 i40e_debug(hw, I40E_DEBUG_INIT, 3649 "HW Capability: DCB = %d\n", p->dcb); 3650 i40e_debug(hw, I40E_DEBUG_INIT, 3651 "HW Capability: TC Mapping = %d\n", 3652 logical_id); 3653 i40e_debug(hw, I40E_DEBUG_INIT, 3654 "HW Capability: TC Max = %d\n", p->maxtc); 3655 break; 3656 case I40E_AQ_CAP_ID_FCOE: 3657 if (number == 1) 3658 p->fcoe = TRUE; 3659 i40e_debug(hw, I40E_DEBUG_INIT, 3660 "HW Capability: FCOE = %d\n", p->fcoe); 3661 break; 3662 case I40E_AQ_CAP_ID_ISCSI: 3663 if (number == 1) 3664 p->iscsi = TRUE; 3665 i40e_debug(hw, I40E_DEBUG_INIT, 3666 "HW Capability: iSCSI = %d\n", p->iscsi); 3667 break; 3668 case I40E_AQ_CAP_ID_RSS: 3669 p->rss = TRUE; 3670 p->rss_table_size = number; 3671 p->rss_table_entry_width = logical_id; 3672 i40e_debug(hw, I40E_DEBUG_INIT, 3673 "HW Capability: RSS = %d\n", p->rss); 3674 i40e_debug(hw, I40E_DEBUG_INIT, 3675 "HW Capability: RSS table size = %d\n", 3676 p->rss_table_size); 3677 i40e_debug(hw, I40E_DEBUG_INIT, 3678 "HW Capability: RSS table width = %d\n", 3679 p->rss_table_entry_width); 3680 break; 3681 case I40E_AQ_CAP_ID_RXQ: 3682 p->num_rx_qp = number; 3683 p->base_queue = phys_id; 3684 i40e_debug(hw, I40E_DEBUG_INIT, 3685 "HW Capability: Rx QP = %d\n", number); 3686 i40e_debug(hw, I40E_DEBUG_INIT, 3687 "HW Capability: base_queue = %d\n", 3688 p->base_queue); 3689 break; 3690 case I40E_AQ_CAP_ID_TXQ: 3691 p->num_tx_qp = number; 3692 p->base_queue = phys_id; 3693 i40e_debug(hw, I40E_DEBUG_INIT, 3694 "HW Capability: Tx QP = %d\n", number); 3695 i40e_debug(hw, I40E_DEBUG_INIT, 3696 "HW Capability: base_queue = %d\n", 3697 p->base_queue); 3698 break; 3699 case I40E_AQ_CAP_ID_MSIX: 3700 p->num_msix_vectors = number; 3701 i40e_debug(hw, I40E_DEBUG_INIT, 3702 "HW Capability: MSIX vector count = %d\n", 3703 p->num_msix_vectors); 3704 break; 3705 case I40E_AQ_CAP_ID_VF_MSIX: 3706 p->num_msix_vectors_vf = number; 3707 i40e_debug(hw, I40E_DEBUG_INIT, 3708 "HW Capability: MSIX VF vector count = %d\n", 3709 p->num_msix_vectors_vf); 3710 break; 3711 case I40E_AQ_CAP_ID_FLEX10: 3712 if (major_rev == 1) { 3713 if (number == 1) { 3714 p->flex10_enable = TRUE; 3715 p->flex10_capable = TRUE; 3716 } 3717 } else { 3718 /* Capability revision >= 2 */ 3719 if (number & 1) 3720 p->flex10_enable = TRUE; 3721 if (number & 2) 3722 p->flex10_capable = TRUE; 3723 } 3724 p->flex10_mode = logical_id; 3725 p->flex10_status = phys_id; 3726 i40e_debug(hw, I40E_DEBUG_INIT, 3727 "HW Capability: Flex10 mode = %d\n", 3728 p->flex10_mode); 3729 i40e_debug(hw, I40E_DEBUG_INIT, 3730 "HW Capability: Flex10 status = %d\n", 3731 p->flex10_status); 3732 break; 3733 case I40E_AQ_CAP_ID_CEM: 3734 if (number == 1) 3735 p->mgmt_cem = TRUE; 3736 i40e_debug(hw, I40E_DEBUG_INIT, 3737 "HW Capability: CEM = %d\n", p->mgmt_cem); 3738 break; 3739 case I40E_AQ_CAP_ID_IWARP: 3740 if (number == 1) 3741 p->iwarp = TRUE; 3742 i40e_debug(hw, I40E_DEBUG_INIT, 3743 "HW Capability: iWARP = %d\n", p->iwarp); 3744 break; 3745 case I40E_AQ_CAP_ID_LED: 3746 if (phys_id < I40E_HW_CAP_MAX_GPIO) 3747 p->led[phys_id] = TRUE; 3748 i40e_debug(hw, I40E_DEBUG_INIT, 3749 "HW Capability: LED - PIN %d\n", phys_id); 3750 break; 3751 case I40E_AQ_CAP_ID_SDP: 3752 if (phys_id < I40E_HW_CAP_MAX_GPIO) 3753 p->sdp[phys_id] = TRUE; 3754 i40e_debug(hw, I40E_DEBUG_INIT, 3755 "HW Capability: SDP - PIN %d\n", phys_id); 3756 break; 3757 case I40E_AQ_CAP_ID_MDIO: 3758 if (number == 1) { 3759 p->mdio_port_num = phys_id; 3760 p->mdio_port_mode = logical_id; 3761 } 3762 i40e_debug(hw, I40E_DEBUG_INIT, 3763 "HW Capability: MDIO port number = %d\n", 3764 p->mdio_port_num); 3765 i40e_debug(hw, I40E_DEBUG_INIT, 3766 "HW Capability: MDIO port mode = %d\n", 3767 p->mdio_port_mode); 3768 break; 3769 case I40E_AQ_CAP_ID_1588: 3770 if (number == 1) 3771 p->ieee_1588 = TRUE; 3772 i40e_debug(hw, I40E_DEBUG_INIT, 3773 "HW Capability: IEEE 1588 = %d\n", 3774 p->ieee_1588); 3775 break; 3776 case I40E_AQ_CAP_ID_FLOW_DIRECTOR: 3777 p->fd = TRUE; 3778 p->fd_filters_guaranteed = number; 3779 p->fd_filters_best_effort = logical_id; 3780 i40e_debug(hw, I40E_DEBUG_INIT, 3781 "HW Capability: Flow Director = 1\n"); 3782 i40e_debug(hw, I40E_DEBUG_INIT, 3783 "HW Capability: Guaranteed FD filters = %d\n", 3784 p->fd_filters_guaranteed); 3785 break; 3786 case I40E_AQ_CAP_ID_WSR_PROT: 3787 p->wr_csr_prot = (u64)number; 3788 p->wr_csr_prot |= (u64)logical_id << 32; 3789 i40e_debug(hw, I40E_DEBUG_INIT, 3790 "HW Capability: wr_csr_prot = 0x%llX\n\n", 3791 (p->wr_csr_prot & 0xffff)); 3792 break; 3793 case I40E_AQ_CAP_ID_NVM_MGMT: 3794 if (number & I40E_NVM_MGMT_SEC_REV_DISABLED) 3795 p->sec_rev_disabled = TRUE; 3796 if (number & I40E_NVM_MGMT_UPDATE_DISABLED) 3797 p->update_disabled = TRUE; 3798 break; 3799 case I40E_AQ_CAP_ID_WOL_AND_PROXY: 3800 hw->num_wol_proxy_filters = (u16)number; 3801 hw->wol_proxy_vsi_seid = (u16)logical_id; 3802 p->apm_wol_support = phys_id & I40E_WOL_SUPPORT_MASK; 3803 if (phys_id & I40E_ACPI_PROGRAMMING_METHOD_MASK) 3804 p->acpi_prog_method = I40E_ACPI_PROGRAMMING_METHOD_AQC_FPK; 3805 else 3806 p->acpi_prog_method = I40E_ACPI_PROGRAMMING_METHOD_HW_FVL; 3807 p->proxy_support = (phys_id & I40E_PROXY_SUPPORT_MASK) ? 1 : 0; 3808 i40e_debug(hw, I40E_DEBUG_INIT, 3809 "HW Capability: WOL proxy filters = %d\n", 3810 hw->num_wol_proxy_filters); 3811 break; 3812 default: 3813 break; 3814 } 3815 } 3816 3817 if (p->fcoe) 3818 i40e_debug(hw, I40E_DEBUG_ALL, "device is FCoE capable\n"); 3819 3820 /* Always disable FCoE if compiled without the I40E_FCOE_ENA flag */ 3821 p->fcoe = FALSE; 3822 3823 /* count the enabled ports (aka the "not disabled" ports) */ 3824 hw->num_ports = 0; 3825 for (i = 0; i < 4; i++) { 3826 u32 port_cfg_reg = I40E_PRTGEN_CNF + (4 * i); 3827 u64 port_cfg = 0; 3828 3829 /* use AQ read to get the physical register offset instead 3830 * of the port relative offset 3831 */ 3832 i40e_aq_debug_read_register(hw, port_cfg_reg, &port_cfg, NULL); 3833 if (!(port_cfg & I40E_PRTGEN_CNF_PORT_DIS_MASK)) 3834 hw->num_ports++; 3835 } 3836 3837 valid_functions = p->valid_functions; 3838 num_functions = 0; 3839 while (valid_functions) { 3840 if (valid_functions & 1) 3841 num_functions++; 3842 valid_functions >>= 1; 3843 } 3844 3845 /* partition id is 1-based, and functions are evenly spread 3846 * across the ports as partitions 3847 */ 3848 if (hw->num_ports != 0) { 3849 hw->partition_id = (hw->pf_id / hw->num_ports) + 1; 3850 hw->num_partitions = num_functions / hw->num_ports; 3851 } 3852 3853 /* additional HW specific goodies that might 3854 * someday be HW version specific 3855 */ 3856 p->rx_buf_chain_len = I40E_MAX_CHAINED_RX_BUFFERS; 3857 } 3858 3859 /** 3860 * i40e_aq_discover_capabilities 3861 * @hw: pointer to the hw struct 3862 * @buff: a virtual buffer to hold the capabilities 3863 * @buff_size: Size of the virtual buffer 3864 * @data_size: Size of the returned data, or buff size needed if AQ err==ENOMEM 3865 * @list_type_opc: capabilities type to discover - pass in the command opcode 3866 * @cmd_details: pointer to command details structure or NULL 3867 * 3868 * Get the device capabilities descriptions from the firmware 3869 **/ 3870 enum i40e_status_code i40e_aq_discover_capabilities(struct i40e_hw *hw, 3871 void *buff, u16 buff_size, u16 *data_size, 3872 enum i40e_admin_queue_opc list_type_opc, 3873 struct i40e_asq_cmd_details *cmd_details) 3874 { 3875 struct i40e_aqc_list_capabilites *cmd; 3876 struct i40e_aq_desc desc; 3877 enum i40e_status_code status = I40E_SUCCESS; 3878 3879 cmd = (struct i40e_aqc_list_capabilites *)&desc.params.raw; 3880 3881 if (list_type_opc != i40e_aqc_opc_list_func_capabilities && 3882 list_type_opc != i40e_aqc_opc_list_dev_capabilities) { 3883 status = I40E_ERR_PARAM; 3884 goto exit; 3885 } 3886 3887 i40e_fill_default_direct_cmd_desc(&desc, list_type_opc); 3888 3889 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF); 3890 if (buff_size > I40E_AQ_LARGE_BUF) 3891 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB); 3892 3893 status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details); 3894 *data_size = LE16_TO_CPU(desc.datalen); 3895 3896 if (status) 3897 goto exit; 3898 3899 i40e_parse_discover_capabilities(hw, buff, LE32_TO_CPU(cmd->count), 3900 list_type_opc); 3901 3902 exit: 3903 return status; 3904 } 3905 3906 /** 3907 * i40e_aq_update_nvm 3908 * @hw: pointer to the hw struct 3909 * @module_pointer: module pointer location in words from the NVM beginning 3910 * @offset: byte offset from the module beginning 3911 * @length: length of the section to be written (in bytes from the offset) 3912 * @data: command buffer (size [bytes] = length) 3913 * @last_command: tells if this is the last command in a series 3914 * @cmd_details: pointer to command details structure or NULL 3915 * 3916 * Update the NVM using the admin queue commands 3917 **/ 3918 enum i40e_status_code i40e_aq_update_nvm(struct i40e_hw *hw, u8 module_pointer, 3919 u32 offset, u16 length, void *data, 3920 bool last_command, 3921 struct i40e_asq_cmd_details *cmd_details) 3922 { 3923 struct i40e_aq_desc desc; 3924 struct i40e_aqc_nvm_update *cmd = 3925 (struct i40e_aqc_nvm_update *)&desc.params.raw; 3926 enum i40e_status_code status; 3927 3928 DEBUGFUNC("i40e_aq_update_nvm"); 3929 3930 /* In offset the highest byte must be zeroed. */ 3931 if (offset & 0xFF000000) { 3932 status = I40E_ERR_PARAM; 3933 goto i40e_aq_update_nvm_exit; 3934 } 3935 3936 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_nvm_update); 3937 3938 /* If this is the last command in a series, set the proper flag. */ 3939 if (last_command) 3940 cmd->command_flags |= I40E_AQ_NVM_LAST_CMD; 3941 cmd->module_pointer = module_pointer; 3942 cmd->offset = CPU_TO_LE32(offset); 3943 cmd->length = CPU_TO_LE16(length); 3944 3945 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD)); 3946 if (length > I40E_AQ_LARGE_BUF) 3947 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB); 3948 3949 status = i40e_asq_send_command(hw, &desc, data, length, cmd_details); 3950 3951 i40e_aq_update_nvm_exit: 3952 return status; 3953 } 3954 3955 /** 3956 * i40e_aq_get_lldp_mib 3957 * @hw: pointer to the hw struct 3958 * @bridge_type: type of bridge requested 3959 * @mib_type: Local, Remote or both Local and Remote MIBs 3960 * @buff: pointer to a user supplied buffer to store the MIB block 3961 * @buff_size: size of the buffer (in bytes) 3962 * @local_len : length of the returned Local LLDP MIB 3963 * @remote_len: length of the returned Remote LLDP MIB 3964 * @cmd_details: pointer to command details structure or NULL 3965 * 3966 * Requests the complete LLDP MIB (entire packet). 3967 **/ 3968 enum i40e_status_code i40e_aq_get_lldp_mib(struct i40e_hw *hw, u8 bridge_type, 3969 u8 mib_type, void *buff, u16 buff_size, 3970 u16 *local_len, u16 *remote_len, 3971 struct i40e_asq_cmd_details *cmd_details) 3972 { 3973 struct i40e_aq_desc desc; 3974 struct i40e_aqc_lldp_get_mib *cmd = 3975 (struct i40e_aqc_lldp_get_mib *)&desc.params.raw; 3976 struct i40e_aqc_lldp_get_mib *resp = 3977 (struct i40e_aqc_lldp_get_mib *)&desc.params.raw; 3978 enum i40e_status_code status; 3979 3980 if (buff_size == 0 || !buff) 3981 return I40E_ERR_PARAM; 3982 3983 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_get_mib); 3984 /* Indirect Command */ 3985 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF); 3986 3987 cmd->type = mib_type & I40E_AQ_LLDP_MIB_TYPE_MASK; 3988 cmd->type |= ((bridge_type << I40E_AQ_LLDP_BRIDGE_TYPE_SHIFT) & 3989 I40E_AQ_LLDP_BRIDGE_TYPE_MASK); 3990 3991 desc.datalen = CPU_TO_LE16(buff_size); 3992 3993 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF); 3994 if (buff_size > I40E_AQ_LARGE_BUF) 3995 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB); 3996 3997 status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details); 3998 if (!status) { 3999 if (local_len != NULL) 4000 *local_len = LE16_TO_CPU(resp->local_len); 4001 if (remote_len != NULL) 4002 *remote_len = LE16_TO_CPU(resp->remote_len); 4003 } 4004 4005 return status; 4006 } 4007 4008 /** 4009 * i40e_aq_set_lldp_mib - Set the LLDP MIB 4010 * @hw: pointer to the hw struct 4011 * @mib_type: Local, Remote or both Local and Remote MIBs 4012 * @buff: pointer to a user supplied buffer to store the MIB block 4013 * @buff_size: size of the buffer (in bytes) 4014 * @cmd_details: pointer to command details structure or NULL 4015 * 4016 * Set the LLDP MIB. 4017 **/ 4018 enum i40e_status_code i40e_aq_set_lldp_mib(struct i40e_hw *hw, 4019 u8 mib_type, void *buff, u16 buff_size, 4020 struct i40e_asq_cmd_details *cmd_details) 4021 { 4022 struct i40e_aq_desc desc; 4023 struct i40e_aqc_lldp_set_local_mib *cmd = 4024 (struct i40e_aqc_lldp_set_local_mib *)&desc.params.raw; 4025 enum i40e_status_code status; 4026 4027 if (buff_size == 0 || !buff) 4028 return I40E_ERR_PARAM; 4029 4030 i40e_fill_default_direct_cmd_desc(&desc, 4031 i40e_aqc_opc_lldp_set_local_mib); 4032 /* Indirect Command */ 4033 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD)); 4034 if (buff_size > I40E_AQ_LARGE_BUF) 4035 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB); 4036 desc.datalen = CPU_TO_LE16(buff_size); 4037 4038 cmd->type = mib_type; 4039 cmd->length = CPU_TO_LE16(buff_size); 4040 cmd->address_high = CPU_TO_LE32(I40E_HI_WORD((uintptr_t)buff)); 4041 cmd->address_low = CPU_TO_LE32(I40E_LO_DWORD((uintptr_t)buff)); 4042 4043 status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details); 4044 return status; 4045 } 4046 4047 /** 4048 * i40e_aq_cfg_lldp_mib_change_event 4049 * @hw: pointer to the hw struct 4050 * @enable_update: Enable or Disable event posting 4051 * @cmd_details: pointer to command details structure or NULL 4052 * 4053 * Enable or Disable posting of an event on ARQ when LLDP MIB 4054 * associated with the interface changes 4055 **/ 4056 enum i40e_status_code i40e_aq_cfg_lldp_mib_change_event(struct i40e_hw *hw, 4057 bool enable_update, 4058 struct i40e_asq_cmd_details *cmd_details) 4059 { 4060 struct i40e_aq_desc desc; 4061 struct i40e_aqc_lldp_update_mib *cmd = 4062 (struct i40e_aqc_lldp_update_mib *)&desc.params.raw; 4063 enum i40e_status_code status; 4064 4065 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_update_mib); 4066 4067 if (!enable_update) 4068 cmd->command |= I40E_AQ_LLDP_MIB_UPDATE_DISABLE; 4069 4070 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 4071 4072 return status; 4073 } 4074 4075 /** 4076 * i40e_aq_add_lldp_tlv 4077 * @hw: pointer to the hw struct 4078 * @bridge_type: type of bridge 4079 * @buff: buffer with TLV to add 4080 * @buff_size: length of the buffer 4081 * @tlv_len: length of the TLV to be added 4082 * @mib_len: length of the LLDP MIB returned in response 4083 * @cmd_details: pointer to command details structure or NULL 4084 * 4085 * Add the specified TLV to LLDP Local MIB for the given bridge type, 4086 * it is responsibility of the caller to make sure that the TLV is not 4087 * already present in the LLDPDU. 4088 * In return firmware will write the complete LLDP MIB with the newly 4089 * added TLV in the response buffer. 4090 **/ 4091 enum i40e_status_code i40e_aq_add_lldp_tlv(struct i40e_hw *hw, u8 bridge_type, 4092 void *buff, u16 buff_size, u16 tlv_len, 4093 u16 *mib_len, 4094 struct i40e_asq_cmd_details *cmd_details) 4095 { 4096 struct i40e_aq_desc desc; 4097 struct i40e_aqc_lldp_add_tlv *cmd = 4098 (struct i40e_aqc_lldp_add_tlv *)&desc.params.raw; 4099 enum i40e_status_code status; 4100 4101 if (buff_size == 0 || !buff || tlv_len == 0) 4102 return I40E_ERR_PARAM; 4103 4104 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_add_tlv); 4105 4106 /* Indirect Command */ 4107 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD)); 4108 if (buff_size > I40E_AQ_LARGE_BUF) 4109 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB); 4110 desc.datalen = CPU_TO_LE16(buff_size); 4111 4112 cmd->type = ((bridge_type << I40E_AQ_LLDP_BRIDGE_TYPE_SHIFT) & 4113 I40E_AQ_LLDP_BRIDGE_TYPE_MASK); 4114 cmd->len = CPU_TO_LE16(tlv_len); 4115 4116 status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details); 4117 if (!status) { 4118 if (mib_len != NULL) 4119 *mib_len = LE16_TO_CPU(desc.datalen); 4120 } 4121 4122 return status; 4123 } 4124 4125 /** 4126 * i40e_aq_update_lldp_tlv 4127 * @hw: pointer to the hw struct 4128 * @bridge_type: type of bridge 4129 * @buff: buffer with TLV to update 4130 * @buff_size: size of the buffer holding original and updated TLVs 4131 * @old_len: Length of the Original TLV 4132 * @new_len: Length of the Updated TLV 4133 * @offset: offset of the updated TLV in the buff 4134 * @mib_len: length of the returned LLDP MIB 4135 * @cmd_details: pointer to command details structure or NULL 4136 * 4137 * Update the specified TLV to the LLDP Local MIB for the given bridge type. 4138 * Firmware will place the complete LLDP MIB in response buffer with the 4139 * updated TLV. 4140 **/ 4141 enum i40e_status_code i40e_aq_update_lldp_tlv(struct i40e_hw *hw, 4142 u8 bridge_type, void *buff, u16 buff_size, 4143 u16 old_len, u16 new_len, u16 offset, 4144 u16 *mib_len, 4145 struct i40e_asq_cmd_details *cmd_details) 4146 { 4147 struct i40e_aq_desc desc; 4148 struct i40e_aqc_lldp_update_tlv *cmd = 4149 (struct i40e_aqc_lldp_update_tlv *)&desc.params.raw; 4150 enum i40e_status_code status; 4151 4152 if (buff_size == 0 || !buff || offset == 0 || 4153 old_len == 0 || new_len == 0) 4154 return I40E_ERR_PARAM; 4155 4156 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_update_tlv); 4157 4158 /* Indirect Command */ 4159 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD)); 4160 if (buff_size > I40E_AQ_LARGE_BUF) 4161 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB); 4162 desc.datalen = CPU_TO_LE16(buff_size); 4163 4164 cmd->type = ((bridge_type << I40E_AQ_LLDP_BRIDGE_TYPE_SHIFT) & 4165 I40E_AQ_LLDP_BRIDGE_TYPE_MASK); 4166 cmd->old_len = CPU_TO_LE16(old_len); 4167 cmd->new_offset = CPU_TO_LE16(offset); 4168 cmd->new_len = CPU_TO_LE16(new_len); 4169 4170 status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details); 4171 if (!status) { 4172 if (mib_len != NULL) 4173 *mib_len = LE16_TO_CPU(desc.datalen); 4174 } 4175 4176 return status; 4177 } 4178 4179 /** 4180 * i40e_aq_delete_lldp_tlv 4181 * @hw: pointer to the hw struct 4182 * @bridge_type: type of bridge 4183 * @buff: pointer to a user supplied buffer that has the TLV 4184 * @buff_size: length of the buffer 4185 * @tlv_len: length of the TLV to be deleted 4186 * @mib_len: length of the returned LLDP MIB 4187 * @cmd_details: pointer to command details structure or NULL 4188 * 4189 * Delete the specified TLV from LLDP Local MIB for the given bridge type. 4190 * The firmware places the entire LLDP MIB in the response buffer. 4191 **/ 4192 enum i40e_status_code i40e_aq_delete_lldp_tlv(struct i40e_hw *hw, 4193 u8 bridge_type, void *buff, u16 buff_size, 4194 u16 tlv_len, u16 *mib_len, 4195 struct i40e_asq_cmd_details *cmd_details) 4196 { 4197 struct i40e_aq_desc desc; 4198 struct i40e_aqc_lldp_add_tlv *cmd = 4199 (struct i40e_aqc_lldp_add_tlv *)&desc.params.raw; 4200 enum i40e_status_code status; 4201 4202 if (buff_size == 0 || !buff) 4203 return I40E_ERR_PARAM; 4204 4205 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_delete_tlv); 4206 4207 /* Indirect Command */ 4208 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD)); 4209 if (buff_size > I40E_AQ_LARGE_BUF) 4210 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB); 4211 desc.datalen = CPU_TO_LE16(buff_size); 4212 cmd->len = CPU_TO_LE16(tlv_len); 4213 cmd->type = ((bridge_type << I40E_AQ_LLDP_BRIDGE_TYPE_SHIFT) & 4214 I40E_AQ_LLDP_BRIDGE_TYPE_MASK); 4215 4216 status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details); 4217 if (!status) { 4218 if (mib_len != NULL) 4219 *mib_len = LE16_TO_CPU(desc.datalen); 4220 } 4221 4222 return status; 4223 } 4224 4225 /** 4226 * i40e_aq_stop_lldp 4227 * @hw: pointer to the hw struct 4228 * @shutdown_agent: True if LLDP Agent needs to be Shutdown 4229 * @cmd_details: pointer to command details structure or NULL 4230 * 4231 * Stop or Shutdown the embedded LLDP Agent 4232 **/ 4233 enum i40e_status_code i40e_aq_stop_lldp(struct i40e_hw *hw, bool shutdown_agent, 4234 struct i40e_asq_cmd_details *cmd_details) 4235 { 4236 struct i40e_aq_desc desc; 4237 struct i40e_aqc_lldp_stop *cmd = 4238 (struct i40e_aqc_lldp_stop *)&desc.params.raw; 4239 enum i40e_status_code status; 4240 4241 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_stop); 4242 4243 if (shutdown_agent) 4244 cmd->command |= I40E_AQ_LLDP_AGENT_SHUTDOWN; 4245 4246 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 4247 4248 return status; 4249 } 4250 4251 /** 4252 * i40e_aq_start_lldp 4253 * @hw: pointer to the hw struct 4254 * @cmd_details: pointer to command details structure or NULL 4255 * 4256 * Start the embedded LLDP Agent on all ports. 4257 **/ 4258 enum i40e_status_code i40e_aq_start_lldp(struct i40e_hw *hw, 4259 struct i40e_asq_cmd_details *cmd_details) 4260 { 4261 struct i40e_aq_desc desc; 4262 struct i40e_aqc_lldp_start *cmd = 4263 (struct i40e_aqc_lldp_start *)&desc.params.raw; 4264 enum i40e_status_code status; 4265 4266 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_start); 4267 4268 cmd->command = I40E_AQ_LLDP_AGENT_START; 4269 4270 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 4271 4272 return status; 4273 } 4274 4275 /** 4276 * i40e_aq_get_cee_dcb_config 4277 * @hw: pointer to the hw struct 4278 * @buff: response buffer that stores CEE operational configuration 4279 * @buff_size: size of the buffer passed 4280 * @cmd_details: pointer to command details structure or NULL 4281 * 4282 * Get CEE DCBX mode operational configuration from firmware 4283 **/ 4284 enum i40e_status_code i40e_aq_get_cee_dcb_config(struct i40e_hw *hw, 4285 void *buff, u16 buff_size, 4286 struct i40e_asq_cmd_details *cmd_details) 4287 { 4288 struct i40e_aq_desc desc; 4289 enum i40e_status_code status; 4290 4291 if (buff_size == 0 || !buff) 4292 return I40E_ERR_PARAM; 4293 4294 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_get_cee_dcb_cfg); 4295 4296 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF); 4297 status = i40e_asq_send_command(hw, &desc, (void *)buff, buff_size, 4298 cmd_details); 4299 4300 return status; 4301 } 4302 4303 /** 4304 * i40e_aq_start_stop_dcbx - Start/Stop DCBx service in FW 4305 * @hw: pointer to the hw struct 4306 * @start_agent: True if DCBx Agent needs to be Started 4307 * False if DCBx Agent needs to be Stopped 4308 * @cmd_details: pointer to command details structure or NULL 4309 * 4310 * Start/Stop the embedded dcbx Agent 4311 **/ 4312 enum i40e_status_code i40e_aq_start_stop_dcbx(struct i40e_hw *hw, 4313 bool start_agent, 4314 struct i40e_asq_cmd_details *cmd_details) 4315 { 4316 struct i40e_aq_desc desc; 4317 struct i40e_aqc_lldp_stop_start_specific_agent *cmd = 4318 (struct i40e_aqc_lldp_stop_start_specific_agent *) 4319 &desc.params.raw; 4320 enum i40e_status_code status; 4321 4322 i40e_fill_default_direct_cmd_desc(&desc, 4323 i40e_aqc_opc_lldp_stop_start_spec_agent); 4324 4325 if (start_agent) 4326 cmd->command = I40E_AQC_START_SPECIFIC_AGENT_MASK; 4327 4328 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 4329 4330 return status; 4331 } 4332 4333 /** 4334 * i40e_aq_add_udp_tunnel 4335 * @hw: pointer to the hw struct 4336 * @udp_port: the UDP port to add 4337 * @header_len: length of the tunneling header length in DWords 4338 * @protocol_index: protocol index type 4339 * @filter_index: pointer to filter index 4340 * @cmd_details: pointer to command details structure or NULL 4341 **/ 4342 enum i40e_status_code i40e_aq_add_udp_tunnel(struct i40e_hw *hw, 4343 u16 udp_port, u8 protocol_index, 4344 u8 *filter_index, 4345 struct i40e_asq_cmd_details *cmd_details) 4346 { 4347 struct i40e_aq_desc desc; 4348 struct i40e_aqc_add_udp_tunnel *cmd = 4349 (struct i40e_aqc_add_udp_tunnel *)&desc.params.raw; 4350 struct i40e_aqc_del_udp_tunnel_completion *resp = 4351 (struct i40e_aqc_del_udp_tunnel_completion *)&desc.params.raw; 4352 enum i40e_status_code status; 4353 4354 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_add_udp_tunnel); 4355 4356 cmd->udp_port = CPU_TO_LE16(udp_port); 4357 cmd->protocol_type = protocol_index; 4358 4359 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 4360 4361 if (!status && filter_index) 4362 *filter_index = resp->index; 4363 4364 return status; 4365 } 4366 4367 /** 4368 * i40e_aq_del_udp_tunnel 4369 * @hw: pointer to the hw struct 4370 * @index: filter index 4371 * @cmd_details: pointer to command details structure or NULL 4372 **/ 4373 enum i40e_status_code i40e_aq_del_udp_tunnel(struct i40e_hw *hw, u8 index, 4374 struct i40e_asq_cmd_details *cmd_details) 4375 { 4376 struct i40e_aq_desc desc; 4377 struct i40e_aqc_remove_udp_tunnel *cmd = 4378 (struct i40e_aqc_remove_udp_tunnel *)&desc.params.raw; 4379 enum i40e_status_code status; 4380 4381 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_del_udp_tunnel); 4382 4383 cmd->index = index; 4384 4385 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 4386 4387 return status; 4388 } 4389 4390 /** 4391 * i40e_aq_get_switch_resource_alloc (0x0204) 4392 * @hw: pointer to the hw struct 4393 * @num_entries: pointer to u8 to store the number of resource entries returned 4394 * @buf: pointer to a user supplied buffer. This buffer must be large enough 4395 * to store the resource information for all resource types. Each 4396 * resource type is a i40e_aqc_switch_resource_alloc_data structure. 4397 * @count: size, in bytes, of the buffer provided 4398 * @cmd_details: pointer to command details structure or NULL 4399 * 4400 * Query the resources allocated to a function. 4401 **/ 4402 enum i40e_status_code i40e_aq_get_switch_resource_alloc(struct i40e_hw *hw, 4403 u8 *num_entries, 4404 struct i40e_aqc_switch_resource_alloc_element_resp *buf, 4405 u16 count, 4406 struct i40e_asq_cmd_details *cmd_details) 4407 { 4408 struct i40e_aq_desc desc; 4409 struct i40e_aqc_get_switch_resource_alloc *cmd_resp = 4410 (struct i40e_aqc_get_switch_resource_alloc *)&desc.params.raw; 4411 enum i40e_status_code status; 4412 u16 length = count * sizeof(*buf); 4413 4414 i40e_fill_default_direct_cmd_desc(&desc, 4415 i40e_aqc_opc_get_switch_resource_alloc); 4416 4417 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF); 4418 if (length > I40E_AQ_LARGE_BUF) 4419 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB); 4420 4421 status = i40e_asq_send_command(hw, &desc, buf, length, cmd_details); 4422 4423 if (!status && num_entries) 4424 *num_entries = cmd_resp->num_entries; 4425 4426 return status; 4427 } 4428 4429 /** 4430 * i40e_aq_delete_element - Delete switch element 4431 * @hw: pointer to the hw struct 4432 * @seid: the SEID to delete from the switch 4433 * @cmd_details: pointer to command details structure or NULL 4434 * 4435 * This deletes a switch element from the switch. 4436 **/ 4437 enum i40e_status_code i40e_aq_delete_element(struct i40e_hw *hw, u16 seid, 4438 struct i40e_asq_cmd_details *cmd_details) 4439 { 4440 struct i40e_aq_desc desc; 4441 struct i40e_aqc_switch_seid *cmd = 4442 (struct i40e_aqc_switch_seid *)&desc.params.raw; 4443 enum i40e_status_code status; 4444 4445 if (seid == 0) 4446 return I40E_ERR_PARAM; 4447 4448 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_delete_element); 4449 4450 cmd->seid = CPU_TO_LE16(seid); 4451 4452 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 4453 4454 return status; 4455 } 4456 4457 /** 4458 * i40e_aq_add_pvirt - Instantiate a Port Virtualizer on a port 4459 * @hw: pointer to the hw struct 4460 * @flags: component flags 4461 * @mac_seid: uplink seid (MAC SEID) 4462 * @vsi_seid: connected vsi seid 4463 * @ret_seid: seid of create pv component 4464 * 4465 * This instantiates an i40e port virtualizer with specified flags. 4466 * Depending on specified flags the port virtualizer can act as a 4467 * 802.1Qbr port virtualizer or a 802.1Qbg S-component. 4468 */ 4469 enum i40e_status_code i40e_aq_add_pvirt(struct i40e_hw *hw, u16 flags, 4470 u16 mac_seid, u16 vsi_seid, 4471 u16 *ret_seid) 4472 { 4473 struct i40e_aq_desc desc; 4474 struct i40e_aqc_add_update_pv *cmd = 4475 (struct i40e_aqc_add_update_pv *)&desc.params.raw; 4476 struct i40e_aqc_add_update_pv_completion *resp = 4477 (struct i40e_aqc_add_update_pv_completion *)&desc.params.raw; 4478 enum i40e_status_code status; 4479 4480 if (vsi_seid == 0) 4481 return I40E_ERR_PARAM; 4482 4483 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_add_pv); 4484 cmd->command_flags = CPU_TO_LE16(flags); 4485 cmd->uplink_seid = CPU_TO_LE16(mac_seid); 4486 cmd->connected_seid = CPU_TO_LE16(vsi_seid); 4487 4488 status = i40e_asq_send_command(hw, &desc, NULL, 0, NULL); 4489 if (!status && ret_seid) 4490 *ret_seid = LE16_TO_CPU(resp->pv_seid); 4491 4492 return status; 4493 } 4494 4495 /** 4496 * i40e_aq_add_tag - Add an S/E-tag 4497 * @hw: pointer to the hw struct 4498 * @direct_to_queue: should s-tag direct flow to a specific queue 4499 * @vsi_seid: VSI SEID to use this tag 4500 * @tag: value of the tag 4501 * @queue_num: queue number, only valid is direct_to_queue is TRUE 4502 * @tags_used: return value, number of tags in use by this PF 4503 * @tags_free: return value, number of unallocated tags 4504 * @cmd_details: pointer to command details structure or NULL 4505 * 4506 * This associates an S- or E-tag to a VSI in the switch complex. It returns 4507 * the number of tags allocated by the PF, and the number of unallocated 4508 * tags available. 4509 **/ 4510 enum i40e_status_code i40e_aq_add_tag(struct i40e_hw *hw, bool direct_to_queue, 4511 u16 vsi_seid, u16 tag, u16 queue_num, 4512 u16 *tags_used, u16 *tags_free, 4513 struct i40e_asq_cmd_details *cmd_details) 4514 { 4515 struct i40e_aq_desc desc; 4516 struct i40e_aqc_add_tag *cmd = 4517 (struct i40e_aqc_add_tag *)&desc.params.raw; 4518 struct i40e_aqc_add_remove_tag_completion *resp = 4519 (struct i40e_aqc_add_remove_tag_completion *)&desc.params.raw; 4520 enum i40e_status_code status; 4521 4522 if (vsi_seid == 0) 4523 return I40E_ERR_PARAM; 4524 4525 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_add_tag); 4526 4527 cmd->seid = CPU_TO_LE16(vsi_seid); 4528 cmd->tag = CPU_TO_LE16(tag); 4529 if (direct_to_queue) { 4530 cmd->flags = CPU_TO_LE16(I40E_AQC_ADD_TAG_FLAG_TO_QUEUE); 4531 cmd->queue_number = CPU_TO_LE16(queue_num); 4532 } 4533 4534 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 4535 4536 if (!status) { 4537 if (tags_used != NULL) 4538 *tags_used = LE16_TO_CPU(resp->tags_used); 4539 if (tags_free != NULL) 4540 *tags_free = LE16_TO_CPU(resp->tags_free); 4541 } 4542 4543 return status; 4544 } 4545 4546 /** 4547 * i40e_aq_remove_tag - Remove an S- or E-tag 4548 * @hw: pointer to the hw struct 4549 * @vsi_seid: VSI SEID this tag is associated with 4550 * @tag: value of the S-tag to delete 4551 * @tags_used: return value, number of tags in use by this PF 4552 * @tags_free: return value, number of unallocated tags 4553 * @cmd_details: pointer to command details structure or NULL 4554 * 4555 * This deletes an S- or E-tag from a VSI in the switch complex. It returns 4556 * the number of tags allocated by the PF, and the number of unallocated 4557 * tags available. 4558 **/ 4559 enum i40e_status_code i40e_aq_remove_tag(struct i40e_hw *hw, u16 vsi_seid, 4560 u16 tag, u16 *tags_used, u16 *tags_free, 4561 struct i40e_asq_cmd_details *cmd_details) 4562 { 4563 struct i40e_aq_desc desc; 4564 struct i40e_aqc_remove_tag *cmd = 4565 (struct i40e_aqc_remove_tag *)&desc.params.raw; 4566 struct i40e_aqc_add_remove_tag_completion *resp = 4567 (struct i40e_aqc_add_remove_tag_completion *)&desc.params.raw; 4568 enum i40e_status_code status; 4569 4570 if (vsi_seid == 0) 4571 return I40E_ERR_PARAM; 4572 4573 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_remove_tag); 4574 4575 cmd->seid = CPU_TO_LE16(vsi_seid); 4576 cmd->tag = CPU_TO_LE16(tag); 4577 4578 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 4579 4580 if (!status) { 4581 if (tags_used != NULL) 4582 *tags_used = LE16_TO_CPU(resp->tags_used); 4583 if (tags_free != NULL) 4584 *tags_free = LE16_TO_CPU(resp->tags_free); 4585 } 4586 4587 return status; 4588 } 4589 4590 /** 4591 * i40e_aq_add_mcast_etag - Add a multicast E-tag 4592 * @hw: pointer to the hw struct 4593 * @pv_seid: Port Virtualizer of this SEID to associate E-tag with 4594 * @etag: value of E-tag to add 4595 * @num_tags_in_buf: number of unicast E-tags in indirect buffer 4596 * @buf: address of indirect buffer 4597 * @tags_used: return value, number of E-tags in use by this port 4598 * @tags_free: return value, number of unallocated M-tags 4599 * @cmd_details: pointer to command details structure or NULL 4600 * 4601 * This associates a multicast E-tag to a port virtualizer. It will return 4602 * the number of tags allocated by the PF, and the number of unallocated 4603 * tags available. 4604 * 4605 * The indirect buffer pointed to by buf is a list of 2-byte E-tags, 4606 * num_tags_in_buf long. 4607 **/ 4608 enum i40e_status_code i40e_aq_add_mcast_etag(struct i40e_hw *hw, u16 pv_seid, 4609 u16 etag, u8 num_tags_in_buf, void *buf, 4610 u16 *tags_used, u16 *tags_free, 4611 struct i40e_asq_cmd_details *cmd_details) 4612 { 4613 struct i40e_aq_desc desc; 4614 struct i40e_aqc_add_remove_mcast_etag *cmd = 4615 (struct i40e_aqc_add_remove_mcast_etag *)&desc.params.raw; 4616 struct i40e_aqc_add_remove_mcast_etag_completion *resp = 4617 (struct i40e_aqc_add_remove_mcast_etag_completion *)&desc.params.raw; 4618 enum i40e_status_code status; 4619 u16 length = sizeof(u16) * num_tags_in_buf; 4620 4621 if ((pv_seid == 0) || (buf == NULL) || (num_tags_in_buf == 0)) 4622 return I40E_ERR_PARAM; 4623 4624 i40e_fill_default_direct_cmd_desc(&desc, 4625 i40e_aqc_opc_add_multicast_etag); 4626 4627 cmd->pv_seid = CPU_TO_LE16(pv_seid); 4628 cmd->etag = CPU_TO_LE16(etag); 4629 cmd->num_unicast_etags = num_tags_in_buf; 4630 4631 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD)); 4632 if (length > I40E_AQ_LARGE_BUF) 4633 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB); 4634 4635 status = i40e_asq_send_command(hw, &desc, buf, length, cmd_details); 4636 4637 if (!status) { 4638 if (tags_used != NULL) 4639 *tags_used = LE16_TO_CPU(resp->mcast_etags_used); 4640 if (tags_free != NULL) 4641 *tags_free = LE16_TO_CPU(resp->mcast_etags_free); 4642 } 4643 4644 return status; 4645 } 4646 4647 /** 4648 * i40e_aq_remove_mcast_etag - Remove a multicast E-tag 4649 * @hw: pointer to the hw struct 4650 * @pv_seid: Port Virtualizer SEID this M-tag is associated with 4651 * @etag: value of the E-tag to remove 4652 * @tags_used: return value, number of tags in use by this port 4653 * @tags_free: return value, number of unallocated tags 4654 * @cmd_details: pointer to command details structure or NULL 4655 * 4656 * This deletes an E-tag from the port virtualizer. It will return 4657 * the number of tags allocated by the port, and the number of unallocated 4658 * tags available. 4659 **/ 4660 enum i40e_status_code i40e_aq_remove_mcast_etag(struct i40e_hw *hw, u16 pv_seid, 4661 u16 etag, u16 *tags_used, u16 *tags_free, 4662 struct i40e_asq_cmd_details *cmd_details) 4663 { 4664 struct i40e_aq_desc desc; 4665 struct i40e_aqc_add_remove_mcast_etag *cmd = 4666 (struct i40e_aqc_add_remove_mcast_etag *)&desc.params.raw; 4667 struct i40e_aqc_add_remove_mcast_etag_completion *resp = 4668 (struct i40e_aqc_add_remove_mcast_etag_completion *)&desc.params.raw; 4669 enum i40e_status_code status; 4670 4671 4672 if (pv_seid == 0) 4673 return I40E_ERR_PARAM; 4674 4675 i40e_fill_default_direct_cmd_desc(&desc, 4676 i40e_aqc_opc_remove_multicast_etag); 4677 4678 cmd->pv_seid = CPU_TO_LE16(pv_seid); 4679 cmd->etag = CPU_TO_LE16(etag); 4680 4681 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 4682 4683 if (!status) { 4684 if (tags_used != NULL) 4685 *tags_used = LE16_TO_CPU(resp->mcast_etags_used); 4686 if (tags_free != NULL) 4687 *tags_free = LE16_TO_CPU(resp->mcast_etags_free); 4688 } 4689 4690 return status; 4691 } 4692 4693 /** 4694 * i40e_aq_update_tag - Update an S/E-tag 4695 * @hw: pointer to the hw struct 4696 * @vsi_seid: VSI SEID using this S-tag 4697 * @old_tag: old tag value 4698 * @new_tag: new tag value 4699 * @tags_used: return value, number of tags in use by this PF 4700 * @tags_free: return value, number of unallocated tags 4701 * @cmd_details: pointer to command details structure or NULL 4702 * 4703 * This updates the value of the tag currently attached to this VSI 4704 * in the switch complex. It will return the number of tags allocated 4705 * by the PF, and the number of unallocated tags available. 4706 **/ 4707 enum i40e_status_code i40e_aq_update_tag(struct i40e_hw *hw, u16 vsi_seid, 4708 u16 old_tag, u16 new_tag, u16 *tags_used, 4709 u16 *tags_free, 4710 struct i40e_asq_cmd_details *cmd_details) 4711 { 4712 struct i40e_aq_desc desc; 4713 struct i40e_aqc_update_tag *cmd = 4714 (struct i40e_aqc_update_tag *)&desc.params.raw; 4715 struct i40e_aqc_update_tag_completion *resp = 4716 (struct i40e_aqc_update_tag_completion *)&desc.params.raw; 4717 enum i40e_status_code status; 4718 4719 if (vsi_seid == 0) 4720 return I40E_ERR_PARAM; 4721 4722 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_update_tag); 4723 4724 cmd->seid = CPU_TO_LE16(vsi_seid); 4725 cmd->old_tag = CPU_TO_LE16(old_tag); 4726 cmd->new_tag = CPU_TO_LE16(new_tag); 4727 4728 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 4729 4730 if (!status) { 4731 if (tags_used != NULL) 4732 *tags_used = LE16_TO_CPU(resp->tags_used); 4733 if (tags_free != NULL) 4734 *tags_free = LE16_TO_CPU(resp->tags_free); 4735 } 4736 4737 return status; 4738 } 4739 4740 /** 4741 * i40e_aq_dcb_ignore_pfc - Ignore PFC for given TCs 4742 * @hw: pointer to the hw struct 4743 * @tcmap: TC map for request/release any ignore PFC condition 4744 * @request: request or release ignore PFC condition 4745 * @tcmap_ret: return TCs for which PFC is currently ignored 4746 * @cmd_details: pointer to command details structure or NULL 4747 * 4748 * This sends out request/release to ignore PFC condition for a TC. 4749 * It will return the TCs for which PFC is currently ignored. 4750 **/ 4751 enum i40e_status_code i40e_aq_dcb_ignore_pfc(struct i40e_hw *hw, u8 tcmap, 4752 bool request, u8 *tcmap_ret, 4753 struct i40e_asq_cmd_details *cmd_details) 4754 { 4755 struct i40e_aq_desc desc; 4756 struct i40e_aqc_pfc_ignore *cmd_resp = 4757 (struct i40e_aqc_pfc_ignore *)&desc.params.raw; 4758 enum i40e_status_code status; 4759 4760 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_dcb_ignore_pfc); 4761 4762 if (request) 4763 cmd_resp->command_flags = I40E_AQC_PFC_IGNORE_SET; 4764 4765 cmd_resp->tc_bitmap = tcmap; 4766 4767 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 4768 4769 if (!status) { 4770 if (tcmap_ret != NULL) 4771 *tcmap_ret = cmd_resp->tc_bitmap; 4772 } 4773 4774 return status; 4775 } 4776 4777 /** 4778 * i40e_aq_dcb_updated - DCB Updated Command 4779 * @hw: pointer to the hw struct 4780 * @cmd_details: pointer to command details structure or NULL 4781 * 4782 * When LLDP is handled in PF this command is used by the PF 4783 * to notify EMP that a DCB setting is modified. 4784 * When LLDP is handled in EMP this command is used by the PF 4785 * to notify EMP whenever one of the following parameters get 4786 * modified: 4787 * - PFCLinkDelayAllowance in PRTDCB_GENC.PFCLDA 4788 * - PCIRTT in PRTDCB_GENC.PCIRTT 4789 * - Maximum Frame Size for non-FCoE TCs set by PRTDCB_TDPUC.MAX_TXFRAME. 4790 * EMP will return when the shared RPB settings have been 4791 * recomputed and modified. The retval field in the descriptor 4792 * will be set to 0 when RPB is modified. 4793 **/ 4794 enum i40e_status_code i40e_aq_dcb_updated(struct i40e_hw *hw, 4795 struct i40e_asq_cmd_details *cmd_details) 4796 { 4797 struct i40e_aq_desc desc; 4798 enum i40e_status_code status; 4799 4800 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_dcb_updated); 4801 4802 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 4803 4804 return status; 4805 } 4806 4807 /** 4808 * i40e_aq_add_statistics - Add a statistics block to a VLAN in a switch. 4809 * @hw: pointer to the hw struct 4810 * @seid: defines the SEID of the switch for which the stats are requested 4811 * @vlan_id: the VLAN ID for which the statistics are requested 4812 * @stat_index: index of the statistics counters block assigned to this VLAN 4813 * @cmd_details: pointer to command details structure or NULL 4814 * 4815 * XL710 supports 128 smonVlanStats counters.This command is used to 4816 * allocate a set of smonVlanStats counters to a specific VLAN in a specific 4817 * switch. 4818 **/ 4819 enum i40e_status_code i40e_aq_add_statistics(struct i40e_hw *hw, u16 seid, 4820 u16 vlan_id, u16 *stat_index, 4821 struct i40e_asq_cmd_details *cmd_details) 4822 { 4823 struct i40e_aq_desc desc; 4824 struct i40e_aqc_add_remove_statistics *cmd_resp = 4825 (struct i40e_aqc_add_remove_statistics *)&desc.params.raw; 4826 enum i40e_status_code status; 4827 4828 if ((seid == 0) || (stat_index == NULL)) 4829 return I40E_ERR_PARAM; 4830 4831 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_add_statistics); 4832 4833 cmd_resp->seid = CPU_TO_LE16(seid); 4834 cmd_resp->vlan = CPU_TO_LE16(vlan_id); 4835 4836 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 4837 4838 if (!status && stat_index) 4839 *stat_index = LE16_TO_CPU(cmd_resp->stat_index); 4840 4841 return status; 4842 } 4843 4844 /** 4845 * i40e_aq_remove_statistics - Remove a statistics block to a VLAN in a switch. 4846 * @hw: pointer to the hw struct 4847 * @seid: defines the SEID of the switch for which the stats are requested 4848 * @vlan_id: the VLAN ID for which the statistics are requested 4849 * @stat_index: index of the statistics counters block assigned to this VLAN 4850 * @cmd_details: pointer to command details structure or NULL 4851 * 4852 * XL710 supports 128 smonVlanStats counters.This command is used to 4853 * deallocate a set of smonVlanStats counters to a specific VLAN in a specific 4854 * switch. 4855 **/ 4856 enum i40e_status_code i40e_aq_remove_statistics(struct i40e_hw *hw, u16 seid, 4857 u16 vlan_id, u16 stat_index, 4858 struct i40e_asq_cmd_details *cmd_details) 4859 { 4860 struct i40e_aq_desc desc; 4861 struct i40e_aqc_add_remove_statistics *cmd = 4862 (struct i40e_aqc_add_remove_statistics *)&desc.params.raw; 4863 enum i40e_status_code status; 4864 4865 if (seid == 0) 4866 return I40E_ERR_PARAM; 4867 4868 i40e_fill_default_direct_cmd_desc(&desc, 4869 i40e_aqc_opc_remove_statistics); 4870 4871 cmd->seid = CPU_TO_LE16(seid); 4872 cmd->vlan = CPU_TO_LE16(vlan_id); 4873 cmd->stat_index = CPU_TO_LE16(stat_index); 4874 4875 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 4876 4877 return status; 4878 } 4879 4880 /** 4881 * i40e_aq_set_port_parameters - set physical port parameters. 4882 * @hw: pointer to the hw struct 4883 * @bad_frame_vsi: defines the VSI to which bad frames are forwarded 4884 * @save_bad_pac: if set packets with errors are forwarded to the bad frames VSI 4885 * @pad_short_pac: if set transmit packets smaller than 60 bytes are padded 4886 * @double_vlan: if set double VLAN is enabled 4887 * @cmd_details: pointer to command details structure or NULL 4888 **/ 4889 enum i40e_status_code i40e_aq_set_port_parameters(struct i40e_hw *hw, 4890 u16 bad_frame_vsi, bool save_bad_pac, 4891 bool pad_short_pac, bool double_vlan, 4892 struct i40e_asq_cmd_details *cmd_details) 4893 { 4894 struct i40e_aqc_set_port_parameters *cmd; 4895 enum i40e_status_code status; 4896 struct i40e_aq_desc desc; 4897 u16 command_flags = 0; 4898 4899 cmd = (struct i40e_aqc_set_port_parameters *)&desc.params.raw; 4900 4901 i40e_fill_default_direct_cmd_desc(&desc, 4902 i40e_aqc_opc_set_port_parameters); 4903 4904 cmd->bad_frame_vsi = CPU_TO_LE16(bad_frame_vsi); 4905 if (save_bad_pac) 4906 command_flags |= I40E_AQ_SET_P_PARAMS_SAVE_BAD_PACKETS; 4907 if (pad_short_pac) 4908 command_flags |= I40E_AQ_SET_P_PARAMS_PAD_SHORT_PACKETS; 4909 if (double_vlan) 4910 command_flags |= I40E_AQ_SET_P_PARAMS_DOUBLE_VLAN_ENA; 4911 cmd->command_flags = CPU_TO_LE16(command_flags); 4912 4913 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 4914 4915 return status; 4916 } 4917 4918 /** 4919 * i40e_aq_tx_sched_cmd - generic Tx scheduler AQ command handler 4920 * @hw: pointer to the hw struct 4921 * @seid: seid for the physical port/switching component/vsi 4922 * @buff: Indirect buffer to hold data parameters and response 4923 * @buff_size: Indirect buffer size 4924 * @opcode: Tx scheduler AQ command opcode 4925 * @cmd_details: pointer to command details structure or NULL 4926 * 4927 * Generic command handler for Tx scheduler AQ commands 4928 **/ 4929 static enum i40e_status_code i40e_aq_tx_sched_cmd(struct i40e_hw *hw, u16 seid, 4930 void *buff, u16 buff_size, 4931 enum i40e_admin_queue_opc opcode, 4932 struct i40e_asq_cmd_details *cmd_details) 4933 { 4934 struct i40e_aq_desc desc; 4935 struct i40e_aqc_tx_sched_ind *cmd = 4936 (struct i40e_aqc_tx_sched_ind *)&desc.params.raw; 4937 enum i40e_status_code status; 4938 bool cmd_param_flag = FALSE; 4939 4940 switch (opcode) { 4941 case i40e_aqc_opc_configure_vsi_ets_sla_bw_limit: 4942 case i40e_aqc_opc_configure_vsi_tc_bw: 4943 case i40e_aqc_opc_enable_switching_comp_ets: 4944 case i40e_aqc_opc_modify_switching_comp_ets: 4945 case i40e_aqc_opc_disable_switching_comp_ets: 4946 case i40e_aqc_opc_configure_switching_comp_ets_bw_limit: 4947 case i40e_aqc_opc_configure_switching_comp_bw_config: 4948 cmd_param_flag = TRUE; 4949 break; 4950 case i40e_aqc_opc_query_vsi_bw_config: 4951 case i40e_aqc_opc_query_vsi_ets_sla_config: 4952 case i40e_aqc_opc_query_switching_comp_ets_config: 4953 case i40e_aqc_opc_query_port_ets_config: 4954 case i40e_aqc_opc_query_switching_comp_bw_config: 4955 cmd_param_flag = FALSE; 4956 break; 4957 default: 4958 return I40E_ERR_PARAM; 4959 } 4960 4961 i40e_fill_default_direct_cmd_desc(&desc, opcode); 4962 4963 /* Indirect command */ 4964 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF); 4965 if (cmd_param_flag) 4966 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_RD); 4967 if (buff_size > I40E_AQ_LARGE_BUF) 4968 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB); 4969 4970 desc.datalen = CPU_TO_LE16(buff_size); 4971 4972 cmd->vsi_seid = CPU_TO_LE16(seid); 4973 4974 status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details); 4975 4976 return status; 4977 } 4978 4979 /** 4980 * i40e_aq_config_vsi_bw_limit - Configure VSI BW Limit 4981 * @hw: pointer to the hw struct 4982 * @seid: VSI seid 4983 * @credit: BW limit credits (0 = disabled) 4984 * @max_credit: Max BW limit credits 4985 * @cmd_details: pointer to command details structure or NULL 4986 **/ 4987 enum i40e_status_code i40e_aq_config_vsi_bw_limit(struct i40e_hw *hw, 4988 u16 seid, u16 credit, u8 max_credit, 4989 struct i40e_asq_cmd_details *cmd_details) 4990 { 4991 struct i40e_aq_desc desc; 4992 struct i40e_aqc_configure_vsi_bw_limit *cmd = 4993 (struct i40e_aqc_configure_vsi_bw_limit *)&desc.params.raw; 4994 enum i40e_status_code status; 4995 4996 i40e_fill_default_direct_cmd_desc(&desc, 4997 i40e_aqc_opc_configure_vsi_bw_limit); 4998 4999 cmd->vsi_seid = CPU_TO_LE16(seid); 5000 cmd->credit = CPU_TO_LE16(credit); 5001 cmd->max_credit = max_credit; 5002 5003 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 5004 5005 return status; 5006 } 5007 5008 /** 5009 * i40e_aq_config_switch_comp_bw_limit - Configure Switching component BW Limit 5010 * @hw: pointer to the hw struct 5011 * @seid: switching component seid 5012 * @credit: BW limit credits (0 = disabled) 5013 * @max_bw: Max BW limit credits 5014 * @cmd_details: pointer to command details structure or NULL 5015 **/ 5016 enum i40e_status_code i40e_aq_config_switch_comp_bw_limit(struct i40e_hw *hw, 5017 u16 seid, u16 credit, u8 max_bw, 5018 struct i40e_asq_cmd_details *cmd_details) 5019 { 5020 struct i40e_aq_desc desc; 5021 struct i40e_aqc_configure_switching_comp_bw_limit *cmd = 5022 (struct i40e_aqc_configure_switching_comp_bw_limit *)&desc.params.raw; 5023 enum i40e_status_code status; 5024 5025 i40e_fill_default_direct_cmd_desc(&desc, 5026 i40e_aqc_opc_configure_switching_comp_bw_limit); 5027 5028 cmd->seid = CPU_TO_LE16(seid); 5029 cmd->credit = CPU_TO_LE16(credit); 5030 cmd->max_bw = max_bw; 5031 5032 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 5033 5034 return status; 5035 } 5036 5037 /** 5038 * i40e_aq_config_vsi_ets_sla_bw_limit - Config VSI BW Limit per TC 5039 * @hw: pointer to the hw struct 5040 * @seid: VSI seid 5041 * @bw_data: Buffer holding enabled TCs, per TC BW limit/credits 5042 * @cmd_details: pointer to command details structure or NULL 5043 **/ 5044 enum i40e_status_code i40e_aq_config_vsi_ets_sla_bw_limit(struct i40e_hw *hw, 5045 u16 seid, 5046 struct i40e_aqc_configure_vsi_ets_sla_bw_data *bw_data, 5047 struct i40e_asq_cmd_details *cmd_details) 5048 { 5049 return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data), 5050 i40e_aqc_opc_configure_vsi_ets_sla_bw_limit, 5051 cmd_details); 5052 } 5053 5054 /** 5055 * i40e_aq_config_vsi_tc_bw - Config VSI BW Allocation per TC 5056 * @hw: pointer to the hw struct 5057 * @seid: VSI seid 5058 * @bw_data: Buffer holding enabled TCs, relative TC BW limit/credits 5059 * @cmd_details: pointer to command details structure or NULL 5060 **/ 5061 enum i40e_status_code i40e_aq_config_vsi_tc_bw(struct i40e_hw *hw, 5062 u16 seid, 5063 struct i40e_aqc_configure_vsi_tc_bw_data *bw_data, 5064 struct i40e_asq_cmd_details *cmd_details) 5065 { 5066 return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data), 5067 i40e_aqc_opc_configure_vsi_tc_bw, 5068 cmd_details); 5069 } 5070 5071 /** 5072 * i40e_aq_config_switch_comp_ets_bw_limit - Config Switch comp BW Limit per TC 5073 * @hw: pointer to the hw struct 5074 * @seid: seid of the switching component 5075 * @bw_data: Buffer holding enabled TCs, per TC BW limit/credits 5076 * @cmd_details: pointer to command details structure or NULL 5077 **/ 5078 enum i40e_status_code i40e_aq_config_switch_comp_ets_bw_limit( 5079 struct i40e_hw *hw, u16 seid, 5080 struct i40e_aqc_configure_switching_comp_ets_bw_limit_data *bw_data, 5081 struct i40e_asq_cmd_details *cmd_details) 5082 { 5083 return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data), 5084 i40e_aqc_opc_configure_switching_comp_ets_bw_limit, 5085 cmd_details); 5086 } 5087 5088 /** 5089 * i40e_aq_query_vsi_bw_config - Query VSI BW configuration 5090 * @hw: pointer to the hw struct 5091 * @seid: seid of the VSI 5092 * @bw_data: Buffer to hold VSI BW configuration 5093 * @cmd_details: pointer to command details structure or NULL 5094 **/ 5095 enum i40e_status_code i40e_aq_query_vsi_bw_config(struct i40e_hw *hw, 5096 u16 seid, 5097 struct i40e_aqc_query_vsi_bw_config_resp *bw_data, 5098 struct i40e_asq_cmd_details *cmd_details) 5099 { 5100 return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data), 5101 i40e_aqc_opc_query_vsi_bw_config, 5102 cmd_details); 5103 } 5104 5105 /** 5106 * i40e_aq_query_vsi_ets_sla_config - Query VSI BW configuration per TC 5107 * @hw: pointer to the hw struct 5108 * @seid: seid of the VSI 5109 * @bw_data: Buffer to hold VSI BW configuration per TC 5110 * @cmd_details: pointer to command details structure or NULL 5111 **/ 5112 enum i40e_status_code i40e_aq_query_vsi_ets_sla_config(struct i40e_hw *hw, 5113 u16 seid, 5114 struct i40e_aqc_query_vsi_ets_sla_config_resp *bw_data, 5115 struct i40e_asq_cmd_details *cmd_details) 5116 { 5117 return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data), 5118 i40e_aqc_opc_query_vsi_ets_sla_config, 5119 cmd_details); 5120 } 5121 5122 /** 5123 * i40e_aq_query_switch_comp_ets_config - Query Switch comp BW config per TC 5124 * @hw: pointer to the hw struct 5125 * @seid: seid of the switching component 5126 * @bw_data: Buffer to hold switching component's per TC BW config 5127 * @cmd_details: pointer to command details structure or NULL 5128 **/ 5129 enum i40e_status_code i40e_aq_query_switch_comp_ets_config(struct i40e_hw *hw, 5130 u16 seid, 5131 struct i40e_aqc_query_switching_comp_ets_config_resp *bw_data, 5132 struct i40e_asq_cmd_details *cmd_details) 5133 { 5134 return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data), 5135 i40e_aqc_opc_query_switching_comp_ets_config, 5136 cmd_details); 5137 } 5138 5139 /** 5140 * i40e_aq_query_port_ets_config - Query Physical Port ETS configuration 5141 * @hw: pointer to the hw struct 5142 * @seid: seid of the VSI or switching component connected to Physical Port 5143 * @bw_data: Buffer to hold current ETS configuration for the Physical Port 5144 * @cmd_details: pointer to command details structure or NULL 5145 **/ 5146 enum i40e_status_code i40e_aq_query_port_ets_config(struct i40e_hw *hw, 5147 u16 seid, 5148 struct i40e_aqc_query_port_ets_config_resp *bw_data, 5149 struct i40e_asq_cmd_details *cmd_details) 5150 { 5151 return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data), 5152 i40e_aqc_opc_query_port_ets_config, 5153 cmd_details); 5154 } 5155 5156 /** 5157 * i40e_aq_query_switch_comp_bw_config - Query Switch comp BW configuration 5158 * @hw: pointer to the hw struct 5159 * @seid: seid of the switching component 5160 * @bw_data: Buffer to hold switching component's BW configuration 5161 * @cmd_details: pointer to command details structure or NULL 5162 **/ 5163 enum i40e_status_code i40e_aq_query_switch_comp_bw_config(struct i40e_hw *hw, 5164 u16 seid, 5165 struct i40e_aqc_query_switching_comp_bw_config_resp *bw_data, 5166 struct i40e_asq_cmd_details *cmd_details) 5167 { 5168 return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data), 5169 i40e_aqc_opc_query_switching_comp_bw_config, 5170 cmd_details); 5171 } 5172 5173 /** 5174 * i40e_validate_filter_settings 5175 * @hw: pointer to the hardware structure 5176 * @settings: Filter control settings 5177 * 5178 * Check and validate the filter control settings passed. 5179 * The function checks for the valid filter/context sizes being 5180 * passed for FCoE and PE. 5181 * 5182 * Returns I40E_SUCCESS if the values passed are valid and within 5183 * range else returns an error. 5184 **/ 5185 static enum i40e_status_code i40e_validate_filter_settings(struct i40e_hw *hw, 5186 struct i40e_filter_control_settings *settings) 5187 { 5188 u32 fcoe_cntx_size, fcoe_filt_size; 5189 u32 pe_cntx_size, pe_filt_size; 5190 u32 fcoe_fmax; 5191 5192 u32 val; 5193 5194 /* Validate FCoE settings passed */ 5195 switch (settings->fcoe_filt_num) { 5196 case I40E_HASH_FILTER_SIZE_1K: 5197 case I40E_HASH_FILTER_SIZE_2K: 5198 case I40E_HASH_FILTER_SIZE_4K: 5199 case I40E_HASH_FILTER_SIZE_8K: 5200 case I40E_HASH_FILTER_SIZE_16K: 5201 case I40E_HASH_FILTER_SIZE_32K: 5202 fcoe_filt_size = I40E_HASH_FILTER_BASE_SIZE; 5203 fcoe_filt_size <<= (u32)settings->fcoe_filt_num; 5204 break; 5205 default: 5206 return I40E_ERR_PARAM; 5207 } 5208 5209 switch (settings->fcoe_cntx_num) { 5210 case I40E_DMA_CNTX_SIZE_512: 5211 case I40E_DMA_CNTX_SIZE_1K: 5212 case I40E_DMA_CNTX_SIZE_2K: 5213 case I40E_DMA_CNTX_SIZE_4K: 5214 fcoe_cntx_size = I40E_DMA_CNTX_BASE_SIZE; 5215 fcoe_cntx_size <<= (u32)settings->fcoe_cntx_num; 5216 break; 5217 default: 5218 return I40E_ERR_PARAM; 5219 } 5220 5221 /* Validate PE settings passed */ 5222 switch (settings->pe_filt_num) { 5223 case I40E_HASH_FILTER_SIZE_1K: 5224 case I40E_HASH_FILTER_SIZE_2K: 5225 case I40E_HASH_FILTER_SIZE_4K: 5226 case I40E_HASH_FILTER_SIZE_8K: 5227 case I40E_HASH_FILTER_SIZE_16K: 5228 case I40E_HASH_FILTER_SIZE_32K: 5229 case I40E_HASH_FILTER_SIZE_64K: 5230 case I40E_HASH_FILTER_SIZE_128K: 5231 case I40E_HASH_FILTER_SIZE_256K: 5232 case I40E_HASH_FILTER_SIZE_512K: 5233 case I40E_HASH_FILTER_SIZE_1M: 5234 pe_filt_size = I40E_HASH_FILTER_BASE_SIZE; 5235 pe_filt_size <<= (u32)settings->pe_filt_num; 5236 break; 5237 default: 5238 return I40E_ERR_PARAM; 5239 } 5240 5241 switch (settings->pe_cntx_num) { 5242 case I40E_DMA_CNTX_SIZE_512: 5243 case I40E_DMA_CNTX_SIZE_1K: 5244 case I40E_DMA_CNTX_SIZE_2K: 5245 case I40E_DMA_CNTX_SIZE_4K: 5246 case I40E_DMA_CNTX_SIZE_8K: 5247 case I40E_DMA_CNTX_SIZE_16K: 5248 case I40E_DMA_CNTX_SIZE_32K: 5249 case I40E_DMA_CNTX_SIZE_64K: 5250 case I40E_DMA_CNTX_SIZE_128K: 5251 case I40E_DMA_CNTX_SIZE_256K: 5252 pe_cntx_size = I40E_DMA_CNTX_BASE_SIZE; 5253 pe_cntx_size <<= (u32)settings->pe_cntx_num; 5254 break; 5255 default: 5256 return I40E_ERR_PARAM; 5257 } 5258 5259 /* FCHSIZE + FCDSIZE should not be greater than PMFCOEFMAX */ 5260 val = rd32(hw, I40E_GLHMC_FCOEFMAX); 5261 fcoe_fmax = (val & I40E_GLHMC_FCOEFMAX_PMFCOEFMAX_MASK) 5262 >> I40E_GLHMC_FCOEFMAX_PMFCOEFMAX_SHIFT; 5263 if (fcoe_filt_size + fcoe_cntx_size > fcoe_fmax) 5264 return I40E_ERR_INVALID_SIZE; 5265 5266 return I40E_SUCCESS; 5267 } 5268 5269 /** 5270 * i40e_set_filter_control 5271 * @hw: pointer to the hardware structure 5272 * @settings: Filter control settings 5273 * 5274 * Set the Queue Filters for PE/FCoE and enable filters required 5275 * for a single PF. It is expected that these settings are programmed 5276 * at the driver initialization time. 5277 **/ 5278 enum i40e_status_code i40e_set_filter_control(struct i40e_hw *hw, 5279 struct i40e_filter_control_settings *settings) 5280 { 5281 enum i40e_status_code ret = I40E_SUCCESS; 5282 u32 hash_lut_size = 0; 5283 u32 val; 5284 5285 if (!settings) 5286 return I40E_ERR_PARAM; 5287 5288 /* Validate the input settings */ 5289 ret = i40e_validate_filter_settings(hw, settings); 5290 if (ret) 5291 return ret; 5292 5293 /* Read the PF Queue Filter control register */ 5294 val = i40e_read_rx_ctl(hw, I40E_PFQF_CTL_0); 5295 5296 /* Program required PE hash buckets for the PF */ 5297 val &= ~I40E_PFQF_CTL_0_PEHSIZE_MASK; 5298 val |= ((u32)settings->pe_filt_num << I40E_PFQF_CTL_0_PEHSIZE_SHIFT) & 5299 I40E_PFQF_CTL_0_PEHSIZE_MASK; 5300 /* Program required PE contexts for the PF */ 5301 val &= ~I40E_PFQF_CTL_0_PEDSIZE_MASK; 5302 val |= ((u32)settings->pe_cntx_num << I40E_PFQF_CTL_0_PEDSIZE_SHIFT) & 5303 I40E_PFQF_CTL_0_PEDSIZE_MASK; 5304 5305 /* Program required FCoE hash buckets for the PF */ 5306 val &= ~I40E_PFQF_CTL_0_PFFCHSIZE_MASK; 5307 val |= ((u32)settings->fcoe_filt_num << 5308 I40E_PFQF_CTL_0_PFFCHSIZE_SHIFT) & 5309 I40E_PFQF_CTL_0_PFFCHSIZE_MASK; 5310 /* Program required FCoE DDP contexts for the PF */ 5311 val &= ~I40E_PFQF_CTL_0_PFFCDSIZE_MASK; 5312 val |= ((u32)settings->fcoe_cntx_num << 5313 I40E_PFQF_CTL_0_PFFCDSIZE_SHIFT) & 5314 I40E_PFQF_CTL_0_PFFCDSIZE_MASK; 5315 5316 /* Program Hash LUT size for the PF */ 5317 val &= ~I40E_PFQF_CTL_0_HASHLUTSIZE_MASK; 5318 if (settings->hash_lut_size == I40E_HASH_LUT_SIZE_512) 5319 hash_lut_size = 1; 5320 val |= (hash_lut_size << I40E_PFQF_CTL_0_HASHLUTSIZE_SHIFT) & 5321 I40E_PFQF_CTL_0_HASHLUTSIZE_MASK; 5322 5323 /* Enable FDIR, Ethertype and MACVLAN filters for PF and VFs */ 5324 if (settings->enable_fdir) 5325 val |= I40E_PFQF_CTL_0_FD_ENA_MASK; 5326 if (settings->enable_ethtype) 5327 val |= I40E_PFQF_CTL_0_ETYPE_ENA_MASK; 5328 if (settings->enable_macvlan) 5329 val |= I40E_PFQF_CTL_0_MACVLAN_ENA_MASK; 5330 5331 i40e_write_rx_ctl(hw, I40E_PFQF_CTL_0, val); 5332 5333 return I40E_SUCCESS; 5334 } 5335 5336 /** 5337 * i40e_aq_add_rem_control_packet_filter - Add or Remove Control Packet Filter 5338 * @hw: pointer to the hw struct 5339 * @mac_addr: MAC address to use in the filter 5340 * @ethtype: Ethertype to use in the filter 5341 * @flags: Flags that needs to be applied to the filter 5342 * @vsi_seid: seid of the control VSI 5343 * @queue: VSI queue number to send the packet to 5344 * @is_add: Add control packet filter if True else remove 5345 * @stats: Structure to hold information on control filter counts 5346 * @cmd_details: pointer to command details structure or NULL 5347 * 5348 * This command will Add or Remove control packet filter for a control VSI. 5349 * In return it will update the total number of perfect filter count in 5350 * the stats member. 5351 **/ 5352 enum i40e_status_code i40e_aq_add_rem_control_packet_filter(struct i40e_hw *hw, 5353 u8 *mac_addr, u16 ethtype, u16 flags, 5354 u16 vsi_seid, u16 queue, bool is_add, 5355 struct i40e_control_filter_stats *stats, 5356 struct i40e_asq_cmd_details *cmd_details) 5357 { 5358 struct i40e_aq_desc desc; 5359 struct i40e_aqc_add_remove_control_packet_filter *cmd = 5360 (struct i40e_aqc_add_remove_control_packet_filter *) 5361 &desc.params.raw; 5362 struct i40e_aqc_add_remove_control_packet_filter_completion *resp = 5363 (struct i40e_aqc_add_remove_control_packet_filter_completion *) 5364 &desc.params.raw; 5365 enum i40e_status_code status; 5366 5367 if (vsi_seid == 0) 5368 return I40E_ERR_PARAM; 5369 5370 if (is_add) { 5371 i40e_fill_default_direct_cmd_desc(&desc, 5372 i40e_aqc_opc_add_control_packet_filter); 5373 cmd->queue = CPU_TO_LE16(queue); 5374 } else { 5375 i40e_fill_default_direct_cmd_desc(&desc, 5376 i40e_aqc_opc_remove_control_packet_filter); 5377 } 5378 5379 if (mac_addr) 5380 i40e_memcpy(cmd->mac, mac_addr, I40E_ETH_LENGTH_OF_ADDRESS, 5381 I40E_NONDMA_TO_NONDMA); 5382 5383 cmd->etype = CPU_TO_LE16(ethtype); 5384 cmd->flags = CPU_TO_LE16(flags); 5385 cmd->seid = CPU_TO_LE16(vsi_seid); 5386 5387 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 5388 5389 if (!status && stats) { 5390 stats->mac_etype_used = LE16_TO_CPU(resp->mac_etype_used); 5391 stats->etype_used = LE16_TO_CPU(resp->etype_used); 5392 stats->mac_etype_free = LE16_TO_CPU(resp->mac_etype_free); 5393 stats->etype_free = LE16_TO_CPU(resp->etype_free); 5394 } 5395 5396 return status; 5397 } 5398 5399 /** 5400 * i40e_add_filter_to_drop_tx_flow_control_frames- filter to drop flow control 5401 * @hw: pointer to the hw struct 5402 * @seid: VSI seid to add ethertype filter from 5403 **/ 5404 #define I40E_FLOW_CONTROL_ETHTYPE 0x8808 5405 void i40e_add_filter_to_drop_tx_flow_control_frames(struct i40e_hw *hw, 5406 u16 seid) 5407 { 5408 u16 flag = I40E_AQC_ADD_CONTROL_PACKET_FLAGS_IGNORE_MAC | 5409 I40E_AQC_ADD_CONTROL_PACKET_FLAGS_DROP | 5410 I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TX; 5411 u16 ethtype = I40E_FLOW_CONTROL_ETHTYPE; 5412 enum i40e_status_code status; 5413 5414 status = i40e_aq_add_rem_control_packet_filter(hw, NULL, ethtype, flag, 5415 seid, 0, TRUE, NULL, 5416 NULL); 5417 if (status) 5418 DEBUGOUT("Ethtype Filter Add failed: Error pruning Tx flow control frames\n"); 5419 } 5420 5421 /** 5422 * i40e_fix_up_geneve_vni - adjust Geneve VNI for HW issue 5423 * @filters: list of cloud filters 5424 * @filter_count: length of list 5425 * 5426 * There's an issue in the device where the Geneve VNI layout needs 5427 * to be shifted 1 byte over from the VxLAN VNI 5428 **/ 5429 static void i40e_fix_up_geneve_vni( 5430 struct i40e_aqc_add_remove_cloud_filters_element_data *filters, 5431 u8 filter_count) 5432 { 5433 struct i40e_aqc_add_remove_cloud_filters_element_data *f = filters; 5434 int i; 5435 5436 for (i = 0; i < filter_count; i++) { 5437 u16 tnl_type; 5438 u32 ti; 5439 5440 tnl_type = (LE16_TO_CPU(f[i].flags) & 5441 I40E_AQC_ADD_CLOUD_TNL_TYPE_MASK) >> 5442 I40E_AQC_ADD_CLOUD_TNL_TYPE_SHIFT; 5443 if (tnl_type == I40E_AQC_ADD_CLOUD_TNL_TYPE_GENEVE) { 5444 ti = LE32_TO_CPU(f[i].tenant_id); 5445 f[i].tenant_id = CPU_TO_LE32(ti << 8); 5446 } 5447 } 5448 } 5449 5450 /** 5451 * i40e_aq_add_cloud_filters 5452 * @hw: pointer to the hardware structure 5453 * @seid: VSI seid to add cloud filters from 5454 * @filters: Buffer which contains the filters to be added 5455 * @filter_count: number of filters contained in the buffer 5456 * 5457 * Set the cloud filters for a given VSI. The contents of the 5458 * i40e_aqc_add_remove_cloud_filters_element_data are filled 5459 * in by the caller of the function. 5460 * 5461 **/ 5462 enum i40e_status_code i40e_aq_add_cloud_filters(struct i40e_hw *hw, 5463 u16 seid, 5464 struct i40e_aqc_add_remove_cloud_filters_element_data *filters, 5465 u8 filter_count) 5466 { 5467 struct i40e_aq_desc desc; 5468 struct i40e_aqc_add_remove_cloud_filters *cmd = 5469 (struct i40e_aqc_add_remove_cloud_filters *)&desc.params.raw; 5470 enum i40e_status_code status; 5471 u16 buff_len; 5472 5473 i40e_fill_default_direct_cmd_desc(&desc, 5474 i40e_aqc_opc_add_cloud_filters); 5475 5476 buff_len = filter_count * sizeof(*filters); 5477 desc.datalen = CPU_TO_LE16(buff_len); 5478 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD)); 5479 cmd->num_filters = filter_count; 5480 cmd->seid = CPU_TO_LE16(seid); 5481 5482 i40e_fix_up_geneve_vni(filters, filter_count); 5483 5484 status = i40e_asq_send_command(hw, &desc, filters, buff_len, NULL); 5485 5486 return status; 5487 } 5488 5489 /** 5490 * i40e_aq_remove_cloud_filters 5491 * @hw: pointer to the hardware structure 5492 * @seid: VSI seid to remove cloud filters from 5493 * @filters: Buffer which contains the filters to be removed 5494 * @filter_count: number of filters contained in the buffer 5495 * 5496 * Remove the cloud filters for a given VSI. The contents of the 5497 * i40e_aqc_add_remove_cloud_filters_element_data are filled 5498 * in by the caller of the function. 5499 * 5500 **/ 5501 enum i40e_status_code i40e_aq_remove_cloud_filters(struct i40e_hw *hw, 5502 u16 seid, 5503 struct i40e_aqc_add_remove_cloud_filters_element_data *filters, 5504 u8 filter_count) 5505 { 5506 struct i40e_aq_desc desc; 5507 struct i40e_aqc_add_remove_cloud_filters *cmd = 5508 (struct i40e_aqc_add_remove_cloud_filters *)&desc.params.raw; 5509 enum i40e_status_code status; 5510 u16 buff_len; 5511 5512 i40e_fill_default_direct_cmd_desc(&desc, 5513 i40e_aqc_opc_remove_cloud_filters); 5514 5515 buff_len = filter_count * sizeof(*filters); 5516 desc.datalen = CPU_TO_LE16(buff_len); 5517 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD)); 5518 cmd->num_filters = filter_count; 5519 cmd->seid = CPU_TO_LE16(seid); 5520 5521 i40e_fix_up_geneve_vni(filters, filter_count); 5522 5523 status = i40e_asq_send_command(hw, &desc, filters, buff_len, NULL); 5524 5525 return status; 5526 } 5527 5528 /** 5529 * i40e_aq_alternate_write 5530 * @hw: pointer to the hardware structure 5531 * @reg_addr0: address of first dword to be read 5532 * @reg_val0: value to be written under 'reg_addr0' 5533 * @reg_addr1: address of second dword to be read 5534 * @reg_val1: value to be written under 'reg_addr1' 5535 * 5536 * Write one or two dwords to alternate structure. Fields are indicated 5537 * by 'reg_addr0' and 'reg_addr1' register numbers. 5538 * 5539 **/ 5540 enum i40e_status_code i40e_aq_alternate_write(struct i40e_hw *hw, 5541 u32 reg_addr0, u32 reg_val0, 5542 u32 reg_addr1, u32 reg_val1) 5543 { 5544 struct i40e_aq_desc desc; 5545 struct i40e_aqc_alternate_write *cmd_resp = 5546 (struct i40e_aqc_alternate_write *)&desc.params.raw; 5547 enum i40e_status_code status; 5548 5549 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_alternate_write); 5550 cmd_resp->address0 = CPU_TO_LE32(reg_addr0); 5551 cmd_resp->address1 = CPU_TO_LE32(reg_addr1); 5552 cmd_resp->data0 = CPU_TO_LE32(reg_val0); 5553 cmd_resp->data1 = CPU_TO_LE32(reg_val1); 5554 5555 status = i40e_asq_send_command(hw, &desc, NULL, 0, NULL); 5556 5557 return status; 5558 } 5559 5560 /** 5561 * i40e_aq_alternate_write_indirect 5562 * @hw: pointer to the hardware structure 5563 * @addr: address of a first register to be modified 5564 * @dw_count: number of alternate structure fields to write 5565 * @buffer: pointer to the command buffer 5566 * 5567 * Write 'dw_count' dwords from 'buffer' to alternate structure 5568 * starting at 'addr'. 5569 * 5570 **/ 5571 enum i40e_status_code i40e_aq_alternate_write_indirect(struct i40e_hw *hw, 5572 u32 addr, u32 dw_count, void *buffer) 5573 { 5574 struct i40e_aq_desc desc; 5575 struct i40e_aqc_alternate_ind_write *cmd_resp = 5576 (struct i40e_aqc_alternate_ind_write *)&desc.params.raw; 5577 enum i40e_status_code status; 5578 5579 if (buffer == NULL) 5580 return I40E_ERR_PARAM; 5581 5582 /* Indirect command */ 5583 i40e_fill_default_direct_cmd_desc(&desc, 5584 i40e_aqc_opc_alternate_write_indirect); 5585 5586 desc.flags |= CPU_TO_LE16(I40E_AQ_FLAG_RD); 5587 desc.flags |= CPU_TO_LE16(I40E_AQ_FLAG_BUF); 5588 if (dw_count > (I40E_AQ_LARGE_BUF/4)) 5589 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB); 5590 5591 cmd_resp->address = CPU_TO_LE32(addr); 5592 cmd_resp->length = CPU_TO_LE32(dw_count); 5593 5594 status = i40e_asq_send_command(hw, &desc, buffer, 5595 I40E_LO_DWORD(4*dw_count), NULL); 5596 5597 return status; 5598 } 5599 5600 /** 5601 * i40e_aq_alternate_read 5602 * @hw: pointer to the hardware structure 5603 * @reg_addr0: address of first dword to be read 5604 * @reg_val0: pointer for data read from 'reg_addr0' 5605 * @reg_addr1: address of second dword to be read 5606 * @reg_val1: pointer for data read from 'reg_addr1' 5607 * 5608 * Read one or two dwords from alternate structure. Fields are indicated 5609 * by 'reg_addr0' and 'reg_addr1' register numbers. If 'reg_val1' pointer 5610 * is not passed then only register at 'reg_addr0' is read. 5611 * 5612 **/ 5613 enum i40e_status_code i40e_aq_alternate_read(struct i40e_hw *hw, 5614 u32 reg_addr0, u32 *reg_val0, 5615 u32 reg_addr1, u32 *reg_val1) 5616 { 5617 struct i40e_aq_desc desc; 5618 struct i40e_aqc_alternate_write *cmd_resp = 5619 (struct i40e_aqc_alternate_write *)&desc.params.raw; 5620 enum i40e_status_code status; 5621 5622 if (reg_val0 == NULL) 5623 return I40E_ERR_PARAM; 5624 5625 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_alternate_read); 5626 cmd_resp->address0 = CPU_TO_LE32(reg_addr0); 5627 cmd_resp->address1 = CPU_TO_LE32(reg_addr1); 5628 5629 status = i40e_asq_send_command(hw, &desc, NULL, 0, NULL); 5630 5631 if (status == I40E_SUCCESS) { 5632 *reg_val0 = LE32_TO_CPU(cmd_resp->data0); 5633 5634 if (reg_val1 != NULL) 5635 *reg_val1 = LE32_TO_CPU(cmd_resp->data1); 5636 } 5637 5638 return status; 5639 } 5640 5641 /** 5642 * i40e_aq_alternate_read_indirect 5643 * @hw: pointer to the hardware structure 5644 * @addr: address of the alternate structure field 5645 * @dw_count: number of alternate structure fields to read 5646 * @buffer: pointer to the command buffer 5647 * 5648 * Read 'dw_count' dwords from alternate structure starting at 'addr' and 5649 * place them in 'buffer'. The buffer should be allocated by caller. 5650 * 5651 **/ 5652 enum i40e_status_code i40e_aq_alternate_read_indirect(struct i40e_hw *hw, 5653 u32 addr, u32 dw_count, void *buffer) 5654 { 5655 struct i40e_aq_desc desc; 5656 struct i40e_aqc_alternate_ind_write *cmd_resp = 5657 (struct i40e_aqc_alternate_ind_write *)&desc.params.raw; 5658 enum i40e_status_code status; 5659 5660 if (buffer == NULL) 5661 return I40E_ERR_PARAM; 5662 5663 /* Indirect command */ 5664 i40e_fill_default_direct_cmd_desc(&desc, 5665 i40e_aqc_opc_alternate_read_indirect); 5666 5667 desc.flags |= CPU_TO_LE16(I40E_AQ_FLAG_RD); 5668 desc.flags |= CPU_TO_LE16(I40E_AQ_FLAG_BUF); 5669 if (dw_count > (I40E_AQ_LARGE_BUF/4)) 5670 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB); 5671 5672 cmd_resp->address = CPU_TO_LE32(addr); 5673 cmd_resp->length = CPU_TO_LE32(dw_count); 5674 5675 status = i40e_asq_send_command(hw, &desc, buffer, 5676 I40E_LO_DWORD(4*dw_count), NULL); 5677 5678 return status; 5679 } 5680 5681 /** 5682 * i40e_aq_alternate_clear 5683 * @hw: pointer to the HW structure. 5684 * 5685 * Clear the alternate structures of the port from which the function 5686 * is called. 5687 * 5688 **/ 5689 enum i40e_status_code i40e_aq_alternate_clear(struct i40e_hw *hw) 5690 { 5691 struct i40e_aq_desc desc; 5692 enum i40e_status_code status; 5693 5694 i40e_fill_default_direct_cmd_desc(&desc, 5695 i40e_aqc_opc_alternate_clear_port); 5696 5697 status = i40e_asq_send_command(hw, &desc, NULL, 0, NULL); 5698 5699 return status; 5700 } 5701 5702 /** 5703 * i40e_aq_alternate_write_done 5704 * @hw: pointer to the HW structure. 5705 * @bios_mode: indicates whether the command is executed by UEFI or legacy BIOS 5706 * @reset_needed: indicates the SW should trigger GLOBAL reset 5707 * 5708 * Indicates to the FW that alternate structures have been changed. 5709 * 5710 **/ 5711 enum i40e_status_code i40e_aq_alternate_write_done(struct i40e_hw *hw, 5712 u8 bios_mode, bool *reset_needed) 5713 { 5714 struct i40e_aq_desc desc; 5715 struct i40e_aqc_alternate_write_done *cmd = 5716 (struct i40e_aqc_alternate_write_done *)&desc.params.raw; 5717 enum i40e_status_code status; 5718 5719 if (reset_needed == NULL) 5720 return I40E_ERR_PARAM; 5721 5722 i40e_fill_default_direct_cmd_desc(&desc, 5723 i40e_aqc_opc_alternate_write_done); 5724 5725 cmd->cmd_flags = CPU_TO_LE16(bios_mode); 5726 5727 status = i40e_asq_send_command(hw, &desc, NULL, 0, NULL); 5728 if (!status && reset_needed) 5729 *reset_needed = ((LE16_TO_CPU(cmd->cmd_flags) & 5730 I40E_AQ_ALTERNATE_RESET_NEEDED) != 0); 5731 5732 return status; 5733 } 5734 5735 /** 5736 * i40e_aq_set_oem_mode 5737 * @hw: pointer to the HW structure. 5738 * @oem_mode: the OEM mode to be used 5739 * 5740 * Sets the device to a specific operating mode. Currently the only supported 5741 * mode is no_clp, which causes FW to refrain from using Alternate RAM. 5742 * 5743 **/ 5744 enum i40e_status_code i40e_aq_set_oem_mode(struct i40e_hw *hw, 5745 u8 oem_mode) 5746 { 5747 struct i40e_aq_desc desc; 5748 struct i40e_aqc_alternate_write_done *cmd = 5749 (struct i40e_aqc_alternate_write_done *)&desc.params.raw; 5750 enum i40e_status_code status; 5751 5752 i40e_fill_default_direct_cmd_desc(&desc, 5753 i40e_aqc_opc_alternate_set_mode); 5754 5755 cmd->cmd_flags = CPU_TO_LE16(oem_mode); 5756 5757 status = i40e_asq_send_command(hw, &desc, NULL, 0, NULL); 5758 5759 return status; 5760 } 5761 5762 /** 5763 * i40e_aq_resume_port_tx 5764 * @hw: pointer to the hardware structure 5765 * @cmd_details: pointer to command details structure or NULL 5766 * 5767 * Resume port's Tx traffic 5768 **/ 5769 enum i40e_status_code i40e_aq_resume_port_tx(struct i40e_hw *hw, 5770 struct i40e_asq_cmd_details *cmd_details) 5771 { 5772 struct i40e_aq_desc desc; 5773 enum i40e_status_code status; 5774 5775 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_resume_port_tx); 5776 5777 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 5778 5779 return status; 5780 } 5781 5782 /** 5783 * i40e_set_pci_config_data - store PCI bus info 5784 * @hw: pointer to hardware structure 5785 * @link_status: the link status word from PCI config space 5786 * 5787 * Stores the PCI bus info (speed, width, type) within the i40e_hw structure 5788 **/ 5789 void i40e_set_pci_config_data(struct i40e_hw *hw, u16 link_status) 5790 { 5791 hw->bus.type = i40e_bus_type_pci_express; 5792 5793 switch (link_status & I40E_PCI_LINK_WIDTH) { 5794 case I40E_PCI_LINK_WIDTH_1: 5795 hw->bus.width = i40e_bus_width_pcie_x1; 5796 break; 5797 case I40E_PCI_LINK_WIDTH_2: 5798 hw->bus.width = i40e_bus_width_pcie_x2; 5799 break; 5800 case I40E_PCI_LINK_WIDTH_4: 5801 hw->bus.width = i40e_bus_width_pcie_x4; 5802 break; 5803 case I40E_PCI_LINK_WIDTH_8: 5804 hw->bus.width = i40e_bus_width_pcie_x8; 5805 break; 5806 default: 5807 hw->bus.width = i40e_bus_width_unknown; 5808 break; 5809 } 5810 5811 switch (link_status & I40E_PCI_LINK_SPEED) { 5812 case I40E_PCI_LINK_SPEED_2500: 5813 hw->bus.speed = i40e_bus_speed_2500; 5814 break; 5815 case I40E_PCI_LINK_SPEED_5000: 5816 hw->bus.speed = i40e_bus_speed_5000; 5817 break; 5818 case I40E_PCI_LINK_SPEED_8000: 5819 hw->bus.speed = i40e_bus_speed_8000; 5820 break; 5821 default: 5822 hw->bus.speed = i40e_bus_speed_unknown; 5823 break; 5824 } 5825 } 5826 5827 /** 5828 * i40e_aq_debug_dump 5829 * @hw: pointer to the hardware structure 5830 * @cluster_id: specific cluster to dump 5831 * @table_id: table id within cluster 5832 * @start_index: index of line in the block to read 5833 * @buff_size: dump buffer size 5834 * @buff: dump buffer 5835 * @ret_buff_size: actual buffer size returned 5836 * @ret_next_table: next block to read 5837 * @ret_next_index: next index to read 5838 * 5839 * Dump internal FW/HW data for debug purposes. 5840 * 5841 **/ 5842 enum i40e_status_code i40e_aq_debug_dump(struct i40e_hw *hw, u8 cluster_id, 5843 u8 table_id, u32 start_index, u16 buff_size, 5844 void *buff, u16 *ret_buff_size, 5845 u8 *ret_next_table, u32 *ret_next_index, 5846 struct i40e_asq_cmd_details *cmd_details) 5847 { 5848 struct i40e_aq_desc desc; 5849 struct i40e_aqc_debug_dump_internals *cmd = 5850 (struct i40e_aqc_debug_dump_internals *)&desc.params.raw; 5851 struct i40e_aqc_debug_dump_internals *resp = 5852 (struct i40e_aqc_debug_dump_internals *)&desc.params.raw; 5853 enum i40e_status_code status; 5854 5855 if (buff_size == 0 || !buff) 5856 return I40E_ERR_PARAM; 5857 5858 i40e_fill_default_direct_cmd_desc(&desc, 5859 i40e_aqc_opc_debug_dump_internals); 5860 /* Indirect Command */ 5861 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF); 5862 if (buff_size > I40E_AQ_LARGE_BUF) 5863 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB); 5864 5865 cmd->cluster_id = cluster_id; 5866 cmd->table_id = table_id; 5867 cmd->idx = CPU_TO_LE32(start_index); 5868 5869 desc.datalen = CPU_TO_LE16(buff_size); 5870 5871 status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details); 5872 if (!status) { 5873 if (ret_buff_size != NULL) 5874 *ret_buff_size = LE16_TO_CPU(desc.datalen); 5875 if (ret_next_table != NULL) 5876 *ret_next_table = resp->table_id; 5877 if (ret_next_index != NULL) 5878 *ret_next_index = LE32_TO_CPU(resp->idx); 5879 } 5880 5881 return status; 5882 } 5883 5884 /** 5885 * i40e_read_bw_from_alt_ram 5886 * @hw: pointer to the hardware structure 5887 * @max_bw: pointer for max_bw read 5888 * @min_bw: pointer for min_bw read 5889 * @min_valid: pointer for bool that is TRUE if min_bw is a valid value 5890 * @max_valid: pointer for bool that is TRUE if max_bw is a valid value 5891 * 5892 * Read bw from the alternate ram for the given pf 5893 **/ 5894 enum i40e_status_code i40e_read_bw_from_alt_ram(struct i40e_hw *hw, 5895 u32 *max_bw, u32 *min_bw, 5896 bool *min_valid, bool *max_valid) 5897 { 5898 enum i40e_status_code status; 5899 u32 max_bw_addr, min_bw_addr; 5900 5901 /* Calculate the address of the min/max bw registers */ 5902 max_bw_addr = I40E_ALT_STRUCT_FIRST_PF_OFFSET + 5903 I40E_ALT_STRUCT_MAX_BW_OFFSET + 5904 (I40E_ALT_STRUCT_DWORDS_PER_PF * hw->pf_id); 5905 min_bw_addr = I40E_ALT_STRUCT_FIRST_PF_OFFSET + 5906 I40E_ALT_STRUCT_MIN_BW_OFFSET + 5907 (I40E_ALT_STRUCT_DWORDS_PER_PF * hw->pf_id); 5908 5909 /* Read the bandwidths from alt ram */ 5910 status = i40e_aq_alternate_read(hw, max_bw_addr, max_bw, 5911 min_bw_addr, min_bw); 5912 5913 if (*min_bw & I40E_ALT_BW_VALID_MASK) 5914 *min_valid = TRUE; 5915 else 5916 *min_valid = FALSE; 5917 5918 if (*max_bw & I40E_ALT_BW_VALID_MASK) 5919 *max_valid = TRUE; 5920 else 5921 *max_valid = FALSE; 5922 5923 return status; 5924 } 5925 5926 /** 5927 * i40e_aq_configure_partition_bw 5928 * @hw: pointer to the hardware structure 5929 * @bw_data: Buffer holding valid pfs and bw limits 5930 * @cmd_details: pointer to command details 5931 * 5932 * Configure partitions guaranteed/max bw 5933 **/ 5934 enum i40e_status_code i40e_aq_configure_partition_bw(struct i40e_hw *hw, 5935 struct i40e_aqc_configure_partition_bw_data *bw_data, 5936 struct i40e_asq_cmd_details *cmd_details) 5937 { 5938 enum i40e_status_code status; 5939 struct i40e_aq_desc desc; 5940 u16 bwd_size = sizeof(*bw_data); 5941 5942 i40e_fill_default_direct_cmd_desc(&desc, 5943 i40e_aqc_opc_configure_partition_bw); 5944 5945 /* Indirect command */ 5946 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF); 5947 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_RD); 5948 5949 desc.datalen = CPU_TO_LE16(bwd_size); 5950 5951 status = i40e_asq_send_command(hw, &desc, bw_data, bwd_size, cmd_details); 5952 5953 return status; 5954 } 5955 5956 /** 5957 * i40e_read_phy_register_clause22 5958 * @hw: pointer to the HW structure 5959 * @reg: register address in the page 5960 * @phy_adr: PHY address on MDIO interface 5961 * @value: PHY register value 5962 * 5963 * Reads specified PHY register value 5964 **/ 5965 enum i40e_status_code i40e_read_phy_register_clause22(struct i40e_hw *hw, 5966 u16 reg, u8 phy_addr, u16 *value) 5967 { 5968 enum i40e_status_code status = I40E_ERR_TIMEOUT; 5969 u8 port_num = (u8)hw->func_caps.mdio_port_num; 5970 u32 command = 0; 5971 u16 retry = 1000; 5972 5973 command = (reg << I40E_GLGEN_MSCA_DEVADD_SHIFT) | 5974 (phy_addr << I40E_GLGEN_MSCA_PHYADD_SHIFT) | 5975 (I40E_MDIO_CLAUSE22_OPCODE_READ_MASK) | 5976 (I40E_MDIO_CLAUSE22_STCODE_MASK) | 5977 (I40E_GLGEN_MSCA_MDICMD_MASK); 5978 wr32(hw, I40E_GLGEN_MSCA(port_num), command); 5979 do { 5980 command = rd32(hw, I40E_GLGEN_MSCA(port_num)); 5981 if (!(command & I40E_GLGEN_MSCA_MDICMD_MASK)) { 5982 status = I40E_SUCCESS; 5983 break; 5984 } 5985 i40e_usec_delay(10); 5986 retry--; 5987 } while (retry); 5988 5989 if (status) { 5990 i40e_debug(hw, I40E_DEBUG_PHY, 5991 "PHY: Can't write command to external PHY.\n"); 5992 } else { 5993 command = rd32(hw, I40E_GLGEN_MSRWD(port_num)); 5994 *value = (command & I40E_GLGEN_MSRWD_MDIRDDATA_MASK) >> 5995 I40E_GLGEN_MSRWD_MDIRDDATA_SHIFT; 5996 } 5997 5998 return status; 5999 } 6000 6001 /** 6002 * i40e_write_phy_register_clause22 6003 * @hw: pointer to the HW structure 6004 * @reg: register address in the page 6005 * @phy_adr: PHY address on MDIO interface 6006 * @value: PHY register value 6007 * 6008 * Writes specified PHY register value 6009 **/ 6010 enum i40e_status_code i40e_write_phy_register_clause22(struct i40e_hw *hw, 6011 u16 reg, u8 phy_addr, u16 value) 6012 { 6013 enum i40e_status_code status = I40E_ERR_TIMEOUT; 6014 u8 port_num = (u8)hw->func_caps.mdio_port_num; 6015 u32 command = 0; 6016 u16 retry = 1000; 6017 6018 command = value << I40E_GLGEN_MSRWD_MDIWRDATA_SHIFT; 6019 wr32(hw, I40E_GLGEN_MSRWD(port_num), command); 6020 6021 command = (reg << I40E_GLGEN_MSCA_DEVADD_SHIFT) | 6022 (phy_addr << I40E_GLGEN_MSCA_PHYADD_SHIFT) | 6023 (I40E_MDIO_CLAUSE22_OPCODE_WRITE_MASK) | 6024 (I40E_MDIO_CLAUSE22_STCODE_MASK) | 6025 (I40E_GLGEN_MSCA_MDICMD_MASK); 6026 6027 wr32(hw, I40E_GLGEN_MSCA(port_num), command); 6028 do { 6029 command = rd32(hw, I40E_GLGEN_MSCA(port_num)); 6030 if (!(command & I40E_GLGEN_MSCA_MDICMD_MASK)) { 6031 status = I40E_SUCCESS; 6032 break; 6033 } 6034 i40e_usec_delay(10); 6035 retry--; 6036 } while (retry); 6037 6038 return status; 6039 } 6040 6041 /** 6042 * i40e_read_phy_register_clause45 6043 * @hw: pointer to the HW structure 6044 * @page: registers page number 6045 * @reg: register address in the page 6046 * @phy_adr: PHY address on MDIO interface 6047 * @value: PHY register value 6048 * 6049 * Reads specified PHY register value 6050 **/ 6051 enum i40e_status_code i40e_read_phy_register_clause45(struct i40e_hw *hw, 6052 u8 page, u16 reg, u8 phy_addr, u16 *value) 6053 { 6054 enum i40e_status_code status = I40E_ERR_TIMEOUT; 6055 u32 command = 0; 6056 u16 retry = 1000; 6057 u8 port_num = (u8)hw->func_caps.mdio_port_num; 6058 6059 command = (reg << I40E_GLGEN_MSCA_MDIADD_SHIFT) | 6060 (page << I40E_GLGEN_MSCA_DEVADD_SHIFT) | 6061 (phy_addr << I40E_GLGEN_MSCA_PHYADD_SHIFT) | 6062 (I40E_MDIO_CLAUSE45_OPCODE_ADDRESS_MASK) | 6063 (I40E_MDIO_CLAUSE45_STCODE_MASK) | 6064 (I40E_GLGEN_MSCA_MDICMD_MASK) | 6065 (I40E_GLGEN_MSCA_MDIINPROGEN_MASK); 6066 wr32(hw, I40E_GLGEN_MSCA(port_num), command); 6067 do { 6068 command = rd32(hw, I40E_GLGEN_MSCA(port_num)); 6069 if (!(command & I40E_GLGEN_MSCA_MDICMD_MASK)) { 6070 status = I40E_SUCCESS; 6071 break; 6072 } 6073 i40e_usec_delay(10); 6074 retry--; 6075 } while (retry); 6076 6077 if (status) { 6078 i40e_debug(hw, I40E_DEBUG_PHY, 6079 "PHY: Can't write command to external PHY.\n"); 6080 goto phy_read_end; 6081 } 6082 6083 command = (page << I40E_GLGEN_MSCA_DEVADD_SHIFT) | 6084 (phy_addr << I40E_GLGEN_MSCA_PHYADD_SHIFT) | 6085 (I40E_MDIO_CLAUSE45_OPCODE_READ_MASK) | 6086 (I40E_MDIO_CLAUSE45_STCODE_MASK) | 6087 (I40E_GLGEN_MSCA_MDICMD_MASK) | 6088 (I40E_GLGEN_MSCA_MDIINPROGEN_MASK); 6089 status = I40E_ERR_TIMEOUT; 6090 retry = 1000; 6091 wr32(hw, I40E_GLGEN_MSCA(port_num), command); 6092 do { 6093 command = rd32(hw, I40E_GLGEN_MSCA(port_num)); 6094 if (!(command & I40E_GLGEN_MSCA_MDICMD_MASK)) { 6095 status = I40E_SUCCESS; 6096 break; 6097 } 6098 i40e_usec_delay(10); 6099 retry--; 6100 } while (retry); 6101 6102 if (!status) { 6103 command = rd32(hw, I40E_GLGEN_MSRWD(port_num)); 6104 *value = (command & I40E_GLGEN_MSRWD_MDIRDDATA_MASK) >> 6105 I40E_GLGEN_MSRWD_MDIRDDATA_SHIFT; 6106 } else { 6107 i40e_debug(hw, I40E_DEBUG_PHY, 6108 "PHY: Can't read register value from external PHY.\n"); 6109 } 6110 6111 phy_read_end: 6112 return status; 6113 } 6114 6115 /** 6116 * i40e_write_phy_register_clause45 6117 * @hw: pointer to the HW structure 6118 * @page: registers page number 6119 * @reg: register address in the page 6120 * @phy_adr: PHY address on MDIO interface 6121 * @value: PHY register value 6122 * 6123 * Writes value to specified PHY register 6124 **/ 6125 enum i40e_status_code i40e_write_phy_register_clause45(struct i40e_hw *hw, 6126 u8 page, u16 reg, u8 phy_addr, u16 value) 6127 { 6128 enum i40e_status_code status = I40E_ERR_TIMEOUT; 6129 u32 command = 0; 6130 u16 retry = 1000; 6131 u8 port_num = (u8)hw->func_caps.mdio_port_num; 6132 6133 command = (reg << I40E_GLGEN_MSCA_MDIADD_SHIFT) | 6134 (page << I40E_GLGEN_MSCA_DEVADD_SHIFT) | 6135 (phy_addr << I40E_GLGEN_MSCA_PHYADD_SHIFT) | 6136 (I40E_MDIO_CLAUSE45_OPCODE_ADDRESS_MASK) | 6137 (I40E_MDIO_CLAUSE45_STCODE_MASK) | 6138 (I40E_GLGEN_MSCA_MDICMD_MASK) | 6139 (I40E_GLGEN_MSCA_MDIINPROGEN_MASK); 6140 wr32(hw, I40E_GLGEN_MSCA(port_num), command); 6141 do { 6142 command = rd32(hw, I40E_GLGEN_MSCA(port_num)); 6143 if (!(command & I40E_GLGEN_MSCA_MDICMD_MASK)) { 6144 status = I40E_SUCCESS; 6145 break; 6146 } 6147 i40e_usec_delay(10); 6148 retry--; 6149 } while (retry); 6150 if (status) { 6151 i40e_debug(hw, I40E_DEBUG_PHY, 6152 "PHY: Can't write command to external PHY.\n"); 6153 goto phy_write_end; 6154 } 6155 6156 command = value << I40E_GLGEN_MSRWD_MDIWRDATA_SHIFT; 6157 wr32(hw, I40E_GLGEN_MSRWD(port_num), command); 6158 6159 command = (page << I40E_GLGEN_MSCA_DEVADD_SHIFT) | 6160 (phy_addr << I40E_GLGEN_MSCA_PHYADD_SHIFT) | 6161 (I40E_MDIO_CLAUSE45_OPCODE_WRITE_MASK) | 6162 (I40E_MDIO_CLAUSE45_STCODE_MASK) | 6163 (I40E_GLGEN_MSCA_MDICMD_MASK) | 6164 (I40E_GLGEN_MSCA_MDIINPROGEN_MASK); 6165 status = I40E_ERR_TIMEOUT; 6166 retry = 1000; 6167 wr32(hw, I40E_GLGEN_MSCA(port_num), command); 6168 do { 6169 command = rd32(hw, I40E_GLGEN_MSCA(port_num)); 6170 if (!(command & I40E_GLGEN_MSCA_MDICMD_MASK)) { 6171 status = I40E_SUCCESS; 6172 break; 6173 } 6174 i40e_usec_delay(10); 6175 retry--; 6176 } while (retry); 6177 6178 phy_write_end: 6179 return status; 6180 } 6181 6182 /** 6183 * i40e_write_phy_register 6184 * @hw: pointer to the HW structure 6185 * @page: registers page number 6186 * @reg: register address in the page 6187 * @phy_adr: PHY address on MDIO interface 6188 * @value: PHY register value 6189 * 6190 * Writes value to specified PHY register 6191 **/ 6192 enum i40e_status_code i40e_write_phy_register(struct i40e_hw *hw, 6193 u8 page, u16 reg, u8 phy_addr, u16 value) 6194 { 6195 enum i40e_status_code status; 6196 6197 switch (hw->device_id) { 6198 case I40E_DEV_ID_1G_BASE_T_X722: 6199 status = i40e_write_phy_register_clause22(hw, 6200 reg, phy_addr, value); 6201 break; 6202 case I40E_DEV_ID_10G_BASE_T: 6203 case I40E_DEV_ID_10G_BASE_T4: 6204 case I40E_DEV_ID_10G_BASE_T_X722: 6205 case I40E_DEV_ID_25G_B: 6206 case I40E_DEV_ID_25G_SFP28: 6207 status = i40e_write_phy_register_clause45(hw, 6208 page, reg, phy_addr, value); 6209 break; 6210 default: 6211 status = I40E_ERR_UNKNOWN_PHY; 6212 break; 6213 } 6214 6215 return status; 6216 } 6217 6218 /** 6219 * i40e_read_phy_register 6220 * @hw: pointer to the HW structure 6221 * @page: registers page number 6222 * @reg: register address in the page 6223 * @phy_adr: PHY address on MDIO interface 6224 * @value: PHY register value 6225 * 6226 * Reads specified PHY register value 6227 **/ 6228 enum i40e_status_code i40e_read_phy_register(struct i40e_hw *hw, 6229 u8 page, u16 reg, u8 phy_addr, u16 *value) 6230 { 6231 enum i40e_status_code status; 6232 6233 switch (hw->device_id) { 6234 case I40E_DEV_ID_1G_BASE_T_X722: 6235 status = i40e_read_phy_register_clause22(hw, reg, phy_addr, 6236 value); 6237 break; 6238 case I40E_DEV_ID_10G_BASE_T: 6239 case I40E_DEV_ID_10G_BASE_T4: 6240 case I40E_DEV_ID_10G_BASE_T_X722: 6241 case I40E_DEV_ID_25G_B: 6242 case I40E_DEV_ID_25G_SFP28: 6243 status = i40e_read_phy_register_clause45(hw, page, reg, 6244 phy_addr, value); 6245 break; 6246 default: 6247 status = I40E_ERR_UNKNOWN_PHY; 6248 break; 6249 } 6250 6251 return status; 6252 } 6253 6254 /** 6255 * i40e_get_phy_address 6256 * @hw: pointer to the HW structure 6257 * @dev_num: PHY port num that address we want 6258 * @phy_addr: Returned PHY address 6259 * 6260 * Gets PHY address for current port 6261 **/ 6262 u8 i40e_get_phy_address(struct i40e_hw *hw, u8 dev_num) 6263 { 6264 u8 port_num = (u8)hw->func_caps.mdio_port_num; 6265 u32 reg_val = rd32(hw, I40E_GLGEN_MDIO_I2C_SEL(port_num)); 6266 6267 return (u8)(reg_val >> ((dev_num + 1) * 5)) & 0x1f; 6268 } 6269 6270 /** 6271 * i40e_blink_phy_led 6272 * @hw: pointer to the HW structure 6273 * @time: time how long led will blinks in secs 6274 * @interval: gap between LED on and off in msecs 6275 * 6276 * Blinks PHY link LED 6277 **/ 6278 enum i40e_status_code i40e_blink_phy_link_led(struct i40e_hw *hw, 6279 u32 time, u32 interval) 6280 { 6281 enum i40e_status_code status = I40E_SUCCESS; 6282 u32 i; 6283 u16 led_ctl = 0; 6284 u16 gpio_led_port; 6285 u16 led_reg; 6286 u16 led_addr = I40E_PHY_LED_PROV_REG_1; 6287 u8 phy_addr = 0; 6288 u8 port_num; 6289 6290 i = rd32(hw, I40E_PFGEN_PORTNUM); 6291 port_num = (u8)(i & I40E_PFGEN_PORTNUM_PORT_NUM_MASK); 6292 phy_addr = i40e_get_phy_address(hw, port_num); 6293 6294 for (gpio_led_port = 0; gpio_led_port < 3; gpio_led_port++, 6295 led_addr++) { 6296 status = i40e_read_phy_register_clause45(hw, 6297 I40E_PHY_COM_REG_PAGE, 6298 led_addr, phy_addr, 6299 &led_reg); 6300 if (status) 6301 goto phy_blinking_end; 6302 led_ctl = led_reg; 6303 if (led_reg & I40E_PHY_LED_LINK_MODE_MASK) { 6304 led_reg = 0; 6305 status = i40e_write_phy_register_clause45(hw, 6306 I40E_PHY_COM_REG_PAGE, 6307 led_addr, phy_addr, 6308 led_reg); 6309 if (status) 6310 goto phy_blinking_end; 6311 break; 6312 } 6313 } 6314 6315 if (time > 0 && interval > 0) { 6316 for (i = 0; i < time * 1000; i += interval) { 6317 status = i40e_read_phy_register_clause45(hw, 6318 I40E_PHY_COM_REG_PAGE, 6319 led_addr, phy_addr, &led_reg); 6320 if (status) 6321 goto restore_config; 6322 if (led_reg & I40E_PHY_LED_MANUAL_ON) 6323 led_reg = 0; 6324 else 6325 led_reg = I40E_PHY_LED_MANUAL_ON; 6326 status = i40e_write_phy_register_clause45(hw, 6327 I40E_PHY_COM_REG_PAGE, 6328 led_addr, phy_addr, led_reg); 6329 if (status) 6330 goto restore_config; 6331 i40e_msec_delay(interval); 6332 } 6333 } 6334 6335 restore_config: 6336 status = i40e_write_phy_register_clause45(hw, 6337 I40E_PHY_COM_REG_PAGE, 6338 led_addr, phy_addr, led_ctl); 6339 6340 phy_blinking_end: 6341 return status; 6342 } 6343 6344 /** 6345 * i40e_led_get_phy - return current on/off mode 6346 * @hw: pointer to the hw struct 6347 * @led_addr: address of led register to use 6348 * @val: original value of register to use 6349 * 6350 **/ 6351 enum i40e_status_code i40e_led_get_phy(struct i40e_hw *hw, u16 *led_addr, 6352 u16 *val) 6353 { 6354 enum i40e_status_code status = I40E_SUCCESS; 6355 u16 gpio_led_port; 6356 u8 phy_addr = 0; 6357 u16 reg_val; 6358 u16 temp_addr; 6359 u8 port_num; 6360 u32 i; 6361 6362 temp_addr = I40E_PHY_LED_PROV_REG_1; 6363 i = rd32(hw, I40E_PFGEN_PORTNUM); 6364 port_num = (u8)(i & I40E_PFGEN_PORTNUM_PORT_NUM_MASK); 6365 phy_addr = i40e_get_phy_address(hw, port_num); 6366 6367 for (gpio_led_port = 0; gpio_led_port < 3; gpio_led_port++, 6368 temp_addr++) { 6369 status = i40e_read_phy_register_clause45(hw, 6370 I40E_PHY_COM_REG_PAGE, 6371 temp_addr, phy_addr, 6372 ®_val); 6373 if (status) 6374 return status; 6375 *val = reg_val; 6376 if (reg_val & I40E_PHY_LED_LINK_MODE_MASK) { 6377 *led_addr = temp_addr; 6378 break; 6379 } 6380 } 6381 return status; 6382 } 6383 6384 /** 6385 * i40e_led_set_phy 6386 * @hw: pointer to the HW structure 6387 * @on: TRUE or FALSE 6388 * @mode: original val plus bit for set or ignore 6389 * Set led's on or off when controlled by the PHY 6390 * 6391 **/ 6392 enum i40e_status_code i40e_led_set_phy(struct i40e_hw *hw, bool on, 6393 u16 led_addr, u32 mode) 6394 { 6395 enum i40e_status_code status = I40E_SUCCESS; 6396 u16 led_ctl = 0; 6397 u16 led_reg = 0; 6398 u8 phy_addr = 0; 6399 u8 port_num; 6400 u32 i; 6401 6402 i = rd32(hw, I40E_PFGEN_PORTNUM); 6403 port_num = (u8)(i & I40E_PFGEN_PORTNUM_PORT_NUM_MASK); 6404 phy_addr = i40e_get_phy_address(hw, port_num); 6405 status = i40e_read_phy_register_clause45(hw, I40E_PHY_COM_REG_PAGE, 6406 led_addr, phy_addr, &led_reg); 6407 if (status) 6408 return status; 6409 led_ctl = led_reg; 6410 if (led_reg & I40E_PHY_LED_LINK_MODE_MASK) { 6411 led_reg = 0; 6412 status = i40e_write_phy_register_clause45(hw, 6413 I40E_PHY_COM_REG_PAGE, 6414 led_addr, phy_addr, 6415 led_reg); 6416 if (status) 6417 return status; 6418 } 6419 status = i40e_read_phy_register_clause45(hw, I40E_PHY_COM_REG_PAGE, 6420 led_addr, phy_addr, &led_reg); 6421 if (status) 6422 goto restore_config; 6423 if (on) 6424 led_reg = I40E_PHY_LED_MANUAL_ON; 6425 else 6426 led_reg = 0; 6427 status = i40e_write_phy_register_clause45(hw, I40E_PHY_COM_REG_PAGE, 6428 led_addr, phy_addr, led_reg); 6429 if (status) 6430 goto restore_config; 6431 if (mode & I40E_PHY_LED_MODE_ORIG) { 6432 led_ctl = (mode & I40E_PHY_LED_MODE_MASK); 6433 status = i40e_write_phy_register_clause45(hw, 6434 I40E_PHY_COM_REG_PAGE, 6435 led_addr, phy_addr, led_ctl); 6436 } 6437 return status; 6438 restore_config: 6439 status = i40e_write_phy_register_clause45(hw, I40E_PHY_COM_REG_PAGE, 6440 led_addr, phy_addr, led_ctl); 6441 return status; 6442 } 6443 6444 /** 6445 * i40e_aq_rx_ctl_read_register - use FW to read from an Rx control register 6446 * @hw: pointer to the hw struct 6447 * @reg_addr: register address 6448 * @reg_val: ptr to register value 6449 * @cmd_details: pointer to command details structure or NULL 6450 * 6451 * Use the firmware to read the Rx control register, 6452 * especially useful if the Rx unit is under heavy pressure 6453 **/ 6454 enum i40e_status_code i40e_aq_rx_ctl_read_register(struct i40e_hw *hw, 6455 u32 reg_addr, u32 *reg_val, 6456 struct i40e_asq_cmd_details *cmd_details) 6457 { 6458 struct i40e_aq_desc desc; 6459 struct i40e_aqc_rx_ctl_reg_read_write *cmd_resp = 6460 (struct i40e_aqc_rx_ctl_reg_read_write *)&desc.params.raw; 6461 enum i40e_status_code status; 6462 6463 if (reg_val == NULL) 6464 return I40E_ERR_PARAM; 6465 6466 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_rx_ctl_reg_read); 6467 6468 cmd_resp->address = CPU_TO_LE32(reg_addr); 6469 6470 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 6471 6472 if (status == I40E_SUCCESS) 6473 *reg_val = LE32_TO_CPU(cmd_resp->value); 6474 6475 return status; 6476 } 6477 6478 /** 6479 * i40e_read_rx_ctl - read from an Rx control register 6480 * @hw: pointer to the hw struct 6481 * @reg_addr: register address 6482 **/ 6483 u32 i40e_read_rx_ctl(struct i40e_hw *hw, u32 reg_addr) 6484 { 6485 enum i40e_status_code status = I40E_SUCCESS; 6486 bool use_register; 6487 int retry = 5; 6488 u32 val = 0; 6489 6490 use_register = (hw->aq.api_maj_ver == 1) && (hw->aq.api_min_ver < 5); 6491 if (!use_register) { 6492 do_retry: 6493 status = i40e_aq_rx_ctl_read_register(hw, reg_addr, &val, NULL); 6494 if (hw->aq.asq_last_status == I40E_AQ_RC_EAGAIN && retry) { 6495 i40e_msec_delay(1); 6496 retry--; 6497 goto do_retry; 6498 } 6499 } 6500 6501 /* if the AQ access failed, try the old-fashioned way */ 6502 if (status || use_register) 6503 val = rd32(hw, reg_addr); 6504 6505 return val; 6506 } 6507 6508 /** 6509 * i40e_aq_rx_ctl_write_register 6510 * @hw: pointer to the hw struct 6511 * @reg_addr: register address 6512 * @reg_val: register value 6513 * @cmd_details: pointer to command details structure or NULL 6514 * 6515 * Use the firmware to write to an Rx control register, 6516 * especially useful if the Rx unit is under heavy pressure 6517 **/ 6518 enum i40e_status_code i40e_aq_rx_ctl_write_register(struct i40e_hw *hw, 6519 u32 reg_addr, u32 reg_val, 6520 struct i40e_asq_cmd_details *cmd_details) 6521 { 6522 struct i40e_aq_desc desc; 6523 struct i40e_aqc_rx_ctl_reg_read_write *cmd = 6524 (struct i40e_aqc_rx_ctl_reg_read_write *)&desc.params.raw; 6525 enum i40e_status_code status; 6526 6527 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_rx_ctl_reg_write); 6528 6529 cmd->address = CPU_TO_LE32(reg_addr); 6530 cmd->value = CPU_TO_LE32(reg_val); 6531 6532 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 6533 6534 return status; 6535 } 6536 6537 /** 6538 * i40e_write_rx_ctl - write to an Rx control register 6539 * @hw: pointer to the hw struct 6540 * @reg_addr: register address 6541 * @reg_val: register value 6542 **/ 6543 void i40e_write_rx_ctl(struct i40e_hw *hw, u32 reg_addr, u32 reg_val) 6544 { 6545 enum i40e_status_code status = I40E_SUCCESS; 6546 bool use_register; 6547 int retry = 5; 6548 6549 use_register = (hw->aq.api_maj_ver == 1) && (hw->aq.api_min_ver < 5); 6550 if (!use_register) { 6551 do_retry: 6552 status = i40e_aq_rx_ctl_write_register(hw, reg_addr, 6553 reg_val, NULL); 6554 if (hw->aq.asq_last_status == I40E_AQ_RC_EAGAIN && retry) { 6555 i40e_msec_delay(1); 6556 retry--; 6557 goto do_retry; 6558 } 6559 } 6560 6561 /* if the AQ access failed, try the old-fashioned way */ 6562 if (status || use_register) 6563 wr32(hw, reg_addr, reg_val); 6564 } 6565 6566 6567 /** 6568 * i40e_aq_set_phy_register 6569 * @hw: pointer to the hw struct 6570 * @phy_select: select which phy should be accessed 6571 * @dev_addr: PHY device address 6572 * @reg_addr: PHY register address 6573 * @reg_val: new register value 6574 * @cmd_details: pointer to command details structure or NULL 6575 * 6576 * Write the external PHY register. 6577 **/ 6578 enum i40e_status_code i40e_aq_set_phy_register(struct i40e_hw *hw, 6579 u8 phy_select, u8 dev_addr, 6580 u32 reg_addr, u32 reg_val, 6581 struct i40e_asq_cmd_details *cmd_details) 6582 { 6583 struct i40e_aq_desc desc; 6584 struct i40e_aqc_phy_register_access *cmd = 6585 (struct i40e_aqc_phy_register_access *)&desc.params.raw; 6586 enum i40e_status_code status; 6587 6588 i40e_fill_default_direct_cmd_desc(&desc, 6589 i40e_aqc_opc_set_phy_register); 6590 6591 cmd->phy_interface = phy_select; 6592 cmd->dev_addres = dev_addr; 6593 cmd->reg_address = reg_addr; 6594 cmd->reg_value = reg_val; 6595 6596 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 6597 6598 return status; 6599 } 6600 6601 /** 6602 * i40e_aq_get_phy_register 6603 * @hw: pointer to the hw struct 6604 * @phy_select: select which phy should be accessed 6605 * @dev_addr: PHY device address 6606 * @reg_addr: PHY register address 6607 * @reg_val: read register value 6608 * @cmd_details: pointer to command details structure or NULL 6609 * 6610 * Read the external PHY register. 6611 **/ 6612 enum i40e_status_code i40e_aq_get_phy_register(struct i40e_hw *hw, 6613 u8 phy_select, u8 dev_addr, 6614 u32 reg_addr, u32 *reg_val, 6615 struct i40e_asq_cmd_details *cmd_details) 6616 { 6617 struct i40e_aq_desc desc; 6618 struct i40e_aqc_phy_register_access *cmd = 6619 (struct i40e_aqc_phy_register_access *)&desc.params.raw; 6620 enum i40e_status_code status; 6621 6622 i40e_fill_default_direct_cmd_desc(&desc, 6623 i40e_aqc_opc_get_phy_register); 6624 6625 cmd->phy_interface = phy_select; 6626 cmd->dev_addres = dev_addr; 6627 cmd->reg_address = reg_addr; 6628 6629 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 6630 if (!status) 6631 *reg_val = cmd->reg_value; 6632 6633 return status; 6634 } 6635 6636 /** 6637 * i40e_aq_set_arp_proxy_config 6638 * @hw: pointer to the HW structure 6639 * @proxy_config - pointer to proxy config command table struct 6640 * @cmd_details: pointer to command details 6641 * 6642 * Set ARP offload parameters from pre-populated 6643 * i40e_aqc_arp_proxy_data struct 6644 **/ 6645 enum i40e_status_code i40e_aq_set_arp_proxy_config(struct i40e_hw *hw, 6646 struct i40e_aqc_arp_proxy_data *proxy_config, 6647 struct i40e_asq_cmd_details *cmd_details) 6648 { 6649 struct i40e_aq_desc desc; 6650 enum i40e_status_code status; 6651 6652 if (!proxy_config) 6653 return I40E_ERR_PARAM; 6654 6655 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_set_proxy_config); 6656 6657 desc.params.external.addr_high = 6658 CPU_TO_LE32(I40E_HI_DWORD((uintptr_t)proxy_config)); 6659 desc.params.external.addr_low = 6660 CPU_TO_LE32(I40E_LO_DWORD((uintptr_t)proxy_config)); 6661 6662 status = i40e_asq_send_command(hw, &desc, proxy_config, 6663 sizeof(struct i40e_aqc_arp_proxy_data), 6664 cmd_details); 6665 6666 return status; 6667 } 6668 6669 /** 6670 * i40e_aq_opc_set_ns_proxy_table_entry 6671 * @hw: pointer to the HW structure 6672 * @ns_proxy_table_entry: pointer to NS table entry command struct 6673 * @cmd_details: pointer to command details 6674 * 6675 * Set IPv6 Neighbor Solicitation (NS) protocol offload parameters 6676 * from pre-populated i40e_aqc_ns_proxy_data struct 6677 **/ 6678 enum i40e_status_code i40e_aq_set_ns_proxy_table_entry(struct i40e_hw *hw, 6679 struct i40e_aqc_ns_proxy_data *ns_proxy_table_entry, 6680 struct i40e_asq_cmd_details *cmd_details) 6681 { 6682 struct i40e_aq_desc desc; 6683 enum i40e_status_code status; 6684 6685 if (!ns_proxy_table_entry) 6686 return I40E_ERR_PARAM; 6687 6688 i40e_fill_default_direct_cmd_desc(&desc, 6689 i40e_aqc_opc_set_ns_proxy_table_entry); 6690 6691 desc.params.external.addr_high = 6692 CPU_TO_LE32(I40E_HI_DWORD((uintptr_t)ns_proxy_table_entry)); 6693 desc.params.external.addr_low = 6694 CPU_TO_LE32(I40E_LO_DWORD((uintptr_t)ns_proxy_table_entry)); 6695 6696 status = i40e_asq_send_command(hw, &desc, ns_proxy_table_entry, 6697 sizeof(struct i40e_aqc_ns_proxy_data), 6698 cmd_details); 6699 6700 return status; 6701 } 6702 6703 /** 6704 * i40e_aq_set_clear_wol_filter 6705 * @hw: pointer to the hw struct 6706 * @filter_index: index of filter to modify (0-7) 6707 * @filter: buffer containing filter to be set 6708 * @set_filter: TRUE to set filter, FALSE to clear filter 6709 * @no_wol_tco: if TRUE, pass through packets cannot cause wake-up 6710 * if FALSE, pass through packets may cause wake-up 6711 * @filter_valid: TRUE if filter action is valid 6712 * @no_wol_tco_valid: TRUE if no WoL in TCO traffic action valid 6713 * @cmd_details: pointer to command details structure or NULL 6714 * 6715 * Set or clear WoL filter for port attached to the PF 6716 **/ 6717 enum i40e_status_code i40e_aq_set_clear_wol_filter(struct i40e_hw *hw, 6718 u8 filter_index, 6719 struct i40e_aqc_set_wol_filter_data *filter, 6720 bool set_filter, bool no_wol_tco, 6721 bool filter_valid, bool no_wol_tco_valid, 6722 struct i40e_asq_cmd_details *cmd_details) 6723 { 6724 struct i40e_aq_desc desc; 6725 struct i40e_aqc_set_wol_filter *cmd = 6726 (struct i40e_aqc_set_wol_filter *)&desc.params.raw; 6727 enum i40e_status_code status; 6728 u16 cmd_flags = 0; 6729 u16 valid_flags = 0; 6730 u16 buff_len = 0; 6731 6732 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_set_wol_filter); 6733 6734 if (filter_index >= I40E_AQC_MAX_NUM_WOL_FILTERS) 6735 return I40E_ERR_PARAM; 6736 cmd->filter_index = CPU_TO_LE16(filter_index); 6737 6738 if (set_filter) { 6739 if (!filter) 6740 return I40E_ERR_PARAM; 6741 cmd_flags |= I40E_AQC_SET_WOL_FILTER; 6742 buff_len = sizeof(*filter); 6743 } 6744 if (no_wol_tco) 6745 cmd_flags |= I40E_AQC_SET_WOL_FILTER_NO_TCO_WOL; 6746 cmd->cmd_flags = CPU_TO_LE16(cmd_flags); 6747 6748 if (filter_valid) 6749 valid_flags |= I40E_AQC_SET_WOL_FILTER_ACTION_VALID; 6750 if (no_wol_tco_valid) 6751 valid_flags |= I40E_AQC_SET_WOL_FILTER_NO_TCO_ACTION_VALID; 6752 cmd->valid_flags = CPU_TO_LE16(valid_flags); 6753 6754 cmd->address_high = CPU_TO_LE32(I40E_HI_DWORD((uintptr_t)filter)); 6755 cmd->address_low = CPU_TO_LE32(I40E_LO_DWORD((uintptr_t)filter)); 6756 6757 status = i40e_asq_send_command(hw, &desc, filter, 6758 buff_len, cmd_details); 6759 6760 return status; 6761 } 6762 6763 /** 6764 * i40e_aq_get_wake_event_reason 6765 * @hw: pointer to the hw struct 6766 * @wake_reason: return value, index of matching filter 6767 * @cmd_details: pointer to command details structure or NULL 6768 * 6769 * Get information for the reason of a Wake Up event 6770 **/ 6771 enum i40e_status_code i40e_aq_get_wake_event_reason(struct i40e_hw *hw, 6772 u16 *wake_reason, 6773 struct i40e_asq_cmd_details *cmd_details) 6774 { 6775 struct i40e_aq_desc desc; 6776 struct i40e_aqc_get_wake_reason_completion *resp = 6777 (struct i40e_aqc_get_wake_reason_completion *)&desc.params.raw; 6778 enum i40e_status_code status; 6779 6780 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_get_wake_reason); 6781 6782 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 6783 6784 if (status == I40E_SUCCESS) 6785 *wake_reason = LE16_TO_CPU(resp->wake_reason); 6786 6787 return status; 6788 } 6789 6790