19d26e4fcSRobert Mustacchi /****************************************************************************** 29d26e4fcSRobert Mustacchi 3*df36e06dSRobert Mustacchi Copyright (c) 2013-2018, Intel Corporation 49d26e4fcSRobert Mustacchi All rights reserved. 59d26e4fcSRobert Mustacchi 69d26e4fcSRobert Mustacchi Redistribution and use in source and binary forms, with or without 79d26e4fcSRobert Mustacchi modification, are permitted provided that the following conditions are met: 89d26e4fcSRobert Mustacchi 99d26e4fcSRobert Mustacchi 1. Redistributions of source code must retain the above copyright notice, 109d26e4fcSRobert Mustacchi this list of conditions and the following disclaimer. 119d26e4fcSRobert Mustacchi 129d26e4fcSRobert Mustacchi 2. Redistributions in binary form must reproduce the above copyright 139d26e4fcSRobert Mustacchi notice, this list of conditions and the following disclaimer in the 149d26e4fcSRobert Mustacchi documentation and/or other materials provided with the distribution. 159d26e4fcSRobert Mustacchi 169d26e4fcSRobert Mustacchi 3. Neither the name of the Intel Corporation nor the names of its 179d26e4fcSRobert Mustacchi contributors may be used to endorse or promote products derived from 189d26e4fcSRobert Mustacchi this software without specific prior written permission. 199d26e4fcSRobert Mustacchi 209d26e4fcSRobert Mustacchi THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 219d26e4fcSRobert Mustacchi AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 229d26e4fcSRobert Mustacchi IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 239d26e4fcSRobert Mustacchi ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 249d26e4fcSRobert Mustacchi LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 259d26e4fcSRobert Mustacchi CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 269d26e4fcSRobert Mustacchi SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 279d26e4fcSRobert Mustacchi INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 289d26e4fcSRobert Mustacchi CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 299d26e4fcSRobert Mustacchi ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 309d26e4fcSRobert Mustacchi POSSIBILITY OF SUCH DAMAGE. 319d26e4fcSRobert Mustacchi 329d26e4fcSRobert Mustacchi ******************************************************************************/ 333d75a287SRobert Mustacchi /*$FreeBSD$*/ 349d26e4fcSRobert Mustacchi 359d26e4fcSRobert Mustacchi #ifndef _I40E_LAN_HMC_H_ 369d26e4fcSRobert Mustacchi #define _I40E_LAN_HMC_H_ 379d26e4fcSRobert Mustacchi 389d26e4fcSRobert Mustacchi /* forward-declare the HW struct for the compiler */ 399d26e4fcSRobert Mustacchi struct i40e_hw; 409d26e4fcSRobert Mustacchi 419d26e4fcSRobert Mustacchi /* HMC element context information */ 429d26e4fcSRobert Mustacchi 439d26e4fcSRobert Mustacchi /* Rx queue context data 449d26e4fcSRobert Mustacchi * 459d26e4fcSRobert Mustacchi * The sizes of the variables may be larger than needed due to crossing byte 469d26e4fcSRobert Mustacchi * boundaries. If we do not have the width of the variable set to the correct 479d26e4fcSRobert Mustacchi * size then we could end up shifting bits off the top of the variable when the 489d26e4fcSRobert Mustacchi * variable is at the top of a byte and crosses over into the next byte. 499d26e4fcSRobert Mustacchi */ 509d26e4fcSRobert Mustacchi struct i40e_hmc_obj_rxq { 519d26e4fcSRobert Mustacchi u16 head; 529d26e4fcSRobert Mustacchi u16 cpuid; /* bigger than needed, see above for reason */ 539d26e4fcSRobert Mustacchi u64 base; 549d26e4fcSRobert Mustacchi u16 qlen; 559d26e4fcSRobert Mustacchi #define I40E_RXQ_CTX_DBUFF_SHIFT 7 569d26e4fcSRobert Mustacchi u16 dbuff; /* bigger than needed, see above for reason */ 579d26e4fcSRobert Mustacchi #define I40E_RXQ_CTX_HBUFF_SHIFT 6 589d26e4fcSRobert Mustacchi u16 hbuff; /* bigger than needed, see above for reason */ 599d26e4fcSRobert Mustacchi u8 dtype; 609d26e4fcSRobert Mustacchi u8 dsize; 619d26e4fcSRobert Mustacchi u8 crcstrip; 629d26e4fcSRobert Mustacchi u8 fc_ena; 639d26e4fcSRobert Mustacchi u8 l2tsel; 649d26e4fcSRobert Mustacchi u8 hsplit_0; 659d26e4fcSRobert Mustacchi u8 hsplit_1; 669d26e4fcSRobert Mustacchi u8 showiv; 679d26e4fcSRobert Mustacchi u32 rxmax; /* bigger than needed, see above for reason */ 689d26e4fcSRobert Mustacchi u8 tphrdesc_ena; 699d26e4fcSRobert Mustacchi u8 tphwdesc_ena; 709d26e4fcSRobert Mustacchi u8 tphdata_ena; 719d26e4fcSRobert Mustacchi u8 tphhead_ena; 729d26e4fcSRobert Mustacchi u16 lrxqthresh; /* bigger than needed, see above for reason */ 739d26e4fcSRobert Mustacchi u8 prefena; /* NOTE: normally must be set to 1 at init */ 749d26e4fcSRobert Mustacchi }; 759d26e4fcSRobert Mustacchi 769d26e4fcSRobert Mustacchi /* Tx queue context data 779d26e4fcSRobert Mustacchi * 789d26e4fcSRobert Mustacchi * The sizes of the variables may be larger than needed due to crossing byte 799d26e4fcSRobert Mustacchi * boundaries. If we do not have the width of the variable set to the correct 809d26e4fcSRobert Mustacchi * size then we could end up shifting bits off the top of the variable when the 819d26e4fcSRobert Mustacchi * variable is at the top of a byte and crosses over into the next byte. 829d26e4fcSRobert Mustacchi */ 839d26e4fcSRobert Mustacchi struct i40e_hmc_obj_txq { 849d26e4fcSRobert Mustacchi u16 head; 859d26e4fcSRobert Mustacchi u8 new_context; 869d26e4fcSRobert Mustacchi u64 base; 879d26e4fcSRobert Mustacchi u8 fc_ena; 889d26e4fcSRobert Mustacchi u8 timesync_ena; 899d26e4fcSRobert Mustacchi u8 fd_ena; 909d26e4fcSRobert Mustacchi u8 alt_vlan_ena; 919d26e4fcSRobert Mustacchi u16 thead_wb; 929d26e4fcSRobert Mustacchi u8 cpuid; 939d26e4fcSRobert Mustacchi u8 head_wb_ena; 949d26e4fcSRobert Mustacchi u16 qlen; 959d26e4fcSRobert Mustacchi u8 tphrdesc_ena; 969d26e4fcSRobert Mustacchi u8 tphrpacket_ena; 979d26e4fcSRobert Mustacchi u8 tphwdesc_ena; 989d26e4fcSRobert Mustacchi u64 head_wb_addr; 999d26e4fcSRobert Mustacchi u32 crc; 1009d26e4fcSRobert Mustacchi u16 rdylist; 1019d26e4fcSRobert Mustacchi u8 rdylist_act; 1029d26e4fcSRobert Mustacchi }; 1039d26e4fcSRobert Mustacchi 1049d26e4fcSRobert Mustacchi /* for hsplit_0 field of Rx HMC context */ 1059d26e4fcSRobert Mustacchi enum i40e_hmc_obj_rx_hsplit_0 { 1069d26e4fcSRobert Mustacchi I40E_HMC_OBJ_RX_HSPLIT_0_NO_SPLIT = 0, 1079d26e4fcSRobert Mustacchi I40E_HMC_OBJ_RX_HSPLIT_0_SPLIT_L2 = 1, 1089d26e4fcSRobert Mustacchi I40E_HMC_OBJ_RX_HSPLIT_0_SPLIT_IP = 2, 1099d26e4fcSRobert Mustacchi I40E_HMC_OBJ_RX_HSPLIT_0_SPLIT_TCP_UDP = 4, 1109d26e4fcSRobert Mustacchi I40E_HMC_OBJ_RX_HSPLIT_0_SPLIT_SCTP = 8, 1119d26e4fcSRobert Mustacchi }; 1129d26e4fcSRobert Mustacchi 1139d26e4fcSRobert Mustacchi /* fcoe_cntx and fcoe_filt are for debugging purpose only */ 1149d26e4fcSRobert Mustacchi struct i40e_hmc_obj_fcoe_cntx { 1159d26e4fcSRobert Mustacchi u32 rsv[32]; 1169d26e4fcSRobert Mustacchi }; 1179d26e4fcSRobert Mustacchi 1189d26e4fcSRobert Mustacchi struct i40e_hmc_obj_fcoe_filt { 1199d26e4fcSRobert Mustacchi u32 rsv[8]; 1209d26e4fcSRobert Mustacchi }; 1219d26e4fcSRobert Mustacchi 1229d26e4fcSRobert Mustacchi /* Context sizes for LAN objects */ 1239d26e4fcSRobert Mustacchi enum i40e_hmc_lan_object_size { 1249d26e4fcSRobert Mustacchi I40E_HMC_LAN_OBJ_SZ_8 = 0x3, 1259d26e4fcSRobert Mustacchi I40E_HMC_LAN_OBJ_SZ_16 = 0x4, 1269d26e4fcSRobert Mustacchi I40E_HMC_LAN_OBJ_SZ_32 = 0x5, 1279d26e4fcSRobert Mustacchi I40E_HMC_LAN_OBJ_SZ_64 = 0x6, 1289d26e4fcSRobert Mustacchi I40E_HMC_LAN_OBJ_SZ_128 = 0x7, 1299d26e4fcSRobert Mustacchi I40E_HMC_LAN_OBJ_SZ_256 = 0x8, 1309d26e4fcSRobert Mustacchi I40E_HMC_LAN_OBJ_SZ_512 = 0x9, 1319d26e4fcSRobert Mustacchi }; 1329d26e4fcSRobert Mustacchi 1339d26e4fcSRobert Mustacchi #define I40E_HMC_L2OBJ_BASE_ALIGNMENT 512 1349d26e4fcSRobert Mustacchi #define I40E_HMC_OBJ_SIZE_TXQ 128 1359d26e4fcSRobert Mustacchi #define I40E_HMC_OBJ_SIZE_RXQ 32 1369d26e4fcSRobert Mustacchi #define I40E_HMC_OBJ_SIZE_FCOE_CNTX 64 1379d26e4fcSRobert Mustacchi #define I40E_HMC_OBJ_SIZE_FCOE_FILT 64 1389d26e4fcSRobert Mustacchi 1399d26e4fcSRobert Mustacchi enum i40e_hmc_lan_rsrc_type { 1409d26e4fcSRobert Mustacchi I40E_HMC_LAN_FULL = 0, 1419d26e4fcSRobert Mustacchi I40E_HMC_LAN_TX = 1, 1429d26e4fcSRobert Mustacchi I40E_HMC_LAN_RX = 2, 1439d26e4fcSRobert Mustacchi I40E_HMC_FCOE_CTX = 3, 1449d26e4fcSRobert Mustacchi I40E_HMC_FCOE_FILT = 4, 1459d26e4fcSRobert Mustacchi I40E_HMC_LAN_MAX = 5 1469d26e4fcSRobert Mustacchi }; 1479d26e4fcSRobert Mustacchi 1489d26e4fcSRobert Mustacchi enum i40e_hmc_model { 1499d26e4fcSRobert Mustacchi I40E_HMC_MODEL_DIRECT_PREFERRED = 0, 1509d26e4fcSRobert Mustacchi I40E_HMC_MODEL_DIRECT_ONLY = 1, 1519d26e4fcSRobert Mustacchi I40E_HMC_MODEL_PAGED_ONLY = 2, 1529d26e4fcSRobert Mustacchi I40E_HMC_MODEL_UNKNOWN, 1539d26e4fcSRobert Mustacchi }; 1549d26e4fcSRobert Mustacchi 1559d26e4fcSRobert Mustacchi struct i40e_hmc_lan_create_obj_info { 1569d26e4fcSRobert Mustacchi struct i40e_hmc_info *hmc_info; 1579d26e4fcSRobert Mustacchi u32 rsrc_type; 1589d26e4fcSRobert Mustacchi u32 start_idx; 1599d26e4fcSRobert Mustacchi u32 count; 1609d26e4fcSRobert Mustacchi enum i40e_sd_entry_type entry_type; 1619d26e4fcSRobert Mustacchi u64 direct_mode_sz; 1629d26e4fcSRobert Mustacchi }; 1639d26e4fcSRobert Mustacchi 1649d26e4fcSRobert Mustacchi struct i40e_hmc_lan_delete_obj_info { 1659d26e4fcSRobert Mustacchi struct i40e_hmc_info *hmc_info; 1669d26e4fcSRobert Mustacchi u32 rsrc_type; 1679d26e4fcSRobert Mustacchi u32 start_idx; 1689d26e4fcSRobert Mustacchi u32 count; 1699d26e4fcSRobert Mustacchi }; 1709d26e4fcSRobert Mustacchi 1719d26e4fcSRobert Mustacchi enum i40e_status_code i40e_init_lan_hmc(struct i40e_hw *hw, u32 txq_num, 1729d26e4fcSRobert Mustacchi u32 rxq_num, u32 fcoe_cntx_num, 1739d26e4fcSRobert Mustacchi u32 fcoe_filt_num); 1749d26e4fcSRobert Mustacchi enum i40e_status_code i40e_configure_lan_hmc(struct i40e_hw *hw, 1759d26e4fcSRobert Mustacchi enum i40e_hmc_model model); 1769d26e4fcSRobert Mustacchi enum i40e_status_code i40e_shutdown_lan_hmc(struct i40e_hw *hw); 1779d26e4fcSRobert Mustacchi 1789d26e4fcSRobert Mustacchi u64 i40e_calculate_l2fpm_size(u32 txq_num, u32 rxq_num, 1799d26e4fcSRobert Mustacchi u32 fcoe_cntx_num, u32 fcoe_filt_num); 1809d26e4fcSRobert Mustacchi enum i40e_status_code i40e_get_lan_tx_queue_context(struct i40e_hw *hw, 1819d26e4fcSRobert Mustacchi u16 queue, 1829d26e4fcSRobert Mustacchi struct i40e_hmc_obj_txq *s); 1839d26e4fcSRobert Mustacchi enum i40e_status_code i40e_clear_lan_tx_queue_context(struct i40e_hw *hw, 1849d26e4fcSRobert Mustacchi u16 queue); 1859d26e4fcSRobert Mustacchi enum i40e_status_code i40e_set_lan_tx_queue_context(struct i40e_hw *hw, 1869d26e4fcSRobert Mustacchi u16 queue, 1879d26e4fcSRobert Mustacchi struct i40e_hmc_obj_txq *s); 1889d26e4fcSRobert Mustacchi enum i40e_status_code i40e_get_lan_rx_queue_context(struct i40e_hw *hw, 1899d26e4fcSRobert Mustacchi u16 queue, 1909d26e4fcSRobert Mustacchi struct i40e_hmc_obj_rxq *s); 1919d26e4fcSRobert Mustacchi enum i40e_status_code i40e_clear_lan_rx_queue_context(struct i40e_hw *hw, 1929d26e4fcSRobert Mustacchi u16 queue); 1939d26e4fcSRobert Mustacchi enum i40e_status_code i40e_set_lan_rx_queue_context(struct i40e_hw *hw, 1949d26e4fcSRobert Mustacchi u16 queue, 1959d26e4fcSRobert Mustacchi struct i40e_hmc_obj_rxq *s); 1969d26e4fcSRobert Mustacchi enum i40e_status_code i40e_create_lan_hmc_object(struct i40e_hw *hw, 1979d26e4fcSRobert Mustacchi struct i40e_hmc_lan_create_obj_info *info); 1989d26e4fcSRobert Mustacchi enum i40e_status_code i40e_delete_lan_hmc_object(struct i40e_hw *hw, 1999d26e4fcSRobert Mustacchi struct i40e_hmc_lan_delete_obj_info *info); 2009d26e4fcSRobert Mustacchi 2019d26e4fcSRobert Mustacchi #endif /* _I40E_LAN_HMC_H_ */ 202