1 /* 2 * CDDL HEADER START 3 * 4 * Copyright(c) 2007-2008 Intel Corporation. All rights reserved. 5 * The contents of this file are subject to the terms of the 6 * Common Development and Distribution License (the "License"). 7 * You may not use this file except in compliance with the License. 8 * 9 * You can obtain a copy of the license at: 10 * http://www.opensolaris.org/os/licensing. 11 * See the License for the specific language governing permissions 12 * and limitations under the License. 13 * 14 * When using or redistributing this file, you may do so under the 15 * License only. No other modification of this header is permitted. 16 * 17 * If applicable, add the following below this CDDL HEADER, with the 18 * fields enclosed by brackets "[]" replaced with your own identifying 19 * information: Portions Copyright [yyyy] [name of copyright owner] 20 * 21 * CDDL HEADER END 22 */ 23 24 /* 25 * Copyright 2008 Sun Microsystems, Inc. All rights reserved. 26 * Use is subject to license terms of the CDDL. 27 */ 28 29 #pragma ident "%Z%%M% %I% %E% SMI" 30 31 #include "igb_sw.h" 32 33 static char ident[] = "Intel 1Gb Ethernet 1.1.1"; 34 35 /* 36 * Local function protoypes 37 */ 38 static int igb_register_mac(igb_t *); 39 static int igb_identify_hardware(igb_t *); 40 static int igb_regs_map(igb_t *); 41 static void igb_init_properties(igb_t *); 42 static int igb_init_driver_settings(igb_t *); 43 static void igb_init_locks(igb_t *); 44 static void igb_destroy_locks(igb_t *); 45 static int igb_init(igb_t *); 46 static int igb_chip_start(igb_t *); 47 static void igb_chip_stop(igb_t *); 48 static int igb_reset(igb_t *); 49 static void igb_tx_clean(igb_t *); 50 static boolean_t igb_tx_drain(igb_t *); 51 static boolean_t igb_rx_drain(igb_t *); 52 static int igb_alloc_rings(igb_t *); 53 static int igb_init_rings(igb_t *); 54 static void igb_free_rings(igb_t *); 55 static void igb_fini_rings(igb_t *); 56 static void igb_setup_rings(igb_t *); 57 static void igb_setup_rx(igb_t *); 58 static void igb_setup_tx(igb_t *); 59 static void igb_setup_rx_ring(igb_rx_ring_t *); 60 static void igb_setup_tx_ring(igb_tx_ring_t *); 61 static void igb_setup_rss(igb_t *); 62 static void igb_init_unicst(igb_t *); 63 static void igb_setup_multicst(igb_t *); 64 static void igb_get_phy_state(igb_t *); 65 static void igb_get_conf(igb_t *); 66 static int igb_get_prop(igb_t *, char *, int, int, int); 67 static boolean_t igb_is_link_up(igb_t *); 68 static boolean_t igb_link_check(igb_t *); 69 static void igb_local_timer(void *); 70 static void igb_arm_watchdog_timer(igb_t *); 71 static void igb_start_watchdog_timer(igb_t *); 72 static void igb_restart_watchdog_timer(igb_t *); 73 static void igb_stop_watchdog_timer(igb_t *); 74 static void igb_disable_adapter_interrupts(igb_t *); 75 static void igb_enable_adapter_interrupts(igb_t *); 76 static boolean_t is_valid_mac_addr(uint8_t *); 77 static boolean_t igb_stall_check(igb_t *); 78 static boolean_t igb_set_loopback_mode(igb_t *, uint32_t); 79 static void igb_set_external_loopback(igb_t *); 80 static void igb_set_internal_mac_loopback(igb_t *); 81 static void igb_set_internal_phy_loopback(igb_t *); 82 static void igb_set_internal_serdes_loopback(igb_t *); 83 static boolean_t igb_find_mac_address(igb_t *); 84 static int igb_alloc_intrs(igb_t *); 85 static int igb_alloc_intrs_msix(igb_t *); 86 static int igb_alloc_intrs_msi(igb_t *); 87 static int igb_alloc_intrs_legacy(igb_t *); 88 static int igb_add_intr_handlers(igb_t *); 89 static void igb_rem_intr_handlers(igb_t *); 90 static void igb_rem_intrs(igb_t *); 91 static int igb_enable_intrs(igb_t *); 92 static int igb_disable_intrs(igb_t *); 93 static void igb_setup_adapter_msix(igb_t *); 94 static uint_t igb_intr_legacy(void *, void *); 95 static uint_t igb_intr_msi(void *, void *); 96 static uint_t igb_intr_rx(void *, void *); 97 static uint_t igb_intr_tx_other(void *, void *); 98 static void igb_intr_rx_work(igb_rx_ring_t *); 99 static void igb_intr_tx_work(igb_tx_ring_t *); 100 static void igb_intr_other_work(igb_t *); 101 static void igb_get_driver_control(struct e1000_hw *); 102 static void igb_release_driver_control(struct e1000_hw *); 103 104 static int igb_attach(dev_info_t *, ddi_attach_cmd_t); 105 static int igb_detach(dev_info_t *, ddi_detach_cmd_t); 106 static int igb_resume(dev_info_t *); 107 static int igb_suspend(dev_info_t *); 108 static void igb_unconfigure(dev_info_t *, igb_t *); 109 110 static struct cb_ops igb_cb_ops = { 111 nulldev, /* cb_open */ 112 nulldev, /* cb_close */ 113 nodev, /* cb_strategy */ 114 nodev, /* cb_print */ 115 nodev, /* cb_dump */ 116 nodev, /* cb_read */ 117 nodev, /* cb_write */ 118 nodev, /* cb_ioctl */ 119 nodev, /* cb_devmap */ 120 nodev, /* cb_mmap */ 121 nodev, /* cb_segmap */ 122 nochpoll, /* cb_chpoll */ 123 ddi_prop_op, /* cb_prop_op */ 124 NULL, /* cb_stream */ 125 D_MP | D_HOTPLUG, /* cb_flag */ 126 CB_REV, /* cb_rev */ 127 nodev, /* cb_aread */ 128 nodev /* cb_awrite */ 129 }; 130 131 static struct dev_ops igb_dev_ops = { 132 DEVO_REV, /* devo_rev */ 133 0, /* devo_refcnt */ 134 NULL, /* devo_getinfo */ 135 nulldev, /* devo_identify */ 136 nulldev, /* devo_probe */ 137 igb_attach, /* devo_attach */ 138 igb_detach, /* devo_detach */ 139 nodev, /* devo_reset */ 140 &igb_cb_ops, /* devo_cb_ops */ 141 NULL, /* devo_bus_ops */ 142 ddi_power /* devo_power */ 143 }; 144 145 static struct modldrv igb_modldrv = { 146 &mod_driverops, /* Type of module. This one is a driver */ 147 ident, /* Discription string */ 148 &igb_dev_ops, /* driver ops */ 149 }; 150 151 static struct modlinkage igb_modlinkage = { 152 MODREV_1, &igb_modldrv, NULL 153 }; 154 155 /* Access attributes for register mapping */ 156 ddi_device_acc_attr_t igb_regs_acc_attr = { 157 DDI_DEVICE_ATTR_V0, 158 DDI_STRUCTURE_LE_ACC, 159 DDI_STRICTORDER_ACC, 160 }; 161 162 #define IGB_M_CALLBACK_FLAGS (MC_IOCTL | MC_GETCAPAB) 163 164 static mac_callbacks_t igb_m_callbacks = { 165 IGB_M_CALLBACK_FLAGS, 166 igb_m_stat, 167 igb_m_start, 168 igb_m_stop, 169 igb_m_promisc, 170 igb_m_multicst, 171 igb_m_unicst, 172 igb_m_tx, 173 NULL, 174 igb_m_ioctl, 175 igb_m_getcapab 176 }; 177 178 179 /* 180 * Module Initialization Functions 181 */ 182 183 int 184 _init(void) 185 { 186 int status; 187 188 mac_init_ops(&igb_dev_ops, MODULE_NAME); 189 190 status = mod_install(&igb_modlinkage); 191 192 if (status != DDI_SUCCESS) { 193 mac_fini_ops(&igb_dev_ops); 194 } 195 196 return (status); 197 } 198 199 int 200 _fini(void) 201 { 202 int status; 203 204 status = mod_remove(&igb_modlinkage); 205 206 if (status == DDI_SUCCESS) { 207 mac_fini_ops(&igb_dev_ops); 208 } 209 210 return (status); 211 212 } 213 214 int 215 _info(struct modinfo *modinfop) 216 { 217 int status; 218 219 status = mod_info(&igb_modlinkage, modinfop); 220 221 return (status); 222 } 223 224 /* 225 * igb_attach - driver attach 226 * 227 * This function is the device specific initialization entry 228 * point. This entry point is required and must be written. 229 * The DDI_ATTACH command must be provided in the attach entry 230 * point. When attach() is called with cmd set to DDI_ATTACH, 231 * all normal kernel services (such as kmem_alloc(9F)) are 232 * available for use by the driver. 233 * 234 * The attach() function will be called once for each instance 235 * of the device on the system with cmd set to DDI_ATTACH. 236 * Until attach() succeeds, the only driver entry points which 237 * may be called are open(9E) and getinfo(9E). 238 */ 239 static int 240 igb_attach(dev_info_t *devinfo, ddi_attach_cmd_t cmd) 241 { 242 igb_t *igb; 243 struct igb_osdep *osdep; 244 struct e1000_hw *hw; 245 int instance; 246 247 /* 248 * Check the command and perform corresponding operations 249 */ 250 switch (cmd) { 251 default: 252 return (DDI_FAILURE); 253 254 case DDI_RESUME: 255 return (igb_resume(devinfo)); 256 257 case DDI_ATTACH: 258 break; 259 } 260 261 /* Get the device instance */ 262 instance = ddi_get_instance(devinfo); 263 264 /* Allocate memory for the instance data structure */ 265 igb = kmem_zalloc(sizeof (igb_t), KM_SLEEP); 266 267 igb->dip = devinfo; 268 igb->instance = instance; 269 270 hw = &igb->hw; 271 osdep = &igb->osdep; 272 hw->back = osdep; 273 osdep->igb = igb; 274 275 /* Attach the instance pointer to the dev_info data structure */ 276 ddi_set_driver_private(devinfo, igb); 277 278 /* 279 * Map PCI config space registers 280 */ 281 if (pci_config_setup(devinfo, &osdep->cfg_handle) != DDI_SUCCESS) { 282 igb_error(igb, "Failed to map PCI configurations"); 283 goto attach_fail; 284 } 285 igb->attach_progress |= ATTACH_PROGRESS_PCI_CONFIG; 286 287 /* 288 * Identify the chipset family 289 */ 290 if (igb_identify_hardware(igb) != IGB_SUCCESS) { 291 igb_error(igb, "Failed to identify hardware"); 292 goto attach_fail; 293 } 294 295 /* 296 * Map device registers 297 */ 298 if (igb_regs_map(igb) != IGB_SUCCESS) { 299 igb_error(igb, "Failed to map device registers"); 300 goto attach_fail; 301 } 302 igb->attach_progress |= ATTACH_PROGRESS_REGS_MAP; 303 304 /* 305 * Initialize driver parameters 306 */ 307 igb_init_properties(igb); 308 igb->attach_progress |= ATTACH_PROGRESS_PROPS; 309 310 /* 311 * Allocate interrupts 312 */ 313 if (igb_alloc_intrs(igb) != IGB_SUCCESS) { 314 igb_error(igb, "Failed to allocate interrupts"); 315 goto attach_fail; 316 } 317 igb->attach_progress |= ATTACH_PROGRESS_ALLOC_INTR; 318 319 /* 320 * Allocate rx/tx rings based on the ring numbers. 321 * The actual numbers of rx/tx rings are decided by the number of 322 * allocated interrupt vectors, so we should allocate the rings after 323 * interrupts are allocated. 324 */ 325 if (igb_alloc_rings(igb) != IGB_SUCCESS) { 326 igb_error(igb, "Failed to allocate rx and tx rings"); 327 goto attach_fail; 328 } 329 igb->attach_progress |= ATTACH_PROGRESS_ALLOC_RINGS; 330 331 /* 332 * Add interrupt handlers 333 */ 334 if (igb_add_intr_handlers(igb) != IGB_SUCCESS) { 335 igb_error(igb, "Failed to add interrupt handlers"); 336 goto attach_fail; 337 } 338 igb->attach_progress |= ATTACH_PROGRESS_ADD_INTR; 339 340 /* 341 * Initialize driver parameters 342 */ 343 if (igb_init_driver_settings(igb) != IGB_SUCCESS) { 344 igb_error(igb, "Failed to initialize driver settings"); 345 goto attach_fail; 346 } 347 348 /* 349 * Initialize mutexes for this device. 350 * Do this before enabling the interrupt handler and 351 * register the softint to avoid the condition where 352 * interrupt handler can try using uninitialized mutex 353 */ 354 igb_init_locks(igb); 355 igb->attach_progress |= ATTACH_PROGRESS_LOCKS; 356 357 /* 358 * Initialize chipset hardware 359 */ 360 if (igb_init(igb) != IGB_SUCCESS) { 361 igb_error(igb, "Failed to initialize adapter"); 362 goto attach_fail; 363 } 364 igb->attach_progress |= ATTACH_PROGRESS_INIT; 365 366 /* 367 * Initialize DMA and hardware settings for rx/tx rings 368 */ 369 if (igb_init_rings(igb) != IGB_SUCCESS) { 370 igb_error(igb, "Failed to initialize rings"); 371 goto attach_fail; 372 } 373 igb->attach_progress |= ATTACH_PROGRESS_INIT_RINGS; 374 375 /* 376 * Initialize statistics 377 */ 378 if (igb_init_stats(igb) != IGB_SUCCESS) { 379 igb_error(igb, "Failed to initialize statistics"); 380 goto attach_fail; 381 } 382 igb->attach_progress |= ATTACH_PROGRESS_STATS; 383 384 /* 385 * Initialize NDD parameters 386 */ 387 if (igb_nd_init(igb) != IGB_SUCCESS) { 388 igb_error(igb, "Failed to initialize ndd"); 389 goto attach_fail; 390 } 391 igb->attach_progress |= ATTACH_PROGRESS_NDD; 392 393 /* 394 * Register the driver to the MAC 395 */ 396 if (igb_register_mac(igb) != IGB_SUCCESS) { 397 igb_error(igb, "Failed to register MAC"); 398 goto attach_fail; 399 } 400 igb->attach_progress |= ATTACH_PROGRESS_MAC; 401 402 /* 403 * Now that mutex locks are initialized, and the chip is also 404 * initialized, enable interrupts. 405 */ 406 if (igb_enable_intrs(igb) != IGB_SUCCESS) { 407 igb_error(igb, "Failed to enable DDI interrupts"); 408 goto attach_fail; 409 } 410 igb->attach_progress |= ATTACH_PROGRESS_ENABLE_INTR; 411 412 igb->igb_state |= IGB_INITIALIZED; 413 414 return (DDI_SUCCESS); 415 416 attach_fail: 417 igb_unconfigure(devinfo, igb); 418 return (DDI_FAILURE); 419 } 420 421 /* 422 * igb_detach - driver detach 423 * 424 * The detach() function is the complement of the attach routine. 425 * If cmd is set to DDI_DETACH, detach() is used to remove the 426 * state associated with a given instance of a device node 427 * prior to the removal of that instance from the system. 428 * 429 * The detach() function will be called once for each instance 430 * of the device for which there has been a successful attach() 431 * once there are no longer any opens on the device. 432 * 433 * Interrupts routine are disabled, All memory allocated by this 434 * driver are freed. 435 */ 436 static int 437 igb_detach(dev_info_t *devinfo, ddi_detach_cmd_t cmd) 438 { 439 igb_t *igb; 440 441 /* 442 * Check detach command 443 */ 444 switch (cmd) { 445 default: 446 return (DDI_FAILURE); 447 448 case DDI_SUSPEND: 449 return (igb_suspend(devinfo)); 450 451 case DDI_DETACH: 452 break; 453 } 454 455 456 /* 457 * Get the pointer to the driver private data structure 458 */ 459 igb = (igb_t *)ddi_get_driver_private(devinfo); 460 if (igb == NULL) 461 return (DDI_FAILURE); 462 463 /* 464 * Unregister MAC. If failed, we have to fail the detach 465 */ 466 if (mac_unregister(igb->mac_hdl) != 0) { 467 igb_error(igb, "Failed to unregister MAC"); 468 return (DDI_FAILURE); 469 } 470 igb->attach_progress &= ~ATTACH_PROGRESS_MAC; 471 472 /* 473 * If the device is still running, it needs to be stopped first. 474 * This check is necessary because under some specific circumstances, 475 * the detach routine can be called without stopping the interface 476 * first. 477 */ 478 mutex_enter(&igb->gen_lock); 479 if (igb->igb_state & IGB_STARTED) { 480 igb->igb_state &= ~IGB_STARTED; 481 igb_stop(igb); 482 mutex_exit(&igb->gen_lock); 483 /* Disable and stop the watchdog timer */ 484 igb_disable_watchdog_timer(igb); 485 } else 486 mutex_exit(&igb->gen_lock); 487 488 /* 489 * Check if there are still rx buffers held by the upper layer. 490 * If so, fail the detach. 491 */ 492 if (!igb_rx_drain(igb)) 493 return (DDI_FAILURE); 494 495 /* 496 * Do the remaining unconfigure routines 497 */ 498 igb_unconfigure(devinfo, igb); 499 500 return (DDI_SUCCESS); 501 } 502 503 static void 504 igb_unconfigure(dev_info_t *devinfo, igb_t *igb) 505 { 506 /* 507 * Disable interrupt 508 */ 509 if (igb->attach_progress & ATTACH_PROGRESS_ENABLE_INTR) { 510 (void) igb_disable_intrs(igb); 511 } 512 513 /* 514 * Unregister MAC 515 */ 516 if (igb->attach_progress & ATTACH_PROGRESS_MAC) { 517 (void) mac_unregister(igb->mac_hdl); 518 } 519 520 /* 521 * Free ndd parameters 522 */ 523 if (igb->attach_progress & ATTACH_PROGRESS_NDD) { 524 igb_nd_cleanup(igb); 525 } 526 527 /* 528 * Free statistics 529 */ 530 if (igb->attach_progress & ATTACH_PROGRESS_STATS) { 531 kstat_delete((kstat_t *)igb->igb_ks); 532 } 533 534 /* 535 * Remove interrupt handlers 536 */ 537 if (igb->attach_progress & ATTACH_PROGRESS_ADD_INTR) { 538 igb_rem_intr_handlers(igb); 539 } 540 541 /* 542 * Remove interrupts 543 */ 544 if (igb->attach_progress & ATTACH_PROGRESS_ALLOC_INTR) { 545 igb_rem_intrs(igb); 546 } 547 548 /* 549 * Remove driver properties 550 */ 551 if (igb->attach_progress & ATTACH_PROGRESS_PROPS) { 552 (void) ddi_prop_remove_all(devinfo); 553 } 554 555 /* 556 * Release the DMA resources of rx/tx rings 557 */ 558 if (igb->attach_progress & ATTACH_PROGRESS_INIT_RINGS) { 559 igb_fini_rings(igb); 560 } 561 562 /* 563 * Stop the chipset 564 */ 565 if (igb->attach_progress & ATTACH_PROGRESS_INIT) { 566 mutex_enter(&igb->gen_lock); 567 igb_chip_stop(igb); 568 mutex_exit(&igb->gen_lock); 569 } 570 571 /* 572 * Free register handle 573 */ 574 if (igb->attach_progress & ATTACH_PROGRESS_REGS_MAP) { 575 if (igb->osdep.reg_handle != NULL) 576 ddi_regs_map_free(&igb->osdep.reg_handle); 577 } 578 579 /* 580 * Free PCI config handle 581 */ 582 if (igb->attach_progress & ATTACH_PROGRESS_PCI_CONFIG) { 583 if (igb->osdep.cfg_handle != NULL) 584 pci_config_teardown(&igb->osdep.cfg_handle); 585 } 586 587 /* 588 * Free locks 589 */ 590 if (igb->attach_progress & ATTACH_PROGRESS_LOCKS) { 591 igb_destroy_locks(igb); 592 } 593 594 /* 595 * Free the rx/tx rings 596 */ 597 if (igb->attach_progress & ATTACH_PROGRESS_ALLOC_RINGS) { 598 igb_free_rings(igb); 599 } 600 601 /* 602 * Free device specific structure 603 */ 604 e1000_remove_device(&igb->hw); 605 606 /* 607 * Free the driver data structure 608 */ 609 kmem_free(igb, sizeof (igb_t)); 610 611 ddi_set_driver_private(devinfo, NULL); 612 } 613 614 /* 615 * igb_register_mac - Register the driver and its function pointers with 616 * the GLD interface 617 */ 618 static int 619 igb_register_mac(igb_t *igb) 620 { 621 struct e1000_hw *hw = &igb->hw; 622 mac_register_t *mac; 623 int status; 624 625 if ((mac = mac_alloc(MAC_VERSION)) == NULL) 626 return (IGB_FAILURE); 627 628 mac->m_type_ident = MAC_PLUGIN_IDENT_ETHER; 629 mac->m_driver = igb; 630 mac->m_dip = igb->dip; 631 mac->m_src_addr = hw->mac.addr; 632 mac->m_callbacks = &igb_m_callbacks; 633 mac->m_min_sdu = 0; 634 mac->m_max_sdu = igb->max_frame_size - 635 sizeof (struct ether_vlan_header) - ETHERFCSL; 636 mac->m_margin = VLAN_TAGSZ; 637 638 status = mac_register(mac, &igb->mac_hdl); 639 640 mac_free(mac); 641 642 return ((status == 0) ? IGB_SUCCESS : IGB_FAILURE); 643 } 644 645 /* 646 * igb_identify_hardware - Identify the type of the chipset 647 */ 648 static int 649 igb_identify_hardware(igb_t *igb) 650 { 651 struct e1000_hw *hw = &igb->hw; 652 struct igb_osdep *osdep = &igb->osdep; 653 654 /* 655 * Get the device id 656 */ 657 hw->vendor_id = 658 pci_config_get16(osdep->cfg_handle, PCI_CONF_VENID); 659 hw->device_id = 660 pci_config_get16(osdep->cfg_handle, PCI_CONF_DEVID); 661 hw->revision_id = 662 pci_config_get8(osdep->cfg_handle, PCI_CONF_REVID); 663 hw->subsystem_device_id = 664 pci_config_get16(osdep->cfg_handle, PCI_CONF_SUBSYSID); 665 hw->subsystem_vendor_id = 666 pci_config_get16(osdep->cfg_handle, PCI_CONF_SUBVENID); 667 668 /* 669 * Set the mac type of the adapter based on the device id 670 */ 671 if (e1000_set_mac_type(hw) != E1000_SUCCESS) { 672 return (IGB_FAILURE); 673 } 674 675 return (IGB_SUCCESS); 676 } 677 678 /* 679 * igb_regs_map - Map the device registers 680 */ 681 static int 682 igb_regs_map(igb_t *igb) 683 { 684 dev_info_t *devinfo = igb->dip; 685 struct e1000_hw *hw = &igb->hw; 686 struct igb_osdep *osdep = &igb->osdep; 687 off_t mem_size; 688 689 /* 690 * First get the size of device registers to be mapped. 691 */ 692 if (ddi_dev_regsize(devinfo, 1, &mem_size) != DDI_SUCCESS) { 693 return (IGB_FAILURE); 694 } 695 696 /* 697 * Call ddi_regs_map_setup() to map registers 698 */ 699 if ((ddi_regs_map_setup(devinfo, 1, 700 (caddr_t *)&hw->hw_addr, 0, 701 mem_size, &igb_regs_acc_attr, 702 &osdep->reg_handle)) != DDI_SUCCESS) { 703 return (IGB_FAILURE); 704 } 705 706 return (IGB_SUCCESS); 707 } 708 709 /* 710 * igb_init_properties - Initialize driver properties 711 */ 712 static void 713 igb_init_properties(igb_t *igb) 714 { 715 /* 716 * Get conf file properties, including link settings 717 * jumbo frames, ring number, descriptor number, etc. 718 */ 719 igb_get_conf(igb); 720 } 721 722 /* 723 * igb_init_driver_settings - Initialize driver settings 724 * 725 * The settings include hardware function pointers, bus information, 726 * rx/tx rings settings, link state, and any other parameters that 727 * need to be setup during driver initialization. 728 */ 729 static int 730 igb_init_driver_settings(igb_t *igb) 731 { 732 struct e1000_hw *hw = &igb->hw; 733 igb_rx_ring_t *rx_ring; 734 igb_tx_ring_t *tx_ring; 735 uint32_t rx_size; 736 uint32_t tx_size; 737 int i; 738 739 /* 740 * Initialize chipset specific hardware function pointers 741 */ 742 if (e1000_setup_init_funcs(hw, B_TRUE) != E1000_SUCCESS) { 743 return (IGB_FAILURE); 744 } 745 746 /* 747 * Get bus information 748 */ 749 if (e1000_get_bus_info(hw) != E1000_SUCCESS) { 750 return (IGB_FAILURE); 751 } 752 753 /* 754 * Set rx buffer size 755 * The IP header alignment room is counted in the calculation. 756 * The rx buffer size is in unit of 1K that is required by the 757 * chipset hardware. 758 */ 759 rx_size = igb->max_frame_size + IPHDR_ALIGN_ROOM; 760 igb->rx_buf_size = ((rx_size >> 10) + 761 ((rx_size & (((uint32_t)1 << 10) - 1)) > 0 ? 1 : 0)) << 10; 762 763 /* 764 * Set tx buffer size 765 */ 766 tx_size = igb->max_frame_size; 767 igb->tx_buf_size = ((tx_size >> 10) + 768 ((tx_size & (((uint32_t)1 << 10) - 1)) > 0 ? 1 : 0)) << 10; 769 770 /* 771 * Initialize rx/tx rings parameters 772 */ 773 for (i = 0; i < igb->num_rx_rings; i++) { 774 rx_ring = &igb->rx_rings[i]; 775 rx_ring->index = i; 776 rx_ring->igb = igb; 777 778 rx_ring->ring_size = igb->rx_ring_size; 779 rx_ring->free_list_size = igb->rx_ring_size; 780 rx_ring->copy_thresh = igb->rx_copy_thresh; 781 rx_ring->limit_per_intr = igb->rx_limit_per_intr; 782 } 783 784 for (i = 0; i < igb->num_tx_rings; i++) { 785 tx_ring = &igb->tx_rings[i]; 786 tx_ring->index = i; 787 tx_ring->igb = igb; 788 if (igb->tx_head_wb_enable) 789 tx_ring->tx_recycle = igb_tx_recycle_head_wb; 790 else 791 tx_ring->tx_recycle = igb_tx_recycle_legacy; 792 793 tx_ring->ring_size = igb->tx_ring_size; 794 tx_ring->free_list_size = igb->tx_ring_size + 795 (igb->tx_ring_size >> 1); 796 tx_ring->copy_thresh = igb->tx_copy_thresh; 797 tx_ring->recycle_thresh = igb->tx_recycle_thresh; 798 tx_ring->overload_thresh = igb->tx_overload_thresh; 799 tx_ring->resched_thresh = igb->tx_resched_thresh; 800 } 801 802 /* 803 * Initialize values of interrupt throttling rate 804 */ 805 for (i = 1; i < MAX_NUM_EITR; i++) 806 igb->intr_throttling[i] = igb->intr_throttling[0]; 807 808 /* 809 * The initial link state should be "unknown" 810 */ 811 igb->link_state = LINK_STATE_UNKNOWN; 812 813 return (IGB_SUCCESS); 814 } 815 816 /* 817 * igb_init_locks - Initialize locks 818 */ 819 static void 820 igb_init_locks(igb_t *igb) 821 { 822 igb_rx_ring_t *rx_ring; 823 igb_tx_ring_t *tx_ring; 824 int i; 825 826 for (i = 0; i < igb->num_rx_rings; i++) { 827 rx_ring = &igb->rx_rings[i]; 828 mutex_init(&rx_ring->rx_lock, NULL, 829 MUTEX_DRIVER, DDI_INTR_PRI(igb->intr_pri)); 830 mutex_init(&rx_ring->recycle_lock, NULL, 831 MUTEX_DRIVER, DDI_INTR_PRI(igb->intr_pri)); 832 } 833 834 for (i = 0; i < igb->num_tx_rings; i++) { 835 tx_ring = &igb->tx_rings[i]; 836 mutex_init(&tx_ring->tx_lock, NULL, 837 MUTEX_DRIVER, DDI_INTR_PRI(igb->intr_pri)); 838 mutex_init(&tx_ring->recycle_lock, NULL, 839 MUTEX_DRIVER, DDI_INTR_PRI(igb->intr_pri)); 840 mutex_init(&tx_ring->tcb_head_lock, NULL, 841 MUTEX_DRIVER, DDI_INTR_PRI(igb->intr_pri)); 842 mutex_init(&tx_ring->tcb_tail_lock, NULL, 843 MUTEX_DRIVER, DDI_INTR_PRI(igb->intr_pri)); 844 } 845 846 mutex_init(&igb->gen_lock, NULL, 847 MUTEX_DRIVER, DDI_INTR_PRI(igb->intr_pri)); 848 849 mutex_init(&igb->watchdog_lock, NULL, 850 MUTEX_DRIVER, DDI_INTR_PRI(igb->intr_pri)); 851 } 852 853 /* 854 * igb_destroy_locks - Destroy locks 855 */ 856 static void 857 igb_destroy_locks(igb_t *igb) 858 { 859 igb_rx_ring_t *rx_ring; 860 igb_tx_ring_t *tx_ring; 861 int i; 862 863 for (i = 0; i < igb->num_rx_rings; i++) { 864 rx_ring = &igb->rx_rings[i]; 865 mutex_destroy(&rx_ring->rx_lock); 866 mutex_destroy(&rx_ring->recycle_lock); 867 } 868 869 for (i = 0; i < igb->num_tx_rings; i++) { 870 tx_ring = &igb->tx_rings[i]; 871 mutex_destroy(&tx_ring->tx_lock); 872 mutex_destroy(&tx_ring->recycle_lock); 873 mutex_destroy(&tx_ring->tcb_head_lock); 874 mutex_destroy(&tx_ring->tcb_tail_lock); 875 } 876 877 mutex_destroy(&igb->gen_lock); 878 mutex_destroy(&igb->watchdog_lock); 879 } 880 881 static int 882 igb_resume(dev_info_t *devinfo) 883 { 884 igb_t *igb; 885 886 igb = (igb_t *)ddi_get_driver_private(devinfo); 887 if (igb == NULL) 888 return (DDI_FAILURE); 889 890 mutex_enter(&igb->gen_lock); 891 892 if (igb->igb_state & IGB_STARTED) { 893 if (igb_start(igb) != IGB_SUCCESS) { 894 mutex_exit(&igb->gen_lock); 895 return (DDI_FAILURE); 896 } 897 898 /* 899 * Enable and start the watchdog timer 900 */ 901 igb_enable_watchdog_timer(igb); 902 } 903 904 igb->igb_state &= ~IGB_SUSPENDED; 905 906 mutex_exit(&igb->gen_lock); 907 908 return (DDI_SUCCESS); 909 } 910 911 static int 912 igb_suspend(dev_info_t *devinfo) 913 { 914 igb_t *igb; 915 916 igb = (igb_t *)ddi_get_driver_private(devinfo); 917 if (igb == NULL) 918 return (DDI_FAILURE); 919 920 mutex_enter(&igb->gen_lock); 921 922 igb->igb_state |= IGB_SUSPENDED; 923 924 igb_stop(igb); 925 926 mutex_exit(&igb->gen_lock); 927 928 /* 929 * Disable and stop the watchdog timer 930 */ 931 igb_disable_watchdog_timer(igb); 932 933 return (DDI_SUCCESS); 934 } 935 936 /* 937 * igb_init - Initialize the device 938 */ 939 static int 940 igb_init(igb_t *igb) 941 { 942 struct e1000_hw *hw = &igb->hw; 943 uint32_t pba; 944 uint32_t high_water; 945 946 mutex_enter(&igb->gen_lock); 947 948 /* 949 * Reset chipset to put the hardware in a known state 950 * before we try to do anything with the eeprom 951 */ 952 (void) e1000_reset_hw(hw); 953 954 /* 955 * NVM validation 956 */ 957 if (e1000_validate_nvm_checksum(hw) < 0) { 958 /* 959 * Some PCI-E parts fail the first check due to 960 * the link being in sleep state. Call it again, 961 * if it fails a second time its a real issue. 962 */ 963 if (e1000_validate_nvm_checksum(hw) < 0) { 964 igb_error(igb, 965 "Invalid NVM checksum. Please contact " 966 "the vendor to update the NVM."); 967 goto init_fail; 968 } 969 } 970 971 /* 972 * Set the FIFO size 973 */ 974 pba = E1000_PBA_32K; /* 32K for Rx, 16K for Tx */ 975 E1000_WRITE_REG(hw, E1000_PBA, pba); 976 977 /* 978 * Setup flow control 979 * 980 * These parameters set thresholds for the adapter's generation(Tx) 981 * and response(Rx) to Ethernet PAUSE frames. These are just threshold 982 * settings. Flow control is enabled or disabled in the configuration 983 * file. 984 * High-water mark is set down from the top of the rx fifo (not 985 * sensitive to max_frame_size) and low-water is set just below 986 * high-water mark. 987 * The high water mark must be low enough to fit one full frame above 988 * it in the rx FIFO. Should be the lower of: 989 * 90% of the Rx FIFO size, or the full Rx FIFO size minus one full 990 * frame. 991 */ 992 high_water = min(((pba << 10) * 9 / 10), 993 ((pba << 10) - igb->max_frame_size)); 994 995 hw->fc.high_water = high_water & 0xFFF8; 996 hw->fc.low_water = hw->fc.high_water - 8; 997 hw->fc.pause_time = E1000_FC_PAUSE_TIME; 998 hw->fc.send_xon = B_TRUE; 999 1000 /* 1001 * Reset the chipset hardware the second time to validate 1002 * the PBA setting. 1003 */ 1004 (void) e1000_reset_hw(hw); 1005 1006 /* 1007 * Don't wait for auto-negotiation to complete 1008 */ 1009 hw->phy.autoneg_wait_to_complete = B_FALSE; 1010 1011 /* 1012 * Copper options 1013 */ 1014 if (hw->phy.media_type == e1000_media_type_copper) { 1015 hw->phy.mdix = 0; /* AUTO_ALL_MODES */ 1016 hw->phy.disable_polarity_correction = B_FALSE; 1017 hw->phy.ms_type = e1000_ms_hw_default; /* E1000_MASTER_SLAVE */ 1018 } 1019 1020 /* 1021 * Initialize link settings 1022 */ 1023 (void) igb_setup_link(igb, B_FALSE); 1024 1025 /* 1026 * Initialize the chipset hardware 1027 */ 1028 if (igb_chip_start(igb) != IGB_SUCCESS) { 1029 goto init_fail; 1030 } 1031 1032 mutex_exit(&igb->gen_lock); 1033 return (IGB_SUCCESS); 1034 1035 init_fail: 1036 /* 1037 * Reset PHY if possible 1038 */ 1039 if (e1000_check_reset_block(hw) == E1000_SUCCESS) 1040 (void) e1000_phy_hw_reset(hw); 1041 1042 mutex_exit(&igb->gen_lock); 1043 return (IGB_FAILURE); 1044 } 1045 1046 /* 1047 * igb_init_rings - Allocate DMA resources for all rx/tx rings and 1048 * initialize relevant hardware settings. 1049 */ 1050 static int 1051 igb_init_rings(igb_t *igb) 1052 { 1053 int i; 1054 1055 /* 1056 * Allocate buffers for all the rx/tx rings 1057 */ 1058 if (igb_alloc_dma(igb) != IGB_SUCCESS) 1059 return (IGB_FAILURE); 1060 1061 /* 1062 * Setup the rx/tx rings 1063 */ 1064 mutex_enter(&igb->gen_lock); 1065 1066 for (i = 0; i < igb->num_rx_rings; i++) 1067 mutex_enter(&igb->rx_rings[i].rx_lock); 1068 for (i = 0; i < igb->num_tx_rings; i++) 1069 mutex_enter(&igb->tx_rings[i].tx_lock); 1070 1071 igb_setup_rings(igb); 1072 1073 for (i = igb->num_tx_rings - 1; i >= 0; i--) 1074 mutex_exit(&igb->tx_rings[i].tx_lock); 1075 for (i = igb->num_rx_rings - 1; i >= 0; i--) 1076 mutex_exit(&igb->rx_rings[i].rx_lock); 1077 1078 mutex_exit(&igb->gen_lock); 1079 1080 return (IGB_SUCCESS); 1081 } 1082 1083 /* 1084 * igb_fini_rings - Release DMA resources of all rx/tx rings 1085 */ 1086 static void 1087 igb_fini_rings(igb_t *igb) 1088 { 1089 /* 1090 * Release the DMA/memory resources of rx/tx rings 1091 */ 1092 igb_free_dma(igb); 1093 } 1094 1095 /* 1096 * igb_chip_start - Initialize and start the chipset hardware 1097 */ 1098 static int 1099 igb_chip_start(igb_t *igb) 1100 { 1101 struct e1000_hw *hw = &igb->hw; 1102 int i; 1103 1104 ASSERT(mutex_owned(&igb->gen_lock)); 1105 1106 /* 1107 * Get the mac address 1108 * This function should handle SPARC case correctly. 1109 */ 1110 if (!igb_find_mac_address(igb)) { 1111 igb_error(igb, "Failed to get the mac address"); 1112 return (IGB_FAILURE); 1113 } 1114 1115 /* Validate mac address */ 1116 if (!is_valid_mac_addr(hw->mac.addr)) { 1117 igb_error(igb, "Invalid mac address"); 1118 return (IGB_FAILURE); 1119 } 1120 1121 /* Disable wakeup control by default */ 1122 E1000_WRITE_REG(hw, E1000_WUC, 0); 1123 1124 /* 1125 * Configure/Initialize hardware 1126 */ 1127 if (e1000_init_hw(hw) != E1000_SUCCESS) { 1128 igb_error(igb, "Failed to initialize hardware"); 1129 return (IGB_FAILURE); 1130 } 1131 1132 /* 1133 * Make sure driver has control 1134 */ 1135 igb_get_driver_control(hw); 1136 1137 /* 1138 * Setup MSI-X interrupts 1139 */ 1140 if (igb->intr_type == DDI_INTR_TYPE_MSIX) 1141 igb_setup_adapter_msix(igb); 1142 1143 /* 1144 * Initialize unicast addresses. 1145 */ 1146 igb_init_unicst(igb); 1147 1148 /* 1149 * Setup and initialize the mctable structures. 1150 */ 1151 igb_setup_multicst(igb); 1152 1153 /* 1154 * Set interrupt throttling rate 1155 */ 1156 for (i = 0; i < igb->intr_cnt; i++) 1157 E1000_WRITE_REG(hw, E1000_EITR(i), igb->intr_throttling[i]); 1158 1159 /* Enable PCI-E master */ 1160 if (hw->bus.type == e1000_bus_type_pci_express) { 1161 e1000_enable_pciex_master(hw); 1162 } 1163 1164 /* 1165 * Save the state of the phy 1166 */ 1167 igb_get_phy_state(igb); 1168 1169 return (IGB_SUCCESS); 1170 } 1171 1172 /* 1173 * igb_chip_stop - Stop the chipset hardware 1174 */ 1175 static void 1176 igb_chip_stop(igb_t *igb) 1177 { 1178 struct e1000_hw *hw = &igb->hw; 1179 1180 ASSERT(mutex_owned(&igb->gen_lock)); 1181 1182 /* Tell firmware driver is no longer in control */ 1183 igb_release_driver_control(hw); 1184 1185 /* 1186 * Reset the chipset 1187 */ 1188 (void) e1000_reset_hw(hw); 1189 1190 /* 1191 * Reset PHY if possible 1192 */ 1193 if (e1000_check_reset_block(hw) == E1000_SUCCESS) 1194 (void) e1000_phy_hw_reset(hw); 1195 } 1196 1197 /* 1198 * igb_reset - Reset the chipset and restart the driver. 1199 * 1200 * It involves stopping and re-starting the chipset, 1201 * and re-configuring the rx/tx rings. 1202 */ 1203 static int 1204 igb_reset(igb_t *igb) 1205 { 1206 int i; 1207 1208 mutex_enter(&igb->gen_lock); 1209 1210 ASSERT(igb->igb_state & IGB_STARTED); 1211 1212 /* 1213 * Disable the adapter interrupts to stop any rx/tx activities 1214 * before draining pending data and resetting hardware. 1215 */ 1216 igb_disable_adapter_interrupts(igb); 1217 1218 /* 1219 * Drain the pending transmit packets 1220 */ 1221 (void) igb_tx_drain(igb); 1222 1223 for (i = 0; i < igb->num_rx_rings; i++) 1224 mutex_enter(&igb->rx_rings[i].rx_lock); 1225 for (i = 0; i < igb->num_tx_rings; i++) 1226 mutex_enter(&igb->tx_rings[i].tx_lock); 1227 1228 /* 1229 * Stop the chipset hardware 1230 */ 1231 igb_chip_stop(igb); 1232 1233 /* 1234 * Clean the pending tx data/resources 1235 */ 1236 igb_tx_clean(igb); 1237 1238 /* 1239 * Start the chipset hardware 1240 */ 1241 if (igb_chip_start(igb) != IGB_SUCCESS) { 1242 goto reset_failure; 1243 } 1244 1245 /* 1246 * Setup the rx/tx rings 1247 */ 1248 igb_setup_rings(igb); 1249 1250 /* 1251 * Enable adapter interrupts 1252 * The interrupts must be enabled after the driver state is START 1253 */ 1254 igb_enable_adapter_interrupts(igb); 1255 1256 for (i = igb->num_tx_rings - 1; i >= 0; i--) 1257 mutex_exit(&igb->tx_rings[i].tx_lock); 1258 for (i = igb->num_rx_rings - 1; i >= 0; i--) 1259 mutex_exit(&igb->rx_rings[i].rx_lock); 1260 1261 mutex_exit(&igb->gen_lock); 1262 1263 return (IGB_SUCCESS); 1264 1265 reset_failure: 1266 for (i = igb->num_tx_rings - 1; i >= 0; i--) 1267 mutex_exit(&igb->tx_rings[i].tx_lock); 1268 for (i = igb->num_rx_rings - 1; i >= 0; i--) 1269 mutex_exit(&igb->rx_rings[i].rx_lock); 1270 1271 mutex_exit(&igb->gen_lock); 1272 1273 return (IGB_FAILURE); 1274 } 1275 1276 /* 1277 * igb_tx_clean - Clean the pending transmit packets and DMA resources 1278 */ 1279 static void 1280 igb_tx_clean(igb_t *igb) 1281 { 1282 igb_tx_ring_t *tx_ring; 1283 tx_control_block_t *tcb; 1284 link_list_t pending_list; 1285 uint32_t desc_num; 1286 int i, j; 1287 1288 LINK_LIST_INIT(&pending_list); 1289 1290 for (i = 0; i < igb->num_tx_rings; i++) { 1291 tx_ring = &igb->tx_rings[i]; 1292 1293 mutex_enter(&tx_ring->recycle_lock); 1294 1295 /* 1296 * Clean the pending tx data - the pending packets in the 1297 * work_list that have no chances to be transmitted again. 1298 * 1299 * We must ensure the chipset is stopped or the link is down 1300 * before cleaning the transmit packets. 1301 */ 1302 desc_num = 0; 1303 for (j = 0; j < tx_ring->ring_size; j++) { 1304 tcb = tx_ring->work_list[j]; 1305 if (tcb != NULL) { 1306 desc_num += tcb->desc_num; 1307 1308 tx_ring->work_list[j] = NULL; 1309 1310 igb_free_tcb(tcb); 1311 1312 LIST_PUSH_TAIL(&pending_list, &tcb->link); 1313 } 1314 } 1315 1316 if (desc_num > 0) { 1317 atomic_add_32(&tx_ring->tbd_free, desc_num); 1318 ASSERT(tx_ring->tbd_free == tx_ring->ring_size); 1319 1320 /* 1321 * Reset the head and tail pointers of the tbd ring 1322 */ 1323 tx_ring->tbd_head = 0; 1324 tx_ring->tbd_tail = 0; 1325 1326 E1000_WRITE_REG(&igb->hw, E1000_TDH(tx_ring->index), 0); 1327 E1000_WRITE_REG(&igb->hw, E1000_TDT(tx_ring->index), 0); 1328 } 1329 1330 mutex_exit(&tx_ring->recycle_lock); 1331 1332 /* 1333 * Add the tx control blocks in the pending list to 1334 * the free list. 1335 */ 1336 igb_put_free_list(tx_ring, &pending_list); 1337 } 1338 } 1339 1340 /* 1341 * igb_tx_drain - Drain the tx rings to allow pending packets to be transmitted 1342 */ 1343 static boolean_t 1344 igb_tx_drain(igb_t *igb) 1345 { 1346 igb_tx_ring_t *tx_ring; 1347 boolean_t done; 1348 int i, j; 1349 1350 /* 1351 * Wait for a specific time to allow pending tx packets 1352 * to be transmitted. 1353 * 1354 * Check the counter tbd_free to see if transmission is done. 1355 * No lock protection is needed here. 1356 * 1357 * Return B_TRUE if all pending packets have been transmitted; 1358 * Otherwise return B_FALSE; 1359 */ 1360 for (i = 0; i < TX_DRAIN_TIME; i++) { 1361 1362 done = B_TRUE; 1363 for (j = 0; j < igb->num_tx_rings; j++) { 1364 tx_ring = &igb->tx_rings[j]; 1365 done = done && 1366 (tx_ring->tbd_free == tx_ring->ring_size); 1367 } 1368 1369 if (done) 1370 break; 1371 1372 msec_delay(1); 1373 } 1374 1375 return (done); 1376 } 1377 1378 /* 1379 * igb_rx_drain - Wait for all rx buffers to be released by upper layer 1380 */ 1381 static boolean_t 1382 igb_rx_drain(igb_t *igb) 1383 { 1384 igb_rx_ring_t *rx_ring; 1385 boolean_t done; 1386 int i, j; 1387 1388 /* 1389 * Polling the rx free list to check if those rx buffers held by 1390 * the upper layer are released. 1391 * 1392 * Check the counter rcb_free to see if all pending buffers are 1393 * released. No lock protection is needed here. 1394 * 1395 * Return B_TRUE if all pending buffers have been released; 1396 * Otherwise return B_FALSE; 1397 */ 1398 for (i = 0; i < RX_DRAIN_TIME; i++) { 1399 1400 done = B_TRUE; 1401 for (j = 0; j < igb->num_rx_rings; j++) { 1402 rx_ring = &igb->rx_rings[j]; 1403 done = done && 1404 (rx_ring->rcb_free == rx_ring->free_list_size); 1405 } 1406 1407 if (done) 1408 break; 1409 1410 msec_delay(1); 1411 } 1412 1413 return (done); 1414 } 1415 1416 /* 1417 * igb_start - Start the driver/chipset 1418 */ 1419 int 1420 igb_start(igb_t *igb) 1421 { 1422 int i; 1423 1424 ASSERT(mutex_owned(&igb->gen_lock)); 1425 1426 for (i = 0; i < igb->num_rx_rings; i++) 1427 mutex_enter(&igb->rx_rings[i].rx_lock); 1428 for (i = 0; i < igb->num_tx_rings; i++) 1429 mutex_enter(&igb->tx_rings[i].tx_lock); 1430 1431 /* 1432 * Start the chipset hardware 1433 */ 1434 if (igb_chip_start(igb) != IGB_SUCCESS) { 1435 goto start_failure; 1436 } 1437 1438 /* 1439 * Setup the rx/tx rings 1440 */ 1441 igb_setup_rings(igb); 1442 1443 /* 1444 * Enable adapter interrupts 1445 * The interrupts must be enabled after the driver state is START 1446 */ 1447 igb_enable_adapter_interrupts(igb); 1448 1449 for (i = igb->num_tx_rings - 1; i >= 0; i--) 1450 mutex_exit(&igb->tx_rings[i].tx_lock); 1451 for (i = igb->num_rx_rings - 1; i >= 0; i--) 1452 mutex_exit(&igb->rx_rings[i].rx_lock); 1453 1454 return (IGB_SUCCESS); 1455 1456 start_failure: 1457 for (i = igb->num_tx_rings - 1; i >= 0; i--) 1458 mutex_exit(&igb->tx_rings[i].tx_lock); 1459 for (i = igb->num_rx_rings - 1; i >= 0; i--) 1460 mutex_exit(&igb->rx_rings[i].rx_lock); 1461 1462 return (IGB_FAILURE); 1463 } 1464 1465 /* 1466 * igb_stop - Stop the driver/chipset 1467 */ 1468 void 1469 igb_stop(igb_t *igb) 1470 { 1471 int i; 1472 1473 ASSERT(mutex_owned(&igb->gen_lock)); 1474 1475 /* 1476 * Disable the adapter interrupts 1477 */ 1478 igb_disable_adapter_interrupts(igb); 1479 1480 /* 1481 * Drain the pending tx packets 1482 */ 1483 (void) igb_tx_drain(igb); 1484 1485 for (i = 0; i < igb->num_rx_rings; i++) 1486 mutex_enter(&igb->rx_rings[i].rx_lock); 1487 for (i = 0; i < igb->num_tx_rings; i++) 1488 mutex_enter(&igb->tx_rings[i].tx_lock); 1489 1490 /* 1491 * Stop the chipset hardware 1492 */ 1493 igb_chip_stop(igb); 1494 1495 /* 1496 * Clean the pending tx data/resources 1497 */ 1498 igb_tx_clean(igb); 1499 1500 for (i = igb->num_tx_rings - 1; i >= 0; i--) 1501 mutex_exit(&igb->tx_rings[i].tx_lock); 1502 for (i = igb->num_rx_rings - 1; i >= 0; i--) 1503 mutex_exit(&igb->rx_rings[i].rx_lock); 1504 } 1505 1506 /* 1507 * igb_alloc_rings - Allocate memory space for rx/tx rings 1508 */ 1509 static int 1510 igb_alloc_rings(igb_t *igb) 1511 { 1512 /* 1513 * Allocate memory space for rx rings 1514 */ 1515 igb->rx_rings = kmem_zalloc( 1516 sizeof (igb_rx_ring_t) * igb->num_rx_rings, 1517 KM_NOSLEEP); 1518 1519 if (igb->rx_rings == NULL) { 1520 return (IGB_FAILURE); 1521 } 1522 1523 /* 1524 * Allocate memory space for tx rings 1525 */ 1526 igb->tx_rings = kmem_zalloc( 1527 sizeof (igb_tx_ring_t) * igb->num_tx_rings, 1528 KM_NOSLEEP); 1529 1530 if (igb->tx_rings == NULL) { 1531 kmem_free(igb->rx_rings, 1532 sizeof (igb_rx_ring_t) * igb->num_rx_rings); 1533 igb->rx_rings = NULL; 1534 return (IGB_FAILURE); 1535 } 1536 1537 return (IGB_SUCCESS); 1538 } 1539 1540 /* 1541 * igb_free_rings - Free the memory space of rx/tx rings. 1542 */ 1543 static void 1544 igb_free_rings(igb_t *igb) 1545 { 1546 if (igb->rx_rings != NULL) { 1547 kmem_free(igb->rx_rings, 1548 sizeof (igb_rx_ring_t) * igb->num_rx_rings); 1549 igb->rx_rings = NULL; 1550 } 1551 1552 if (igb->tx_rings != NULL) { 1553 kmem_free(igb->tx_rings, 1554 sizeof (igb_tx_ring_t) * igb->num_tx_rings); 1555 igb->tx_rings = NULL; 1556 } 1557 } 1558 1559 /* 1560 * igb_setup_rings - Setup rx/tx rings 1561 */ 1562 static void 1563 igb_setup_rings(igb_t *igb) 1564 { 1565 /* 1566 * Setup the rx/tx rings, including the following: 1567 * 1568 * 1. Setup the descriptor ring and the control block buffers; 1569 * 2. Initialize necessary registers for receive/transmit; 1570 * 3. Initialize software pointers/parameters for receive/transmit; 1571 */ 1572 igb_setup_rx(igb); 1573 1574 igb_setup_tx(igb); 1575 } 1576 1577 static void 1578 igb_setup_rx_ring(igb_rx_ring_t *rx_ring) 1579 { 1580 igb_t *igb = rx_ring->igb; 1581 struct e1000_hw *hw = &igb->hw; 1582 rx_control_block_t *rcb; 1583 union e1000_adv_rx_desc *rbd; 1584 uint32_t size; 1585 uint32_t buf_low; 1586 uint32_t buf_high; 1587 uint32_t reg_val; 1588 int i; 1589 1590 ASSERT(mutex_owned(&rx_ring->rx_lock)); 1591 ASSERT(mutex_owned(&igb->gen_lock)); 1592 1593 for (i = 0; i < igb->rx_ring_size; i++) { 1594 rcb = rx_ring->work_list[i]; 1595 rbd = &rx_ring->rbd_ring[i]; 1596 1597 rbd->read.pkt_addr = rcb->rx_buf.dma_address; 1598 rbd->read.hdr_addr = NULL; 1599 } 1600 1601 /* 1602 * Initialize the length register 1603 */ 1604 size = rx_ring->ring_size * sizeof (union e1000_adv_rx_desc); 1605 E1000_WRITE_REG(hw, E1000_RDLEN(rx_ring->index), size); 1606 1607 /* 1608 * Initialize the base address registers 1609 */ 1610 buf_low = (uint32_t)rx_ring->rbd_area.dma_address; 1611 buf_high = (uint32_t)(rx_ring->rbd_area.dma_address >> 32); 1612 E1000_WRITE_REG(hw, E1000_RDBAH(rx_ring->index), buf_high); 1613 E1000_WRITE_REG(hw, E1000_RDBAL(rx_ring->index), buf_low); 1614 1615 /* 1616 * Setup head & tail pointers 1617 */ 1618 E1000_WRITE_REG(hw, E1000_RDT(rx_ring->index), rx_ring->ring_size - 1); 1619 E1000_WRITE_REG(hw, E1000_RDH(rx_ring->index), 0); 1620 1621 rx_ring->rbd_next = 0; 1622 1623 /* 1624 * Note: Considering the case that the chipset is being reset 1625 * and there are still some buffers held by the upper layer, 1626 * we should not reset the values of rcb_head, rcb_tail and 1627 * rcb_free; 1628 */ 1629 if (igb->igb_state == IGB_UNKNOWN) { 1630 rx_ring->rcb_head = 0; 1631 rx_ring->rcb_tail = 0; 1632 rx_ring->rcb_free = rx_ring->free_list_size; 1633 } 1634 1635 /* 1636 * Setup the Receive Descriptor Control Register (RXDCTL) 1637 */ 1638 reg_val = E1000_READ_REG(hw, E1000_RXDCTL(rx_ring->index)); 1639 reg_val |= E1000_RXDCTL_QUEUE_ENABLE; 1640 reg_val &= 0xFFF00000; 1641 reg_val |= 16; /* pthresh */ 1642 reg_val |= 8 << 8; /* hthresh */ 1643 reg_val |= 1 << 16; /* wthresh */ 1644 E1000_WRITE_REG(hw, E1000_RXDCTL(rx_ring->index), reg_val); 1645 1646 /* 1647 * Setup the Split and Replication Receive Control Register. 1648 * Set the rx buffer size and the advanced descriptor type. 1649 */ 1650 reg_val = (igb->rx_buf_size >> E1000_SRRCTL_BSIZEPKT_SHIFT) | 1651 E1000_SRRCTL_DESCTYPE_ADV_ONEBUF; 1652 1653 E1000_WRITE_REG(hw, E1000_SRRCTL(rx_ring->index), reg_val); 1654 } 1655 1656 static void 1657 igb_setup_rx(igb_t *igb) 1658 { 1659 igb_rx_ring_t *rx_ring; 1660 struct e1000_hw *hw = &igb->hw; 1661 uint32_t reg_val; 1662 int i; 1663 1664 /* 1665 * Setup the Receive Control Register (RCTL), and ENABLE the 1666 * receiver. The initial configuration is to: Enable the receiver, 1667 * accept broadcasts, discard bad packets (and long packets), 1668 * disable VLAN filter checking, set the receive descriptor 1669 * minimum threshold size to 1/2, and the receive buffer size to 1670 * 2k. 1671 */ 1672 reg_val = E1000_RCTL_EN | /* Enable Receive Unit */ 1673 E1000_RCTL_BAM | /* Accept Broadcast Packets */ 1674 E1000_RCTL_LPE | /* Large Packet Enable bit */ 1675 (hw->mac.mc_filter_type << E1000_RCTL_MO_SHIFT) | 1676 E1000_RCTL_RDMTS_HALF | 1677 E1000_RCTL_SECRC | /* Strip Ethernet CRC */ 1678 E1000_RCTL_LBM_NO; /* Loopback Mode = none */ 1679 1680 E1000_WRITE_REG(hw, E1000_RCTL, reg_val); 1681 1682 /* 1683 * igb_setup_rx_ring must be called after configuring RCTL 1684 */ 1685 for (i = 0; i < igb->num_rx_rings; i++) { 1686 rx_ring = &igb->rx_rings[i]; 1687 igb_setup_rx_ring(rx_ring); 1688 } 1689 1690 /* 1691 * Setup the Rx Long Packet Max Length register 1692 */ 1693 E1000_WRITE_REG(hw, E1000_RLPML, igb->max_frame_size); 1694 1695 /* 1696 * Hardware checksum settings 1697 */ 1698 if (igb->rx_hcksum_enable) { 1699 reg_val = 1700 E1000_RXCSUM_TUOFL | /* TCP/UDP checksum */ 1701 E1000_RXCSUM_IPOFL; /* IP checksum */ 1702 1703 E1000_WRITE_REG(hw, E1000_RXCSUM, reg_val); 1704 } 1705 1706 /* 1707 * Setup RSS for multiple receive queues 1708 */ 1709 if (igb->num_rx_rings > 1) 1710 igb_setup_rss(igb); 1711 } 1712 1713 static void 1714 igb_setup_tx_ring(igb_tx_ring_t *tx_ring) 1715 { 1716 igb_t *igb = tx_ring->igb; 1717 struct e1000_hw *hw = &igb->hw; 1718 uint32_t size; 1719 uint32_t buf_low; 1720 uint32_t buf_high; 1721 uint32_t reg_val; 1722 1723 ASSERT(mutex_owned(&tx_ring->tx_lock)); 1724 ASSERT(mutex_owned(&igb->gen_lock)); 1725 1726 /* 1727 * Initialize the length register 1728 */ 1729 size = tx_ring->ring_size * sizeof (union e1000_adv_tx_desc); 1730 E1000_WRITE_REG(hw, E1000_TDLEN(tx_ring->index), size); 1731 1732 /* 1733 * Initialize the base address registers 1734 */ 1735 buf_low = (uint32_t)tx_ring->tbd_area.dma_address; 1736 buf_high = (uint32_t)(tx_ring->tbd_area.dma_address >> 32); 1737 E1000_WRITE_REG(hw, E1000_TDBAL(tx_ring->index), buf_low); 1738 E1000_WRITE_REG(hw, E1000_TDBAH(tx_ring->index), buf_high); 1739 1740 /* 1741 * Setup head & tail pointers 1742 */ 1743 E1000_WRITE_REG(hw, E1000_TDH(tx_ring->index), 0); 1744 E1000_WRITE_REG(hw, E1000_TDT(tx_ring->index), 0); 1745 1746 /* 1747 * Setup head write-back 1748 */ 1749 if (igb->tx_head_wb_enable) { 1750 /* 1751 * The memory of the head write-back is allocated using 1752 * the extra tbd beyond the tail of the tbd ring. 1753 */ 1754 tx_ring->tbd_head_wb = (uint32_t *) 1755 ((uintptr_t)tx_ring->tbd_area.address + size); 1756 1757 buf_low = (uint32_t) 1758 (tx_ring->tbd_area.dma_address + size); 1759 buf_high = (uint32_t) 1760 ((tx_ring->tbd_area.dma_address + size) >> 32); 1761 1762 /* Set the head write-back enable bit */ 1763 buf_low |= E1000_TX_HEAD_WB_ENABLE; 1764 1765 E1000_WRITE_REG(hw, E1000_TDWBAL(tx_ring->index), buf_low); 1766 E1000_WRITE_REG(hw, E1000_TDWBAH(tx_ring->index), buf_high); 1767 1768 /* 1769 * Turn off relaxed ordering for head write back or it will 1770 * cause problems with the tx recycling 1771 */ 1772 reg_val = E1000_READ_REG(hw, 1773 E1000_DCA_TXCTRL(tx_ring->index)); 1774 reg_val &= ~E1000_DCA_TXCTRL_TX_WB_RO_EN; 1775 E1000_WRITE_REG(hw, 1776 E1000_DCA_TXCTRL(tx_ring->index), reg_val); 1777 } else { 1778 tx_ring->tbd_head_wb = NULL; 1779 } 1780 1781 tx_ring->tbd_head = 0; 1782 tx_ring->tbd_tail = 0; 1783 tx_ring->tbd_free = tx_ring->ring_size; 1784 1785 /* 1786 * Note: Considering the case that the chipset is being reset, 1787 * and there are still some buffers held by the upper layer, 1788 * we should not reset the values of tcb_head, tcb_tail. 1789 */ 1790 if (igb->igb_state == IGB_UNKNOWN) { 1791 tx_ring->tcb_head = 0; 1792 tx_ring->tcb_tail = 0; 1793 tx_ring->tcb_free = tx_ring->free_list_size; 1794 } else { 1795 ASSERT(tx_ring->tcb_free == tx_ring->free_list_size); 1796 } 1797 1798 /* 1799 * Initialize hardware checksum offload settings 1800 */ 1801 tx_ring->hcksum_context.hcksum_flags = 0; 1802 tx_ring->hcksum_context.ip_hdr_len = 0; 1803 tx_ring->hcksum_context.mac_hdr_len = 0; 1804 tx_ring->hcksum_context.l4_proto = 0; 1805 } 1806 1807 static void 1808 igb_setup_tx(igb_t *igb) 1809 { 1810 igb_tx_ring_t *tx_ring; 1811 struct e1000_hw *hw = &igb->hw; 1812 uint32_t reg_val; 1813 int i; 1814 1815 for (i = 0; i < igb->num_tx_rings; i++) { 1816 tx_ring = &igb->tx_rings[i]; 1817 igb_setup_tx_ring(tx_ring); 1818 } 1819 1820 /* 1821 * Setup the Transmit Control Register (TCTL) 1822 */ 1823 reg_val = E1000_TCTL_PSP | E1000_TCTL_EN | 1824 (E1000_COLLISION_THRESHOLD << E1000_CT_SHIFT) | 1825 (E1000_COLLISION_DISTANCE << E1000_COLD_SHIFT) | 1826 E1000_TCTL_RTLC; 1827 1828 /* Enable the MULR bit */ 1829 if (hw->bus.type == e1000_bus_type_pci_express) 1830 reg_val |= E1000_TCTL_MULR; 1831 1832 E1000_WRITE_REG(hw, E1000_TCTL, reg_val); 1833 1834 /* 1835 * Set the default values for the Tx Inter Packet Gap timer 1836 */ 1837 if (hw->phy.media_type == e1000_media_type_fiber) 1838 reg_val = DEFAULT_82543_TIPG_IPGT_FIBER; 1839 else 1840 reg_val = DEFAULT_82543_TIPG_IPGT_COPPER; 1841 reg_val |= 1842 DEFAULT_82543_TIPG_IPGR1 << E1000_TIPG_IPGR1_SHIFT; 1843 reg_val |= 1844 DEFAULT_82543_TIPG_IPGR2 << E1000_TIPG_IPGR2_SHIFT; 1845 1846 E1000_WRITE_REG(hw, E1000_TIPG, reg_val); 1847 } 1848 1849 /* 1850 * igb_setup_rss - Setup receive-side scaling feature 1851 */ 1852 static void 1853 igb_setup_rss(igb_t *igb) 1854 { 1855 struct e1000_hw *hw = &igb->hw; 1856 uint32_t i, mrqc, rxcsum; 1857 int shift; 1858 uint32_t random; 1859 union e1000_reta { 1860 uint32_t dword; 1861 uint8_t bytes[4]; 1862 } reta; 1863 1864 /* Setup the Redirection Table */ 1865 shift = 6; 1866 for (i = 0; i < (32 * 4); i++) { 1867 reta.bytes[i & 3] = (i % igb->num_rx_rings) << shift; 1868 if ((i & 3) == 3) { 1869 E1000_WRITE_REG(hw, 1870 (E1000_RETA(0) + (i & ~3)), reta.dword); 1871 } 1872 } 1873 1874 /* Fill out hash function seeds */ 1875 for (i = 0; i < 10; i++) { 1876 (void) random_get_pseudo_bytes((uint8_t *)&random, 1877 sizeof (uint32_t)); 1878 E1000_WRITE_REG(hw, E1000_RSSRK(i), random); 1879 } 1880 1881 /* Setup the Multiple Receive Queue Control register */ 1882 mrqc = E1000_MRQC_ENABLE_RSS_4Q; 1883 mrqc |= (E1000_MRQC_RSS_FIELD_IPV4 | 1884 E1000_MRQC_RSS_FIELD_IPV4_TCP | 1885 E1000_MRQC_RSS_FIELD_IPV6 | 1886 E1000_MRQC_RSS_FIELD_IPV6_TCP | 1887 E1000_MRQC_RSS_FIELD_IPV4_UDP | 1888 E1000_MRQC_RSS_FIELD_IPV6_UDP | 1889 E1000_MRQC_RSS_FIELD_IPV6_UDP_EX | 1890 E1000_MRQC_RSS_FIELD_IPV6_TCP_EX); 1891 1892 E1000_WRITE_REG(hw, E1000_MRQC, mrqc); 1893 1894 /* 1895 * Disable Packet Checksum to enable RSS for multiple receive queues. 1896 * 1897 * The Packet Checksum is not ethernet CRC. It is another kind of 1898 * checksum offloading provided by the 82575 chipset besides the IP 1899 * header checksum offloading and the TCP/UDP checksum offloading. 1900 * The Packet Checksum is by default computed over the entire packet 1901 * from the first byte of the DA through the last byte of the CRC, 1902 * including the Ethernet and IP headers. 1903 * 1904 * It is a hardware limitation that Packet Checksum is mutually 1905 * exclusive with RSS. 1906 */ 1907 rxcsum = E1000_READ_REG(hw, E1000_RXCSUM); 1908 rxcsum |= E1000_RXCSUM_PCSD; 1909 E1000_WRITE_REG(hw, E1000_RXCSUM, rxcsum); 1910 } 1911 1912 /* 1913 * igb_init_unicst - Initialize the unicast addresses 1914 */ 1915 static void 1916 igb_init_unicst(igb_t *igb) 1917 { 1918 struct e1000_hw *hw = &igb->hw; 1919 int slot; 1920 1921 /* 1922 * Here we should consider two situations: 1923 * 1924 * 1. Chipset is initialized the first time 1925 * Initialize the multiple unicast addresses, and 1926 * save the default mac address. 1927 * 1928 * 2. Chipset is reset 1929 * Recover the multiple unicast addresses from the 1930 * software data structure to the RAR registers. 1931 */ 1932 if (!igb->unicst_init) { 1933 /* Initialize the multiple unicast addresses */ 1934 igb->unicst_total = MAX_NUM_UNICAST_ADDRESSES; 1935 1936 igb->unicst_avail = igb->unicst_total - 1; 1937 1938 /* Store the default mac address */ 1939 e1000_rar_set(hw, hw->mac.addr, 0); 1940 1941 bcopy(hw->mac.addr, igb->unicst_addr[0].mac.addr, 1942 ETHERADDRL); 1943 igb->unicst_addr[0].mac.set = 1; 1944 1945 for (slot = 1; slot < igb->unicst_total; slot++) 1946 igb->unicst_addr[slot].mac.set = 0; 1947 1948 igb->unicst_init = B_TRUE; 1949 } else { 1950 /* Recover the default mac address */ 1951 bcopy(igb->unicst_addr[0].mac.addr, hw->mac.addr, 1952 ETHERADDRL); 1953 1954 /* Store the default mac address */ 1955 e1000_rar_set(hw, hw->mac.addr, 0); 1956 1957 /* Re-configure the RAR registers */ 1958 for (slot = 1; slot < igb->unicst_total; slot++) 1959 e1000_rar_set(hw, 1960 igb->unicst_addr[slot].mac.addr, slot); 1961 } 1962 } 1963 1964 /* 1965 * igb_unicst_set - Set the unicast address to the specified slot 1966 */ 1967 int 1968 igb_unicst_set(igb_t *igb, const uint8_t *mac_addr, 1969 mac_addr_slot_t slot) 1970 { 1971 struct e1000_hw *hw = &igb->hw; 1972 1973 ASSERT(mutex_owned(&igb->gen_lock)); 1974 1975 /* 1976 * Save the unicast address in the software data structure 1977 */ 1978 bcopy(mac_addr, igb->unicst_addr[slot].mac.addr, ETHERADDRL); 1979 1980 /* 1981 * Set the unicast address to the RAR register 1982 */ 1983 e1000_rar_set(hw, (uint8_t *)mac_addr, slot); 1984 1985 return (0); 1986 } 1987 1988 /* 1989 * igb_multicst_add - Add a multicst address 1990 */ 1991 int 1992 igb_multicst_add(igb_t *igb, const uint8_t *multiaddr) 1993 { 1994 ASSERT(mutex_owned(&igb->gen_lock)); 1995 1996 if ((multiaddr[0] & 01) == 0) { 1997 return (EINVAL); 1998 } 1999 2000 if (igb->mcast_count >= MAX_NUM_MULTICAST_ADDRESSES) { 2001 return (ENOENT); 2002 } 2003 2004 bcopy(multiaddr, 2005 &igb->mcast_table[igb->mcast_count], ETHERADDRL); 2006 igb->mcast_count++; 2007 2008 /* 2009 * Update the multicast table in the hardware 2010 */ 2011 igb_setup_multicst(igb); 2012 2013 return (0); 2014 } 2015 2016 /* 2017 * igb_multicst_remove - Remove a multicst address 2018 */ 2019 int 2020 igb_multicst_remove(igb_t *igb, const uint8_t *multiaddr) 2021 { 2022 int i; 2023 2024 ASSERT(mutex_owned(&igb->gen_lock)); 2025 2026 for (i = 0; i < igb->mcast_count; i++) { 2027 if (bcmp(multiaddr, &igb->mcast_table[i], 2028 ETHERADDRL) == 0) { 2029 for (i++; i < igb->mcast_count; i++) { 2030 igb->mcast_table[i - 1] = 2031 igb->mcast_table[i]; 2032 } 2033 igb->mcast_count--; 2034 break; 2035 } 2036 } 2037 2038 /* 2039 * Update the multicast table in the hardware 2040 */ 2041 igb_setup_multicst(igb); 2042 2043 return (0); 2044 } 2045 2046 /* 2047 * igb_setup_multicast - setup multicast data structures 2048 * 2049 * This routine initializes all of the multicast related structures 2050 * and save them in the hardware registers. 2051 */ 2052 static void 2053 igb_setup_multicst(igb_t *igb) 2054 { 2055 uint8_t *mc_addr_list; 2056 uint32_t mc_addr_count; 2057 struct e1000_hw *hw = &igb->hw; 2058 2059 ASSERT(mutex_owned(&igb->gen_lock)); 2060 2061 ASSERT(igb->mcast_count <= MAX_NUM_MULTICAST_ADDRESSES); 2062 2063 mc_addr_list = (uint8_t *)igb->mcast_table; 2064 mc_addr_count = igb->mcast_count; 2065 2066 /* 2067 * Update the multicase addresses to the MTA registers 2068 */ 2069 e1000_update_mc_addr_list(hw, mc_addr_list, mc_addr_count, 2070 igb->unicst_total, hw->mac.rar_entry_count); 2071 } 2072 2073 /* 2074 * igb_get_conf - Get driver configurations set in driver.conf 2075 * 2076 * This routine gets user-configured values out of the configuration 2077 * file igb.conf. 2078 * 2079 * For each configurable value, there is a minimum, a maximum, and a 2080 * default. 2081 * If user does not configure a value, use the default. 2082 * If user configures below the minimum, use the minumum. 2083 * If user configures above the maximum, use the maxumum. 2084 */ 2085 static void 2086 igb_get_conf(igb_t *igb) 2087 { 2088 struct e1000_hw *hw = &igb->hw; 2089 uint32_t default_mtu; 2090 uint32_t flow_control; 2091 2092 /* 2093 * igb driver supports the following user configurations: 2094 * 2095 * Link configurations: 2096 * adv_autoneg_cap 2097 * adv_1000fdx_cap 2098 * adv_100fdx_cap 2099 * adv_100hdx_cap 2100 * adv_10fdx_cap 2101 * adv_10hdx_cap 2102 * Note: 1000hdx is not supported. 2103 * 2104 * Jumbo frame configuration: 2105 * default_mtu 2106 * 2107 * Ethernet flow control configuration: 2108 * flow_control 2109 * 2110 * Multiple rings configurations: 2111 * tx_queue_number 2112 * tx_ring_size 2113 * rx_queue_number 2114 * rx_ring_size 2115 * 2116 * Call igb_get_prop() to get the value for a specific 2117 * configuration parameter. 2118 */ 2119 2120 /* 2121 * Link configurations 2122 */ 2123 igb->param_adv_autoneg_cap = igb_get_prop(igb, 2124 PROP_ADV_AUTONEG_CAP, 0, 1, 1); 2125 igb->param_adv_1000fdx_cap = igb_get_prop(igb, 2126 PROP_ADV_1000FDX_CAP, 0, 1, 1); 2127 igb->param_adv_100fdx_cap = igb_get_prop(igb, 2128 PROP_ADV_100FDX_CAP, 0, 1, 1); 2129 igb->param_adv_100hdx_cap = igb_get_prop(igb, 2130 PROP_ADV_100HDX_CAP, 0, 1, 1); 2131 igb->param_adv_10fdx_cap = igb_get_prop(igb, 2132 PROP_ADV_10FDX_CAP, 0, 1, 1); 2133 igb->param_adv_10hdx_cap = igb_get_prop(igb, 2134 PROP_ADV_10HDX_CAP, 0, 1, 1); 2135 2136 /* 2137 * Jumbo frame configurations 2138 */ 2139 default_mtu = igb_get_prop(igb, PROP_DEFAULT_MTU, 2140 MIN_MTU, MAX_MTU, DEFAULT_MTU); 2141 2142 igb->max_frame_size = default_mtu + 2143 sizeof (struct ether_vlan_header) + ETHERFCSL; 2144 2145 /* 2146 * Ethernet flow control configuration 2147 */ 2148 flow_control = igb_get_prop(igb, PROP_FLOW_CONTROL, 2149 e1000_fc_none, 4, e1000_fc_full); 2150 if (flow_control == 4) 2151 flow_control = e1000_fc_default; 2152 2153 hw->fc.type = flow_control; 2154 2155 /* 2156 * Multiple rings configurations 2157 */ 2158 igb->num_tx_rings = igb_get_prop(igb, PROP_TX_QUEUE_NUM, 2159 MIN_TX_QUEUE_NUM, MAX_TX_QUEUE_NUM, DEFAULT_TX_QUEUE_NUM); 2160 igb->tx_ring_size = igb_get_prop(igb, PROP_TX_RING_SIZE, 2161 MIN_TX_RING_SIZE, MAX_TX_RING_SIZE, DEFAULT_TX_RING_SIZE); 2162 2163 igb->num_rx_rings = igb_get_prop(igb, PROP_RX_QUEUE_NUM, 2164 MIN_RX_QUEUE_NUM, MAX_RX_QUEUE_NUM, DEFAULT_RX_QUEUE_NUM); 2165 igb->rx_ring_size = igb_get_prop(igb, PROP_RX_RING_SIZE, 2166 MIN_RX_RING_SIZE, MAX_RX_RING_SIZE, DEFAULT_RX_RING_SIZE); 2167 2168 /* 2169 * Tunable used to force an interrupt type. The only use is 2170 * for testing of the lesser interrupt types. 2171 * 0 = don't force interrupt type 2172 * 1 = force interrupt type MSIX 2173 * 2 = force interrupt type MSI 2174 * 3 = force interrupt type Legacy 2175 */ 2176 igb->intr_force = igb_get_prop(igb, PROP_INTR_FORCE, 2177 IGB_INTR_NONE, IGB_INTR_LEGACY, IGB_INTR_NONE); 2178 2179 igb->tx_hcksum_enable = igb_get_prop(igb, PROP_TX_HCKSUM_ENABLE, 2180 0, 1, 1); 2181 igb->rx_hcksum_enable = igb_get_prop(igb, PROP_RX_HCKSUM_ENABLE, 2182 0, 1, 1); 2183 igb->lso_enable = igb_get_prop(igb, PROP_LSO_ENABLE, 2184 0, 1, 0); 2185 igb->tx_head_wb_enable = igb_get_prop(igb, PROP_TX_HEAD_WB_ENABLE, 2186 0, 1, 1); 2187 2188 igb->tx_copy_thresh = igb_get_prop(igb, PROP_TX_COPY_THRESHOLD, 2189 MIN_TX_COPY_THRESHOLD, MAX_TX_COPY_THRESHOLD, 2190 DEFAULT_TX_COPY_THRESHOLD); 2191 igb->tx_recycle_thresh = igb_get_prop(igb, PROP_TX_RECYCLE_THRESHOLD, 2192 MIN_TX_RECYCLE_THRESHOLD, MAX_TX_RECYCLE_THRESHOLD, 2193 DEFAULT_TX_RECYCLE_THRESHOLD); 2194 igb->tx_overload_thresh = igb_get_prop(igb, PROP_TX_OVERLOAD_THRESHOLD, 2195 MIN_TX_OVERLOAD_THRESHOLD, MAX_TX_OVERLOAD_THRESHOLD, 2196 DEFAULT_TX_OVERLOAD_THRESHOLD); 2197 igb->tx_resched_thresh = igb_get_prop(igb, PROP_TX_RESCHED_THRESHOLD, 2198 MIN_TX_RESCHED_THRESHOLD, MAX_TX_RESCHED_THRESHOLD, 2199 DEFAULT_TX_RESCHED_THRESHOLD); 2200 2201 igb->rx_copy_thresh = igb_get_prop(igb, PROP_RX_COPY_THRESHOLD, 2202 MIN_RX_COPY_THRESHOLD, MAX_RX_COPY_THRESHOLD, 2203 DEFAULT_RX_COPY_THRESHOLD); 2204 igb->rx_limit_per_intr = igb_get_prop(igb, PROP_RX_LIMIT_PER_INTR, 2205 MIN_RX_LIMIT_PER_INTR, MAX_RX_LIMIT_PER_INTR, 2206 DEFAULT_RX_LIMIT_PER_INTR); 2207 2208 igb->intr_throttling[0] = igb_get_prop(igb, PROP_INTR_THROTTLING, 2209 MIN_INTR_THROTTLING, MAX_INTR_THROTTLING, 2210 DEFAULT_INTR_THROTTLING); 2211 } 2212 2213 /* 2214 * igb_get_prop - Get a property value out of the configuration file igb.conf 2215 * 2216 * Caller provides the name of the property, a default value, a minimum 2217 * value, and a maximum value. 2218 * 2219 * Return configured value of the property, with default, minimum and 2220 * maximum properly applied. 2221 */ 2222 static int 2223 igb_get_prop(igb_t *igb, 2224 char *propname, /* name of the property */ 2225 int minval, /* minimum acceptable value */ 2226 int maxval, /* maximim acceptable value */ 2227 int defval) /* default value */ 2228 { 2229 int value; 2230 2231 /* 2232 * Call ddi_prop_get_int() to read the conf settings 2233 */ 2234 value = ddi_prop_get_int(DDI_DEV_T_ANY, igb->dip, 2235 DDI_PROP_DONTPASS, propname, defval); 2236 2237 if (value > maxval) 2238 value = maxval; 2239 2240 if (value < minval) 2241 value = minval; 2242 2243 return (value); 2244 } 2245 2246 /* 2247 * igb_setup_link - Using the link properties to setup the link 2248 */ 2249 int 2250 igb_setup_link(igb_t *igb, boolean_t setup_hw) 2251 { 2252 struct e1000_mac_info *mac; 2253 struct e1000_phy_info *phy; 2254 boolean_t invalid; 2255 2256 mac = &igb->hw.mac; 2257 phy = &igb->hw.phy; 2258 invalid = B_FALSE; 2259 2260 if (igb->param_adv_autoneg_cap == 1) { 2261 mac->autoneg = B_TRUE; 2262 phy->autoneg_advertised = 0; 2263 2264 /* 2265 * 1000hdx is not supported for autonegotiation 2266 */ 2267 if (igb->param_adv_1000fdx_cap == 1) 2268 phy->autoneg_advertised |= ADVERTISE_1000_FULL; 2269 2270 if (igb->param_adv_100fdx_cap == 1) 2271 phy->autoneg_advertised |= ADVERTISE_100_FULL; 2272 2273 if (igb->param_adv_100hdx_cap == 1) 2274 phy->autoneg_advertised |= ADVERTISE_100_HALF; 2275 2276 if (igb->param_adv_10fdx_cap == 1) 2277 phy->autoneg_advertised |= ADVERTISE_10_FULL; 2278 2279 if (igb->param_adv_10hdx_cap == 1) 2280 phy->autoneg_advertised |= ADVERTISE_10_HALF; 2281 2282 if (phy->autoneg_advertised == 0) 2283 invalid = B_TRUE; 2284 } else { 2285 mac->autoneg = B_FALSE; 2286 2287 /* 2288 * 1000fdx and 1000hdx are not supported for forced link 2289 */ 2290 if (igb->param_adv_100fdx_cap == 1) 2291 mac->forced_speed_duplex = ADVERTISE_100_FULL; 2292 else if (igb->param_adv_100hdx_cap == 1) 2293 mac->forced_speed_duplex = ADVERTISE_100_HALF; 2294 else if (igb->param_adv_10fdx_cap == 1) 2295 mac->forced_speed_duplex = ADVERTISE_10_FULL; 2296 else if (igb->param_adv_10hdx_cap == 1) 2297 mac->forced_speed_duplex = ADVERTISE_10_HALF; 2298 else 2299 invalid = B_TRUE; 2300 } 2301 2302 if (invalid) { 2303 igb_notice(igb, "Invalid link settings. Setup link to " 2304 "autonegotiation with full link capabilities."); 2305 mac->autoneg = B_TRUE; 2306 phy->autoneg_advertised = ADVERTISE_1000_FULL | 2307 ADVERTISE_100_FULL | ADVERTISE_100_HALF | 2308 ADVERTISE_10_FULL | ADVERTISE_10_HALF; 2309 } 2310 2311 if (setup_hw) { 2312 if (e1000_setup_link(&igb->hw) != E1000_SUCCESS) 2313 return (IGB_FAILURE); 2314 } 2315 2316 return (IGB_SUCCESS); 2317 } 2318 2319 2320 /* 2321 * igb_is_link_up - Check if the link is up 2322 */ 2323 static boolean_t 2324 igb_is_link_up(igb_t *igb) 2325 { 2326 struct e1000_hw *hw = &igb->hw; 2327 boolean_t link_up; 2328 2329 ASSERT(mutex_owned(&igb->gen_lock)); 2330 2331 (void) e1000_check_for_link(hw); 2332 2333 if ((E1000_READ_REG(hw, E1000_STATUS) & E1000_STATUS_LU) || 2334 ((hw->phy.media_type == e1000_media_type_internal_serdes) && 2335 (hw->mac.serdes_has_link))) { 2336 link_up = B_TRUE; 2337 } else { 2338 link_up = B_FALSE; 2339 } 2340 2341 return (link_up); 2342 } 2343 2344 /* 2345 * igb_link_check - Link status processing 2346 */ 2347 static boolean_t 2348 igb_link_check(igb_t *igb) 2349 { 2350 struct e1000_hw *hw = &igb->hw; 2351 uint16_t speed = 0, duplex = 0; 2352 boolean_t link_changed = B_FALSE; 2353 2354 ASSERT(mutex_owned(&igb->gen_lock)); 2355 2356 if (igb_is_link_up(igb)) { 2357 /* 2358 * The Link is up, check whether it was marked as down earlier 2359 */ 2360 if (igb->link_state != LINK_STATE_UP) { 2361 (void) e1000_get_speed_and_duplex(hw, &speed, &duplex); 2362 igb->link_speed = speed; 2363 igb->link_duplex = duplex; 2364 igb->link_state = LINK_STATE_UP; 2365 igb->link_down_timeout = 0; 2366 link_changed = B_TRUE; 2367 } 2368 } else { 2369 if (igb->link_state != LINK_STATE_DOWN) { 2370 igb->link_speed = 0; 2371 igb->link_duplex = 0; 2372 igb->link_state = LINK_STATE_DOWN; 2373 link_changed = B_TRUE; 2374 } 2375 2376 if (igb->igb_state & IGB_STARTED) { 2377 if (igb->link_down_timeout < MAX_LINK_DOWN_TIMEOUT) { 2378 igb->link_down_timeout++; 2379 } else if (igb->link_down_timeout == 2380 MAX_LINK_DOWN_TIMEOUT) { 2381 igb_tx_clean(igb); 2382 igb->link_down_timeout++; 2383 } 2384 } 2385 } 2386 2387 return (link_changed); 2388 } 2389 2390 /* 2391 * igb_local_timer - driver watchdog function 2392 * 2393 * This function will handle the transmit stall check, link status check and 2394 * other routines. 2395 */ 2396 static void 2397 igb_local_timer(void *arg) 2398 { 2399 igb_t *igb = (igb_t *)arg; 2400 struct e1000_hw *hw = &igb->hw; 2401 boolean_t link_changed; 2402 2403 if (igb_stall_check(igb)) { 2404 igb->reset_count++; 2405 (void) igb_reset(igb); 2406 } 2407 2408 mutex_enter(&igb->gen_lock); 2409 link_changed = igb_link_check(igb); 2410 mutex_exit(&igb->gen_lock); 2411 2412 if (link_changed) 2413 mac_link_update(igb->mac_hdl, igb->link_state); 2414 2415 /* 2416 * Set Timer Interrupts 2417 */ 2418 if (igb->intr_type != DDI_INTR_TYPE_MSIX) 2419 E1000_WRITE_REG(hw, E1000_ICS, E1000_IMS_RXT0); 2420 2421 igb_restart_watchdog_timer(igb); 2422 } 2423 2424 /* 2425 * igb_stall_check - check for transmit stall 2426 * 2427 * This function checks if the adapter is stalled (in transmit). 2428 * 2429 * It is called each time the watchdog timeout is invoked. 2430 * If the transmit descriptor reclaim continuously fails, 2431 * the watchdog value will increment by 1. If the watchdog 2432 * value exceeds the threshold, the igb is assumed to 2433 * have stalled and need to be reset. 2434 */ 2435 static boolean_t 2436 igb_stall_check(igb_t *igb) 2437 { 2438 igb_tx_ring_t *tx_ring; 2439 boolean_t result; 2440 int i; 2441 2442 if (igb->link_state != LINK_STATE_UP) 2443 return (B_FALSE); 2444 2445 /* 2446 * If any tx ring is stalled, we'll reset the chipset 2447 */ 2448 result = B_FALSE; 2449 for (i = 0; i < igb->num_tx_rings; i++) { 2450 tx_ring = &igb->tx_rings[i]; 2451 2452 if (tx_ring->recycle_fail > 0) 2453 tx_ring->stall_watchdog++; 2454 else 2455 tx_ring->stall_watchdog = 0; 2456 2457 if (tx_ring->stall_watchdog >= STALL_WATCHDOG_TIMEOUT) { 2458 result = B_TRUE; 2459 break; 2460 } 2461 } 2462 2463 if (result) { 2464 tx_ring->stall_watchdog = 0; 2465 tx_ring->recycle_fail = 0; 2466 } 2467 2468 return (result); 2469 } 2470 2471 2472 /* 2473 * is_valid_mac_addr - Check if the mac address is valid 2474 */ 2475 static boolean_t 2476 is_valid_mac_addr(uint8_t *mac_addr) 2477 { 2478 const uint8_t addr_test1[6] = { 0, 0, 0, 0, 0, 0 }; 2479 const uint8_t addr_test2[6] = 2480 { 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF }; 2481 2482 if (!(bcmp(addr_test1, mac_addr, ETHERADDRL)) || 2483 !(bcmp(addr_test2, mac_addr, ETHERADDRL))) 2484 return (B_FALSE); 2485 2486 return (B_TRUE); 2487 } 2488 2489 static boolean_t 2490 igb_find_mac_address(igb_t *igb) 2491 { 2492 struct e1000_hw *hw = &igb->hw; 2493 #ifdef __sparc 2494 uchar_t *bytes; 2495 struct ether_addr sysaddr; 2496 uint_t nelts; 2497 int err; 2498 boolean_t found = B_FALSE; 2499 2500 /* 2501 * The "vendor's factory-set address" may already have 2502 * been extracted from the chip, but if the property 2503 * "local-mac-address" is set we use that instead. 2504 * 2505 * We check whether it looks like an array of 6 2506 * bytes (which it should, if OBP set it). If we can't 2507 * make sense of it this way, we'll ignore it. 2508 */ 2509 err = ddi_prop_lookup_byte_array(DDI_DEV_T_ANY, igb->dip, 2510 DDI_PROP_DONTPASS, "local-mac-address", &bytes, &nelts); 2511 if (err == DDI_PROP_SUCCESS) { 2512 if (nelts == ETHERADDRL) { 2513 while (nelts--) 2514 hw->mac.addr[nelts] = bytes[nelts]; 2515 found = B_TRUE; 2516 } 2517 ddi_prop_free(bytes); 2518 } 2519 2520 /* 2521 * Look up the OBP property "local-mac-address?". If the user has set 2522 * 'local-mac-address? = false', use "the system address" instead. 2523 */ 2524 if (ddi_prop_lookup_byte_array(DDI_DEV_T_ANY, igb->dip, 0, 2525 "local-mac-address?", &bytes, &nelts) == DDI_PROP_SUCCESS) { 2526 if (strncmp("false", (caddr_t)bytes, (size_t)nelts) == 0) { 2527 if (localetheraddr(NULL, &sysaddr) != 0) { 2528 bcopy(&sysaddr, hw->mac.addr, ETHERADDRL); 2529 found = B_TRUE; 2530 } 2531 } 2532 ddi_prop_free(bytes); 2533 } 2534 2535 /* 2536 * Finally(!), if there's a valid "mac-address" property (created 2537 * if we netbooted from this interface), we must use this instead 2538 * of any of the above to ensure that the NFS/install server doesn't 2539 * get confused by the address changing as Solaris takes over! 2540 */ 2541 err = ddi_prop_lookup_byte_array(DDI_DEV_T_ANY, igb->dip, 2542 DDI_PROP_DONTPASS, "mac-address", &bytes, &nelts); 2543 if (err == DDI_PROP_SUCCESS) { 2544 if (nelts == ETHERADDRL) { 2545 while (nelts--) 2546 hw->mac.addr[nelts] = bytes[nelts]; 2547 found = B_TRUE; 2548 } 2549 ddi_prop_free(bytes); 2550 } 2551 2552 if (found) { 2553 bcopy(hw->mac.addr, hw->mac.perm_addr, ETHERADDRL); 2554 return (B_TRUE); 2555 } 2556 #endif 2557 2558 /* 2559 * Read the device MAC address from the EEPROM 2560 */ 2561 if (e1000_read_mac_addr(hw) != E1000_SUCCESS) 2562 return (B_FALSE); 2563 2564 return (B_TRUE); 2565 } 2566 2567 #pragma inline(igb_arm_watchdog_timer) 2568 2569 static void 2570 igb_arm_watchdog_timer(igb_t *igb) 2571 { 2572 /* 2573 * Fire a watchdog timer 2574 */ 2575 igb->watchdog_tid = 2576 timeout(igb_local_timer, 2577 (void *)igb, 1 * drv_usectohz(1000000)); 2578 2579 } 2580 2581 /* 2582 * igb_enable_watchdog_timer - Enable and start the driver watchdog timer 2583 */ 2584 void 2585 igb_enable_watchdog_timer(igb_t *igb) 2586 { 2587 mutex_enter(&igb->watchdog_lock); 2588 2589 if (!igb->watchdog_enable) { 2590 igb->watchdog_enable = B_TRUE; 2591 igb->watchdog_start = B_TRUE; 2592 igb_arm_watchdog_timer(igb); 2593 } 2594 2595 mutex_exit(&igb->watchdog_lock); 2596 2597 } 2598 2599 /* 2600 * igb_disable_watchdog_timer - Disable and stop the driver watchdog timer 2601 */ 2602 void 2603 igb_disable_watchdog_timer(igb_t *igb) 2604 { 2605 timeout_id_t tid; 2606 2607 mutex_enter(&igb->watchdog_lock); 2608 2609 igb->watchdog_enable = B_FALSE; 2610 igb->watchdog_start = B_FALSE; 2611 tid = igb->watchdog_tid; 2612 igb->watchdog_tid = 0; 2613 2614 mutex_exit(&igb->watchdog_lock); 2615 2616 if (tid != 0) 2617 (void) untimeout(tid); 2618 2619 } 2620 2621 /* 2622 * igb_start_watchdog_timer - Start the driver watchdog timer 2623 */ 2624 static void 2625 igb_start_watchdog_timer(igb_t *igb) 2626 { 2627 mutex_enter(&igb->watchdog_lock); 2628 2629 if (igb->watchdog_enable) { 2630 if (!igb->watchdog_start) { 2631 igb->watchdog_start = B_TRUE; 2632 igb_arm_watchdog_timer(igb); 2633 } 2634 } 2635 2636 mutex_exit(&igb->watchdog_lock); 2637 } 2638 2639 /* 2640 * igb_restart_watchdog_timer - Restart the driver watchdog timer 2641 */ 2642 static void 2643 igb_restart_watchdog_timer(igb_t *igb) 2644 { 2645 mutex_enter(&igb->watchdog_lock); 2646 2647 if (igb->watchdog_start) 2648 igb_arm_watchdog_timer(igb); 2649 2650 mutex_exit(&igb->watchdog_lock); 2651 } 2652 2653 /* 2654 * igb_stop_watchdog_timer - Stop the driver watchdog timer 2655 */ 2656 static void 2657 igb_stop_watchdog_timer(igb_t *igb) 2658 { 2659 timeout_id_t tid; 2660 2661 mutex_enter(&igb->watchdog_lock); 2662 2663 igb->watchdog_start = B_FALSE; 2664 tid = igb->watchdog_tid; 2665 igb->watchdog_tid = 0; 2666 2667 mutex_exit(&igb->watchdog_lock); 2668 2669 if (tid != 0) 2670 (void) untimeout(tid); 2671 } 2672 2673 /* 2674 * igb_disable_adapter_interrupts - Clear/disable all hardware interrupts 2675 */ 2676 static void 2677 igb_disable_adapter_interrupts(igb_t *igb) 2678 { 2679 struct e1000_hw *hw = &igb->hw; 2680 2681 /* 2682 * Set the IMC register to mask all the interrupts, 2683 * including the tx interrupts. 2684 */ 2685 E1000_WRITE_REG(hw, E1000_IMC, 0xffffffff); 2686 2687 /* 2688 * Additional disabling for MSI-X 2689 */ 2690 if (igb->intr_type == DDI_INTR_TYPE_MSIX) { 2691 E1000_WRITE_REG(hw, E1000_EIMC, 0xffffffff); 2692 E1000_WRITE_REG(hw, E1000_EIAC, 0x0); 2693 } 2694 2695 E1000_WRITE_FLUSH(hw); 2696 } 2697 2698 /* 2699 * igb_enable_adapter_interrupts - Mask/enable all hardware interrupts 2700 */ 2701 static void 2702 igb_enable_adapter_interrupts(igb_t *igb) 2703 { 2704 struct e1000_hw *hw = &igb->hw; 2705 uint32_t reg; 2706 2707 if (igb->intr_type == DDI_INTR_TYPE_MSIX) { 2708 /* Interrupt enabling for MSI-X */ 2709 E1000_WRITE_REG(hw, E1000_EIMS, igb->eims_mask); 2710 E1000_WRITE_REG(hw, E1000_EIAC, igb->eims_mask); 2711 E1000_WRITE_REG(hw, E1000_IMS, E1000_IMS_LSC); 2712 2713 /* Enable MSI-X PBA support */ 2714 reg = E1000_READ_REG(hw, E1000_CTRL_EXT); 2715 reg |= E1000_CTRL_EXT_PBA_CLR; 2716 2717 /* Non-selective interrupt clear-on-read */ 2718 reg |= E1000_CTRL_EXT_IRCA; /* Called NSICR in the EAS */ 2719 2720 E1000_WRITE_REG(hw, E1000_CTRL_EXT, reg); 2721 } else { 2722 /* Interrupt enabling for MSI and legacy */ 2723 E1000_WRITE_REG(hw, E1000_IMS, IMS_ENABLE_MASK); 2724 } 2725 2726 E1000_WRITE_FLUSH(hw); 2727 } 2728 2729 /* 2730 * Loopback Support 2731 */ 2732 static lb_property_t lb_normal = 2733 { normal, "normal", IGB_LB_NONE }; 2734 static lb_property_t lb_external = 2735 { external, "External", IGB_LB_EXTERNAL }; 2736 static lb_property_t lb_mac = 2737 { internal, "MAC", IGB_LB_INTERNAL_MAC }; 2738 static lb_property_t lb_phy = 2739 { internal, "PHY", IGB_LB_INTERNAL_PHY }; 2740 static lb_property_t lb_serdes = 2741 { internal, "SerDes", IGB_LB_INTERNAL_SERDES }; 2742 2743 enum ioc_reply 2744 igb_loopback_ioctl(igb_t *igb, struct iocblk *iocp, mblk_t *mp) 2745 { 2746 lb_info_sz_t *lbsp; 2747 lb_property_t *lbpp; 2748 struct e1000_hw *hw; 2749 uint32_t *lbmp; 2750 uint32_t size; 2751 uint32_t value; 2752 2753 hw = &igb->hw; 2754 2755 if (mp->b_cont == NULL) 2756 return (IOC_INVAL); 2757 2758 switch (iocp->ioc_cmd) { 2759 default: 2760 return (IOC_INVAL); 2761 2762 case LB_GET_INFO_SIZE: 2763 size = sizeof (lb_info_sz_t); 2764 if (iocp->ioc_count != size) 2765 return (IOC_INVAL); 2766 2767 value = sizeof (lb_normal); 2768 value += sizeof (lb_mac); 2769 if (hw->phy.media_type == e1000_media_type_copper) 2770 value += sizeof (lb_phy); 2771 else 2772 value += sizeof (lb_serdes); 2773 value += sizeof (lb_external); 2774 2775 lbsp = (lb_info_sz_t *)(uintptr_t)mp->b_cont->b_rptr; 2776 *lbsp = value; 2777 break; 2778 2779 case LB_GET_INFO: 2780 value = sizeof (lb_normal); 2781 value += sizeof (lb_mac); 2782 if (hw->phy.media_type == e1000_media_type_copper) 2783 value += sizeof (lb_phy); 2784 else 2785 value += sizeof (lb_serdes); 2786 value += sizeof (lb_external); 2787 2788 size = value; 2789 if (iocp->ioc_count != size) 2790 return (IOC_INVAL); 2791 2792 value = 0; 2793 lbpp = (lb_property_t *)(uintptr_t)mp->b_cont->b_rptr; 2794 2795 lbpp[value++] = lb_normal; 2796 lbpp[value++] = lb_mac; 2797 if (hw->phy.media_type == e1000_media_type_copper) 2798 lbpp[value++] = lb_phy; 2799 else 2800 lbpp[value++] = lb_serdes; 2801 lbpp[value++] = lb_external; 2802 break; 2803 2804 case LB_GET_MODE: 2805 size = sizeof (uint32_t); 2806 if (iocp->ioc_count != size) 2807 return (IOC_INVAL); 2808 2809 lbmp = (uint32_t *)(uintptr_t)mp->b_cont->b_rptr; 2810 *lbmp = igb->loopback_mode; 2811 break; 2812 2813 case LB_SET_MODE: 2814 size = 0; 2815 if (iocp->ioc_count != sizeof (uint32_t)) 2816 return (IOC_INVAL); 2817 2818 lbmp = (uint32_t *)(uintptr_t)mp->b_cont->b_rptr; 2819 if (!igb_set_loopback_mode(igb, *lbmp)) 2820 return (IOC_INVAL); 2821 break; 2822 } 2823 2824 iocp->ioc_count = size; 2825 iocp->ioc_error = 0; 2826 2827 return (IOC_REPLY); 2828 } 2829 2830 /* 2831 * igb_set_loopback_mode - Setup loopback based on the loopback mode 2832 */ 2833 static boolean_t 2834 igb_set_loopback_mode(igb_t *igb, uint32_t mode) 2835 { 2836 struct e1000_hw *hw; 2837 2838 if (mode == igb->loopback_mode) 2839 return (B_TRUE); 2840 2841 hw = &igb->hw; 2842 2843 igb->loopback_mode = mode; 2844 2845 if (mode == IGB_LB_NONE) { 2846 /* Reset the chip */ 2847 hw->phy.autoneg_wait_to_complete = B_TRUE; 2848 (void) igb_reset(igb); 2849 hw->phy.autoneg_wait_to_complete = B_FALSE; 2850 return (B_TRUE); 2851 } 2852 2853 mutex_enter(&igb->gen_lock); 2854 2855 switch (mode) { 2856 default: 2857 mutex_exit(&igb->gen_lock); 2858 return (B_FALSE); 2859 2860 case IGB_LB_EXTERNAL: 2861 igb_set_external_loopback(igb); 2862 break; 2863 2864 case IGB_LB_INTERNAL_MAC: 2865 igb_set_internal_mac_loopback(igb); 2866 break; 2867 2868 case IGB_LB_INTERNAL_PHY: 2869 igb_set_internal_phy_loopback(igb); 2870 break; 2871 2872 case IGB_LB_INTERNAL_SERDES: 2873 igb_set_internal_serdes_loopback(igb); 2874 break; 2875 } 2876 2877 mutex_exit(&igb->gen_lock); 2878 2879 return (B_TRUE); 2880 } 2881 2882 /* 2883 * igb_set_external_loopback - Set the external loopback mode 2884 */ 2885 static void 2886 igb_set_external_loopback(igb_t *igb) 2887 { 2888 struct e1000_hw *hw; 2889 2890 hw = &igb->hw; 2891 2892 /* Set phy to known state */ 2893 (void) e1000_phy_hw_reset(hw); 2894 2895 (void) e1000_write_phy_reg(hw, 0x0, 0x0140); 2896 (void) e1000_write_phy_reg(hw, 0x9, 0x1b00); 2897 (void) e1000_write_phy_reg(hw, 0x12, 0x1610); 2898 (void) e1000_write_phy_reg(hw, 0x1f37, 0x3f1c); 2899 } 2900 2901 /* 2902 * igb_set_internal_mac_loopback - Set the internal MAC loopback mode 2903 */ 2904 static void 2905 igb_set_internal_mac_loopback(igb_t *igb) 2906 { 2907 struct e1000_hw *hw; 2908 uint32_t ctrl; 2909 uint32_t rctl; 2910 2911 hw = &igb->hw; 2912 2913 /* Set the Receive Control register */ 2914 rctl = E1000_READ_REG(hw, E1000_RCTL); 2915 rctl &= ~E1000_RCTL_LBM_TCVR; 2916 rctl |= E1000_RCTL_LBM_MAC; 2917 E1000_WRITE_REG(hw, E1000_RCTL, rctl); 2918 2919 /* Set the Device Control register */ 2920 ctrl = E1000_READ_REG(hw, E1000_CTRL); 2921 ctrl &= ~E1000_CTRL_SPD_SEL; /* Clear the speed sel bits */ 2922 ctrl |= (E1000_CTRL_SLU | /* Force link up */ 2923 E1000_CTRL_FRCSPD | /* Force speed */ 2924 E1000_CTRL_FRCDPX | /* Force duplex */ 2925 E1000_CTRL_SPD_1000 | /* Force speed to 1000 */ 2926 E1000_CTRL_FD); /* Force full duplex */ 2927 ctrl &= ~E1000_CTRL_ILOS; /* Clear ILOS when there's a link */ 2928 E1000_WRITE_REG(hw, E1000_CTRL, ctrl); 2929 } 2930 2931 /* 2932 * igb_set_internal_phy_loopback - Set the internal PHY loopback mode 2933 */ 2934 static void 2935 igb_set_internal_phy_loopback(igb_t *igb) 2936 { 2937 struct e1000_hw *hw; 2938 uint32_t ctrl_ext; 2939 uint16_t phy_ctrl; 2940 uint16_t phy_pconf; 2941 2942 hw = &igb->hw; 2943 2944 /* Set link mode to PHY (00b) in the Extended Control register */ 2945 ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT); 2946 ctrl_ext &= ~E1000_CTRL_EXT_LINK_MODE_MASK; 2947 E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext); 2948 2949 /* 2950 * Set PHY control register (0x4140): 2951 * Set full duplex mode 2952 * Set loopback bit 2953 * Clear auto-neg enable bit 2954 * Set PHY speed 2955 */ 2956 phy_ctrl = MII_CR_FULL_DUPLEX | MII_CR_SPEED_1000 | MII_CR_LOOPBACK; 2957 (void) e1000_write_phy_reg(hw, PHY_CONTROL, phy_ctrl); 2958 2959 /* Set the link disable bit in the Port Configuration register */ 2960 (void) e1000_read_phy_reg(hw, 0x10, &phy_pconf); 2961 phy_pconf |= (uint16_t)1 << 14; 2962 (void) e1000_write_phy_reg(hw, 0x10, phy_pconf); 2963 } 2964 2965 /* 2966 * igb_set_internal_serdes_loopback - Set the internal SerDes loopback mode 2967 */ 2968 static void 2969 igb_set_internal_serdes_loopback(igb_t *igb) 2970 { 2971 struct e1000_hw *hw; 2972 uint32_t ctrl_ext; 2973 uint32_t ctrl; 2974 uint32_t pcs_lctl; 2975 uint32_t connsw; 2976 2977 hw = &igb->hw; 2978 2979 /* Set link mode to SerDes (11b) in the Extended Control register */ 2980 ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT); 2981 ctrl_ext |= E1000_CTRL_EXT_LINK_MODE_PCIE_SERDES; 2982 E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext); 2983 2984 /* Configure the SerDes to loopback */ 2985 E1000_WRITE_REG(hw, E1000_SCTL, 0x410); 2986 2987 /* Set Device Control register */ 2988 ctrl = E1000_READ_REG(hw, E1000_CTRL); 2989 ctrl |= (E1000_CTRL_FD | /* Force full duplex */ 2990 E1000_CTRL_SLU); /* Force link up */ 2991 ctrl &= ~(E1000_CTRL_RFCE | /* Disable receive flow control */ 2992 E1000_CTRL_TFCE | /* Disable transmit flow control */ 2993 E1000_CTRL_LRST); /* Clear link reset */ 2994 E1000_WRITE_REG(hw, E1000_CTRL, ctrl); 2995 2996 /* Set PCS Link Control register */ 2997 pcs_lctl = E1000_READ_REG(hw, E1000_PCS_LCTL); 2998 pcs_lctl |= (E1000_PCS_LCTL_FORCE_LINK | 2999 E1000_PCS_LCTL_FSD | 3000 E1000_PCS_LCTL_FDV_FULL | 3001 E1000_PCS_LCTL_FLV_LINK_UP); 3002 pcs_lctl &= ~E1000_PCS_LCTL_AN_ENABLE; 3003 E1000_WRITE_REG(hw, E1000_PCS_LCTL, pcs_lctl); 3004 3005 /* Set the Copper/Fiber Switch Control - CONNSW register */ 3006 connsw = E1000_READ_REG(hw, E1000_CONNSW); 3007 connsw &= ~E1000_CONNSW_ENRGSRC; 3008 E1000_WRITE_REG(hw, E1000_CONNSW, connsw); 3009 } 3010 3011 #pragma inline(igb_intr_rx_work) 3012 /* 3013 * igb_intr_rx_work - rx processing of ISR 3014 */ 3015 static void 3016 igb_intr_rx_work(igb_rx_ring_t *rx_ring) 3017 { 3018 mblk_t *mp; 3019 3020 mutex_enter(&rx_ring->rx_lock); 3021 mp = igb_rx(rx_ring); 3022 mutex_exit(&rx_ring->rx_lock); 3023 3024 if (mp != NULL) 3025 mac_rx(rx_ring->igb->mac_hdl, NULL, mp); 3026 } 3027 3028 #pragma inline(igb_intr_tx_work) 3029 /* 3030 * igb_intr_tx_work - tx processing of ISR 3031 */ 3032 static void 3033 igb_intr_tx_work(igb_tx_ring_t *tx_ring) 3034 { 3035 /* Recycle the tx descriptors */ 3036 tx_ring->tx_recycle(tx_ring); 3037 3038 /* Schedule the re-transmit */ 3039 if (tx_ring->reschedule && 3040 (tx_ring->tbd_free >= tx_ring->resched_thresh)) { 3041 tx_ring->reschedule = B_FALSE; 3042 mac_tx_update(tx_ring->igb->mac_hdl); 3043 IGB_DEBUG_STAT(tx_ring->stat_reschedule); 3044 } 3045 } 3046 3047 #pragma inline(igb_intr_other_work) 3048 /* 3049 * igb_intr_other_work - other processing of ISR 3050 */ 3051 static void 3052 igb_intr_other_work(igb_t *igb) 3053 { 3054 boolean_t link_changed; 3055 3056 igb_stop_watchdog_timer(igb); 3057 3058 mutex_enter(&igb->gen_lock); 3059 3060 /* 3061 * Because we got a link-status-change interrupt, force 3062 * e1000_check_for_link() to look at phy 3063 */ 3064 igb->hw.mac.get_link_status = B_TRUE; 3065 3066 /* igb_link_check takes care of link status change */ 3067 link_changed = igb_link_check(igb); 3068 3069 /* Get new phy state */ 3070 igb_get_phy_state(igb); 3071 3072 mutex_exit(&igb->gen_lock); 3073 3074 if (link_changed) 3075 mac_link_update(igb->mac_hdl, igb->link_state); 3076 3077 igb_start_watchdog_timer(igb); 3078 } 3079 3080 /* 3081 * igb_intr_legacy - Interrupt handler for legacy interrupts 3082 */ 3083 static uint_t 3084 igb_intr_legacy(void *arg1, void *arg2) 3085 { 3086 igb_t *igb = (igb_t *)arg1; 3087 igb_tx_ring_t *tx_ring; 3088 uint32_t icr; 3089 mblk_t *mp; 3090 boolean_t tx_reschedule; 3091 boolean_t link_changed; 3092 uint_t result; 3093 3094 _NOTE(ARGUNUSED(arg2)); 3095 3096 mutex_enter(&igb->gen_lock); 3097 3098 if (igb->igb_state & IGB_SUSPENDED) { 3099 mutex_exit(&igb->gen_lock); 3100 return (DDI_INTR_UNCLAIMED); 3101 } 3102 3103 mp = NULL; 3104 tx_reschedule = B_FALSE; 3105 link_changed = B_FALSE; 3106 icr = E1000_READ_REG(&igb->hw, E1000_ICR); 3107 3108 if (icr & E1000_ICR_INT_ASSERTED) { 3109 /* 3110 * E1000_ICR_INT_ASSERTED bit was set: 3111 * Read(Clear) the ICR, claim this interrupt, 3112 * look for work to do. 3113 */ 3114 ASSERT(igb->num_rx_rings == 1); 3115 ASSERT(igb->num_tx_rings == 1); 3116 3117 if (icr & E1000_ICR_RXT0) { 3118 mp = igb_rx(&igb->rx_rings[0]); 3119 } 3120 3121 if (icr & E1000_ICR_TXDW) { 3122 tx_ring = &igb->tx_rings[0]; 3123 3124 /* Recycle the tx descriptors */ 3125 tx_ring->tx_recycle(tx_ring); 3126 3127 /* Schedule the re-transmit */ 3128 tx_reschedule = (tx_ring->reschedule && 3129 (tx_ring->tbd_free >= tx_ring->resched_thresh)); 3130 } 3131 3132 if (icr & E1000_ICR_LSC) { 3133 /* 3134 * Because we got a link-status-change interrupt, force 3135 * e1000_check_for_link() to look at phy 3136 */ 3137 igb->hw.mac.get_link_status = B_TRUE; 3138 3139 /* igb_link_check takes care of link status change */ 3140 link_changed = igb_link_check(igb); 3141 3142 /* Get new phy state */ 3143 igb_get_phy_state(igb); 3144 } 3145 3146 result = DDI_INTR_CLAIMED; 3147 } else { 3148 /* 3149 * E1000_ICR_INT_ASSERTED bit was not set: 3150 * Don't claim this interrupt. 3151 */ 3152 result = DDI_INTR_UNCLAIMED; 3153 } 3154 3155 mutex_exit(&igb->gen_lock); 3156 3157 /* 3158 * Do the following work outside of the gen_lock 3159 */ 3160 if (mp != NULL) 3161 mac_rx(igb->mac_hdl, NULL, mp); 3162 3163 if (tx_reschedule) { 3164 tx_ring->reschedule = B_FALSE; 3165 mac_tx_update(igb->mac_hdl); 3166 IGB_DEBUG_STAT(tx_ring->stat_reschedule); 3167 } 3168 3169 if (link_changed) 3170 mac_link_update(igb->mac_hdl, igb->link_state); 3171 3172 return (result); 3173 } 3174 3175 /* 3176 * igb_intr_msi - Interrupt handler for MSI 3177 */ 3178 static uint_t 3179 igb_intr_msi(void *arg1, void *arg2) 3180 { 3181 igb_t *igb = (igb_t *)arg1; 3182 uint32_t icr; 3183 3184 _NOTE(ARGUNUSED(arg2)); 3185 3186 icr = E1000_READ_REG(&igb->hw, E1000_ICR); 3187 3188 /* 3189 * For MSI interrupt, we have only one vector, 3190 * so we have only one rx ring and one tx ring enabled. 3191 */ 3192 ASSERT(igb->num_rx_rings == 1); 3193 ASSERT(igb->num_tx_rings == 1); 3194 3195 if (icr & E1000_ICR_RXT0) { 3196 igb_intr_rx_work(&igb->rx_rings[0]); 3197 } 3198 3199 if (icr & E1000_ICR_TXDW) { 3200 igb_intr_tx_work(&igb->tx_rings[0]); 3201 } 3202 3203 if (icr & E1000_ICR_LSC) { 3204 igb_intr_other_work(igb); 3205 } 3206 3207 return (DDI_INTR_CLAIMED); 3208 } 3209 3210 /* 3211 * igb_intr_rx - Interrupt handler for rx 3212 */ 3213 static uint_t 3214 igb_intr_rx(void *arg1, void *arg2) 3215 { 3216 igb_rx_ring_t *rx_ring = (igb_rx_ring_t *)arg1; 3217 3218 _NOTE(ARGUNUSED(arg2)); 3219 3220 /* 3221 * Only used via MSI-X vector so don't check cause bits 3222 * and only clean the given ring. 3223 */ 3224 igb_intr_rx_work(rx_ring); 3225 3226 return (DDI_INTR_CLAIMED); 3227 } 3228 3229 /* 3230 * igb_intr_tx_other - Interrupt handler for both tx and other 3231 * 3232 * Always look for Tx cleanup work. Only look for other work if the right 3233 * bits are set in the Interrupt Cause Register. 3234 */ 3235 static uint_t 3236 igb_intr_tx_other(void *arg1, void *arg2) 3237 { 3238 igb_t *igb = (igb_t *)arg1; 3239 uint32_t icr; 3240 3241 _NOTE(ARGUNUSED(arg2)); 3242 3243 icr = E1000_READ_REG(&igb->hw, E1000_ICR); 3244 3245 /* 3246 * Always look for Tx cleanup work. We don't have separate 3247 * transmit vectors, so we have only one tx ring enabled. 3248 */ 3249 ASSERT(igb->num_tx_rings == 1); 3250 igb_intr_tx_work(&igb->tx_rings[0]); 3251 3252 /* 3253 * Check for "other" causes. 3254 */ 3255 if (icr & E1000_ICR_LSC) { 3256 igb_intr_other_work(igb); 3257 } 3258 3259 return (DDI_INTR_CLAIMED); 3260 } 3261 3262 /* 3263 * igb_alloc_intrs - Allocate interrupts for the driver 3264 * 3265 * Normal sequence is to try MSI-X; if not sucessful, try MSI; 3266 * if not successful, try Legacy. 3267 * igb->intr_force can be used to force sequence to start with 3268 * any of the 3 types. 3269 * If MSI-X is not used, number of tx/rx rings is forced to 1. 3270 */ 3271 static int 3272 igb_alloc_intrs(igb_t *igb) 3273 { 3274 dev_info_t *devinfo; 3275 int intr_types; 3276 int rc; 3277 3278 devinfo = igb->dip; 3279 3280 /* Get supported interrupt types */ 3281 rc = ddi_intr_get_supported_types(devinfo, &intr_types); 3282 3283 if (rc != DDI_SUCCESS) { 3284 igb_log(igb, 3285 "Get supported interrupt types failed: %d", rc); 3286 return (IGB_FAILURE); 3287 } 3288 IGB_DEBUGLOG_1(igb, "Supported interrupt types: %x", intr_types); 3289 3290 igb->intr_type = 0; 3291 3292 /* Install MSI-X interrupts */ 3293 if ((intr_types & DDI_INTR_TYPE_MSIX) && 3294 (igb->intr_force <= IGB_INTR_MSIX)) { 3295 rc = igb_alloc_intrs_msix(igb); 3296 3297 if (rc == IGB_SUCCESS) 3298 return (IGB_SUCCESS); 3299 3300 igb_log(igb, 3301 "Allocate MSI-X failed, trying MSI interrupts..."); 3302 } 3303 3304 /* MSI-X not used, force rings to 1 */ 3305 igb->num_rx_rings = 1; 3306 igb->num_tx_rings = 1; 3307 igb_log(igb, 3308 "MSI-X not used, force rx and tx queue number to 1"); 3309 3310 /* Install MSI interrupts */ 3311 if ((intr_types & DDI_INTR_TYPE_MSI) && 3312 (igb->intr_force <= IGB_INTR_MSI)) { 3313 rc = igb_alloc_intrs_msi(igb); 3314 3315 if (rc == IGB_SUCCESS) 3316 return (IGB_SUCCESS); 3317 3318 igb_log(igb, 3319 "Allocate MSI failed, trying Legacy interrupts..."); 3320 } 3321 3322 /* Install legacy interrupts */ 3323 if (intr_types & DDI_INTR_TYPE_FIXED) { 3324 rc = igb_alloc_intrs_legacy(igb); 3325 3326 if (rc == IGB_SUCCESS) 3327 return (IGB_SUCCESS); 3328 3329 igb_log(igb, 3330 "Allocate Legacy interrupts failed"); 3331 } 3332 3333 /* If none of the 3 types succeeded, return failure */ 3334 return (IGB_FAILURE); 3335 } 3336 3337 /* 3338 * igb_alloc_intrs_msix - Allocate the MSIX interrupts 3339 * 3340 * If fewer than 2 vectors are available, return failure. 3341 * Upon success, this sets the number of Rx rings to a number that 3342 * matches the vectors available for Rx interrupts. 3343 */ 3344 static int 3345 igb_alloc_intrs_msix(igb_t *igb) 3346 { 3347 dev_info_t *devinfo; 3348 int request, count, avail, actual; 3349 int rx_rings; 3350 int rc; 3351 3352 devinfo = igb->dip; 3353 3354 /* 3355 * Currently only 1 tx ring is supported. More tx rings 3356 * will be supported with future enhancement. 3357 */ 3358 if (igb->num_tx_rings > 1) { 3359 igb->num_tx_rings = 1; 3360 igb_log(igb, 3361 "Use only 1 MSI-X vector for tx, " 3362 "force tx queue number to 1"); 3363 } 3364 3365 /* 3366 * Best number of vectors for the adapter is 3367 * # rx rings + # tx rings + 1 for other 3368 * But currently we only support number of vectors of 3369 * # rx rings + 1 for tx & other 3370 */ 3371 request = igb->num_rx_rings + 1; 3372 IGB_DEBUGLOG_1(igb, "MSI-X interrupts requested: %d", request); 3373 3374 /* Get number of supported interrupts */ 3375 rc = ddi_intr_get_nintrs(devinfo, DDI_INTR_TYPE_MSIX, &count); 3376 if ((rc != DDI_SUCCESS) || (count == 0)) { 3377 igb_log(igb, 3378 "Get interrupt number failed. Return: %d, count: %d", 3379 rc, count); 3380 return (IGB_FAILURE); 3381 } 3382 IGB_DEBUGLOG_1(igb, "MSI-X interrupts supported: %d", count); 3383 3384 /* Get number of available interrupts */ 3385 rc = ddi_intr_get_navail(devinfo, DDI_INTR_TYPE_MSIX, &avail); 3386 if ((rc != DDI_SUCCESS) || (avail == 0)) { 3387 igb_log(igb, 3388 "Get interrupt available number failed. " 3389 "Return: %d, available: %d", rc, avail); 3390 return (IGB_FAILURE); 3391 } 3392 IGB_DEBUGLOG_1(igb, "MSI-X interrupts available: %d", avail); 3393 3394 if (avail < request) { 3395 igb_log(igb, 3396 "Request %d MSI-X vectors, %d available", 3397 request, avail); 3398 request = avail; 3399 } 3400 3401 actual = 0; 3402 igb->intr_cnt = 0; 3403 3404 /* Allocate an array of interrupt handles */ 3405 igb->intr_size = request * sizeof (ddi_intr_handle_t); 3406 igb->htable = kmem_alloc(igb->intr_size, KM_SLEEP); 3407 3408 /* Call ddi_intr_alloc() */ 3409 rc = ddi_intr_alloc(devinfo, igb->htable, DDI_INTR_TYPE_MSIX, 0, 3410 request, &actual, DDI_INTR_ALLOC_NORMAL); 3411 if (rc != DDI_SUCCESS) { 3412 igb_log(igb, "Allocate MSI-X interrupts failed. " 3413 "return: %d, request: %d, actual: %d", 3414 rc, request, actual); 3415 goto alloc_msix_fail; 3416 } 3417 IGB_DEBUGLOG_1(igb, "MSI-X interrupts actually allocated: %d", actual); 3418 3419 igb->intr_cnt = actual; 3420 3421 /* 3422 * Now we know the actual number of vectors. Here we assume that 3423 * tx and other will share 1 vector and all remaining (must be at 3424 * least 1 remaining) will be used for rx. 3425 */ 3426 if (actual < 2) { 3427 igb_log(igb, "Insufficient MSI-X interrupts available: %d", 3428 actual); 3429 goto alloc_msix_fail; 3430 } 3431 3432 rx_rings = actual - 1; 3433 if (rx_rings < igb->num_rx_rings) { 3434 igb_log(igb, "MSI-X vectors force Rx queue number to %d", 3435 rx_rings); 3436 igb->num_rx_rings = rx_rings; 3437 } 3438 3439 /* Get priority for first vector, assume remaining are all the same */ 3440 rc = ddi_intr_get_pri(igb->htable[0], &igb->intr_pri); 3441 if (rc != DDI_SUCCESS) { 3442 igb_log(igb, 3443 "Get interrupt priority failed: %d", rc); 3444 goto alloc_msix_fail; 3445 } 3446 3447 rc = ddi_intr_get_cap(igb->htable[0], &igb->intr_cap); 3448 if (rc != DDI_SUCCESS) { 3449 igb_log(igb, 3450 "Get interrupt cap failed: %d", rc); 3451 goto alloc_msix_fail; 3452 } 3453 3454 igb->intr_type = DDI_INTR_TYPE_MSIX; 3455 3456 return (IGB_SUCCESS); 3457 3458 alloc_msix_fail: 3459 igb_rem_intrs(igb); 3460 3461 return (IGB_FAILURE); 3462 } 3463 3464 /* 3465 * igb_alloc_intrs_msi - Allocate the MSI interrupts 3466 */ 3467 static int 3468 igb_alloc_intrs_msi(igb_t *igb) 3469 { 3470 dev_info_t *devinfo; 3471 int request, count, avail, actual; 3472 int rc; 3473 3474 devinfo = igb->dip; 3475 3476 /* Request 1 MSI interrupt vector */ 3477 request = 1; 3478 IGB_DEBUGLOG_1(igb, "MSI interrupts requested: %d", request); 3479 3480 /* Get number of supported interrupts */ 3481 rc = ddi_intr_get_nintrs(devinfo, DDI_INTR_TYPE_MSI, &count); 3482 if ((rc != DDI_SUCCESS) || (count == 0)) { 3483 igb_log(igb, 3484 "Get MSI supported number failed. Return: %d, count: %d", 3485 rc, count); 3486 return (IGB_FAILURE); 3487 } 3488 IGB_DEBUGLOG_1(igb, "MSI interrupts supported: %d", count); 3489 3490 /* Get number of available interrupts */ 3491 rc = ddi_intr_get_navail(devinfo, DDI_INTR_TYPE_MSI, &avail); 3492 if ((rc != DDI_SUCCESS) || (avail == 0)) { 3493 igb_log(igb, 3494 "Get MSI available number failed. " 3495 "Return: %d, available: %d", rc, avail); 3496 return (IGB_FAILURE); 3497 } 3498 IGB_DEBUGLOG_1(igb, "MSI interrupts available: %d", avail); 3499 3500 actual = 0; 3501 igb->intr_cnt = 0; 3502 3503 /* Allocate an array of interrupt handles */ 3504 igb->intr_size = request * sizeof (ddi_intr_handle_t); 3505 igb->htable = kmem_alloc(igb->intr_size, KM_SLEEP); 3506 3507 /* Call ddi_intr_alloc() */ 3508 rc = ddi_intr_alloc(devinfo, igb->htable, DDI_INTR_TYPE_MSI, 0, 3509 request, &actual, DDI_INTR_ALLOC_NORMAL); 3510 if ((rc != DDI_SUCCESS) || (actual == 0)) { 3511 igb_log(igb, 3512 "Allocate MSI interrupts failed: %d", rc); 3513 goto alloc_msi_fail; 3514 } 3515 3516 ASSERT(actual == 1); 3517 igb->intr_cnt = actual; 3518 3519 /* Get priority for first msi, assume remaining are all the same */ 3520 rc = ddi_intr_get_pri(igb->htable[0], &igb->intr_pri); 3521 if (rc != DDI_SUCCESS) { 3522 igb_log(igb, 3523 "Get interrupt priority failed: %d", rc); 3524 goto alloc_msi_fail; 3525 } 3526 3527 rc = ddi_intr_get_cap(igb->htable[0], &igb->intr_cap); 3528 if (rc != DDI_SUCCESS) { 3529 igb_log(igb, 3530 "Get interrupt cap failed: %d\n", rc); 3531 goto alloc_msi_fail; 3532 3533 } 3534 3535 igb->intr_type = DDI_INTR_TYPE_MSI; 3536 3537 return (IGB_SUCCESS); 3538 3539 alloc_msi_fail: 3540 igb_rem_intrs(igb); 3541 3542 return (IGB_FAILURE); 3543 } 3544 3545 /* 3546 * igb_alloc_intrs_legacy - Allocate the Legacy interrupts 3547 */ 3548 static int 3549 igb_alloc_intrs_legacy(igb_t *igb) 3550 { 3551 dev_info_t *devinfo; 3552 int request, count, avail, actual; 3553 int rc; 3554 3555 devinfo = igb->dip; 3556 3557 /* Request 1 Legacy interrupt vector */ 3558 request = 1; 3559 IGB_DEBUGLOG_1(igb, "Legacy interrupts requested: %d", request); 3560 3561 /* Get number of supported interrupts */ 3562 rc = ddi_intr_get_nintrs(devinfo, DDI_INTR_TYPE_FIXED, &count); 3563 if ((rc != DDI_SUCCESS) || (count == 0)) { 3564 igb_log(igb, 3565 "Get Legacy supported number failed. Return: %d, count: %d", 3566 rc, count); 3567 return (IGB_FAILURE); 3568 } 3569 IGB_DEBUGLOG_1(igb, "Legacy interrupts supported: %d", count); 3570 3571 /* Get number of available interrupts */ 3572 rc = ddi_intr_get_navail(devinfo, DDI_INTR_TYPE_FIXED, &avail); 3573 if ((rc != DDI_SUCCESS) || (avail == 0)) { 3574 igb_log(igb, 3575 "Get Legacy available number failed. " 3576 "Return: %d, available: %d", rc, avail); 3577 return (IGB_FAILURE); 3578 } 3579 IGB_DEBUGLOG_1(igb, "Legacy interrupts available: %d", avail); 3580 3581 actual = 0; 3582 igb->intr_cnt = 0; 3583 3584 /* Allocate an array of interrupt handles */ 3585 igb->intr_size = request * sizeof (ddi_intr_handle_t); 3586 igb->htable = kmem_alloc(igb->intr_size, KM_SLEEP); 3587 3588 /* Call ddi_intr_alloc() */ 3589 rc = ddi_intr_alloc(devinfo, igb->htable, DDI_INTR_TYPE_FIXED, 0, 3590 request, &actual, DDI_INTR_ALLOC_NORMAL); 3591 if ((rc != DDI_SUCCESS) || (actual == 0)) { 3592 igb_log(igb, 3593 "Allocate Legacy interrupts failed: %d", rc); 3594 goto alloc_legacy_fail; 3595 } 3596 3597 ASSERT(actual == 1); 3598 igb->intr_cnt = actual; 3599 3600 /* Get priority for first msi, assume remaining are all the same */ 3601 rc = ddi_intr_get_pri(igb->htable[0], &igb->intr_pri); 3602 if (rc != DDI_SUCCESS) { 3603 igb_log(igb, 3604 "Get interrupt priority failed: %d", rc); 3605 goto alloc_legacy_fail; 3606 } 3607 3608 rc = ddi_intr_get_cap(igb->htable[0], &igb->intr_cap); 3609 if (rc != DDI_SUCCESS) { 3610 igb_log(igb, 3611 "Get interrupt cap failed: %d\n", rc); 3612 goto alloc_legacy_fail; 3613 } 3614 3615 igb->intr_type = DDI_INTR_TYPE_FIXED; 3616 3617 return (IGB_SUCCESS); 3618 3619 alloc_legacy_fail: 3620 igb_rem_intrs(igb); 3621 3622 return (IGB_FAILURE); 3623 } 3624 3625 /* 3626 * igb_add_intr_handlers - Add interrupt handlers based on the interrupt type 3627 * 3628 * Before adding the interrupt handlers, the interrupt vectors have 3629 * been allocated, and the rx/tx rings have also been allocated. 3630 */ 3631 static int 3632 igb_add_intr_handlers(igb_t *igb) 3633 { 3634 igb_rx_ring_t *rx_ring; 3635 int vector; 3636 int rc; 3637 int i; 3638 3639 vector = 0; 3640 3641 switch (igb->intr_type) { 3642 case DDI_INTR_TYPE_MSIX: 3643 /* Add interrupt handler for tx + other */ 3644 rc = ddi_intr_add_handler(igb->htable[vector], 3645 (ddi_intr_handler_t *)igb_intr_tx_other, 3646 (void *)igb, NULL); 3647 if (rc != DDI_SUCCESS) { 3648 igb_log(igb, 3649 "Add tx/other interrupt handler failed: %d", rc); 3650 return (IGB_FAILURE); 3651 } 3652 vector++; 3653 3654 /* Add interrupt handler for each rx ring */ 3655 for (i = 0; i < igb->num_rx_rings; i++) { 3656 rx_ring = &igb->rx_rings[i]; 3657 3658 rc = ddi_intr_add_handler(igb->htable[vector], 3659 (ddi_intr_handler_t *)igb_intr_rx, 3660 (void *)rx_ring, NULL); 3661 3662 if (rc != DDI_SUCCESS) { 3663 igb_log(igb, 3664 "Add rx interrupt handler failed. " 3665 "return: %d, rx ring: %d", rc, i); 3666 for (vector--; vector >= 0; vector--) { 3667 (void) ddi_intr_remove_handler( 3668 igb->htable[vector]); 3669 } 3670 return (IGB_FAILURE); 3671 } 3672 3673 rx_ring->intr_vector = vector; 3674 3675 vector++; 3676 } 3677 break; 3678 3679 case DDI_INTR_TYPE_MSI: 3680 /* Add interrupt handlers for the only vector */ 3681 rc = ddi_intr_add_handler(igb->htable[vector], 3682 (ddi_intr_handler_t *)igb_intr_msi, 3683 (void *)igb, NULL); 3684 3685 if (rc != DDI_SUCCESS) { 3686 igb_log(igb, 3687 "Add MSI interrupt handler failed: %d", rc); 3688 return (IGB_FAILURE); 3689 } 3690 3691 rx_ring = &igb->rx_rings[0]; 3692 rx_ring->intr_vector = vector; 3693 3694 vector++; 3695 break; 3696 3697 case DDI_INTR_TYPE_FIXED: 3698 /* Add interrupt handlers for the only vector */ 3699 rc = ddi_intr_add_handler(igb->htable[vector], 3700 (ddi_intr_handler_t *)igb_intr_legacy, 3701 (void *)igb, NULL); 3702 3703 if (rc != DDI_SUCCESS) { 3704 igb_log(igb, 3705 "Add legacy interrupt handler failed: %d", rc); 3706 return (IGB_FAILURE); 3707 } 3708 3709 rx_ring = &igb->rx_rings[0]; 3710 rx_ring->intr_vector = vector; 3711 3712 vector++; 3713 break; 3714 3715 default: 3716 return (IGB_FAILURE); 3717 } 3718 3719 ASSERT(vector == igb->intr_cnt); 3720 3721 return (IGB_SUCCESS); 3722 } 3723 3724 /* 3725 * igb_setup_adapter_msix - setup the adapter to use MSI-X interrupts 3726 * 3727 * For each vector enabled on the adapter, Set the MSIXBM register accordingly 3728 */ 3729 static void 3730 igb_setup_adapter_msix(igb_t *igb) 3731 { 3732 uint32_t eims = 0; 3733 int i, vector; 3734 struct e1000_hw *hw = &igb->hw; 3735 3736 /* 3737 * Set vector for Tx + Other causes 3738 * NOTE assumption that there is only one of these and it is vector 0 3739 */ 3740 vector = 0; 3741 igb->eims_mask = E1000_EICR_TX_QUEUE0 | E1000_EICR_OTHER; 3742 E1000_WRITE_REG(hw, E1000_MSIXBM(vector), igb->eims_mask); 3743 3744 vector++; 3745 for (i = 0; i < igb->num_rx_rings; i++) { 3746 /* 3747 * Set vector for each rx ring 3748 */ 3749 eims = (E1000_EICR_RX_QUEUE0 << i); 3750 E1000_WRITE_REG(hw, E1000_MSIXBM(vector), eims); 3751 3752 /* 3753 * Accumulate bits to enable in igb_enable_adapter_interrupts() 3754 */ 3755 igb->eims_mask |= eims; 3756 3757 vector++; 3758 } 3759 3760 ASSERT(vector == igb->intr_cnt); 3761 3762 /* 3763 * Disable IAM for ICR interrupt bits 3764 */ 3765 E1000_WRITE_REG(hw, E1000_IAM, 0); 3766 E1000_WRITE_FLUSH(hw); 3767 } 3768 3769 /* 3770 * igb_rem_intr_handlers - remove the interrupt handlers 3771 */ 3772 static void 3773 igb_rem_intr_handlers(igb_t *igb) 3774 { 3775 int i; 3776 int rc; 3777 3778 for (i = 0; i < igb->intr_cnt; i++) { 3779 rc = ddi_intr_remove_handler(igb->htable[i]); 3780 if (rc != DDI_SUCCESS) { 3781 IGB_DEBUGLOG_1(igb, 3782 "Remove intr handler failed: %d", rc); 3783 } 3784 } 3785 } 3786 3787 /* 3788 * igb_rem_intrs - remove the allocated interrupts 3789 */ 3790 static void 3791 igb_rem_intrs(igb_t *igb) 3792 { 3793 int i; 3794 int rc; 3795 3796 for (i = 0; i < igb->intr_cnt; i++) { 3797 rc = ddi_intr_free(igb->htable[i]); 3798 if (rc != DDI_SUCCESS) { 3799 IGB_DEBUGLOG_1(igb, 3800 "Free intr failed: %d", rc); 3801 } 3802 } 3803 3804 kmem_free(igb->htable, igb->intr_size); 3805 igb->htable = NULL; 3806 } 3807 3808 /* 3809 * igb_enable_intrs - enable all the ddi interrupts 3810 */ 3811 static int 3812 igb_enable_intrs(igb_t *igb) 3813 { 3814 int i; 3815 int rc; 3816 3817 /* Enable interrupts */ 3818 if (igb->intr_cap & DDI_INTR_FLAG_BLOCK) { 3819 /* Call ddi_intr_block_enable() for MSI */ 3820 rc = ddi_intr_block_enable(igb->htable, igb->intr_cnt); 3821 if (rc != DDI_SUCCESS) { 3822 igb_log(igb, 3823 "Enable block intr failed: %d", rc); 3824 return (IGB_FAILURE); 3825 } 3826 } else { 3827 /* Call ddi_intr_enable() for Legacy/MSI non block enable */ 3828 for (i = 0; i < igb->intr_cnt; i++) { 3829 rc = ddi_intr_enable(igb->htable[i]); 3830 if (rc != DDI_SUCCESS) { 3831 igb_log(igb, 3832 "Enable intr failed: %d", rc); 3833 return (IGB_FAILURE); 3834 } 3835 } 3836 } 3837 3838 return (IGB_SUCCESS); 3839 } 3840 3841 /* 3842 * igb_disable_intrs - disable all the ddi interrupts 3843 */ 3844 static int 3845 igb_disable_intrs(igb_t *igb) 3846 { 3847 int i; 3848 int rc; 3849 3850 /* Disable all interrupts */ 3851 if (igb->intr_cap & DDI_INTR_FLAG_BLOCK) { 3852 rc = ddi_intr_block_disable(igb->htable, igb->intr_cnt); 3853 if (rc != DDI_SUCCESS) { 3854 igb_log(igb, 3855 "Disable block intr failed: %d", rc); 3856 return (IGB_FAILURE); 3857 } 3858 } else { 3859 for (i = 0; i < igb->intr_cnt; i++) { 3860 rc = ddi_intr_disable(igb->htable[i]); 3861 if (rc != DDI_SUCCESS) { 3862 igb_log(igb, 3863 "Disable intr failed: %d", rc); 3864 return (IGB_FAILURE); 3865 } 3866 } 3867 } 3868 3869 return (IGB_SUCCESS); 3870 } 3871 3872 /* 3873 * igb_get_phy_state - Get and save the parameters read from PHY registers 3874 */ 3875 static void 3876 igb_get_phy_state(igb_t *igb) 3877 { 3878 struct e1000_hw *hw = &igb->hw; 3879 uint16_t phy_ctrl; 3880 uint16_t phy_status; 3881 uint16_t phy_an_adv; 3882 uint16_t phy_an_exp; 3883 uint16_t phy_ext_status; 3884 uint16_t phy_1000t_ctrl; 3885 uint16_t phy_1000t_status; 3886 uint16_t phy_lp_able; 3887 3888 ASSERT(mutex_owned(&igb->gen_lock)); 3889 3890 (void) e1000_read_phy_reg(hw, PHY_CONTROL, &phy_ctrl); 3891 (void) e1000_read_phy_reg(hw, PHY_STATUS, &phy_status); 3892 (void) e1000_read_phy_reg(hw, PHY_AUTONEG_ADV, &phy_an_adv); 3893 (void) e1000_read_phy_reg(hw, PHY_AUTONEG_EXP, &phy_an_exp); 3894 (void) e1000_read_phy_reg(hw, PHY_EXT_STATUS, &phy_ext_status); 3895 (void) e1000_read_phy_reg(hw, PHY_1000T_CTRL, &phy_1000t_ctrl); 3896 (void) e1000_read_phy_reg(hw, PHY_1000T_STATUS, &phy_1000t_status); 3897 (void) e1000_read_phy_reg(hw, PHY_LP_ABILITY, &phy_lp_able); 3898 3899 igb->param_autoneg_cap = 3900 (phy_status & MII_SR_AUTONEG_CAPS) ? 1 : 0; 3901 igb->param_pause_cap = 3902 (phy_an_adv & NWAY_AR_PAUSE) ? 1 : 0; 3903 igb->param_asym_pause_cap = 3904 (phy_an_adv & NWAY_AR_ASM_DIR) ? 1 : 0; 3905 igb->param_1000fdx_cap = ((phy_ext_status & IEEE_ESR_1000T_FD_CAPS) || 3906 (phy_ext_status & IEEE_ESR_1000X_FD_CAPS)) ? 1 : 0; 3907 igb->param_1000hdx_cap = ((phy_ext_status & IEEE_ESR_1000T_HD_CAPS) || 3908 (phy_ext_status & IEEE_ESR_1000X_HD_CAPS)) ? 1 : 0; 3909 igb->param_100t4_cap = 3910 (phy_status & MII_SR_100T4_CAPS) ? 1 : 0; 3911 igb->param_100fdx_cap = ((phy_status & MII_SR_100X_FD_CAPS) || 3912 (phy_status & MII_SR_100T2_FD_CAPS)) ? 1 : 0; 3913 igb->param_100hdx_cap = ((phy_status & MII_SR_100X_HD_CAPS) || 3914 (phy_status & MII_SR_100T2_HD_CAPS)) ? 1 : 0; 3915 igb->param_10fdx_cap = 3916 (phy_status & MII_SR_10T_FD_CAPS) ? 1 : 0; 3917 igb->param_10hdx_cap = 3918 (phy_status & MII_SR_10T_HD_CAPS) ? 1 : 0; 3919 igb->param_rem_fault = 3920 (phy_status & MII_SR_REMOTE_FAULT) ? 1 : 0; 3921 3922 igb->param_adv_autoneg_cap = hw->mac.autoneg; 3923 igb->param_adv_pause_cap = 3924 (phy_an_adv & NWAY_AR_PAUSE) ? 1 : 0; 3925 igb->param_adv_asym_pause_cap = 3926 (phy_an_adv & NWAY_AR_ASM_DIR) ? 1 : 0; 3927 igb->param_adv_1000hdx_cap = 3928 (phy_1000t_ctrl & CR_1000T_HD_CAPS) ? 1 : 0; 3929 igb->param_adv_100t4_cap = 3930 (phy_an_adv & NWAY_AR_100T4_CAPS) ? 1 : 0; 3931 igb->param_adv_rem_fault = 3932 (phy_an_adv & NWAY_AR_REMOTE_FAULT) ? 1 : 0; 3933 if (igb->param_adv_autoneg_cap == 1) { 3934 igb->param_adv_1000fdx_cap = 3935 (phy_1000t_ctrl & CR_1000T_FD_CAPS) ? 1 : 0; 3936 igb->param_adv_100fdx_cap = 3937 (phy_an_adv & NWAY_AR_100TX_FD_CAPS) ? 1 : 0; 3938 igb->param_adv_100hdx_cap = 3939 (phy_an_adv & NWAY_AR_100TX_HD_CAPS) ? 1 : 0; 3940 igb->param_adv_10fdx_cap = 3941 (phy_an_adv & NWAY_AR_10T_FD_CAPS) ? 1 : 0; 3942 igb->param_adv_10hdx_cap = 3943 (phy_an_adv & NWAY_AR_10T_HD_CAPS) ? 1 : 0; 3944 } 3945 3946 igb->param_lp_autoneg_cap = 3947 (phy_an_exp & NWAY_ER_LP_NWAY_CAPS) ? 1 : 0; 3948 igb->param_lp_pause_cap = 3949 (phy_lp_able & NWAY_LPAR_PAUSE) ? 1 : 0; 3950 igb->param_lp_asym_pause_cap = 3951 (phy_lp_able & NWAY_LPAR_ASM_DIR) ? 1 : 0; 3952 igb->param_lp_1000fdx_cap = 3953 (phy_1000t_status & SR_1000T_LP_FD_CAPS) ? 1 : 0; 3954 igb->param_lp_1000hdx_cap = 3955 (phy_1000t_status & SR_1000T_LP_HD_CAPS) ? 1 : 0; 3956 igb->param_lp_100t4_cap = 3957 (phy_lp_able & NWAY_LPAR_100T4_CAPS) ? 1 : 0; 3958 igb->param_lp_100fdx_cap = 3959 (phy_lp_able & NWAY_LPAR_100TX_FD_CAPS) ? 1 : 0; 3960 igb->param_lp_100hdx_cap = 3961 (phy_lp_able & NWAY_LPAR_100TX_HD_CAPS) ? 1 : 0; 3962 igb->param_lp_10fdx_cap = 3963 (phy_lp_able & NWAY_LPAR_10T_FD_CAPS) ? 1 : 0; 3964 igb->param_lp_10hdx_cap = 3965 (phy_lp_able & NWAY_LPAR_10T_HD_CAPS) ? 1 : 0; 3966 igb->param_lp_rem_fault = 3967 (phy_lp_able & NWAY_LPAR_REMOTE_FAULT) ? 1 : 0; 3968 } 3969 3970 /* 3971 * igb_get_driver_control 3972 */ 3973 static void 3974 igb_get_driver_control(struct e1000_hw *hw) 3975 { 3976 uint32_t ctrl_ext; 3977 3978 /* Notify firmware that driver is in control of device */ 3979 ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT); 3980 ctrl_ext |= E1000_CTRL_EXT_DRV_LOAD; 3981 E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext); 3982 } 3983 3984 /* 3985 * igb_release_driver_control 3986 */ 3987 static void 3988 igb_release_driver_control(struct e1000_hw *hw) 3989 { 3990 uint32_t ctrl_ext; 3991 3992 /* Notify firmware that driver is no longer in control of device */ 3993 ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT); 3994 ctrl_ext &= ~E1000_CTRL_EXT_DRV_LOAD; 3995 E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext); 3996 } 3997 3998 /* 3999 * igb_atomic_reserve - Atomic decrease operation 4000 */ 4001 int 4002 igb_atomic_reserve(uint32_t *count_p, uint32_t n) 4003 { 4004 uint32_t oldval; 4005 uint32_t newval; 4006 4007 /* ATOMICALLY */ 4008 do { 4009 oldval = *count_p; 4010 if (oldval < n) 4011 return (-1); 4012 newval = oldval - n; 4013 } while (atomic_cas_32(count_p, oldval, newval) != oldval); 4014 4015 return (newval); 4016 } 4017