1 /*- 2 * Copyright 2021 Intel Corp 3 * Copyright 2021 Rubicon Communications, LLC (Netgate) 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #include "igc_api.h" 8 9 static void igc_reload_nvm_generic(struct igc_hw *hw); 10 11 /** 12 * igc_init_nvm_ops_generic - Initialize NVM function pointers 13 * @hw: pointer to the HW structure 14 * 15 * Setups up the function pointers to no-op functions 16 **/ 17 void igc_init_nvm_ops_generic(struct igc_hw *hw) 18 { 19 struct igc_nvm_info *nvm = &hw->nvm; 20 DEBUGFUNC("igc_init_nvm_ops_generic"); 21 22 /* Initialize function pointers */ 23 nvm->ops.init_params = igc_null_ops_generic; 24 nvm->ops.acquire = igc_null_ops_generic; 25 nvm->ops.read = igc_null_read_nvm; 26 nvm->ops.release = igc_null_nvm_generic; 27 nvm->ops.reload = igc_reload_nvm_generic; 28 nvm->ops.update = igc_null_ops_generic; 29 nvm->ops.validate = igc_null_ops_generic; 30 nvm->ops.write = igc_null_write_nvm; 31 } 32 33 /** 34 * igc_null_nvm_read - No-op function, return 0 35 * @hw: pointer to the HW structure 36 * @a: dummy variable 37 * @b: dummy variable 38 * @c: dummy variable 39 **/ 40 s32 igc_null_read_nvm(struct igc_hw IGC_UNUSEDARG *hw, 41 u16 IGC_UNUSEDARG a, u16 IGC_UNUSEDARG b, 42 u16 IGC_UNUSEDARG *c) 43 { 44 DEBUGFUNC("igc_null_read_nvm"); 45 return IGC_SUCCESS; 46 } 47 48 /** 49 * igc_null_nvm_generic - No-op function, return void 50 * @hw: pointer to the HW structure 51 **/ 52 void igc_null_nvm_generic(struct igc_hw IGC_UNUSEDARG *hw) 53 { 54 DEBUGFUNC("igc_null_nvm_generic"); 55 return; 56 } 57 58 /** 59 * igc_null_write_nvm - No-op function, return 0 60 * @hw: pointer to the HW structure 61 * @a: dummy variable 62 * @b: dummy variable 63 * @c: dummy variable 64 **/ 65 s32 igc_null_write_nvm(struct igc_hw IGC_UNUSEDARG *hw, 66 u16 IGC_UNUSEDARG a, u16 IGC_UNUSEDARG b, 67 u16 IGC_UNUSEDARG *c) 68 { 69 DEBUGFUNC("igc_null_write_nvm"); 70 return IGC_SUCCESS; 71 } 72 73 /** 74 * igc_raise_eec_clk - Raise EEPROM clock 75 * @hw: pointer to the HW structure 76 * @eecd: pointer to the EEPROM 77 * 78 * Enable/Raise the EEPROM clock bit. 79 **/ 80 static void igc_raise_eec_clk(struct igc_hw *hw, u32 *eecd) 81 { 82 *eecd = *eecd | IGC_EECD_SK; 83 IGC_WRITE_REG(hw, IGC_EECD, *eecd); 84 IGC_WRITE_FLUSH(hw); 85 usec_delay(hw->nvm.delay_usec); 86 } 87 88 /** 89 * igc_lower_eec_clk - Lower EEPROM clock 90 * @hw: pointer to the HW structure 91 * @eecd: pointer to the EEPROM 92 * 93 * Clear/Lower the EEPROM clock bit. 94 **/ 95 static void igc_lower_eec_clk(struct igc_hw *hw, u32 *eecd) 96 { 97 *eecd = *eecd & ~IGC_EECD_SK; 98 IGC_WRITE_REG(hw, IGC_EECD, *eecd); 99 IGC_WRITE_FLUSH(hw); 100 usec_delay(hw->nvm.delay_usec); 101 } 102 103 /** 104 * igc_shift_out_eec_bits - Shift data bits our to the EEPROM 105 * @hw: pointer to the HW structure 106 * @data: data to send to the EEPROM 107 * @count: number of bits to shift out 108 * 109 * We need to shift 'count' bits out to the EEPROM. So, the value in the 110 * "data" parameter will be shifted out to the EEPROM one bit at a time. 111 * In order to do this, "data" must be broken down into bits. 112 **/ 113 static void igc_shift_out_eec_bits(struct igc_hw *hw, u16 data, u16 count) 114 { 115 struct igc_nvm_info *nvm = &hw->nvm; 116 u32 eecd = IGC_READ_REG(hw, IGC_EECD); 117 u32 mask; 118 119 DEBUGFUNC("igc_shift_out_eec_bits"); 120 121 mask = 0x01 << (count - 1); 122 if (nvm->type == igc_nvm_eeprom_spi) 123 eecd |= IGC_EECD_DO; 124 125 do { 126 eecd &= ~IGC_EECD_DI; 127 128 if (data & mask) 129 eecd |= IGC_EECD_DI; 130 131 IGC_WRITE_REG(hw, IGC_EECD, eecd); 132 IGC_WRITE_FLUSH(hw); 133 134 usec_delay(nvm->delay_usec); 135 136 igc_raise_eec_clk(hw, &eecd); 137 igc_lower_eec_clk(hw, &eecd); 138 139 mask >>= 1; 140 } while (mask); 141 142 eecd &= ~IGC_EECD_DI; 143 IGC_WRITE_REG(hw, IGC_EECD, eecd); 144 } 145 146 /** 147 * igc_shift_in_eec_bits - Shift data bits in from the EEPROM 148 * @hw: pointer to the HW structure 149 * @count: number of bits to shift in 150 * 151 * In order to read a register from the EEPROM, we need to shift 'count' bits 152 * in from the EEPROM. Bits are "shifted in" by raising the clock input to 153 * the EEPROM (setting the SK bit), and then reading the value of the data out 154 * "DO" bit. During this "shifting in" process the data in "DI" bit should 155 * always be clear. 156 **/ 157 static u16 igc_shift_in_eec_bits(struct igc_hw *hw, u16 count) 158 { 159 u32 eecd; 160 u32 i; 161 u16 data; 162 163 DEBUGFUNC("igc_shift_in_eec_bits"); 164 165 eecd = IGC_READ_REG(hw, IGC_EECD); 166 167 eecd &= ~(IGC_EECD_DO | IGC_EECD_DI); 168 data = 0; 169 170 for (i = 0; i < count; i++) { 171 data <<= 1; 172 igc_raise_eec_clk(hw, &eecd); 173 174 eecd = IGC_READ_REG(hw, IGC_EECD); 175 176 eecd &= ~IGC_EECD_DI; 177 if (eecd & IGC_EECD_DO) 178 data |= 1; 179 180 igc_lower_eec_clk(hw, &eecd); 181 } 182 183 return data; 184 } 185 186 /** 187 * igc_poll_eerd_eewr_done - Poll for EEPROM read/write completion 188 * @hw: pointer to the HW structure 189 * @ee_reg: EEPROM flag for polling 190 * 191 * Polls the EEPROM status bit for either read or write completion based 192 * upon the value of 'ee_reg'. 193 **/ 194 s32 igc_poll_eerd_eewr_done(struct igc_hw *hw, int ee_reg) 195 { 196 u32 attempts = 100000; 197 u32 i, reg = 0; 198 199 DEBUGFUNC("igc_poll_eerd_eewr_done"); 200 201 for (i = 0; i < attempts; i++) { 202 if (ee_reg == IGC_NVM_POLL_READ) 203 reg = IGC_READ_REG(hw, IGC_EERD); 204 else 205 reg = IGC_READ_REG(hw, IGC_EEWR); 206 207 if (reg & IGC_NVM_RW_REG_DONE) 208 return IGC_SUCCESS; 209 210 usec_delay(5); 211 } 212 213 return -IGC_ERR_NVM; 214 } 215 216 /** 217 * igc_acquire_nvm_generic - Generic request for access to EEPROM 218 * @hw: pointer to the HW structure 219 * 220 * Set the EEPROM access request bit and wait for EEPROM access grant bit. 221 * Return successful if access grant bit set, else clear the request for 222 * EEPROM access and return -IGC_ERR_NVM (-1). 223 **/ 224 s32 igc_acquire_nvm_generic(struct igc_hw *hw) 225 { 226 u32 eecd = IGC_READ_REG(hw, IGC_EECD); 227 s32 timeout = IGC_NVM_GRANT_ATTEMPTS; 228 229 DEBUGFUNC("igc_acquire_nvm_generic"); 230 231 IGC_WRITE_REG(hw, IGC_EECD, eecd | IGC_EECD_REQ); 232 eecd = IGC_READ_REG(hw, IGC_EECD); 233 234 while (timeout) { 235 if (eecd & IGC_EECD_GNT) 236 break; 237 usec_delay(5); 238 eecd = IGC_READ_REG(hw, IGC_EECD); 239 timeout--; 240 } 241 242 if (!timeout) { 243 eecd &= ~IGC_EECD_REQ; 244 IGC_WRITE_REG(hw, IGC_EECD, eecd); 245 DEBUGOUT("Could not acquire NVM grant\n"); 246 return -IGC_ERR_NVM; 247 } 248 249 return IGC_SUCCESS; 250 } 251 252 /** 253 * igc_standby_nvm - Return EEPROM to standby state 254 * @hw: pointer to the HW structure 255 * 256 * Return the EEPROM to a standby state. 257 **/ 258 static void igc_standby_nvm(struct igc_hw *hw) 259 { 260 struct igc_nvm_info *nvm = &hw->nvm; 261 u32 eecd = IGC_READ_REG(hw, IGC_EECD); 262 263 DEBUGFUNC("igc_standby_nvm"); 264 265 if (nvm->type == igc_nvm_eeprom_spi) { 266 /* Toggle CS to flush commands */ 267 eecd |= IGC_EECD_CS; 268 IGC_WRITE_REG(hw, IGC_EECD, eecd); 269 IGC_WRITE_FLUSH(hw); 270 usec_delay(nvm->delay_usec); 271 eecd &= ~IGC_EECD_CS; 272 IGC_WRITE_REG(hw, IGC_EECD, eecd); 273 IGC_WRITE_FLUSH(hw); 274 usec_delay(nvm->delay_usec); 275 } 276 } 277 278 /** 279 * igc_stop_nvm - Terminate EEPROM command 280 * @hw: pointer to the HW structure 281 * 282 * Terminates the current command by inverting the EEPROM's chip select pin. 283 **/ 284 static void igc_stop_nvm(struct igc_hw *hw) 285 { 286 u32 eecd; 287 288 DEBUGFUNC("igc_stop_nvm"); 289 290 eecd = IGC_READ_REG(hw, IGC_EECD); 291 if (hw->nvm.type == igc_nvm_eeprom_spi) { 292 /* Pull CS high */ 293 eecd |= IGC_EECD_CS; 294 igc_lower_eec_clk(hw, &eecd); 295 } 296 } 297 298 /** 299 * igc_release_nvm_generic - Release exclusive access to EEPROM 300 * @hw: pointer to the HW structure 301 * 302 * Stop any current commands to the EEPROM and clear the EEPROM request bit. 303 **/ 304 void igc_release_nvm_generic(struct igc_hw *hw) 305 { 306 u32 eecd; 307 308 DEBUGFUNC("igc_release_nvm_generic"); 309 310 igc_stop_nvm(hw); 311 312 eecd = IGC_READ_REG(hw, IGC_EECD); 313 eecd &= ~IGC_EECD_REQ; 314 IGC_WRITE_REG(hw, IGC_EECD, eecd); 315 } 316 317 /** 318 * igc_ready_nvm_eeprom - Prepares EEPROM for read/write 319 * @hw: pointer to the HW structure 320 * 321 * Setups the EEPROM for reading and writing. 322 **/ 323 static s32 igc_ready_nvm_eeprom(struct igc_hw *hw) 324 { 325 struct igc_nvm_info *nvm = &hw->nvm; 326 u32 eecd = IGC_READ_REG(hw, IGC_EECD); 327 u8 spi_stat_reg; 328 329 DEBUGFUNC("igc_ready_nvm_eeprom"); 330 331 if (nvm->type == igc_nvm_eeprom_spi) { 332 u16 timeout = NVM_MAX_RETRY_SPI; 333 334 /* Clear SK and CS */ 335 eecd &= ~(IGC_EECD_CS | IGC_EECD_SK); 336 IGC_WRITE_REG(hw, IGC_EECD, eecd); 337 IGC_WRITE_FLUSH(hw); 338 usec_delay(1); 339 340 /* Read "Status Register" repeatedly until the LSB is cleared. 341 * The EEPROM will signal that the command has been completed 342 * by clearing bit 0 of the internal status register. If it's 343 * not cleared within 'timeout', then error out. 344 */ 345 while (timeout) { 346 igc_shift_out_eec_bits(hw, NVM_RDSR_OPCODE_SPI, 347 hw->nvm.opcode_bits); 348 spi_stat_reg = (u8)igc_shift_in_eec_bits(hw, 8); 349 if (!(spi_stat_reg & NVM_STATUS_RDY_SPI)) 350 break; 351 352 usec_delay(5); 353 igc_standby_nvm(hw); 354 timeout--; 355 } 356 357 if (!timeout) { 358 DEBUGOUT("SPI NVM Status error\n"); 359 return -IGC_ERR_NVM; 360 } 361 } 362 363 return IGC_SUCCESS; 364 } 365 366 /** 367 * igc_read_nvm_eerd - Reads EEPROM using EERD register 368 * @hw: pointer to the HW structure 369 * @offset: offset of word in the EEPROM to read 370 * @words: number of words to read 371 * @data: word read from the EEPROM 372 * 373 * Reads a 16 bit word from the EEPROM using the EERD register. 374 **/ 375 s32 igc_read_nvm_eerd(struct igc_hw *hw, u16 offset, u16 words, u16 *data) 376 { 377 struct igc_nvm_info *nvm = &hw->nvm; 378 u32 i, eerd = 0; 379 s32 ret_val = IGC_SUCCESS; 380 381 DEBUGFUNC("igc_read_nvm_eerd"); 382 383 /* A check for invalid values: offset too large, too many words, 384 * too many words for the offset, and not enough words. 385 */ 386 if ((offset >= nvm->word_size) || (words > (nvm->word_size - offset)) || 387 (words == 0)) { 388 DEBUGOUT("nvm parameter(s) out of bounds\n"); 389 return -IGC_ERR_NVM; 390 } 391 392 for (i = 0; i < words; i++) { 393 eerd = ((offset + i) << IGC_NVM_RW_ADDR_SHIFT) + 394 IGC_NVM_RW_REG_START; 395 396 IGC_WRITE_REG(hw, IGC_EERD, eerd); 397 ret_val = igc_poll_eerd_eewr_done(hw, IGC_NVM_POLL_READ); 398 if (ret_val) 399 break; 400 401 data[i] = (IGC_READ_REG(hw, IGC_EERD) >> 402 IGC_NVM_RW_REG_DATA); 403 } 404 405 if (ret_val) 406 DEBUGOUT1("NVM read error: %d\n", ret_val); 407 408 return ret_val; 409 } 410 411 /** 412 * igc_write_nvm_spi - Write to EEPROM using SPI 413 * @hw: pointer to the HW structure 414 * @offset: offset within the EEPROM to be written to 415 * @words: number of words to write 416 * @data: 16 bit word(s) to be written to the EEPROM 417 * 418 * Writes data to EEPROM at offset using SPI interface. 419 * 420 * If igc_update_nvm_checksum is not called after this function , the 421 * EEPROM will most likely contain an invalid checksum. 422 **/ 423 s32 igc_write_nvm_spi(struct igc_hw *hw, u16 offset, u16 words, u16 *data) 424 { 425 struct igc_nvm_info *nvm = &hw->nvm; 426 s32 ret_val = -IGC_ERR_NVM; 427 u16 widx = 0; 428 429 DEBUGFUNC("igc_write_nvm_spi"); 430 431 /* A check for invalid values: offset too large, too many words, 432 * and not enough words. 433 */ 434 if ((offset >= nvm->word_size) || (words > (nvm->word_size - offset)) || 435 (words == 0)) { 436 DEBUGOUT("nvm parameter(s) out of bounds\n"); 437 return -IGC_ERR_NVM; 438 } 439 440 while (widx < words) { 441 u8 write_opcode = NVM_WRITE_OPCODE_SPI; 442 443 ret_val = nvm->ops.acquire(hw); 444 if (ret_val) 445 return ret_val; 446 447 ret_val = igc_ready_nvm_eeprom(hw); 448 if (ret_val) { 449 nvm->ops.release(hw); 450 return ret_val; 451 } 452 453 igc_standby_nvm(hw); 454 455 /* Send the WRITE ENABLE command (8 bit opcode) */ 456 igc_shift_out_eec_bits(hw, NVM_WREN_OPCODE_SPI, 457 nvm->opcode_bits); 458 459 igc_standby_nvm(hw); 460 461 /* Some SPI eeproms use the 8th address bit embedded in the 462 * opcode 463 */ 464 if ((nvm->address_bits == 8) && (offset >= 128)) 465 write_opcode |= NVM_A8_OPCODE_SPI; 466 467 /* Send the Write command (8-bit opcode + addr) */ 468 igc_shift_out_eec_bits(hw, write_opcode, nvm->opcode_bits); 469 igc_shift_out_eec_bits(hw, (u16)((offset + widx) * 2), 470 nvm->address_bits); 471 472 /* Loop to allow for up to whole page write of eeprom */ 473 while (widx < words) { 474 u16 word_out = data[widx]; 475 word_out = (word_out >> 8) | (word_out << 8); 476 igc_shift_out_eec_bits(hw, word_out, 16); 477 widx++; 478 479 if ((((offset + widx) * 2) % nvm->page_size) == 0) { 480 igc_standby_nvm(hw); 481 break; 482 } 483 } 484 msec_delay(10); 485 nvm->ops.release(hw); 486 } 487 488 return ret_val; 489 } 490 491 /** 492 * igc_read_pba_string_generic - Read device part number 493 * @hw: pointer to the HW structure 494 * @pba_num: pointer to device part number 495 * @pba_num_size: size of part number buffer 496 * 497 * Reads the product board assembly (PBA) number from the EEPROM and stores 498 * the value in pba_num. 499 **/ 500 s32 igc_read_pba_string_generic(struct igc_hw *hw, u8 *pba_num, 501 u32 pba_num_size) 502 { 503 s32 ret_val; 504 u16 nvm_data; 505 u16 pba_ptr; 506 u16 offset; 507 u16 length; 508 509 DEBUGFUNC("igc_read_pba_string_generic"); 510 511 if (pba_num == NULL) { 512 DEBUGOUT("PBA string buffer was null\n"); 513 return -IGC_ERR_INVALID_ARGUMENT; 514 } 515 516 ret_val = hw->nvm.ops.read(hw, NVM_PBA_OFFSET_0, 1, &nvm_data); 517 if (ret_val) { 518 DEBUGOUT("NVM Read Error\n"); 519 return ret_val; 520 } 521 522 ret_val = hw->nvm.ops.read(hw, NVM_PBA_OFFSET_1, 1, &pba_ptr); 523 if (ret_val) { 524 DEBUGOUT("NVM Read Error\n"); 525 return ret_val; 526 } 527 528 /* if nvm_data is not ptr guard the PBA must be in legacy format which 529 * means pba_ptr is actually our second data word for the PBA number 530 * and we can decode it into an ascii string 531 */ 532 if (nvm_data != NVM_PBA_PTR_GUARD) { 533 DEBUGOUT("NVM PBA number is not stored as string\n"); 534 535 /* make sure callers buffer is big enough to store the PBA */ 536 if (pba_num_size < IGC_PBANUM_LENGTH) { 537 DEBUGOUT("PBA string buffer too small\n"); 538 return IGC_ERR_NO_SPACE; 539 } 540 541 /* extract hex string from data and pba_ptr */ 542 pba_num[0] = (nvm_data >> 12) & 0xF; 543 pba_num[1] = (nvm_data >> 8) & 0xF; 544 pba_num[2] = (nvm_data >> 4) & 0xF; 545 pba_num[3] = nvm_data & 0xF; 546 pba_num[4] = (pba_ptr >> 12) & 0xF; 547 pba_num[5] = (pba_ptr >> 8) & 0xF; 548 pba_num[6] = '-'; 549 pba_num[7] = 0; 550 pba_num[8] = (pba_ptr >> 4) & 0xF; 551 pba_num[9] = pba_ptr & 0xF; 552 553 /* put a null character on the end of our string */ 554 pba_num[10] = '\0'; 555 556 /* switch all the data but the '-' to hex char */ 557 for (offset = 0; offset < 10; offset++) { 558 if (pba_num[offset] < 0xA) 559 pba_num[offset] += '0'; 560 else if (pba_num[offset] < 0x10) 561 pba_num[offset] += 'A' - 0xA; 562 } 563 564 return IGC_SUCCESS; 565 } 566 567 ret_val = hw->nvm.ops.read(hw, pba_ptr, 1, &length); 568 if (ret_val) { 569 DEBUGOUT("NVM Read Error\n"); 570 return ret_val; 571 } 572 573 if (length == 0xFFFF || length == 0) { 574 DEBUGOUT("NVM PBA number section invalid length\n"); 575 return -IGC_ERR_NVM_PBA_SECTION; 576 } 577 /* check if pba_num buffer is big enough */ 578 if (pba_num_size < (((u32)length * 2) - 1)) { 579 DEBUGOUT("PBA string buffer too small\n"); 580 return -IGC_ERR_NO_SPACE; 581 } 582 583 /* trim pba length from start of string */ 584 pba_ptr++; 585 length--; 586 587 for (offset = 0; offset < length; offset++) { 588 ret_val = hw->nvm.ops.read(hw, pba_ptr + offset, 1, &nvm_data); 589 if (ret_val) { 590 DEBUGOUT("NVM Read Error\n"); 591 return ret_val; 592 } 593 pba_num[offset * 2] = (u8)(nvm_data >> 8); 594 pba_num[(offset * 2) + 1] = (u8)(nvm_data & 0xFF); 595 } 596 pba_num[offset * 2] = '\0'; 597 598 return IGC_SUCCESS; 599 } 600 601 602 603 604 605 /** 606 * igc_read_mac_addr_generic - Read device MAC address 607 * @hw: pointer to the HW structure 608 * 609 * Reads the device MAC address from the EEPROM and stores the value. 610 * Since devices with two ports use the same EEPROM, we increment the 611 * last bit in the MAC address for the second port. 612 **/ 613 s32 igc_read_mac_addr_generic(struct igc_hw *hw) 614 { 615 u32 rar_high; 616 u32 rar_low; 617 u16 i; 618 619 rar_high = IGC_READ_REG(hw, IGC_RAH(0)); 620 rar_low = IGC_READ_REG(hw, IGC_RAL(0)); 621 622 for (i = 0; i < IGC_RAL_MAC_ADDR_LEN; i++) 623 hw->mac.perm_addr[i] = (u8)(rar_low >> (i*8)); 624 625 for (i = 0; i < IGC_RAH_MAC_ADDR_LEN; i++) 626 hw->mac.perm_addr[i+4] = (u8)(rar_high >> (i*8)); 627 628 for (i = 0; i < ETH_ADDR_LEN; i++) 629 hw->mac.addr[i] = hw->mac.perm_addr[i]; 630 631 return IGC_SUCCESS; 632 } 633 634 /** 635 * igc_validate_nvm_checksum_generic - Validate EEPROM checksum 636 * @hw: pointer to the HW structure 637 * 638 * Calculates the EEPROM checksum by reading/adding each word of the EEPROM 639 * and then verifies that the sum of the EEPROM is equal to 0xBABA. 640 **/ 641 s32 igc_validate_nvm_checksum_generic(struct igc_hw *hw) 642 { 643 s32 ret_val; 644 u16 checksum = 0; 645 u16 i, nvm_data; 646 647 DEBUGFUNC("igc_validate_nvm_checksum_generic"); 648 649 for (i = 0; i < (NVM_CHECKSUM_REG + 1); i++) { 650 ret_val = hw->nvm.ops.read(hw, i, 1, &nvm_data); 651 if (ret_val) { 652 DEBUGOUT("NVM Read Error\n"); 653 return ret_val; 654 } 655 checksum += nvm_data; 656 } 657 658 if (checksum != (u16) NVM_SUM) { 659 DEBUGOUT("NVM Checksum Invalid\n"); 660 return -IGC_ERR_NVM; 661 } 662 663 return IGC_SUCCESS; 664 } 665 666 /** 667 * igc_update_nvm_checksum_generic - Update EEPROM checksum 668 * @hw: pointer to the HW structure 669 * 670 * Updates the EEPROM checksum by reading/adding each word of the EEPROM 671 * up to the checksum. Then calculates the EEPROM checksum and writes the 672 * value to the EEPROM. 673 **/ 674 s32 igc_update_nvm_checksum_generic(struct igc_hw *hw) 675 { 676 s32 ret_val; 677 u16 checksum = 0; 678 u16 i, nvm_data; 679 680 DEBUGFUNC("igc_update_nvm_checksum"); 681 682 for (i = 0; i < NVM_CHECKSUM_REG; i++) { 683 ret_val = hw->nvm.ops.read(hw, i, 1, &nvm_data); 684 if (ret_val) { 685 DEBUGOUT("NVM Read Error while updating checksum.\n"); 686 return ret_val; 687 } 688 checksum += nvm_data; 689 } 690 checksum = (u16) NVM_SUM - checksum; 691 ret_val = hw->nvm.ops.write(hw, NVM_CHECKSUM_REG, 1, &checksum); 692 if (ret_val) 693 DEBUGOUT("NVM Write Error while updating checksum.\n"); 694 695 return ret_val; 696 } 697 698 /** 699 * igc_reload_nvm_generic - Reloads EEPROM 700 * @hw: pointer to the HW structure 701 * 702 * Reloads the EEPROM by setting the "Reinitialize from EEPROM" bit in the 703 * extended control register. 704 **/ 705 static void igc_reload_nvm_generic(struct igc_hw *hw) 706 { 707 u32 ctrl_ext; 708 709 DEBUGFUNC("igc_reload_nvm_generic"); 710 711 usec_delay(10); 712 ctrl_ext = IGC_READ_REG(hw, IGC_CTRL_EXT); 713 ctrl_ext |= IGC_CTRL_EXT_EE_RST; 714 IGC_WRITE_REG(hw, IGC_CTRL_EXT, ctrl_ext); 715 IGC_WRITE_FLUSH(hw); 716 } 717 718 719