1 /* 2 * mr_sas.h: header for mr_sas 3 * 4 * Solaris MegaRAID driver for SAS2.0 controllers 5 * Copyright (c) 2008-2009, LSI Logic Corporation. 6 * All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions are met: 10 * 11 * 1. Redistributions of source code must retain the above copyright notice, 12 * this list of conditions and the following disclaimer. 13 * 14 * 2. Redistributions in binary form must reproduce the above copyright notice, 15 * this list of conditions and the following disclaimer in the documentation 16 * and/or other materials provided with the distribution. 17 * 18 * 3. Neither the name of the author nor the names of its contributors may be 19 * used to endorse or promote products derived from this software without 20 * specific prior written permission. 21 * 22 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 23 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 24 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS 25 * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE 26 * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, 27 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, 28 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS 29 * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED 30 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 31 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT 32 * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH 33 * DAMAGE. 34 */ 35 36 /* 37 * Copyright 2010 Sun Microsystems, Inc. All rights reserved. 38 * Use is subject to license terms. 39 */ 40 #ifndef _MR_SAS_H_ 41 #define _MR_SAS_H_ 42 43 #ifdef __cplusplus 44 extern "C" { 45 #endif 46 47 #include <sys/scsi/scsi.h> 48 #include "mr_sas_list.h" 49 50 /* 51 * MegaRAID SAS2.0 Driver meta data 52 */ 53 #define MRSAS_VERSION "LSIv2.4" 54 #define MRSAS_RELDATE "Feb 28, 2010" 55 56 #define MRSAS_TRUE 1 57 #define MRSAS_FALSE 0 58 59 /* 60 * MegaRAID SAS2.0 device id conversion definitions. 61 */ 62 #define INST2LSIRDCTL(x) ((x) << INST_MINOR_SHIFT) 63 64 /* 65 * MegaRAID SAS2.0 supported controllers 66 */ 67 #define PCI_DEVICE_ID_LSI_2108VDE 0x0078 68 #define PCI_DEVICE_ID_LSI_2108V 0x0079 69 70 /* 71 * Register Index for 2108 Controllers. 72 */ 73 #define REGISTER_SET_IO_2108 (2) 74 75 #define MRSAS_MAX_SGE_CNT 0x50 76 77 #define MRSAS_IOCTL_DRIVER 0x12341234 78 #define MRSAS_IOCTL_FIRMWARE 0x12345678 79 #define MRSAS_IOCTL_AEN 0x87654321 80 81 #define MRSAS_1_SECOND 1000000 82 83 /* Dynamic Enumeration Flags */ 84 #define MRSAS_PD_LUN 1 85 #define MRSAS_LD_LUN 0 86 #define MRSAS_PD_TGT_MAX 255 87 #define MRSAS_GET_PD_MAX(s) ((s)->mr_pd_max) 88 #define WWN_STRLEN 17 89 90 /* 91 * ===================================== 92 * MegaRAID SAS2.0 MFI firmware definitions 93 * ===================================== 94 */ 95 /* 96 * MFI stands for MegaRAID SAS2.0 FW Interface. This is just a moniker for 97 * protocol between the software and firmware. Commands are issued using 98 * "message frames" 99 */ 100 101 /* 102 * FW posts its state in upper 4 bits of outbound_msg_0 register 103 */ 104 #define MFI_STATE_SHIFT 28 105 #define MFI_STATE_MASK ((uint32_t)0xF<<MFI_STATE_SHIFT) 106 #define MFI_STATE_UNDEFINED ((uint32_t)0x0<<MFI_STATE_SHIFT) 107 #define MFI_STATE_BB_INIT ((uint32_t)0x1<<MFI_STATE_SHIFT) 108 #define MFI_STATE_FW_INIT ((uint32_t)0x4<<MFI_STATE_SHIFT) 109 #define MFI_STATE_WAIT_HANDSHAKE ((uint32_t)0x6<<MFI_STATE_SHIFT) 110 #define MFI_STATE_FW_INIT_2 ((uint32_t)0x7<<MFI_STATE_SHIFT) 111 #define MFI_STATE_DEVICE_SCAN ((uint32_t)0x8<<MFI_STATE_SHIFT) 112 #define MFI_STATE_BOOT_MESSAGE_PENDING ((uint32_t)0x9<<MFI_STATE_SHIFT) 113 #define MFI_STATE_FLUSH_CACHE ((uint32_t)0xA<<MFI_STATE_SHIFT) 114 #define MFI_STATE_READY ((uint32_t)0xB<<MFI_STATE_SHIFT) 115 #define MFI_STATE_OPERATIONAL ((uint32_t)0xC<<MFI_STATE_SHIFT) 116 #define MFI_STATE_FAULT ((uint32_t)0xF<<MFI_STATE_SHIFT) 117 118 #define MRMFI_FRAME_SIZE 64 119 120 /* 121 * During FW init, clear pending cmds & reset state using inbound_msg_0 122 * 123 * ABORT : Abort all pending cmds 124 * READY : Move from OPERATIONAL to READY state; discard queue info 125 * MFIMODE : Discard (possible) low MFA posted in 64-bit mode (??) 126 * CLR_HANDSHAKE: FW is waiting for HANDSHAKE from BIOS or Driver 127 */ 128 #define MFI_INIT_ABORT 0x00000001 129 #define MFI_INIT_READY 0x00000002 130 #define MFI_INIT_MFIMODE 0x00000004 131 #define MFI_INIT_CLEAR_HANDSHAKE 0x00000008 132 #define MFI_INIT_HOTPLUG 0x00000010 133 #define MFI_STOP_ADP 0x00000020 134 #define MFI_RESET_FLAGS MFI_INIT_READY|MFI_INIT_MFIMODE|MFI_INIT_ABORT 135 136 /* 137 * MFI frame flags 138 */ 139 #define MFI_FRAME_POST_IN_REPLY_QUEUE 0x0000 140 #define MFI_FRAME_DONT_POST_IN_REPLY_QUEUE 0x0001 141 #define MFI_FRAME_SGL32 0x0000 142 #define MFI_FRAME_SGL64 0x0002 143 #define MFI_FRAME_SENSE32 0x0000 144 #define MFI_FRAME_SENSE64 0x0004 145 #define MFI_FRAME_DIR_NONE 0x0000 146 #define MFI_FRAME_DIR_WRITE 0x0008 147 #define MFI_FRAME_DIR_READ 0x0010 148 #define MFI_FRAME_DIR_BOTH 0x0018 149 #define MFI_FRAME_IEEE 0x0020 150 151 /* 152 * Definition for cmd_status 153 */ 154 #define MFI_CMD_STATUS_POLL_MODE 0xFF 155 #define MFI_CMD_STATUS_SYNC_MODE 0xFF 156 157 /* 158 * MFI command opcodes 159 */ 160 #define MFI_CMD_OP_INIT 0x00 161 #define MFI_CMD_OP_LD_READ 0x01 162 #define MFI_CMD_OP_LD_WRITE 0x02 163 #define MFI_CMD_OP_LD_SCSI 0x03 164 #define MFI_CMD_OP_PD_SCSI 0x04 165 #define MFI_CMD_OP_DCMD 0x05 166 #define MFI_CMD_OP_ABORT 0x06 167 #define MFI_CMD_OP_SMP 0x07 168 #define MFI_CMD_OP_STP 0x08 169 170 #define MR_DCMD_CTRL_GET_INFO 0x01010000 171 172 #define MR_DCMD_CTRL_CACHE_FLUSH 0x01101000 173 #define MR_FLUSH_CTRL_CACHE 0x01 174 #define MR_FLUSH_DISK_CACHE 0x02 175 176 #define MR_DCMD_CTRL_SHUTDOWN 0x01050000 177 #define MRSAS_ENABLE_DRIVE_SPINDOWN 0x01 178 179 #define MR_DCMD_CTRL_EVENT_GET_INFO 0x01040100 180 #define MR_DCMD_CTRL_EVENT_GET 0x01040300 181 #define MR_DCMD_CTRL_EVENT_WAIT 0x01040500 182 #define MR_DCMD_LD_GET_PROPERTIES 0x03030000 183 #define MR_DCMD_PD_GET_INFO 0x02020000 184 185 /* 186 * Solaris Specific MAX values 187 */ 188 #define MAX_SGL 24 189 /* 190 * MFI command completion codes 191 */ 192 enum MFI_STAT { 193 MFI_STAT_OK = 0x00, 194 MFI_STAT_INVALID_CMD = 0x01, 195 MFI_STAT_INVALID_DCMD = 0x02, 196 MFI_STAT_INVALID_PARAMETER = 0x03, 197 MFI_STAT_INVALID_SEQUENCE_NUMBER = 0x04, 198 MFI_STAT_ABORT_NOT_POSSIBLE = 0x05, 199 MFI_STAT_APP_HOST_CODE_NOT_FOUND = 0x06, 200 MFI_STAT_APP_IN_USE = 0x07, 201 MFI_STAT_APP_NOT_INITIALIZED = 0x08, 202 MFI_STAT_ARRAY_INDEX_INVALID = 0x09, 203 MFI_STAT_ARRAY_ROW_NOT_EMPTY = 0x0a, 204 MFI_STAT_CONFIG_RESOURCE_CONFLICT = 0x0b, 205 MFI_STAT_DEVICE_NOT_FOUND = 0x0c, 206 MFI_STAT_DRIVE_TOO_SMALL = 0x0d, 207 MFI_STAT_FLASH_ALLOC_FAIL = 0x0e, 208 MFI_STAT_FLASH_BUSY = 0x0f, 209 MFI_STAT_FLASH_ERROR = 0x10, 210 MFI_STAT_FLASH_IMAGE_BAD = 0x11, 211 MFI_STAT_FLASH_IMAGE_INCOMPLETE = 0x12, 212 MFI_STAT_FLASH_NOT_OPEN = 0x13, 213 MFI_STAT_FLASH_NOT_STARTED = 0x14, 214 MFI_STAT_FLUSH_FAILED = 0x15, 215 MFI_STAT_HOST_CODE_NOT_FOUNT = 0x16, 216 MFI_STAT_LD_CC_IN_PROGRESS = 0x17, 217 MFI_STAT_LD_INIT_IN_PROGRESS = 0x18, 218 MFI_STAT_LD_LBA_OUT_OF_RANGE = 0x19, 219 MFI_STAT_LD_MAX_CONFIGURED = 0x1a, 220 MFI_STAT_LD_NOT_OPTIMAL = 0x1b, 221 MFI_STAT_LD_RBLD_IN_PROGRESS = 0x1c, 222 MFI_STAT_LD_RECON_IN_PROGRESS = 0x1d, 223 MFI_STAT_LD_WRONG_RAID_LEVEL = 0x1e, 224 MFI_STAT_MAX_SPARES_EXCEEDED = 0x1f, 225 MFI_STAT_MEMORY_NOT_AVAILABLE = 0x20, 226 MFI_STAT_MFC_HW_ERROR = 0x21, 227 MFI_STAT_NO_HW_PRESENT = 0x22, 228 MFI_STAT_NOT_FOUND = 0x23, 229 MFI_STAT_NOT_IN_ENCL = 0x24, 230 MFI_STAT_PD_CLEAR_IN_PROGRESS = 0x25, 231 MFI_STAT_PD_TYPE_WRONG = 0x26, 232 MFI_STAT_PR_DISABLED = 0x27, 233 MFI_STAT_ROW_INDEX_INVALID = 0x28, 234 MFI_STAT_SAS_CONFIG_INVALID_ACTION = 0x29, 235 MFI_STAT_SAS_CONFIG_INVALID_DATA = 0x2a, 236 MFI_STAT_SAS_CONFIG_INVALID_PAGE = 0x2b, 237 MFI_STAT_SAS_CONFIG_INVALID_TYPE = 0x2c, 238 MFI_STAT_SCSI_DONE_WITH_ERROR = 0x2d, 239 MFI_STAT_SCSI_IO_FAILED = 0x2e, 240 MFI_STAT_SCSI_RESERVATION_CONFLICT = 0x2f, 241 MFI_STAT_SHUTDOWN_FAILED = 0x30, 242 MFI_STAT_TIME_NOT_SET = 0x31, 243 MFI_STAT_WRONG_STATE = 0x32, 244 MFI_STAT_LD_OFFLINE = 0x33, 245 /* UNUSED: 0x34 to 0xfe */ 246 MFI_STAT_INVALID_STATUS = 0xFF 247 }; 248 249 enum MR_EVT_CLASS { 250 MR_EVT_CLASS_DEBUG = -2, 251 MR_EVT_CLASS_PROGRESS = -1, 252 MR_EVT_CLASS_INFO = 0, 253 MR_EVT_CLASS_WARNING = 1, 254 MR_EVT_CLASS_CRITICAL = 2, 255 MR_EVT_CLASS_FATAL = 3, 256 MR_EVT_CLASS_DEAD = 4 257 }; 258 259 enum MR_EVT_LOCALE { 260 MR_EVT_LOCALE_LD = 0x0001, 261 MR_EVT_LOCALE_PD = 0x0002, 262 MR_EVT_LOCALE_ENCL = 0x0004, 263 MR_EVT_LOCALE_BBU = 0x0008, 264 MR_EVT_LOCALE_SAS = 0x0010, 265 MR_EVT_LOCALE_CTRL = 0x0020, 266 MR_EVT_LOCALE_CONFIG = 0x0040, 267 MR_EVT_LOCALE_CLUSTER = 0x0080, 268 MR_EVT_LOCALE_ALL = 0xffff 269 }; 270 271 #define MR_EVT_CFG_CLEARED 0x0004 272 #define MR_EVT_LD_CREATED 0x008a 273 #define MR_EVT_LD_DELETED 0x008b 274 #define MR_EVT_PD_REMOVED_EXT 0x00f8 275 #define MR_EVT_PD_INSERTED_EXT 0x00f7 276 277 enum LD_STATE { 278 LD_OFFLINE = 0, 279 LD_PARTIALLY_DEGRADED = 1, 280 LD_DEGRADED = 2, 281 LD_OPTIMAL = 3, 282 LD_INVALID = 0xFF 283 }; 284 285 enum MRSAS_EVT { 286 MRSAS_EVT_CONFIG_TGT = 0, 287 MRSAS_EVT_UNCONFIG_TGT = 1, 288 MRSAS_EVT_UNCONFIG_SMP = 2 289 }; 290 291 #define DMA_OBJ_ALLOCATED 1 292 #define DMA_OBJ_REALLOCATED 2 293 #define DMA_OBJ_FREED 3 294 295 /* 296 * dma_obj_t - Our DMA object 297 * @param buffer : kernel virtual address 298 * @param size : size of the data to be allocated 299 * @param acc_handle : access handle 300 * @param dma_handle : dma handle 301 * @param dma_cookie : scatter-gather list 302 * @param dma_attr : dma attributes for this buffer 303 * Our DMA object. The caller must initialize the size and dma attributes 304 * (dma_attr) fields before allocating the resources. 305 */ 306 typedef struct { 307 caddr_t buffer; 308 uint32_t size; 309 ddi_acc_handle_t acc_handle; 310 ddi_dma_handle_t dma_handle; 311 ddi_dma_cookie_t dma_cookie[MRSAS_MAX_SGE_CNT]; 312 ddi_dma_attr_t dma_attr; 313 uint8_t status; 314 uint8_t reserved[3]; 315 } dma_obj_t; 316 317 struct mrsas_eventinfo { 318 struct mrsas_instance *instance; 319 int tgt; 320 int lun; 321 int event; 322 }; 323 324 struct mrsas_ld { 325 dev_info_t *dip; 326 uint8_t lun_type; 327 uint8_t reserved[3]; 328 }; 329 330 struct mrsas_pd { 331 dev_info_t *dip; 332 uint8_t lun_type; 333 uint8_t dev_id; 334 uint8_t flags; 335 uint8_t reserved; 336 }; 337 338 struct mrsas_pd_info { 339 uint16_t deviceId; 340 uint16_t seqNum; 341 uint8_t inquiryData[96]; 342 uint8_t vpdPage83[64]; 343 uint8_t notSupported; 344 uint8_t scsiDevType; 345 uint8_t a; 346 uint8_t device_speed; 347 uint32_t mediaerrcnt; 348 uint32_t other; 349 uint32_t pred; 350 uint32_t lastpred; 351 uint16_t fwState; 352 uint8_t disabled; 353 uint8_t linkspwwd; 354 uint32_t ddfType; 355 struct { 356 uint8_t count; 357 uint8_t isPathBroken; 358 uint8_t connectorIndex[2]; 359 uint8_t reserved[4]; 360 uint64_t sasAddr[2]; 361 uint8_t reserved2[16]; 362 } pathInfo; 363 }; 364 365 typedef struct mrsas_instance { 366 uint32_t *producer; 367 uint32_t *consumer; 368 369 uint32_t *reply_queue; 370 dma_obj_t mfi_internal_dma_obj; 371 372 uint8_t init_id; 373 uint8_t flag_ieee; 374 uint8_t reserved[2]; 375 376 uint16_t max_num_sge; 377 uint16_t max_fw_cmds; 378 uint32_t max_sectors_per_req; 379 380 struct mrsas_cmd **cmd_list; 381 382 mlist_t cmd_pool_list; 383 kmutex_t cmd_pool_mtx; 384 385 mlist_t cmd_pend_list; 386 kmutex_t cmd_pend_mtx; 387 388 dma_obj_t mfi_evt_detail_obj; 389 struct mrsas_cmd *aen_cmd; 390 391 uint32_t aen_seq_num; 392 uint32_t aen_class_locale_word; 393 394 scsi_hba_tran_t *tran; 395 396 kcondvar_t int_cmd_cv; 397 kmutex_t int_cmd_mtx; 398 399 kcondvar_t aen_cmd_cv; 400 kmutex_t aen_cmd_mtx; 401 402 kcondvar_t abort_cmd_cv; 403 kmutex_t abort_cmd_mtx; 404 405 dev_info_t *dip; 406 ddi_acc_handle_t pci_handle; 407 408 timeout_id_t timeout_id; 409 uint32_t unique_id; 410 uint16_t fw_outstanding; 411 caddr_t regmap; 412 ddi_acc_handle_t regmap_handle; 413 uint8_t isr_level; 414 ddi_iblock_cookie_t iblock_cookie; 415 ddi_iblock_cookie_t soft_iblock_cookie; 416 ddi_softintr_t soft_intr_id; 417 uint8_t softint_running; 418 kmutex_t completed_pool_mtx; 419 mlist_t completed_pool_list; 420 421 caddr_t internal_buf; 422 uint32_t internal_buf_dmac_add; 423 uint32_t internal_buf_size; 424 425 uint16_t vendor_id; 426 uint16_t device_id; 427 uint16_t subsysvid; 428 uint16_t subsysid; 429 int instance; 430 int baseaddress; 431 char iocnode[16]; 432 433 int fm_capabilities; 434 435 struct mrsas_func_ptr *func_ptr; 436 /* MSI interrupts specific */ 437 ddi_intr_handle_t *intr_htable; 438 int intr_type; 439 int intr_cnt; 440 size_t intr_size; 441 uint_t intr_pri; 442 int intr_cap; 443 444 ddi_taskq_t *taskq; 445 struct mrsas_ld *mr_ld_list; 446 } mrsas_t; 447 448 struct mrsas_func_ptr { 449 int (*read_fw_status_reg)(struct mrsas_instance *); 450 void (*issue_cmd)(struct mrsas_cmd *, struct mrsas_instance *); 451 int (*issue_cmd_in_sync_mode)(struct mrsas_instance *, 452 struct mrsas_cmd *); 453 int (*issue_cmd_in_poll_mode)(struct mrsas_instance *, 454 struct mrsas_cmd *); 455 void (*enable_intr)(struct mrsas_instance *); 456 void (*disable_intr)(struct mrsas_instance *); 457 int (*intr_ack)(struct mrsas_instance *); 458 }; 459 460 /* 461 * ### Helper routines ### 462 */ 463 464 /* 465 * con_log() - console log routine 466 * @param level : indicates the severity of the message. 467 * @fparam mt : format string 468 * 469 * con_log displays the error messages on the console based on the current 470 * debug level. Also it attaches the appropriate kernel severity level with 471 * the message. 472 * 473 * 474 * console messages debug levels 475 */ 476 #define CL_NONE 0 /* No debug information */ 477 #define CL_ANN 1 /* print unconditionally, announcements */ 478 #define CL_ANN1 2 /* No o/p */ 479 #define CL_DLEVEL1 3 /* debug level 1, informative */ 480 #define CL_DLEVEL2 4 /* debug level 2, verbose */ 481 #define CL_DLEVEL3 5 /* debug level 3, very verbose */ 482 483 #ifdef __SUNPRO_C 484 #define __func__ "" 485 #endif 486 487 #define con_log(level, fmt) { if (debug_level_g >= level) cmn_err fmt; } 488 489 /* 490 * ### SCSA definitions ### 491 */ 492 #define PKT2TGT(pkt) ((pkt)->pkt_address.a_target) 493 #define PKT2LUN(pkt) ((pkt)->pkt_address.a_lun) 494 #define PKT2TRAN(pkt) ((pkt)->pkt_adress.a_hba_tran) 495 #define ADDR2TRAN(ap) ((ap)->a_hba_tran) 496 497 #define TRAN2MR(tran) (struct mrsas_instance *)(tran)->tran_hba_private) 498 #define ADDR2MR(ap) (TRAN2MR(ADDR2TRAN(ap)) 499 500 #define PKT2CMD(pkt) ((struct scsa_cmd *)(pkt)->pkt_ha_private) 501 #define CMD2PKT(sp) ((sp)->cmd_pkt) 502 #define PKT2REQ(pkt) (&(PKT2CMD(pkt)->request)) 503 504 #define CMD2ADDR(cmd) (&CMD2PKT(cmd)->pkt_address) 505 #define CMD2TRAN(cmd) (CMD2PKT(cmd)->pkt_address.a_hba_tran) 506 #define CMD2MR(cmd) (TRAN2MR(CMD2TRAN(cmd))) 507 508 #define CFLAG_DMAVALID 0x0001 /* requires a dma operation */ 509 #define CFLAG_DMASEND 0x0002 /* Transfer from the device */ 510 #define CFLAG_CONSISTENT 0x0040 /* consistent data transfer */ 511 512 /* 513 * ### Data structures for ioctl inteface and internal commands ### 514 */ 515 516 /* 517 * Data direction flags 518 */ 519 #define UIOC_RD 0x00001 520 #define UIOC_WR 0x00002 521 522 #define SCP2HOST(scp) (scp)->device->host /* to host */ 523 #define SCP2HOSTDATA(scp) SCP2HOST(scp)->hostdata /* to soft state */ 524 #define SCP2CHANNEL(scp) (scp)->device->channel /* to channel */ 525 #define SCP2TARGET(scp) (scp)->device->id /* to target */ 526 #define SCP2LUN(scp) (scp)->device->lun /* to LUN */ 527 528 #define SCSIHOST2ADAP(host) (((caddr_t *)(host->hostdata))[0]) 529 #define SCP2ADAPTER(scp) \ 530 (struct mrsas_instance *)SCSIHOST2ADAP(SCP2HOST(scp)) 531 532 #define MRDRV_IS_LOGICAL_SCSA(instance, acmd) \ 533 (acmd->device_id < MRDRV_MAX_LD) ? 1 : 0 534 #define MRDRV_IS_LOGICAL(ap) \ 535 ((ap->a_target < MRDRV_MAX_LD) && (ap->a_lun == 0)) ? 1 : 0 536 #define MAP_DEVICE_ID(instance, ap) \ 537 (ap->a_target) 538 539 #define HIGH_LEVEL_INTR 1 540 #define NORMAL_LEVEL_INTR 0 541 542 /* 543 * scsa_cmd - Per-command mr private data 544 * @param cmd_dmahandle : dma handle 545 * @param cmd_dmacookies : current dma cookies 546 * @param cmd_pkt : scsi_pkt reference 547 * @param cmd_dmacount : dma count 548 * @param cmd_cookie : next cookie 549 * @param cmd_ncookies : cookies per window 550 * @param cmd_cookiecnt : cookies per sub-win 551 * @param cmd_nwin : number of dma windows 552 * @param cmd_curwin : current dma window 553 * @param cmd_dma_offset : current window offset 554 * @param cmd_dma_len : current window length 555 * @param cmd_flags : private flags 556 * @param cmd_cdblen : length of cdb 557 * @param cmd_scblen : length of scb 558 * @param cmd_buf : command buffer 559 * @param channel : channel for scsi sub-system 560 * @param target : target for scsi sub-system 561 * @param lun : LUN for scsi sub-system 562 * 563 * - Allocated at same time as scsi_pkt by scsi_hba_pkt_alloc(9E) 564 * - Pointed to by pkt_ha_private field in scsi_pkt 565 */ 566 struct scsa_cmd { 567 ddi_dma_handle_t cmd_dmahandle; 568 ddi_dma_cookie_t cmd_dmacookies[MRSAS_MAX_SGE_CNT]; 569 struct scsi_pkt *cmd_pkt; 570 ulong_t cmd_dmacount; 571 uint_t cmd_cookie; 572 uint_t cmd_ncookies; 573 uint_t cmd_cookiecnt; 574 uint_t cmd_nwin; 575 uint_t cmd_curwin; 576 off_t cmd_dma_offset; 577 ulong_t cmd_dma_len; 578 ulong_t cmd_flags; 579 uint_t cmd_cdblen; 580 uint_t cmd_scblen; 581 struct buf *cmd_buf; 582 ushort_t device_id; 583 uchar_t islogical; 584 uchar_t lun; 585 struct mrsas_device *mrsas_dev; 586 }; 587 588 589 struct mrsas_cmd { 590 union mrsas_frame *frame; 591 uint32_t frame_phys_addr; 592 uint8_t *sense; 593 uint32_t sense_phys_addr; 594 dma_obj_t frame_dma_obj; 595 uint8_t frame_dma_obj_status; 596 597 uint32_t index; 598 uint8_t sync_cmd; 599 uint8_t cmd_status; 600 uint16_t abort_aen; 601 mlist_t list; 602 uint32_t frame_count; 603 struct scsa_cmd *cmd; 604 struct scsi_pkt *pkt; 605 }; 606 607 #define MAX_MGMT_ADAPTERS 1024 608 #define IOC_SIGNATURE "MR-SAS" 609 610 #define IOC_CMD_FIRMWARE 0x0 611 #define MRSAS_DRIVER_IOCTL_COMMON 0xF0010000 612 #define MRSAS_DRIVER_IOCTL_DRIVER_VERSION 0xF0010100 613 #define MRSAS_DRIVER_IOCTL_PCI_INFORMATION 0xF0010200 614 #define MRSAS_DRIVER_IOCTL_MRRAID_STATISTICS 0xF0010300 615 616 617 #define MRSAS_MAX_SENSE_LENGTH 32 618 619 struct mrsas_mgmt_info { 620 621 uint16_t count; 622 struct mrsas_instance *instance[MAX_MGMT_ADAPTERS]; 623 uint16_t map[MAX_MGMT_ADAPTERS]; 624 int max_index; 625 }; 626 627 #pragma pack(1) 628 629 /* 630 * SAS controller properties 631 */ 632 struct mrsas_ctrl_prop { 633 uint16_t seq_num; 634 uint16_t pred_fail_poll_interval; 635 uint16_t intr_throttle_count; 636 uint16_t intr_throttle_timeouts; 637 638 uint8_t rebuild_rate; 639 uint8_t patrol_read_rate; 640 uint8_t bgi_rate; 641 uint8_t cc_rate; 642 uint8_t recon_rate; 643 644 uint8_t cache_flush_interval; 645 646 uint8_t spinup_drv_count; 647 uint8_t spinup_delay; 648 649 uint8_t cluster_enable; 650 uint8_t coercion_mode; 651 uint8_t disk_write_cache_disable; 652 uint8_t alarm_enable; 653 654 uint8_t reserved[44]; 655 }; 656 657 /* 658 * SAS controller information 659 */ 660 struct mrsas_ctrl_info { 661 /* PCI device information */ 662 struct { 663 uint16_t vendor_id; 664 uint16_t device_id; 665 uint16_t sub_vendor_id; 666 uint16_t sub_device_id; 667 uint8_t reserved[24]; 668 } pci; 669 670 /* Host interface information */ 671 struct { 672 uint8_t PCIX : 1; 673 uint8_t PCIE : 1; 674 uint8_t iSCSI : 1; 675 uint8_t SAS_3G : 1; 676 uint8_t reserved_0 : 4; 677 uint8_t reserved_1[6]; 678 uint8_t port_count; 679 uint64_t port_addr[8]; 680 } host_interface; 681 682 /* Device (backend) interface information */ 683 struct { 684 uint8_t SPI : 1; 685 uint8_t SAS_3G : 1; 686 uint8_t SATA_1_5G : 1; 687 uint8_t SATA_3G : 1; 688 uint8_t reserved_0 : 4; 689 uint8_t reserved_1[6]; 690 uint8_t port_count; 691 uint64_t port_addr[8]; 692 } device_interface; 693 694 /* List of components residing in flash. All str are null terminated */ 695 uint32_t image_check_word; 696 uint32_t image_component_count; 697 698 struct { 699 char name[8]; 700 char version[32]; 701 char build_date[16]; 702 char built_time[16]; 703 } image_component[8]; 704 705 /* 706 * List of flash components that have been flashed on the card, but 707 * are not in use, pending reset of the adapter. This list will be 708 * empty if a flash operation has not occurred. All stings are null 709 * terminated 710 */ 711 uint32_t pending_image_component_count; 712 713 struct { 714 char name[8]; 715 char version[32]; 716 char build_date[16]; 717 char build_time[16]; 718 } pending_image_component[8]; 719 720 uint8_t max_arms; 721 uint8_t max_spans; 722 uint8_t max_arrays; 723 uint8_t max_lds; 724 725 char product_name[80]; 726 char serial_no[32]; 727 728 /* 729 * Other physical/controller/operation information. Indicates the 730 * presence of the hardware 731 */ 732 struct { 733 uint32_t bbu : 1; 734 uint32_t alarm : 1; 735 uint32_t nvram : 1; 736 uint32_t uart : 1; 737 uint32_t reserved : 28; 738 } hw_present; 739 740 uint32_t current_fw_time; 741 742 /* Maximum data transfer sizes */ 743 uint16_t max_concurrent_cmds; 744 uint16_t max_sge_count; 745 uint32_t max_request_size; 746 747 /* Logical and physical device counts */ 748 uint16_t ld_present_count; 749 uint16_t ld_degraded_count; 750 uint16_t ld_offline_count; 751 752 uint16_t pd_present_count; 753 uint16_t pd_disk_present_count; 754 uint16_t pd_disk_pred_failure_count; 755 uint16_t pd_disk_failed_count; 756 757 /* Memory size information */ 758 uint16_t nvram_size; 759 uint16_t memory_size; 760 uint16_t flash_size; 761 762 /* Error counters */ 763 uint16_t mem_correctable_error_count; 764 uint16_t mem_uncorrectable_error_count; 765 766 /* Cluster information */ 767 uint8_t cluster_permitted; 768 uint8_t cluster_active; 769 uint8_t reserved_1[2]; 770 771 /* Controller capabilities structures */ 772 struct { 773 uint32_t raid_level_0 : 1; 774 uint32_t raid_level_1 : 1; 775 uint32_t raid_level_5 : 1; 776 uint32_t raid_level_1E : 1; 777 uint32_t reserved : 28; 778 } raid_levels; 779 780 struct { 781 uint32_t rbld_rate : 1; 782 uint32_t cc_rate : 1; 783 uint32_t bgi_rate : 1; 784 uint32_t recon_rate : 1; 785 uint32_t patrol_rate : 1; 786 uint32_t alarm_control : 1; 787 uint32_t cluster_supported : 1; 788 uint32_t bbu : 1; 789 uint32_t spanning_allowed : 1; 790 uint32_t dedicated_hotspares : 1; 791 uint32_t revertible_hotspares : 1; 792 uint32_t foreign_config_import : 1; 793 uint32_t self_diagnostic : 1; 794 uint32_t reserved : 19; 795 } adapter_operations; 796 797 struct { 798 uint32_t read_policy : 1; 799 uint32_t write_policy : 1; 800 uint32_t io_policy : 1; 801 uint32_t access_policy : 1; 802 uint32_t reserved : 28; 803 } ld_operations; 804 805 struct { 806 uint8_t min; 807 uint8_t max; 808 uint8_t reserved[2]; 809 } stripe_size_operations; 810 811 struct { 812 uint32_t force_online : 1; 813 uint32_t force_offline : 1; 814 uint32_t force_rebuild : 1; 815 uint32_t reserved : 29; 816 } pd_operations; 817 818 struct { 819 uint32_t ctrl_supports_sas : 1; 820 uint32_t ctrl_supports_sata : 1; 821 uint32_t allow_mix_in_encl : 1; 822 uint32_t allow_mix_in_ld : 1; 823 uint32_t allow_sata_in_cluster : 1; 824 uint32_t reserved : 27; 825 } pd_mix_support; 826 827 /* Include the controller properties (changeable items) */ 828 uint8_t reserved_2[12]; 829 struct mrsas_ctrl_prop properties; 830 831 uint8_t pad[0x800 - 0x640]; 832 }; 833 834 /* 835 * ================================== 836 * MegaRAID SAS2.0 driver definitions 837 * ================================== 838 */ 839 #define MRDRV_MAX_NUM_CMD 1024 840 841 #define MRDRV_MAX_PD_CHANNELS 2 842 #define MRDRV_MAX_LD_CHANNELS 2 843 #define MRDRV_MAX_CHANNELS (MRDRV_MAX_PD_CHANNELS + \ 844 MRDRV_MAX_LD_CHANNELS) 845 #define MRDRV_MAX_DEV_PER_CHANNEL 128 846 #define MRDRV_DEFAULT_INIT_ID -1 847 #define MRDRV_MAX_CMD_PER_LUN 1000 848 #define MRDRV_MAX_LUN 1 849 #define MRDRV_MAX_LD 64 850 851 #define MRDRV_RESET_WAIT_TIME 300 852 #define MRDRV_RESET_NOTICE_INTERVAL 5 853 854 #define MRSAS_IOCTL_CMD 0 855 856 /* 857 * FW can accept both 32 and 64 bit SGLs. We want to allocate 32/64 bit 858 * SGLs based on the size of dma_addr_t 859 */ 860 #define IS_DMA64 (sizeof (dma_addr_t) == 8) 861 862 #define IB_MSG_0_OFF 0x10 /* XScale */ 863 #define OB_MSG_0_OFF 0x18 /* XScale */ 864 #define IB_DOORBELL_OFF 0x20 /* XScale & ROC */ 865 #define OB_INTR_STATUS_OFF 0x30 /* XScale & ROC */ 866 #define OB_INTR_MASK_OFF 0x34 /* XScale & ROC */ 867 #define IB_QPORT_OFF 0x40 /* XScale & ROC */ 868 #define OB_DOORBELL_CLEAR_OFF 0xA0 /* ROC */ 869 #define OB_SCRATCH_PAD_0_OFF 0xB0 /* ROC */ 870 #define OB_INTR_MASK 0xFFFFFFFF 871 #define OB_DOORBELL_CLEAR_MASK 0xFFFFFFFF 872 873 /* 874 * All MFI register set macros accept mrsas_register_set* 875 */ 876 #define WR_IB_MSG_0(v, instance) ddi_put32((instance)->regmap_handle, \ 877 (uint32_t *)((uintptr_t)(instance)->regmap + IB_MSG_0_OFF), (v)) 878 879 #define RD_OB_MSG_0(instance) ddi_get32((instance)->regmap_handle, \ 880 (uint32_t *)((uintptr_t)(instance)->regmap + OB_MSG_0_OFF)) 881 882 #define WR_IB_DOORBELL(v, instance) ddi_put32((instance)->regmap_handle, \ 883 (uint32_t *)((uintptr_t)(instance)->regmap + IB_DOORBELL_OFF), (v)) 884 885 #define RD_IB_DOORBELL(instance) ddi_get32((instance)->regmap_handle, \ 886 (uint32_t *)((uintptr_t)(instance)->regmap + IB_DOORBELL_OFF)) 887 888 #define WR_OB_INTR_STATUS(v, instance) ddi_put32((instance)->regmap_handle, \ 889 (uint32_t *)((uintptr_t)(instance)->regmap + OB_INTR_STATUS_OFF), (v)) 890 891 #define RD_OB_INTR_STATUS(instance) ddi_get32((instance)->regmap_handle, \ 892 (uint32_t *)((uintptr_t)(instance)->regmap + OB_INTR_STATUS_OFF)) 893 894 #define WR_OB_INTR_MASK(v, instance) ddi_put32((instance)->regmap_handle, \ 895 (uint32_t *)((uintptr_t)(instance)->regmap + OB_INTR_MASK_OFF), (v)) 896 897 #define RD_OB_INTR_MASK(instance) ddi_get32((instance)->regmap_handle, \ 898 (uint32_t *)((uintptr_t)(instance)->regmap + OB_INTR_MASK_OFF)) 899 900 #define WR_IB_QPORT(v, instance) ddi_put32((instance)->regmap_handle, \ 901 (uint32_t *)((uintptr_t)(instance)->regmap + IB_QPORT_OFF), (v)) 902 903 #define WR_OB_DOORBELL_CLEAR(v, instance) ddi_put32((instance)->regmap_handle, \ 904 (uint32_t *)((uintptr_t)(instance)->regmap + OB_DOORBELL_CLEAR_OFF), \ 905 (v)) 906 907 #define RD_OB_SCRATCH_PAD_0(instance) ddi_get32((instance)->regmap_handle, \ 908 (uint32_t *)((uintptr_t)(instance)->regmap + OB_SCRATCH_PAD_0_OFF)) 909 910 /* 911 * When FW is in MFI_STATE_READY or MFI_STATE_OPERATIONAL, the state data 912 * of Outbound Msg Reg 0 indicates max concurrent cmds supported, max SGEs 913 * supported per cmd and if 64-bit MFAs (M64) is enabled or disabled. 914 */ 915 #define MFI_OB_INTR_STATUS_MASK 0x00000002 916 917 /* 918 * This MFI_REPLY_2108_MESSAGE_INTR flag is used also 919 * in enable_intr_ppc also. Hence bit 2, i.e. 0x4 has 920 * been set in this flag along with bit 1. 921 */ 922 #define MFI_REPLY_2108_MESSAGE_INTR 0x00000001 923 #define MFI_REPLY_2108_MESSAGE_INTR_MASK 0x00000005 924 925 #define MFI_POLL_TIMEOUT_SECS 60 926 927 #define MFI_ENABLE_INTR(instance) ddi_put32((instance)->regmap_handle, \ 928 (uint32_t *)((uintptr_t)(instance)->regmap + OB_INTR_MASK_OFF), 1) 929 #define MFI_DISABLE_INTR(instance) \ 930 { \ 931 uint32_t disable = 1; \ 932 uint32_t mask = ddi_get32((instance)->regmap_handle, \ 933 (uint32_t *)((uintptr_t)(instance)->regmap + OB_INTR_MASK_OFF));\ 934 mask &= ~disable; \ 935 ddi_put32((instance)->regmap_handle, (uint32_t *) \ 936 (uintptr_t)((instance)->regmap + OB_INTR_MASK_OFF), mask); \ 937 } 938 939 /* By default, the firmware programs for 8 Kbytes of memory */ 940 #define DEFAULT_MFI_MEM_SZ 8192 941 #define MINIMUM_MFI_MEM_SZ 4096 942 943 /* DCMD Message Frame MAILBOX0-11 */ 944 #define DCMD_MBOX_SZ 12 945 946 947 struct mrsas_register_set { 948 uint32_t reserved_0[4]; 949 950 uint32_t inbound_msg_0; 951 uint32_t inbound_msg_1; 952 uint32_t outbound_msg_0; 953 uint32_t outbound_msg_1; 954 955 uint32_t inbound_doorbell; 956 uint32_t inbound_intr_status; 957 uint32_t inbound_intr_mask; 958 959 uint32_t outbound_doorbell; 960 uint32_t outbound_intr_status; 961 uint32_t outbound_intr_mask; 962 963 uint32_t reserved_1[2]; 964 965 uint32_t inbound_queue_port; 966 uint32_t outbound_queue_port; 967 968 uint32_t reserved_2[22]; 969 970 uint32_t outbound_doorbell_clear; 971 972 uint32_t reserved_3[3]; 973 974 uint32_t outbound_scratch_pad; 975 976 uint32_t reserved_4[3]; 977 978 uint32_t inbound_low_queue_port; 979 980 uint32_t inbound_high_queue_port; 981 982 uint32_t reserved_5; 983 uint32_t index_registers[820]; 984 }; 985 986 struct mrsas_sge32 { 987 uint32_t phys_addr; 988 uint32_t length; 989 }; 990 991 struct mrsas_sge64 { 992 uint64_t phys_addr; 993 uint32_t length; 994 }; 995 996 struct mrsas_sge_ieee { 997 uint64_t phys_addr; 998 uint32_t length; 999 uint32_t flag; 1000 }; 1001 1002 union mrsas_sgl { 1003 struct mrsas_sge32 sge32[1]; 1004 struct mrsas_sge64 sge64[1]; 1005 struct mrsas_sge_ieee sge_ieee[1]; 1006 }; 1007 1008 struct mrsas_header { 1009 uint8_t cmd; 1010 uint8_t sense_len; 1011 uint8_t cmd_status; 1012 uint8_t scsi_status; 1013 1014 uint8_t target_id; 1015 uint8_t lun; 1016 uint8_t cdb_len; 1017 uint8_t sge_count; 1018 1019 uint32_t context; 1020 uint8_t req_id; 1021 uint8_t msgvector; 1022 uint16_t pad_0; 1023 1024 uint16_t flags; 1025 uint16_t timeout; 1026 uint32_t data_xferlen; 1027 }; 1028 1029 union mrsas_sgl_frame { 1030 struct mrsas_sge32 sge32[8]; 1031 struct mrsas_sge64 sge64[5]; 1032 }; 1033 1034 struct mrsas_init_frame { 1035 uint8_t cmd; 1036 uint8_t reserved_0; 1037 uint8_t cmd_status; 1038 1039 uint8_t reserved_1; 1040 uint32_t reserved_2; 1041 1042 uint32_t context; 1043 uint8_t req_id; 1044 uint8_t msgvector; 1045 uint16_t pad_0; 1046 1047 uint16_t flags; 1048 uint16_t reserved_3; 1049 uint32_t data_xfer_len; 1050 1051 uint32_t queue_info_new_phys_addr_lo; 1052 uint32_t queue_info_new_phys_addr_hi; 1053 uint32_t queue_info_old_phys_addr_lo; 1054 uint32_t queue_info_old_phys_addr_hi; 1055 1056 uint32_t reserved_4[6]; 1057 }; 1058 1059 struct mrsas_init_queue_info { 1060 uint32_t init_flags; 1061 uint32_t reply_queue_entries; 1062 1063 uint32_t reply_queue_start_phys_addr_lo; 1064 uint32_t reply_queue_start_phys_addr_hi; 1065 uint32_t producer_index_phys_addr_lo; 1066 uint32_t producer_index_phys_addr_hi; 1067 uint32_t consumer_index_phys_addr_lo; 1068 uint32_t consumer_index_phys_addr_hi; 1069 }; 1070 1071 struct mrsas_io_frame { 1072 uint8_t cmd; 1073 uint8_t sense_len; 1074 uint8_t cmd_status; 1075 uint8_t scsi_status; 1076 1077 uint8_t target_id; 1078 uint8_t access_byte; 1079 uint8_t reserved_0; 1080 uint8_t sge_count; 1081 1082 uint32_t context; 1083 uint8_t req_id; 1084 uint8_t msgvector; 1085 uint16_t pad_0; 1086 1087 uint16_t flags; 1088 uint16_t timeout; 1089 uint32_t lba_count; 1090 1091 uint32_t sense_buf_phys_addr_lo; 1092 uint32_t sense_buf_phys_addr_hi; 1093 1094 uint32_t start_lba_lo; 1095 uint32_t start_lba_hi; 1096 1097 union mrsas_sgl sgl; 1098 }; 1099 1100 struct mrsas_pthru_frame { 1101 uint8_t cmd; 1102 uint8_t sense_len; 1103 uint8_t cmd_status; 1104 uint8_t scsi_status; 1105 1106 uint8_t target_id; 1107 uint8_t lun; 1108 uint8_t cdb_len; 1109 uint8_t sge_count; 1110 1111 uint32_t context; 1112 uint8_t req_id; 1113 uint8_t msgvector; 1114 uint16_t pad_0; 1115 1116 uint16_t flags; 1117 uint16_t timeout; 1118 uint32_t data_xfer_len; 1119 1120 uint32_t sense_buf_phys_addr_lo; 1121 uint32_t sense_buf_phys_addr_hi; 1122 1123 uint8_t cdb[16]; 1124 union mrsas_sgl sgl; 1125 }; 1126 1127 struct mrsas_dcmd_frame { 1128 uint8_t cmd; 1129 uint8_t reserved_0; 1130 uint8_t cmd_status; 1131 uint8_t reserved_1[4]; 1132 uint8_t sge_count; 1133 1134 uint32_t context; 1135 uint8_t req_id; 1136 uint8_t msgvector; 1137 uint16_t pad_0; 1138 1139 uint16_t flags; 1140 uint16_t timeout; 1141 1142 uint32_t data_xfer_len; 1143 uint32_t opcode; 1144 1145 union { 1146 uint8_t b[DCMD_MBOX_SZ]; 1147 uint16_t s[6]; 1148 uint32_t w[3]; 1149 } mbox; 1150 1151 union mrsas_sgl sgl; 1152 }; 1153 1154 struct mrsas_abort_frame { 1155 uint8_t cmd; 1156 uint8_t reserved_0; 1157 uint8_t cmd_status; 1158 1159 uint8_t reserved_1; 1160 uint32_t reserved_2; 1161 1162 uint32_t context; 1163 uint8_t req_id; 1164 uint8_t msgvector; 1165 uint16_t pad_0; 1166 1167 uint16_t flags; 1168 uint16_t reserved_3; 1169 uint32_t reserved_4; 1170 1171 uint32_t abort_context; 1172 uint32_t pad_1; 1173 1174 uint32_t abort_mfi_phys_addr_lo; 1175 uint32_t abort_mfi_phys_addr_hi; 1176 1177 uint32_t reserved_5[6]; 1178 }; 1179 1180 struct mrsas_smp_frame { 1181 uint8_t cmd; 1182 uint8_t reserved_1; 1183 uint8_t cmd_status; 1184 uint8_t connection_status; 1185 1186 uint8_t reserved_2[3]; 1187 uint8_t sge_count; 1188 1189 uint32_t context; 1190 uint8_t req_id; 1191 uint8_t msgvector; 1192 uint16_t pad_0; 1193 1194 uint16_t flags; 1195 uint16_t timeout; 1196 1197 uint32_t data_xfer_len; 1198 1199 uint64_t sas_addr; 1200 1201 union mrsas_sgl sgl[2]; 1202 }; 1203 1204 struct mrsas_stp_frame { 1205 uint8_t cmd; 1206 uint8_t reserved_1; 1207 uint8_t cmd_status; 1208 uint8_t connection_status; 1209 1210 uint8_t target_id; 1211 uint8_t reserved_2[2]; 1212 uint8_t sge_count; 1213 1214 uint32_t context; 1215 uint8_t req_id; 1216 uint8_t msgvector; 1217 uint16_t pad_0; 1218 1219 uint16_t flags; 1220 uint16_t timeout; 1221 1222 uint32_t data_xfer_len; 1223 1224 uint16_t fis[10]; 1225 uint32_t stp_flags; 1226 union mrsas_sgl sgl; 1227 }; 1228 1229 union mrsas_frame { 1230 struct mrsas_header hdr; 1231 struct mrsas_init_frame init; 1232 struct mrsas_io_frame io; 1233 struct mrsas_pthru_frame pthru; 1234 struct mrsas_dcmd_frame dcmd; 1235 struct mrsas_abort_frame abort; 1236 struct mrsas_smp_frame smp; 1237 struct mrsas_stp_frame stp; 1238 1239 uint8_t raw_bytes[64]; 1240 }; 1241 1242 typedef struct mrsas_pd_address { 1243 uint16_t device_id; 1244 uint16_t encl_id; 1245 1246 union { 1247 struct { 1248 uint8_t encl_index; 1249 uint8_t slot_number; 1250 } pd_address; 1251 struct { 1252 uint8_t encl_position; 1253 uint8_t encl_connector_index; 1254 } encl_address; 1255 }address; 1256 1257 uint8_t scsi_dev_type; 1258 1259 union { 1260 uint8_t port_bitmap; 1261 uint8_t port_numbers; 1262 } connected; 1263 1264 uint64_t sas_addr[2]; 1265 } mrsas_pd_address_t; 1266 1267 union mrsas_evt_class_locale { 1268 struct { 1269 uint16_t locale; 1270 uint8_t reserved; 1271 int8_t class; 1272 } members; 1273 1274 uint32_t word; 1275 }; 1276 1277 struct mrsas_evt_log_info { 1278 uint32_t newest_seq_num; 1279 uint32_t oldest_seq_num; 1280 uint32_t clear_seq_num; 1281 uint32_t shutdown_seq_num; 1282 uint32_t boot_seq_num; 1283 }; 1284 1285 struct mrsas_progress { 1286 uint16_t progress; 1287 uint16_t elapsed_seconds; 1288 }; 1289 1290 struct mrsas_evtarg_ld { 1291 uint16_t target_id; 1292 uint8_t ld_index; 1293 uint8_t reserved; 1294 }; 1295 1296 struct mrsas_evtarg_pd { 1297 uint16_t device_id; 1298 uint8_t encl_index; 1299 uint8_t slot_number; 1300 }; 1301 1302 struct mrsas_evt_detail { 1303 uint32_t seq_num; 1304 uint32_t time_stamp; 1305 uint32_t code; 1306 union mrsas_evt_class_locale cl; 1307 uint8_t arg_type; 1308 uint8_t reserved1[15]; 1309 1310 union { 1311 struct { 1312 struct mrsas_evtarg_pd pd; 1313 uint8_t cdb_length; 1314 uint8_t sense_length; 1315 uint8_t reserved[2]; 1316 uint8_t cdb[16]; 1317 uint8_t sense[64]; 1318 } cdbSense; 1319 1320 struct mrsas_evtarg_ld ld; 1321 1322 struct { 1323 struct mrsas_evtarg_ld ld; 1324 uint64_t count; 1325 } ld_count; 1326 1327 struct { 1328 uint64_t lba; 1329 struct mrsas_evtarg_ld ld; 1330 } ld_lba; 1331 1332 struct { 1333 struct mrsas_evtarg_ld ld; 1334 uint32_t prevOwner; 1335 uint32_t newOwner; 1336 } ld_owner; 1337 1338 struct { 1339 uint64_t ld_lba; 1340 uint64_t pd_lba; 1341 struct mrsas_evtarg_ld ld; 1342 struct mrsas_evtarg_pd pd; 1343 } ld_lba_pd_lba; 1344 1345 struct { 1346 struct mrsas_evtarg_ld ld; 1347 struct mrsas_progress prog; 1348 } ld_prog; 1349 1350 struct { 1351 struct mrsas_evtarg_ld ld; 1352 uint32_t prev_state; 1353 uint32_t new_state; 1354 } ld_state; 1355 1356 struct { 1357 uint64_t strip; 1358 struct mrsas_evtarg_ld ld; 1359 } ld_strip; 1360 1361 struct mrsas_evtarg_pd pd; 1362 1363 struct { 1364 struct mrsas_evtarg_pd pd; 1365 uint32_t err; 1366 } pd_err; 1367 1368 struct { 1369 uint64_t lba; 1370 struct mrsas_evtarg_pd pd; 1371 } pd_lba; 1372 1373 struct { 1374 uint64_t lba; 1375 struct mrsas_evtarg_pd pd; 1376 struct mrsas_evtarg_ld ld; 1377 } pd_lba_ld; 1378 1379 struct { 1380 struct mrsas_evtarg_pd pd; 1381 struct mrsas_progress prog; 1382 } pd_prog; 1383 1384 struct { 1385 struct mrsas_evtarg_pd pd; 1386 uint32_t prevState; 1387 uint32_t newState; 1388 } pd_state; 1389 1390 struct { 1391 uint16_t vendorId; 1392 uint16_t deviceId; 1393 uint16_t subVendorId; 1394 uint16_t subDeviceId; 1395 } pci; 1396 1397 uint32_t rate; 1398 char str[96]; 1399 1400 struct { 1401 uint32_t rtc; 1402 uint32_t elapsedSeconds; 1403 } time; 1404 1405 struct { 1406 uint32_t ecar; 1407 uint32_t elog; 1408 char str[64]; 1409 } ecc; 1410 1411 mrsas_pd_address_t pd_addr; 1412 1413 uint8_t b[96]; 1414 uint16_t s[48]; 1415 uint32_t w[24]; 1416 uint64_t d[12]; 1417 } args; 1418 1419 char description[128]; 1420 1421 }; 1422 1423 /* only 63 are usable by the application */ 1424 #define MAX_LOGICAL_DRIVES 64 1425 /* only 255 physical devices may be used */ 1426 #define MAX_PHYSICAL_DEVICES 256 1427 #define MAX_PD_PER_ENCLOSURE 64 1428 /* maximum disks per array */ 1429 #define MAX_ROW_SIZE 32 1430 /* maximum spans per logical drive */ 1431 #define MAX_SPAN_DEPTH 8 1432 /* maximum number of arrays a hot spare may be dedicated to */ 1433 #define MAX_ARRAYS_DEDICATED 16 1434 /* maximum number of arrays which may exist */ 1435 #define MAX_ARRAYS 128 1436 /* maximum number of foreign configs that may ha managed at once */ 1437 #define MAX_FOREIGN_CONFIGS 8 1438 /* maximum spares (global and dedicated combined) */ 1439 #define MAX_SPARES_FOR_THE_CONTROLLER MAX_PHYSICAL_DEVICES 1440 /* maximum possible Target IDs (i.e. 0 to 63) */ 1441 #define MAX_TARGET_ID 63 1442 /* maximum number of supported enclosures */ 1443 #define MAX_ENCLOSURES 32 1444 /* maximum number of PHYs per controller */ 1445 #define MAX_PHYS_PER_CONTROLLER 16 1446 /* maximum number of LDs per array (due to DDF limitations) */ 1447 #define MAX_LDS_PER_ARRAY 16 1448 1449 /* 1450 * ----------------------------------------------------------------------------- 1451 * ----------------------------------------------------------------------------- 1452 * 1453 * Logical Drive commands 1454 * 1455 * ----------------------------------------------------------------------------- 1456 * ----------------------------------------------------------------------------- 1457 */ 1458 #define MR_DCMD_LD 0x03000000, /* Logical Device (LD) opcodes */ 1459 1460 /* 1461 * Input: dcmd.opcode - MR_DCMD_LD_GET_LIST 1462 * dcmd.mbox - reserved 1463 * dcmd.sge IN - ptr to returned MR_LD_LIST structure 1464 * Desc: Return the logical drive list structure 1465 * Status: No error 1466 */ 1467 1468 /* 1469 * defines the logical drive reference structure 1470 */ 1471 typedef union _MR_LD_REF { /* LD reference structure */ 1472 struct { 1473 uint8_t targetId; /* LD target id (0 to MAX_TARGET_ID) */ 1474 uint8_t reserved; /* reserved for in line with MR_PD_REF */ 1475 uint16_t seqNum; /* Sequence Number */ 1476 } ld_ref; 1477 uint32_t ref; /* shorthand reference to full 32-bits */ 1478 } MR_LD_REF; /* 4 bytes */ 1479 1480 /* 1481 * defines the logical drive list structure 1482 */ 1483 typedef struct _MR_LD_LIST { 1484 uint32_t ldCount; /* number of LDs */ 1485 uint32_t reserved; /* pad to 8-byte boundary */ 1486 struct { 1487 MR_LD_REF ref; /* LD reference */ 1488 uint8_t state; /* current LD state (MR_LD_STATE) */ 1489 uint8_t reserved[3]; /* pad to 8-byte boundary */ 1490 uint64_t size; /* LD size */ 1491 } ldList[MAX_LOGICAL_DRIVES]; 1492 } MR_LD_LIST; 1493 1494 struct mrsas_drv_ver { 1495 uint8_t signature[12]; 1496 uint8_t os_name[16]; 1497 uint8_t os_ver[12]; 1498 uint8_t drv_name[20]; 1499 uint8_t drv_ver[32]; 1500 uint8_t drv_rel_date[20]; 1501 }; 1502 1503 #define PCI_TYPE0_ADDRESSES 6 1504 #define PCI_TYPE1_ADDRESSES 2 1505 #define PCI_TYPE2_ADDRESSES 5 1506 1507 struct mrsas_pci_common_header { 1508 uint16_t vendorID; /* (ro) */ 1509 uint16_t deviceID; /* (ro) */ 1510 uint16_t command; /* Device control */ 1511 uint16_t status; 1512 uint8_t revisionID; /* (ro) */ 1513 uint8_t progIf; /* (ro) */ 1514 uint8_t subClass; /* (ro) */ 1515 uint8_t baseClass; /* (ro) */ 1516 uint8_t cacheLineSize; /* (ro+) */ 1517 uint8_t latencyTimer; /* (ro+) */ 1518 uint8_t headerType; /* (ro) */ 1519 uint8_t bist; /* Built in self test */ 1520 1521 union { 1522 struct { 1523 uint32_t baseAddresses[PCI_TYPE0_ADDRESSES]; 1524 uint32_t cis; 1525 uint16_t subVendorID; 1526 uint16_t subSystemID; 1527 uint32_t romBaseAddress; 1528 uint8_t capabilitiesPtr; 1529 uint8_t reserved1[3]; 1530 uint32_t reserved2; 1531 uint8_t interruptLine; 1532 uint8_t interruptPin; /* (ro) */ 1533 uint8_t minimumGrant; /* (ro) */ 1534 uint8_t maximumLatency; /* (ro) */ 1535 } type_0; 1536 1537 struct { 1538 uint32_t baseAddresses[PCI_TYPE1_ADDRESSES]; 1539 uint8_t primaryBus; 1540 uint8_t secondaryBus; 1541 uint8_t subordinateBus; 1542 uint8_t secondaryLatency; 1543 uint8_t ioBase; 1544 uint8_t ioLimit; 1545 uint16_t secondaryStatus; 1546 uint16_t memoryBase; 1547 uint16_t memoryLimit; 1548 uint16_t prefetchBase; 1549 uint16_t prefetchLimit; 1550 uint32_t prefetchBaseUpper32; 1551 uint32_t prefetchLimitUpper32; 1552 uint16_t ioBaseUpper16; 1553 uint16_t ioLimitUpper16; 1554 uint8_t capabilitiesPtr; 1555 uint8_t reserved1[3]; 1556 uint32_t romBaseAddress; 1557 uint8_t interruptLine; 1558 uint8_t interruptPin; 1559 uint16_t bridgeControl; 1560 } type_1; 1561 1562 struct { 1563 uint32_t socketRegistersBaseAddress; 1564 uint8_t capabilitiesPtr; 1565 uint8_t reserved; 1566 uint16_t secondaryStatus; 1567 uint8_t primaryBus; 1568 uint8_t secondaryBus; 1569 uint8_t subordinateBus; 1570 uint8_t secondaryLatency; 1571 struct { 1572 uint32_t base; 1573 uint32_t limit; 1574 } range[PCI_TYPE2_ADDRESSES-1]; 1575 uint8_t interruptLine; 1576 uint8_t interruptPin; 1577 uint16_t bridgeControl; 1578 } type_2; 1579 } header; 1580 }; 1581 1582 struct mrsas_pci_link_capability { 1583 union { 1584 struct { 1585 uint32_t linkSpeed :4; 1586 uint32_t linkWidth :6; 1587 uint32_t aspmSupport :2; 1588 uint32_t losExitLatency :3; 1589 uint32_t l1ExitLatency :3; 1590 uint32_t rsvdp :6; 1591 uint32_t portNumber :8; 1592 } bits; 1593 1594 uint32_t asUlong; 1595 } cap; 1596 1597 }; 1598 1599 struct mrsas_pci_link_status_capability { 1600 union { 1601 struct { 1602 uint16_t linkSpeed :4; 1603 uint16_t negotiatedLinkWidth :6; 1604 uint16_t linkTrainingError :1; 1605 uint16_t linkTraning :1; 1606 uint16_t slotClockConfig :1; 1607 uint16_t rsvdZ :3; 1608 } bits; 1609 1610 uint16_t asUshort; 1611 } stat_cap; 1612 1613 uint16_t reserved; 1614 1615 }; 1616 1617 struct mrsas_pci_capabilities { 1618 struct mrsas_pci_link_capability linkCapability; 1619 struct mrsas_pci_link_status_capability linkStatusCapability; 1620 }; 1621 1622 struct mrsas_pci_information 1623 { 1624 uint32_t busNumber; 1625 uint8_t deviceNumber; 1626 uint8_t functionNumber; 1627 uint8_t interruptVector; 1628 uint8_t reserved; 1629 struct mrsas_pci_common_header pciHeaderInfo; 1630 struct mrsas_pci_capabilities capability; 1631 uint8_t reserved2[32]; 1632 }; 1633 1634 struct mrsas_ioctl { 1635 uint16_t version; 1636 uint16_t controller_id; 1637 uint8_t signature[8]; 1638 uint32_t reserved_1; 1639 uint32_t control_code; 1640 uint32_t reserved_2[2]; 1641 uint8_t frame[64]; 1642 union mrsas_sgl_frame sgl_frame; 1643 uint8_t sense_buff[MRSAS_MAX_SENSE_LENGTH]; 1644 uint8_t data[1]; 1645 }; 1646 1647 struct mrsas_aen { 1648 uint16_t host_no; 1649 uint16_t cmd_status; 1650 uint32_t seq_num; 1651 uint32_t class_locale_word; 1652 }; 1653 #pragma pack() 1654 1655 #ifndef DDI_VENDOR_LSI 1656 #define DDI_VENDOR_LSI "LSI" 1657 #endif /* DDI_VENDOR_LSI */ 1658 1659 #ifndef KMDB_MODULE 1660 static int mrsas_getinfo(dev_info_t *, ddi_info_cmd_t, void *, void **); 1661 static int mrsas_attach(dev_info_t *, ddi_attach_cmd_t); 1662 static int mrsas_reset(dev_info_t *, ddi_reset_cmd_t); 1663 static int mrsas_detach(dev_info_t *, ddi_detach_cmd_t); 1664 static int mrsas_open(dev_t *, int, int, cred_t *); 1665 static int mrsas_close(dev_t, int, int, cred_t *); 1666 static int mrsas_ioctl(dev_t, int, intptr_t, int, cred_t *, int *); 1667 1668 static int mrsas_tran_tgt_init(dev_info_t *, dev_info_t *, 1669 scsi_hba_tran_t *, struct scsi_device *); 1670 static struct scsi_pkt *mrsas_tran_init_pkt(struct scsi_address *, register 1671 struct scsi_pkt *, struct buf *, int, int, int, int, 1672 int (*)(), caddr_t); 1673 static int mrsas_tran_start(struct scsi_address *, 1674 register struct scsi_pkt *); 1675 static int mrsas_tran_abort(struct scsi_address *, struct scsi_pkt *); 1676 static int mrsas_tran_reset(struct scsi_address *, int); 1677 static int mrsas_tran_getcap(struct scsi_address *, char *, int); 1678 static int mrsas_tran_setcap(struct scsi_address *, char *, int, int); 1679 static void mrsas_tran_destroy_pkt(struct scsi_address *, 1680 struct scsi_pkt *); 1681 static void mrsas_tran_dmafree(struct scsi_address *, struct scsi_pkt *); 1682 static void mrsas_tran_sync_pkt(struct scsi_address *, struct scsi_pkt *); 1683 static uint_t mrsas_isr(); 1684 static uint_t mrsas_softintr(); 1685 1686 static int init_mfi(struct mrsas_instance *); 1687 static int mrsas_free_dma_obj(struct mrsas_instance *, dma_obj_t); 1688 static int mrsas_alloc_dma_obj(struct mrsas_instance *, dma_obj_t *, 1689 uchar_t); 1690 static struct mrsas_cmd *get_mfi_pkt(struct mrsas_instance *); 1691 static void return_mfi_pkt(struct mrsas_instance *, 1692 struct mrsas_cmd *); 1693 1694 static void free_space_for_mfi(struct mrsas_instance *); 1695 static void free_additional_dma_buffer(struct mrsas_instance *); 1696 static int alloc_additional_dma_buffer(struct mrsas_instance *); 1697 static int read_fw_status_reg_ppc(struct mrsas_instance *); 1698 static void issue_cmd_ppc(struct mrsas_cmd *, struct mrsas_instance *); 1699 static int issue_cmd_in_poll_mode_ppc(struct mrsas_instance *, 1700 struct mrsas_cmd *); 1701 static int issue_cmd_in_sync_mode_ppc(struct mrsas_instance *, 1702 struct mrsas_cmd *); 1703 static void enable_intr_ppc(struct mrsas_instance *); 1704 static void disable_intr_ppc(struct mrsas_instance *); 1705 static int intr_ack_ppc(struct mrsas_instance *); 1706 static int mfi_state_transition_to_ready(struct mrsas_instance *); 1707 static void destroy_mfi_frame_pool(struct mrsas_instance *); 1708 static int create_mfi_frame_pool(struct mrsas_instance *); 1709 static int mrsas_dma_alloc(struct mrsas_instance *, struct scsi_pkt *, 1710 struct buf *, int, int (*)()); 1711 static int mrsas_dma_move(struct mrsas_instance *, 1712 struct scsi_pkt *, struct buf *); 1713 static void flush_cache(struct mrsas_instance *instance); 1714 static void display_scsi_inquiry(caddr_t); 1715 static int start_mfi_aen(struct mrsas_instance *instance); 1716 static int handle_drv_ioctl(struct mrsas_instance *instance, 1717 struct mrsas_ioctl *ioctl, int mode); 1718 static int handle_mfi_ioctl(struct mrsas_instance *instance, 1719 struct mrsas_ioctl *ioctl, int mode); 1720 static int handle_mfi_aen(struct mrsas_instance *instance, 1721 struct mrsas_aen *aen); 1722 static void fill_up_drv_ver(struct mrsas_drv_ver *dv); 1723 static struct mrsas_cmd *build_cmd(struct mrsas_instance *instance, 1724 struct scsi_address *ap, struct scsi_pkt *pkt, 1725 uchar_t *cmd_done); 1726 static int register_mfi_aen(struct mrsas_instance *instance, 1727 uint32_t seq_num, uint32_t class_locale_word); 1728 static int issue_mfi_pthru(struct mrsas_instance *instance, struct 1729 mrsas_ioctl *ioctl, struct mrsas_cmd *cmd, int mode); 1730 static int issue_mfi_dcmd(struct mrsas_instance *instance, struct 1731 mrsas_ioctl *ioctl, struct mrsas_cmd *cmd, int mode); 1732 static int issue_mfi_smp(struct mrsas_instance *instance, struct 1733 mrsas_ioctl *ioctl, struct mrsas_cmd *cmd, int mode); 1734 static int issue_mfi_stp(struct mrsas_instance *instance, struct 1735 mrsas_ioctl *ioctl, struct mrsas_cmd *cmd, int mode); 1736 static int abort_aen_cmd(struct mrsas_instance *instance, 1737 struct mrsas_cmd *cmd_to_abort); 1738 1739 static int mrsas_common_check(struct mrsas_instance *instance, 1740 struct mrsas_cmd *cmd); 1741 static void mrsas_fm_init(struct mrsas_instance *instance); 1742 static void mrsas_fm_fini(struct mrsas_instance *instance); 1743 static int mrsas_fm_error_cb(dev_info_t *, ddi_fm_error_t *, 1744 const void *); 1745 static void mrsas_fm_ereport(struct mrsas_instance *instance, 1746 char *detail); 1747 static int mrsas_check_dma_handle(ddi_dma_handle_t handle); 1748 static int mrsas_check_acc_handle(ddi_acc_handle_t handle); 1749 1750 static void mrsas_rem_intrs(struct mrsas_instance *instance); 1751 static int mrsas_add_intrs(struct mrsas_instance *instance, int intr_type); 1752 1753 static void mrsas_tran_tgt_free(dev_info_t *, dev_info_t *, 1754 scsi_hba_tran_t *, struct scsi_device *); 1755 static int mrsas_tran_bus_config(dev_info_t *, uint_t, 1756 ddi_bus_config_op_t, void *, dev_info_t **); 1757 static int mrsas_parse_devname(char *, int *, int *); 1758 static int mrsas_config_all_devices(struct mrsas_instance *); 1759 static int mrsas_config_scsi_device(struct mrsas_instance *, 1760 struct scsi_device *, dev_info_t **); 1761 static int mrsas_config_ld(struct mrsas_instance *, uint16_t, 1762 uint8_t, dev_info_t **); 1763 static dev_info_t *mrsas_find_child(struct mrsas_instance *, uint16_t, 1764 uint8_t); 1765 static int mrsas_name_node(dev_info_t *, char *, int); 1766 static void mrsas_issue_evt_taskq(struct mrsas_eventinfo *); 1767 static int mrsas_service_evt(struct mrsas_instance *, int, int, int, 1768 uint64_t); 1769 static int mrsas_mode_sense_build(struct scsi_pkt *); 1770 #endif /* KMDB_MODULE */ 1771 1772 #ifdef __cplusplus 1773 } 1774 #endif 1775 1776 #endif /* _MR_SAS_H_ */ 1777