1 /* 2 * mr_sas.h: header for mr_sas 3 * 4 * Solaris MegaRAID driver for SAS2.0 controllers 5 * Copyright (c) 2008-2012, LSI Logic Corporation. 6 * All rights reserved. 7 * 8 * Version: 9 * Author: 10 * Swaminathan K S 11 * Arun Chandrashekhar 12 * Manju R 13 * Rasheed 14 * Shakeel Bukhari 15 * 16 * Redistribution and use in source and binary forms, with or without 17 * modification, are permitted provided that the following conditions are met: 18 * 19 * 1. Redistributions of source code must retain the above copyright notice, 20 * this list of conditions and the following disclaimer. 21 * 22 * 2. Redistributions in binary form must reproduce the above copyright notice, 23 * this list of conditions and the following disclaimer in the documentation 24 * and/or other materials provided with the distribution. 25 * 26 * 3. Neither the name of the author nor the names of its contributors may be 27 * used to endorse or promote products derived from this software without 28 * specific prior written permission. 29 * 30 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 31 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 32 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS 33 * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE 34 * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, 35 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, 36 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS 37 * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED 38 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 39 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT 40 * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH 41 * DAMAGE. 42 */ 43 44 /* 45 * Copyright (c) 2009, 2010, Oracle and/or its affiliates. All rights reserved. 46 */ 47 48 #ifndef _MR_SAS_H_ 49 #define _MR_SAS_H_ 50 51 #ifdef __cplusplus 52 extern "C" { 53 #endif 54 55 #include <sys/scsi/scsi.h> 56 #include "mr_sas_list.h" 57 #include "ld_pd_map.h" 58 59 /* 60 * MegaRAID SAS2.0 Driver meta data 61 */ 62 #define MRSAS_VERSION "6.503.00.00ILLUMOS" 63 #define MRSAS_RELDATE "July 30, 2012" 64 65 #define MRSAS_TRUE 1 66 #define MRSAS_FALSE 0 67 68 #define ADAPTER_RESET_NOT_REQUIRED 0 69 #define ADAPTER_RESET_REQUIRED 1 70 71 #define PDSUPPORT 1 72 73 /* 74 * MegaRAID SAS2.0 device id conversion definitions. 75 */ 76 #define INST2LSIRDCTL(x) ((x) << INST_MINOR_SHIFT) 77 #define MRSAS_GET_BOUNDARY_ALIGNED_LEN(len, new_len, boundary_len) { \ 78 int rem; \ 79 rem = (len / boundary_len); \ 80 if ((rem * boundary_len) != len) { \ 81 new_len = len + ((rem + 1) * boundary_len - len); \ 82 } else { \ 83 new_len = len; \ 84 } \ 85 } 86 87 88 /* 89 * MegaRAID SAS2.0 supported controllers 90 */ 91 #define PCI_DEVICE_ID_LSI_2108VDE 0x0078 92 #define PCI_DEVICE_ID_LSI_2108V 0x0079 93 #define PCI_DEVICE_ID_LSI_TBOLT 0x005b 94 #define PCI_DEVICE_ID_LSI_INVADER 0x005d 95 96 /* 97 * Register Index for 2108 Controllers. 98 */ 99 #define REGISTER_SET_IO_2108 (2) 100 101 #define MRSAS_MAX_SGE_CNT 0x50 102 #define MRSAS_APP_RESERVED_CMDS 32 103 104 #define MRSAS_IOCTL_DRIVER 0x12341234 105 #define MRSAS_IOCTL_FIRMWARE 0x12345678 106 #define MRSAS_IOCTL_AEN 0x87654321 107 108 #define MRSAS_1_SECOND 1000000 109 110 #ifdef PDSUPPORT 111 112 #define UNCONFIGURED_GOOD 0x0 113 #define PD_SYSTEM 0x40 114 #define MR_EVT_PD_STATE_CHANGE 0x0072 115 #define MR_EVT_PD_REMOVED_EXT 0x00f8 116 #define MR_EVT_PD_INSERTED_EXT 0x00f7 117 #define MR_DCMD_PD_GET_INFO 0x02020000 118 #define MRSAS_TBOLT_PD_LUN 1 119 #define MRSAS_TBOLT_PD_TGT_MAX 255 120 #define MRSAS_TBOLT_GET_PD_MAX(s) ((s)->mr_tbolt_pd_max) 121 122 #endif 123 124 /* Raid Context Flags */ 125 #define MR_RAID_CTX_RAID_FLAGS_IO_SUB_TYPE_SHIFT 0x4 126 #define MR_RAID_CTX_RAID_FLAGS_IO_SUB_TYPE_MASK 0x30 127 typedef enum MR_RAID_FLAGS_IO_SUB_TYPE { 128 MR_RAID_FLAGS_IO_SUB_TYPE_NONE = 0, 129 MR_RAID_FLAGS_IO_SUB_TYPE_SYSTEM_PD = 1 130 } MR_RAID_FLAGS_IO_SUB_TYPE; 131 132 /* Dynamic Enumeration Flags */ 133 #define MRSAS_LD_LUN 0 134 #define WWN_STRLEN 17 135 #define LD_SYNC_BIT 1 136 #define LD_SYNC_SHIFT 14 137 /* ThunderBolt (TB) specific */ 138 #define MRSAS_THUNDERBOLT_MSG_SIZE 256 139 #define MRSAS_THUNDERBOLT_MAX_COMMANDS 1024 140 #define MRSAS_THUNDERBOLT_MAX_REPLY_COUNT 1024 141 #define MRSAS_THUNDERBOLT_REPLY_SIZE 8 142 #define MRSAS_THUNDERBOLT_MAX_CHAIN_COUNT 1 143 144 #define MPI2_FUNCTION_PASSTHRU_IO_REQUEST 0xF0 145 #define MPI2_FUNCTION_LD_IO_REQUEST 0xF1 146 147 #define MR_EVT_LD_FAST_PATH_IO_STATUS_CHANGED (0xFFFF) 148 149 #define MR_INTERNAL_MFI_FRAMES_SMID 1 150 #define MR_CTRL_EVENT_WAIT_SMID 2 151 #define MR_INTERNAL_DRIVER_RESET_SMID 3 152 153 154 /* 155 * ===================================== 156 * MegaRAID SAS2.0 MFI firmware definitions 157 * ===================================== 158 */ 159 /* 160 * MFI stands for MegaRAID SAS2.0 FW Interface. This is just a moniker for 161 * protocol between the software and firmware. Commands are issued using 162 * "message frames" 163 */ 164 165 /* 166 * FW posts its state in upper 4 bits of outbound_msg_0 register 167 */ 168 #define MFI_STATE_MASK 0xF0000000 169 #define MFI_STATE_UNDEFINED 0x00000000 170 #define MFI_STATE_BB_INIT 0x10000000 171 #define MFI_STATE_FW_INIT 0x40000000 172 #define MFI_STATE_WAIT_HANDSHAKE 0x60000000 173 #define MFI_STATE_FW_INIT_2 0x70000000 174 #define MFI_STATE_DEVICE_SCAN 0x80000000 175 #define MFI_STATE_BOOT_MESSAGE_PENDING 0x90000000 176 #define MFI_STATE_FLUSH_CACHE 0xA0000000 177 #define MFI_STATE_READY 0xB0000000 178 #define MFI_STATE_OPERATIONAL 0xC0000000 179 #define MFI_STATE_FAULT 0xF0000000 180 181 #define MRMFI_FRAME_SIZE 64 182 183 /* 184 * During FW init, clear pending cmds & reset state using inbound_msg_0 185 * 186 * ABORT : Abort all pending cmds 187 * READY : Move from OPERATIONAL to READY state; discard queue info 188 * MFIMODE : Discard (possible) low MFA posted in 64-bit mode (??) 189 * CLR_HANDSHAKE: FW is waiting for HANDSHAKE from BIOS or Driver 190 */ 191 #define MFI_INIT_ABORT 0x00000001 192 #define MFI_INIT_READY 0x00000002 193 #define MFI_INIT_MFIMODE 0x00000004 194 #define MFI_INIT_CLEAR_HANDSHAKE 0x00000008 195 #define MFI_INIT_HOTPLUG 0x00000010 196 #define MFI_STOP_ADP 0x00000020 197 #define MFI_RESET_FLAGS MFI_INIT_READY|MFI_INIT_MFIMODE|MFI_INIT_ABORT 198 199 /* 200 * MFI frame flags 201 */ 202 #define MFI_FRAME_POST_IN_REPLY_QUEUE 0x0000 203 #define MFI_FRAME_DONT_POST_IN_REPLY_QUEUE 0x0001 204 #define MFI_FRAME_SGL32 0x0000 205 #define MFI_FRAME_SGL64 0x0002 206 #define MFI_FRAME_SENSE32 0x0000 207 #define MFI_FRAME_SENSE64 0x0004 208 #define MFI_FRAME_DIR_NONE 0x0000 209 #define MFI_FRAME_DIR_WRITE 0x0008 210 #define MFI_FRAME_DIR_READ 0x0010 211 #define MFI_FRAME_DIR_BOTH 0x0018 212 #define MFI_FRAME_IEEE 0x0020 213 214 /* 215 * Definition for cmd_status 216 */ 217 #define MFI_CMD_STATUS_POLL_MODE 0xFF 218 #define MFI_CMD_STATUS_SYNC_MODE 0xFF 219 220 /* 221 * MFI command opcodes 222 */ 223 #define MFI_CMD_OP_INIT 0x00 224 #define MFI_CMD_OP_LD_READ 0x01 225 #define MFI_CMD_OP_LD_WRITE 0x02 226 #define MFI_CMD_OP_LD_SCSI 0x03 227 #define MFI_CMD_OP_PD_SCSI 0x04 228 #define MFI_CMD_OP_DCMD 0x05 229 #define MFI_CMD_OP_ABORT 0x06 230 #define MFI_CMD_OP_SMP 0x07 231 #define MFI_CMD_OP_STP 0x08 232 233 #define MR_DCMD_CTRL_GET_INFO 0x01010000 234 235 #define MR_DCMD_CTRL_CACHE_FLUSH 0x01101000 236 #define MR_FLUSH_CTRL_CACHE 0x01 237 #define MR_FLUSH_DISK_CACHE 0x02 238 239 #define MR_DCMD_CTRL_SHUTDOWN 0x01050000 240 #define MRSAS_ENABLE_DRIVE_SPINDOWN 0x01 241 242 #define MR_DCMD_CTRL_EVENT_GET_INFO 0x01040100 243 #define MR_DCMD_CTRL_EVENT_GET 0x01040300 244 #define MR_DCMD_CTRL_EVENT_WAIT 0x01040500 245 #define MR_DCMD_LD_GET_PROPERTIES 0x03030000 246 247 /* 248 * Solaris Specific MAX values 249 */ 250 #define MAX_SGL 24 251 252 /* 253 * MFI command completion codes 254 */ 255 enum MFI_STAT { 256 MFI_STAT_OK = 0x00, 257 MFI_STAT_INVALID_CMD = 0x01, 258 MFI_STAT_INVALID_DCMD = 0x02, 259 MFI_STAT_INVALID_PARAMETER = 0x03, 260 MFI_STAT_INVALID_SEQUENCE_NUMBER = 0x04, 261 MFI_STAT_ABORT_NOT_POSSIBLE = 0x05, 262 MFI_STAT_APP_HOST_CODE_NOT_FOUND = 0x06, 263 MFI_STAT_APP_IN_USE = 0x07, 264 MFI_STAT_APP_NOT_INITIALIZED = 0x08, 265 MFI_STAT_ARRAY_INDEX_INVALID = 0x09, 266 MFI_STAT_ARRAY_ROW_NOT_EMPTY = 0x0a, 267 MFI_STAT_CONFIG_RESOURCE_CONFLICT = 0x0b, 268 MFI_STAT_DEVICE_NOT_FOUND = 0x0c, 269 MFI_STAT_DRIVE_TOO_SMALL = 0x0d, 270 MFI_STAT_FLASH_ALLOC_FAIL = 0x0e, 271 MFI_STAT_FLASH_BUSY = 0x0f, 272 MFI_STAT_FLASH_ERROR = 0x10, 273 MFI_STAT_FLASH_IMAGE_BAD = 0x11, 274 MFI_STAT_FLASH_IMAGE_INCOMPLETE = 0x12, 275 MFI_STAT_FLASH_NOT_OPEN = 0x13, 276 MFI_STAT_FLASH_NOT_STARTED = 0x14, 277 MFI_STAT_FLUSH_FAILED = 0x15, 278 MFI_STAT_HOST_CODE_NOT_FOUNT = 0x16, 279 MFI_STAT_LD_CC_IN_PROGRESS = 0x17, 280 MFI_STAT_LD_INIT_IN_PROGRESS = 0x18, 281 MFI_STAT_LD_LBA_OUT_OF_RANGE = 0x19, 282 MFI_STAT_LD_MAX_CONFIGURED = 0x1a, 283 MFI_STAT_LD_NOT_OPTIMAL = 0x1b, 284 MFI_STAT_LD_RBLD_IN_PROGRESS = 0x1c, 285 MFI_STAT_LD_RECON_IN_PROGRESS = 0x1d, 286 MFI_STAT_LD_WRONG_RAID_LEVEL = 0x1e, 287 MFI_STAT_MAX_SPARES_EXCEEDED = 0x1f, 288 MFI_STAT_MEMORY_NOT_AVAILABLE = 0x20, 289 MFI_STAT_MFC_HW_ERROR = 0x21, 290 MFI_STAT_NO_HW_PRESENT = 0x22, 291 MFI_STAT_NOT_FOUND = 0x23, 292 MFI_STAT_NOT_IN_ENCL = 0x24, 293 MFI_STAT_PD_CLEAR_IN_PROGRESS = 0x25, 294 MFI_STAT_PD_TYPE_WRONG = 0x26, 295 MFI_STAT_PR_DISABLED = 0x27, 296 MFI_STAT_ROW_INDEX_INVALID = 0x28, 297 MFI_STAT_SAS_CONFIG_INVALID_ACTION = 0x29, 298 MFI_STAT_SAS_CONFIG_INVALID_DATA = 0x2a, 299 MFI_STAT_SAS_CONFIG_INVALID_PAGE = 0x2b, 300 MFI_STAT_SAS_CONFIG_INVALID_TYPE = 0x2c, 301 MFI_STAT_SCSI_DONE_WITH_ERROR = 0x2d, 302 MFI_STAT_SCSI_IO_FAILED = 0x2e, 303 MFI_STAT_SCSI_RESERVATION_CONFLICT = 0x2f, 304 MFI_STAT_SHUTDOWN_FAILED = 0x30, 305 MFI_STAT_TIME_NOT_SET = 0x31, 306 MFI_STAT_WRONG_STATE = 0x32, 307 MFI_STAT_LD_OFFLINE = 0x33, 308 MFI_STAT_INVALID_STATUS = 0xFF 309 }; 310 311 enum MR_EVT_CLASS { 312 MR_EVT_CLASS_DEBUG = -2, 313 MR_EVT_CLASS_PROGRESS = -1, 314 MR_EVT_CLASS_INFO = 0, 315 MR_EVT_CLASS_WARNING = 1, 316 MR_EVT_CLASS_CRITICAL = 2, 317 MR_EVT_CLASS_FATAL = 3, 318 MR_EVT_CLASS_DEAD = 4 319 }; 320 321 enum MR_EVT_LOCALE { 322 MR_EVT_LOCALE_LD = 0x0001, 323 MR_EVT_LOCALE_PD = 0x0002, 324 MR_EVT_LOCALE_ENCL = 0x0004, 325 MR_EVT_LOCALE_BBU = 0x0008, 326 MR_EVT_LOCALE_SAS = 0x0010, 327 MR_EVT_LOCALE_CTRL = 0x0020, 328 MR_EVT_LOCALE_CONFIG = 0x0040, 329 MR_EVT_LOCALE_CLUSTER = 0x0080, 330 MR_EVT_LOCALE_ALL = 0xffff 331 }; 332 333 enum MR_EVT_ARGS { 334 MR_EVT_ARGS_NONE, 335 MR_EVT_ARGS_CDB_SENSE, 336 MR_EVT_ARGS_LD, 337 MR_EVT_ARGS_LD_COUNT, 338 MR_EVT_ARGS_LD_LBA, 339 MR_EVT_ARGS_LD_OWNER, 340 MR_EVT_ARGS_LD_LBA_PD_LBA, 341 MR_EVT_ARGS_LD_PROG, 342 MR_EVT_ARGS_LD_STATE, 343 MR_EVT_ARGS_LD_STRIP, 344 MR_EVT_ARGS_PD, 345 MR_EVT_ARGS_PD_ERR, 346 MR_EVT_ARGS_PD_LBA, 347 MR_EVT_ARGS_PD_LBA_LD, 348 MR_EVT_ARGS_PD_PROG, 349 MR_EVT_ARGS_PD_STATE, 350 MR_EVT_ARGS_PCI, 351 MR_EVT_ARGS_RATE, 352 MR_EVT_ARGS_STR, 353 MR_EVT_ARGS_TIME, 354 MR_EVT_ARGS_ECC 355 }; 356 357 #define MR_EVT_CFG_CLEARED 0x0004 358 #define MR_EVT_LD_CREATED 0x008a 359 #define MR_EVT_LD_DELETED 0x008b 360 #define MR_EVT_CFG_FP_CHANGE 0x017B 361 362 enum LD_STATE { 363 LD_OFFLINE = 0, 364 LD_PARTIALLY_DEGRADED = 1, 365 LD_DEGRADED = 2, 366 LD_OPTIMAL = 3, 367 LD_INVALID = 0xFF 368 }; 369 370 enum MRSAS_EVT { 371 MRSAS_EVT_CONFIG_TGT = 0, 372 MRSAS_EVT_UNCONFIG_TGT = 1, 373 MRSAS_EVT_UNCONFIG_SMP = 2 374 }; 375 376 #define DMA_OBJ_ALLOCATED 1 377 #define DMA_OBJ_REALLOCATED 2 378 #define DMA_OBJ_FREED 3 379 380 /* 381 * dma_obj_t - Our DMA object 382 * @param buffer : kernel virtual address 383 * @param size : size of the data to be allocated 384 * @param acc_handle : access handle 385 * @param dma_handle : dma handle 386 * @param dma_cookie : scatter-gather list 387 * @param dma_attr : dma attributes for this buffer 388 * 389 * Our DMA object. The caller must initialize the size and dma attributes 390 * (dma_attr) fields before allocating the resources. 391 */ 392 typedef struct { 393 caddr_t buffer; 394 uint32_t size; 395 ddi_acc_handle_t acc_handle; 396 ddi_dma_handle_t dma_handle; 397 ddi_dma_cookie_t dma_cookie[MRSAS_MAX_SGE_CNT]; 398 ddi_dma_attr_t dma_attr; 399 uint8_t status; 400 uint8_t reserved[3]; 401 } dma_obj_t; 402 403 struct mrsas_eventinfo { 404 struct mrsas_instance *instance; 405 int tgt; 406 int lun; 407 int event; 408 uint64_t wwn; 409 }; 410 411 struct mrsas_ld { 412 dev_info_t *dip; 413 uint8_t lun_type; 414 uint8_t flag; 415 uint8_t reserved[2]; 416 }; 417 418 419 #ifdef PDSUPPORT 420 struct mrsas_tbolt_pd { 421 dev_info_t *dip; 422 uint8_t lun_type; 423 uint8_t dev_id; 424 uint8_t flag; 425 uint8_t reserved; 426 }; 427 struct mrsas_tbolt_pd_info { 428 uint16_t deviceId; 429 uint16_t seqNum; 430 uint8_t inquiryData[96]; 431 uint8_t vpdPage83[64]; 432 uint8_t notSupported; 433 uint8_t scsiDevType; 434 uint8_t a; 435 uint8_t device_speed; 436 uint32_t mediaerrcnt; 437 uint32_t other; 438 uint32_t pred; 439 uint32_t lastpred; 440 uint16_t fwState; 441 uint8_t disabled; 442 uint8_t linkspwwd; 443 uint32_t ddfType; 444 struct { 445 uint8_t count; 446 uint8_t isPathBroken; 447 uint8_t connectorIndex[2]; 448 uint8_t reserved[4]; 449 uint64_t sasAddr[2]; 450 uint8_t reserved2[16]; 451 } pathInfo; 452 }; 453 #endif 454 455 typedef struct mrsas_instance { 456 uint32_t *producer; 457 uint32_t *consumer; 458 459 uint32_t *reply_queue; 460 dma_obj_t mfi_internal_dma_obj; 461 uint16_t adapterresetinprogress; 462 uint16_t deadadapter; 463 /* ThunderBolt (TB) specific */ 464 dma_obj_t mpi2_frame_pool_dma_obj; 465 dma_obj_t request_desc_dma_obj; 466 dma_obj_t reply_desc_dma_obj; 467 dma_obj_t ld_map_obj[2]; 468 469 uint8_t init_id; 470 uint8_t flag_ieee; 471 uint8_t disable_online_ctrl_reset; 472 uint8_t fw_fault_count_after_ocr; 473 474 uint16_t max_num_sge; 475 uint16_t max_fw_cmds; 476 uint32_t max_sectors_per_req; 477 478 struct mrsas_cmd **cmd_list; 479 480 mlist_t cmd_pool_list; 481 kmutex_t cmd_pool_mtx; 482 kmutex_t sync_map_mtx; 483 484 mlist_t app_cmd_pool_list; 485 kmutex_t app_cmd_pool_mtx; 486 mlist_t cmd_app_pool_list; 487 kmutex_t cmd_app_pool_mtx; 488 489 490 mlist_t cmd_pend_list; 491 kmutex_t cmd_pend_mtx; 492 493 dma_obj_t mfi_evt_detail_obj; 494 struct mrsas_cmd *aen_cmd; 495 496 uint32_t aen_seq_num; 497 uint32_t aen_class_locale_word; 498 499 scsi_hba_tran_t *tran; 500 501 kcondvar_t int_cmd_cv; 502 kmutex_t int_cmd_mtx; 503 504 kcondvar_t aen_cmd_cv; 505 kmutex_t aen_cmd_mtx; 506 507 kcondvar_t abort_cmd_cv; 508 kmutex_t abort_cmd_mtx; 509 510 kmutex_t reg_write_mtx; 511 kmutex_t chip_mtx; 512 513 dev_info_t *dip; 514 ddi_acc_handle_t pci_handle; 515 516 timeout_id_t timeout_id; 517 uint32_t unique_id; 518 uint16_t fw_outstanding; 519 caddr_t regmap; 520 ddi_acc_handle_t regmap_handle; 521 uint8_t isr_level; 522 ddi_iblock_cookie_t iblock_cookie; 523 ddi_iblock_cookie_t soft_iblock_cookie; 524 ddi_softintr_t soft_intr_id; 525 uint8_t softint_running; 526 uint8_t tbolt_softint_running; 527 kmutex_t completed_pool_mtx; 528 mlist_t completed_pool_list; 529 530 caddr_t internal_buf; 531 uint32_t internal_buf_dmac_add; 532 uint32_t internal_buf_size; 533 534 uint16_t vendor_id; 535 uint16_t device_id; 536 uint16_t subsysvid; 537 uint16_t subsysid; 538 int instance; 539 int baseaddress; 540 char iocnode[16]; 541 542 int fm_capabilities; 543 /* 544 * Driver resources unroll flags. The flag is set for resources that 545 * are needed to be free'd at detach() time. 546 */ 547 struct _unroll { 548 uint8_t softs; /* The software state was allocated. */ 549 uint8_t regs; /* Controller registers mapped. */ 550 uint8_t intr; /* Interrupt handler added. */ 551 uint8_t reqs; /* Request structs allocated. */ 552 uint8_t mutexs; /* Mutex's allocated. */ 553 uint8_t taskq; /* Task q's created. */ 554 uint8_t tran; /* Tran struct allocated */ 555 uint8_t tranSetup; /* Tran attached to the ddi. */ 556 uint8_t devctl; /* Device nodes for cfgadm created. */ 557 uint8_t scsictl; /* Device nodes for cfgadm created. */ 558 uint8_t ioctl; /* Device nodes for ioctl's created. */ 559 uint8_t timer; /* Timer started. */ 560 uint8_t aenPend; /* AEN cmd pending f/w. */ 561 uint8_t mapUpdate_pend; /* LD MAP update cmd pending f/w. */ 562 uint8_t soft_isr; /* Soft interrupt handler allocated. */ 563 uint8_t ldlist_buff; /* Logical disk list allocated. */ 564 uint8_t pdlist_buff; /* Physical disk list allocated. */ 565 uint8_t syncCmd; /* Sync map command allocated. */ 566 uint8_t verBuff; /* 2108 MFI buffer allocated. */ 567 uint8_t alloc_space_mfi; /* Allocated space for 2108 MFI. */ 568 uint8_t alloc_space_mpi2; /* Allocated space for 2208 MPI2. */ 569 } unroll; 570 571 572 /* function template pointer */ 573 struct mrsas_function_template *func_ptr; 574 575 576 /* MSI interrupts specific */ 577 ddi_intr_handle_t *intr_htable; /* Interrupt handle array */ 578 size_t intr_htable_size; /* Int. handle array size */ 579 int intr_type; 580 int intr_cnt; 581 uint_t intr_pri; 582 int intr_cap; 583 584 ddi_taskq_t *taskq; 585 struct mrsas_ld *mr_ld_list; 586 kmutex_t config_dev_mtx; 587 /* ThunderBolt (TB) specific */ 588 ddi_softintr_t tbolt_soft_intr_id; 589 590 #ifdef PDSUPPORT 591 uint32_t mr_tbolt_pd_max; 592 struct mrsas_tbolt_pd *mr_tbolt_pd_list; 593 #endif 594 595 uint8_t fast_path_io; 596 597 uint16_t tbolt; 598 uint16_t reply_read_index; 599 uint16_t reply_size; /* Single Reply struct size */ 600 uint16_t raid_io_msg_size; /* Single message size */ 601 uint32_t io_request_frames_phy; 602 uint8_t *io_request_frames; 603 /* Virtual address of request desc frame pool */ 604 MRSAS_REQUEST_DESCRIPTOR_UNION *request_message_pool; 605 /* Physical address of request desc frame pool */ 606 uint32_t request_message_pool_phy; 607 /* Virtual address of reply Frame */ 608 MPI2_REPLY_DESCRIPTORS_UNION *reply_frame_pool; 609 /* Physical address of reply Frame */ 610 uint32_t reply_frame_pool_phy; 611 uint8_t *reply_pool_limit; /* Last reply frame address */ 612 /* Physical address of Last reply frame */ 613 uint32_t reply_pool_limit_phy; 614 uint32_t reply_q_depth; /* Reply Queue Depth */ 615 uint8_t max_sge_in_main_msg; 616 uint8_t max_sge_in_chain; 617 uint8_t chain_offset_io_req; 618 uint8_t chain_offset_mpt_msg; 619 MR_FW_RAID_MAP_ALL *ld_map[2]; 620 uint32_t ld_map_phy[2]; 621 uint32_t size_map_info; 622 uint64_t map_id; 623 LD_LOAD_BALANCE_INFO load_balance_info[MAX_LOGICAL_DRIVES]; 624 struct mrsas_cmd *map_update_cmd; 625 uint32_t SyncRequired; 626 kmutex_t ocr_flags_mtx; 627 dma_obj_t drv_ver_dma_obj; 628 } mrsas_t; 629 630 631 /* 632 * Function templates for various controller specific functions 633 */ 634 struct mrsas_function_template { 635 uint32_t (*read_fw_status_reg)(struct mrsas_instance *); 636 void (*issue_cmd)(struct mrsas_cmd *, struct mrsas_instance *); 637 int (*issue_cmd_in_sync_mode)(struct mrsas_instance *, 638 struct mrsas_cmd *); 639 int (*issue_cmd_in_poll_mode)(struct mrsas_instance *, 640 struct mrsas_cmd *); 641 void (*enable_intr)(struct mrsas_instance *); 642 void (*disable_intr)(struct mrsas_instance *); 643 int (*intr_ack)(struct mrsas_instance *); 644 int (*init_adapter)(struct mrsas_instance *); 645 /* int (*reset_adapter)(struct mrsas_instance *); */ 646 }; 647 648 /* 649 * ### Helper routines ### 650 */ 651 652 /* 653 * con_log() - console log routine 654 * @param level : indicates the severity of the message. 655 * @fparam mt : format string 656 * 657 * con_log displays the error messages on the console based on the current 658 * debug level. Also it attaches the appropriate kernel severity level with 659 * the message. 660 * 661 * 662 * console messages debug levels 663 */ 664 #define CL_NONE 0 /* No debug information */ 665 #define CL_ANN 1 /* print unconditionally, announcements */ 666 #define CL_ANN1 2 /* No-op */ 667 #define CL_DLEVEL1 3 /* debug level 1, informative */ 668 #define CL_DLEVEL2 4 /* debug level 2, verbose */ 669 #define CL_DLEVEL3 5 /* debug level 3, very verbose */ 670 671 #ifdef __SUNPRO_C 672 #define __func__ "" 673 #endif 674 675 #define con_log(level, fmt) { if (debug_level_g >= level) cmn_err fmt; } 676 677 /* 678 * ### SCSA definitions ### 679 */ 680 #define PKT2TGT(pkt) ((pkt)->pkt_address.a_target) 681 #define PKT2LUN(pkt) ((pkt)->pkt_address.a_lun) 682 #define PKT2TRAN(pkt) ((pkt)->pkt_adress.a_hba_tran) 683 #define ADDR2TRAN(ap) ((ap)->a_hba_tran) 684 685 #define TRAN2MR(tran) (struct mrsas_instance *)(tran)->tran_hba_private) 686 #define ADDR2MR(ap) (TRAN2MR(ADDR2TRAN(ap)) 687 688 #define PKT2CMD(pkt) ((struct scsa_cmd *)(pkt)->pkt_ha_private) 689 #define CMD2PKT(sp) ((sp)->cmd_pkt) 690 #define PKT2REQ(pkt) (&(PKT2CMD(pkt)->request)) 691 692 #define CMD2ADDR(cmd) (&CMD2PKT(cmd)->pkt_address) 693 #define CMD2TRAN(cmd) (CMD2PKT(cmd)->pkt_address.a_hba_tran) 694 #define CMD2MR(cmd) (TRAN2MR(CMD2TRAN(cmd))) 695 696 #define CFLAG_DMAVALID 0x0001 /* requires a dma operation */ 697 #define CFLAG_DMASEND 0x0002 /* Transfer from the device */ 698 #define CFLAG_CONSISTENT 0x0040 /* consistent data transfer */ 699 700 /* 701 * ### Data structures for ioctl inteface and internal commands ### 702 */ 703 704 /* 705 * Data direction flags 706 */ 707 #define UIOC_RD 0x00001 708 #define UIOC_WR 0x00002 709 710 #define SCP2HOST(scp) (scp)->device->host /* to host */ 711 #define SCP2HOSTDATA(scp) SCP2HOST(scp)->hostdata /* to soft state */ 712 #define SCP2CHANNEL(scp) (scp)->device->channel /* to channel */ 713 #define SCP2TARGET(scp) (scp)->device->id /* to target */ 714 #define SCP2LUN(scp) (scp)->device->lun /* to LUN */ 715 716 #define SCSIHOST2ADAP(host) (((caddr_t *)(host->hostdata))[0]) 717 #define SCP2ADAPTER(scp) \ 718 (struct mrsas_instance *)SCSIHOST2ADAP(SCP2HOST(scp)) 719 720 #define MRDRV_IS_LOGICAL_SCSA(instance, acmd) \ 721 (acmd->device_id < MRDRV_MAX_LD) ? 1 : 0 722 #define MRDRV_IS_LOGICAL(ap) \ 723 ((ap->a_target < MRDRV_MAX_LD) && (ap->a_lun == 0)) ? 1 : 0 724 #define MAP_DEVICE_ID(instance, ap) \ 725 (ap->a_target) 726 727 #define HIGH_LEVEL_INTR 1 728 #define NORMAL_LEVEL_INTR 0 729 730 #define IO_TIMEOUT_VAL 0 731 #define IO_RETRY_COUNT 3 732 #define MAX_FW_RESET_COUNT 3 733 /* 734 * scsa_cmd - Per-command mr private data 735 * @param cmd_dmahandle : dma handle 736 * @param cmd_dmacookies : current dma cookies 737 * @param cmd_pkt : scsi_pkt reference 738 * @param cmd_dmacount : dma count 739 * @param cmd_cookie : next cookie 740 * @param cmd_ncookies : cookies per window 741 * @param cmd_cookiecnt : cookies per sub-win 742 * @param cmd_nwin : number of dma windows 743 * @param cmd_curwin : current dma window 744 * @param cmd_dma_offset : current window offset 745 * @param cmd_dma_len : current window length 746 * @param cmd_flags : private flags 747 * @param cmd_cdblen : length of cdb 748 * @param cmd_scblen : length of scb 749 * @param cmd_buf : command buffer 750 * @param channel : channel for scsi sub-system 751 * @param target : target for scsi sub-system 752 * @param lun : LUN for scsi sub-system 753 * 754 * - Allocated at same time as scsi_pkt by scsi_hba_pkt_alloc(9E) 755 * - Pointed to by pkt_ha_private field in scsi_pkt 756 */ 757 struct scsa_cmd { 758 ddi_dma_handle_t cmd_dmahandle; 759 ddi_dma_cookie_t cmd_dmacookies[MRSAS_MAX_SGE_CNT]; 760 struct scsi_pkt *cmd_pkt; 761 ulong_t cmd_dmacount; 762 uint_t cmd_cookie; 763 uint_t cmd_ncookies; 764 uint_t cmd_cookiecnt; 765 uint_t cmd_nwin; 766 uint_t cmd_curwin; 767 off_t cmd_dma_offset; 768 ulong_t cmd_dma_len; 769 ulong_t cmd_flags; 770 uint_t cmd_cdblen; 771 uint_t cmd_scblen; 772 struct buf *cmd_buf; 773 ushort_t device_id; 774 uchar_t islogical; 775 uchar_t lun; 776 struct mrsas_device *mrsas_dev; 777 }; 778 779 780 struct mrsas_cmd { 781 /* 782 * ThunderBolt(TB) We would be needing to have a placeholder 783 * for RAID_MSG_IO_REQUEST inside this structure. We are 784 * supposed to embed the mr_frame inside the RAID_MSG and post 785 * it down to the firmware. 786 */ 787 union mrsas_frame *frame; 788 uint32_t frame_phys_addr; 789 uint8_t *sense; 790 uint8_t *sense1; 791 uint32_t sense_phys_addr; 792 uint32_t sense_phys_addr1; 793 dma_obj_t frame_dma_obj; 794 uint8_t frame_dma_obj_status; 795 uint32_t index; 796 uint8_t sync_cmd; 797 uint8_t cmd_status; 798 uint16_t abort_aen; 799 mlist_t list; 800 uint32_t frame_count; 801 struct scsa_cmd *cmd; 802 struct scsi_pkt *pkt; 803 Mpi2RaidSCSIIORequest_t *scsi_io_request; 804 Mpi2SGEIOUnion_t *sgl; 805 uint32_t sgl_phys_addr; 806 uint32_t scsi_io_request_phys_addr; 807 MRSAS_REQUEST_DESCRIPTOR_UNION *request_desc; 808 uint16_t SMID; 809 uint16_t retry_count_for_ocr; 810 uint16_t drv_pkt_time; 811 uint16_t load_balance_flag; 812 813 }; 814 815 #define MAX_MGMT_ADAPTERS 1024 816 #define IOC_SIGNATURE "MR-SAS" 817 818 #define IOC_CMD_FIRMWARE 0x0 819 #define MRSAS_DRIVER_IOCTL_COMMON 0xF0010000 820 #define MRSAS_DRIVER_IOCTL_DRIVER_VERSION 0xF0010100 821 #define MRSAS_DRIVER_IOCTL_PCI_INFORMATION 0xF0010200 822 #define MRSAS_DRIVER_IOCTL_MRRAID_STATISTICS 0xF0010300 823 824 825 #define MRSAS_MAX_SENSE_LENGTH 32 826 827 struct mrsas_mgmt_info { 828 829 uint16_t count; 830 struct mrsas_instance *instance[MAX_MGMT_ADAPTERS]; 831 uint16_t map[MAX_MGMT_ADAPTERS]; 832 int max_index; 833 }; 834 835 836 #pragma pack(1) 837 /* 838 * SAS controller properties 839 */ 840 struct mrsas_ctrl_prop { 841 uint16_t seq_num; 842 uint16_t pred_fail_poll_interval; 843 uint16_t intr_throttle_count; 844 uint16_t intr_throttle_timeouts; 845 846 uint8_t rebuild_rate; 847 uint8_t patrol_read_rate; 848 uint8_t bgi_rate; 849 uint8_t cc_rate; 850 uint8_t recon_rate; 851 852 uint8_t cache_flush_interval; 853 854 uint8_t spinup_drv_count; 855 uint8_t spinup_delay; 856 857 uint8_t cluster_enable; 858 uint8_t coercion_mode; 859 uint8_t alarm_enable; 860 861 uint8_t reserved_1[13]; 862 uint32_t on_off_properties; 863 uint8_t reserved_4[28]; 864 }; 865 866 867 /* 868 * SAS controller information 869 */ 870 struct mrsas_ctrl_info { 871 /* PCI device information */ 872 struct { 873 uint16_t vendor_id; 874 uint16_t device_id; 875 uint16_t sub_vendor_id; 876 uint16_t sub_device_id; 877 uint8_t reserved[24]; 878 } pci; 879 880 /* Host interface information */ 881 struct { 882 uint8_t PCIX : 1; 883 uint8_t PCIE : 1; 884 uint8_t iSCSI : 1; 885 uint8_t SAS_3G : 1; 886 uint8_t reserved_0 : 4; 887 uint8_t reserved_1[6]; 888 uint8_t port_count; 889 uint64_t port_addr[8]; 890 } host_interface; 891 892 /* Device (backend) interface information */ 893 struct { 894 uint8_t SPI : 1; 895 uint8_t SAS_3G : 1; 896 uint8_t SATA_1_5G : 1; 897 uint8_t SATA_3G : 1; 898 uint8_t reserved_0 : 4; 899 uint8_t reserved_1[6]; 900 uint8_t port_count; 901 uint64_t port_addr[8]; 902 } device_interface; 903 904 /* List of components residing in flash. All str are null terminated */ 905 uint32_t image_check_word; 906 uint32_t image_component_count; 907 908 struct { 909 char name[8]; 910 char version[32]; 911 char build_date[16]; 912 char built_time[16]; 913 } image_component[8]; 914 915 /* 916 * List of flash components that have been flashed on the card, but 917 * are not in use, pending reset of the adapter. This list will be 918 * empty if a flash operation has not occurred. All stings are null 919 * terminated 920 */ 921 uint32_t pending_image_component_count; 922 923 struct { 924 char name[8]; 925 char version[32]; 926 char build_date[16]; 927 char build_time[16]; 928 } pending_image_component[8]; 929 930 uint8_t max_arms; 931 uint8_t max_spans; 932 uint8_t max_arrays; 933 uint8_t max_lds; 934 935 char product_name[80]; 936 char serial_no[32]; 937 938 /* 939 * Other physical/controller/operation information. Indicates the 940 * presence of the hardware 941 */ 942 struct { 943 uint32_t bbu : 1; 944 uint32_t alarm : 1; 945 uint32_t nvram : 1; 946 uint32_t uart : 1; 947 uint32_t reserved : 28; 948 } hw_present; 949 950 uint32_t current_fw_time; 951 952 /* Maximum data transfer sizes */ 953 uint16_t max_concurrent_cmds; 954 uint16_t max_sge_count; 955 uint32_t max_request_size; 956 957 /* Logical and physical device counts */ 958 uint16_t ld_present_count; 959 uint16_t ld_degraded_count; 960 uint16_t ld_offline_count; 961 962 uint16_t pd_present_count; 963 uint16_t pd_disk_present_count; 964 uint16_t pd_disk_pred_failure_count; 965 uint16_t pd_disk_failed_count; 966 967 /* Memory size information */ 968 uint16_t nvram_size; 969 uint16_t memory_size; 970 uint16_t flash_size; 971 972 /* Error counters */ 973 uint16_t mem_correctable_error_count; 974 uint16_t mem_uncorrectable_error_count; 975 976 /* Cluster information */ 977 uint8_t cluster_permitted; 978 uint8_t cluster_active; 979 uint8_t reserved_1[2]; 980 981 /* Controller capabilities structures */ 982 struct { 983 uint32_t raid_level_0 : 1; 984 uint32_t raid_level_1 : 1; 985 uint32_t raid_level_5 : 1; 986 uint32_t raid_level_1E : 1; 987 uint32_t reserved : 28; 988 } raid_levels; 989 990 struct { 991 uint32_t rbld_rate : 1; 992 uint32_t cc_rate : 1; 993 uint32_t bgi_rate : 1; 994 uint32_t recon_rate : 1; 995 uint32_t patrol_rate : 1; 996 uint32_t alarm_control : 1; 997 uint32_t cluster_supported : 1; 998 uint32_t bbu : 1; 999 uint32_t spanning_allowed : 1; 1000 uint32_t dedicated_hotspares : 1; 1001 uint32_t revertible_hotspares : 1; 1002 uint32_t foreign_config_import : 1; 1003 uint32_t self_diagnostic : 1; 1004 uint32_t reserved : 19; 1005 } adapter_operations; 1006 1007 struct { 1008 uint32_t read_policy : 1; 1009 uint32_t write_policy : 1; 1010 uint32_t io_policy : 1; 1011 uint32_t access_policy : 1; 1012 uint32_t reserved : 28; 1013 } ld_operations; 1014 1015 struct { 1016 uint8_t min; 1017 uint8_t max; 1018 uint8_t reserved[2]; 1019 } stripe_size_operations; 1020 1021 struct { 1022 uint32_t force_online : 1; 1023 uint32_t force_offline : 1; 1024 uint32_t force_rebuild : 1; 1025 uint32_t reserved : 29; 1026 } pd_operations; 1027 1028 struct { 1029 uint32_t ctrl_supports_sas : 1; 1030 uint32_t ctrl_supports_sata : 1; 1031 uint32_t allow_mix_in_encl : 1; 1032 uint32_t allow_mix_in_ld : 1; 1033 uint32_t allow_sata_in_cluster : 1; 1034 uint32_t reserved : 27; 1035 } pd_mix_support; 1036 1037 /* Include the controller properties (changeable items) */ 1038 uint8_t reserved_2[12]; 1039 struct mrsas_ctrl_prop properties; 1040 1041 uint8_t pad[0x800 - 0x640]; 1042 }; 1043 1044 /* 1045 * ================================== 1046 * MegaRAID SAS2.0 driver definitions 1047 * ================================== 1048 */ 1049 #define MRDRV_MAX_NUM_CMD 1024 1050 1051 #define MRDRV_MAX_PD_CHANNELS 2 1052 #define MRDRV_MAX_LD_CHANNELS 2 1053 #define MRDRV_MAX_CHANNELS (MRDRV_MAX_PD_CHANNELS + \ 1054 MRDRV_MAX_LD_CHANNELS) 1055 #define MRDRV_MAX_DEV_PER_CHANNEL 128 1056 #define MRDRV_DEFAULT_INIT_ID -1 1057 #define MRDRV_MAX_CMD_PER_LUN 1000 1058 #define MRDRV_MAX_LUN 1 1059 #define MRDRV_MAX_LD 64 1060 1061 #define MRDRV_RESET_WAIT_TIME 300 1062 #define MRDRV_RESET_NOTICE_INTERVAL 5 1063 1064 #define MRSAS_IOCTL_CMD 0 1065 1066 #define MRDRV_TGT_VALID 1 1067 1068 /* 1069 * FW can accept both 32 and 64 bit SGLs. We want to allocate 32/64 bit 1070 * SGLs based on the size of dma_addr_t 1071 */ 1072 #define IS_DMA64 (sizeof (dma_addr_t) == 8) 1073 1074 #define RESERVED0_REGISTER 0x00 /* XScale */ 1075 #define IB_MSG_0_OFF 0x10 /* XScale */ 1076 #define OB_MSG_0_OFF 0x18 /* XScale */ 1077 #define IB_DOORBELL_OFF 0x20 /* XScale & ROC */ 1078 #define OB_INTR_STATUS_OFF 0x30 /* XScale & ROC */ 1079 #define OB_INTR_MASK_OFF 0x34 /* XScale & ROC */ 1080 #define IB_QPORT_OFF 0x40 /* XScale & ROC */ 1081 #define OB_DOORBELL_CLEAR_OFF 0xA0 /* ROC */ 1082 #define OB_SCRATCH_PAD_0_OFF 0xB0 /* ROC */ 1083 #define OB_INTR_MASK 0xFFFFFFFF 1084 #define OB_DOORBELL_CLEAR_MASK 0xFFFFFFFF 1085 #define SYSTOIOP_INTERRUPT_MASK 0x80000000 1086 #define OB_SCRATCH_PAD_2_OFF 0xB4 1087 #define WRITE_TBOLT_SEQ_OFF 0x00000004 1088 #define DIAG_TBOLT_RESET_ADAPTER 0x00000004 1089 #define HOST_TBOLT_DIAG_OFF 0x00000008 1090 #define RESET_TBOLT_STATUS_OFF 0x000003C3 1091 #define WRITE_SEQ_OFF 0x000000FC 1092 #define HOST_DIAG_OFF 0x000000F8 1093 #define DIAG_RESET_ADAPTER 0x00000004 1094 #define DIAG_WRITE_ENABLE 0x00000080 1095 #define SYSTOIOP_INTERRUPT_MASK 0x80000000 1096 1097 #define WR_IB_WRITE_SEQ(v, instance) ddi_put32((instance)->regmap_handle, \ 1098 (uint32_t *)((uintptr_t)(instance)->regmap + WRITE_SEQ_OFF), (v)) 1099 1100 #define RD_OB_DRWE(instance) ddi_get32((instance)->regmap_handle, \ 1101 (uint32_t *)((uintptr_t)(instance)->regmap + HOST_DIAG_OFF)) 1102 1103 #define WR_IB_DRWE(v, instance) ddi_put32((instance)->regmap_handle, \ 1104 (uint32_t *)((uintptr_t)(instance)->regmap + HOST_DIAG_OFF), (v)) 1105 1106 #define IB_LOW_QPORT 0xC0 1107 #define IB_HIGH_QPORT 0xC4 1108 #define OB_DOORBELL_REGISTER 0x9C /* 1078 implementation */ 1109 1110 /* 1111 * All MFI register set macros accept mrsas_register_set* 1112 */ 1113 #define WR_IB_MSG_0(v, instance) ddi_put32((instance)->regmap_handle, \ 1114 (uint32_t *)((uintptr_t)(instance)->regmap + IB_MSG_0_OFF), (v)) 1115 1116 #define RD_OB_MSG_0(instance) ddi_get32((instance)->regmap_handle, \ 1117 (uint32_t *)((uintptr_t)(instance)->regmap + OB_MSG_0_OFF)) 1118 1119 #define WR_IB_DOORBELL(v, instance) ddi_put32((instance)->regmap_handle, \ 1120 (uint32_t *)((uintptr_t)(instance)->regmap + IB_DOORBELL_OFF), (v)) 1121 1122 #define RD_IB_DOORBELL(instance) ddi_get32((instance)->regmap_handle, \ 1123 (uint32_t *)((uintptr_t)(instance)->regmap + IB_DOORBELL_OFF)) 1124 1125 #define WR_OB_INTR_STATUS(v, instance) ddi_put32((instance)->regmap_handle, \ 1126 (uint32_t *)((uintptr_t)(instance)->regmap + OB_INTR_STATUS_OFF), (v)) 1127 1128 #define RD_OB_INTR_STATUS(instance) ddi_get32((instance)->regmap_handle, \ 1129 (uint32_t *)((uintptr_t)(instance)->regmap + OB_INTR_STATUS_OFF)) 1130 1131 #define WR_OB_INTR_MASK(v, instance) ddi_put32((instance)->regmap_handle, \ 1132 (uint32_t *)((uintptr_t)(instance)->regmap + OB_INTR_MASK_OFF), (v)) 1133 1134 #define RD_OB_INTR_MASK(instance) ddi_get32((instance)->regmap_handle, \ 1135 (uint32_t *)((uintptr_t)(instance)->regmap + OB_INTR_MASK_OFF)) 1136 1137 #define WR_IB_QPORT(v, instance) ddi_put32((instance)->regmap_handle, \ 1138 (uint32_t *)((uintptr_t)(instance)->regmap + IB_QPORT_OFF), (v)) 1139 1140 #define WR_OB_DOORBELL_CLEAR(v, instance) ddi_put32((instance)->regmap_handle, \ 1141 (uint32_t *)((uintptr_t)(instance)->regmap + OB_DOORBELL_CLEAR_OFF), \ 1142 (v)) 1143 1144 #define RD_OB_SCRATCH_PAD_0(instance) ddi_get32((instance)->regmap_handle, \ 1145 (uint32_t *)((uintptr_t)(instance)->regmap + OB_SCRATCH_PAD_0_OFF)) 1146 1147 /* Thunderbolt specific registers */ 1148 #define RD_OB_SCRATCH_PAD_2(instance) ddi_get32((instance)->regmap_handle, \ 1149 (uint32_t *)((uintptr_t)(instance)->regmap + OB_SCRATCH_PAD_2_OFF)) 1150 1151 #define WR_TBOLT_IB_WRITE_SEQ(v, instance) \ 1152 ddi_put32((instance)->regmap_handle, \ 1153 (uint32_t *)((uintptr_t)(instance)->regmap + WRITE_TBOLT_SEQ_OFF), (v)) 1154 1155 #define RD_TBOLT_HOST_DIAG(instance) ddi_get32((instance)->regmap_handle, \ 1156 (uint32_t *)((uintptr_t)(instance)->regmap + HOST_TBOLT_DIAG_OFF)) 1157 1158 #define WR_TBOLT_HOST_DIAG(v, instance) ddi_put32((instance)->regmap_handle, \ 1159 (uint32_t *)((uintptr_t)(instance)->regmap + HOST_TBOLT_DIAG_OFF), (v)) 1160 1161 #define RD_TBOLT_RESET_STAT(instance) ddi_get32((instance)->regmap_handle, \ 1162 (uint32_t *)((uintptr_t)(instance)->regmap + RESET_TBOLT_STATUS_OFF)) 1163 1164 1165 #define WR_MPI2_REPLY_POST_INDEX(v, instance)\ 1166 ddi_put32((instance)->regmap_handle,\ 1167 (uint32_t *)\ 1168 ((uintptr_t)(instance)->regmap + MPI2_REPLY_POST_HOST_INDEX_OFFSET),\ 1169 (v)) 1170 1171 1172 #define RD_MPI2_REPLY_POST_INDEX(instance)\ 1173 ddi_get32((instance)->regmap_handle,\ 1174 (uint32_t *)\ 1175 ((uintptr_t)(instance)->regmap + MPI2_REPLY_POST_HOST_INDEX_OFFSET)) 1176 1177 #define WR_IB_LOW_QPORT(v, instance) ddi_put32((instance)->regmap_handle, \ 1178 (uint32_t *)((uintptr_t)(instance)->regmap + IB_LOW_QPORT), (v)) 1179 1180 #define WR_IB_HIGH_QPORT(v, instance) ddi_put32((instance)->regmap_handle, \ 1181 (uint32_t *)((uintptr_t)(instance)->regmap + IB_HIGH_QPORT), (v)) 1182 1183 #define WR_OB_DOORBELL_REGISTER_CLEAR(v, instance)\ 1184 ddi_put32((instance)->regmap_handle,\ 1185 (uint32_t *)((uintptr_t)(instance)->regmap + OB_DOORBELL_REGISTER), \ 1186 (v)) 1187 1188 #define WR_RESERVED0_REGISTER(v, instance) ddi_put32((instance)->regmap_handle,\ 1189 (uint32_t *)((uintptr_t)(instance)->regmap + RESERVED0_REGISTER), \ 1190 (v)) 1191 1192 #define RD_RESERVED0_REGISTER(instance) ddi_get32((instance)->regmap_handle, \ 1193 (uint32_t *)((uintptr_t)(instance)->regmap + RESERVED0_REGISTER)) 1194 1195 1196 1197 /* 1198 * When FW is in MFI_STATE_READY or MFI_STATE_OPERATIONAL, the state data 1199 * of Outbound Msg Reg 0 indicates max concurrent cmds supported, max SGEs 1200 * supported per cmd and if 64-bit MFAs (M64) is enabled or disabled. 1201 */ 1202 #define MFI_OB_INTR_STATUS_MASK 0x00000002 1203 1204 /* 1205 * This MFI_REPLY_2108_MESSAGE_INTR flag is used also 1206 * in enable_intr_ppc also. Hence bit 2, i.e. 0x4 has 1207 * been set in this flag along with bit 1. 1208 */ 1209 #define MFI_REPLY_2108_MESSAGE_INTR 0x00000001 1210 #define MFI_REPLY_2108_MESSAGE_INTR_MASK 0x00000005 1211 1212 /* Fusion interrupt mask */ 1213 #define MFI_FUSION_ENABLE_INTERRUPT_MASK (0x00000008) 1214 1215 #define MFI_POLL_TIMEOUT_SECS 60 1216 1217 #define MFI_ENABLE_INTR(instance) ddi_put32((instance)->regmap_handle, \ 1218 (uint32_t *)((uintptr_t)(instance)->regmap + OB_INTR_MASK_OFF), 1) 1219 #define MFI_DISABLE_INTR(instance) \ 1220 { \ 1221 uint32_t disable = 1; \ 1222 uint32_t mask = ddi_get32((instance)->regmap_handle, \ 1223 (uint32_t *)((uintptr_t)(instance)->regmap + OB_INTR_MASK_OFF));\ 1224 mask &= ~disable; \ 1225 ddi_put32((instance)->regmap_handle, (uint32_t *) \ 1226 (uintptr_t)((instance)->regmap + OB_INTR_MASK_OFF), mask); \ 1227 } 1228 1229 /* By default, the firmware programs for 8 Kbytes of memory */ 1230 #define DEFAULT_MFI_MEM_SZ 8192 1231 #define MINIMUM_MFI_MEM_SZ 4096 1232 1233 /* DCMD Message Frame MAILBOX0-11 */ 1234 #define DCMD_MBOX_SZ 12 1235 1236 /* 1237 * on_off_property of mrsas_ctrl_prop 1238 * bit0-9, 11-31 are reserved 1239 */ 1240 #define DISABLE_OCR_PROP_FLAG 0x00000400 /* bit 10 */ 1241 1242 struct mrsas_register_set { 1243 uint32_t reserved_0[4]; /* 0000h */ 1244 1245 uint32_t inbound_msg_0; /* 0010h */ 1246 uint32_t inbound_msg_1; /* 0014h */ 1247 uint32_t outbound_msg_0; /* 0018h */ 1248 uint32_t outbound_msg_1; /* 001Ch */ 1249 1250 uint32_t inbound_doorbell; /* 0020h */ 1251 uint32_t inbound_intr_status; /* 0024h */ 1252 uint32_t inbound_intr_mask; /* 0028h */ 1253 1254 uint32_t outbound_doorbell; /* 002Ch */ 1255 uint32_t outbound_intr_status; /* 0030h */ 1256 uint32_t outbound_intr_mask; /* 0034h */ 1257 1258 uint32_t reserved_1[2]; /* 0038h */ 1259 1260 uint32_t inbound_queue_port; /* 0040h */ 1261 uint32_t outbound_queue_port; /* 0044h */ 1262 1263 uint32_t reserved_2[22]; /* 0048h */ 1264 1265 uint32_t outbound_doorbell_clear; /* 00A0h */ 1266 1267 uint32_t reserved_3[3]; /* 00A4h */ 1268 1269 uint32_t outbound_scratch_pad; /* 00B0h */ 1270 1271 uint32_t reserved_4[3]; /* 00B4h */ 1272 1273 uint32_t inbound_low_queue_port; /* 00C0h */ 1274 1275 uint32_t inbound_high_queue_port; /* 00C4h */ 1276 1277 uint32_t reserved_5; /* 00C8h */ 1278 uint32_t index_registers[820]; /* 00CCh */ 1279 }; 1280 1281 struct mrsas_sge32 { 1282 uint32_t phys_addr; 1283 uint32_t length; 1284 }; 1285 1286 struct mrsas_sge64 { 1287 uint64_t phys_addr; 1288 uint32_t length; 1289 }; 1290 1291 struct mrsas_sge_ieee { 1292 uint64_t phys_addr; 1293 uint32_t length; 1294 uint32_t flag; 1295 }; 1296 1297 union mrsas_sgl { 1298 struct mrsas_sge32 sge32[1]; 1299 struct mrsas_sge64 sge64[1]; 1300 struct mrsas_sge_ieee sge_ieee[1]; 1301 }; 1302 1303 struct mrsas_header { 1304 uint8_t cmd; /* 00h */ 1305 uint8_t sense_len; /* 01h */ 1306 uint8_t cmd_status; /* 02h */ 1307 uint8_t scsi_status; /* 03h */ 1308 1309 uint8_t target_id; /* 04h */ 1310 uint8_t lun; /* 05h */ 1311 uint8_t cdb_len; /* 06h */ 1312 uint8_t sge_count; /* 07h */ 1313 1314 uint32_t context; /* 08h */ 1315 uint8_t req_id; /* 0Ch */ 1316 uint8_t msgvector; /* 0Dh */ 1317 uint16_t pad_0; /* 0Eh */ 1318 1319 uint16_t flags; /* 10h */ 1320 uint16_t timeout; /* 12h */ 1321 uint32_t data_xferlen; /* 14h */ 1322 }; 1323 1324 union mrsas_sgl_frame { 1325 struct mrsas_sge32 sge32[8]; 1326 struct mrsas_sge64 sge64[5]; 1327 }; 1328 1329 struct mrsas_init_frame { 1330 uint8_t cmd; /* 00h */ 1331 uint8_t reserved_0; /* 01h */ 1332 uint8_t cmd_status; /* 02h */ 1333 1334 uint8_t reserved_1; /* 03h */ 1335 uint32_t reserved_2; /* 04h */ 1336 1337 uint32_t context; /* 08h */ 1338 uint8_t req_id; /* 0Ch */ 1339 uint8_t msgvector; /* 0Dh */ 1340 uint16_t pad_0; /* 0Eh */ 1341 1342 uint16_t flags; /* 10h */ 1343 uint16_t reserved_3; /* 12h */ 1344 uint32_t data_xfer_len; /* 14h */ 1345 1346 uint32_t queue_info_new_phys_addr_lo; /* 18h */ 1347 uint32_t queue_info_new_phys_addr_hi; /* 1Ch */ 1348 uint32_t queue_info_old_phys_addr_lo; /* 20h */ 1349 uint32_t queue_info_old_phys_addr_hi; /* 24h */ 1350 uint64_t driverversion; /* 28h */ 1351 uint32_t reserved_4[4]; /* 30h */ 1352 }; 1353 1354 struct mrsas_init_queue_info { 1355 uint32_t init_flags; /* 00h */ 1356 uint32_t reply_queue_entries; /* 04h */ 1357 1358 uint32_t reply_queue_start_phys_addr_lo; /* 08h */ 1359 uint32_t reply_queue_start_phys_addr_hi; /* 0Ch */ 1360 uint32_t producer_index_phys_addr_lo; /* 10h */ 1361 uint32_t producer_index_phys_addr_hi; /* 14h */ 1362 uint32_t consumer_index_phys_addr_lo; /* 18h */ 1363 uint32_t consumer_index_phys_addr_hi; /* 1Ch */ 1364 }; 1365 1366 struct mrsas_io_frame { 1367 uint8_t cmd; /* 00h */ 1368 uint8_t sense_len; /* 01h */ 1369 uint8_t cmd_status; /* 02h */ 1370 uint8_t scsi_status; /* 03h */ 1371 1372 uint8_t target_id; /* 04h */ 1373 uint8_t access_byte; /* 05h */ 1374 uint8_t reserved_0; /* 06h */ 1375 uint8_t sge_count; /* 07h */ 1376 1377 uint32_t context; /* 08h */ 1378 uint8_t req_id; /* 0Ch */ 1379 uint8_t msgvector; /* 0Dh */ 1380 uint16_t pad_0; /* 0Eh */ 1381 1382 uint16_t flags; /* 10h */ 1383 uint16_t timeout; /* 12h */ 1384 uint32_t lba_count; /* 14h */ 1385 1386 uint32_t sense_buf_phys_addr_lo; /* 18h */ 1387 uint32_t sense_buf_phys_addr_hi; /* 1Ch */ 1388 1389 uint32_t start_lba_lo; /* 20h */ 1390 uint32_t start_lba_hi; /* 24h */ 1391 1392 union mrsas_sgl sgl; /* 28h */ 1393 }; 1394 1395 struct mrsas_pthru_frame { 1396 uint8_t cmd; /* 00h */ 1397 uint8_t sense_len; /* 01h */ 1398 uint8_t cmd_status; /* 02h */ 1399 uint8_t scsi_status; /* 03h */ 1400 1401 uint8_t target_id; /* 04h */ 1402 uint8_t lun; /* 05h */ 1403 uint8_t cdb_len; /* 06h */ 1404 uint8_t sge_count; /* 07h */ 1405 1406 uint32_t context; /* 08h */ 1407 uint8_t req_id; /* 0Ch */ 1408 uint8_t msgvector; /* 0Dh */ 1409 uint16_t pad_0; /* 0Eh */ 1410 1411 uint16_t flags; /* 10h */ 1412 uint16_t timeout; /* 12h */ 1413 uint32_t data_xfer_len; /* 14h */ 1414 1415 uint32_t sense_buf_phys_addr_lo; /* 18h */ 1416 uint32_t sense_buf_phys_addr_hi; /* 1Ch */ 1417 1418 uint8_t cdb[16]; /* 20h */ 1419 union mrsas_sgl sgl; /* 30h */ 1420 }; 1421 1422 struct mrsas_dcmd_frame { 1423 uint8_t cmd; /* 00h */ 1424 uint8_t reserved_0; /* 01h */ 1425 uint8_t cmd_status; /* 02h */ 1426 uint8_t reserved_1[4]; /* 03h */ 1427 uint8_t sge_count; /* 07h */ 1428 1429 uint32_t context; /* 08h */ 1430 uint8_t req_id; /* 0Ch */ 1431 uint8_t msgvector; /* 0Dh */ 1432 uint16_t pad_0; /* 0Eh */ 1433 1434 uint16_t flags; /* 10h */ 1435 uint16_t timeout; /* 12h */ 1436 1437 uint32_t data_xfer_len; /* 14h */ 1438 uint32_t opcode; /* 18h */ 1439 1440 /* uint8_t mbox[DCMD_MBOX_SZ]; */ /* 1Ch */ 1441 union { /* 1Ch */ 1442 uint8_t b[DCMD_MBOX_SZ]; 1443 uint16_t s[6]; 1444 uint32_t w[3]; 1445 } mbox; 1446 1447 union mrsas_sgl sgl; /* 28h */ 1448 }; 1449 1450 struct mrsas_abort_frame { 1451 uint8_t cmd; /* 00h */ 1452 uint8_t reserved_0; /* 01h */ 1453 uint8_t cmd_status; /* 02h */ 1454 1455 uint8_t reserved_1; /* 03h */ 1456 uint32_t reserved_2; /* 04h */ 1457 1458 uint32_t context; /* 08h */ 1459 uint8_t req_id; /* 0Ch */ 1460 uint8_t msgvector; /* 0Dh */ 1461 uint16_t pad_0; /* 0Eh */ 1462 1463 uint16_t flags; /* 10h */ 1464 uint16_t reserved_3; /* 12h */ 1465 uint32_t reserved_4; /* 14h */ 1466 1467 uint32_t abort_context; /* 18h */ 1468 uint32_t pad_1; /* 1Ch */ 1469 1470 uint32_t abort_mfi_phys_addr_lo; /* 20h */ 1471 uint32_t abort_mfi_phys_addr_hi; /* 24h */ 1472 1473 uint32_t reserved_5[6]; /* 28h */ 1474 }; 1475 1476 struct mrsas_smp_frame { 1477 uint8_t cmd; /* 00h */ 1478 uint8_t reserved_1; /* 01h */ 1479 uint8_t cmd_status; /* 02h */ 1480 uint8_t connection_status; /* 03h */ 1481 1482 uint8_t reserved_2[3]; /* 04h */ 1483 uint8_t sge_count; /* 07h */ 1484 1485 uint32_t context; /* 08h */ 1486 uint8_t req_id; /* 0Ch */ 1487 uint8_t msgvector; /* 0Dh */ 1488 uint16_t pad_0; /* 0Eh */ 1489 1490 uint16_t flags; /* 10h */ 1491 uint16_t timeout; /* 12h */ 1492 1493 uint32_t data_xfer_len; /* 14h */ 1494 1495 uint64_t sas_addr; /* 20h */ 1496 1497 union mrsas_sgl sgl[2]; /* 28h */ 1498 }; 1499 1500 struct mrsas_stp_frame { 1501 uint8_t cmd; /* 00h */ 1502 uint8_t reserved_1; /* 01h */ 1503 uint8_t cmd_status; /* 02h */ 1504 uint8_t connection_status; /* 03h */ 1505 1506 uint8_t target_id; /* 04h */ 1507 uint8_t reserved_2[2]; /* 04h */ 1508 uint8_t sge_count; /* 07h */ 1509 1510 uint32_t context; /* 08h */ 1511 uint8_t req_id; /* 0Ch */ 1512 uint8_t msgvector; /* 0Dh */ 1513 uint16_t pad_0; /* 0Eh */ 1514 1515 uint16_t flags; /* 10h */ 1516 uint16_t timeout; /* 12h */ 1517 1518 uint32_t data_xfer_len; /* 14h */ 1519 1520 uint16_t fis[10]; /* 28h */ 1521 uint32_t stp_flags; /* 3C */ 1522 union mrsas_sgl sgl; /* 40 */ 1523 }; 1524 1525 union mrsas_frame { 1526 struct mrsas_header hdr; 1527 struct mrsas_init_frame init; 1528 struct mrsas_io_frame io; 1529 struct mrsas_pthru_frame pthru; 1530 struct mrsas_dcmd_frame dcmd; 1531 struct mrsas_abort_frame abort; 1532 struct mrsas_smp_frame smp; 1533 struct mrsas_stp_frame stp; 1534 1535 uint8_t raw_bytes[64]; 1536 }; 1537 1538 typedef struct mrsas_pd_address { 1539 uint16_t device_id; 1540 uint16_t encl_id; 1541 1542 union { 1543 struct { 1544 uint8_t encl_index; 1545 uint8_t slot_number; 1546 } pd_address; 1547 struct { 1548 uint8_t encl_position; 1549 uint8_t encl_connector_index; 1550 } encl_address; 1551 }address; 1552 1553 uint8_t scsi_dev_type; 1554 1555 union { 1556 uint8_t port_bitmap; 1557 uint8_t port_numbers; 1558 } connected; 1559 1560 uint64_t sas_addr[2]; 1561 } mrsas_pd_address_t; 1562 1563 union mrsas_evt_class_locale { 1564 struct { 1565 uint16_t locale; 1566 uint8_t reserved; 1567 int8_t class; 1568 } members; 1569 1570 uint32_t word; 1571 }; 1572 1573 struct mrsas_evt_log_info { 1574 uint32_t newest_seq_num; 1575 uint32_t oldest_seq_num; 1576 uint32_t clear_seq_num; 1577 uint32_t shutdown_seq_num; 1578 uint32_t boot_seq_num; 1579 }; 1580 1581 struct mrsas_progress { 1582 uint16_t progress; 1583 uint16_t elapsed_seconds; 1584 }; 1585 1586 struct mrsas_evtarg_ld { 1587 uint16_t target_id; 1588 uint8_t ld_index; 1589 uint8_t reserved; 1590 }; 1591 1592 struct mrsas_evtarg_pd { 1593 uint16_t device_id; 1594 uint8_t encl_index; 1595 uint8_t slot_number; 1596 }; 1597 1598 struct mrsas_evt_detail { 1599 uint32_t seq_num; 1600 uint32_t time_stamp; 1601 uint32_t code; 1602 union mrsas_evt_class_locale cl; 1603 uint8_t arg_type; 1604 uint8_t reserved1[15]; 1605 1606 union { 1607 struct { 1608 struct mrsas_evtarg_pd pd; 1609 uint8_t cdb_length; 1610 uint8_t sense_length; 1611 uint8_t reserved[2]; 1612 uint8_t cdb[16]; 1613 uint8_t sense[64]; 1614 } cdbSense; 1615 1616 struct mrsas_evtarg_ld ld; 1617 1618 struct { 1619 struct mrsas_evtarg_ld ld; 1620 uint64_t count; 1621 } ld_count; 1622 1623 struct { 1624 uint64_t lba; 1625 struct mrsas_evtarg_ld ld; 1626 } ld_lba; 1627 1628 struct { 1629 struct mrsas_evtarg_ld ld; 1630 uint32_t prevOwner; 1631 uint32_t newOwner; 1632 } ld_owner; 1633 1634 struct { 1635 uint64_t ld_lba; 1636 uint64_t pd_lba; 1637 struct mrsas_evtarg_ld ld; 1638 struct mrsas_evtarg_pd pd; 1639 } ld_lba_pd_lba; 1640 1641 struct { 1642 struct mrsas_evtarg_ld ld; 1643 struct mrsas_progress prog; 1644 } ld_prog; 1645 1646 struct { 1647 struct mrsas_evtarg_ld ld; 1648 uint32_t prev_state; 1649 uint32_t new_state; 1650 } ld_state; 1651 1652 struct { 1653 uint64_t strip; 1654 struct mrsas_evtarg_ld ld; 1655 } ld_strip; 1656 1657 struct mrsas_evtarg_pd pd; 1658 1659 struct { 1660 struct mrsas_evtarg_pd pd; 1661 uint32_t err; 1662 } pd_err; 1663 1664 struct { 1665 uint64_t lba; 1666 struct mrsas_evtarg_pd pd; 1667 } pd_lba; 1668 1669 struct { 1670 uint64_t lba; 1671 struct mrsas_evtarg_pd pd; 1672 struct mrsas_evtarg_ld ld; 1673 } pd_lba_ld; 1674 1675 struct { 1676 struct mrsas_evtarg_pd pd; 1677 struct mrsas_progress prog; 1678 } pd_prog; 1679 1680 struct { 1681 struct mrsas_evtarg_pd pd; 1682 uint32_t prevState; 1683 uint32_t newState; 1684 } pd_state; 1685 1686 struct { 1687 uint16_t vendorId; 1688 uint16_t deviceId; 1689 uint16_t subVendorId; 1690 uint16_t subDeviceId; 1691 } pci; 1692 1693 uint32_t rate; 1694 char str[96]; 1695 1696 struct { 1697 uint32_t rtc; 1698 uint32_t elapsedSeconds; 1699 } time; 1700 1701 struct { 1702 uint32_t ecar; 1703 uint32_t elog; 1704 char str[64]; 1705 } ecc; 1706 1707 mrsas_pd_address_t pd_addr; 1708 1709 uint8_t b[96]; 1710 uint16_t s[48]; 1711 uint32_t w[24]; 1712 uint64_t d[12]; 1713 } args; 1714 1715 char description[128]; 1716 1717 }; 1718 1719 /* only 63 are usable by the application */ 1720 #define MAX_LOGICAL_DRIVES 64 1721 /* only 255 physical devices may be used */ 1722 #define MAX_PHYSICAL_DEVICES 256 1723 #define MAX_PD_PER_ENCLOSURE 64 1724 /* maximum disks per array */ 1725 #define MAX_ROW_SIZE 32 1726 /* maximum spans per logical drive */ 1727 #define MAX_SPAN_DEPTH 8 1728 /* maximum number of arrays a hot spare may be dedicated to */ 1729 #define MAX_ARRAYS_DEDICATED 16 1730 /* maximum number of arrays which may exist */ 1731 #define MAX_ARRAYS 128 1732 /* maximum number of foreign configs that may ha managed at once */ 1733 #define MAX_FOREIGN_CONFIGS 8 1734 /* maximum spares (global and dedicated combined) */ 1735 #define MAX_SPARES_FOR_THE_CONTROLLER MAX_PHYSICAL_DEVICES 1736 /* maximum possible Target IDs (i.e. 0 to 63) */ 1737 #define MAX_TARGET_ID 63 1738 /* maximum number of supported enclosures */ 1739 #define MAX_ENCLOSURES 32 1740 /* maximum number of PHYs per controller */ 1741 #define MAX_PHYS_PER_CONTROLLER 16 1742 /* maximum number of LDs per array (due to DDF limitations) */ 1743 #define MAX_LDS_PER_ARRAY 16 1744 1745 /* 1746 * ----------------------------------------------------------------------------- 1747 * ----------------------------------------------------------------------------- 1748 * 1749 * Logical Drive commands 1750 * 1751 * ----------------------------------------------------------------------------- 1752 * ----------------------------------------------------------------------------- 1753 */ 1754 #define MR_DCMD_LD 0x03000000, /* Logical Device (LD) opcodes */ 1755 1756 /* 1757 * Input: dcmd.opcode - MR_DCMD_LD_GET_LIST 1758 * dcmd.mbox - reserved 1759 * dcmd.sge IN - ptr to returned MR_LD_LIST structure 1760 * Desc: Return the logical drive list structure 1761 * Status: No error 1762 */ 1763 1764 /* 1765 * defines the logical drive reference structure 1766 */ 1767 typedef union _MR_LD_REF { /* LD reference structure */ 1768 struct { 1769 uint8_t targetId; /* LD target id (0 to MAX_TARGET_ID) */ 1770 uint8_t reserved; /* reserved for in line with MR_PD_REF */ 1771 uint16_t seqNum; /* Sequence Number */ 1772 } ld_ref; 1773 uint32_t ref; /* shorthand reference to full 32-bits */ 1774 } MR_LD_REF; /* 4 bytes */ 1775 1776 /* 1777 * defines the logical drive list structure 1778 */ 1779 typedef struct _MR_LD_LIST { 1780 uint32_t ldCount; /* number of LDs */ 1781 uint32_t reserved; /* pad to 8-byte boundary */ 1782 struct { 1783 MR_LD_REF ref; /* LD reference */ 1784 uint8_t state; /* current LD state (MR_LD_STATE) */ 1785 uint8_t reserved[3]; /* pad to 8-byte boundary */ 1786 uint64_t size; /* LD size */ 1787 } ldList[MAX_LOGICAL_DRIVES]; 1788 } MR_LD_LIST; 1789 1790 struct mrsas_drv_ver { 1791 uint8_t signature[12]; 1792 uint8_t os_name[16]; 1793 uint8_t os_ver[12]; 1794 uint8_t drv_name[20]; 1795 uint8_t drv_ver[32]; 1796 uint8_t drv_rel_date[20]; 1797 }; 1798 1799 #define PCI_TYPE0_ADDRESSES 6 1800 #define PCI_TYPE1_ADDRESSES 2 1801 #define PCI_TYPE2_ADDRESSES 5 1802 1803 struct mrsas_pci_common_header { 1804 uint16_t vendorID; /* (ro) */ 1805 uint16_t deviceID; /* (ro) */ 1806 uint16_t command; /* Device control */ 1807 uint16_t status; 1808 uint8_t revisionID; /* (ro) */ 1809 uint8_t progIf; /* (ro) */ 1810 uint8_t subClass; /* (ro) */ 1811 uint8_t baseClass; /* (ro) */ 1812 uint8_t cacheLineSize; /* (ro+) */ 1813 uint8_t latencyTimer; /* (ro+) */ 1814 uint8_t headerType; /* (ro) */ 1815 uint8_t bist; /* Built in self test */ 1816 1817 union { 1818 struct { 1819 uint32_t baseAddresses[PCI_TYPE0_ADDRESSES]; 1820 uint32_t cis; 1821 uint16_t subVendorID; 1822 uint16_t subSystemID; 1823 uint32_t romBaseAddress; 1824 uint8_t capabilitiesPtr; 1825 uint8_t reserved1[3]; 1826 uint32_t reserved2; 1827 uint8_t interruptLine; 1828 uint8_t interruptPin; /* (ro) */ 1829 uint8_t minimumGrant; /* (ro) */ 1830 uint8_t maximumLatency; /* (ro) */ 1831 } type_0; 1832 1833 struct { 1834 uint32_t baseAddresses[PCI_TYPE1_ADDRESSES]; 1835 uint8_t primaryBus; 1836 uint8_t secondaryBus; 1837 uint8_t subordinateBus; 1838 uint8_t secondaryLatency; 1839 uint8_t ioBase; 1840 uint8_t ioLimit; 1841 uint16_t secondaryStatus; 1842 uint16_t memoryBase; 1843 uint16_t memoryLimit; 1844 uint16_t prefetchBase; 1845 uint16_t prefetchLimit; 1846 uint32_t prefetchBaseUpper32; 1847 uint32_t prefetchLimitUpper32; 1848 uint16_t ioBaseUpper16; 1849 uint16_t ioLimitUpper16; 1850 uint8_t capabilitiesPtr; 1851 uint8_t reserved1[3]; 1852 uint32_t romBaseAddress; 1853 uint8_t interruptLine; 1854 uint8_t interruptPin; 1855 uint16_t bridgeControl; 1856 } type_1; 1857 1858 struct { 1859 uint32_t socketRegistersBaseAddress; 1860 uint8_t capabilitiesPtr; 1861 uint8_t reserved; 1862 uint16_t secondaryStatus; 1863 uint8_t primaryBus; 1864 uint8_t secondaryBus; 1865 uint8_t subordinateBus; 1866 uint8_t secondaryLatency; 1867 struct { 1868 uint32_t base; 1869 uint32_t limit; 1870 } range[PCI_TYPE2_ADDRESSES-1]; 1871 uint8_t interruptLine; 1872 uint8_t interruptPin; 1873 uint16_t bridgeControl; 1874 } type_2; 1875 } header; 1876 }; 1877 1878 struct mrsas_pci_link_capability { 1879 union { 1880 struct { 1881 uint32_t linkSpeed :4; 1882 uint32_t linkWidth :6; 1883 uint32_t aspmSupport :2; 1884 uint32_t losExitLatency :3; 1885 uint32_t l1ExitLatency :3; 1886 uint32_t rsvdp :6; 1887 uint32_t portNumber :8; 1888 } bits; 1889 1890 uint32_t asUlong; 1891 } cap; 1892 1893 }; 1894 1895 struct mrsas_pci_link_status_capability { 1896 union { 1897 struct { 1898 uint16_t linkSpeed :4; 1899 uint16_t negotiatedLinkWidth :6; 1900 uint16_t linkTrainingError :1; 1901 uint16_t linkTraning :1; 1902 uint16_t slotClockConfig :1; 1903 uint16_t rsvdZ :3; 1904 } bits; 1905 1906 uint16_t asUshort; 1907 } stat_cap; 1908 1909 uint16_t reserved; 1910 1911 }; 1912 1913 struct mrsas_pci_capabilities { 1914 struct mrsas_pci_link_capability linkCapability; 1915 struct mrsas_pci_link_status_capability linkStatusCapability; 1916 }; 1917 1918 struct mrsas_pci_information 1919 { 1920 uint32_t busNumber; 1921 uint8_t deviceNumber; 1922 uint8_t functionNumber; 1923 uint8_t interruptVector; 1924 uint8_t reserved; 1925 struct mrsas_pci_common_header pciHeaderInfo; 1926 struct mrsas_pci_capabilities capability; 1927 uint8_t reserved2[32]; 1928 }; 1929 1930 struct mrsas_ioctl { 1931 uint16_t version; 1932 uint16_t controller_id; 1933 uint8_t signature[8]; 1934 uint32_t reserved_1; 1935 uint32_t control_code; 1936 uint32_t reserved_2[2]; 1937 uint8_t frame[64]; 1938 union mrsas_sgl_frame sgl_frame; 1939 uint8_t sense_buff[MRSAS_MAX_SENSE_LENGTH]; 1940 uint8_t data[1]; 1941 }; 1942 1943 struct mrsas_aen { 1944 uint16_t host_no; 1945 uint16_t cmd_status; 1946 uint32_t seq_num; 1947 uint32_t class_locale_word; 1948 }; 1949 1950 #pragma pack() 1951 1952 #ifndef DDI_VENDOR_LSI 1953 #define DDI_VENDOR_LSI "LSI" 1954 #endif /* DDI_VENDOR_LSI */ 1955 1956 int mrsas_config_scsi_device(struct mrsas_instance *, 1957 struct scsi_device *, dev_info_t **); 1958 1959 #ifdef PDSUPPORT 1960 int mrsas_tbolt_config_pd(struct mrsas_instance *, uint16_t, 1961 uint8_t, dev_info_t **); 1962 #endif 1963 1964 dev_info_t *mrsas_find_child(struct mrsas_instance *, uint16_t, uint8_t); 1965 int mrsas_service_evt(struct mrsas_instance *, int, int, int, uint64_t); 1966 void return_raid_msg_pkt(struct mrsas_instance *, struct mrsas_cmd *); 1967 struct mrsas_cmd *get_raid_msg_mfi_pkt(struct mrsas_instance *); 1968 void return_raid_msg_mfi_pkt(struct mrsas_instance *, struct mrsas_cmd *); 1969 1970 int alloc_space_for_mpi2(struct mrsas_instance *); 1971 void fill_up_drv_ver(struct mrsas_drv_ver *dv); 1972 1973 int mrsas_issue_init_mpi2(struct mrsas_instance *); 1974 struct scsi_pkt *mrsas_tbolt_tran_init_pkt(struct scsi_address *, register 1975 struct scsi_pkt *, struct buf *, int, int, int, int, 1976 int (*)(), caddr_t); 1977 int mrsas_tbolt_tran_start(struct scsi_address *, 1978 register struct scsi_pkt *); 1979 uint32_t tbolt_read_fw_status_reg(struct mrsas_instance *); 1980 void tbolt_issue_cmd(struct mrsas_cmd *, struct mrsas_instance *); 1981 int tbolt_issue_cmd_in_poll_mode(struct mrsas_instance *, 1982 struct mrsas_cmd *); 1983 int tbolt_issue_cmd_in_sync_mode(struct mrsas_instance *, 1984 struct mrsas_cmd *); 1985 void tbolt_enable_intr(struct mrsas_instance *); 1986 void tbolt_disable_intr(struct mrsas_instance *); 1987 int tbolt_intr_ack(struct mrsas_instance *); 1988 uint_t mr_sas_tbolt_process_outstanding_cmd(struct mrsas_instance *); 1989 uint_t tbolt_softintr(); 1990 int mrsas_tbolt_dma(struct mrsas_instance *, uint32_t, int, int (*)()); 1991 int mrsas_check_dma_handle(ddi_dma_handle_t handle); 1992 int mrsas_check_acc_handle(ddi_acc_handle_t handle); 1993 int mrsas_dma_alloc(struct mrsas_instance *, struct scsi_pkt *, 1994 struct buf *, int, int (*)()); 1995 int mrsas_dma_move(struct mrsas_instance *, 1996 struct scsi_pkt *, struct buf *); 1997 int mrsas_alloc_dma_obj(struct mrsas_instance *, dma_obj_t *, 1998 uchar_t); 1999 void mr_sas_tbolt_build_mfi_cmd(struct mrsas_instance *, struct mrsas_cmd *); 2000 int mrsas_dma_alloc_dmd(struct mrsas_instance *, dma_obj_t *); 2001 void tbolt_complete_cmd_in_sync_mode(struct mrsas_instance *, 2002 struct mrsas_cmd *); 2003 int alloc_req_rep_desc(struct mrsas_instance *); 2004 int mrsas_mode_sense_build(struct scsi_pkt *); 2005 void push_pending_mfi_pkt(struct mrsas_instance *, 2006 struct mrsas_cmd *); 2007 int mrsas_issue_pending_cmds(struct mrsas_instance *); 2008 int mrsas_print_pending_cmds(struct mrsas_instance *); 2009 int mrsas_complete_pending_cmds(struct mrsas_instance *); 2010 2011 int create_mfi_frame_pool(struct mrsas_instance *); 2012 void destroy_mfi_frame_pool(struct mrsas_instance *); 2013 int create_mfi_mpi_frame_pool(struct mrsas_instance *); 2014 void destroy_mfi_mpi_frame_pool(struct mrsas_instance *); 2015 int create_mpi2_frame_pool(struct mrsas_instance *); 2016 void destroy_mpi2_frame_pool(struct mrsas_instance *); 2017 int mrsas_free_dma_obj(struct mrsas_instance *, dma_obj_t); 2018 void mrsas_tbolt_free_additional_dma_buffer(struct mrsas_instance *); 2019 void free_req_desc_pool(struct mrsas_instance *); 2020 void free_space_for_mpi2(struct mrsas_instance *); 2021 void mrsas_dump_reply_desc(struct mrsas_instance *); 2022 void tbolt_complete_cmd(struct mrsas_instance *, struct mrsas_cmd *); 2023 void display_scsi_inquiry(caddr_t); 2024 void service_mfi_aen(struct mrsas_instance *, struct mrsas_cmd *); 2025 int mrsas_mode_sense_build(struct scsi_pkt *); 2026 int mrsas_tbolt_get_ld_map_info(struct mrsas_instance *); 2027 struct mrsas_cmd *mrsas_tbolt_build_poll_cmd(struct mrsas_instance *, 2028 struct scsi_address *, struct scsi_pkt *, uchar_t *); 2029 int mrsas_tbolt_reset_ppc(struct mrsas_instance *instance); 2030 void mrsas_tbolt_kill_adapter(struct mrsas_instance *instance); 2031 int abort_syncmap_cmd(struct mrsas_instance *, struct mrsas_cmd *); 2032 void mrsas_tbolt_prepare_cdb(struct mrsas_instance *instance, U8 cdb[], 2033 struct IO_REQUEST_INFO *, Mpi2RaidSCSIIORequest_t *, U32); 2034 2035 2036 int mrsas_init_adapter_ppc(struct mrsas_instance *instance); 2037 int mrsas_init_adapter_tbolt(struct mrsas_instance *instance); 2038 int mrsas_init_adapter(struct mrsas_instance *instance); 2039 2040 int mrsas_alloc_cmd_pool(struct mrsas_instance *instance); 2041 void mrsas_free_cmd_pool(struct mrsas_instance *instance); 2042 2043 void mrsas_print_cmd_details(struct mrsas_instance *, struct mrsas_cmd *, int); 2044 struct mrsas_cmd *get_raid_msg_pkt(struct mrsas_instance *); 2045 2046 int mfi_state_transition_to_ready(struct mrsas_instance *); 2047 2048 2049 /* FMA functions. */ 2050 int mrsas_common_check(struct mrsas_instance *, struct mrsas_cmd *); 2051 void mrsas_fm_ereport(struct mrsas_instance *, char *); 2052 2053 2054 #ifdef __cplusplus 2055 } 2056 #endif 2057 2058 #endif /* _MR_SAS_H_ */ 2059