1 /* 2 * This file and its contents are supplied under the terms of the 3 * Common Development and Distribution License ("CDDL"), version 1.0. 4 * You may only use this file in accordance with the terms of version 5 * 1.0 of the CDDL. 6 * 7 * A full copy of the text of the CDDL should have accompanied this 8 * source. A copy of the CDDL is also available via the Internet at 9 * http://www.illumos.org/license/CDDL. 10 */ 11 12 /* 13 * Copyright 2016 Nexenta Systems, Inc. All rights reserved. 14 * Copyright 2016 Tegile Systems, Inc. All rights reserved. 15 * Copyright (c) 2016 The MathWorks, Inc. All rights reserved. 16 * Copyright 2017 Joyent, Inc. 17 */ 18 19 /* 20 * blkdev driver for NVMe compliant storage devices 21 * 22 * This driver was written to conform to version 1.2.1 of the NVMe 23 * specification. It may work with newer versions, but that is completely 24 * untested and disabled by default. 25 * 26 * The driver has only been tested on x86 systems and will not work on big- 27 * endian systems without changes to the code accessing registers and data 28 * structures used by the hardware. 29 * 30 * 31 * Interrupt Usage: 32 * 33 * The driver will use a single interrupt while configuring the device as the 34 * specification requires, but contrary to the specification it will try to use 35 * a single-message MSI(-X) or FIXED interrupt. Later in the attach process it 36 * will switch to multiple-message MSI(-X) if supported. The driver wants to 37 * have one interrupt vector per CPU, but it will work correctly if less are 38 * available. Interrupts can be shared by queues, the interrupt handler will 39 * iterate through the I/O queue array by steps of n_intr_cnt. Usually only 40 * the admin queue will share an interrupt with one I/O queue. The interrupt 41 * handler will retrieve completed commands from all queues sharing an interrupt 42 * vector and will post them to a taskq for completion processing. 43 * 44 * 45 * Command Processing: 46 * 47 * NVMe devices can have up to 65535 I/O queue pairs, with each queue holding up 48 * to 65536 I/O commands. The driver will configure one I/O queue pair per 49 * available interrupt vector, with the queue length usually much smaller than 50 * the maximum of 65536. If the hardware doesn't provide enough queues, fewer 51 * interrupt vectors will be used. 52 * 53 * Additionally the hardware provides a single special admin queue pair that can 54 * hold up to 4096 admin commands. 55 * 56 * From the hardware perspective both queues of a queue pair are independent, 57 * but they share some driver state: the command array (holding pointers to 58 * commands currently being processed by the hardware) and the active command 59 * counter. Access to a queue pair and the shared state is protected by 60 * nq_mutex. 61 * 62 * When a command is submitted to a queue pair the active command counter is 63 * incremented and a pointer to the command is stored in the command array. The 64 * array index is used as command identifier (CID) in the submission queue 65 * entry. Some commands may take a very long time to complete, and if the queue 66 * wraps around in that time a submission may find the next array slot to still 67 * be used by a long-running command. In this case the array is sequentially 68 * searched for the next free slot. The length of the command array is the same 69 * as the configured queue length. Queue overrun is prevented by the semaphore, 70 * so a command submission may block if the queue is full. 71 * 72 * 73 * Polled I/O Support: 74 * 75 * For kernel core dump support the driver can do polled I/O. As interrupts are 76 * turned off while dumping the driver will just submit a command in the regular 77 * way, and then repeatedly attempt a command retrieval until it gets the 78 * command back. 79 * 80 * 81 * Namespace Support: 82 * 83 * NVMe devices can have multiple namespaces, each being a independent data 84 * store. The driver supports multiple namespaces and creates a blkdev interface 85 * for each namespace found. Namespaces can have various attributes to support 86 * thin provisioning and protection information. This driver does not support 87 * any of this and ignores namespaces that have these attributes. 88 * 89 * As of NVMe 1.1 namespaces can have an 64bit Extended Unique Identifier 90 * (EUI64). This driver uses the EUI64 if present to generate the devid and 91 * passes it to blkdev to use it in the device node names. As this is currently 92 * untested namespaces with EUI64 are ignored by default. 93 * 94 * We currently support only (2 << NVME_MINOR_INST_SHIFT) - 2 namespaces in a 95 * single controller. This is an artificial limit imposed by the driver to be 96 * able to address a reasonable number of controllers and namespaces using a 97 * 32bit minor node number. 98 * 99 * 100 * Minor nodes: 101 * 102 * For each NVMe device the driver exposes one minor node for the controller and 103 * one minor node for each namespace. The only operations supported by those 104 * minor nodes are open(9E), close(9E), and ioctl(9E). This serves as the 105 * interface for the nvmeadm(1M) utility. 106 * 107 * 108 * Blkdev Interface: 109 * 110 * This driver uses blkdev to do all the heavy lifting involved with presenting 111 * a disk device to the system. As a result, the processing of I/O requests is 112 * relatively simple as blkdev takes care of partitioning, boundary checks, DMA 113 * setup, and splitting of transfers into manageable chunks. 114 * 115 * I/O requests coming in from blkdev are turned into NVM commands and posted to 116 * an I/O queue. The queue is selected by taking the CPU id modulo the number of 117 * queues. There is currently no timeout handling of I/O commands. 118 * 119 * Blkdev also supports querying device/media information and generating a 120 * devid. The driver reports the best block size as determined by the namespace 121 * format back to blkdev as physical block size to support partition and block 122 * alignment. The devid is either based on the namespace EUI64, if present, or 123 * composed using the device vendor ID, model number, serial number, and the 124 * namespace ID. 125 * 126 * 127 * Error Handling: 128 * 129 * Error handling is currently limited to detecting fatal hardware errors, 130 * either by asynchronous events, or synchronously through command status or 131 * admin command timeouts. In case of severe errors the device is fenced off, 132 * all further requests will return EIO. FMA is then called to fault the device. 133 * 134 * The hardware has a limit for outstanding asynchronous event requests. Before 135 * this limit is known the driver assumes it is at least 1 and posts a single 136 * asynchronous request. Later when the limit is known more asynchronous event 137 * requests are posted to allow quicker reception of error information. When an 138 * asynchronous event is posted by the hardware the driver will parse the error 139 * status fields and log information or fault the device, depending on the 140 * severity of the asynchronous event. The asynchronous event request is then 141 * reused and posted to the admin queue again. 142 * 143 * On command completion the command status is checked for errors. In case of 144 * errors indicating a driver bug the driver panics. Almost all other error 145 * status values just cause EIO to be returned. 146 * 147 * Command timeouts are currently detected for all admin commands except 148 * asynchronous event requests. If a command times out and the hardware appears 149 * to be healthy the driver attempts to abort the command. The original command 150 * timeout is also applied to the abort command. If the abort times out too the 151 * driver assumes the device to be dead, fences it off, and calls FMA to retire 152 * it. In all other cases the aborted command should return immediately with a 153 * status indicating it was aborted, and the driver will wait indefinitely for 154 * that to happen. No timeout handling of normal I/O commands is presently done. 155 * 156 * Any command that times out due to the controller dropping dead will be put on 157 * nvme_lost_cmds list if it references DMA memory. This will prevent the DMA 158 * memory being reused by the system and later be written to by a "dead" NVMe 159 * controller. 160 * 161 * 162 * Locking: 163 * 164 * Each queue pair has its own nq_mutex, which must be held when accessing the 165 * associated queue registers or the shared state of the queue pair. Callers of 166 * nvme_unqueue_cmd() must make sure that nq_mutex is held, while 167 * nvme_submit_{admin,io}_cmd() and nvme_retrieve_cmd() take care of this 168 * themselves. 169 * 170 * Each command also has its own nc_mutex, which is associated with the 171 * condition variable nc_cv. It is only used on admin commands which are run 172 * synchronously. In that case it must be held across calls to 173 * nvme_submit_{admin,io}_cmd() and nvme_wait_cmd(), which is taken care of by 174 * nvme_admin_cmd(). It must also be held whenever the completion state of the 175 * command is changed or while a admin command timeout is handled. 176 * 177 * If both nc_mutex and nq_mutex must be held, nc_mutex must be acquired first. 178 * More than one nc_mutex may only be held when aborting commands. In this case, 179 * the nc_mutex of the command to be aborted must be held across the call to 180 * nvme_abort_cmd() to prevent the command from completing while the abort is in 181 * progress. 182 * 183 * Each minor node has its own nm_mutex, which protects the open count nm_ocnt 184 * and exclusive-open flag nm_oexcl. 185 * 186 * 187 * Quiesce / Fast Reboot: 188 * 189 * The driver currently does not support fast reboot. A quiesce(9E) entry point 190 * is still provided which is used to send a shutdown notification to the 191 * device. 192 * 193 * 194 * Driver Configuration: 195 * 196 * The following driver properties can be changed to control some aspects of the 197 * drivers operation: 198 * - strict-version: can be set to 0 to allow devices conforming to newer 199 * versions or namespaces with EUI64 to be used 200 * - ignore-unknown-vendor-status: can be set to 1 to not handle any vendor 201 * specific command status as a fatal error leading device faulting 202 * - admin-queue-len: the maximum length of the admin queue (16-4096) 203 * - io-queue-len: the maximum length of the I/O queues (16-65536) 204 * - async-event-limit: the maximum number of asynchronous event requests to be 205 * posted by the driver 206 * - volatile-write-cache-enable: can be set to 0 to disable the volatile write 207 * cache 208 * - min-phys-block-size: the minimum physical block size to report to blkdev, 209 * which is among other things the basis for ZFS vdev ashift 210 * 211 * 212 * TODO: 213 * - figure out sane default for I/O queue depth reported to blkdev 214 * - FMA handling of media errors 215 * - support for devices supporting very large I/O requests using chained PRPs 216 * - support for configuring hardware parameters like interrupt coalescing 217 * - support for media formatting and hard partitioning into namespaces 218 * - support for big-endian systems 219 * - support for fast reboot 220 * - support for firmware updates 221 * - support for NVMe Subsystem Reset (1.1) 222 * - support for Scatter/Gather lists (1.1) 223 * - support for Reservations (1.1) 224 * - support for power management 225 */ 226 227 #include <sys/byteorder.h> 228 #ifdef _BIG_ENDIAN 229 #error nvme driver needs porting for big-endian platforms 230 #endif 231 232 #include <sys/modctl.h> 233 #include <sys/conf.h> 234 #include <sys/devops.h> 235 #include <sys/ddi.h> 236 #include <sys/sunddi.h> 237 #include <sys/sunndi.h> 238 #include <sys/bitmap.h> 239 #include <sys/sysmacros.h> 240 #include <sys/param.h> 241 #include <sys/varargs.h> 242 #include <sys/cpuvar.h> 243 #include <sys/disp.h> 244 #include <sys/blkdev.h> 245 #include <sys/atomic.h> 246 #include <sys/archsystm.h> 247 #include <sys/sata/sata_hba.h> 248 #include <sys/stat.h> 249 #include <sys/policy.h> 250 #include <sys/list.h> 251 252 #include <sys/nvme.h> 253 254 #ifdef __x86 255 #include <sys/x86_archext.h> 256 #endif 257 258 #include "nvme_reg.h" 259 #include "nvme_var.h" 260 261 262 /* NVMe spec version supported */ 263 static const int nvme_version_major = 1; 264 static const int nvme_version_minor = 2; 265 266 /* tunable for admin command timeout in seconds, default is 1s */ 267 int nvme_admin_cmd_timeout = 1; 268 269 /* tunable for FORMAT NVM command timeout in seconds, default is 600s */ 270 int nvme_format_cmd_timeout = 600; 271 272 static int nvme_attach(dev_info_t *, ddi_attach_cmd_t); 273 static int nvme_detach(dev_info_t *, ddi_detach_cmd_t); 274 static int nvme_quiesce(dev_info_t *); 275 static int nvme_fm_errcb(dev_info_t *, ddi_fm_error_t *, const void *); 276 static int nvme_setup_interrupts(nvme_t *, int, int); 277 static void nvme_release_interrupts(nvme_t *); 278 static uint_t nvme_intr(caddr_t, caddr_t); 279 280 static void nvme_shutdown(nvme_t *, int, boolean_t); 281 static boolean_t nvme_reset(nvme_t *, boolean_t); 282 static int nvme_init(nvme_t *); 283 static nvme_cmd_t *nvme_alloc_cmd(nvme_t *, int); 284 static void nvme_free_cmd(nvme_cmd_t *); 285 static nvme_cmd_t *nvme_create_nvm_cmd(nvme_namespace_t *, uint8_t, 286 bd_xfer_t *); 287 static void nvme_admin_cmd(nvme_cmd_t *, int); 288 static void nvme_submit_admin_cmd(nvme_qpair_t *, nvme_cmd_t *); 289 static int nvme_submit_io_cmd(nvme_qpair_t *, nvme_cmd_t *); 290 static void nvme_submit_cmd_common(nvme_qpair_t *, nvme_cmd_t *); 291 static nvme_cmd_t *nvme_unqueue_cmd(nvme_t *, nvme_qpair_t *, int); 292 static nvme_cmd_t *nvme_retrieve_cmd(nvme_t *, nvme_qpair_t *); 293 static void nvme_wait_cmd(nvme_cmd_t *, uint_t); 294 static void nvme_wakeup_cmd(void *); 295 static void nvme_async_event_task(void *); 296 297 static int nvme_check_unknown_cmd_status(nvme_cmd_t *); 298 static int nvme_check_vendor_cmd_status(nvme_cmd_t *); 299 static int nvme_check_integrity_cmd_status(nvme_cmd_t *); 300 static int nvme_check_specific_cmd_status(nvme_cmd_t *); 301 static int nvme_check_generic_cmd_status(nvme_cmd_t *); 302 static inline int nvme_check_cmd_status(nvme_cmd_t *); 303 304 static int nvme_abort_cmd(nvme_cmd_t *, uint_t); 305 static void nvme_async_event(nvme_t *); 306 static int nvme_format_nvm(nvme_t *, uint32_t, uint8_t, boolean_t, uint8_t, 307 boolean_t, uint8_t); 308 static int nvme_get_logpage(nvme_t *, void **, size_t *, uint8_t, ...); 309 static int nvme_identify(nvme_t *, uint32_t, void **); 310 static int nvme_set_features(nvme_t *, uint32_t, uint8_t, uint32_t, 311 uint32_t *); 312 static int nvme_get_features(nvme_t *, uint32_t, uint8_t, uint32_t *, 313 void **, size_t *); 314 static int nvme_write_cache_set(nvme_t *, boolean_t); 315 static int nvme_set_nqueues(nvme_t *, uint16_t *); 316 317 static void nvme_free_dma(nvme_dma_t *); 318 static int nvme_zalloc_dma(nvme_t *, size_t, uint_t, ddi_dma_attr_t *, 319 nvme_dma_t **); 320 static int nvme_zalloc_queue_dma(nvme_t *, uint32_t, uint16_t, uint_t, 321 nvme_dma_t **); 322 static void nvme_free_qpair(nvme_qpair_t *); 323 static int nvme_alloc_qpair(nvme_t *, uint32_t, nvme_qpair_t **, int); 324 static int nvme_create_io_qpair(nvme_t *, nvme_qpair_t *, uint16_t); 325 326 static inline void nvme_put64(nvme_t *, uintptr_t, uint64_t); 327 static inline void nvme_put32(nvme_t *, uintptr_t, uint32_t); 328 static inline uint64_t nvme_get64(nvme_t *, uintptr_t); 329 static inline uint32_t nvme_get32(nvme_t *, uintptr_t); 330 331 static boolean_t nvme_check_regs_hdl(nvme_t *); 332 static boolean_t nvme_check_dma_hdl(nvme_dma_t *); 333 334 static int nvme_fill_prp(nvme_cmd_t *, bd_xfer_t *); 335 336 static void nvme_bd_xfer_done(void *); 337 static void nvme_bd_driveinfo(void *, bd_drive_t *); 338 static int nvme_bd_mediainfo(void *, bd_media_t *); 339 static int nvme_bd_cmd(nvme_namespace_t *, bd_xfer_t *, uint8_t); 340 static int nvme_bd_read(void *, bd_xfer_t *); 341 static int nvme_bd_write(void *, bd_xfer_t *); 342 static int nvme_bd_sync(void *, bd_xfer_t *); 343 static int nvme_bd_devid(void *, dev_info_t *, ddi_devid_t *); 344 345 static int nvme_prp_dma_constructor(void *, void *, int); 346 static void nvme_prp_dma_destructor(void *, void *); 347 348 static void nvme_prepare_devid(nvme_t *, uint32_t); 349 350 static int nvme_open(dev_t *, int, int, cred_t *); 351 static int nvme_close(dev_t, int, int, cred_t *); 352 static int nvme_ioctl(dev_t, int, intptr_t, int, cred_t *, int *); 353 354 #define NVME_MINOR_INST_SHIFT 9 355 #define NVME_MINOR(inst, nsid) (((inst) << NVME_MINOR_INST_SHIFT) | (nsid)) 356 #define NVME_MINOR_INST(minor) ((minor) >> NVME_MINOR_INST_SHIFT) 357 #define NVME_MINOR_NSID(minor) ((minor) & ((1 << NVME_MINOR_INST_SHIFT) - 1)) 358 #define NVME_MINOR_MAX (NVME_MINOR(1, 0) - 2) 359 360 static void *nvme_state; 361 static kmem_cache_t *nvme_cmd_cache; 362 363 /* 364 * DMA attributes for queue DMA memory 365 * 366 * Queue DMA memory must be page aligned. The maximum length of a queue is 367 * 65536 entries, and an entry can be 64 bytes long. 368 */ 369 static ddi_dma_attr_t nvme_queue_dma_attr = { 370 .dma_attr_version = DMA_ATTR_V0, 371 .dma_attr_addr_lo = 0, 372 .dma_attr_addr_hi = 0xffffffffffffffffULL, 373 .dma_attr_count_max = (UINT16_MAX + 1) * sizeof (nvme_sqe_t) - 1, 374 .dma_attr_align = 0x1000, 375 .dma_attr_burstsizes = 0x7ff, 376 .dma_attr_minxfer = 0x1000, 377 .dma_attr_maxxfer = (UINT16_MAX + 1) * sizeof (nvme_sqe_t), 378 .dma_attr_seg = 0xffffffffffffffffULL, 379 .dma_attr_sgllen = 1, 380 .dma_attr_granular = 1, 381 .dma_attr_flags = 0, 382 }; 383 384 /* 385 * DMA attributes for transfers using Physical Region Page (PRP) entries 386 * 387 * A PRP entry describes one page of DMA memory using the page size specified 388 * in the controller configuration's memory page size register (CC.MPS). It uses 389 * a 64bit base address aligned to this page size. There is no limitation on 390 * chaining PRPs together for arbitrarily large DMA transfers. 391 */ 392 static ddi_dma_attr_t nvme_prp_dma_attr = { 393 .dma_attr_version = DMA_ATTR_V0, 394 .dma_attr_addr_lo = 0, 395 .dma_attr_addr_hi = 0xffffffffffffffffULL, 396 .dma_attr_count_max = 0xfff, 397 .dma_attr_align = 0x1000, 398 .dma_attr_burstsizes = 0x7ff, 399 .dma_attr_minxfer = 0x1000, 400 .dma_attr_maxxfer = 0x1000, 401 .dma_attr_seg = 0xfff, 402 .dma_attr_sgllen = -1, 403 .dma_attr_granular = 1, 404 .dma_attr_flags = 0, 405 }; 406 407 /* 408 * DMA attributes for transfers using scatter/gather lists 409 * 410 * A SGL entry describes a chunk of DMA memory using a 64bit base address and a 411 * 32bit length field. SGL Segment and SGL Last Segment entries require the 412 * length to be a multiple of 16 bytes. 413 */ 414 static ddi_dma_attr_t nvme_sgl_dma_attr = { 415 .dma_attr_version = DMA_ATTR_V0, 416 .dma_attr_addr_lo = 0, 417 .dma_attr_addr_hi = 0xffffffffffffffffULL, 418 .dma_attr_count_max = 0xffffffffUL, 419 .dma_attr_align = 1, 420 .dma_attr_burstsizes = 0x7ff, 421 .dma_attr_minxfer = 0x10, 422 .dma_attr_maxxfer = 0xfffffffffULL, 423 .dma_attr_seg = 0xffffffffffffffffULL, 424 .dma_attr_sgllen = -1, 425 .dma_attr_granular = 0x10, 426 .dma_attr_flags = 0 427 }; 428 429 static ddi_device_acc_attr_t nvme_reg_acc_attr = { 430 .devacc_attr_version = DDI_DEVICE_ATTR_V0, 431 .devacc_attr_endian_flags = DDI_STRUCTURE_LE_ACC, 432 .devacc_attr_dataorder = DDI_STRICTORDER_ACC 433 }; 434 435 static struct cb_ops nvme_cb_ops = { 436 .cb_open = nvme_open, 437 .cb_close = nvme_close, 438 .cb_strategy = nodev, 439 .cb_print = nodev, 440 .cb_dump = nodev, 441 .cb_read = nodev, 442 .cb_write = nodev, 443 .cb_ioctl = nvme_ioctl, 444 .cb_devmap = nodev, 445 .cb_mmap = nodev, 446 .cb_segmap = nodev, 447 .cb_chpoll = nochpoll, 448 .cb_prop_op = ddi_prop_op, 449 .cb_str = 0, 450 .cb_flag = D_NEW | D_MP, 451 .cb_rev = CB_REV, 452 .cb_aread = nodev, 453 .cb_awrite = nodev 454 }; 455 456 static struct dev_ops nvme_dev_ops = { 457 .devo_rev = DEVO_REV, 458 .devo_refcnt = 0, 459 .devo_getinfo = ddi_no_info, 460 .devo_identify = nulldev, 461 .devo_probe = nulldev, 462 .devo_attach = nvme_attach, 463 .devo_detach = nvme_detach, 464 .devo_reset = nodev, 465 .devo_cb_ops = &nvme_cb_ops, 466 .devo_bus_ops = NULL, 467 .devo_power = NULL, 468 .devo_quiesce = nvme_quiesce, 469 }; 470 471 static struct modldrv nvme_modldrv = { 472 .drv_modops = &mod_driverops, 473 .drv_linkinfo = "NVMe v1.1b", 474 .drv_dev_ops = &nvme_dev_ops 475 }; 476 477 static struct modlinkage nvme_modlinkage = { 478 .ml_rev = MODREV_1, 479 .ml_linkage = { &nvme_modldrv, NULL } 480 }; 481 482 static bd_ops_t nvme_bd_ops = { 483 .o_version = BD_OPS_VERSION_0, 484 .o_drive_info = nvme_bd_driveinfo, 485 .o_media_info = nvme_bd_mediainfo, 486 .o_devid_init = nvme_bd_devid, 487 .o_sync_cache = nvme_bd_sync, 488 .o_read = nvme_bd_read, 489 .o_write = nvme_bd_write, 490 }; 491 492 /* 493 * This list will hold commands that have timed out and couldn't be aborted. 494 * As we don't know what the hardware may still do with the DMA memory we can't 495 * free them, so we'll keep them forever on this list where we can easily look 496 * at them with mdb. 497 */ 498 static struct list nvme_lost_cmds; 499 static kmutex_t nvme_lc_mutex; 500 501 int 502 _init(void) 503 { 504 int error; 505 506 error = ddi_soft_state_init(&nvme_state, sizeof (nvme_t), 1); 507 if (error != DDI_SUCCESS) 508 return (error); 509 510 nvme_cmd_cache = kmem_cache_create("nvme_cmd_cache", 511 sizeof (nvme_cmd_t), 64, NULL, NULL, NULL, NULL, NULL, 0); 512 513 mutex_init(&nvme_lc_mutex, NULL, MUTEX_DRIVER, NULL); 514 list_create(&nvme_lost_cmds, sizeof (nvme_cmd_t), 515 offsetof(nvme_cmd_t, nc_list)); 516 517 bd_mod_init(&nvme_dev_ops); 518 519 error = mod_install(&nvme_modlinkage); 520 if (error != DDI_SUCCESS) { 521 ddi_soft_state_fini(&nvme_state); 522 mutex_destroy(&nvme_lc_mutex); 523 list_destroy(&nvme_lost_cmds); 524 bd_mod_fini(&nvme_dev_ops); 525 } 526 527 return (error); 528 } 529 530 int 531 _fini(void) 532 { 533 int error; 534 535 if (!list_is_empty(&nvme_lost_cmds)) 536 return (DDI_FAILURE); 537 538 error = mod_remove(&nvme_modlinkage); 539 if (error == DDI_SUCCESS) { 540 ddi_soft_state_fini(&nvme_state); 541 kmem_cache_destroy(nvme_cmd_cache); 542 mutex_destroy(&nvme_lc_mutex); 543 list_destroy(&nvme_lost_cmds); 544 bd_mod_fini(&nvme_dev_ops); 545 } 546 547 return (error); 548 } 549 550 int 551 _info(struct modinfo *modinfop) 552 { 553 return (mod_info(&nvme_modlinkage, modinfop)); 554 } 555 556 static inline void 557 nvme_put64(nvme_t *nvme, uintptr_t reg, uint64_t val) 558 { 559 ASSERT(((uintptr_t)(nvme->n_regs + reg) & 0x7) == 0); 560 561 /*LINTED: E_BAD_PTR_CAST_ALIGN*/ 562 ddi_put64(nvme->n_regh, (uint64_t *)(nvme->n_regs + reg), val); 563 } 564 565 static inline void 566 nvme_put32(nvme_t *nvme, uintptr_t reg, uint32_t val) 567 { 568 ASSERT(((uintptr_t)(nvme->n_regs + reg) & 0x3) == 0); 569 570 /*LINTED: E_BAD_PTR_CAST_ALIGN*/ 571 ddi_put32(nvme->n_regh, (uint32_t *)(nvme->n_regs + reg), val); 572 } 573 574 static inline uint64_t 575 nvme_get64(nvme_t *nvme, uintptr_t reg) 576 { 577 uint64_t val; 578 579 ASSERT(((uintptr_t)(nvme->n_regs + reg) & 0x7) == 0); 580 581 /*LINTED: E_BAD_PTR_CAST_ALIGN*/ 582 val = ddi_get64(nvme->n_regh, (uint64_t *)(nvme->n_regs + reg)); 583 584 return (val); 585 } 586 587 static inline uint32_t 588 nvme_get32(nvme_t *nvme, uintptr_t reg) 589 { 590 uint32_t val; 591 592 ASSERT(((uintptr_t)(nvme->n_regs + reg) & 0x3) == 0); 593 594 /*LINTED: E_BAD_PTR_CAST_ALIGN*/ 595 val = ddi_get32(nvme->n_regh, (uint32_t *)(nvme->n_regs + reg)); 596 597 return (val); 598 } 599 600 static boolean_t 601 nvme_check_regs_hdl(nvme_t *nvme) 602 { 603 ddi_fm_error_t error; 604 605 ddi_fm_acc_err_get(nvme->n_regh, &error, DDI_FME_VERSION); 606 607 if (error.fme_status != DDI_FM_OK) 608 return (B_TRUE); 609 610 return (B_FALSE); 611 } 612 613 static boolean_t 614 nvme_check_dma_hdl(nvme_dma_t *dma) 615 { 616 ddi_fm_error_t error; 617 618 if (dma == NULL) 619 return (B_FALSE); 620 621 ddi_fm_dma_err_get(dma->nd_dmah, &error, DDI_FME_VERSION); 622 623 if (error.fme_status != DDI_FM_OK) 624 return (B_TRUE); 625 626 return (B_FALSE); 627 } 628 629 static void 630 nvme_free_dma_common(nvme_dma_t *dma) 631 { 632 if (dma->nd_dmah != NULL) 633 (void) ddi_dma_unbind_handle(dma->nd_dmah); 634 if (dma->nd_acch != NULL) 635 ddi_dma_mem_free(&dma->nd_acch); 636 if (dma->nd_dmah != NULL) 637 ddi_dma_free_handle(&dma->nd_dmah); 638 } 639 640 static void 641 nvme_free_dma(nvme_dma_t *dma) 642 { 643 nvme_free_dma_common(dma); 644 kmem_free(dma, sizeof (*dma)); 645 } 646 647 /* ARGSUSED */ 648 static void 649 nvme_prp_dma_destructor(void *buf, void *private) 650 { 651 nvme_dma_t *dma = (nvme_dma_t *)buf; 652 653 nvme_free_dma_common(dma); 654 } 655 656 static int 657 nvme_alloc_dma_common(nvme_t *nvme, nvme_dma_t *dma, 658 size_t len, uint_t flags, ddi_dma_attr_t *dma_attr) 659 { 660 if (ddi_dma_alloc_handle(nvme->n_dip, dma_attr, DDI_DMA_SLEEP, NULL, 661 &dma->nd_dmah) != DDI_SUCCESS) { 662 /* 663 * Due to DDI_DMA_SLEEP this can't be DDI_DMA_NORESOURCES, and 664 * the only other possible error is DDI_DMA_BADATTR which 665 * indicates a driver bug which should cause a panic. 666 */ 667 dev_err(nvme->n_dip, CE_PANIC, 668 "!failed to get DMA handle, check DMA attributes"); 669 return (DDI_FAILURE); 670 } 671 672 /* 673 * ddi_dma_mem_alloc() can only fail when DDI_DMA_NOSLEEP is specified 674 * or the flags are conflicting, which isn't the case here. 675 */ 676 (void) ddi_dma_mem_alloc(dma->nd_dmah, len, &nvme->n_reg_acc_attr, 677 DDI_DMA_CONSISTENT, DDI_DMA_SLEEP, NULL, &dma->nd_memp, 678 &dma->nd_len, &dma->nd_acch); 679 680 if (ddi_dma_addr_bind_handle(dma->nd_dmah, NULL, dma->nd_memp, 681 dma->nd_len, flags | DDI_DMA_CONSISTENT, DDI_DMA_SLEEP, NULL, 682 &dma->nd_cookie, &dma->nd_ncookie) != DDI_DMA_MAPPED) { 683 dev_err(nvme->n_dip, CE_WARN, 684 "!failed to bind DMA memory"); 685 atomic_inc_32(&nvme->n_dma_bind_err); 686 nvme_free_dma_common(dma); 687 return (DDI_FAILURE); 688 } 689 690 return (DDI_SUCCESS); 691 } 692 693 static int 694 nvme_zalloc_dma(nvme_t *nvme, size_t len, uint_t flags, 695 ddi_dma_attr_t *dma_attr, nvme_dma_t **ret) 696 { 697 nvme_dma_t *dma = kmem_zalloc(sizeof (nvme_dma_t), KM_SLEEP); 698 699 if (nvme_alloc_dma_common(nvme, dma, len, flags, dma_attr) != 700 DDI_SUCCESS) { 701 *ret = NULL; 702 kmem_free(dma, sizeof (nvme_dma_t)); 703 return (DDI_FAILURE); 704 } 705 706 bzero(dma->nd_memp, dma->nd_len); 707 708 *ret = dma; 709 return (DDI_SUCCESS); 710 } 711 712 /* ARGSUSED */ 713 static int 714 nvme_prp_dma_constructor(void *buf, void *private, int flags) 715 { 716 nvme_dma_t *dma = (nvme_dma_t *)buf; 717 nvme_t *nvme = (nvme_t *)private; 718 719 dma->nd_dmah = NULL; 720 dma->nd_acch = NULL; 721 722 if (nvme_alloc_dma_common(nvme, dma, nvme->n_pagesize, 723 DDI_DMA_READ, &nvme->n_prp_dma_attr) != DDI_SUCCESS) { 724 return (-1); 725 } 726 727 ASSERT(dma->nd_ncookie == 1); 728 729 dma->nd_cached = B_TRUE; 730 731 return (0); 732 } 733 734 static int 735 nvme_zalloc_queue_dma(nvme_t *nvme, uint32_t nentry, uint16_t qe_len, 736 uint_t flags, nvme_dma_t **dma) 737 { 738 uint32_t len = nentry * qe_len; 739 ddi_dma_attr_t q_dma_attr = nvme->n_queue_dma_attr; 740 741 len = roundup(len, nvme->n_pagesize); 742 743 q_dma_attr.dma_attr_minxfer = len; 744 745 if (nvme_zalloc_dma(nvme, len, flags, &q_dma_attr, dma) 746 != DDI_SUCCESS) { 747 dev_err(nvme->n_dip, CE_WARN, 748 "!failed to get DMA memory for queue"); 749 goto fail; 750 } 751 752 if ((*dma)->nd_ncookie != 1) { 753 dev_err(nvme->n_dip, CE_WARN, 754 "!got too many cookies for queue DMA"); 755 goto fail; 756 } 757 758 return (DDI_SUCCESS); 759 760 fail: 761 if (*dma) { 762 nvme_free_dma(*dma); 763 *dma = NULL; 764 } 765 766 return (DDI_FAILURE); 767 } 768 769 static void 770 nvme_free_qpair(nvme_qpair_t *qp) 771 { 772 int i; 773 774 mutex_destroy(&qp->nq_mutex); 775 sema_destroy(&qp->nq_sema); 776 777 if (qp->nq_sqdma != NULL) 778 nvme_free_dma(qp->nq_sqdma); 779 if (qp->nq_cqdma != NULL) 780 nvme_free_dma(qp->nq_cqdma); 781 782 if (qp->nq_active_cmds > 0) 783 for (i = 0; i != qp->nq_nentry; i++) 784 if (qp->nq_cmd[i] != NULL) 785 nvme_free_cmd(qp->nq_cmd[i]); 786 787 if (qp->nq_cmd != NULL) 788 kmem_free(qp->nq_cmd, sizeof (nvme_cmd_t *) * qp->nq_nentry); 789 790 kmem_free(qp, sizeof (nvme_qpair_t)); 791 } 792 793 static int 794 nvme_alloc_qpair(nvme_t *nvme, uint32_t nentry, nvme_qpair_t **nqp, 795 int idx) 796 { 797 nvme_qpair_t *qp = kmem_zalloc(sizeof (*qp), KM_SLEEP); 798 799 mutex_init(&qp->nq_mutex, NULL, MUTEX_DRIVER, 800 DDI_INTR_PRI(nvme->n_intr_pri)); 801 sema_init(&qp->nq_sema, nentry, NULL, SEMA_DRIVER, NULL); 802 803 if (nvme_zalloc_queue_dma(nvme, nentry, sizeof (nvme_sqe_t), 804 DDI_DMA_WRITE, &qp->nq_sqdma) != DDI_SUCCESS) 805 goto fail; 806 807 if (nvme_zalloc_queue_dma(nvme, nentry, sizeof (nvme_cqe_t), 808 DDI_DMA_READ, &qp->nq_cqdma) != DDI_SUCCESS) 809 goto fail; 810 811 qp->nq_sq = (nvme_sqe_t *)qp->nq_sqdma->nd_memp; 812 qp->nq_cq = (nvme_cqe_t *)qp->nq_cqdma->nd_memp; 813 qp->nq_nentry = nentry; 814 815 qp->nq_sqtdbl = NVME_REG_SQTDBL(nvme, idx); 816 qp->nq_cqhdbl = NVME_REG_CQHDBL(nvme, idx); 817 818 qp->nq_cmd = kmem_zalloc(sizeof (nvme_cmd_t *) * nentry, KM_SLEEP); 819 qp->nq_next_cmd = 0; 820 821 *nqp = qp; 822 return (DDI_SUCCESS); 823 824 fail: 825 nvme_free_qpair(qp); 826 *nqp = NULL; 827 828 return (DDI_FAILURE); 829 } 830 831 static nvme_cmd_t * 832 nvme_alloc_cmd(nvme_t *nvme, int kmflag) 833 { 834 nvme_cmd_t *cmd = kmem_cache_alloc(nvme_cmd_cache, kmflag); 835 836 if (cmd == NULL) 837 return (cmd); 838 839 bzero(cmd, sizeof (nvme_cmd_t)); 840 841 cmd->nc_nvme = nvme; 842 843 mutex_init(&cmd->nc_mutex, NULL, MUTEX_DRIVER, 844 DDI_INTR_PRI(nvme->n_intr_pri)); 845 cv_init(&cmd->nc_cv, NULL, CV_DRIVER, NULL); 846 847 return (cmd); 848 } 849 850 static void 851 nvme_free_cmd(nvme_cmd_t *cmd) 852 { 853 /* Don't free commands on the lost commands list. */ 854 if (list_link_active(&cmd->nc_list)) 855 return; 856 857 if (cmd->nc_dma) { 858 if (cmd->nc_dma->nd_cached) 859 kmem_cache_free(cmd->nc_nvme->n_prp_cache, 860 cmd->nc_dma); 861 else 862 nvme_free_dma(cmd->nc_dma); 863 cmd->nc_dma = NULL; 864 } 865 866 cv_destroy(&cmd->nc_cv); 867 mutex_destroy(&cmd->nc_mutex); 868 869 kmem_cache_free(nvme_cmd_cache, cmd); 870 } 871 872 static void 873 nvme_submit_admin_cmd(nvme_qpair_t *qp, nvme_cmd_t *cmd) 874 { 875 sema_p(&qp->nq_sema); 876 nvme_submit_cmd_common(qp, cmd); 877 } 878 879 static int 880 nvme_submit_io_cmd(nvme_qpair_t *qp, nvme_cmd_t *cmd) 881 { 882 if (sema_tryp(&qp->nq_sema) == 0) 883 return (EAGAIN); 884 885 nvme_submit_cmd_common(qp, cmd); 886 return (0); 887 } 888 889 static void 890 nvme_submit_cmd_common(nvme_qpair_t *qp, nvme_cmd_t *cmd) 891 { 892 nvme_reg_sqtdbl_t tail = { 0 }; 893 894 mutex_enter(&qp->nq_mutex); 895 cmd->nc_completed = B_FALSE; 896 897 /* 898 * Try to insert the cmd into the active cmd array at the nq_next_cmd 899 * slot. If the slot is already occupied advance to the next slot and 900 * try again. This can happen for long running commands like async event 901 * requests. 902 */ 903 while (qp->nq_cmd[qp->nq_next_cmd] != NULL) 904 qp->nq_next_cmd = (qp->nq_next_cmd + 1) % qp->nq_nentry; 905 qp->nq_cmd[qp->nq_next_cmd] = cmd; 906 907 qp->nq_active_cmds++; 908 909 cmd->nc_sqe.sqe_cid = qp->nq_next_cmd; 910 bcopy(&cmd->nc_sqe, &qp->nq_sq[qp->nq_sqtail], sizeof (nvme_sqe_t)); 911 (void) ddi_dma_sync(qp->nq_sqdma->nd_dmah, 912 sizeof (nvme_sqe_t) * qp->nq_sqtail, 913 sizeof (nvme_sqe_t), DDI_DMA_SYNC_FORDEV); 914 qp->nq_next_cmd = (qp->nq_next_cmd + 1) % qp->nq_nentry; 915 916 tail.b.sqtdbl_sqt = qp->nq_sqtail = (qp->nq_sqtail + 1) % qp->nq_nentry; 917 nvme_put32(cmd->nc_nvme, qp->nq_sqtdbl, tail.r); 918 919 mutex_exit(&qp->nq_mutex); 920 } 921 922 static nvme_cmd_t * 923 nvme_unqueue_cmd(nvme_t *nvme, nvme_qpair_t *qp, int cid) 924 { 925 nvme_cmd_t *cmd; 926 927 ASSERT(mutex_owned(&qp->nq_mutex)); 928 ASSERT3S(cid, <, qp->nq_nentry); 929 930 cmd = qp->nq_cmd[cid]; 931 qp->nq_cmd[cid] = NULL; 932 ASSERT3U(qp->nq_active_cmds, >, 0); 933 qp->nq_active_cmds--; 934 sema_v(&qp->nq_sema); 935 936 ASSERT3P(cmd, !=, NULL); 937 ASSERT3P(cmd->nc_nvme, ==, nvme); 938 ASSERT3S(cmd->nc_sqe.sqe_cid, ==, cid); 939 940 return (cmd); 941 } 942 943 static nvme_cmd_t * 944 nvme_retrieve_cmd(nvme_t *nvme, nvme_qpair_t *qp) 945 { 946 nvme_reg_cqhdbl_t head = { 0 }; 947 948 nvme_cqe_t *cqe; 949 nvme_cmd_t *cmd; 950 951 (void) ddi_dma_sync(qp->nq_cqdma->nd_dmah, 0, 952 sizeof (nvme_cqe_t) * qp->nq_nentry, DDI_DMA_SYNC_FORKERNEL); 953 954 mutex_enter(&qp->nq_mutex); 955 cqe = &qp->nq_cq[qp->nq_cqhead]; 956 957 /* Check phase tag of CQE. Hardware inverts it for new entries. */ 958 if (cqe->cqe_sf.sf_p == qp->nq_phase) { 959 mutex_exit(&qp->nq_mutex); 960 return (NULL); 961 } 962 963 ASSERT(nvme->n_ioq[cqe->cqe_sqid] == qp); 964 965 cmd = nvme_unqueue_cmd(nvme, qp, cqe->cqe_cid); 966 967 ASSERT(cmd->nc_sqid == cqe->cqe_sqid); 968 bcopy(cqe, &cmd->nc_cqe, sizeof (nvme_cqe_t)); 969 970 qp->nq_sqhead = cqe->cqe_sqhd; 971 972 head.b.cqhdbl_cqh = qp->nq_cqhead = (qp->nq_cqhead + 1) % qp->nq_nentry; 973 974 /* Toggle phase on wrap-around. */ 975 if (qp->nq_cqhead == 0) 976 qp->nq_phase = qp->nq_phase ? 0 : 1; 977 978 nvme_put32(cmd->nc_nvme, qp->nq_cqhdbl, head.r); 979 mutex_exit(&qp->nq_mutex); 980 981 return (cmd); 982 } 983 984 static int 985 nvme_check_unknown_cmd_status(nvme_cmd_t *cmd) 986 { 987 nvme_cqe_t *cqe = &cmd->nc_cqe; 988 989 dev_err(cmd->nc_nvme->n_dip, CE_WARN, 990 "!unknown command status received: opc = %x, sqid = %d, cid = %d, " 991 "sc = %x, sct = %x, dnr = %d, m = %d", cmd->nc_sqe.sqe_opc, 992 cqe->cqe_sqid, cqe->cqe_cid, cqe->cqe_sf.sf_sc, cqe->cqe_sf.sf_sct, 993 cqe->cqe_sf.sf_dnr, cqe->cqe_sf.sf_m); 994 995 if (cmd->nc_xfer != NULL) 996 bd_error(cmd->nc_xfer, BD_ERR_ILLRQ); 997 998 if (cmd->nc_nvme->n_strict_version) { 999 cmd->nc_nvme->n_dead = B_TRUE; 1000 ddi_fm_service_impact(cmd->nc_nvme->n_dip, DDI_SERVICE_LOST); 1001 } 1002 1003 return (EIO); 1004 } 1005 1006 static int 1007 nvme_check_vendor_cmd_status(nvme_cmd_t *cmd) 1008 { 1009 nvme_cqe_t *cqe = &cmd->nc_cqe; 1010 1011 dev_err(cmd->nc_nvme->n_dip, CE_WARN, 1012 "!unknown command status received: opc = %x, sqid = %d, cid = %d, " 1013 "sc = %x, sct = %x, dnr = %d, m = %d", cmd->nc_sqe.sqe_opc, 1014 cqe->cqe_sqid, cqe->cqe_cid, cqe->cqe_sf.sf_sc, cqe->cqe_sf.sf_sct, 1015 cqe->cqe_sf.sf_dnr, cqe->cqe_sf.sf_m); 1016 if (!cmd->nc_nvme->n_ignore_unknown_vendor_status) { 1017 cmd->nc_nvme->n_dead = B_TRUE; 1018 ddi_fm_service_impact(cmd->nc_nvme->n_dip, DDI_SERVICE_LOST); 1019 } 1020 1021 return (EIO); 1022 } 1023 1024 static int 1025 nvme_check_integrity_cmd_status(nvme_cmd_t *cmd) 1026 { 1027 nvme_cqe_t *cqe = &cmd->nc_cqe; 1028 1029 switch (cqe->cqe_sf.sf_sc) { 1030 case NVME_CQE_SC_INT_NVM_WRITE: 1031 /* write fail */ 1032 /* TODO: post ereport */ 1033 if (cmd->nc_xfer != NULL) 1034 bd_error(cmd->nc_xfer, BD_ERR_MEDIA); 1035 return (EIO); 1036 1037 case NVME_CQE_SC_INT_NVM_READ: 1038 /* read fail */ 1039 /* TODO: post ereport */ 1040 if (cmd->nc_xfer != NULL) 1041 bd_error(cmd->nc_xfer, BD_ERR_MEDIA); 1042 return (EIO); 1043 1044 default: 1045 return (nvme_check_unknown_cmd_status(cmd)); 1046 } 1047 } 1048 1049 static int 1050 nvme_check_generic_cmd_status(nvme_cmd_t *cmd) 1051 { 1052 nvme_cqe_t *cqe = &cmd->nc_cqe; 1053 1054 switch (cqe->cqe_sf.sf_sc) { 1055 case NVME_CQE_SC_GEN_SUCCESS: 1056 return (0); 1057 1058 /* 1059 * Errors indicating a bug in the driver should cause a panic. 1060 */ 1061 case NVME_CQE_SC_GEN_INV_OPC: 1062 /* Invalid Command Opcode */ 1063 dev_err(cmd->nc_nvme->n_dip, CE_PANIC, "programming error: " 1064 "invalid opcode in cmd %p", (void *)cmd); 1065 return (0); 1066 1067 case NVME_CQE_SC_GEN_INV_FLD: 1068 /* Invalid Field in Command */ 1069 if (!cmd->nc_dontpanic) 1070 dev_err(cmd->nc_nvme->n_dip, CE_PANIC, 1071 "programming error: invalid field in cmd %p", 1072 (void *)cmd); 1073 return (EIO); 1074 1075 case NVME_CQE_SC_GEN_ID_CNFL: 1076 /* Command ID Conflict */ 1077 dev_err(cmd->nc_nvme->n_dip, CE_PANIC, "programming error: " 1078 "cmd ID conflict in cmd %p", (void *)cmd); 1079 return (0); 1080 1081 case NVME_CQE_SC_GEN_INV_NS: 1082 /* Invalid Namespace or Format */ 1083 if (!cmd->nc_dontpanic) 1084 dev_err(cmd->nc_nvme->n_dip, CE_PANIC, 1085 "programming error: " "invalid NS/format in cmd %p", 1086 (void *)cmd); 1087 return (EINVAL); 1088 1089 case NVME_CQE_SC_GEN_NVM_LBA_RANGE: 1090 /* LBA Out Of Range */ 1091 dev_err(cmd->nc_nvme->n_dip, CE_PANIC, "programming error: " 1092 "LBA out of range in cmd %p", (void *)cmd); 1093 return (0); 1094 1095 /* 1096 * Non-fatal errors, handle gracefully. 1097 */ 1098 case NVME_CQE_SC_GEN_DATA_XFR_ERR: 1099 /* Data Transfer Error (DMA) */ 1100 /* TODO: post ereport */ 1101 atomic_inc_32(&cmd->nc_nvme->n_data_xfr_err); 1102 if (cmd->nc_xfer != NULL) 1103 bd_error(cmd->nc_xfer, BD_ERR_NTRDY); 1104 return (EIO); 1105 1106 case NVME_CQE_SC_GEN_INTERNAL_ERR: 1107 /* 1108 * Internal Error. The spec (v1.0, section 4.5.1.2) says 1109 * detailed error information is returned as async event, 1110 * so we pretty much ignore the error here and handle it 1111 * in the async event handler. 1112 */ 1113 atomic_inc_32(&cmd->nc_nvme->n_internal_err); 1114 if (cmd->nc_xfer != NULL) 1115 bd_error(cmd->nc_xfer, BD_ERR_NTRDY); 1116 return (EIO); 1117 1118 case NVME_CQE_SC_GEN_ABORT_REQUEST: 1119 /* 1120 * Command Abort Requested. This normally happens only when a 1121 * command times out. 1122 */ 1123 /* TODO: post ereport or change blkdev to handle this? */ 1124 atomic_inc_32(&cmd->nc_nvme->n_abort_rq_err); 1125 return (ECANCELED); 1126 1127 case NVME_CQE_SC_GEN_ABORT_PWRLOSS: 1128 /* Command Aborted due to Power Loss Notification */ 1129 ddi_fm_service_impact(cmd->nc_nvme->n_dip, DDI_SERVICE_LOST); 1130 cmd->nc_nvme->n_dead = B_TRUE; 1131 return (EIO); 1132 1133 case NVME_CQE_SC_GEN_ABORT_SQ_DEL: 1134 /* Command Aborted due to SQ Deletion */ 1135 atomic_inc_32(&cmd->nc_nvme->n_abort_sq_del); 1136 return (EIO); 1137 1138 case NVME_CQE_SC_GEN_NVM_CAP_EXC: 1139 /* Capacity Exceeded */ 1140 atomic_inc_32(&cmd->nc_nvme->n_nvm_cap_exc); 1141 if (cmd->nc_xfer != NULL) 1142 bd_error(cmd->nc_xfer, BD_ERR_MEDIA); 1143 return (EIO); 1144 1145 case NVME_CQE_SC_GEN_NVM_NS_NOTRDY: 1146 /* Namespace Not Ready */ 1147 atomic_inc_32(&cmd->nc_nvme->n_nvm_ns_notrdy); 1148 if (cmd->nc_xfer != NULL) 1149 bd_error(cmd->nc_xfer, BD_ERR_NTRDY); 1150 return (EIO); 1151 1152 default: 1153 return (nvme_check_unknown_cmd_status(cmd)); 1154 } 1155 } 1156 1157 static int 1158 nvme_check_specific_cmd_status(nvme_cmd_t *cmd) 1159 { 1160 nvme_cqe_t *cqe = &cmd->nc_cqe; 1161 1162 switch (cqe->cqe_sf.sf_sc) { 1163 case NVME_CQE_SC_SPC_INV_CQ: 1164 /* Completion Queue Invalid */ 1165 ASSERT(cmd->nc_sqe.sqe_opc == NVME_OPC_CREATE_SQUEUE); 1166 atomic_inc_32(&cmd->nc_nvme->n_inv_cq_err); 1167 return (EINVAL); 1168 1169 case NVME_CQE_SC_SPC_INV_QID: 1170 /* Invalid Queue Identifier */ 1171 ASSERT(cmd->nc_sqe.sqe_opc == NVME_OPC_CREATE_SQUEUE || 1172 cmd->nc_sqe.sqe_opc == NVME_OPC_DELETE_SQUEUE || 1173 cmd->nc_sqe.sqe_opc == NVME_OPC_CREATE_CQUEUE || 1174 cmd->nc_sqe.sqe_opc == NVME_OPC_DELETE_CQUEUE); 1175 atomic_inc_32(&cmd->nc_nvme->n_inv_qid_err); 1176 return (EINVAL); 1177 1178 case NVME_CQE_SC_SPC_MAX_QSZ_EXC: 1179 /* Max Queue Size Exceeded */ 1180 ASSERT(cmd->nc_sqe.sqe_opc == NVME_OPC_CREATE_SQUEUE || 1181 cmd->nc_sqe.sqe_opc == NVME_OPC_CREATE_CQUEUE); 1182 atomic_inc_32(&cmd->nc_nvme->n_max_qsz_exc); 1183 return (EINVAL); 1184 1185 case NVME_CQE_SC_SPC_ABRT_CMD_EXC: 1186 /* Abort Command Limit Exceeded */ 1187 ASSERT(cmd->nc_sqe.sqe_opc == NVME_OPC_ABORT); 1188 dev_err(cmd->nc_nvme->n_dip, CE_PANIC, "programming error: " 1189 "abort command limit exceeded in cmd %p", (void *)cmd); 1190 return (0); 1191 1192 case NVME_CQE_SC_SPC_ASYNC_EVREQ_EXC: 1193 /* Async Event Request Limit Exceeded */ 1194 ASSERT(cmd->nc_sqe.sqe_opc == NVME_OPC_ASYNC_EVENT); 1195 dev_err(cmd->nc_nvme->n_dip, CE_PANIC, "programming error: " 1196 "async event request limit exceeded in cmd %p", 1197 (void *)cmd); 1198 return (0); 1199 1200 case NVME_CQE_SC_SPC_INV_INT_VECT: 1201 /* Invalid Interrupt Vector */ 1202 ASSERT(cmd->nc_sqe.sqe_opc == NVME_OPC_CREATE_CQUEUE); 1203 atomic_inc_32(&cmd->nc_nvme->n_inv_int_vect); 1204 return (EINVAL); 1205 1206 case NVME_CQE_SC_SPC_INV_LOG_PAGE: 1207 /* Invalid Log Page */ 1208 ASSERT(cmd->nc_sqe.sqe_opc == NVME_OPC_GET_LOG_PAGE); 1209 atomic_inc_32(&cmd->nc_nvme->n_inv_log_page); 1210 return (EINVAL); 1211 1212 case NVME_CQE_SC_SPC_INV_FORMAT: 1213 /* Invalid Format */ 1214 ASSERT(cmd->nc_sqe.sqe_opc == NVME_OPC_NVM_FORMAT); 1215 atomic_inc_32(&cmd->nc_nvme->n_inv_format); 1216 if (cmd->nc_xfer != NULL) 1217 bd_error(cmd->nc_xfer, BD_ERR_ILLRQ); 1218 return (EINVAL); 1219 1220 case NVME_CQE_SC_SPC_INV_Q_DEL: 1221 /* Invalid Queue Deletion */ 1222 ASSERT(cmd->nc_sqe.sqe_opc == NVME_OPC_DELETE_CQUEUE); 1223 atomic_inc_32(&cmd->nc_nvme->n_inv_q_del); 1224 return (EINVAL); 1225 1226 case NVME_CQE_SC_SPC_NVM_CNFL_ATTR: 1227 /* Conflicting Attributes */ 1228 ASSERT(cmd->nc_sqe.sqe_opc == NVME_OPC_NVM_DSET_MGMT || 1229 cmd->nc_sqe.sqe_opc == NVME_OPC_NVM_READ || 1230 cmd->nc_sqe.sqe_opc == NVME_OPC_NVM_WRITE); 1231 atomic_inc_32(&cmd->nc_nvme->n_cnfl_attr); 1232 if (cmd->nc_xfer != NULL) 1233 bd_error(cmd->nc_xfer, BD_ERR_ILLRQ); 1234 return (EINVAL); 1235 1236 case NVME_CQE_SC_SPC_NVM_INV_PROT: 1237 /* Invalid Protection Information */ 1238 ASSERT(cmd->nc_sqe.sqe_opc == NVME_OPC_NVM_COMPARE || 1239 cmd->nc_sqe.sqe_opc == NVME_OPC_NVM_READ || 1240 cmd->nc_sqe.sqe_opc == NVME_OPC_NVM_WRITE); 1241 atomic_inc_32(&cmd->nc_nvme->n_inv_prot); 1242 if (cmd->nc_xfer != NULL) 1243 bd_error(cmd->nc_xfer, BD_ERR_ILLRQ); 1244 return (EINVAL); 1245 1246 case NVME_CQE_SC_SPC_NVM_READONLY: 1247 /* Write to Read Only Range */ 1248 ASSERT(cmd->nc_sqe.sqe_opc == NVME_OPC_NVM_WRITE); 1249 atomic_inc_32(&cmd->nc_nvme->n_readonly); 1250 if (cmd->nc_xfer != NULL) 1251 bd_error(cmd->nc_xfer, BD_ERR_ILLRQ); 1252 return (EROFS); 1253 1254 default: 1255 return (nvme_check_unknown_cmd_status(cmd)); 1256 } 1257 } 1258 1259 static inline int 1260 nvme_check_cmd_status(nvme_cmd_t *cmd) 1261 { 1262 nvme_cqe_t *cqe = &cmd->nc_cqe; 1263 1264 /* 1265 * Take a shortcut if the controller is dead, or if 1266 * command status indicates no error. 1267 */ 1268 if (cmd->nc_nvme->n_dead) 1269 return (EIO); 1270 1271 if (cqe->cqe_sf.sf_sct == NVME_CQE_SCT_GENERIC && 1272 cqe->cqe_sf.sf_sc == NVME_CQE_SC_GEN_SUCCESS) 1273 return (0); 1274 1275 if (cqe->cqe_sf.sf_sct == NVME_CQE_SCT_GENERIC) 1276 return (nvme_check_generic_cmd_status(cmd)); 1277 else if (cqe->cqe_sf.sf_sct == NVME_CQE_SCT_SPECIFIC) 1278 return (nvme_check_specific_cmd_status(cmd)); 1279 else if (cqe->cqe_sf.sf_sct == NVME_CQE_SCT_INTEGRITY) 1280 return (nvme_check_integrity_cmd_status(cmd)); 1281 else if (cqe->cqe_sf.sf_sct == NVME_CQE_SCT_VENDOR) 1282 return (nvme_check_vendor_cmd_status(cmd)); 1283 1284 return (nvme_check_unknown_cmd_status(cmd)); 1285 } 1286 1287 static int 1288 nvme_abort_cmd(nvme_cmd_t *abort_cmd, uint_t sec) 1289 { 1290 nvme_t *nvme = abort_cmd->nc_nvme; 1291 nvme_cmd_t *cmd = nvme_alloc_cmd(nvme, KM_SLEEP); 1292 nvme_abort_cmd_t ac = { 0 }; 1293 int ret = 0; 1294 1295 sema_p(&nvme->n_abort_sema); 1296 1297 ac.b.ac_cid = abort_cmd->nc_sqe.sqe_cid; 1298 ac.b.ac_sqid = abort_cmd->nc_sqid; 1299 1300 cmd->nc_sqid = 0; 1301 cmd->nc_sqe.sqe_opc = NVME_OPC_ABORT; 1302 cmd->nc_callback = nvme_wakeup_cmd; 1303 cmd->nc_sqe.sqe_cdw10 = ac.r; 1304 1305 /* 1306 * Send the ABORT to the hardware. The ABORT command will return _after_ 1307 * the aborted command has completed (aborted or otherwise), but since 1308 * we still hold the aborted command's mutex its callback hasn't been 1309 * processed yet. 1310 */ 1311 nvme_admin_cmd(cmd, sec); 1312 sema_v(&nvme->n_abort_sema); 1313 1314 if ((ret = nvme_check_cmd_status(cmd)) != 0) { 1315 dev_err(nvme->n_dip, CE_WARN, 1316 "!ABORT failed with sct = %x, sc = %x", 1317 cmd->nc_cqe.cqe_sf.sf_sct, cmd->nc_cqe.cqe_sf.sf_sc); 1318 atomic_inc_32(&nvme->n_abort_failed); 1319 } else { 1320 dev_err(nvme->n_dip, CE_WARN, 1321 "!ABORT of command %d/%d %ssuccessful", 1322 abort_cmd->nc_sqe.sqe_cid, abort_cmd->nc_sqid, 1323 cmd->nc_cqe.cqe_dw0 & 1 ? "un" : ""); 1324 if ((cmd->nc_cqe.cqe_dw0 & 1) == 0) 1325 atomic_inc_32(&nvme->n_cmd_aborted); 1326 } 1327 1328 nvme_free_cmd(cmd); 1329 return (ret); 1330 } 1331 1332 /* 1333 * nvme_wait_cmd -- wait for command completion or timeout 1334 * 1335 * In case of a serious error or a timeout of the abort command the hardware 1336 * will be declared dead and FMA will be notified. 1337 */ 1338 static void 1339 nvme_wait_cmd(nvme_cmd_t *cmd, uint_t sec) 1340 { 1341 clock_t timeout = ddi_get_lbolt() + drv_usectohz(sec * MICROSEC); 1342 nvme_t *nvme = cmd->nc_nvme; 1343 nvme_reg_csts_t csts; 1344 nvme_qpair_t *qp; 1345 1346 ASSERT(mutex_owned(&cmd->nc_mutex)); 1347 1348 while (!cmd->nc_completed) { 1349 if (cv_timedwait(&cmd->nc_cv, &cmd->nc_mutex, timeout) == -1) 1350 break; 1351 } 1352 1353 if (cmd->nc_completed) 1354 return; 1355 1356 /* 1357 * The command timed out. 1358 * 1359 * Check controller for fatal status, any errors associated with the 1360 * register or DMA handle, or for a double timeout (abort command timed 1361 * out). If necessary log a warning and call FMA. 1362 */ 1363 csts.r = nvme_get32(nvme, NVME_REG_CSTS); 1364 dev_err(nvme->n_dip, CE_WARN, "!command %d/%d timeout, " 1365 "OPC = %x, CFS = %d", cmd->nc_sqe.sqe_cid, cmd->nc_sqid, 1366 cmd->nc_sqe.sqe_opc, csts.b.csts_cfs); 1367 atomic_inc_32(&nvme->n_cmd_timeout); 1368 1369 if (csts.b.csts_cfs || 1370 nvme_check_regs_hdl(nvme) || 1371 nvme_check_dma_hdl(cmd->nc_dma) || 1372 cmd->nc_sqe.sqe_opc == NVME_OPC_ABORT) { 1373 ddi_fm_service_impact(nvme->n_dip, DDI_SERVICE_LOST); 1374 nvme->n_dead = B_TRUE; 1375 } else if (nvme_abort_cmd(cmd, sec) == 0) { 1376 /* 1377 * If the abort succeeded the command should complete 1378 * immediately with an appropriate status. 1379 */ 1380 while (!cmd->nc_completed) 1381 cv_wait(&cmd->nc_cv, &cmd->nc_mutex); 1382 1383 return; 1384 } 1385 1386 qp = nvme->n_ioq[cmd->nc_sqid]; 1387 1388 mutex_enter(&qp->nq_mutex); 1389 (void) nvme_unqueue_cmd(nvme, qp, cmd->nc_sqe.sqe_cid); 1390 mutex_exit(&qp->nq_mutex); 1391 1392 /* 1393 * As we don't know what the presumed dead hardware might still do with 1394 * the DMA memory, we'll put the command on the lost commands list if it 1395 * has any DMA memory. 1396 */ 1397 if (cmd->nc_dma != NULL) { 1398 mutex_enter(&nvme_lc_mutex); 1399 list_insert_head(&nvme_lost_cmds, cmd); 1400 mutex_exit(&nvme_lc_mutex); 1401 } 1402 } 1403 1404 static void 1405 nvme_wakeup_cmd(void *arg) 1406 { 1407 nvme_cmd_t *cmd = arg; 1408 1409 mutex_enter(&cmd->nc_mutex); 1410 cmd->nc_completed = B_TRUE; 1411 cv_signal(&cmd->nc_cv); 1412 mutex_exit(&cmd->nc_mutex); 1413 } 1414 1415 static void 1416 nvme_async_event_task(void *arg) 1417 { 1418 nvme_cmd_t *cmd = arg; 1419 nvme_t *nvme = cmd->nc_nvme; 1420 nvme_error_log_entry_t *error_log = NULL; 1421 nvme_health_log_t *health_log = NULL; 1422 size_t logsize = 0; 1423 nvme_async_event_t event; 1424 1425 /* 1426 * Check for errors associated with the async request itself. The only 1427 * command-specific error is "async event limit exceeded", which 1428 * indicates a programming error in the driver and causes a panic in 1429 * nvme_check_cmd_status(). 1430 * 1431 * Other possible errors are various scenarios where the async request 1432 * was aborted, or internal errors in the device. Internal errors are 1433 * reported to FMA, the command aborts need no special handling here. 1434 */ 1435 if (nvme_check_cmd_status(cmd) != 0) { 1436 dev_err(cmd->nc_nvme->n_dip, CE_WARN, 1437 "!async event request returned failure, sct = %x, " 1438 "sc = %x, dnr = %d, m = %d", cmd->nc_cqe.cqe_sf.sf_sct, 1439 cmd->nc_cqe.cqe_sf.sf_sc, cmd->nc_cqe.cqe_sf.sf_dnr, 1440 cmd->nc_cqe.cqe_sf.sf_m); 1441 1442 if (cmd->nc_cqe.cqe_sf.sf_sct == NVME_CQE_SCT_GENERIC && 1443 cmd->nc_cqe.cqe_sf.sf_sc == NVME_CQE_SC_GEN_INTERNAL_ERR) { 1444 cmd->nc_nvme->n_dead = B_TRUE; 1445 ddi_fm_service_impact(cmd->nc_nvme->n_dip, 1446 DDI_SERVICE_LOST); 1447 } 1448 nvme_free_cmd(cmd); 1449 return; 1450 } 1451 1452 1453 event.r = cmd->nc_cqe.cqe_dw0; 1454 1455 /* Clear CQE and re-submit the async request. */ 1456 bzero(&cmd->nc_cqe, sizeof (nvme_cqe_t)); 1457 nvme_submit_admin_cmd(nvme->n_adminq, cmd); 1458 1459 switch (event.b.ae_type) { 1460 case NVME_ASYNC_TYPE_ERROR: 1461 if (event.b.ae_logpage == NVME_LOGPAGE_ERROR) { 1462 (void) nvme_get_logpage(nvme, (void **)&error_log, 1463 &logsize, event.b.ae_logpage); 1464 } else { 1465 dev_err(nvme->n_dip, CE_WARN, "!wrong logpage in " 1466 "async event reply: %d", event.b.ae_logpage); 1467 atomic_inc_32(&nvme->n_wrong_logpage); 1468 } 1469 1470 switch (event.b.ae_info) { 1471 case NVME_ASYNC_ERROR_INV_SQ: 1472 dev_err(nvme->n_dip, CE_PANIC, "programming error: " 1473 "invalid submission queue"); 1474 return; 1475 1476 case NVME_ASYNC_ERROR_INV_DBL: 1477 dev_err(nvme->n_dip, CE_PANIC, "programming error: " 1478 "invalid doorbell write value"); 1479 return; 1480 1481 case NVME_ASYNC_ERROR_DIAGFAIL: 1482 dev_err(nvme->n_dip, CE_WARN, "!diagnostic failure"); 1483 ddi_fm_service_impact(nvme->n_dip, DDI_SERVICE_LOST); 1484 nvme->n_dead = B_TRUE; 1485 atomic_inc_32(&nvme->n_diagfail_event); 1486 break; 1487 1488 case NVME_ASYNC_ERROR_PERSISTENT: 1489 dev_err(nvme->n_dip, CE_WARN, "!persistent internal " 1490 "device error"); 1491 ddi_fm_service_impact(nvme->n_dip, DDI_SERVICE_LOST); 1492 nvme->n_dead = B_TRUE; 1493 atomic_inc_32(&nvme->n_persistent_event); 1494 break; 1495 1496 case NVME_ASYNC_ERROR_TRANSIENT: 1497 dev_err(nvme->n_dip, CE_WARN, "!transient internal " 1498 "device error"); 1499 /* TODO: send ereport */ 1500 atomic_inc_32(&nvme->n_transient_event); 1501 break; 1502 1503 case NVME_ASYNC_ERROR_FW_LOAD: 1504 dev_err(nvme->n_dip, CE_WARN, 1505 "!firmware image load error"); 1506 atomic_inc_32(&nvme->n_fw_load_event); 1507 break; 1508 } 1509 break; 1510 1511 case NVME_ASYNC_TYPE_HEALTH: 1512 if (event.b.ae_logpage == NVME_LOGPAGE_HEALTH) { 1513 (void) nvme_get_logpage(nvme, (void **)&health_log, 1514 &logsize, event.b.ae_logpage, -1); 1515 } else { 1516 dev_err(nvme->n_dip, CE_WARN, "!wrong logpage in " 1517 "async event reply: %d", event.b.ae_logpage); 1518 atomic_inc_32(&nvme->n_wrong_logpage); 1519 } 1520 1521 switch (event.b.ae_info) { 1522 case NVME_ASYNC_HEALTH_RELIABILITY: 1523 dev_err(nvme->n_dip, CE_WARN, 1524 "!device reliability compromised"); 1525 /* TODO: send ereport */ 1526 atomic_inc_32(&nvme->n_reliability_event); 1527 break; 1528 1529 case NVME_ASYNC_HEALTH_TEMPERATURE: 1530 dev_err(nvme->n_dip, CE_WARN, 1531 "!temperature above threshold"); 1532 /* TODO: send ereport */ 1533 atomic_inc_32(&nvme->n_temperature_event); 1534 break; 1535 1536 case NVME_ASYNC_HEALTH_SPARE: 1537 dev_err(nvme->n_dip, CE_WARN, 1538 "!spare space below threshold"); 1539 /* TODO: send ereport */ 1540 atomic_inc_32(&nvme->n_spare_event); 1541 break; 1542 } 1543 break; 1544 1545 case NVME_ASYNC_TYPE_VENDOR: 1546 dev_err(nvme->n_dip, CE_WARN, "!vendor specific async event " 1547 "received, info = %x, logpage = %x", event.b.ae_info, 1548 event.b.ae_logpage); 1549 atomic_inc_32(&nvme->n_vendor_event); 1550 break; 1551 1552 default: 1553 dev_err(nvme->n_dip, CE_WARN, "!unknown async event received, " 1554 "type = %x, info = %x, logpage = %x", event.b.ae_type, 1555 event.b.ae_info, event.b.ae_logpage); 1556 atomic_inc_32(&nvme->n_unknown_event); 1557 break; 1558 } 1559 1560 if (error_log) 1561 kmem_free(error_log, logsize); 1562 1563 if (health_log) 1564 kmem_free(health_log, logsize); 1565 } 1566 1567 static void 1568 nvme_admin_cmd(nvme_cmd_t *cmd, int sec) 1569 { 1570 mutex_enter(&cmd->nc_mutex); 1571 nvme_submit_admin_cmd(cmd->nc_nvme->n_adminq, cmd); 1572 nvme_wait_cmd(cmd, sec); 1573 mutex_exit(&cmd->nc_mutex); 1574 } 1575 1576 static void 1577 nvme_async_event(nvme_t *nvme) 1578 { 1579 nvme_cmd_t *cmd = nvme_alloc_cmd(nvme, KM_SLEEP); 1580 1581 cmd->nc_sqid = 0; 1582 cmd->nc_sqe.sqe_opc = NVME_OPC_ASYNC_EVENT; 1583 cmd->nc_callback = nvme_async_event_task; 1584 1585 nvme_submit_admin_cmd(nvme->n_adminq, cmd); 1586 } 1587 1588 static int 1589 nvme_format_nvm(nvme_t *nvme, uint32_t nsid, uint8_t lbaf, boolean_t ms, 1590 uint8_t pi, boolean_t pil, uint8_t ses) 1591 { 1592 nvme_cmd_t *cmd = nvme_alloc_cmd(nvme, KM_SLEEP); 1593 nvme_format_nvm_t format_nvm = { 0 }; 1594 int ret; 1595 1596 format_nvm.b.fm_lbaf = lbaf & 0xf; 1597 format_nvm.b.fm_ms = ms ? 1 : 0; 1598 format_nvm.b.fm_pi = pi & 0x7; 1599 format_nvm.b.fm_pil = pil ? 1 : 0; 1600 format_nvm.b.fm_ses = ses & 0x7; 1601 1602 cmd->nc_sqid = 0; 1603 cmd->nc_callback = nvme_wakeup_cmd; 1604 cmd->nc_sqe.sqe_nsid = nsid; 1605 cmd->nc_sqe.sqe_opc = NVME_OPC_NVM_FORMAT; 1606 cmd->nc_sqe.sqe_cdw10 = format_nvm.r; 1607 1608 /* 1609 * Some devices like Samsung SM951 don't allow formatting of all 1610 * namespaces in one command. Handle that gracefully. 1611 */ 1612 if (nsid == (uint32_t)-1) 1613 cmd->nc_dontpanic = B_TRUE; 1614 1615 nvme_admin_cmd(cmd, nvme_format_cmd_timeout); 1616 1617 if ((ret = nvme_check_cmd_status(cmd)) != 0) { 1618 dev_err(nvme->n_dip, CE_WARN, 1619 "!FORMAT failed with sct = %x, sc = %x", 1620 cmd->nc_cqe.cqe_sf.sf_sct, cmd->nc_cqe.cqe_sf.sf_sc); 1621 } 1622 1623 nvme_free_cmd(cmd); 1624 return (ret); 1625 } 1626 1627 static int 1628 nvme_get_logpage(nvme_t *nvme, void **buf, size_t *bufsize, uint8_t logpage, 1629 ...) 1630 { 1631 nvme_cmd_t *cmd = nvme_alloc_cmd(nvme, KM_SLEEP); 1632 nvme_getlogpage_t getlogpage = { 0 }; 1633 va_list ap; 1634 int ret; 1635 1636 va_start(ap, logpage); 1637 1638 cmd->nc_sqid = 0; 1639 cmd->nc_callback = nvme_wakeup_cmd; 1640 cmd->nc_sqe.sqe_opc = NVME_OPC_GET_LOG_PAGE; 1641 1642 getlogpage.b.lp_lid = logpage; 1643 1644 switch (logpage) { 1645 case NVME_LOGPAGE_ERROR: 1646 cmd->nc_sqe.sqe_nsid = (uint32_t)-1; 1647 /* 1648 * The GET LOG PAGE command can use at most 2 pages to return 1649 * data, PRP lists are not supported. 1650 */ 1651 *bufsize = MIN(2 * nvme->n_pagesize, 1652 nvme->n_error_log_len * sizeof (nvme_error_log_entry_t)); 1653 break; 1654 1655 case NVME_LOGPAGE_HEALTH: 1656 cmd->nc_sqe.sqe_nsid = va_arg(ap, uint32_t); 1657 *bufsize = sizeof (nvme_health_log_t); 1658 break; 1659 1660 case NVME_LOGPAGE_FWSLOT: 1661 cmd->nc_sqe.sqe_nsid = (uint32_t)-1; 1662 *bufsize = sizeof (nvme_fwslot_log_t); 1663 break; 1664 1665 default: 1666 dev_err(nvme->n_dip, CE_WARN, "!unknown log page requested: %d", 1667 logpage); 1668 atomic_inc_32(&nvme->n_unknown_logpage); 1669 ret = EINVAL; 1670 goto fail; 1671 } 1672 1673 va_end(ap); 1674 1675 getlogpage.b.lp_numd = *bufsize / sizeof (uint32_t) - 1; 1676 1677 cmd->nc_sqe.sqe_cdw10 = getlogpage.r; 1678 1679 if (nvme_zalloc_dma(nvme, getlogpage.b.lp_numd * sizeof (uint32_t), 1680 DDI_DMA_READ, &nvme->n_prp_dma_attr, &cmd->nc_dma) != DDI_SUCCESS) { 1681 dev_err(nvme->n_dip, CE_WARN, 1682 "!nvme_zalloc_dma failed for GET LOG PAGE"); 1683 ret = ENOMEM; 1684 goto fail; 1685 } 1686 1687 if (cmd->nc_dma->nd_ncookie > 2) { 1688 dev_err(nvme->n_dip, CE_WARN, 1689 "!too many DMA cookies for GET LOG PAGE"); 1690 atomic_inc_32(&nvme->n_too_many_cookies); 1691 ret = ENOMEM; 1692 goto fail; 1693 } 1694 1695 cmd->nc_sqe.sqe_dptr.d_prp[0] = cmd->nc_dma->nd_cookie.dmac_laddress; 1696 if (cmd->nc_dma->nd_ncookie > 1) { 1697 ddi_dma_nextcookie(cmd->nc_dma->nd_dmah, 1698 &cmd->nc_dma->nd_cookie); 1699 cmd->nc_sqe.sqe_dptr.d_prp[1] = 1700 cmd->nc_dma->nd_cookie.dmac_laddress; 1701 } 1702 1703 nvme_admin_cmd(cmd, nvme_admin_cmd_timeout); 1704 1705 if ((ret = nvme_check_cmd_status(cmd)) != 0) { 1706 dev_err(nvme->n_dip, CE_WARN, 1707 "!GET LOG PAGE failed with sct = %x, sc = %x", 1708 cmd->nc_cqe.cqe_sf.sf_sct, cmd->nc_cqe.cqe_sf.sf_sc); 1709 goto fail; 1710 } 1711 1712 *buf = kmem_alloc(*bufsize, KM_SLEEP); 1713 bcopy(cmd->nc_dma->nd_memp, *buf, *bufsize); 1714 1715 fail: 1716 nvme_free_cmd(cmd); 1717 1718 return (ret); 1719 } 1720 1721 static int 1722 nvme_identify(nvme_t *nvme, uint32_t nsid, void **buf) 1723 { 1724 nvme_cmd_t *cmd = nvme_alloc_cmd(nvme, KM_SLEEP); 1725 int ret; 1726 1727 if (buf == NULL) 1728 return (EINVAL); 1729 1730 cmd->nc_sqid = 0; 1731 cmd->nc_callback = nvme_wakeup_cmd; 1732 cmd->nc_sqe.sqe_opc = NVME_OPC_IDENTIFY; 1733 cmd->nc_sqe.sqe_nsid = nsid; 1734 cmd->nc_sqe.sqe_cdw10 = nsid ? NVME_IDENTIFY_NSID : NVME_IDENTIFY_CTRL; 1735 1736 if (nvme_zalloc_dma(nvme, NVME_IDENTIFY_BUFSIZE, DDI_DMA_READ, 1737 &nvme->n_prp_dma_attr, &cmd->nc_dma) != DDI_SUCCESS) { 1738 dev_err(nvme->n_dip, CE_WARN, 1739 "!nvme_zalloc_dma failed for IDENTIFY"); 1740 ret = ENOMEM; 1741 goto fail; 1742 } 1743 1744 if (cmd->nc_dma->nd_ncookie > 2) { 1745 dev_err(nvme->n_dip, CE_WARN, 1746 "!too many DMA cookies for IDENTIFY"); 1747 atomic_inc_32(&nvme->n_too_many_cookies); 1748 ret = ENOMEM; 1749 goto fail; 1750 } 1751 1752 cmd->nc_sqe.sqe_dptr.d_prp[0] = cmd->nc_dma->nd_cookie.dmac_laddress; 1753 if (cmd->nc_dma->nd_ncookie > 1) { 1754 ddi_dma_nextcookie(cmd->nc_dma->nd_dmah, 1755 &cmd->nc_dma->nd_cookie); 1756 cmd->nc_sqe.sqe_dptr.d_prp[1] = 1757 cmd->nc_dma->nd_cookie.dmac_laddress; 1758 } 1759 1760 nvme_admin_cmd(cmd, nvme_admin_cmd_timeout); 1761 1762 if ((ret = nvme_check_cmd_status(cmd)) != 0) { 1763 dev_err(nvme->n_dip, CE_WARN, 1764 "!IDENTIFY failed with sct = %x, sc = %x", 1765 cmd->nc_cqe.cqe_sf.sf_sct, cmd->nc_cqe.cqe_sf.sf_sc); 1766 goto fail; 1767 } 1768 1769 *buf = kmem_alloc(NVME_IDENTIFY_BUFSIZE, KM_SLEEP); 1770 bcopy(cmd->nc_dma->nd_memp, *buf, NVME_IDENTIFY_BUFSIZE); 1771 1772 fail: 1773 nvme_free_cmd(cmd); 1774 1775 return (ret); 1776 } 1777 1778 static int 1779 nvme_set_features(nvme_t *nvme, uint32_t nsid, uint8_t feature, uint32_t val, 1780 uint32_t *res) 1781 { 1782 _NOTE(ARGUNUSED(nsid)); 1783 nvme_cmd_t *cmd = nvme_alloc_cmd(nvme, KM_SLEEP); 1784 int ret = EINVAL; 1785 1786 ASSERT(res != NULL); 1787 1788 cmd->nc_sqid = 0; 1789 cmd->nc_callback = nvme_wakeup_cmd; 1790 cmd->nc_sqe.sqe_opc = NVME_OPC_SET_FEATURES; 1791 cmd->nc_sqe.sqe_cdw10 = feature; 1792 cmd->nc_sqe.sqe_cdw11 = val; 1793 1794 switch (feature) { 1795 case NVME_FEAT_WRITE_CACHE: 1796 if (!nvme->n_write_cache_present) 1797 goto fail; 1798 break; 1799 1800 case NVME_FEAT_NQUEUES: 1801 break; 1802 1803 default: 1804 goto fail; 1805 } 1806 1807 nvme_admin_cmd(cmd, nvme_admin_cmd_timeout); 1808 1809 if ((ret = nvme_check_cmd_status(cmd)) != 0) { 1810 dev_err(nvme->n_dip, CE_WARN, 1811 "!SET FEATURES %d failed with sct = %x, sc = %x", 1812 feature, cmd->nc_cqe.cqe_sf.sf_sct, 1813 cmd->nc_cqe.cqe_sf.sf_sc); 1814 goto fail; 1815 } 1816 1817 *res = cmd->nc_cqe.cqe_dw0; 1818 1819 fail: 1820 nvme_free_cmd(cmd); 1821 return (ret); 1822 } 1823 1824 static int 1825 nvme_get_features(nvme_t *nvme, uint32_t nsid, uint8_t feature, uint32_t *res, 1826 void **buf, size_t *bufsize) 1827 { 1828 nvme_cmd_t *cmd = nvme_alloc_cmd(nvme, KM_SLEEP); 1829 int ret = EINVAL; 1830 1831 ASSERT(res != NULL); 1832 1833 if (bufsize != NULL) 1834 *bufsize = 0; 1835 1836 cmd->nc_sqid = 0; 1837 cmd->nc_callback = nvme_wakeup_cmd; 1838 cmd->nc_sqe.sqe_opc = NVME_OPC_GET_FEATURES; 1839 cmd->nc_sqe.sqe_cdw10 = feature; 1840 cmd->nc_sqe.sqe_cdw11 = *res; 1841 1842 switch (feature) { 1843 case NVME_FEAT_ARBITRATION: 1844 case NVME_FEAT_POWER_MGMT: 1845 case NVME_FEAT_TEMPERATURE: 1846 case NVME_FEAT_ERROR: 1847 case NVME_FEAT_NQUEUES: 1848 case NVME_FEAT_INTR_COAL: 1849 case NVME_FEAT_INTR_VECT: 1850 case NVME_FEAT_WRITE_ATOM: 1851 case NVME_FEAT_ASYNC_EVENT: 1852 case NVME_FEAT_PROGRESS: 1853 break; 1854 1855 case NVME_FEAT_WRITE_CACHE: 1856 if (!nvme->n_write_cache_present) 1857 goto fail; 1858 break; 1859 1860 case NVME_FEAT_LBA_RANGE: 1861 if (!nvme->n_lba_range_supported) 1862 goto fail; 1863 1864 /* 1865 * The LBA Range Type feature is optional. There doesn't seem 1866 * be a method of detecting whether it is supported other than 1867 * using it. This will cause a "invalid field in command" error, 1868 * which is normally considered a programming error and causes 1869 * panic in nvme_check_generic_cmd_status(). 1870 */ 1871 cmd->nc_dontpanic = B_TRUE; 1872 cmd->nc_sqe.sqe_nsid = nsid; 1873 ASSERT(bufsize != NULL); 1874 *bufsize = NVME_LBA_RANGE_BUFSIZE; 1875 1876 break; 1877 1878 case NVME_FEAT_AUTO_PST: 1879 if (!nvme->n_auto_pst_supported) 1880 goto fail; 1881 1882 ASSERT(bufsize != NULL); 1883 *bufsize = NVME_AUTO_PST_BUFSIZE; 1884 break; 1885 1886 default: 1887 goto fail; 1888 } 1889 1890 if (bufsize != NULL && *bufsize != 0) { 1891 if (nvme_zalloc_dma(nvme, *bufsize, DDI_DMA_READ, 1892 &nvme->n_prp_dma_attr, &cmd->nc_dma) != DDI_SUCCESS) { 1893 dev_err(nvme->n_dip, CE_WARN, 1894 "!nvme_zalloc_dma failed for GET FEATURES"); 1895 ret = ENOMEM; 1896 goto fail; 1897 } 1898 1899 if (cmd->nc_dma->nd_ncookie > 2) { 1900 dev_err(nvme->n_dip, CE_WARN, 1901 "!too many DMA cookies for GET FEATURES"); 1902 atomic_inc_32(&nvme->n_too_many_cookies); 1903 ret = ENOMEM; 1904 goto fail; 1905 } 1906 1907 cmd->nc_sqe.sqe_dptr.d_prp[0] = 1908 cmd->nc_dma->nd_cookie.dmac_laddress; 1909 if (cmd->nc_dma->nd_ncookie > 1) { 1910 ddi_dma_nextcookie(cmd->nc_dma->nd_dmah, 1911 &cmd->nc_dma->nd_cookie); 1912 cmd->nc_sqe.sqe_dptr.d_prp[1] = 1913 cmd->nc_dma->nd_cookie.dmac_laddress; 1914 } 1915 } 1916 1917 nvme_admin_cmd(cmd, nvme_admin_cmd_timeout); 1918 1919 if ((ret = nvme_check_cmd_status(cmd)) != 0) { 1920 if (feature == NVME_FEAT_LBA_RANGE && 1921 cmd->nc_cqe.cqe_sf.sf_sct == NVME_CQE_SCT_GENERIC && 1922 cmd->nc_cqe.cqe_sf.sf_sc == NVME_CQE_SC_GEN_INV_FLD) 1923 nvme->n_lba_range_supported = B_FALSE; 1924 else 1925 dev_err(nvme->n_dip, CE_WARN, 1926 "!GET FEATURES %d failed with sct = %x, sc = %x", 1927 feature, cmd->nc_cqe.cqe_sf.sf_sct, 1928 cmd->nc_cqe.cqe_sf.sf_sc); 1929 goto fail; 1930 } 1931 1932 if (bufsize != NULL && *bufsize != 0) { 1933 ASSERT(buf != NULL); 1934 *buf = kmem_alloc(*bufsize, KM_SLEEP); 1935 bcopy(cmd->nc_dma->nd_memp, *buf, *bufsize); 1936 } 1937 1938 *res = cmd->nc_cqe.cqe_dw0; 1939 1940 fail: 1941 nvme_free_cmd(cmd); 1942 return (ret); 1943 } 1944 1945 static int 1946 nvme_write_cache_set(nvme_t *nvme, boolean_t enable) 1947 { 1948 nvme_write_cache_t nwc = { 0 }; 1949 1950 if (enable) 1951 nwc.b.wc_wce = 1; 1952 1953 return (nvme_set_features(nvme, 0, NVME_FEAT_WRITE_CACHE, nwc.r, 1954 &nwc.r)); 1955 } 1956 1957 static int 1958 nvme_set_nqueues(nvme_t *nvme, uint16_t *nqueues) 1959 { 1960 nvme_nqueues_t nq = { 0 }; 1961 int ret; 1962 1963 nq.b.nq_nsq = nq.b.nq_ncq = *nqueues - 1; 1964 1965 ret = nvme_set_features(nvme, 0, NVME_FEAT_NQUEUES, nq.r, &nq.r); 1966 1967 if (ret == 0) { 1968 /* 1969 * Always use the same number of submission and completion 1970 * queues, and never use more than the requested number of 1971 * queues. 1972 */ 1973 *nqueues = MIN(*nqueues, MIN(nq.b.nq_nsq, nq.b.nq_ncq) + 1); 1974 } 1975 1976 return (ret); 1977 } 1978 1979 static int 1980 nvme_create_io_qpair(nvme_t *nvme, nvme_qpair_t *qp, uint16_t idx) 1981 { 1982 nvme_cmd_t *cmd = nvme_alloc_cmd(nvme, KM_SLEEP); 1983 nvme_create_queue_dw10_t dw10 = { 0 }; 1984 nvme_create_cq_dw11_t c_dw11 = { 0 }; 1985 nvme_create_sq_dw11_t s_dw11 = { 0 }; 1986 int ret; 1987 1988 dw10.b.q_qid = idx; 1989 dw10.b.q_qsize = qp->nq_nentry - 1; 1990 1991 c_dw11.b.cq_pc = 1; 1992 c_dw11.b.cq_ien = 1; 1993 c_dw11.b.cq_iv = idx % nvme->n_intr_cnt; 1994 1995 cmd->nc_sqid = 0; 1996 cmd->nc_callback = nvme_wakeup_cmd; 1997 cmd->nc_sqe.sqe_opc = NVME_OPC_CREATE_CQUEUE; 1998 cmd->nc_sqe.sqe_cdw10 = dw10.r; 1999 cmd->nc_sqe.sqe_cdw11 = c_dw11.r; 2000 cmd->nc_sqe.sqe_dptr.d_prp[0] = qp->nq_cqdma->nd_cookie.dmac_laddress; 2001 2002 nvme_admin_cmd(cmd, nvme_admin_cmd_timeout); 2003 2004 if ((ret = nvme_check_cmd_status(cmd)) != 0) { 2005 dev_err(nvme->n_dip, CE_WARN, 2006 "!CREATE CQUEUE failed with sct = %x, sc = %x", 2007 cmd->nc_cqe.cqe_sf.sf_sct, cmd->nc_cqe.cqe_sf.sf_sc); 2008 goto fail; 2009 } 2010 2011 nvme_free_cmd(cmd); 2012 2013 s_dw11.b.sq_pc = 1; 2014 s_dw11.b.sq_cqid = idx; 2015 2016 cmd = nvme_alloc_cmd(nvme, KM_SLEEP); 2017 cmd->nc_sqid = 0; 2018 cmd->nc_callback = nvme_wakeup_cmd; 2019 cmd->nc_sqe.sqe_opc = NVME_OPC_CREATE_SQUEUE; 2020 cmd->nc_sqe.sqe_cdw10 = dw10.r; 2021 cmd->nc_sqe.sqe_cdw11 = s_dw11.r; 2022 cmd->nc_sqe.sqe_dptr.d_prp[0] = qp->nq_sqdma->nd_cookie.dmac_laddress; 2023 2024 nvme_admin_cmd(cmd, nvme_admin_cmd_timeout); 2025 2026 if ((ret = nvme_check_cmd_status(cmd)) != 0) { 2027 dev_err(nvme->n_dip, CE_WARN, 2028 "!CREATE SQUEUE failed with sct = %x, sc = %x", 2029 cmd->nc_cqe.cqe_sf.sf_sct, cmd->nc_cqe.cqe_sf.sf_sc); 2030 goto fail; 2031 } 2032 2033 fail: 2034 nvme_free_cmd(cmd); 2035 2036 return (ret); 2037 } 2038 2039 static boolean_t 2040 nvme_reset(nvme_t *nvme, boolean_t quiesce) 2041 { 2042 nvme_reg_csts_t csts; 2043 int i; 2044 2045 nvme_put32(nvme, NVME_REG_CC, 0); 2046 2047 csts.r = nvme_get32(nvme, NVME_REG_CSTS); 2048 if (csts.b.csts_rdy == 1) { 2049 nvme_put32(nvme, NVME_REG_CC, 0); 2050 for (i = 0; i != nvme->n_timeout * 10; i++) { 2051 csts.r = nvme_get32(nvme, NVME_REG_CSTS); 2052 if (csts.b.csts_rdy == 0) 2053 break; 2054 2055 if (quiesce) 2056 drv_usecwait(50000); 2057 else 2058 delay(drv_usectohz(50000)); 2059 } 2060 } 2061 2062 nvme_put32(nvme, NVME_REG_AQA, 0); 2063 nvme_put32(nvme, NVME_REG_ASQ, 0); 2064 nvme_put32(nvme, NVME_REG_ACQ, 0); 2065 2066 csts.r = nvme_get32(nvme, NVME_REG_CSTS); 2067 return (csts.b.csts_rdy == 0 ? B_TRUE : B_FALSE); 2068 } 2069 2070 static void 2071 nvme_shutdown(nvme_t *nvme, int mode, boolean_t quiesce) 2072 { 2073 nvme_reg_cc_t cc; 2074 nvme_reg_csts_t csts; 2075 int i; 2076 2077 ASSERT(mode == NVME_CC_SHN_NORMAL || mode == NVME_CC_SHN_ABRUPT); 2078 2079 cc.r = nvme_get32(nvme, NVME_REG_CC); 2080 cc.b.cc_shn = mode & 0x3; 2081 nvme_put32(nvme, NVME_REG_CC, cc.r); 2082 2083 for (i = 0; i != 10; i++) { 2084 csts.r = nvme_get32(nvme, NVME_REG_CSTS); 2085 if (csts.b.csts_shst == NVME_CSTS_SHN_COMPLETE) 2086 break; 2087 2088 if (quiesce) 2089 drv_usecwait(100000); 2090 else 2091 delay(drv_usectohz(100000)); 2092 } 2093 } 2094 2095 2096 static void 2097 nvme_prepare_devid(nvme_t *nvme, uint32_t nsid) 2098 { 2099 /* 2100 * Section 7.7 of the spec describes how to get a unique ID for 2101 * the controller: the vendor ID, the model name and the serial 2102 * number shall be unique when combined. 2103 * 2104 * If a namespace has no EUI64 we use the above and add the hex 2105 * namespace ID to get a unique ID for the namespace. 2106 */ 2107 char model[sizeof (nvme->n_idctl->id_model) + 1]; 2108 char serial[sizeof (nvme->n_idctl->id_serial) + 1]; 2109 2110 bcopy(nvme->n_idctl->id_model, model, sizeof (nvme->n_idctl->id_model)); 2111 bcopy(nvme->n_idctl->id_serial, serial, 2112 sizeof (nvme->n_idctl->id_serial)); 2113 2114 model[sizeof (nvme->n_idctl->id_model)] = '\0'; 2115 serial[sizeof (nvme->n_idctl->id_serial)] = '\0'; 2116 2117 nvme->n_ns[nsid - 1].ns_devid = kmem_asprintf("%4X-%s-%s-%X", 2118 nvme->n_idctl->id_vid, model, serial, nsid); 2119 } 2120 2121 static int 2122 nvme_init_ns(nvme_t *nvme, int nsid) 2123 { 2124 nvme_namespace_t *ns = &nvme->n_ns[nsid - 1]; 2125 nvme_identify_nsid_t *idns; 2126 int last_rp; 2127 2128 ns->ns_nvme = nvme; 2129 2130 if (nvme_identify(nvme, nsid, (void **)&idns) != 0) { 2131 dev_err(nvme->n_dip, CE_WARN, 2132 "!failed to identify namespace %d", nsid); 2133 return (DDI_FAILURE); 2134 } 2135 2136 ns->ns_idns = idns; 2137 ns->ns_id = nsid; 2138 ns->ns_block_count = idns->id_nsize; 2139 ns->ns_block_size = 2140 1 << idns->id_lbaf[idns->id_flbas.lba_format].lbaf_lbads; 2141 ns->ns_best_block_size = ns->ns_block_size; 2142 2143 /* 2144 * Get the EUI64 if present. Use it for devid and device node names. 2145 */ 2146 if (NVME_VERSION_ATLEAST(&nvme->n_version, 1, 1)) 2147 bcopy(idns->id_eui64, ns->ns_eui64, sizeof (ns->ns_eui64)); 2148 2149 /*LINTED: E_BAD_PTR_CAST_ALIGN*/ 2150 if (*(uint64_t *)ns->ns_eui64 != 0) { 2151 uint8_t *eui64 = ns->ns_eui64; 2152 2153 (void) snprintf(ns->ns_name, sizeof (ns->ns_name), 2154 "%02x%02x%02x%02x%02x%02x%02x%02x", 2155 eui64[0], eui64[1], eui64[2], eui64[3], 2156 eui64[4], eui64[5], eui64[6], eui64[7]); 2157 } else { 2158 (void) snprintf(ns->ns_name, sizeof (ns->ns_name), "%d", 2159 ns->ns_id); 2160 2161 nvme_prepare_devid(nvme, ns->ns_id); 2162 } 2163 2164 /* 2165 * Find the LBA format with no metadata and the best relative 2166 * performance. A value of 3 means "degraded", 0 is best. 2167 */ 2168 last_rp = 3; 2169 for (int j = 0; j <= idns->id_nlbaf; j++) { 2170 if (idns->id_lbaf[j].lbaf_lbads == 0) 2171 break; 2172 if (idns->id_lbaf[j].lbaf_ms != 0) 2173 continue; 2174 if (idns->id_lbaf[j].lbaf_rp >= last_rp) 2175 continue; 2176 last_rp = idns->id_lbaf[j].lbaf_rp; 2177 ns->ns_best_block_size = 2178 1 << idns->id_lbaf[j].lbaf_lbads; 2179 } 2180 2181 if (ns->ns_best_block_size < nvme->n_min_block_size) 2182 ns->ns_best_block_size = nvme->n_min_block_size; 2183 2184 /* 2185 * We currently don't support namespaces that use either: 2186 * - thin provisioning 2187 * - protection information 2188 * - illegal block size (< 512) 2189 */ 2190 if (idns->id_nsfeat.f_thin || 2191 idns->id_dps.dp_pinfo) { 2192 dev_err(nvme->n_dip, CE_WARN, 2193 "!ignoring namespace %d, unsupported features: " 2194 "thin = %d, pinfo = %d", nsid, 2195 idns->id_nsfeat.f_thin, idns->id_dps.dp_pinfo); 2196 ns->ns_ignore = B_TRUE; 2197 } else if (ns->ns_block_size < 512) { 2198 dev_err(nvme->n_dip, CE_WARN, 2199 "!ignoring namespace %d, unsupported block size %"PRIu64, 2200 nsid, (uint64_t)ns->ns_block_size); 2201 ns->ns_ignore = B_TRUE; 2202 } else { 2203 ns->ns_ignore = B_FALSE; 2204 } 2205 2206 return (DDI_SUCCESS); 2207 } 2208 2209 static int 2210 nvme_init(nvme_t *nvme) 2211 { 2212 nvme_reg_cc_t cc = { 0 }; 2213 nvme_reg_aqa_t aqa = { 0 }; 2214 nvme_reg_asq_t asq = { 0 }; 2215 nvme_reg_acq_t acq = { 0 }; 2216 nvme_reg_cap_t cap; 2217 nvme_reg_vs_t vs; 2218 nvme_reg_csts_t csts; 2219 int i = 0; 2220 uint16_t nqueues; 2221 char model[sizeof (nvme->n_idctl->id_model) + 1]; 2222 char *vendor, *product; 2223 2224 /* Check controller version */ 2225 vs.r = nvme_get32(nvme, NVME_REG_VS); 2226 nvme->n_version.v_major = vs.b.vs_mjr; 2227 nvme->n_version.v_minor = vs.b.vs_mnr; 2228 dev_err(nvme->n_dip, CE_CONT, "?NVMe spec version %d.%d", 2229 nvme->n_version.v_major, nvme->n_version.v_minor); 2230 2231 if (NVME_VERSION_HIGHER(&nvme->n_version, 2232 nvme_version_major, nvme_version_minor)) { 2233 dev_err(nvme->n_dip, CE_WARN, "!no support for version > %d.%d", 2234 nvme_version_major, nvme_version_minor); 2235 if (nvme->n_strict_version) 2236 goto fail; 2237 } 2238 2239 /* retrieve controller configuration */ 2240 cap.r = nvme_get64(nvme, NVME_REG_CAP); 2241 2242 if ((cap.b.cap_css & NVME_CAP_CSS_NVM) == 0) { 2243 dev_err(nvme->n_dip, CE_WARN, 2244 "!NVM command set not supported by hardware"); 2245 goto fail; 2246 } 2247 2248 nvme->n_nssr_supported = cap.b.cap_nssrs; 2249 nvme->n_doorbell_stride = 4 << cap.b.cap_dstrd; 2250 nvme->n_timeout = cap.b.cap_to; 2251 nvme->n_arbitration_mechanisms = cap.b.cap_ams; 2252 nvme->n_cont_queues_reqd = cap.b.cap_cqr; 2253 nvme->n_max_queue_entries = cap.b.cap_mqes + 1; 2254 2255 /* 2256 * The MPSMIN and MPSMAX fields in the CAP register use 0 to specify 2257 * the base page size of 4k (1<<12), so add 12 here to get the real 2258 * page size value. 2259 */ 2260 nvme->n_pageshift = MIN(MAX(cap.b.cap_mpsmin + 12, PAGESHIFT), 2261 cap.b.cap_mpsmax + 12); 2262 nvme->n_pagesize = 1UL << (nvme->n_pageshift); 2263 2264 /* 2265 * Set up Queue DMA to transfer at least 1 page-aligned page at a time. 2266 */ 2267 nvme->n_queue_dma_attr.dma_attr_align = nvme->n_pagesize; 2268 nvme->n_queue_dma_attr.dma_attr_minxfer = nvme->n_pagesize; 2269 2270 /* 2271 * Set up PRP DMA to transfer 1 page-aligned page at a time. 2272 * Maxxfer may be increased after we identified the controller limits. 2273 */ 2274 nvme->n_prp_dma_attr.dma_attr_maxxfer = nvme->n_pagesize; 2275 nvme->n_prp_dma_attr.dma_attr_minxfer = nvme->n_pagesize; 2276 nvme->n_prp_dma_attr.dma_attr_align = nvme->n_pagesize; 2277 nvme->n_prp_dma_attr.dma_attr_seg = nvme->n_pagesize - 1; 2278 2279 /* 2280 * Reset controller if it's still in ready state. 2281 */ 2282 if (nvme_reset(nvme, B_FALSE) == B_FALSE) { 2283 dev_err(nvme->n_dip, CE_WARN, "!unable to reset controller"); 2284 ddi_fm_service_impact(nvme->n_dip, DDI_SERVICE_LOST); 2285 nvme->n_dead = B_TRUE; 2286 goto fail; 2287 } 2288 2289 /* 2290 * Create the admin queue pair. 2291 */ 2292 if (nvme_alloc_qpair(nvme, nvme->n_admin_queue_len, &nvme->n_adminq, 0) 2293 != DDI_SUCCESS) { 2294 dev_err(nvme->n_dip, CE_WARN, 2295 "!unable to allocate admin qpair"); 2296 goto fail; 2297 } 2298 nvme->n_ioq = kmem_alloc(sizeof (nvme_qpair_t *), KM_SLEEP); 2299 nvme->n_ioq[0] = nvme->n_adminq; 2300 2301 nvme->n_progress |= NVME_ADMIN_QUEUE; 2302 2303 (void) ddi_prop_update_int(DDI_DEV_T_NONE, nvme->n_dip, 2304 "admin-queue-len", nvme->n_admin_queue_len); 2305 2306 aqa.b.aqa_asqs = aqa.b.aqa_acqs = nvme->n_admin_queue_len - 1; 2307 asq = nvme->n_adminq->nq_sqdma->nd_cookie.dmac_laddress; 2308 acq = nvme->n_adminq->nq_cqdma->nd_cookie.dmac_laddress; 2309 2310 ASSERT((asq & (nvme->n_pagesize - 1)) == 0); 2311 ASSERT((acq & (nvme->n_pagesize - 1)) == 0); 2312 2313 nvme_put32(nvme, NVME_REG_AQA, aqa.r); 2314 nvme_put64(nvme, NVME_REG_ASQ, asq); 2315 nvme_put64(nvme, NVME_REG_ACQ, acq); 2316 2317 cc.b.cc_ams = 0; /* use Round-Robin arbitration */ 2318 cc.b.cc_css = 0; /* use NVM command set */ 2319 cc.b.cc_mps = nvme->n_pageshift - 12; 2320 cc.b.cc_shn = 0; /* no shutdown in progress */ 2321 cc.b.cc_en = 1; /* enable controller */ 2322 cc.b.cc_iosqes = 6; /* submission queue entry is 2^6 bytes long */ 2323 cc.b.cc_iocqes = 4; /* completion queue entry is 2^4 bytes long */ 2324 2325 nvme_put32(nvme, NVME_REG_CC, cc.r); 2326 2327 /* 2328 * Wait for the controller to become ready. 2329 */ 2330 csts.r = nvme_get32(nvme, NVME_REG_CSTS); 2331 if (csts.b.csts_rdy == 0) { 2332 for (i = 0; i != nvme->n_timeout * 10; i++) { 2333 delay(drv_usectohz(50000)); 2334 csts.r = nvme_get32(nvme, NVME_REG_CSTS); 2335 2336 if (csts.b.csts_cfs == 1) { 2337 dev_err(nvme->n_dip, CE_WARN, 2338 "!controller fatal status at init"); 2339 ddi_fm_service_impact(nvme->n_dip, 2340 DDI_SERVICE_LOST); 2341 nvme->n_dead = B_TRUE; 2342 goto fail; 2343 } 2344 2345 if (csts.b.csts_rdy == 1) 2346 break; 2347 } 2348 } 2349 2350 if (csts.b.csts_rdy == 0) { 2351 dev_err(nvme->n_dip, CE_WARN, "!controller not ready"); 2352 ddi_fm_service_impact(nvme->n_dip, DDI_SERVICE_LOST); 2353 nvme->n_dead = B_TRUE; 2354 goto fail; 2355 } 2356 2357 /* 2358 * Assume an abort command limit of 1. We'll destroy and re-init 2359 * that later when we know the true abort command limit. 2360 */ 2361 sema_init(&nvme->n_abort_sema, 1, NULL, SEMA_DRIVER, NULL); 2362 2363 /* 2364 * Setup initial interrupt for admin queue. 2365 */ 2366 if ((nvme_setup_interrupts(nvme, DDI_INTR_TYPE_MSIX, 1) 2367 != DDI_SUCCESS) && 2368 (nvme_setup_interrupts(nvme, DDI_INTR_TYPE_MSI, 1) 2369 != DDI_SUCCESS) && 2370 (nvme_setup_interrupts(nvme, DDI_INTR_TYPE_FIXED, 1) 2371 != DDI_SUCCESS)) { 2372 dev_err(nvme->n_dip, CE_WARN, 2373 "!failed to setup initial interrupt"); 2374 goto fail; 2375 } 2376 2377 /* 2378 * Post an asynchronous event command to catch errors. 2379 */ 2380 nvme_async_event(nvme); 2381 2382 /* 2383 * Identify Controller 2384 */ 2385 if (nvme_identify(nvme, 0, (void **)&nvme->n_idctl) != 0) { 2386 dev_err(nvme->n_dip, CE_WARN, 2387 "!failed to identify controller"); 2388 goto fail; 2389 } 2390 2391 /* 2392 * Get Vendor & Product ID 2393 */ 2394 bcopy(nvme->n_idctl->id_model, model, sizeof (nvme->n_idctl->id_model)); 2395 model[sizeof (nvme->n_idctl->id_model)] = '\0'; 2396 sata_split_model(model, &vendor, &product); 2397 2398 if (vendor == NULL) 2399 nvme->n_vendor = strdup("NVMe"); 2400 else 2401 nvme->n_vendor = strdup(vendor); 2402 2403 nvme->n_product = strdup(product); 2404 2405 /* 2406 * Get controller limits. 2407 */ 2408 nvme->n_async_event_limit = MAX(NVME_MIN_ASYNC_EVENT_LIMIT, 2409 MIN(nvme->n_admin_queue_len / 10, 2410 MIN(nvme->n_idctl->id_aerl + 1, nvme->n_async_event_limit))); 2411 2412 (void) ddi_prop_update_int(DDI_DEV_T_NONE, nvme->n_dip, 2413 "async-event-limit", nvme->n_async_event_limit); 2414 2415 nvme->n_abort_command_limit = nvme->n_idctl->id_acl + 1; 2416 2417 /* 2418 * Reinitialize the semaphore with the true abort command limit 2419 * supported by the hardware. It's not necessary to disable interrupts 2420 * as only command aborts use the semaphore, and no commands are 2421 * executed or aborted while we're here. 2422 */ 2423 sema_destroy(&nvme->n_abort_sema); 2424 sema_init(&nvme->n_abort_sema, nvme->n_abort_command_limit - 1, NULL, 2425 SEMA_DRIVER, NULL); 2426 2427 nvme->n_progress |= NVME_CTRL_LIMITS; 2428 2429 if (nvme->n_idctl->id_mdts == 0) 2430 nvme->n_max_data_transfer_size = nvme->n_pagesize * 65536; 2431 else 2432 nvme->n_max_data_transfer_size = 2433 1ull << (nvme->n_pageshift + nvme->n_idctl->id_mdts); 2434 2435 nvme->n_error_log_len = nvme->n_idctl->id_elpe + 1; 2436 2437 /* 2438 * Limit n_max_data_transfer_size to what we can handle in one PRP. 2439 * Chained PRPs are currently unsupported. 2440 * 2441 * This is a no-op on hardware which doesn't support a transfer size 2442 * big enough to require chained PRPs. 2443 */ 2444 nvme->n_max_data_transfer_size = MIN(nvme->n_max_data_transfer_size, 2445 (nvme->n_pagesize / sizeof (uint64_t) * nvme->n_pagesize)); 2446 2447 nvme->n_prp_dma_attr.dma_attr_maxxfer = nvme->n_max_data_transfer_size; 2448 2449 /* 2450 * Make sure the minimum/maximum queue entry sizes are not 2451 * larger/smaller than the default. 2452 */ 2453 2454 if (((1 << nvme->n_idctl->id_sqes.qes_min) > sizeof (nvme_sqe_t)) || 2455 ((1 << nvme->n_idctl->id_sqes.qes_max) < sizeof (nvme_sqe_t)) || 2456 ((1 << nvme->n_idctl->id_cqes.qes_min) > sizeof (nvme_cqe_t)) || 2457 ((1 << nvme->n_idctl->id_cqes.qes_max) < sizeof (nvme_cqe_t))) 2458 goto fail; 2459 2460 /* 2461 * Check for the presence of a Volatile Write Cache. If present, 2462 * enable or disable based on the value of the property 2463 * volatile-write-cache-enable (default is enabled). 2464 */ 2465 nvme->n_write_cache_present = 2466 nvme->n_idctl->id_vwc.vwc_present == 0 ? B_FALSE : B_TRUE; 2467 2468 (void) ddi_prop_update_int(DDI_DEV_T_NONE, nvme->n_dip, 2469 "volatile-write-cache-present", 2470 nvme->n_write_cache_present ? 1 : 0); 2471 2472 if (!nvme->n_write_cache_present) { 2473 nvme->n_write_cache_enabled = B_FALSE; 2474 } else if (nvme_write_cache_set(nvme, nvme->n_write_cache_enabled) 2475 != 0) { 2476 dev_err(nvme->n_dip, CE_WARN, 2477 "!failed to %sable volatile write cache", 2478 nvme->n_write_cache_enabled ? "en" : "dis"); 2479 /* 2480 * Assume the cache is (still) enabled. 2481 */ 2482 nvme->n_write_cache_enabled = B_TRUE; 2483 } 2484 2485 (void) ddi_prop_update_int(DDI_DEV_T_NONE, nvme->n_dip, 2486 "volatile-write-cache-enable", 2487 nvme->n_write_cache_enabled ? 1 : 0); 2488 2489 /* 2490 * Assume LBA Range Type feature is supported. If it isn't this 2491 * will be set to B_FALSE by nvme_get_features(). 2492 */ 2493 nvme->n_lba_range_supported = B_TRUE; 2494 2495 /* 2496 * Check support for Autonomous Power State Transition. 2497 */ 2498 if (NVME_VERSION_ATLEAST(&nvme->n_version, 1, 1)) 2499 nvme->n_auto_pst_supported = 2500 nvme->n_idctl->id_apsta.ap_sup == 0 ? B_FALSE : B_TRUE; 2501 2502 /* 2503 * Identify Namespaces 2504 */ 2505 nvme->n_namespace_count = nvme->n_idctl->id_nn; 2506 if (nvme->n_namespace_count > NVME_MINOR_MAX) { 2507 dev_err(nvme->n_dip, CE_WARN, 2508 "!too many namespaces: %d, limiting to %d\n", 2509 nvme->n_namespace_count, NVME_MINOR_MAX); 2510 nvme->n_namespace_count = NVME_MINOR_MAX; 2511 } 2512 2513 nvme->n_ns = kmem_zalloc(sizeof (nvme_namespace_t) * 2514 nvme->n_namespace_count, KM_SLEEP); 2515 2516 for (i = 0; i != nvme->n_namespace_count; i++) { 2517 mutex_init(&nvme->n_ns[i].ns_minor.nm_mutex, NULL, MUTEX_DRIVER, 2518 NULL); 2519 if (nvme_init_ns(nvme, i + 1) != DDI_SUCCESS) 2520 goto fail; 2521 } 2522 2523 /* 2524 * Try to set up MSI/MSI-X interrupts. 2525 */ 2526 if ((nvme->n_intr_types & (DDI_INTR_TYPE_MSI | DDI_INTR_TYPE_MSIX)) 2527 != 0) { 2528 nvme_release_interrupts(nvme); 2529 2530 nqueues = MIN(UINT16_MAX, ncpus); 2531 2532 if ((nvme_setup_interrupts(nvme, DDI_INTR_TYPE_MSIX, 2533 nqueues) != DDI_SUCCESS) && 2534 (nvme_setup_interrupts(nvme, DDI_INTR_TYPE_MSI, 2535 nqueues) != DDI_SUCCESS)) { 2536 dev_err(nvme->n_dip, CE_WARN, 2537 "!failed to setup MSI/MSI-X interrupts"); 2538 goto fail; 2539 } 2540 } 2541 2542 nqueues = nvme->n_intr_cnt; 2543 2544 /* 2545 * Create I/O queue pairs. 2546 */ 2547 2548 if (nvme_set_nqueues(nvme, &nqueues) != 0) { 2549 dev_err(nvme->n_dip, CE_WARN, 2550 "!failed to set number of I/O queues to %d", 2551 nvme->n_intr_cnt); 2552 goto fail; 2553 } 2554 2555 /* 2556 * Reallocate I/O queue array 2557 */ 2558 kmem_free(nvme->n_ioq, sizeof (nvme_qpair_t *)); 2559 nvme->n_ioq = kmem_zalloc(sizeof (nvme_qpair_t *) * 2560 (nqueues + 1), KM_SLEEP); 2561 nvme->n_ioq[0] = nvme->n_adminq; 2562 2563 nvme->n_ioq_count = nqueues; 2564 2565 /* 2566 * If we got less queues than we asked for we might as well give 2567 * some of the interrupt vectors back to the system. 2568 */ 2569 if (nvme->n_ioq_count < nvme->n_intr_cnt) { 2570 nvme_release_interrupts(nvme); 2571 2572 if (nvme_setup_interrupts(nvme, nvme->n_intr_type, 2573 nvme->n_ioq_count) != DDI_SUCCESS) { 2574 dev_err(nvme->n_dip, CE_WARN, 2575 "!failed to reduce number of interrupts"); 2576 goto fail; 2577 } 2578 } 2579 2580 /* 2581 * Alloc & register I/O queue pairs 2582 */ 2583 nvme->n_io_queue_len = 2584 MIN(nvme->n_io_queue_len, nvme->n_max_queue_entries); 2585 (void) ddi_prop_update_int(DDI_DEV_T_NONE, nvme->n_dip, "io-queue-len", 2586 nvme->n_io_queue_len); 2587 2588 for (i = 1; i != nvme->n_ioq_count + 1; i++) { 2589 if (nvme_alloc_qpair(nvme, nvme->n_io_queue_len, 2590 &nvme->n_ioq[i], i) != DDI_SUCCESS) { 2591 dev_err(nvme->n_dip, CE_WARN, 2592 "!unable to allocate I/O qpair %d", i); 2593 goto fail; 2594 } 2595 2596 if (nvme_create_io_qpair(nvme, nvme->n_ioq[i], i) != 0) { 2597 dev_err(nvme->n_dip, CE_WARN, 2598 "!unable to create I/O qpair %d", i); 2599 goto fail; 2600 } 2601 } 2602 2603 /* 2604 * Post more asynchronous events commands to reduce event reporting 2605 * latency as suggested by the spec. 2606 */ 2607 for (i = 1; i != nvme->n_async_event_limit; i++) 2608 nvme_async_event(nvme); 2609 2610 return (DDI_SUCCESS); 2611 2612 fail: 2613 (void) nvme_reset(nvme, B_FALSE); 2614 return (DDI_FAILURE); 2615 } 2616 2617 static uint_t 2618 nvme_intr(caddr_t arg1, caddr_t arg2) 2619 { 2620 /*LINTED: E_PTR_BAD_CAST_ALIGN*/ 2621 nvme_t *nvme = (nvme_t *)arg1; 2622 int inum = (int)(uintptr_t)arg2; 2623 int ccnt = 0; 2624 int qnum; 2625 nvme_cmd_t *cmd; 2626 2627 if (inum >= nvme->n_intr_cnt) 2628 return (DDI_INTR_UNCLAIMED); 2629 2630 if (nvme->n_dead) 2631 return (nvme->n_intr_type == DDI_INTR_TYPE_FIXED ? 2632 DDI_INTR_UNCLAIMED : DDI_INTR_CLAIMED); 2633 2634 /* 2635 * The interrupt vector a queue uses is calculated as queue_idx % 2636 * intr_cnt in nvme_create_io_qpair(). Iterate through the queue array 2637 * in steps of n_intr_cnt to process all queues using this vector. 2638 */ 2639 for (qnum = inum; 2640 qnum < nvme->n_ioq_count + 1 && nvme->n_ioq[qnum] != NULL; 2641 qnum += nvme->n_intr_cnt) { 2642 while ((cmd = nvme_retrieve_cmd(nvme, nvme->n_ioq[qnum]))) { 2643 taskq_dispatch_ent((taskq_t *)cmd->nc_nvme->n_cmd_taskq, 2644 cmd->nc_callback, cmd, TQ_NOSLEEP, &cmd->nc_tqent); 2645 ccnt++; 2646 } 2647 } 2648 2649 return (ccnt > 0 ? DDI_INTR_CLAIMED : DDI_INTR_UNCLAIMED); 2650 } 2651 2652 static void 2653 nvme_release_interrupts(nvme_t *nvme) 2654 { 2655 int i; 2656 2657 for (i = 0; i < nvme->n_intr_cnt; i++) { 2658 if (nvme->n_inth[i] == NULL) 2659 break; 2660 2661 if (nvme->n_intr_cap & DDI_INTR_FLAG_BLOCK) 2662 (void) ddi_intr_block_disable(&nvme->n_inth[i], 1); 2663 else 2664 (void) ddi_intr_disable(nvme->n_inth[i]); 2665 2666 (void) ddi_intr_remove_handler(nvme->n_inth[i]); 2667 (void) ddi_intr_free(nvme->n_inth[i]); 2668 } 2669 2670 kmem_free(nvme->n_inth, nvme->n_inth_sz); 2671 nvme->n_inth = NULL; 2672 nvme->n_inth_sz = 0; 2673 2674 nvme->n_progress &= ~NVME_INTERRUPTS; 2675 } 2676 2677 static int 2678 nvme_setup_interrupts(nvme_t *nvme, int intr_type, int nqpairs) 2679 { 2680 int nintrs, navail, count; 2681 int ret; 2682 int i; 2683 2684 if (nvme->n_intr_types == 0) { 2685 ret = ddi_intr_get_supported_types(nvme->n_dip, 2686 &nvme->n_intr_types); 2687 if (ret != DDI_SUCCESS) { 2688 dev_err(nvme->n_dip, CE_WARN, 2689 "!%s: ddi_intr_get_supported types failed", 2690 __func__); 2691 return (ret); 2692 } 2693 #ifdef __x86 2694 if (get_hwenv() == HW_VMWARE) 2695 nvme->n_intr_types &= ~DDI_INTR_TYPE_MSIX; 2696 #endif 2697 } 2698 2699 if ((nvme->n_intr_types & intr_type) == 0) 2700 return (DDI_FAILURE); 2701 2702 ret = ddi_intr_get_nintrs(nvme->n_dip, intr_type, &nintrs); 2703 if (ret != DDI_SUCCESS) { 2704 dev_err(nvme->n_dip, CE_WARN, "!%s: ddi_intr_get_nintrs failed", 2705 __func__); 2706 return (ret); 2707 } 2708 2709 ret = ddi_intr_get_navail(nvme->n_dip, intr_type, &navail); 2710 if (ret != DDI_SUCCESS) { 2711 dev_err(nvme->n_dip, CE_WARN, "!%s: ddi_intr_get_navail failed", 2712 __func__); 2713 return (ret); 2714 } 2715 2716 /* We want at most one interrupt per queue pair. */ 2717 if (navail > nqpairs) 2718 navail = nqpairs; 2719 2720 nvme->n_inth_sz = sizeof (ddi_intr_handle_t) * navail; 2721 nvme->n_inth = kmem_zalloc(nvme->n_inth_sz, KM_SLEEP); 2722 2723 ret = ddi_intr_alloc(nvme->n_dip, nvme->n_inth, intr_type, 0, navail, 2724 &count, 0); 2725 if (ret != DDI_SUCCESS) { 2726 dev_err(nvme->n_dip, CE_WARN, "!%s: ddi_intr_alloc failed", 2727 __func__); 2728 goto fail; 2729 } 2730 2731 nvme->n_intr_cnt = count; 2732 2733 ret = ddi_intr_get_pri(nvme->n_inth[0], &nvme->n_intr_pri); 2734 if (ret != DDI_SUCCESS) { 2735 dev_err(nvme->n_dip, CE_WARN, "!%s: ddi_intr_get_pri failed", 2736 __func__); 2737 goto fail; 2738 } 2739 2740 for (i = 0; i < count; i++) { 2741 ret = ddi_intr_add_handler(nvme->n_inth[i], nvme_intr, 2742 (void *)nvme, (void *)(uintptr_t)i); 2743 if (ret != DDI_SUCCESS) { 2744 dev_err(nvme->n_dip, CE_WARN, 2745 "!%s: ddi_intr_add_handler failed", __func__); 2746 goto fail; 2747 } 2748 } 2749 2750 (void) ddi_intr_get_cap(nvme->n_inth[0], &nvme->n_intr_cap); 2751 2752 for (i = 0; i < count; i++) { 2753 if (nvme->n_intr_cap & DDI_INTR_FLAG_BLOCK) 2754 ret = ddi_intr_block_enable(&nvme->n_inth[i], 1); 2755 else 2756 ret = ddi_intr_enable(nvme->n_inth[i]); 2757 2758 if (ret != DDI_SUCCESS) { 2759 dev_err(nvme->n_dip, CE_WARN, 2760 "!%s: enabling interrupt %d failed", __func__, i); 2761 goto fail; 2762 } 2763 } 2764 2765 nvme->n_intr_type = intr_type; 2766 2767 nvme->n_progress |= NVME_INTERRUPTS; 2768 2769 return (DDI_SUCCESS); 2770 2771 fail: 2772 nvme_release_interrupts(nvme); 2773 2774 return (ret); 2775 } 2776 2777 static int 2778 nvme_fm_errcb(dev_info_t *dip, ddi_fm_error_t *fm_error, const void *arg) 2779 { 2780 _NOTE(ARGUNUSED(arg)); 2781 2782 pci_ereport_post(dip, fm_error, NULL); 2783 return (fm_error->fme_status); 2784 } 2785 2786 static int 2787 nvme_attach(dev_info_t *dip, ddi_attach_cmd_t cmd) 2788 { 2789 nvme_t *nvme; 2790 int instance; 2791 int nregs; 2792 off_t regsize; 2793 int i; 2794 char name[32]; 2795 2796 if (cmd != DDI_ATTACH) 2797 return (DDI_FAILURE); 2798 2799 instance = ddi_get_instance(dip); 2800 2801 if (ddi_soft_state_zalloc(nvme_state, instance) != DDI_SUCCESS) 2802 return (DDI_FAILURE); 2803 2804 nvme = ddi_get_soft_state(nvme_state, instance); 2805 ddi_set_driver_private(dip, nvme); 2806 nvme->n_dip = dip; 2807 2808 mutex_init(&nvme->n_minor.nm_mutex, NULL, MUTEX_DRIVER, NULL); 2809 2810 nvme->n_strict_version = ddi_prop_get_int(DDI_DEV_T_ANY, dip, 2811 DDI_PROP_DONTPASS, "strict-version", 1) == 1 ? B_TRUE : B_FALSE; 2812 nvme->n_ignore_unknown_vendor_status = ddi_prop_get_int(DDI_DEV_T_ANY, 2813 dip, DDI_PROP_DONTPASS, "ignore-unknown-vendor-status", 0) == 1 ? 2814 B_TRUE : B_FALSE; 2815 nvme->n_admin_queue_len = ddi_prop_get_int(DDI_DEV_T_ANY, dip, 2816 DDI_PROP_DONTPASS, "admin-queue-len", NVME_DEFAULT_ADMIN_QUEUE_LEN); 2817 nvme->n_io_queue_len = ddi_prop_get_int(DDI_DEV_T_ANY, dip, 2818 DDI_PROP_DONTPASS, "io-queue-len", NVME_DEFAULT_IO_QUEUE_LEN); 2819 nvme->n_async_event_limit = ddi_prop_get_int(DDI_DEV_T_ANY, dip, 2820 DDI_PROP_DONTPASS, "async-event-limit", 2821 NVME_DEFAULT_ASYNC_EVENT_LIMIT); 2822 nvme->n_write_cache_enabled = ddi_prop_get_int(DDI_DEV_T_ANY, dip, 2823 DDI_PROP_DONTPASS, "volatile-write-cache-enable", 1) != 0 ? 2824 B_TRUE : B_FALSE; 2825 nvme->n_min_block_size = ddi_prop_get_int(DDI_DEV_T_ANY, dip, 2826 DDI_PROP_DONTPASS, "min-phys-block-size", 2827 NVME_DEFAULT_MIN_BLOCK_SIZE); 2828 2829 if (!ISP2(nvme->n_min_block_size) || 2830 (nvme->n_min_block_size < NVME_DEFAULT_MIN_BLOCK_SIZE)) { 2831 dev_err(dip, CE_WARN, "!min-phys-block-size %s, " 2832 "using default %d", ISP2(nvme->n_min_block_size) ? 2833 "too low" : "not a power of 2", 2834 NVME_DEFAULT_MIN_BLOCK_SIZE); 2835 nvme->n_min_block_size = NVME_DEFAULT_MIN_BLOCK_SIZE; 2836 } 2837 2838 if (nvme->n_admin_queue_len < NVME_MIN_ADMIN_QUEUE_LEN) 2839 nvme->n_admin_queue_len = NVME_MIN_ADMIN_QUEUE_LEN; 2840 else if (nvme->n_admin_queue_len > NVME_MAX_ADMIN_QUEUE_LEN) 2841 nvme->n_admin_queue_len = NVME_MAX_ADMIN_QUEUE_LEN; 2842 2843 if (nvme->n_io_queue_len < NVME_MIN_IO_QUEUE_LEN) 2844 nvme->n_io_queue_len = NVME_MIN_IO_QUEUE_LEN; 2845 2846 if (nvme->n_async_event_limit < 1) 2847 nvme->n_async_event_limit = NVME_DEFAULT_ASYNC_EVENT_LIMIT; 2848 2849 nvme->n_reg_acc_attr = nvme_reg_acc_attr; 2850 nvme->n_queue_dma_attr = nvme_queue_dma_attr; 2851 nvme->n_prp_dma_attr = nvme_prp_dma_attr; 2852 nvme->n_sgl_dma_attr = nvme_sgl_dma_attr; 2853 2854 /* 2855 * Setup FMA support. 2856 */ 2857 nvme->n_fm_cap = ddi_getprop(DDI_DEV_T_ANY, dip, 2858 DDI_PROP_CANSLEEP | DDI_PROP_DONTPASS, "fm-capable", 2859 DDI_FM_EREPORT_CAPABLE | DDI_FM_ACCCHK_CAPABLE | 2860 DDI_FM_DMACHK_CAPABLE | DDI_FM_ERRCB_CAPABLE); 2861 2862 ddi_fm_init(dip, &nvme->n_fm_cap, &nvme->n_fm_ibc); 2863 2864 if (nvme->n_fm_cap) { 2865 if (nvme->n_fm_cap & DDI_FM_ACCCHK_CAPABLE) 2866 nvme->n_reg_acc_attr.devacc_attr_access = 2867 DDI_FLAGERR_ACC; 2868 2869 if (nvme->n_fm_cap & DDI_FM_DMACHK_CAPABLE) { 2870 nvme->n_prp_dma_attr.dma_attr_flags |= DDI_DMA_FLAGERR; 2871 nvme->n_sgl_dma_attr.dma_attr_flags |= DDI_DMA_FLAGERR; 2872 } 2873 2874 if (DDI_FM_EREPORT_CAP(nvme->n_fm_cap) || 2875 DDI_FM_ERRCB_CAP(nvme->n_fm_cap)) 2876 pci_ereport_setup(dip); 2877 2878 if (DDI_FM_ERRCB_CAP(nvme->n_fm_cap)) 2879 ddi_fm_handler_register(dip, nvme_fm_errcb, 2880 (void *)nvme); 2881 } 2882 2883 nvme->n_progress |= NVME_FMA_INIT; 2884 2885 /* 2886 * The spec defines several register sets. Only the controller 2887 * registers (set 1) are currently used. 2888 */ 2889 if (ddi_dev_nregs(dip, &nregs) == DDI_FAILURE || 2890 nregs < 2 || 2891 ddi_dev_regsize(dip, 1, ®size) == DDI_FAILURE) 2892 goto fail; 2893 2894 if (ddi_regs_map_setup(dip, 1, &nvme->n_regs, 0, regsize, 2895 &nvme->n_reg_acc_attr, &nvme->n_regh) != DDI_SUCCESS) { 2896 dev_err(dip, CE_WARN, "!failed to map regset 1"); 2897 goto fail; 2898 } 2899 2900 nvme->n_progress |= NVME_REGS_MAPPED; 2901 2902 /* 2903 * Create taskq for command completion. 2904 */ 2905 (void) snprintf(name, sizeof (name), "%s%d_cmd_taskq", 2906 ddi_driver_name(dip), ddi_get_instance(dip)); 2907 nvme->n_cmd_taskq = ddi_taskq_create(dip, name, MIN(UINT16_MAX, ncpus), 2908 TASKQ_DEFAULTPRI, 0); 2909 if (nvme->n_cmd_taskq == NULL) { 2910 dev_err(dip, CE_WARN, "!failed to create cmd taskq"); 2911 goto fail; 2912 } 2913 2914 /* 2915 * Create PRP DMA cache 2916 */ 2917 (void) snprintf(name, sizeof (name), "%s%d_prp_cache", 2918 ddi_driver_name(dip), ddi_get_instance(dip)); 2919 nvme->n_prp_cache = kmem_cache_create(name, sizeof (nvme_dma_t), 2920 0, nvme_prp_dma_constructor, nvme_prp_dma_destructor, 2921 NULL, (void *)nvme, NULL, 0); 2922 2923 if (nvme_init(nvme) != DDI_SUCCESS) 2924 goto fail; 2925 2926 /* 2927 * Attach the blkdev driver for each namespace. 2928 */ 2929 for (i = 0; i != nvme->n_namespace_count; i++) { 2930 if (ddi_create_minor_node(nvme->n_dip, nvme->n_ns[i].ns_name, 2931 S_IFCHR, NVME_MINOR(ddi_get_instance(nvme->n_dip), i + 1), 2932 DDI_NT_NVME_ATTACHMENT_POINT, 0) != DDI_SUCCESS) { 2933 dev_err(dip, CE_WARN, 2934 "!failed to create minor node for namespace %d", i); 2935 goto fail; 2936 } 2937 2938 if (nvme->n_ns[i].ns_ignore) 2939 continue; 2940 2941 nvme->n_ns[i].ns_bd_hdl = bd_alloc_handle(&nvme->n_ns[i], 2942 &nvme_bd_ops, &nvme->n_prp_dma_attr, KM_SLEEP); 2943 2944 if (nvme->n_ns[i].ns_bd_hdl == NULL) { 2945 dev_err(dip, CE_WARN, 2946 "!failed to get blkdev handle for namespace %d", i); 2947 goto fail; 2948 } 2949 2950 if (bd_attach_handle(dip, nvme->n_ns[i].ns_bd_hdl) 2951 != DDI_SUCCESS) { 2952 dev_err(dip, CE_WARN, 2953 "!failed to attach blkdev handle for namespace %d", 2954 i); 2955 goto fail; 2956 } 2957 } 2958 2959 if (ddi_create_minor_node(dip, "devctl", S_IFCHR, 2960 NVME_MINOR(ddi_get_instance(dip), 0), DDI_NT_NVME_NEXUS, 0) 2961 != DDI_SUCCESS) { 2962 dev_err(dip, CE_WARN, "nvme_attach: " 2963 "cannot create devctl minor node"); 2964 goto fail; 2965 } 2966 2967 return (DDI_SUCCESS); 2968 2969 fail: 2970 /* attach successful anyway so that FMA can retire the device */ 2971 if (nvme->n_dead) 2972 return (DDI_SUCCESS); 2973 2974 (void) nvme_detach(dip, DDI_DETACH); 2975 2976 return (DDI_FAILURE); 2977 } 2978 2979 static int 2980 nvme_detach(dev_info_t *dip, ddi_detach_cmd_t cmd) 2981 { 2982 int instance, i; 2983 nvme_t *nvme; 2984 2985 if (cmd != DDI_DETACH) 2986 return (DDI_FAILURE); 2987 2988 instance = ddi_get_instance(dip); 2989 2990 nvme = ddi_get_soft_state(nvme_state, instance); 2991 2992 if (nvme == NULL) 2993 return (DDI_FAILURE); 2994 2995 ddi_remove_minor_node(dip, "devctl"); 2996 mutex_destroy(&nvme->n_minor.nm_mutex); 2997 2998 if (nvme->n_ns) { 2999 for (i = 0; i != nvme->n_namespace_count; i++) { 3000 ddi_remove_minor_node(dip, nvme->n_ns[i].ns_name); 3001 mutex_destroy(&nvme->n_ns[i].ns_minor.nm_mutex); 3002 3003 if (nvme->n_ns[i].ns_bd_hdl) { 3004 (void) bd_detach_handle( 3005 nvme->n_ns[i].ns_bd_hdl); 3006 bd_free_handle(nvme->n_ns[i].ns_bd_hdl); 3007 } 3008 3009 if (nvme->n_ns[i].ns_idns) 3010 kmem_free(nvme->n_ns[i].ns_idns, 3011 sizeof (nvme_identify_nsid_t)); 3012 if (nvme->n_ns[i].ns_devid) 3013 strfree(nvme->n_ns[i].ns_devid); 3014 } 3015 3016 kmem_free(nvme->n_ns, sizeof (nvme_namespace_t) * 3017 nvme->n_namespace_count); 3018 } 3019 3020 if (nvme->n_progress & NVME_INTERRUPTS) 3021 nvme_release_interrupts(nvme); 3022 3023 if (nvme->n_cmd_taskq) 3024 ddi_taskq_wait(nvme->n_cmd_taskq); 3025 3026 if (nvme->n_ioq_count > 0) { 3027 for (i = 1; i != nvme->n_ioq_count + 1; i++) { 3028 if (nvme->n_ioq[i] != NULL) { 3029 /* TODO: send destroy queue commands */ 3030 nvme_free_qpair(nvme->n_ioq[i]); 3031 } 3032 } 3033 3034 kmem_free(nvme->n_ioq, sizeof (nvme_qpair_t *) * 3035 (nvme->n_ioq_count + 1)); 3036 } 3037 3038 if (nvme->n_prp_cache != NULL) { 3039 kmem_cache_destroy(nvme->n_prp_cache); 3040 } 3041 3042 if (nvme->n_progress & NVME_REGS_MAPPED) { 3043 nvme_shutdown(nvme, NVME_CC_SHN_NORMAL, B_FALSE); 3044 (void) nvme_reset(nvme, B_FALSE); 3045 } 3046 3047 if (nvme->n_cmd_taskq) 3048 ddi_taskq_destroy(nvme->n_cmd_taskq); 3049 3050 if (nvme->n_progress & NVME_CTRL_LIMITS) 3051 sema_destroy(&nvme->n_abort_sema); 3052 3053 if (nvme->n_progress & NVME_ADMIN_QUEUE) 3054 nvme_free_qpair(nvme->n_adminq); 3055 3056 if (nvme->n_idctl) 3057 kmem_free(nvme->n_idctl, NVME_IDENTIFY_BUFSIZE); 3058 3059 if (nvme->n_progress & NVME_REGS_MAPPED) 3060 ddi_regs_map_free(&nvme->n_regh); 3061 3062 if (nvme->n_progress & NVME_FMA_INIT) { 3063 if (DDI_FM_ERRCB_CAP(nvme->n_fm_cap)) 3064 ddi_fm_handler_unregister(nvme->n_dip); 3065 3066 if (DDI_FM_EREPORT_CAP(nvme->n_fm_cap) || 3067 DDI_FM_ERRCB_CAP(nvme->n_fm_cap)) 3068 pci_ereport_teardown(nvme->n_dip); 3069 3070 ddi_fm_fini(nvme->n_dip); 3071 } 3072 3073 if (nvme->n_vendor != NULL) 3074 strfree(nvme->n_vendor); 3075 3076 if (nvme->n_product != NULL) 3077 strfree(nvme->n_product); 3078 3079 ddi_soft_state_free(nvme_state, instance); 3080 3081 return (DDI_SUCCESS); 3082 } 3083 3084 static int 3085 nvme_quiesce(dev_info_t *dip) 3086 { 3087 int instance; 3088 nvme_t *nvme; 3089 3090 instance = ddi_get_instance(dip); 3091 3092 nvme = ddi_get_soft_state(nvme_state, instance); 3093 3094 if (nvme == NULL) 3095 return (DDI_FAILURE); 3096 3097 nvme_shutdown(nvme, NVME_CC_SHN_ABRUPT, B_TRUE); 3098 3099 (void) nvme_reset(nvme, B_TRUE); 3100 3101 return (DDI_FAILURE); 3102 } 3103 3104 static int 3105 nvme_fill_prp(nvme_cmd_t *cmd, bd_xfer_t *xfer) 3106 { 3107 nvme_t *nvme = cmd->nc_nvme; 3108 int nprp_page, nprp; 3109 uint64_t *prp; 3110 3111 if (xfer->x_ndmac == 0) 3112 return (DDI_FAILURE); 3113 3114 cmd->nc_sqe.sqe_dptr.d_prp[0] = xfer->x_dmac.dmac_laddress; 3115 ddi_dma_nextcookie(xfer->x_dmah, &xfer->x_dmac); 3116 3117 if (xfer->x_ndmac == 1) { 3118 cmd->nc_sqe.sqe_dptr.d_prp[1] = 0; 3119 return (DDI_SUCCESS); 3120 } else if (xfer->x_ndmac == 2) { 3121 cmd->nc_sqe.sqe_dptr.d_prp[1] = xfer->x_dmac.dmac_laddress; 3122 return (DDI_SUCCESS); 3123 } 3124 3125 xfer->x_ndmac--; 3126 3127 nprp_page = nvme->n_pagesize / sizeof (uint64_t) - 1; 3128 ASSERT(nprp_page > 0); 3129 nprp = (xfer->x_ndmac + nprp_page - 1) / nprp_page; 3130 3131 /* 3132 * We currently don't support chained PRPs and set up our DMA 3133 * attributes to reflect that. If we still get an I/O request 3134 * that needs a chained PRP something is very wrong. 3135 */ 3136 VERIFY(nprp == 1); 3137 3138 cmd->nc_dma = kmem_cache_alloc(nvme->n_prp_cache, KM_SLEEP); 3139 bzero(cmd->nc_dma->nd_memp, cmd->nc_dma->nd_len); 3140 3141 cmd->nc_sqe.sqe_dptr.d_prp[1] = cmd->nc_dma->nd_cookie.dmac_laddress; 3142 3143 /*LINTED: E_PTR_BAD_CAST_ALIGN*/ 3144 for (prp = (uint64_t *)cmd->nc_dma->nd_memp; 3145 xfer->x_ndmac > 0; 3146 prp++, xfer->x_ndmac--) { 3147 *prp = xfer->x_dmac.dmac_laddress; 3148 ddi_dma_nextcookie(xfer->x_dmah, &xfer->x_dmac); 3149 } 3150 3151 (void) ddi_dma_sync(cmd->nc_dma->nd_dmah, 0, cmd->nc_dma->nd_len, 3152 DDI_DMA_SYNC_FORDEV); 3153 return (DDI_SUCCESS); 3154 } 3155 3156 static nvme_cmd_t * 3157 nvme_create_nvm_cmd(nvme_namespace_t *ns, uint8_t opc, bd_xfer_t *xfer) 3158 { 3159 nvme_t *nvme = ns->ns_nvme; 3160 nvme_cmd_t *cmd; 3161 3162 /* 3163 * Blkdev only sets BD_XFER_POLL when dumping, so don't sleep. 3164 */ 3165 cmd = nvme_alloc_cmd(nvme, (xfer->x_flags & BD_XFER_POLL) ? 3166 KM_NOSLEEP : KM_SLEEP); 3167 3168 if (cmd == NULL) 3169 return (NULL); 3170 3171 cmd->nc_sqe.sqe_opc = opc; 3172 cmd->nc_callback = nvme_bd_xfer_done; 3173 cmd->nc_xfer = xfer; 3174 3175 switch (opc) { 3176 case NVME_OPC_NVM_WRITE: 3177 case NVME_OPC_NVM_READ: 3178 VERIFY(xfer->x_nblks <= 0x10000); 3179 3180 cmd->nc_sqe.sqe_nsid = ns->ns_id; 3181 3182 cmd->nc_sqe.sqe_cdw10 = xfer->x_blkno & 0xffffffffu; 3183 cmd->nc_sqe.sqe_cdw11 = (xfer->x_blkno >> 32); 3184 cmd->nc_sqe.sqe_cdw12 = (uint16_t)(xfer->x_nblks - 1); 3185 3186 if (nvme_fill_prp(cmd, xfer) != DDI_SUCCESS) 3187 goto fail; 3188 break; 3189 3190 case NVME_OPC_NVM_FLUSH: 3191 cmd->nc_sqe.sqe_nsid = ns->ns_id; 3192 break; 3193 3194 default: 3195 goto fail; 3196 } 3197 3198 return (cmd); 3199 3200 fail: 3201 nvme_free_cmd(cmd); 3202 return (NULL); 3203 } 3204 3205 static void 3206 nvme_bd_xfer_done(void *arg) 3207 { 3208 nvme_cmd_t *cmd = arg; 3209 bd_xfer_t *xfer = cmd->nc_xfer; 3210 int error = 0; 3211 3212 error = nvme_check_cmd_status(cmd); 3213 nvme_free_cmd(cmd); 3214 3215 bd_xfer_done(xfer, error); 3216 } 3217 3218 static void 3219 nvme_bd_driveinfo(void *arg, bd_drive_t *drive) 3220 { 3221 nvme_namespace_t *ns = arg; 3222 nvme_t *nvme = ns->ns_nvme; 3223 3224 /* 3225 * blkdev maintains one queue size per instance (namespace), 3226 * but all namespace share the I/O queues. 3227 * TODO: need to figure out a sane default, or use per-NS I/O queues, 3228 * or change blkdev to handle EAGAIN 3229 */ 3230 drive->d_qsize = nvme->n_ioq_count * nvme->n_io_queue_len 3231 / nvme->n_namespace_count; 3232 3233 /* 3234 * d_maxxfer is not set, which means the value is taken from the DMA 3235 * attributes specified to bd_alloc_handle. 3236 */ 3237 3238 drive->d_removable = B_FALSE; 3239 drive->d_hotpluggable = B_FALSE; 3240 3241 bcopy(ns->ns_eui64, drive->d_eui64, sizeof (drive->d_eui64)); 3242 drive->d_target = ns->ns_id; 3243 drive->d_lun = 0; 3244 3245 drive->d_model = nvme->n_idctl->id_model; 3246 drive->d_model_len = sizeof (nvme->n_idctl->id_model); 3247 drive->d_vendor = nvme->n_vendor; 3248 drive->d_vendor_len = strlen(nvme->n_vendor); 3249 drive->d_product = nvme->n_product; 3250 drive->d_product_len = strlen(nvme->n_product); 3251 drive->d_serial = nvme->n_idctl->id_serial; 3252 drive->d_serial_len = sizeof (nvme->n_idctl->id_serial); 3253 drive->d_revision = nvme->n_idctl->id_fwrev; 3254 drive->d_revision_len = sizeof (nvme->n_idctl->id_fwrev); 3255 } 3256 3257 static int 3258 nvme_bd_mediainfo(void *arg, bd_media_t *media) 3259 { 3260 nvme_namespace_t *ns = arg; 3261 3262 media->m_nblks = ns->ns_block_count; 3263 media->m_blksize = ns->ns_block_size; 3264 media->m_readonly = B_FALSE; 3265 media->m_solidstate = B_TRUE; 3266 3267 media->m_pblksize = ns->ns_best_block_size; 3268 3269 return (0); 3270 } 3271 3272 static int 3273 nvme_bd_cmd(nvme_namespace_t *ns, bd_xfer_t *xfer, uint8_t opc) 3274 { 3275 nvme_t *nvme = ns->ns_nvme; 3276 nvme_cmd_t *cmd; 3277 nvme_qpair_t *ioq; 3278 boolean_t poll; 3279 int ret; 3280 3281 if (nvme->n_dead) 3282 return (EIO); 3283 3284 cmd = nvme_create_nvm_cmd(ns, opc, xfer); 3285 if (cmd == NULL) 3286 return (ENOMEM); 3287 3288 cmd->nc_sqid = (CPU->cpu_id % nvme->n_ioq_count) + 1; 3289 ASSERT(cmd->nc_sqid <= nvme->n_ioq_count); 3290 ioq = nvme->n_ioq[cmd->nc_sqid]; 3291 3292 /* 3293 * Get the polling flag before submitting the command. The command may 3294 * complete immediately after it was submitted, which means we must 3295 * treat both cmd and xfer as if they have been freed already. 3296 */ 3297 poll = (xfer->x_flags & BD_XFER_POLL) != 0; 3298 3299 ret = nvme_submit_io_cmd(ioq, cmd); 3300 3301 if (ret != 0) 3302 return (ret); 3303 3304 if (!poll) 3305 return (0); 3306 3307 do { 3308 cmd = nvme_retrieve_cmd(nvme, ioq); 3309 if (cmd != NULL) 3310 nvme_bd_xfer_done(cmd); 3311 else 3312 drv_usecwait(10); 3313 } while (ioq->nq_active_cmds != 0); 3314 3315 return (0); 3316 } 3317 3318 static int 3319 nvme_bd_read(void *arg, bd_xfer_t *xfer) 3320 { 3321 nvme_namespace_t *ns = arg; 3322 3323 return (nvme_bd_cmd(ns, xfer, NVME_OPC_NVM_READ)); 3324 } 3325 3326 static int 3327 nvme_bd_write(void *arg, bd_xfer_t *xfer) 3328 { 3329 nvme_namespace_t *ns = arg; 3330 3331 return (nvme_bd_cmd(ns, xfer, NVME_OPC_NVM_WRITE)); 3332 } 3333 3334 static int 3335 nvme_bd_sync(void *arg, bd_xfer_t *xfer) 3336 { 3337 nvme_namespace_t *ns = arg; 3338 3339 if (ns->ns_nvme->n_dead) 3340 return (EIO); 3341 3342 /* 3343 * If the volatile write cache is not present or not enabled the FLUSH 3344 * command is a no-op, so we can take a shortcut here. 3345 */ 3346 if (!ns->ns_nvme->n_write_cache_present) { 3347 bd_xfer_done(xfer, ENOTSUP); 3348 return (0); 3349 } 3350 3351 if (!ns->ns_nvme->n_write_cache_enabled) { 3352 bd_xfer_done(xfer, 0); 3353 return (0); 3354 } 3355 3356 return (nvme_bd_cmd(ns, xfer, NVME_OPC_NVM_FLUSH)); 3357 } 3358 3359 static int 3360 nvme_bd_devid(void *arg, dev_info_t *devinfo, ddi_devid_t *devid) 3361 { 3362 nvme_namespace_t *ns = arg; 3363 3364 /*LINTED: E_BAD_PTR_CAST_ALIGN*/ 3365 if (*(uint64_t *)ns->ns_eui64 != 0) { 3366 return (ddi_devid_init(devinfo, DEVID_SCSI3_WWN, 3367 sizeof (ns->ns_eui64), ns->ns_eui64, devid)); 3368 } else { 3369 return (ddi_devid_init(devinfo, DEVID_ENCAP, 3370 strlen(ns->ns_devid), ns->ns_devid, devid)); 3371 } 3372 } 3373 3374 static int 3375 nvme_open(dev_t *devp, int flag, int otyp, cred_t *cred_p) 3376 { 3377 #ifndef __lock_lint 3378 _NOTE(ARGUNUSED(cred_p)); 3379 #endif 3380 minor_t minor = getminor(*devp); 3381 nvme_t *nvme = ddi_get_soft_state(nvme_state, NVME_MINOR_INST(minor)); 3382 int nsid = NVME_MINOR_NSID(minor); 3383 nvme_minor_state_t *nm; 3384 int rv = 0; 3385 3386 if (otyp != OTYP_CHR) 3387 return (EINVAL); 3388 3389 if (nvme == NULL) 3390 return (ENXIO); 3391 3392 if (nsid > nvme->n_namespace_count) 3393 return (ENXIO); 3394 3395 if (nvme->n_dead) 3396 return (EIO); 3397 3398 nm = nsid == 0 ? &nvme->n_minor : &nvme->n_ns[nsid - 1].ns_minor; 3399 3400 mutex_enter(&nm->nm_mutex); 3401 if (nm->nm_oexcl) { 3402 rv = EBUSY; 3403 goto out; 3404 } 3405 3406 if (flag & FEXCL) { 3407 if (nm->nm_ocnt != 0) { 3408 rv = EBUSY; 3409 goto out; 3410 } 3411 nm->nm_oexcl = B_TRUE; 3412 } 3413 3414 nm->nm_ocnt++; 3415 3416 out: 3417 mutex_exit(&nm->nm_mutex); 3418 return (rv); 3419 3420 } 3421 3422 static int 3423 nvme_close(dev_t dev, int flag, int otyp, cred_t *cred_p) 3424 { 3425 #ifndef __lock_lint 3426 _NOTE(ARGUNUSED(cred_p)); 3427 _NOTE(ARGUNUSED(flag)); 3428 #endif 3429 minor_t minor = getminor(dev); 3430 nvme_t *nvme = ddi_get_soft_state(nvme_state, NVME_MINOR_INST(minor)); 3431 int nsid = NVME_MINOR_NSID(minor); 3432 nvme_minor_state_t *nm; 3433 3434 if (otyp != OTYP_CHR) 3435 return (ENXIO); 3436 3437 if (nvme == NULL) 3438 return (ENXIO); 3439 3440 if (nsid > nvme->n_namespace_count) 3441 return (ENXIO); 3442 3443 nm = nsid == 0 ? &nvme->n_minor : &nvme->n_ns[nsid - 1].ns_minor; 3444 3445 mutex_enter(&nm->nm_mutex); 3446 if (nm->nm_oexcl) 3447 nm->nm_oexcl = B_FALSE; 3448 3449 ASSERT(nm->nm_ocnt > 0); 3450 nm->nm_ocnt--; 3451 mutex_exit(&nm->nm_mutex); 3452 3453 return (0); 3454 } 3455 3456 static int 3457 nvme_ioctl_identify(nvme_t *nvme, int nsid, nvme_ioctl_t *nioc, int mode, 3458 cred_t *cred_p) 3459 { 3460 _NOTE(ARGUNUSED(cred_p)); 3461 int rv = 0; 3462 void *idctl; 3463 3464 if ((mode & FREAD) == 0) 3465 return (EPERM); 3466 3467 if (nioc->n_len < NVME_IDENTIFY_BUFSIZE) 3468 return (EINVAL); 3469 3470 if ((rv = nvme_identify(nvme, nsid, (void **)&idctl)) != 0) 3471 return (rv); 3472 3473 if (ddi_copyout(idctl, (void *)nioc->n_buf, NVME_IDENTIFY_BUFSIZE, mode) 3474 != 0) 3475 rv = EFAULT; 3476 3477 kmem_free(idctl, NVME_IDENTIFY_BUFSIZE); 3478 3479 return (rv); 3480 } 3481 3482 static int 3483 nvme_ioctl_capabilities(nvme_t *nvme, int nsid, nvme_ioctl_t *nioc, 3484 int mode, cred_t *cred_p) 3485 { 3486 _NOTE(ARGUNUSED(nsid, cred_p)); 3487 int rv = 0; 3488 nvme_reg_cap_t cap = { 0 }; 3489 nvme_capabilities_t nc; 3490 3491 if ((mode & FREAD) == 0) 3492 return (EPERM); 3493 3494 if (nioc->n_len < sizeof (nc)) 3495 return (EINVAL); 3496 3497 cap.r = nvme_get64(nvme, NVME_REG_CAP); 3498 3499 /* 3500 * The MPSMIN and MPSMAX fields in the CAP register use 0 to 3501 * specify the base page size of 4k (1<<12), so add 12 here to 3502 * get the real page size value. 3503 */ 3504 nc.mpsmax = 1 << (12 + cap.b.cap_mpsmax); 3505 nc.mpsmin = 1 << (12 + cap.b.cap_mpsmin); 3506 3507 if (ddi_copyout(&nc, (void *)nioc->n_buf, sizeof (nc), mode) != 0) 3508 rv = EFAULT; 3509 3510 return (rv); 3511 } 3512 3513 static int 3514 nvme_ioctl_get_logpage(nvme_t *nvme, int nsid, nvme_ioctl_t *nioc, 3515 int mode, cred_t *cred_p) 3516 { 3517 _NOTE(ARGUNUSED(cred_p)); 3518 void *log = NULL; 3519 size_t bufsize = 0; 3520 int rv = 0; 3521 3522 if ((mode & FREAD) == 0) 3523 return (EPERM); 3524 3525 switch (nioc->n_arg) { 3526 case NVME_LOGPAGE_ERROR: 3527 if (nsid != 0) 3528 return (EINVAL); 3529 break; 3530 case NVME_LOGPAGE_HEALTH: 3531 if (nsid != 0 && nvme->n_idctl->id_lpa.lp_smart == 0) 3532 return (EINVAL); 3533 3534 if (nsid == 0) 3535 nsid = (uint32_t)-1; 3536 3537 break; 3538 case NVME_LOGPAGE_FWSLOT: 3539 if (nsid != 0) 3540 return (EINVAL); 3541 break; 3542 default: 3543 return (EINVAL); 3544 } 3545 3546 if (nvme_get_logpage(nvme, &log, &bufsize, nioc->n_arg, nsid) 3547 != DDI_SUCCESS) 3548 return (EIO); 3549 3550 if (nioc->n_len < bufsize) { 3551 kmem_free(log, bufsize); 3552 return (EINVAL); 3553 } 3554 3555 if (ddi_copyout(log, (void *)nioc->n_buf, bufsize, mode) != 0) 3556 rv = EFAULT; 3557 3558 nioc->n_len = bufsize; 3559 kmem_free(log, bufsize); 3560 3561 return (rv); 3562 } 3563 3564 static int 3565 nvme_ioctl_get_features(nvme_t *nvme, int nsid, nvme_ioctl_t *nioc, 3566 int mode, cred_t *cred_p) 3567 { 3568 _NOTE(ARGUNUSED(cred_p)); 3569 void *buf = NULL; 3570 size_t bufsize = 0; 3571 uint32_t res = 0; 3572 uint8_t feature; 3573 int rv = 0; 3574 3575 if ((mode & FREAD) == 0) 3576 return (EPERM); 3577 3578 if ((nioc->n_arg >> 32) > 0xff) 3579 return (EINVAL); 3580 3581 feature = (uint8_t)(nioc->n_arg >> 32); 3582 3583 switch (feature) { 3584 case NVME_FEAT_ARBITRATION: 3585 case NVME_FEAT_POWER_MGMT: 3586 case NVME_FEAT_TEMPERATURE: 3587 case NVME_FEAT_ERROR: 3588 case NVME_FEAT_NQUEUES: 3589 case NVME_FEAT_INTR_COAL: 3590 case NVME_FEAT_WRITE_ATOM: 3591 case NVME_FEAT_ASYNC_EVENT: 3592 case NVME_FEAT_PROGRESS: 3593 if (nsid != 0) 3594 return (EINVAL); 3595 break; 3596 3597 case NVME_FEAT_INTR_VECT: 3598 if (nsid != 0) 3599 return (EINVAL); 3600 3601 res = nioc->n_arg & 0xffffffffUL; 3602 if (res >= nvme->n_intr_cnt) 3603 return (EINVAL); 3604 break; 3605 3606 case NVME_FEAT_LBA_RANGE: 3607 if (nvme->n_lba_range_supported == B_FALSE) 3608 return (EINVAL); 3609 3610 if (nsid == 0 || 3611 nsid > nvme->n_namespace_count) 3612 return (EINVAL); 3613 3614 break; 3615 3616 case NVME_FEAT_WRITE_CACHE: 3617 if (nsid != 0) 3618 return (EINVAL); 3619 3620 if (!nvme->n_write_cache_present) 3621 return (EINVAL); 3622 3623 break; 3624 3625 case NVME_FEAT_AUTO_PST: 3626 if (nsid != 0) 3627 return (EINVAL); 3628 3629 if (!nvme->n_auto_pst_supported) 3630 return (EINVAL); 3631 3632 break; 3633 3634 default: 3635 return (EINVAL); 3636 } 3637 3638 rv = nvme_get_features(nvme, nsid, feature, &res, &buf, &bufsize); 3639 if (rv != 0) 3640 return (rv); 3641 3642 if (nioc->n_len < bufsize) { 3643 kmem_free(buf, bufsize); 3644 return (EINVAL); 3645 } 3646 3647 if (buf && ddi_copyout(buf, (void*)nioc->n_buf, bufsize, mode) != 0) 3648 rv = EFAULT; 3649 3650 kmem_free(buf, bufsize); 3651 nioc->n_arg = res; 3652 nioc->n_len = bufsize; 3653 3654 return (rv); 3655 } 3656 3657 static int 3658 nvme_ioctl_intr_cnt(nvme_t *nvme, int nsid, nvme_ioctl_t *nioc, int mode, 3659 cred_t *cred_p) 3660 { 3661 _NOTE(ARGUNUSED(nsid, mode, cred_p)); 3662 3663 if ((mode & FREAD) == 0) 3664 return (EPERM); 3665 3666 nioc->n_arg = nvme->n_intr_cnt; 3667 return (0); 3668 } 3669 3670 static int 3671 nvme_ioctl_version(nvme_t *nvme, int nsid, nvme_ioctl_t *nioc, int mode, 3672 cred_t *cred_p) 3673 { 3674 _NOTE(ARGUNUSED(nsid, cred_p)); 3675 int rv = 0; 3676 3677 if ((mode & FREAD) == 0) 3678 return (EPERM); 3679 3680 if (nioc->n_len < sizeof (nvme->n_version)) 3681 return (ENOMEM); 3682 3683 if (ddi_copyout(&nvme->n_version, (void *)nioc->n_buf, 3684 sizeof (nvme->n_version), mode) != 0) 3685 rv = EFAULT; 3686 3687 return (rv); 3688 } 3689 3690 static int 3691 nvme_ioctl_format(nvme_t *nvme, int nsid, nvme_ioctl_t *nioc, int mode, 3692 cred_t *cred_p) 3693 { 3694 _NOTE(ARGUNUSED(mode)); 3695 nvme_format_nvm_t frmt = { 0 }; 3696 int c_nsid = nsid != 0 ? nsid - 1 : 0; 3697 3698 if ((mode & FWRITE) == 0 || secpolicy_sys_config(cred_p, B_FALSE) != 0) 3699 return (EPERM); 3700 3701 frmt.r = nioc->n_arg & 0xffffffff; 3702 3703 /* 3704 * Check whether the FORMAT NVM command is supported. 3705 */ 3706 if (nvme->n_idctl->id_oacs.oa_format == 0) 3707 return (EINVAL); 3708 3709 /* 3710 * Don't allow format or secure erase of individual namespace if that 3711 * would cause a format or secure erase of all namespaces. 3712 */ 3713 if (nsid != 0 && nvme->n_idctl->id_fna.fn_format != 0) 3714 return (EINVAL); 3715 3716 if (nsid != 0 && frmt.b.fm_ses != NVME_FRMT_SES_NONE && 3717 nvme->n_idctl->id_fna.fn_sec_erase != 0) 3718 return (EINVAL); 3719 3720 /* 3721 * Don't allow formatting with Protection Information. 3722 */ 3723 if (frmt.b.fm_pi != 0 || frmt.b.fm_pil != 0 || frmt.b.fm_ms != 0) 3724 return (EINVAL); 3725 3726 /* 3727 * Don't allow formatting using an illegal LBA format, or any LBA format 3728 * that uses metadata. 3729 */ 3730 if (frmt.b.fm_lbaf > nvme->n_ns[c_nsid].ns_idns->id_nlbaf || 3731 nvme->n_ns[c_nsid].ns_idns->id_lbaf[frmt.b.fm_lbaf].lbaf_ms != 0) 3732 return (EINVAL); 3733 3734 /* 3735 * Don't allow formatting using an illegal Secure Erase setting. 3736 */ 3737 if (frmt.b.fm_ses > NVME_FRMT_MAX_SES || 3738 (frmt.b.fm_ses == NVME_FRMT_SES_CRYPTO && 3739 nvme->n_idctl->id_fna.fn_crypt_erase == 0)) 3740 return (EINVAL); 3741 3742 if (nsid == 0) 3743 nsid = (uint32_t)-1; 3744 3745 return (nvme_format_nvm(nvme, nsid, frmt.b.fm_lbaf, B_FALSE, 0, B_FALSE, 3746 frmt.b.fm_ses)); 3747 } 3748 3749 static int 3750 nvme_ioctl_detach(nvme_t *nvme, int nsid, nvme_ioctl_t *nioc, int mode, 3751 cred_t *cred_p) 3752 { 3753 _NOTE(ARGUNUSED(nioc, mode)); 3754 int rv = 0; 3755 3756 if ((mode & FWRITE) == 0 || secpolicy_sys_config(cred_p, B_FALSE) != 0) 3757 return (EPERM); 3758 3759 if (nsid == 0) 3760 return (EINVAL); 3761 3762 rv = bd_detach_handle(nvme->n_ns[nsid - 1].ns_bd_hdl); 3763 if (rv != DDI_SUCCESS) 3764 rv = EBUSY; 3765 3766 return (rv); 3767 } 3768 3769 static int 3770 nvme_ioctl_attach(nvme_t *nvme, int nsid, nvme_ioctl_t *nioc, int mode, 3771 cred_t *cred_p) 3772 { 3773 _NOTE(ARGUNUSED(nioc, mode)); 3774 nvme_identify_nsid_t *idns; 3775 int rv = 0; 3776 3777 if ((mode & FWRITE) == 0 || secpolicy_sys_config(cred_p, B_FALSE) != 0) 3778 return (EPERM); 3779 3780 if (nsid == 0) 3781 return (EINVAL); 3782 3783 /* 3784 * Identify namespace again, free old identify data. 3785 */ 3786 idns = nvme->n_ns[nsid - 1].ns_idns; 3787 if (nvme_init_ns(nvme, nsid) != DDI_SUCCESS) 3788 return (EIO); 3789 3790 kmem_free(idns, sizeof (nvme_identify_nsid_t)); 3791 3792 rv = bd_attach_handle(nvme->n_dip, nvme->n_ns[nsid - 1].ns_bd_hdl); 3793 if (rv != DDI_SUCCESS) 3794 rv = EBUSY; 3795 3796 return (rv); 3797 } 3798 3799 static int 3800 nvme_ioctl(dev_t dev, int cmd, intptr_t arg, int mode, cred_t *cred_p, 3801 int *rval_p) 3802 { 3803 #ifndef __lock_lint 3804 _NOTE(ARGUNUSED(rval_p)); 3805 #endif 3806 minor_t minor = getminor(dev); 3807 nvme_t *nvme = ddi_get_soft_state(nvme_state, NVME_MINOR_INST(minor)); 3808 int nsid = NVME_MINOR_NSID(minor); 3809 int rv = 0; 3810 nvme_ioctl_t nioc; 3811 3812 int (*nvme_ioctl[])(nvme_t *, int, nvme_ioctl_t *, int, cred_t *) = { 3813 NULL, 3814 nvme_ioctl_identify, 3815 nvme_ioctl_identify, 3816 nvme_ioctl_capabilities, 3817 nvme_ioctl_get_logpage, 3818 nvme_ioctl_get_features, 3819 nvme_ioctl_intr_cnt, 3820 nvme_ioctl_version, 3821 nvme_ioctl_format, 3822 nvme_ioctl_detach, 3823 nvme_ioctl_attach 3824 }; 3825 3826 if (nvme == NULL) 3827 return (ENXIO); 3828 3829 if (nsid > nvme->n_namespace_count) 3830 return (ENXIO); 3831 3832 if (IS_DEVCTL(cmd)) 3833 return (ndi_devctl_ioctl(nvme->n_dip, cmd, arg, mode, 0)); 3834 3835 #ifdef _MULTI_DATAMODEL 3836 switch (ddi_model_convert_from(mode & FMODELS)) { 3837 case DDI_MODEL_ILP32: { 3838 nvme_ioctl32_t nioc32; 3839 if (ddi_copyin((void*)arg, &nioc32, sizeof (nvme_ioctl32_t), 3840 mode) != 0) 3841 return (EFAULT); 3842 nioc.n_len = nioc32.n_len; 3843 nioc.n_buf = nioc32.n_buf; 3844 nioc.n_arg = nioc32.n_arg; 3845 break; 3846 } 3847 case DDI_MODEL_NONE: 3848 #endif 3849 if (ddi_copyin((void*)arg, &nioc, sizeof (nvme_ioctl_t), mode) 3850 != 0) 3851 return (EFAULT); 3852 #ifdef _MULTI_DATAMODEL 3853 break; 3854 } 3855 #endif 3856 3857 if (nvme->n_dead && cmd != NVME_IOC_DETACH) 3858 return (EIO); 3859 3860 3861 if (cmd == NVME_IOC_IDENTIFY_CTRL) { 3862 /* 3863 * This makes NVME_IOC_IDENTIFY_CTRL work the same on devctl and 3864 * attachment point nodes. 3865 */ 3866 nsid = 0; 3867 } else if (cmd == NVME_IOC_IDENTIFY_NSID && nsid == 0) { 3868 /* 3869 * This makes NVME_IOC_IDENTIFY_NSID work on a devctl node, it 3870 * will always return identify data for namespace 1. 3871 */ 3872 nsid = 1; 3873 } 3874 3875 if (IS_NVME_IOC(cmd) && nvme_ioctl[NVME_IOC_CMD(cmd)] != NULL) 3876 rv = nvme_ioctl[NVME_IOC_CMD(cmd)](nvme, nsid, &nioc, mode, 3877 cred_p); 3878 else 3879 rv = EINVAL; 3880 3881 #ifdef _MULTI_DATAMODEL 3882 switch (ddi_model_convert_from(mode & FMODELS)) { 3883 case DDI_MODEL_ILP32: { 3884 nvme_ioctl32_t nioc32; 3885 3886 nioc32.n_len = (size32_t)nioc.n_len; 3887 nioc32.n_buf = (uintptr32_t)nioc.n_buf; 3888 nioc32.n_arg = nioc.n_arg; 3889 3890 if (ddi_copyout(&nioc32, (void *)arg, sizeof (nvme_ioctl32_t), 3891 mode) != 0) 3892 return (EFAULT); 3893 break; 3894 } 3895 case DDI_MODEL_NONE: 3896 #endif 3897 if (ddi_copyout(&nioc, (void *)arg, sizeof (nvme_ioctl_t), mode) 3898 != 0) 3899 return (EFAULT); 3900 #ifdef _MULTI_DATAMODEL 3901 break; 3902 } 3903 #endif 3904 3905 return (rv); 3906 } 3907