1 /* 2 * This file and its contents are supplied under the terms of the 3 * Common Development and Distribution License ("CDDL"), version 1.0. 4 * You may only use this file in accordance with the terms of version 5 * 1.0 of the CDDL. 6 * 7 * A full copy of the text of the CDDL should have accompanied this 8 * source. A copy of the CDDL is also available via the Internet at 9 * http://www.illumos.org/license/CDDL. 10 */ 11 12 /* 13 * Copyright 2018 Nexenta Systems, Inc. 14 * Copyright 2016 The MathWorks, Inc. All rights reserved. 15 * Copyright 2019 Joyent, Inc. 16 * Copyright 2019 Western Digital Corporation. 17 * Copyright 2021 Oxide Computer Company. 18 */ 19 20 #ifndef _NVME_VAR_H 21 #define _NVME_VAR_H 22 23 #include <sys/ddi.h> 24 #include <sys/sunddi.h> 25 #include <sys/blkdev.h> 26 #include <sys/taskq_impl.h> 27 #include <sys/list.h> 28 29 /* 30 * NVMe driver state 31 */ 32 33 #ifdef __cplusplus 34 extern "C" { 35 #endif 36 37 #define NVME_FMA_INIT 0x1 38 #define NVME_REGS_MAPPED 0x2 39 #define NVME_ADMIN_QUEUE 0x4 40 #define NVME_CTRL_LIMITS 0x8 41 #define NVME_INTERRUPTS 0x10 42 #define NVME_UFM_INIT 0x20 43 44 #define NVME_MIN_ADMIN_QUEUE_LEN 16 45 #define NVME_MIN_IO_QUEUE_LEN 16 46 #define NVME_DEFAULT_ADMIN_QUEUE_LEN 256 47 #define NVME_DEFAULT_IO_QUEUE_LEN 1024 48 #define NVME_DEFAULT_ASYNC_EVENT_LIMIT 10 49 #define NVME_MIN_ASYNC_EVENT_LIMIT 1 50 #define NVME_DEFAULT_MIN_BLOCK_SIZE 512 51 52 53 typedef struct nvme nvme_t; 54 typedef struct nvme_namespace nvme_namespace_t; 55 typedef struct nvme_minor_state nvme_minor_state_t; 56 typedef struct nvme_dma nvme_dma_t; 57 typedef struct nvme_cmd nvme_cmd_t; 58 typedef struct nvme_cq nvme_cq_t; 59 typedef struct nvme_qpair nvme_qpair_t; 60 typedef struct nvme_task_arg nvme_task_arg_t; 61 62 struct nvme_minor_state { 63 kmutex_t nm_mutex; 64 boolean_t nm_oexcl; 65 uint_t nm_ocnt; 66 }; 67 68 struct nvme_dma { 69 ddi_dma_handle_t nd_dmah; 70 ddi_acc_handle_t nd_acch; 71 ddi_dma_cookie_t nd_cookie; 72 uint_t nd_ncookie; 73 caddr_t nd_memp; 74 size_t nd_len; 75 boolean_t nd_cached; 76 }; 77 78 struct nvme_cmd { 79 struct list_node nc_list; 80 81 nvme_sqe_t nc_sqe; 82 nvme_cqe_t nc_cqe; 83 84 void (*nc_callback)(void *); 85 bd_xfer_t *nc_xfer; 86 boolean_t nc_completed; 87 boolean_t nc_dontpanic; 88 uint16_t nc_sqid; 89 90 nvme_dma_t *nc_dma; 91 nvme_dma_t *nc_prp; /* DMA for PRP lists */ 92 93 kmutex_t nc_mutex; 94 kcondvar_t nc_cv; 95 96 taskq_ent_t nc_tqent; 97 nvme_t *nc_nvme; 98 }; 99 100 struct nvme_cq { 101 size_t ncq_nentry; 102 uint16_t ncq_id; 103 104 nvme_dma_t *ncq_dma; 105 nvme_cqe_t *ncq_cq; 106 uint_t ncq_head; 107 uint_t ncq_tail; 108 uintptr_t ncq_hdbl; 109 int ncq_phase; 110 111 taskq_t *ncq_cmd_taskq; 112 113 kmutex_t ncq_mutex; 114 }; 115 116 struct nvme_qpair { 117 size_t nq_nentry; 118 119 /* submission fields */ 120 nvme_dma_t *nq_sqdma; 121 nvme_sqe_t *nq_sq; 122 uint_t nq_sqhead; 123 uint_t nq_sqtail; 124 uintptr_t nq_sqtdbl; 125 126 /* completion */ 127 nvme_cq_t *nq_cq; 128 129 /* shared structures for completion and submission */ 130 nvme_cmd_t **nq_cmd; /* active command array */ 131 uint16_t nq_next_cmd; /* next potential empty queue slot */ 132 uint_t nq_active_cmds; /* number of active cmds */ 133 134 kmutex_t nq_mutex; /* protects shared state */ 135 ksema_t nq_sema; /* semaphore to ensure q always has >= 1 empty slot */ 136 }; 137 138 struct nvme { 139 dev_info_t *n_dip; 140 int n_progress; 141 142 caddr_t n_regs; 143 ddi_acc_handle_t n_regh; 144 145 kmem_cache_t *n_cmd_cache; 146 kmem_cache_t *n_prp_cache; 147 148 size_t n_inth_sz; 149 ddi_intr_handle_t *n_inth; 150 int n_intr_cnt; 151 uint_t n_intr_pri; 152 int n_intr_cap; 153 int n_intr_type; 154 int n_intr_types; 155 156 char *n_product; 157 char *n_vendor; 158 159 nvme_version_t n_version; 160 boolean_t n_dead; 161 boolean_t n_strict_version; 162 boolean_t n_ignore_unknown_vendor_status; 163 uint32_t n_admin_queue_len; 164 uint32_t n_io_squeue_len; 165 uint32_t n_io_cqueue_len; 166 uint16_t n_async_event_limit; 167 uint_t n_min_block_size; 168 uint16_t n_abort_command_limit; 169 uint64_t n_max_data_transfer_size; 170 boolean_t n_write_cache_present; 171 boolean_t n_write_cache_enabled; 172 int n_error_log_len; 173 boolean_t n_lba_range_supported; 174 boolean_t n_auto_pst_supported; 175 boolean_t n_async_event_supported; 176 boolean_t n_progress_supported; 177 int n_submission_queues; 178 int n_completion_queues; 179 180 int n_nssr_supported; 181 int n_doorbell_stride; 182 int n_timeout; 183 int n_arbitration_mechanisms; 184 int n_cont_queues_reqd; 185 int n_max_queue_entries; 186 int n_pageshift; 187 int n_pagesize; 188 189 int n_namespace_count; 190 uint_t n_namespaces_attachable; 191 uint_t n_ioq_count; 192 uint_t n_cq_count; 193 194 nvme_identify_ctrl_t *n_idctl; 195 196 /* Pointer to the admin queue, which is always queue 0 in n_ioq. */ 197 nvme_qpair_t *n_adminq; 198 /* 199 * All command queues, including the admin queue. 200 * Its length is: n_ioq_count + 1. 201 */ 202 nvme_qpair_t **n_ioq; 203 nvme_cq_t **n_cq; 204 205 nvme_namespace_t *n_ns; 206 207 ddi_dma_attr_t n_queue_dma_attr; 208 ddi_dma_attr_t n_prp_dma_attr; 209 ddi_dma_attr_t n_sgl_dma_attr; 210 ddi_device_acc_attr_t n_reg_acc_attr; 211 ddi_iblock_cookie_t n_fm_ibc; 212 int n_fm_cap; 213 214 ksema_t n_abort_sema; 215 216 /* state for devctl minor node */ 217 nvme_minor_state_t n_minor; 218 219 /* errors detected by driver */ 220 uint32_t n_dma_bind_err; 221 uint32_t n_abort_failed; 222 uint32_t n_cmd_timeout; 223 uint32_t n_cmd_aborted; 224 uint32_t n_wrong_logpage; 225 uint32_t n_unknown_logpage; 226 uint32_t n_too_many_cookies; 227 228 /* errors detected by hardware */ 229 uint32_t n_data_xfr_err; 230 uint32_t n_internal_err; 231 uint32_t n_abort_rq_err; 232 uint32_t n_abort_sq_del; 233 uint32_t n_nvm_cap_exc; 234 uint32_t n_nvm_ns_notrdy; 235 uint32_t n_inv_cq_err; 236 uint32_t n_inv_qid_err; 237 uint32_t n_max_qsz_exc; 238 uint32_t n_inv_int_vect; 239 uint32_t n_inv_log_page; 240 uint32_t n_inv_format; 241 uint32_t n_inv_q_del; 242 uint32_t n_cnfl_attr; 243 uint32_t n_inv_prot; 244 uint32_t n_readonly; 245 246 /* errors reported by asynchronous events */ 247 uint32_t n_diagfail_event; 248 uint32_t n_persistent_event; 249 uint32_t n_transient_event; 250 uint32_t n_fw_load_event; 251 uint32_t n_reliability_event; 252 uint32_t n_temperature_event; 253 uint32_t n_spare_event; 254 uint32_t n_vendor_event; 255 uint32_t n_unknown_event; 256 257 /* hot removal NDI event handling */ 258 ddi_eventcookie_t n_rm_cookie; 259 ddi_callback_id_t n_ev_rm_cb_id; 260 261 /* DDI UFM handle */ 262 ddi_ufm_handle_t *n_ufmh; 263 /* Cached Firmware Slot Information log page */ 264 nvme_fwslot_log_t *n_fwslot; 265 /* Lock protecting the cached firmware slot info */ 266 kmutex_t n_fwslot_mutex; 267 }; 268 269 struct nvme_namespace { 270 nvme_t *ns_nvme; 271 uint8_t ns_eui64[8]; 272 char ns_name[17]; 273 274 bd_handle_t ns_bd_hdl; 275 276 uint32_t ns_id; 277 size_t ns_block_count; 278 size_t ns_block_size; 279 size_t ns_best_block_size; 280 281 boolean_t ns_ignore; 282 283 nvme_identify_nsid_t *ns_idns; 284 285 /* state for attachment point minor node */ 286 nvme_minor_state_t ns_minor; 287 288 /* 289 * If a namespace has no EUI64, we create a devid in 290 * nvme_prepare_devid(). 291 */ 292 char *ns_devid; 293 }; 294 295 struct nvme_task_arg { 296 nvme_t *nt_nvme; 297 nvme_cmd_t *nt_cmd; 298 }; 299 300 #ifdef __cplusplus 301 } 302 #endif 303 304 #endif /* _NVME_VAR_H */ 305