16f45ec7bSml29623 /* 26f45ec7bSml29623 * CDDL HEADER START 36f45ec7bSml29623 * 46f45ec7bSml29623 * The contents of this file are subject to the terms of the 56f45ec7bSml29623 * Common Development and Distribution License (the "License"). 66f45ec7bSml29623 * You may not use this file except in compliance with the License. 76f45ec7bSml29623 * 86f45ec7bSml29623 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 96f45ec7bSml29623 * or http://www.opensolaris.org/os/licensing. 106f45ec7bSml29623 * See the License for the specific language governing permissions 116f45ec7bSml29623 * and limitations under the License. 126f45ec7bSml29623 * 136f45ec7bSml29623 * When distributing Covered Code, include this CDDL HEADER in each 146f45ec7bSml29623 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 156f45ec7bSml29623 * If applicable, add the following below this CDDL HEADER, with the 166f45ec7bSml29623 * fields enclosed by brackets "[]" replaced with your own identifying 176f45ec7bSml29623 * information: Portions Copyright [yyyy] [name of copyright owner] 186f45ec7bSml29623 * 196f45ec7bSml29623 * CDDL HEADER END 206f45ec7bSml29623 */ 216f45ec7bSml29623 /* 22*678453a8Sspeer * Copyright 2008 Sun Microsystems, Inc. All rights reserved. 236f45ec7bSml29623 * Use is subject to license terms. 246f45ec7bSml29623 */ 256f45ec7bSml29623 266f45ec7bSml29623 #ifndef _NPI_TXDMA_H 276f45ec7bSml29623 #define _NPI_TXDMA_H 286f45ec7bSml29623 296f45ec7bSml29623 #ifdef __cplusplus 306f45ec7bSml29623 extern "C" { 316f45ec7bSml29623 #endif 326f45ec7bSml29623 336f45ec7bSml29623 #include <npi.h> 346f45ec7bSml29623 #include <nxge_txdma_hw.h> 356f45ec7bSml29623 366f45ec7bSml29623 #define DMA_LOG_PAGE_FN_VALIDATE(cn, pn, fn, status) \ 376f45ec7bSml29623 { \ 386f45ec7bSml29623 status = NPI_SUCCESS; \ 396f45ec7bSml29623 if (!TXDMA_CHANNEL_VALID(channel)) { \ 406f45ec7bSml29623 status = (NPI_FAILURE | NPI_TXDMA_CHANNEL_INVALID(cn)); \ 416f45ec7bSml29623 } else if (!TXDMA_PAGE_VALID(pn)) { \ 426f45ec7bSml29623 status = (NPI_FAILURE | NPI_TXDMA_PAGE_INVALID(pn)); \ 436f45ec7bSml29623 } else if (!TXDMA_FUNC_VALID(fn)) { \ 446f45ec7bSml29623 status = (NPI_FAILURE | NPI_TXDMA_FUNC_INVALID(fn)); \ 456f45ec7bSml29623 } \ 466f45ec7bSml29623 } 476f45ec7bSml29623 486f45ec7bSml29623 #define DMA_LOG_PAGE_VALIDATE(cn, pn, status) \ 496f45ec7bSml29623 { \ 506f45ec7bSml29623 status = NPI_SUCCESS; \ 516f45ec7bSml29623 if (!TXDMA_CHANNEL_VALID(channel)) { \ 526f45ec7bSml29623 status = (NPI_FAILURE | NPI_TXDMA_CHANNEL_INVALID(cn)); \ 536f45ec7bSml29623 } else if (!TXDMA_PAGE_VALID(pn)) { \ 546f45ec7bSml29623 status = (NPI_FAILURE | NPI_TXDMA_PAGE_INVALID(pn)); \ 556f45ec7bSml29623 } \ 566f45ec7bSml29623 } 576f45ec7bSml29623 586f45ec7bSml29623 typedef enum _txdma_cs_cntl_e { 596f45ec7bSml29623 TXDMA_INIT_RESET = 0x1, 606f45ec7bSml29623 TXDMA_INIT_START = 0x2, 616f45ec7bSml29623 TXDMA_START = 0x3, 626f45ec7bSml29623 TXDMA_RESET = 0x4, 636f45ec7bSml29623 TXDMA_STOP = 0x5, 646f45ec7bSml29623 TXDMA_RESUME = 0x6, 656f45ec7bSml29623 TXDMA_CLEAR_MMK = 0x7, 666f45ec7bSml29623 TXDMA_MBOX_ENABLE = 0x8 676f45ec7bSml29623 } txdma_cs_cntl_t; 686f45ec7bSml29623 696f45ec7bSml29623 typedef enum _txdma_log_cfg_e { 706f45ec7bSml29623 TXDMA_LOG_PAGE_MASK = 0x01, 716f45ec7bSml29623 TXDMA_LOG_PAGE_VALUE = 0x02, 726f45ec7bSml29623 TXDMA_LOG_PAGE_RELOC = 0x04, 736f45ec7bSml29623 TXDMA_LOG_PAGE_VALID = 0x08, 746f45ec7bSml29623 TXDMA_LOG_PAGE_ALL = (TXDMA_LOG_PAGE_MASK | TXDMA_LOG_PAGE_VALUE | 756f45ec7bSml29623 TXDMA_LOG_PAGE_RELOC | TXDMA_LOG_PAGE_VALID) 766f45ec7bSml29623 } txdma_log_cfg_t; 776f45ec7bSml29623 786f45ec7bSml29623 typedef enum _txdma_ent_msk_cfg_e { 796f45ec7bSml29623 CFG_TXDMA_PKT_PRT_MASK = TX_ENT_MSK_PKT_PRT_ERR_MASK, 806f45ec7bSml29623 CFG_TXDMA_CONF_PART_MASK = TX_ENT_MSK_CONF_PART_ERR_MASK, 816f45ec7bSml29623 CFG_TXDMA_NACK_PKT_RD_MASK = TX_ENT_MSK_NACK_PKT_RD_MASK, 826f45ec7bSml29623 CFG_TXDMA_NACK_PREF_MASK = TX_ENT_MSK_NACK_PREF_MASK, 836f45ec7bSml29623 CFG_TXDMA_PREF_BUF_ECC_ERR_MASK = TX_ENT_MSK_PREF_BUF_ECC_ERR_MASK, 846f45ec7bSml29623 CFG_TXDMA_TX_RING_OFLOW_MASK = TX_ENT_MSK_TX_RING_OFLOW_MASK, 856f45ec7bSml29623 CFG_TXDMA_PKT_SIZE_ERR_MASK = TX_ENT_MSK_PKT_SIZE_ERR_MASK, 866f45ec7bSml29623 CFG_TXDMA_MBOX_ERR_MASK = TX_ENT_MSK_MBOX_ERR_MASK, 876f45ec7bSml29623 CFG_TXDMA_MK_MASK = TX_ENT_MSK_MK_MASK, 886f45ec7bSml29623 CFG_TXDMA_MASK_ALL = (TX_ENT_MSK_PKT_PRT_ERR_MASK | 896f45ec7bSml29623 TX_ENT_MSK_CONF_PART_ERR_MASK | 906f45ec7bSml29623 TX_ENT_MSK_NACK_PKT_RD_MASK | 916f45ec7bSml29623 TX_ENT_MSK_NACK_PREF_MASK | 926f45ec7bSml29623 TX_ENT_MSK_PREF_BUF_ECC_ERR_MASK | 936f45ec7bSml29623 TX_ENT_MSK_TX_RING_OFLOW_MASK | 946f45ec7bSml29623 TX_ENT_MSK_PKT_SIZE_ERR_MASK | 956f45ec7bSml29623 TX_ENT_MSK_MBOX_ERR_MASK | 966f45ec7bSml29623 TX_ENT_MSK_MK_MASK) 976f45ec7bSml29623 } txdma_ent_msk_cfg_t; 986f45ec7bSml29623 996f45ec7bSml29623 1006f45ec7bSml29623 typedef struct _txdma_ring_errlog { 1016f45ec7bSml29623 tx_rng_err_logl_t logl; 1026f45ec7bSml29623 tx_rng_err_logh_t logh; 1036f45ec7bSml29623 } txdma_ring_errlog_t, *p_txdma_ring_errlog_t; 1046f45ec7bSml29623 1056f45ec7bSml29623 /* 1066f45ec7bSml29623 * Register offset (0x200 bytes for each channel) for logical pages registers. 1076f45ec7bSml29623 */ 1086f45ec7bSml29623 #define NXGE_TXLOG_OFFSET(x, channel) (x + TX_LOG_DMA_OFFSET(channel)) 1096f45ec7bSml29623 1106f45ec7bSml29623 /* 1116f45ec7bSml29623 * Register offset (0x200 bytes for each channel) for transmit ring registers. 1126f45ec7bSml29623 * (Ring configuration, kick register, event mask, control and status, 1136f45ec7bSml29623 * mailbox, prefetch, ring errors). 1146f45ec7bSml29623 */ 1156f45ec7bSml29623 #define NXGE_TXDMA_OFFSET(x, v, channel) (x + \ 1166f45ec7bSml29623 (!v ? DMC_OFFSET(channel) : TDMC_PIOVADDR_OFFSET(channel))) 1176f45ec7bSml29623 /* 1186f45ec7bSml29623 * Register offset (0x8 bytes for each port) for transmit mapping registers. 1196f45ec7bSml29623 */ 1206f45ec7bSml29623 #define NXGE_TXDMA_MAP_OFFSET(x, port) (x + TX_DMA_MAP_PORT_OFFSET(port)) 1216f45ec7bSml29623 1226f45ec7bSml29623 /* 1236f45ec7bSml29623 * Register offset (0x10 bytes for each channel) for transmit DRR and ring 1246f45ec7bSml29623 * usage registers. 1256f45ec7bSml29623 */ 1266f45ec7bSml29623 #define NXGE_TXDMA_DRR_OFFSET(x, channel) (x + \ 1276f45ec7bSml29623 TXDMA_DRR_RNG_USE_OFFSET(channel)) 1286f45ec7bSml29623 1296f45ec7bSml29623 /* 1306f45ec7bSml29623 * PIO macros to read and write the transmit registers. 1316f45ec7bSml29623 */ 1326f45ec7bSml29623 #define TX_LOG_REG_READ64(handle, reg, channel, val_p) \ 1336f45ec7bSml29623 NXGE_REG_RD64(handle, NXGE_TXLOG_OFFSET(reg, channel), val_p) 1346f45ec7bSml29623 1356f45ec7bSml29623 #define TX_LOG_REG_WRITE64(handle, reg, channel, data) \ 1366f45ec7bSml29623 NXGE_REG_WR64(handle, NXGE_TXLOG_OFFSET(reg, channel), data) 1376f45ec7bSml29623 1386f45ec7bSml29623 /* 1396f45ec7bSml29623 * Transmit Descriptor Definitions. 1406f45ec7bSml29623 */ 1416f45ec7bSml29623 #define TXDMA_DESC_SIZE (sizeof (tx_desc_t)) 1426f45ec7bSml29623 1436f45ec7bSml29623 #define NPI_TXDMA_GATHER_INDEX(index) \ 1446f45ec7bSml29623 ((index <= TX_MAX_GATHER_POINTERS)) ? NPI_SUCCESS : \ 1456f45ec7bSml29623 (NPI_TXDMA_GATHER_INVALID) 1466f45ec7bSml29623 1476f45ec7bSml29623 /* 1486f45ec7bSml29623 * Transmit NPI error codes 1496f45ec7bSml29623 */ 1506f45ec7bSml29623 #define TXDMA_ER_ST (TXDMA_BLK_ID << NPI_BLOCK_ID_SHIFT) 1516f45ec7bSml29623 #define TXDMA_ID_SHIFT(n) (n << NPI_PORT_CHAN_SHIFT) 1526f45ec7bSml29623 1536f45ec7bSml29623 #define TXDMA_HW_STOP_FAILED (NPI_BK_HW_ER_START | 0x1) 1546f45ec7bSml29623 #define TXDMA_HW_RESUME_FAILED (NPI_BK_HW_ER_START | 0x2) 1556f45ec7bSml29623 1566f45ec7bSml29623 #define TXDMA_GATHER_INVALID (NPI_BK_ERROR_START | 0x1) 1576f45ec7bSml29623 #define TXDMA_XFER_LEN_INVALID (NPI_BK_ERROR_START | 0x2) 1586f45ec7bSml29623 1596f45ec7bSml29623 #define NPI_TXDMA_OPCODE_INVALID(n) (TXDMA_ID_SHIFT(n) | \ 1606f45ec7bSml29623 TXDMA_ER_ST | OPCODE_INVALID) 1616f45ec7bSml29623 1626f45ec7bSml29623 #define NPI_TXDMA_FUNC_INVALID(n) (TXDMA_ID_SHIFT(n) | \ 1636f45ec7bSml29623 TXDMA_ER_ST | PORT_INVALID) 1646f45ec7bSml29623 #define NPI_TXDMA_CHANNEL_INVALID(n) (TXDMA_ID_SHIFT(n) | \ 1656f45ec7bSml29623 TXDMA_ER_ST | CHANNEL_INVALID) 1666f45ec7bSml29623 1676f45ec7bSml29623 #define NPI_TXDMA_PAGE_INVALID(n) (TXDMA_ID_SHIFT(n) | \ 1686f45ec7bSml29623 TXDMA_ER_ST | LOGICAL_PAGE_INVALID) 1696f45ec7bSml29623 1706f45ec7bSml29623 #define NPI_TXDMA_REGISTER_INVALID (TXDMA_ER_ST | REGISTER_INVALID) 1716f45ec7bSml29623 #define NPI_TXDMA_COUNTER_INVALID (TXDMA_ER_ST | COUNTER_INVALID) 1726f45ec7bSml29623 #define NPI_TXDMA_CONFIG_INVALID (TXDMA_ER_ST | CONFIG_INVALID) 1736f45ec7bSml29623 1746f45ec7bSml29623 1756f45ec7bSml29623 #define NPI_TXDMA_GATHER_INVALID (TXDMA_ER_ST | TXDMA_GATHER_INVALID) 1766f45ec7bSml29623 #define NPI_TXDMA_XFER_LEN_INVALID (TXDMA_ER_ST | TXDMA_XFER_LEN_INVALID) 1776f45ec7bSml29623 1786f45ec7bSml29623 #define NPI_TXDMA_RESET_FAILED (TXDMA_ER_ST | RESET_FAILED) 1796f45ec7bSml29623 #define NPI_TXDMA_STOP_FAILED (TXDMA_ER_ST | TXDMA_HW_STOP_FAILED) 1806f45ec7bSml29623 #define NPI_TXDMA_RESUME_FAILED (TXDMA_ER_ST | TXDMA_HW_RESUME_FAILED) 1816f45ec7bSml29623 1826f45ec7bSml29623 /* 1836f45ec7bSml29623 * Transmit DMA Channel NPI Prototypes. 1846f45ec7bSml29623 */ 1856f45ec7bSml29623 npi_status_t npi_txdma_mode32_set(npi_handle_t, boolean_t); 1866f45ec7bSml29623 npi_status_t npi_txdma_log_page_set(npi_handle_t, uint8_t, 1876f45ec7bSml29623 p_dma_log_page_t); 1886f45ec7bSml29623 npi_status_t npi_txdma_log_page_get(npi_handle_t, uint8_t, 1896f45ec7bSml29623 p_dma_log_page_t); 1906f45ec7bSml29623 npi_status_t npi_txdma_log_page_handle_set(npi_handle_t, uint8_t, 1916f45ec7bSml29623 p_log_page_hdl_t); 1926f45ec7bSml29623 npi_status_t npi_txdma_log_page_config(npi_handle_t, io_op_t, 1936f45ec7bSml29623 txdma_log_cfg_t, uint8_t, p_dma_log_page_t); 1946f45ec7bSml29623 npi_status_t npi_txdma_log_page_vld_config(npi_handle_t, io_op_t, 1956f45ec7bSml29623 uint8_t, p_log_page_vld_t); 1966f45ec7bSml29623 npi_status_t npi_txdma_drr_weight_set(npi_handle_t, uint8_t, 1976f45ec7bSml29623 uint32_t); 1986f45ec7bSml29623 npi_status_t npi_txdma_channel_reset(npi_handle_t, uint8_t); 1996f45ec7bSml29623 npi_status_t npi_txdma_channel_init_enable(npi_handle_t, 2006f45ec7bSml29623 uint8_t); 2016f45ec7bSml29623 npi_status_t npi_txdma_channel_enable(npi_handle_t, uint8_t); 2026f45ec7bSml29623 npi_status_t npi_txdma_channel_disable(npi_handle_t, uint8_t); 2036f45ec7bSml29623 npi_status_t npi_txdma_channel_resume(npi_handle_t, uint8_t); 2046f45ec7bSml29623 npi_status_t npi_txdma_channel_mmk_clear(npi_handle_t, uint8_t); 2056f45ec7bSml29623 npi_status_t npi_txdma_channel_mbox_enable(npi_handle_t, uint8_t); 2066f45ec7bSml29623 npi_status_t npi_txdma_channel_control(npi_handle_t, 2076f45ec7bSml29623 txdma_cs_cntl_t, uint8_t); 2086f45ec7bSml29623 npi_status_t npi_txdma_control_status(npi_handle_t, io_op_t, 2096f45ec7bSml29623 uint8_t, p_tx_cs_t); 2106f45ec7bSml29623 2116f45ec7bSml29623 npi_status_t npi_txdma_event_mask(npi_handle_t, io_op_t, 2126f45ec7bSml29623 uint8_t, p_tx_dma_ent_msk_t); 2136f45ec7bSml29623 npi_status_t npi_txdma_event_mask_config(npi_handle_t, io_op_t, 2146f45ec7bSml29623 uint8_t, txdma_ent_msk_cfg_t *); 2156f45ec7bSml29623 npi_status_t npi_txdma_event_mask_mk_out(npi_handle_t, uint8_t); 2166f45ec7bSml29623 npi_status_t npi_txdma_event_mask_mk_in(npi_handle_t, uint8_t); 2176f45ec7bSml29623 2186f45ec7bSml29623 npi_status_t npi_txdma_ring_addr_set(npi_handle_t, uint8_t, 2196f45ec7bSml29623 uint64_t, uint32_t); 2206f45ec7bSml29623 npi_status_t npi_txdma_ring_config(npi_handle_t, io_op_t, 2216f45ec7bSml29623 uint8_t, uint64_t *); 2226f45ec7bSml29623 npi_status_t npi_txdma_mbox_config(npi_handle_t, io_op_t, 2236f45ec7bSml29623 uint8_t, uint64_t *); 2246f45ec7bSml29623 npi_status_t npi_txdma_desc_gather_set(npi_handle_t, 2256f45ec7bSml29623 p_tx_desc_t, uint8_t, 2266f45ec7bSml29623 boolean_t, uint8_t, 2276f45ec7bSml29623 uint64_t, uint32_t); 2286f45ec7bSml29623 2296f45ec7bSml29623 npi_status_t npi_txdma_desc_gather_sop_set(npi_handle_t, 2306f45ec7bSml29623 p_tx_desc_t, boolean_t, uint8_t); 2316f45ec7bSml29623 2326f45ec7bSml29623 npi_status_t npi_txdma_desc_gather_sop_set_1(npi_handle_t, 2336f45ec7bSml29623 p_tx_desc_t, boolean_t, uint8_t, 2346f45ec7bSml29623 uint32_t); 2356f45ec7bSml29623 2366f45ec7bSml29623 npi_status_t npi_txdma_desc_set_xfer_len(npi_handle_t, 2376f45ec7bSml29623 p_tx_desc_t, uint32_t); 2386f45ec7bSml29623 2396f45ec7bSml29623 npi_status_t npi_txdma_desc_set_zero(npi_handle_t, uint16_t); 2406f45ec7bSml29623 npi_status_t npi_txdma_desc_mem_get(npi_handle_t, uint16_t, 2416f45ec7bSml29623 p_tx_desc_t); 2426f45ec7bSml29623 npi_status_t npi_txdma_desc_kick_reg_set(npi_handle_t, uint8_t, 2436f45ec7bSml29623 uint16_t, boolean_t); 2446f45ec7bSml29623 npi_status_t npi_txdma_desc_kick_reg_get(npi_handle_t, uint8_t, 2456f45ec7bSml29623 p_tx_ring_kick_t); 2466f45ec7bSml29623 npi_status_t npi_txdma_ring_head_get(npi_handle_t, uint8_t, 2476f45ec7bSml29623 p_tx_ring_hdl_t); 2486f45ec7bSml29623 npi_status_t npi_txdma_channel_mbox_get(npi_handle_t, uint8_t, 2496f45ec7bSml29623 p_txdma_mailbox_t); 2506f45ec7bSml29623 npi_status_t npi_txdma_channel_pre_state_get(npi_handle_t, 2516f45ec7bSml29623 uint8_t, p_tx_dma_pre_st_t); 2526f45ec7bSml29623 npi_status_t npi_txdma_ring_error_get(npi_handle_t, 2536f45ec7bSml29623 uint8_t, p_txdma_ring_errlog_t); 2546f45ec7bSml29623 npi_status_t npi_txdma_inj_par_error_clear(npi_handle_t); 2556f45ec7bSml29623 npi_status_t npi_txdma_inj_par_error_set(npi_handle_t, 2566f45ec7bSml29623 uint32_t); 2576f45ec7bSml29623 npi_status_t npi_txdma_inj_par_error_update(npi_handle_t, 2586f45ec7bSml29623 uint32_t); 2596f45ec7bSml29623 npi_status_t npi_txdma_inj_par_error_get(npi_handle_t, 2606f45ec7bSml29623 uint32_t *); 2616f45ec7bSml29623 npi_status_t npi_txdma_dbg_sel_set(npi_handle_t, uint8_t); 2626f45ec7bSml29623 npi_status_t npi_txdma_training_vector_set(npi_handle_t, 2636f45ec7bSml29623 uint32_t); 2646f45ec7bSml29623 void npi_txdma_dump_desc_one(npi_handle_t, p_tx_desc_t, 2656f45ec7bSml29623 int); 2666f45ec7bSml29623 npi_status_t npi_txdma_dump_tdc_regs(npi_handle_t, uint8_t); 2676f45ec7bSml29623 npi_status_t npi_txdma_dump_fzc_regs(npi_handle_t); 2686f45ec7bSml29623 npi_status_t npi_txdma_inj_int_error_set(npi_handle_t, uint8_t, 2696f45ec7bSml29623 p_tdmc_intr_dbg_t); 2706f45ec7bSml29623 #ifdef __cplusplus 2716f45ec7bSml29623 } 2726f45ec7bSml29623 #endif 2736f45ec7bSml29623 2746f45ec7bSml29623 #endif /* _NPI_TXDMA_H */ 275