xref: /illumos-gate/usr/src/uts/common/io/nxge/npi/npi_vir.h (revision 2d6eb4a5)
16f45ec7bSml29623 /*
26f45ec7bSml29623  * CDDL HEADER START
36f45ec7bSml29623  *
46f45ec7bSml29623  * The contents of this file are subject to the terms of the
56f45ec7bSml29623  * Common Development and Distribution License (the "License").
66f45ec7bSml29623  * You may not use this file except in compliance with the License.
76f45ec7bSml29623  *
86f45ec7bSml29623  * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
96f45ec7bSml29623  * or http://www.opensolaris.org/os/licensing.
106f45ec7bSml29623  * See the License for the specific language governing permissions
116f45ec7bSml29623  * and limitations under the License.
126f45ec7bSml29623  *
136f45ec7bSml29623  * When distributing Covered Code, include this CDDL HEADER in each
146f45ec7bSml29623  * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
156f45ec7bSml29623  * If applicable, add the following below this CDDL HEADER, with the
166f45ec7bSml29623  * fields enclosed by brackets "[]" replaced with your own identifying
176f45ec7bSml29623  * information: Portions Copyright [yyyy] [name of copyright owner]
186f45ec7bSml29623  *
196f45ec7bSml29623  * CDDL HEADER END
206f45ec7bSml29623  */
216f45ec7bSml29623 /*
22*678453a8Sspeer  * Copyright 2008 Sun Microsystems, Inc.  All rights reserved.
236f45ec7bSml29623  * Use is subject to license terms.
246f45ec7bSml29623  */
256f45ec7bSml29623 
266f45ec7bSml29623 #ifndef _NPI_VIR_H
276f45ec7bSml29623 #define	_NPI_VIR_H
286f45ec7bSml29623 
296f45ec7bSml29623 #ifdef	__cplusplus
306f45ec7bSml29623 extern "C" {
316f45ec7bSml29623 #endif
326f45ec7bSml29623 
336f45ec7bSml29623 #include <npi.h>
346f45ec7bSml29623 #include <nxge_hw.h>
356f45ec7bSml29623 
366f45ec7bSml29623 /*
376f45ec7bSml29623  * Virtualization and Logical devices NPI error codes
386f45ec7bSml29623  */
396f45ec7bSml29623 #define	FUNCID_INVALID		PORT_INVALID
406f45ec7bSml29623 #define	VIR_ERR_ST		(VIR_BLK_ID << NPI_BLOCK_ID_SHIFT)
416f45ec7bSml29623 #define	VIR_ID_SHIFT(n)		(n << NPI_PORT_CHAN_SHIFT)
426f45ec7bSml29623 
436f45ec7bSml29623 #define	VIR_HW_BUSY		(NPI_BK_HW_ERROR_START | 0x1)
446f45ec7bSml29623 
456f45ec7bSml29623 #define	VIR_TAS_BUSY		(NPI_BK_ERROR_START | 0x1)
466f45ec7bSml29623 #define	VIR_TAS_NOTREAD	(NPI_BK_ERROR_START | 0x2)
476f45ec7bSml29623 
486f45ec7bSml29623 #define	VIR_SR_RESET		(NPI_BK_ERROR_START | 0x3)
496f45ec7bSml29623 #define	VIR_SR_FREE		(NPI_BK_ERROR_START | 0x4)
506f45ec7bSml29623 #define	VIR_SR_BUSY		(NPI_BK_ERROR_START | 0x5)
516f45ec7bSml29623 #define	VIR_SR_INVALID		(NPI_BK_ERROR_START | 0x6)
526f45ec7bSml29623 #define	VIR_SR_NOTOWNER	(NPI_BK_ERROR_START | 0x7)
536f45ec7bSml29623 #define	VIR_SR_INITIALIZED	(NPI_BK_ERROR_START | 0x8)
546f45ec7bSml29623 
556f45ec7bSml29623 #define	VIR_MPC_DENY		(NPI_BK_ERROR_START | 0x10)
566f45ec7bSml29623 
576f45ec7bSml29623 #define	VIR_BD_FUNC_INVALID	(NPI_BK_ERROR_START | 0x20)
586f45ec7bSml29623 #define	VIR_BD_REG_INVALID	(NPI_BK_ERROR_START | 0x21)
596f45ec7bSml29623 #define	VIR_BD_ID_INVALID	(NPI_BK_ERROR_START | 0x22)
606f45ec7bSml29623 #define	VIR_BD_TXDMA_INVALID	(NPI_BK_ERROR_START | 0x23)
616f45ec7bSml29623 #define	VIR_BD_RXDMA_INVALID	(NPI_BK_ERROR_START | 0x24)
626f45ec7bSml29623 
636f45ec7bSml29623 #define	VIR_LD_INVALID		(NPI_BK_ERROR_START | 0x30)
646f45ec7bSml29623 #define	VIR_LDG_INVALID		(NPI_BK_ERROR_START | 0x31)
656f45ec7bSml29623 #define	VIR_LDSV_INVALID	(NPI_BK_ERROR_START | 0x32)
666f45ec7bSml29623 
676f45ec7bSml29623 #define	VIR_INTM_TM_INVALID	(NPI_BK_ERROR_START | 0x33)
686f45ec7bSml29623 #define	VIR_TM_RES_INVALID	(NPI_BK_ERROR_START | 0x34)
696f45ec7bSml29623 #define	VIR_SID_VEC_INVALID	(NPI_BK_ERROR_START | 0x35)
706f45ec7bSml29623 
716f45ec7bSml29623 #define	NPI_VIR_OCODE_INVALID(n) (VIR_ID_SHIFT(n) | VIR_ERR_ST | OPCODE_INVALID)
726f45ec7bSml29623 #define	NPI_VIR_FUNC_INVALID(n)	 (VIR_ID_SHIFT(n) | VIR_ERR_ST | FUNCID_INVALID)
736f45ec7bSml29623 #define	NPI_VIR_CN_INVALID(n)	(VIR_ID_SHIFT(n) | VIR_ERR_ST | CHANNEL_INVALID)
746f45ec7bSml29623 
756f45ec7bSml29623 /*
766f45ec7bSml29623  * Errors codes of shared register functions.
776f45ec7bSml29623  */
786f45ec7bSml29623 #define	NPI_VIR_TAS_BUSY(n)	(VIR_ID_SHIFT(n) | VIR_ERR_ST | VIR_TAS_BUSY)
796f45ec7bSml29623 #define	NPI_VIR_TAS_NOTREAD(n)	(VIR_ID_SHIFT(n) | VIR_ERR_ST | VIR_TAS_NOTREAD)
806f45ec7bSml29623 #define	NPI_VIR_SR_RESET(n)	(VIR_ID_SHIFT(n) | VIR_ERR_ST | VIR_SR_RESET)
816f45ec7bSml29623 #define	NPI_VIR_SR_FREE(n)	(VIR_ID_SHIFT(n) | VIR_ERR_ST | VIR_SR_FREE)
826f45ec7bSml29623 #define	NPI_VIR_SR_BUSY(n)	(VIR_ID_SHIFT(n) | VIR_ERR_ST | VIR_SR_BUSY)
836f45ec7bSml29623 #define	NPI_VIR_SR_INVALID(n)	(VIR_ID_SHIFT(n) | VIR_ERR_ST | VIR_SR_INVALID)
846f45ec7bSml29623 #define	NPI_VIR_SR_NOTOWNER(n)	(VIR_ID_SHIFT(n) | VIR_ERR_ST | VIR_SR_NOTOWNER)
856f45ec7bSml29623 #define	NPI_VIR_SR_INITIALIZED(n) (VIR_ID_SHIFT(n) | \
866f45ec7bSml29623 					VIR_ERR_ST | VIR_SR_INITIALIZED)
876f45ec7bSml29623 
886f45ec7bSml29623 /*
896f45ec7bSml29623  * Error codes of muti-partition control register functions.
906f45ec7bSml29623  */
916f45ec7bSml29623 #define	NPI_VIR_MPC_DENY	(VIR_ERR_ST | VIR_MPU_DENY)
926f45ec7bSml29623 
936f45ec7bSml29623 /*
946f45ec7bSml29623  * Error codes of DMA binding functions.
956f45ec7bSml29623  */
966f45ec7bSml29623 #define	NPI_VIR_BD_FUNC_INVALID(n)	(VIR_ID_SHIFT(n) | \
976f45ec7bSml29623 					VIR_ERR_ST | VIR_BD_FUNC_INVALID)
986f45ec7bSml29623 #define	NPI_VIR_BD_REG_INVALID(n)	(VIR_ID_SHIFT(n) | \
996f45ec7bSml29623 					VIR_ERR_ST | VIR_BD_REG_INVALID)
1006f45ec7bSml29623 #define	NPI_VIR_BD_ID_INVALID(n)	(VIR_ID_SHIFT(n) | \
1016f45ec7bSml29623 					VIR_ERR_ST | VIR_BD_ID_INVALID)
1026f45ec7bSml29623 #define	NPI_VIR_BD_TXDMA_INVALID(n)	(VIR_ID_SHIFT(n) | \
1036f45ec7bSml29623 					VIR_ERR_ST | VIR_BD_TXDMA_INVALID)
1046f45ec7bSml29623 #define	NPI_VIR_BD_RXDMA_INVALID(n)	(VIR_ID_SHIFT(n) | \
1056f45ec7bSml29623 					VIR_ERR_ST | VIR_BD_RXDMA_INVALID)
1066f45ec7bSml29623 
1076f45ec7bSml29623 /*
1086f45ec7bSml29623  * Error codes of logical devices and groups functions.
1096f45ec7bSml29623  */
1106f45ec7bSml29623 #define	NPI_VIR_LD_INVALID(n) 	(VIR_ID_SHIFT(n) | VIR_ERR_ST | VIR_LD_INVALID)
1116f45ec7bSml29623 #define	NPI_VIR_LDG_INVALID(n)	(VIR_ID_SHIFT(n) | VIR_ERR_ST | VIR_LDG_INVALID)
1126f45ec7bSml29623 #define	NPI_VIR_LDSV_INVALID(n) (VIR_ID_SHIFT(n) | \
1136f45ec7bSml29623 					VIR_ERR_ST | VIR_LDSV_INVALID)
1146f45ec7bSml29623 #define	NPI_VIR_INTM_TM_INVALID(n)	(VIR_ID_SHIFT(n) | \
1156f45ec7bSml29623 					VIR_ERR_ST | VIR_INTM_TM_INVALID)
1166f45ec7bSml29623 #define	NPI_VIR_TM_RES_INVALID		(VIR_ERR_ST | VIR_TM_RES_INVALID)
1176f45ec7bSml29623 #define	NPI_VIR_SID_VEC_INVALID(n)	(VIR_ID_SHIFT(n) | \
1186f45ec7bSml29623 						VIR_ERR_ST | VIR_TM_RES_INVALID)
1196f45ec7bSml29623 
1206f45ec7bSml29623 /*
1216f45ec7bSml29623  * Bit definition ([15:0] of the shared register
1226f45ec7bSml29623  * used by the driver as locking mechanism.
1236f45ec7bSml29623  *	[1:0]		lock state (RESET, FREE, BUSY)
1246f45ec7bSml29623  *	[3:2]		function ID (owner)
1256f45ec7bSml29623  *	[11:4]		Implementation specific states
1266f45ec7bSml29623  *	[15:12]  	Individual function state
1276f45ec7bSml29623  */
1286f45ec7bSml29623 #define	NPI_DEV_SR_LOCK_ST_RESET	0
1296f45ec7bSml29623 #define	NPI_DEV_SR_LOCK_ST_FREE		1
1306f45ec7bSml29623 #define	NPI_DEV_SR_LOCK_ST_BUSY		2
1316f45ec7bSml29623 
1326f45ec7bSml29623 #define	NPI_DEV_SR_LOCK_ST_SHIFT	0
1336f45ec7bSml29623 #define	NPI_DEV_SR_LOCK_ST_MASK		0x03
1346f45ec7bSml29623 #define	NPI_DEV_SR_LOCK_FID_SHIFT	2
1356f45ec7bSml29623 #define	NPI_DEV_SR_LOCK_FID_MASK	0x0C
1366f45ec7bSml29623 
1376f45ec7bSml29623 #define	NPI_DEV_SR_IMPL_ST_SHIFT	4
1386f45ec7bSml29623 #define	NPI_DEV_SR_IMPL_ST_MASK	0xfff0
1396f45ec7bSml29623 
1406f45ec7bSml29623 #define	NPI_GET_LOCK_OWNER(sr)		((sr & NPI_DEV_SR_LOCK_FID_MASK) \
1416f45ec7bSml29623 						>> NPI_DEV_SR_LOCK_FID_SHIFT)
1426f45ec7bSml29623 #define	NPI_GET_LOCK_ST(sr)		(sr & NPI_DEV_SR_LOCK_ST_MASK)
1436f45ec7bSml29623 #define	NPI_GET_LOCK_IMPL_ST(sr)	((sr & NPI_DEV_SR_IMPL_ST_MASK) \
1446f45ec7bSml29623 						>> NPI_DEV_SR_IMPL_ST_SHIFT)
1456f45ec7bSml29623 
1466f45ec7bSml29623 /*
1476f45ec7bSml29623  * DMA channel binding definitions.
1486f45ec7bSml29623  */
1496f45ec7bSml29623 #define	DMA_BIND_VADDR_VALIDATE(fn, rn, id, status)			\
1506f45ec7bSml29623 {									\
1516f45ec7bSml29623 	status = NPI_SUCCESS;						\
1526f45ec7bSml29623 	if (!TXDMA_FUNC_VALID(fn)) {					\
1536f45ec7bSml29623 		status = (NPI_FAILURE | NPI_VIR_BD_FUNC_INVALID(fn));	\
1546f45ec7bSml29623 	} else if (!SUBREGION_VALID(rn)) {				\
1556f45ec7bSml29623 		status = (NPI_FAILURE | NPI_VIR_BD_REG_INVALID(rn));	\
1566f45ec7bSml29623 	} else if (!VIR_PAGE_INDEX_VALID(id)) {				\
1576f45ec7bSml29623 		status = (NPI_FAILURE | NPI_VIR_BD_ID_INVALID(id));	\
1586f45ec7bSml29623 	}								\
1596f45ec7bSml29623 }
1606f45ec7bSml29623 
1616f45ec7bSml29623 #define	DMA_BIND_TX_VALIDATE(n, status)					\
1626f45ec7bSml29623 {									\
1636f45ec7bSml29623 	status = NPI_SUCCESS;						\
1646f45ec7bSml29623 	if (!TXDMA_CHANNEL_VALID(n)) {					\
1656f45ec7bSml29623 		status = (NPI_FAILURE | NPI_VIR_BD_TXDMA_INVALID(n));	\
1666f45ec7bSml29623 	}								\
1676f45ec7bSml29623 }
1686f45ec7bSml29623 
1696f45ec7bSml29623 #define	DMA_BIND_RX_VALIDATE(n, status)					\
1706f45ec7bSml29623 {									\
1716f45ec7bSml29623 	status = NPI_SUCCESS;						\
1726f45ec7bSml29623 	if (!VRXDMA_CHANNEL_VALID(n)) {					\
1736f45ec7bSml29623 		status = (NPI_FAILURE | NPI_VIR_BD_RXDMA_INVALID(n));	\
1746f45ec7bSml29623 	}								\
1756f45ec7bSml29623 }
1766f45ec7bSml29623 
1776f45ec7bSml29623 #define	DMA_BIND_STEP			8
1786f45ec7bSml29623 #define	DMA_BIND_REG_OFFSET(fn, rn, id)	(DMA_BIND_STEP * \
1796f45ec7bSml29623 					(fn * 2 * VIR_PAGE_INDEX_MAX + \
1806f45ec7bSml29623 					rn * VIR_PAGE_INDEX_MAX) + id)
1816f45ec7bSml29623 
1826f45ec7bSml29623 /*
1836f45ec7bSml29623  * NPI defined data structure to program the DMA binding register.
1846f45ec7bSml29623  */
1856f45ec7bSml29623 typedef struct _fzc_dma_bind {
1866f45ec7bSml29623 	uint8_t		function_id;	/* 0 to 3 */
1876f45ec7bSml29623 	uint8_t		sub_vir_region;	/* 0 or 1 */
1886f45ec7bSml29623 	uint8_t		vir_index;	/* 0 to 7 */
1896f45ec7bSml29623 	boolean_t	tx_bind;	/* set 1 to bind */
1906f45ec7bSml29623 	uint8_t		tx_channel;	/* hardware channel number (0 - 23) */
1916f45ec7bSml29623 	boolean_t	rx_bind;	/* set 1 to bind */
1926f45ec7bSml29623 	uint8_t		rx_channel;	/* hardware channel number (0 - 15) */
1936f45ec7bSml29623 } fzc_dma_bind_t, *p_fzc_dma_bind;
1946f45ec7bSml29623 
1956f45ec7bSml29623 /*
1966f45ec7bSml29623  * Logical device definitions.
1976f45ec7bSml29623  */
1986f45ec7bSml29623 #define	LD_NUM_STEP		8
1996f45ec7bSml29623 #define	LD_NUM_OFFSET(ld)	(ld * LDG_NUM_STEP)
2006f45ec7bSml29623 #define	LDG_NUM_STEP		8
2016f45ec7bSml29623 #define	LDG_NUM_OFFSET(ldg)	(ldg * LDG_NUM_STEP)
2026f45ec7bSml29623 #define	LDGNUM_OFFSET(ldg)	(ldg * LDG_NUM_STEP)
2036f45ec7bSml29623 #define	LDSV_STEP		8192
2046f45ec7bSml29623 #define	LDSVG_OFFSET(ldg)	(ldg * LDSV_STEP)
2056f45ec7bSml29623 #define	LDSV_OFFSET(ldv)	(ldv * LDSV_STEP)
2066f45ec7bSml29623 
2076f45ec7bSml29623 #define	LDSV_OFFSET_MASK(ld)			\
2086f45ec7bSml29623 	(((ld < NXGE_MAC_LD_START) ?		\
2096f45ec7bSml29623 	(LD_IM0_REG + LDSV_OFFSET(ld)) :	\
2106f45ec7bSml29623 	(LD_IM1_REG + LDSV_OFFSET((ld - NXGE_MAC_LD_START))))); \
2116f45ec7bSml29623 
2126f45ec7bSml29623 #define	LDG_SID_STEP		8
2136f45ec7bSml29623 #define	LDG_SID_OFFSET(ldg)	(ldg * LDG_SID_STEP)
2146f45ec7bSml29623 
2156f45ec7bSml29623 typedef enum {
2166f45ec7bSml29623 	LDF0,
2176f45ec7bSml29623 	LDF1
2186f45ec7bSml29623 } ldf_type_t;
2196f45ec7bSml29623 
2206f45ec7bSml29623 typedef enum {
2216f45ec7bSml29623 	VECTOR0,
2226f45ec7bSml29623 	VECTOR1,
2236f45ec7bSml29623 	VECTOR2
2246f45ec7bSml29623 } ldsv_type_t;
2256f45ec7bSml29623 
2266f45ec7bSml29623 /*
2276f45ec7bSml29623  * Definitions for the system interrupt data.
2286f45ec7bSml29623  */
2296f45ec7bSml29623 typedef struct _fzc_sid {
2306f45ec7bSml29623 	boolean_t	niu;
2316f45ec7bSml29623 	uint8_t		ldg;
2326f45ec7bSml29623 	uint8_t		func;
2336f45ec7bSml29623 	uint8_t		vector;
2346f45ec7bSml29623 } fzc_sid_t, *p_fzc_sid_t;
2356f45ec7bSml29623 
2366f45ec7bSml29623 /*
2376f45ec7bSml29623  * Virtualization and Interrupt Prototypes.
2386f45ec7bSml29623  */
2396f45ec7bSml29623 /*
2406f45ec7bSml29623  * npi_dev_func_sr_init():
2416f45ec7bSml29623  *	This function is called to initialize the device function
2426f45ec7bSml29623  *	shared register (set the software implementation lock
2436f45ec7bSml29623  *	state to FREE).
2446f45ec7bSml29623  * Parameters:
2456f45ec7bSml29623  *	handle		- NPI handle
2466f45ec7bSml29623  * Return:
2476f45ec7bSml29623  *	NPI_SUCCESS	- If initialization is complete successfully.
2486f45ec7bSml29623  *			  (set sr bits to free).
2496f45ec7bSml29623  *	Error:
2506f45ec7bSml29623  *	NPI_FAILURE
2516f45ec7bSml29623  *		VIR_TAS_BUSY
2526f45ec7bSml29623  */
2536f45ec7bSml29623 npi_status_t npi_dev_func_sr_init(npi_handle_t);
2546f45ec7bSml29623 
2556f45ec7bSml29623 /*
2566f45ec7bSml29623  * npi_dev_func_sr_lock_enter():
2576f45ec7bSml29623  *	This function is called to lock the function shared register
2586f45ec7bSml29623  *	by setting the lock state to busy.
2596f45ec7bSml29623  * Parameters:
2606f45ec7bSml29623  *	handle		- NPI handle
2616f45ec7bSml29623  * Return:
2626f45ec7bSml29623  *	NPI_SUCCESS	- If the function id can own the lock.
2636f45ec7bSml29623  *
2646f45ec7bSml29623  *	Error:
2656f45ec7bSml29623  *	NPI_FAILURE
2666f45ec7bSml29623  *		VIR_SR_RESET
2676f45ec7bSml29623  *		VIR_SR_BUSY
2686f45ec7bSml29623  *		VIR_SR_INVALID
2696f45ec7bSml29623  *		VIR_TAS_BUSY
2706f45ec7bSml29623  */
2716f45ec7bSml29623 npi_status_t npi_dev_func_sr_lock_enter(npi_handle_t);
2726f45ec7bSml29623 
2736f45ec7bSml29623 /*
2746f45ec7bSml29623  * npi_dev_func_sr_lock_free():
2756f45ec7bSml29623  *	This function is called to free the function shared register
2766f45ec7bSml29623  *	by setting the lock state to free.
2776f45ec7bSml29623  * Parameters:
2786f45ec7bSml29623  *	handle		- NPI handle
2796f45ec7bSml29623  * Return:
2806f45ec7bSml29623  *	NPI_SUCCESS	- If the function id can free the lock.
2816f45ec7bSml29623  *
2826f45ec7bSml29623  *	Error:
2836f45ec7bSml29623  *	NPI_FAILURE
2846f45ec7bSml29623  *		VIR_SR_NOTOWNER
2856f45ec7bSml29623  *		VIR_TAS_NOTREAD
2866f45ec7bSml29623  */
2876f45ec7bSml29623 npi_status_t npi_dev_func_sr_lock_free(npi_handle_t);
2886f45ec7bSml29623 
2896f45ec7bSml29623 /*
2906f45ec7bSml29623  * npi_dev_func_sr_funcid_get():
2916f45ec7bSml29623  *	This function is called to get the caller's function ID.
2926f45ec7bSml29623  *	(based on address bits [25:26] on read access.
2936f45ec7bSml29623  *	(After read, the TAS bit is always set to 1. Software needs
2946f45ec7bSml29623  *	to write 0 to clear.) This function will write 0 to clear
2956f45ec7bSml29623  *	the TAS bit if we own it.
2966f45ec7bSml29623  * Parameters:
2976f45ec7bSml29623  *	handle		- NPI handle
2986f45ec7bSml29623  *	funcid_p	- pointer to store the function id.
2996f45ec7bSml29623  * Return:
3006f45ec7bSml29623  *	NPI_SUCCESS	- If get function id is complete successfully.
3016f45ec7bSml29623  *
3026f45ec7bSml29623  *	Error:
3036f45ec7bSml29623  */
3046f45ec7bSml29623 npi_status_t npi_dev_func_sr_funcid_get(npi_handle_t, uint8_t *);
3056f45ec7bSml29623 
3066f45ec7bSml29623 /*
3076f45ec7bSml29623  * npi_dev_func_sr_sr_raw_get():
3086f45ec7bSml29623  *	This function is called to get the shared register value.
3096f45ec7bSml29623  *	(After read, the TAS bit is always set to 1. Software needs
3106f45ec7bSml29623  *	to write 0 to clear if we own it.)
3116f45ec7bSml29623  *
3126f45ec7bSml29623  * Parameters:
3136f45ec7bSml29623  *	handle		- NPI handle
3146f45ec7bSml29623  *	sr_p		- pointer to store the shared value of this register.
3156f45ec7bSml29623  *
3166f45ec7bSml29623  * Return:
3176f45ec7bSml29623  *	NPI_SUCCESS		- If shared value get is complete successfully.
3186f45ec7bSml29623  *
3196f45ec7bSml29623  *	Error:
3206f45ec7bSml29623  */
3216f45ec7bSml29623 npi_status_t npi_dev_func_sr_sr_raw_get(npi_handle_t, uint16_t *);
3226f45ec7bSml29623 
3236f45ec7bSml29623 /*
3246f45ec7bSml29623  * npi_dev_func_sr_sr_get():
3256f45ec7bSml29623  *	This function is called to get the shared register value.
3266f45ec7bSml29623  *	(After read, the TAS bit is always set to 1. Software needs
3276f45ec7bSml29623  *	to write 0 to clear if we own it.)
3286f45ec7bSml29623  *
3296f45ec7bSml29623  * Parameters:
3306f45ec7bSml29623  *	handle		- NPI handle
3316f45ec7bSml29623  *	sr_p		- pointer to store the shared value of this register.
3326f45ec7bSml29623  *		    . this will get only non-lock, non-function id portion
3336f45ec7bSml29623  *              . of the register
3346f45ec7bSml29623  *
3356f45ec7bSml29623  *
3366f45ec7bSml29623  * Return:
3376f45ec7bSml29623  *	NPI_SUCCESS		- If shared value get is complete successfully.
3386f45ec7bSml29623  *
3396f45ec7bSml29623  *	Error:
3406f45ec7bSml29623  */
3416f45ec7bSml29623 
3426f45ec7bSml29623 npi_status_t npi_dev_func_sr_sr_get(npi_handle_t, uint16_t *);
3436f45ec7bSml29623 
3446f45ec7bSml29623 /*
3456f45ec7bSml29623  * npi_dev_func_sr_sr_get_set_clear():
3466f45ec7bSml29623  *	This function is called to set the shared register value.
3476f45ec7bSml29623  *	(Shared register must be read first. If tas bit is 0, then
3486f45ec7bSml29623  *	it implies that the software can proceed to set). After
3496f45ec7bSml29623  *	setting, tas bit will be cleared.
3506f45ec7bSml29623  * Parameters:
3516f45ec7bSml29623  *	handle		- NPI handle
3526f45ec7bSml29623  *	impl_sr		- shared value to set (only the 8 bit
3536f45ec7bSml29623  *			  implementation specific state info).
3546f45ec7bSml29623  *
3556f45ec7bSml29623  * Return:
3566f45ec7bSml29623  *	NPI_SUCCESS		- If shared value is set successfully.
3576f45ec7bSml29623  *
3586f45ec7bSml29623  *	Error:
3596f45ec7bSml29623  *	NPI_FAILURE
3606f45ec7bSml29623  *		VIR_TAS_BUSY
3616f45ec7bSml29623  */
3626f45ec7bSml29623 npi_status_t npi_dev_func_sr_sr_get_set_clear(npi_handle_t,
3636f45ec7bSml29623 					    uint16_t);
3646f45ec7bSml29623 
3656f45ec7bSml29623 /*
3666f45ec7bSml29623  * npi_dev_func_sr_sr_set_only():
3676f45ec7bSml29623  *	This function is called to only set the shared register value.
3686f45ec7bSml29623  * Parameters:
3696f45ec7bSml29623  *	handle		- NPI handle
3706f45ec7bSml29623  *	impl_sr		- shared value to set.
3716f45ec7bSml29623  *
3726f45ec7bSml29623  * Return:
3736f45ec7bSml29623  *	NPI_SUCCESS		- If shared value is set successfully.
3746f45ec7bSml29623  *
3756f45ec7bSml29623  *	Error:
3766f45ec7bSml29623  *	NPI_FAILURE
3776f45ec7bSml29623  *		VIR_TAS_BUSY
3786f45ec7bSml29623  */
3796f45ec7bSml29623 npi_status_t npi_dev_func_sr_sr_set_only(npi_handle_t, uint16_t);
3806f45ec7bSml29623 
3816f45ec7bSml29623 /*
3826f45ec7bSml29623  * npi_dev_func_sr_busy():
3836f45ec7bSml29623  *	This function is called to see if we can own the device.
3846f45ec7bSml29623  *	It will not reset the tas bit.
3856f45ec7bSml29623  * Parameters:
3866f45ec7bSml29623  *	handle		- NPI handle
3876f45ec7bSml29623  *	busy_p		- pointer to store busy flag.
3886f45ec7bSml29623  *				(B_TRUE: device is in use, B_FALSE: free).
3896f45ec7bSml29623  * Return:
3906f45ec7bSml29623  *	NPI_SUCCESS		- If tas bit is read successfully.
3916f45ec7bSml29623  *	Error:
3926f45ec7bSml29623  */
3936f45ec7bSml29623 npi_status_t npi_dev_func_sr_busy(npi_handle_t, boolean_t *);
3946f45ec7bSml29623 
3956f45ec7bSml29623 /*
3966f45ec7bSml29623  * npi_dev_func_sr_tas_get():
3976f45ec7bSml29623  *	This function is called to get the tas bit
3986f45ec7bSml29623  *	(after read, this bit is always set to 1, software write 0
3996f45ec7bSml29623  *	 to clear it).
4006f45ec7bSml29623  *
4016f45ec7bSml29623  * Parameters:
4026f45ec7bSml29623  *	handle		- NPI handle
4036f45ec7bSml29623  *	tas_p		- pointer to store the tas value
4046f45ec7bSml29623  *
4056f45ec7bSml29623  * Return:
4066f45ec7bSml29623  *	NPI_SUCCESS		- If tas value get is complete successfully.
4076f45ec7bSml29623  *	Error:
4086f45ec7bSml29623  */
4096f45ec7bSml29623 npi_status_t npi_dev_func_sr_tas_get(npi_handle_t, uint8_t *);
4106f45ec7bSml29623 
4116f45ec7bSml29623 /*
4126f45ec7bSml29623  * npi_fzc_mpc_set():
4136f45ec7bSml29623  *	This function is called to enable the write access
4146f45ec7bSml29623  *	to FZC region to function zero.
4156f45ec7bSml29623  * Parameters:
4166f45ec7bSml29623  *	handle		- NPI handle
4176f45ec7bSml29623  * Return:
4186f45ec7bSml29623  *	NPI_SUCCESS	-
4196f45ec7bSml29623  *	Error:
4206f45ec7bSml29623  */
4216f45ec7bSml29623 npi_status_t npi_fzc_mpc_set(npi_handle_t, boolean_t);
4226f45ec7bSml29623 
4236f45ec7bSml29623 /*
4246f45ec7bSml29623  * npi_fzc_mpc_get():
4256f45ec7bSml29623  *	This function is called to get the access mode.
4266f45ec7bSml29623  * Parameters:
4276f45ec7bSml29623  *	handle		- NPI handle
4286f45ec7bSml29623  * Return:
4296f45ec7bSml29623  *	NPI_SUCCESS	-
4306f45ec7bSml29623  *
4316f45ec7bSml29623  */
4326f45ec7bSml29623 npi_status_t npi_fzc_mpc_get(npi_handle_t, boolean_t *);
4336f45ec7bSml29623 
4346f45ec7bSml29623 /*
4356f45ec7bSml29623  * npi_fzc_dma_bind_set():
4366f45ec7bSml29623  *	This function is called to set DMA binding register.
4376f45ec7bSml29623  * Parameters:
4386f45ec7bSml29623  *	handle		- NPI handle
4396f45ec7bSml29623  *	dma_bind	- NPI defined data structure that
4406f45ec7bSml29623  *			  contains the tx/rx channel binding info.
4416f45ec7bSml29623  *			  to set.
4426f45ec7bSml29623  * Return:
4436f45ec7bSml29623  *	NPI_SUCCESS	-
4446f45ec7bSml29623  *	Error:
4456f45ec7bSml29623  *	NPI_FAILURE
4466f45ec7bSml29623  *
4476f45ec7bSml29623  */
4486f45ec7bSml29623 npi_status_t npi_fzc_dma_bind_set(npi_handle_t, fzc_dma_bind_t);
4496f45ec7bSml29623 
4506f45ec7bSml29623 /*
451*678453a8Sspeer  * npi_fzc_dma_bind_get():
452*678453a8Sspeer  *	This function is called to get a DMA binding register.
453*678453a8Sspeer  * Parameters:
454*678453a8Sspeer  *	handle		- NPI handle
455*678453a8Sspeer  *	dma_bind	- NPI defined data structure that
456*678453a8Sspeer  *			  contains the tx/rx channel binding info.
457*678453a8Sspeer  *	value		- Where to put the register value.
458*678453a8Sspeer  * Return:
459*678453a8Sspeer  *	NPI_SUCCESS	-
460*678453a8Sspeer  *	Error:
461*678453a8Sspeer  *	NPI_FAILURE
462*678453a8Sspeer  *
463*678453a8Sspeer  */
464*678453a8Sspeer npi_status_t npi_fzc_dma_bind_get(npi_handle_t, fzc_dma_bind_t, uint64_t *);
465*678453a8Sspeer 
466*678453a8Sspeer /*
4676f45ec7bSml29623  * npi_fzc_ldg_num_set():
4686f45ec7bSml29623  *	This function is called to set up a logical group number that
4696f45ec7bSml29623  *	a logical device belongs to.
4706f45ec7bSml29623  * Parameters:
4716f45ec7bSml29623  *	handle		- NPI handle
4726f45ec7bSml29623  *	ld		- logical device number (0 - 68)
4736f45ec7bSml29623  *	ldg		- logical device group number (0 - 63)
4746f45ec7bSml29623  * Return:
4756f45ec7bSml29623  *	NPI_SUCCESS	-
4766f45ec7bSml29623  *	Error:
4776f45ec7bSml29623  *	NPI_FAILURE
4786f45ec7bSml29623  *
4796f45ec7bSml29623  */
4806f45ec7bSml29623 npi_status_t npi_fzc_ldg_num_set(npi_handle_t, uint8_t, uint8_t);
4816f45ec7bSml29623 
4826f45ec7bSml29623 /*
4836f45ec7bSml29623  * npi_fzc_ldg_num_get():
4846f45ec7bSml29623  *	This function is called to get the logical device group that
4856f45ec7bSml29623  *	a logical device belongs to.
4866f45ec7bSml29623  * Parameters:
4876f45ec7bSml29623  *	handle		- NPI handle
4886f45ec7bSml29623  *	ld		- logical device number (0 - 68)
4896f45ec7bSml29623  *	*ldg_p		- pointer to store its group number.
4906f45ec7bSml29623  * Return:
4916f45ec7bSml29623  *	NPI_SUCCESS	-
4926f45ec7bSml29623  *	Error:
4936f45ec7bSml29623  *	NPI_FAILURE
4946f45ec7bSml29623  */
4956f45ec7bSml29623 npi_status_t npi_fzc_ldg_num_get(npi_handle_t, uint8_t,
4966f45ec7bSml29623 		uint8_t *);
4976f45ec7bSml29623 
4986f45ec7bSml29623 npi_status_t npi_ldsv_ldfs_get(npi_handle_t, uint8_t,
4996f45ec7bSml29623 		uint64_t *, uint64_t *, uint64_t *);
5006f45ec7bSml29623 /*
5016f45ec7bSml29623  * npi_ldsv_get():
5026f45ec7bSml29623  *	This function is called to get device state vectors.
5036f45ec7bSml29623  * Parameters:
5046f45ec7bSml29623  *	handle		- NPI handle
5056f45ec7bSml29623  *	ldg		- logical device group (0 - 63)
5066f45ec7bSml29623  *	ldf_type	- either LDF0 (0) or LDF1 (1)
5076f45ec7bSml29623  *	vector		- vector type (0, 1 or 2)
5086f45ec7bSml29623  *	*ldf_p		- pointer to store its flag bits.
5096f45ec7bSml29623  * Return:
5106f45ec7bSml29623  *	NPI_SUCCESS	-
5116f45ec7bSml29623  *	Error:
5126f45ec7bSml29623  *	NPI_FAILURE
5136f45ec7bSml29623  */
5146f45ec7bSml29623 npi_status_t npi_ldsv_get(npi_handle_t, uint8_t, ldsv_type_t,
5156f45ec7bSml29623 		uint64_t *);
5166f45ec7bSml29623 
5176f45ec7bSml29623 /*
5186f45ec7bSml29623  * npi_ldsv_ld_get():
5196f45ec7bSml29623  *	This function is called to get the flag bit value of a device.
5206f45ec7bSml29623  * Parameters:
5216f45ec7bSml29623  *	handle		- NPI handle
5226f45ec7bSml29623  *	ldg		- logical device group (0 - 63)
5236f45ec7bSml29623  *	ld		- logical device (0 - 68)
5246f45ec7bSml29623  *	ldf_type	- either LDF0 (0) or LDF1 (1)
5256f45ec7bSml29623  *	vector		- vector type (0, 1 or 2)
5266f45ec7bSml29623  *	*ldf_p		- pointer to store its flag bits.
5276f45ec7bSml29623  * Return:
5286f45ec7bSml29623  *	NPI_SUCCESS	-
5296f45ec7bSml29623  *	Error:
5306f45ec7bSml29623  *	NPI_FAILURE
5316f45ec7bSml29623  */
5326f45ec7bSml29623 npi_status_t npi_ldsv_ld_get(npi_handle_t, uint8_t, uint8_t,
5336f45ec7bSml29623 		ldsv_type_t, ldf_type_t, boolean_t *);
5346f45ec7bSml29623 /*
5356f45ec7bSml29623  * npi_ldsv_ld_ldf0_get():
5366f45ec7bSml29623  *	This function is called to get the ldf0 bit value of a device.
5376f45ec7bSml29623  * Parameters:
5386f45ec7bSml29623  *	handle		- NPI handle
5396f45ec7bSml29623  *	ldg		- logical device group (0 - 63)
5406f45ec7bSml29623  *	ld		- logical device (0 - 68)
5416f45ec7bSml29623  *	*ldf_p		- pointer to store its flag bits.
5426f45ec7bSml29623  * Return:
5436f45ec7bSml29623  *	NPI_SUCCESS	-
5446f45ec7bSml29623  *	Error:
5456f45ec7bSml29623  *	NPI_FAILURE
5466f45ec7bSml29623  */
5476f45ec7bSml29623 npi_status_t npi_ldsv_ld_ldf0_get(npi_handle_t, uint8_t, uint8_t,
5486f45ec7bSml29623 		boolean_t *);
5496f45ec7bSml29623 
5506f45ec7bSml29623 /*
5516f45ec7bSml29623  * npi_ldsv_ld_ldf1_get():
5526f45ec7bSml29623  *	This function is called to get the ldf1 bit value of a device.
5536f45ec7bSml29623  * Parameters:
5546f45ec7bSml29623  *	handle		- NPI handle
5556f45ec7bSml29623  *	ldg		- logical device group (0 - 63)
5566f45ec7bSml29623  *	ld		- logical device (0 - 68)
5576f45ec7bSml29623  *	*ldf_p		- pointer to store its flag bits.
5586f45ec7bSml29623  * Return:
5596f45ec7bSml29623  *	NPI_SUCCESS	-
5606f45ec7bSml29623  *	Error:
5616f45ec7bSml29623  *	NPI_FAILURE
5626f45ec7bSml29623  */
5636f45ec7bSml29623 npi_status_t npi_ldsv_ld_ldf1_get(npi_handle_t, uint8_t, uint8_t,
5646f45ec7bSml29623 		boolean_t *);
5656f45ec7bSml29623 /*
5666f45ec7bSml29623  * npi_intr_mask_set():
5676f45ec7bSml29623  *	This function is called to select the mask bits for both ldf0 and ldf1.
5686f45ec7bSml29623  * Parameters:
5696f45ec7bSml29623  *	handle		- NPI handle
5706f45ec7bSml29623  *	ld		- logical device (0 - 68)
5716f45ec7bSml29623  *	ldf_mask	- mask value to set (both ldf0 and ldf1).
5726f45ec7bSml29623  * Return:
5736f45ec7bSml29623  *	NPI_SUCCESS	-
5746f45ec7bSml29623  *	Error:
5756f45ec7bSml29623  *	NPI_FAILURE
5766f45ec7bSml29623  */
5776f45ec7bSml29623 npi_status_t npi_intr_mask_set(npi_handle_t, uint8_t,
5786f45ec7bSml29623 			uint8_t);
5796f45ec7bSml29623 
5806f45ec7bSml29623 /*
5816f45ec7bSml29623  * npi_intr_mask_get():
5826f45ec7bSml29623  *	This function is called to get the mask bits.
5836f45ec7bSml29623  * Parameters:
5846f45ec7bSml29623  *	handle		- NPI handle
5856f45ec7bSml29623  *	ld		- logical device (0 - 68)
5866f45ec7bSml29623  *	ldf_mask	- pointer to store mask bits info.
5876f45ec7bSml29623  * Return:
5886f45ec7bSml29623  *	NPI_SUCCESS	-
5896f45ec7bSml29623  *	Error:
5906f45ec7bSml29623  *	NPI_FAILURE
5916f45ec7bSml29623  */
5926f45ec7bSml29623 npi_status_t npi_intr_mask_get(npi_handle_t, uint8_t,
5936f45ec7bSml29623 			uint8_t *);
5946f45ec7bSml29623 
5956f45ec7bSml29623 /*
5966f45ec7bSml29623  * npi_intr_ldg_mgmt_set():
5976f45ec7bSml29623  *	This function is called to set interrupt timer and arm bit.
5986f45ec7bSml29623  * Parameters:
5996f45ec7bSml29623  *	handle		- NPI handle
6006f45ec7bSml29623  *	ldg		- logical device group (0 - 63)
6016f45ec7bSml29623  *	arm		- B_TRUE (arm) B_FALSE (disable)
6026f45ec7bSml29623  * Return:
6036f45ec7bSml29623  *	NPI_SUCCESS	-
6046f45ec7bSml29623  *	Error:
6056f45ec7bSml29623  *	NPI_FAILURE
6066f45ec7bSml29623  */
6076f45ec7bSml29623 npi_status_t npi_intr_ldg_mgmt_set(npi_handle_t, uint8_t,
6086f45ec7bSml29623 			boolean_t, uint8_t);
6096f45ec7bSml29623 
6106f45ec7bSml29623 
6116f45ec7bSml29623 /*
6126f45ec7bSml29623  * npi_intr_ldg_mgmt_timer_get():
6136f45ec7bSml29623  *	This function is called to get the timer counter
6146f45ec7bSml29623  * Parameters:
6156f45ec7bSml29623  *	handle		- NPI handle
6166f45ec7bSml29623  *	ldg		- logical device group (0 - 63)
6176f45ec7bSml29623  *	timer_p		- pointer to store the timer counter.
6186f45ec7bSml29623  * Return:
6196f45ec7bSml29623  *	NPI_SUCCESS	-
6206f45ec7bSml29623  *	Error:
6216f45ec7bSml29623  *	NPI_FAILURE
6226f45ec7bSml29623  */
6236f45ec7bSml29623 npi_status_t npi_intr_ldg_mgmt_timer_get(npi_handle_t, uint8_t,
6246f45ec7bSml29623 		uint8_t *);
6256f45ec7bSml29623 
6266f45ec7bSml29623 /*
6276f45ec7bSml29623  * npi_intr_ldg_mgmt_arm():
6286f45ec7bSml29623  *	This function is called to arm the group.
6296f45ec7bSml29623  * Parameters:
6306f45ec7bSml29623  *	handle		- NPI handle
6316f45ec7bSml29623  *	ldg		- logical device group (0 - 63)
6326f45ec7bSml29623  * Return:
6336f45ec7bSml29623  *	NPI_SUCCESS	-
6346f45ec7bSml29623  *	Error:
6356f45ec7bSml29623  *	NPI_FAILURE
6366f45ec7bSml29623  */
6376f45ec7bSml29623 npi_status_t npi_intr_ldg_mgmt_arm(npi_handle_t, uint8_t);
6386f45ec7bSml29623 
6396f45ec7bSml29623 /*
6406f45ec7bSml29623  * npi_fzc_ldg_timer_res_set():
6416f45ec7bSml29623  *	This function is called to set the timer resolution.
6426f45ec7bSml29623  * Parameters:
6436f45ec7bSml29623  *	handle		- NPI handle
6446f45ec7bSml29623  *	res		- timer resolution (# of system clocks)
6456f45ec7bSml29623  * Return:
6466f45ec7bSml29623  *	NPI_SUCCESS	-
6476f45ec7bSml29623  *	Error:
6486f45ec7bSml29623  *	NPI_FAILURE
6496f45ec7bSml29623  */
6506f45ec7bSml29623 npi_status_t npi_fzc_ldg_timer_res_set(npi_handle_t, uint32_t);
6516f45ec7bSml29623 
6526f45ec7bSml29623 /*
6536f45ec7bSml29623  * npi_fzc_ldg_timer_res_get():
6546f45ec7bSml29623  *	This function is called to get the timer resolution.
6556f45ec7bSml29623  * Parameters:
6566f45ec7bSml29623  *	handle		- NPI handle
6576f45ec7bSml29623  *	res_p		- pointer to store the timer resolution.
6586f45ec7bSml29623  * Return:
6596f45ec7bSml29623  *	NPI_SUCCESS	-
6606f45ec7bSml29623  *	Error:
6616f45ec7bSml29623  *	NPI_FAILURE
6626f45ec7bSml29623  */
6636f45ec7bSml29623 npi_status_t npi_fzc_ldg_timer_res_get(npi_handle_t, uint8_t *);
6646f45ec7bSml29623 
6656f45ec7bSml29623 /*
6666f45ec7bSml29623  * npi_fzc_sid_set():
6676f45ec7bSml29623  *	This function is called to set the system interrupt data.
6686f45ec7bSml29623  * Parameters:
6696f45ec7bSml29623  *	handle		- NPI handle
6706f45ec7bSml29623  *	ldg		- logical group (0 - 63)
6716f45ec7bSml29623  *	sid		- NPI defined data to set
6726f45ec7bSml29623  * Return:
6736f45ec7bSml29623  *	NPI_SUCCESS	-
6746f45ec7bSml29623  *	Error:
6756f45ec7bSml29623  *	NPI_FAILURE
6766f45ec7bSml29623  */
6776f45ec7bSml29623 npi_status_t npi_fzc_sid_set(npi_handle_t, fzc_sid_t);
6786f45ec7bSml29623 
6796f45ec7bSml29623 /*
6806f45ec7bSml29623  * npi_fzc_sid_get():
6816f45ec7bSml29623  *	This function is called to get the system interrupt data.
6826f45ec7bSml29623  * Parameters:
6836f45ec7bSml29623  *	handle		- NPI handle
6846f45ec7bSml29623  *	ldg		- logical group (0 - 63)
6856f45ec7bSml29623  *	sid_p		- NPI defined data to get
6866f45ec7bSml29623  * Return:
6876f45ec7bSml29623  *	NPI_SUCCESS	-
6886f45ec7bSml29623  *	Error:
6896f45ec7bSml29623  *	NPI_FAILURE
6906f45ec7bSml29623  */
6916f45ec7bSml29623 npi_status_t npi_fzc_sid_get(npi_handle_t, p_fzc_sid_t);
6926f45ec7bSml29623 npi_status_t npi_fzc_sys_err_mask_set(npi_handle_t, uint64_t);
6936f45ec7bSml29623 npi_status_t npi_fzc_sys_err_stat_get(npi_handle_t,
6946f45ec7bSml29623 						p_sys_err_stat_t);
6956f45ec7bSml29623 npi_status_t npi_vir_dump_pio_fzc_regs_one(npi_handle_t);
6966f45ec7bSml29623 npi_status_t npi_vir_dump_ldgnum(npi_handle_t);
6976f45ec7bSml29623 npi_status_t npi_vir_dump_ldsv(npi_handle_t);
6986f45ec7bSml29623 npi_status_t npi_vir_dump_imask0(npi_handle_t);
6996f45ec7bSml29623 npi_status_t npi_vir_dump_sid(npi_handle_t);
7006f45ec7bSml29623 #ifdef	__cplusplus
7016f45ec7bSml29623 }
7026f45ec7bSml29623 #endif
7036f45ec7bSml29623 
7046f45ec7bSml29623 #endif	/* _NPI_VIR_H */
705