1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License (the "License"). 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9 * or http://www.opensolaris.org/os/licensing. 10 * See the License for the specific language governing permissions 11 * and limitations under the License. 12 * 13 * When distributing Covered Code, include this CDDL HEADER in each 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15 * If applicable, add the following below this CDDL HEADER, with the 16 * fields enclosed by brackets "[]" replaced with your own identifying 17 * information: Portions Copyright [yyyy] [name of copyright owner] 18 * 19 * CDDL HEADER END 20 */ 21 22 /* 23 * Copyright 2007 Sun Microsystems, Inc. All rights reserved. 24 * Use is subject to license terms. 25 */ 26 27 #pragma ident "%Z%%M% %I% %E% SMI" 28 29 /* 30 * PCIC device/interrupt handler 31 * The "pcic" driver handles the Intel 82365SL, Cirrus Logic 32 * and Toshiba (and possibly other clones) PCMCIA adapter chip 33 * sets. It implements a subset of Socket Services as defined 34 * in the Solaris PCMCIA design documents 35 */ 36 37 /* 38 * currently defined "properties" 39 * 40 * clock-frequency bus clock frequency 41 * smi system management interrupt override 42 * need-mult-irq need status IRQ for each pair of sockets 43 * disable-audio don't route audio signal to speaker 44 */ 45 46 47 #include <sys/types.h> 48 #include <sys/inttypes.h> 49 #include <sys/param.h> 50 #include <sys/systm.h> 51 #include <sys/user.h> 52 #include <sys/buf.h> 53 #include <sys/file.h> 54 #include <sys/uio.h> 55 #include <sys/conf.h> 56 #include <sys/stat.h> 57 #include <sys/autoconf.h> 58 #include <sys/vtoc.h> 59 #include <sys/dkio.h> 60 #include <sys/ddi.h> 61 #include <sys/sunddi.h> 62 #include <sys/sunndi.h> 63 #include <sys/var.h> 64 #include <sys/callb.h> 65 #include <sys/open.h> 66 #include <sys/ddidmareq.h> 67 #include <sys/dma_engine.h> 68 #include <sys/kstat.h> 69 #include <sys/kmem.h> 70 #include <sys/modctl.h> 71 #include <sys/pci.h> 72 #include <sys/pci_impl.h> 73 74 #include <sys/pctypes.h> 75 #include <sys/pcmcia.h> 76 #include <sys/sservice.h> 77 78 #include <sys/note.h> 79 80 #include <sys/pcic_reg.h> 81 #include <sys/pcic_var.h> 82 83 #if defined(__sparc) 84 #include <sys/pci/pci_nexus.h> 85 #endif 86 87 #include <sys/hotplug/hpcsvc.h> 88 #include "cardbus/cardbus.h" 89 90 #define SOFTC_SIZE (sizeof (anp_t)) 91 92 static int pcic_getinfo(dev_info_t *, ddi_info_cmd_t, void *, void **); 93 static int pcic_attach(dev_info_t *, ddi_attach_cmd_t); 94 static int pcic_detach(dev_info_t *, ddi_detach_cmd_t); 95 static uint_t pcic_intr(caddr_t, caddr_t); 96 static int pcic_do_io_intr(pcicdev_t *, uint32_t); 97 static int pcic_probe(dev_info_t *); 98 99 static int pcic_open(dev_t *, int, int, cred_t *); 100 static int pcic_close(dev_t, int, int, cred_t *); 101 static int pcic_ioctl(dev_t, int, intptr_t, int, cred_t *, int *); 102 103 typedef struct pcm_regs pcm_regs_t; 104 105 static void pcic_init_assigned(dev_info_t *); 106 static int pcic_apply_avail_ranges(dev_info_t *, pcm_regs_t *, 107 pci_regspec_t *, int); 108 int pci_resource_setup_avail(dev_info_t *, pci_regspec_t *, int); 109 110 /* 111 * On x86 platforms the ddi_iobp_alloc(9F) and ddi_mem_alloc(9F) calls 112 * are xlated into DMA ctlops. To make this nexus work on x86, we 113 * need to have the default ddi_dma_mctl ctlops in the bus_ops 114 * structure, just to pass the request to the parent. The correct 115 * ctlops should be ddi_no_dma_mctl because so far we don't do DMA. 116 */ 117 static 118 struct bus_ops pcmciabus_ops = { 119 BUSO_REV, 120 pcmcia_bus_map, 121 NULL, 122 NULL, 123 NULL, 124 i_ddi_map_fault, 125 ddi_no_dma_map, 126 ddi_no_dma_allochdl, 127 ddi_no_dma_freehdl, 128 ddi_no_dma_bindhdl, 129 ddi_no_dma_unbindhdl, 130 ddi_no_dma_flush, 131 ddi_no_dma_win, 132 ddi_dma_mctl, 133 pcmcia_ctlops, 134 pcmcia_prop_op, 135 NULL, /* (*bus_get_eventcookie)(); */ 136 NULL, /* (*bus_add_eventcall)(); */ 137 NULL, /* (*bus_remove_eventcall)(); */ 138 NULL, /* (*bus_post_event)(); */ 139 NULL, /* (*bus_intr_ctl)(); */ 140 NULL, /* (*bus_config)(); */ 141 NULL, /* (*bus_unconfig)(); */ 142 NULL, /* (*bus_fm_init)(); */ 143 NULL, /* (*bus_fm_fini)(); */ 144 NULL, /* (*bus_enter)() */ 145 NULL, /* (*bus_exit)() */ 146 NULL, /* (*bus_power)() */ 147 pcmcia_intr_ops /* (*bus_intr_op)(); */ 148 }; 149 150 static struct cb_ops pcic_cbops = { 151 pcic_open, 152 pcic_close, 153 nodev, 154 nodev, 155 nodev, 156 nodev, 157 nodev, 158 pcic_ioctl, 159 nodev, 160 nodev, 161 nodev, 162 nochpoll, 163 ddi_prop_op, 164 NULL, 165 #ifdef CARDBUS 166 D_NEW | D_MP | D_HOTPLUG 167 #else 168 D_NEW | D_MP 169 #endif 170 }; 171 172 static struct dev_ops pcic_devops = { 173 DEVO_REV, 174 0, 175 pcic_getinfo, 176 nulldev, 177 pcic_probe, 178 pcic_attach, 179 pcic_detach, 180 nulldev, 181 &pcic_cbops, 182 &pcmciabus_ops, 183 NULL 184 }; 185 186 void *pcic_soft_state_p = NULL; 187 static int pcic_maxinst = -1; 188 static timeout_id_t pcic_delayed_resume_toid; 189 190 int pcic_do_insertion = 1; 191 int pcic_do_removal = 1; 192 193 struct irqmap { 194 int irq; 195 int count; 196 } pcic_irq_map[16]; 197 198 199 int pcic_debug = 0x0; 200 static void pcic_err(dev_info_t *dip, int level, const char *fmt, ...); 201 extern void cardbus_dump_pci_config(dev_info_t *dip); 202 extern void cardbus_dump_socket(dev_info_t *dip); 203 extern int cardbus_validate_iline(dev_info_t *dip, ddi_acc_handle_t handle); 204 static void pcic_dump_debqueue(char *msg); 205 206 #if defined(PCIC_DEBUG) 207 static void xxdmp_all_regs(pcicdev_t *, int, uint32_t); 208 209 #define pcic_mutex_enter(a) \ 210 { \ 211 pcic_err(NULL, 10, "Set lock at %d\n", __LINE__); \ 212 mutex_enter(a); \ 213 }; 214 215 #define pcic_mutex_exit(a) \ 216 { \ 217 pcic_err(NULL, 10, "Clear lock at %d\n", __LINE__); \ 218 mutex_exit(a); \ 219 }; 220 221 #else 222 #define pcic_mutex_enter(a) mutex_enter(a) 223 #define pcic_mutex_exit(a) mutex_exit(a) 224 #endif 225 226 #define PCIC_VCC_3VLEVEL 1 227 #define PCIC_VCC_5VLEVEL 2 228 #define PCIC_VCC_12LEVEL 3 229 230 /* bit patterns to select voltage levels */ 231 int pcic_vpp_levels[13] = { 232 0, 0, 0, 233 1, /* 3.3V */ 234 0, 235 1, /* 5V */ 236 0, 0, 0, 0, 0, 0, 237 2 /* 12V */ 238 }; 239 240 uint8_t pcic_cbv_levels[13] = { 241 0, 0, 0, 242 3, /* 3.3V */ 243 0, 244 2, /* 5V */ 245 0, 0, 0, 0, 0, 0, 246 1 /* 12V */ 247 }; 248 249 struct power_entry pcic_power[4] = { 250 { 251 0, VCC|VPP1|VPP2 252 }, 253 { 254 33, /* 3.3Volt */ 255 VCC|VPP1|VPP2 256 }, 257 { 258 5*10, /* 5Volt */ 259 VCC|VPP1|VPP2 /* currently only know about this */ 260 }, 261 { 262 12*10, /* 12Volt */ 263 VPP1|VPP2 264 } 265 }; 266 267 /* 268 * Base used to allocate ranges of PCI memory on x86 systems 269 * Each instance gets a chunk above the base that is used to map 270 * in the memory and I/O windows for that device. 271 * Pages below the base are also allocated for the EXCA registers, 272 * one per instance. 273 */ 274 #define PCIC_PCI_MEMCHUNK 0x1000000 275 276 static int pcic_wait_insert_time = 5000000; /* In micro-seconds */ 277 static int pcic_debounce_time = 200000; /* In micro-seconds */ 278 279 struct debounce { 280 pcic_socket_t *pcs; 281 clock_t expire; 282 struct debounce *next; 283 }; 284 285 static struct debounce *pcic_deb_queue = NULL; 286 static kmutex_t pcic_deb_mtx; 287 static kcondvar_t pcic_deb_cv; 288 static kthread_t *pcic_deb_threadid; 289 290 static inthandler_t *pcic_handlers; 291 292 static void pcic_setup_adapter(pcicdev_t *); 293 static int pcic_change(pcicdev_t *, int); 294 static int pcic_ll_reset(pcicdev_t *, int); 295 static void pcic_mswait(pcicdev_t *, int, int); 296 static boolean_t pcic_check_ready(pcicdev_t *, int); 297 static void pcic_set_cdtimers(pcicdev_t *, int, uint32_t, int); 298 static void pcic_ready_wait(pcicdev_t *, int); 299 extern int pcmcia_get_intr(dev_info_t *, int); 300 extern int pcmcia_return_intr(dev_info_t *, int); 301 302 static int pcic_callback(dev_info_t *, int (*)(), int); 303 static int pcic_inquire_adapter(dev_info_t *, inquire_adapter_t *); 304 static int pcic_get_adapter(dev_info_t *, get_adapter_t *); 305 static int pcic_get_page(dev_info_t *, get_page_t *); 306 static int pcic_get_socket(dev_info_t *, get_socket_t *); 307 static int pcic_get_status(dev_info_t *, get_ss_status_t *); 308 static int pcic_get_window(dev_info_t *, get_window_t *); 309 static int pcic_inquire_socket(dev_info_t *, inquire_socket_t *); 310 static int pcic_inquire_window(dev_info_t *, inquire_window_t *); 311 static int pcic_reset_socket(dev_info_t *, int, int); 312 static int pcic_set_page(dev_info_t *, set_page_t *); 313 static int pcic_set_window(dev_info_t *, set_window_t *); 314 static int pcic_set_socket(dev_info_t *, set_socket_t *); 315 static int pcic_set_interrupt(dev_info_t *, set_irq_handler_t *); 316 static int pcic_clear_interrupt(dev_info_t *, clear_irq_handler_t *); 317 static void pcic_pm_detection(void *); 318 static void pcic_iomem_pci_ctl(ddi_acc_handle_t, uchar_t *, unsigned); 319 static int clext_reg_read(pcicdev_t *, int, uchar_t); 320 static void clext_reg_write(pcicdev_t *, int, uchar_t, uchar_t); 321 static int pcic_calc_speed(pcicdev_t *, uint32_t); 322 static int pcic_card_state(pcicdev_t *, pcic_socket_t *); 323 static int pcic_find_pci_type(pcicdev_t *); 324 static void pcic_82092_smiirq_ctl(pcicdev_t *, int, int, int); 325 static void pcic_handle_cd_change(pcicdev_t *, pcic_socket_t *, uint8_t); 326 static uint_t pcic_cd_softint(caddr_t, caddr_t); 327 static uint8_t pcic_getb(pcicdev_t *, int, int); 328 static void pcic_putb(pcicdev_t *, int, int, int8_t); 329 static int pcic_set_vcc_level(pcicdev_t *, set_socket_t *); 330 static uint_t pcic_softintr(caddr_t, caddr_t); 331 332 static void pcic_debounce(pcic_socket_t *); 333 static void pcic_delayed_resume(void *); 334 static void *pcic_add_debqueue(pcic_socket_t *, int); 335 static void pcic_rm_debqueue(void *); 336 static void pcic_deb_thread(); 337 338 static boolean_t pcic_load_cardbus(pcicdev_t *pcic, const pcic_socket_t *sockp); 339 static void pcic_unload_cardbus(pcicdev_t *pcic, const pcic_socket_t *sockp); 340 static uint32_t pcic_getcb(pcicdev_t *pcic, int reg); 341 static void pcic_putcb(pcicdev_t *pcic, int reg, uint32_t value); 342 static void pcic_cb_enable_intr(dev_info_t *); 343 static void pcic_cb_disable_intr(dev_info_t *); 344 static void pcic_enable_io_intr(pcicdev_t *pcic, int socket, int irq); 345 static void pcic_disable_io_intr(pcicdev_t *pcic, int socket); 346 347 static cb_nexus_cb_t pcic_cbnexus_ops = { 348 pcic_cb_enable_intr, 349 pcic_cb_disable_intr 350 }; 351 352 static int pcic_exca_powerctl(pcicdev_t *pcic, int socket, int powerlevel); 353 static int pcic_cbus_powerctl(pcicdev_t *pcic, int socket); 354 355 #if defined(__sparc) 356 static int pcic_fault(enum pci_fault_ops op, void *arg); 357 #endif 358 359 360 /* 361 * pcmcia interface operations structure 362 * this is the private interface that is exported to the nexus 363 */ 364 pcmcia_if_t pcic_if_ops = { 365 PCIF_MAGIC, 366 PCIF_VERSION, 367 pcic_callback, 368 pcic_get_adapter, 369 pcic_get_page, 370 pcic_get_socket, 371 pcic_get_status, 372 pcic_get_window, 373 pcic_inquire_adapter, 374 pcic_inquire_socket, 375 pcic_inquire_window, 376 pcic_reset_socket, 377 pcic_set_page, 378 pcic_set_window, 379 pcic_set_socket, 380 pcic_set_interrupt, 381 pcic_clear_interrupt, 382 NULL, 383 }; 384 385 /* 386 * chip type identification routines 387 * this list of functions is searched until one of them succeeds 388 * or all fail. i82365SL is assumed if failed. 389 */ 390 static int pcic_ci_cirrus(pcicdev_t *); 391 static int pcic_ci_vadem(pcicdev_t *); 392 static int pcic_ci_ricoh(pcicdev_t *); 393 394 int (*pcic_ci_funcs[])(pcicdev_t *) = { 395 pcic_ci_cirrus, 396 pcic_ci_vadem, 397 pcic_ci_ricoh, 398 NULL 399 }; 400 401 static struct modldrv modldrv = { 402 &mod_driverops, /* Type of module. This one is a driver */ 403 "PCIC PCMCIA adapter driver %I%", /* Name of the module. */ 404 &pcic_devops, /* driver ops */ 405 }; 406 407 static struct modlinkage modlinkage = { 408 MODREV_1, (void *)&modldrv, NULL 409 }; 410 411 int 412 _init() 413 { 414 int stat; 415 416 /* Allocate soft state */ 417 if ((stat = ddi_soft_state_init(&pcic_soft_state_p, 418 SOFTC_SIZE, 2)) != DDI_SUCCESS) 419 return (stat); 420 421 if ((stat = mod_install(&modlinkage)) != 0) 422 ddi_soft_state_fini(&pcic_soft_state_p); 423 424 return (stat); 425 } 426 427 int 428 _fini() 429 { 430 int stat = 0; 431 432 if ((stat = mod_remove(&modlinkage)) != 0) 433 return (stat); 434 435 if (pcic_deb_threadid) { 436 mutex_enter(&pcic_deb_mtx); 437 pcic_deb_threadid = 0; 438 while (!pcic_deb_threadid) 439 cv_wait(&pcic_deb_cv, &pcic_deb_mtx); 440 pcic_deb_threadid = 0; 441 mutex_exit(&pcic_deb_mtx); 442 443 mutex_destroy(&pcic_deb_mtx); 444 cv_destroy(&pcic_deb_cv); 445 } 446 447 ddi_soft_state_fini(&pcic_soft_state_p); 448 449 return (stat); 450 } 451 452 int 453 _info(struct modinfo *modinfop) 454 { 455 return (mod_info(&modlinkage, modinfop)); 456 } 457 458 /* 459 * pcic_getinfo() 460 * provide instance/device information about driver 461 */ 462 /*ARGSUSED*/ 463 static int 464 pcic_getinfo(dev_info_t *dip, ddi_info_cmd_t cmd, void *arg, void **result) 465 { 466 anp_t *anp; 467 int error = DDI_SUCCESS; 468 minor_t minor; 469 470 switch (cmd) { 471 case DDI_INFO_DEVT2DEVINFO: 472 minor = getminor((dev_t)arg); 473 minor &= 0x7f; 474 if (!(anp = ddi_get_soft_state(pcic_soft_state_p, minor))) 475 *result = NULL; 476 else 477 *result = anp->an_dip; 478 break; 479 case DDI_INFO_DEVT2INSTANCE: 480 minor = getminor((dev_t)arg); 481 minor &= 0x7f; 482 *result = (void *)((long)minor); 483 break; 484 default: 485 error = DDI_FAILURE; 486 break; 487 } 488 return (error); 489 } 490 491 static int 492 pcic_probe(dev_info_t *dip) 493 { 494 int value; 495 ddi_device_acc_attr_t attr; 496 ddi_acc_handle_t handle; 497 uchar_t *index, *data; 498 499 if (ddi_dev_is_sid(dip) == DDI_SUCCESS) 500 return (DDI_PROBE_DONTCARE); 501 502 /* 503 * find a PCIC device (any vendor) 504 * while there can be up to 4 such devices in 505 * a system, we currently only look for 1 506 * per probe. There will be up to 2 chips per 507 * instance since they share I/O space 508 */ 509 attr.devacc_attr_version = DDI_DEVICE_ATTR_V0; 510 attr.devacc_attr_endian_flags = DDI_NEVERSWAP_ACC; 511 attr.devacc_attr_dataorder = DDI_STRICTORDER_ACC; 512 513 if (ddi_regs_map_setup(dip, PCIC_ISA_CONTROL_REG_NUM, 514 (caddr_t *)&index, 515 PCIC_ISA_CONTROL_REG_OFFSET, 516 PCIC_ISA_CONTROL_REG_LENGTH, 517 &attr, &handle) != DDI_SUCCESS) 518 return (DDI_PROBE_FAILURE); 519 520 data = index + 1; 521 522 #if defined(PCIC_DEBUG) 523 if (pcic_debug) 524 cmn_err(CE_CONT, "pcic_probe: entered\n"); 525 if (pcic_debug) 526 cmn_err(CE_CONT, "\tindex=%p\n", (void *)index); 527 #endif 528 ddi_put8(handle, index, PCIC_CHIP_REVISION); 529 ddi_put8(handle, data, 0); 530 value = ddi_get8(handle, data); 531 #if defined(PCIC_DEBUG) 532 if (pcic_debug) 533 cmn_err(CE_CONT, "\tchip revision register = %x\n", value); 534 #endif 535 if ((value & PCIC_REV_MASK) >= PCIC_REV_LEVEL_LOW && 536 (value & 0x30) == 0) { 537 /* 538 * we probably have a PCIC chip in the system 539 * do a little more checking. If we find one, 540 * reset everything in case of softboot 541 */ 542 ddi_put8(handle, index, PCIC_MAPPING_ENABLE); 543 ddi_put8(handle, data, 0); 544 value = ddi_get8(handle, data); 545 #if defined(PCIC_DEBUG) 546 if (pcic_debug) 547 cmn_err(CE_CONT, "\tzero test = %x\n", value); 548 #endif 549 /* should read back as zero */ 550 if (value == 0) { 551 /* 552 * we do have one and it is off the bus 553 */ 554 #if defined(PCIC_DEBUG) 555 if (pcic_debug) 556 cmn_err(CE_CONT, "pcic_probe: success\n"); 557 #endif 558 ddi_regs_map_free(&handle); 559 return (DDI_PROBE_SUCCESS); 560 } 561 } 562 #if defined(PCIC_DEBUG) 563 if (pcic_debug) 564 cmn_err(CE_CONT, "pcic_probe: failed\n"); 565 #endif 566 ddi_regs_map_free(&handle); 567 return (DDI_PROBE_FAILURE); 568 } 569 570 /* 571 * These are just defaults they can also be changed via a property in the 572 * conf file. 573 */ 574 static int pci_config_reg_num = PCIC_PCI_CONFIG_REG_NUM; 575 static int pci_control_reg_num = PCIC_PCI_CONTROL_REG_NUM; 576 static int pcic_do_pcmcia_sr = 0; 577 static int pcic_use_cbpwrctl = PCF_CBPWRCTL; 578 579 /* 580 * enable insertion/removal interrupt for 32bit cards 581 */ 582 static int 583 cardbus_enable_cd_intr(dev_info_t *dip) 584 { 585 ddi_acc_handle_t iohandle; 586 caddr_t ioaddr; 587 ddi_device_acc_attr_t attr; 588 attr.devacc_attr_version = DDI_DEVICE_ATTR_V0; 589 attr.devacc_attr_endian_flags = DDI_STRUCTURE_LE_ACC; 590 attr.devacc_attr_dataorder = DDI_STRICTORDER_ACC; 591 (void) ddi_regs_map_setup(dip, 1, 592 (caddr_t *)&ioaddr, 593 0, 594 4096, 595 &attr, &iohandle); 596 597 /* CSC Interrupt: Card detect interrupt on */ 598 ddi_put32(iohandle, (uint32_t *)(ioaddr+CB_STATUS_MASK), 599 ddi_get32(iohandle, 600 (uint32_t *)(ioaddr+CB_STATUS_MASK)) | CB_SE_CCDMASK); 601 602 ddi_put32(iohandle, (uint32_t *)(ioaddr+CB_STATUS_EVENT), 603 ddi_get32(iohandle, (uint32_t *)(ioaddr+CB_STATUS_EVENT))); 604 605 ddi_regs_map_free(&iohandle); 606 return (1); 607 } 608 609 /* 610 * pcic_attach() 611 * attach the PCIC (Intel 82365SL/CirrusLogic/Toshiba) driver 612 * to the system. This is a child of "sysbus" since that is where 613 * the hardware lives, but it provides services to the "pcmcia" 614 * nexus driver. It gives a pointer back via its private data 615 * structure which contains both the dip and socket services entry 616 * points 617 */ 618 static int 619 pcic_attach(dev_info_t *dip, ddi_attach_cmd_t cmd) 620 { 621 anp_t *pcic_nexus; 622 pcicdev_t *pcic; 623 int irqlevel, value; 624 int pci_cfrn, pci_ctrn; 625 int i, j, smi, actual; 626 char *typename; 627 char bus_type[16] = "(unknown)"; 628 int len = sizeof (bus_type); 629 ddi_device_acc_attr_t attr; 630 anp_t *anp = ddi_get_driver_private(dip); 631 uint_t pri; 632 633 #if defined(PCIC_DEBUG) 634 if (pcic_debug) { 635 cmn_err(CE_CONT, "pcic_attach: entered\n"); 636 } 637 #endif 638 switch (cmd) { 639 case DDI_ATTACH: 640 break; 641 case DDI_RESUME: 642 pcic = anp->an_private; 643 /* 644 * for now, this is a simulated resume. 645 * a real one may need different things. 646 */ 647 if (pcic != NULL && pcic->pc_flags & PCF_SUSPENDED) { 648 mutex_enter(&pcic->pc_lock); 649 /* should probe for new sockets showing up */ 650 pcic_setup_adapter(pcic); 651 pcic->pc_flags &= ~PCF_SUSPENDED; 652 mutex_exit(&pcic->pc_lock); 653 (void) pcmcia_begin_resume(dip); 654 /* 655 * this will do the CARD_INSERTION 656 * due to needing time for threads to 657 * run, it must be delayed for a short amount 658 * of time. pcmcia_wait_insert checks for all 659 * children to be removed and then triggers insert. 660 */ 661 /* 662 * The reason for having a single timeout here 663 * rather than seperate timeout()s for each instance 664 * is due to the limited number (2) of callout threads 665 * available in Solaris 2.6. A single 1250A ends up 666 * as two instances of the interface with one slot each. 667 * The pcic_delayed_resume() function ends by calling 668 * pcmcia_wait_insert() which at one point does a 669 * delay(). delay() is implemented with a timeout() 670 * call so you end up with both the callout() 671 * threads waiting to be woken up by another callout(). 672 * This situation locks up the machine hence the 673 * convolution here to only use one timeout. 674 */ 675 if (!pcic_delayed_resume_toid) 676 pcic_delayed_resume_toid = 677 timeout(pcic_delayed_resume, (caddr_t)0, 678 drv_usectohz(pcic_wait_insert_time)); 679 680 /* 681 * for complete implementation need END_RESUME (later) 682 */ 683 return (DDI_SUCCESS); 684 685 } 686 return (DDI_SUCCESS); 687 default: 688 return (DDI_FAILURE); 689 } 690 691 /* 692 * Allocate soft state associated with this instance. 693 */ 694 if (ddi_soft_state_zalloc(pcic_soft_state_p, 695 ddi_get_instance(dip)) != DDI_SUCCESS) { 696 cmn_err(CE_CONT, "pcic%d: Unable to alloc state\n", 697 ddi_get_instance(dip)); 698 return (DDI_FAILURE); 699 } 700 701 pcic_nexus = ddi_get_soft_state(pcic_soft_state_p, 702 ddi_get_instance(dip)); 703 704 pcic = kmem_zalloc(sizeof (pcicdev_t), KM_SLEEP); 705 706 pcic->dip = dip; 707 pcic_nexus->an_dip = dip; 708 pcic_nexus->an_if = &pcic_if_ops; 709 pcic_nexus->an_private = pcic; 710 pcic->pc_numpower = sizeof (pcic_power)/sizeof (pcic_power[0]); 711 pcic->pc_power = pcic_power; 712 713 pci_ctrn = ddi_getprop(DDI_DEV_T_ANY, dip, DDI_PROP_CANSLEEP, 714 "pci-control-reg-number", pci_control_reg_num); 715 pci_cfrn = ddi_getprop(DDI_DEV_T_ANY, dip, DDI_PROP_CANSLEEP, 716 "pci-config-reg-number", pci_config_reg_num); 717 718 ddi_set_driver_private(dip, pcic_nexus); 719 720 /* 721 * pcic->pc_irq is really the IPL level we want to run at 722 * set the default values here and override from intr spec 723 */ 724 pcic->pc_irq = ddi_getprop(DDI_DEV_T_ANY, dip, DDI_PROP_CANSLEEP, 725 "interrupt-priorities", -1); 726 727 if (pcic->pc_irq == -1) { 728 int actual; 729 uint_t pri; 730 ddi_intr_handle_t hdl; 731 732 /* see if intrspec tells us different */ 733 if (ddi_intr_alloc(dip, &hdl, DDI_INTR_TYPE_FIXED, 734 0, 1, &actual, DDI_INTR_ALLOC_NORMAL) == DDI_SUCCESS) { 735 if (ddi_intr_get_pri(hdl, &pri) == DDI_SUCCESS) 736 pcic->pc_irq = pri; 737 else 738 pcic->pc_irq = LOCK_LEVEL + 1; 739 (void) ddi_intr_free(hdl); 740 } 741 } 742 pcic_nexus->an_ipl = pcic->pc_irq; 743 744 /* 745 * Check our parent bus type. We do different things based on which 746 * bus we're on. 747 */ 748 if (ddi_prop_op(DDI_DEV_T_ANY, ddi_get_parent(dip), 749 PROP_LEN_AND_VAL_BUF, DDI_PROP_CANSLEEP, 750 "device_type", (caddr_t)&bus_type[0], &len) != 751 DDI_PROP_SUCCESS) { 752 if (ddi_prop_op(DDI_DEV_T_ANY, ddi_get_parent(dip), 753 PROP_LEN_AND_VAL_BUF, DDI_PROP_CANSLEEP, 754 "bus-type", (caddr_t)&bus_type[0], &len) != 755 DDI_PROP_SUCCESS) { 756 757 cmn_err(CE_CONT, 758 "pcic%d: can't find parent bus type\n", 759 ddi_get_instance(dip)); 760 761 kmem_free(pcic, sizeof (pcicdev_t)); 762 ddi_soft_state_free(pcic_soft_state_p, 763 ddi_get_instance(dip)); 764 return (DDI_FAILURE); 765 } 766 } /* ddi_prop_op("device_type") */ 767 768 if (strcmp(bus_type, DEVI_PCI_NEXNAME) == 0 || 769 strcmp(bus_type, DEVI_PCIEX_NEXNAME) == 0) { 770 pcic->pc_flags = PCF_PCIBUS; 771 } else { 772 cmn_err(CE_WARN, "!pcic%d: non-pci mode (%s) not supported, " 773 "set BIOS to yenta mode if applicable\n", 774 ddi_get_instance(dip), bus_type); 775 kmem_free(pcic, sizeof (pcicdev_t)); 776 ddi_soft_state_free(pcic_soft_state_p, 777 ddi_get_instance(dip)); 778 return (DDI_FAILURE); 779 } 780 781 if ((pcic->bus_speed = ddi_getprop(DDI_DEV_T_ANY, ddi_get_parent(dip), 782 DDI_PROP_CANSLEEP, 783 "clock-frequency", 0)) == 0) { 784 if (pcic->pc_flags & PCF_PCIBUS) 785 pcic->bus_speed = PCIC_PCI_DEF_SYSCLK; 786 else 787 pcic->bus_speed = PCIC_ISA_DEF_SYSCLK; 788 } else { 789 /* 790 * OBP can declare the speed in Hz... 791 */ 792 if (pcic->bus_speed > 1000000) 793 pcic->bus_speed /= 1000000; 794 } /* ddi_prop_op("clock-frequency") */ 795 796 pcic->pc_io_type = PCIC_IO_TYPE_82365SL; /* default mode */ 797 798 #ifdef PCIC_DEBUG 799 if (pcic_debug) { 800 cmn_err(CE_CONT, 801 "pcic%d: parent bus type = [%s], speed = %d MHz\n", 802 ddi_get_instance(dip), 803 bus_type, pcic->bus_speed); 804 } 805 #endif 806 807 /* 808 * The reg properties on a PCI node are different than those 809 * on a non-PCI node. Handle that difference here. 810 * If it turns out to be a CardBus chip, we have even more 811 * differences. 812 */ 813 if (pcic->pc_flags & PCF_PCIBUS) { 814 int class_code; 815 #if defined(__i386) || defined(__amd64) 816 pcic->pc_base = 0x1000000; 817 pcic->pc_bound = (uint32_t)~0; 818 pcic->pc_iobase = 0x1000; 819 pcic->pc_iobound = 0xefff; 820 #elif defined(__sparc) 821 pcic->pc_base = 0x0; 822 pcic->pc_bound = (uint32_t)~0; 823 pcic->pc_iobase = 0x00000; 824 pcic->pc_iobound = 0xffff; 825 #endif 826 827 /* usually need to get at config space so map first */ 828 attr.devacc_attr_version = DDI_DEVICE_ATTR_V0; 829 attr.devacc_attr_endian_flags = DDI_STRUCTURE_LE_ACC; 830 attr.devacc_attr_dataorder = DDI_STRICTORDER_ACC; 831 832 if (ddi_regs_map_setup(dip, pci_cfrn, 833 (caddr_t *)&pcic->cfgaddr, 834 PCIC_PCI_CONFIG_REG_OFFSET, 835 PCIC_PCI_CONFIG_REG_LENGTH, 836 &attr, 837 &pcic->cfg_handle) != 838 DDI_SUCCESS) { 839 cmn_err(CE_CONT, 840 "pcic%d: unable to map config space" 841 "regs\n", 842 ddi_get_instance(dip)); 843 844 kmem_free(pcic, sizeof (pcicdev_t)); 845 return (DDI_FAILURE); 846 } /* ddi_regs_map_setup */ 847 848 class_code = ddi_getprop(DDI_DEV_T_ANY, dip, 849 DDI_PROP_CANSLEEP|DDI_PROP_DONTPASS, 850 "class-code", -1); 851 #ifdef PCIC_DEBUG 852 if (pcic_debug) { 853 cmn_err(CE_CONT, "pcic_attach class_code=%x\n", 854 class_code); 855 } 856 #endif 857 858 switch (class_code) { 859 case PCIC_PCI_CARDBUS: 860 pcic->pc_flags |= PCF_CARDBUS; 861 pcic->pc_io_type = PCIC_IO_TYPE_YENTA; 862 /* 863 * Get access to the adapter registers on the 864 * PCI bus. A 4K memory page 865 */ 866 #if defined(PCIC_DEBUG) 867 pcic_err(dip, 8, "Is Cardbus device\n"); 868 if (pcic_debug) { 869 int nr; 870 long rs; 871 (void) ddi_dev_nregs(dip, &nr); 872 pcic_err(dip, 9, "\tdev, cfgaddr 0x%p," 873 "cfghndl 0x%p nregs %d", 874 (void *)pcic->cfgaddr, 875 (void *)pcic->cfg_handle, nr); 876 877 (void) ddi_dev_regsize(dip, 878 PCIC_PCI_CONTROL_REG_NUM, &rs); 879 880 pcic_err(dip, 9, "\tsize of reg %d is 0x%x\n", 881 PCIC_PCI_CONTROL_REG_NUM, (int)rs); 882 } 883 #endif 884 attr.devacc_attr_version = DDI_DEVICE_ATTR_V0; 885 attr.devacc_attr_endian_flags = DDI_STRUCTURE_LE_ACC; 886 attr.devacc_attr_dataorder = DDI_STRICTORDER_ACC; 887 888 if (ddi_regs_map_setup(dip, pci_ctrn, 889 (caddr_t *)&pcic->ioaddr, 890 PCIC_PCI_CONTROL_REG_OFFSET, 891 PCIC_CB_CONTROL_REG_LENGTH, 892 &attr, &pcic->handle) != 893 DDI_SUCCESS) { 894 cmn_err(CE_CONT, 895 "pcic%d: unable to map PCI regs\n", 896 ddi_get_instance(dip)); 897 ddi_regs_map_free(&pcic->cfg_handle); 898 kmem_free(pcic, sizeof (pcicdev_t)); 899 return (DDI_FAILURE); 900 } /* ddi_regs_map_setup */ 901 902 /* 903 * Find out the chip type - If we're on a PCI bus, 904 * the adapter has that information in the PCI 905 * config space. 906 * Note that we call pcic_find_pci_type here since 907 * it needs a valid mapped pcic->handle to 908 * access some of the adapter registers in 909 * some cases. 910 */ 911 if (pcic_find_pci_type(pcic) != DDI_SUCCESS) { 912 ddi_regs_map_free(&pcic->handle); 913 ddi_regs_map_free(&pcic->cfg_handle); 914 kmem_free(pcic, sizeof (pcicdev_t)); 915 cmn_err(CE_WARN, "pcic: %s: unsupported " 916 "bridge\n", 917 ddi_get_name_addr(dip)); 918 return (DDI_FAILURE); 919 } 920 break; 921 922 default: 923 case PCIC_PCI_PCMCIA: 924 /* 925 * Get access to the adapter IO registers on the 926 * PCI bus config space. 927 */ 928 attr.devacc_attr_version = DDI_DEVICE_ATTR_V0; 929 attr.devacc_attr_endian_flags = DDI_STRUCTURE_LE_ACC; 930 attr.devacc_attr_dataorder = DDI_STRICTORDER_ACC; 931 932 /* 933 * We need a default mapping to the adapter's IO 934 * control register space. For most adapters 935 * that are of class PCIC_PCI_PCMCIA (or of 936 * a default class) the control registers 937 * will be using the 82365-type control/data 938 * format. 939 */ 940 if (ddi_regs_map_setup(dip, pci_ctrn, 941 (caddr_t *)&pcic->ioaddr, 942 PCIC_PCI_CONTROL_REG_OFFSET, 943 PCIC_PCI_CONTROL_REG_LENGTH, 944 &attr, 945 &pcic->handle) != DDI_SUCCESS) { 946 cmn_err(CE_CONT, 947 "pcic%d: unable to map PCI regs\n", 948 ddi_get_instance(dip)); 949 ddi_regs_map_free(&pcic->cfg_handle); 950 kmem_free(pcic, sizeof (pcicdev_t)); 951 return (DDI_FAILURE); 952 } /* ddi_regs_map_setup */ 953 954 /* 955 * Find out the chip type - If we're on a PCI bus, 956 * the adapter has that information in the PCI 957 * config space. 958 * Note that we call pcic_find_pci_type here since 959 * it needs a valid mapped pcic->handle to 960 * access some of the adapter registers in 961 * some cases. 962 */ 963 if (pcic_find_pci_type(pcic) != DDI_SUCCESS) { 964 ddi_regs_map_free(&pcic->handle); 965 ddi_regs_map_free(&pcic->cfg_handle); 966 kmem_free(pcic, sizeof (pcicdev_t)); 967 cmn_err(CE_WARN, "pcic: %s: unsupported " 968 "bridge\n", 969 ddi_get_name_addr(dip)); 970 return (DDI_FAILURE); 971 } 972 973 /* 974 * Some PCI-PCMCIA(R2) adapters are Yenta-compliant 975 * for extended registers even though they are 976 * not CardBus adapters. For those adapters, 977 * re-map pcic->handle to be large enough to 978 * encompass the Yenta registers. 979 */ 980 switch (pcic->pc_type) { 981 case PCIC_TI_PCI1031: 982 ddi_regs_map_free(&pcic->handle); 983 984 if (ddi_regs_map_setup(dip, 985 PCIC_PCI_CONTROL_REG_NUM, 986 (caddr_t *)&pcic->ioaddr, 987 PCIC_PCI_CONTROL_REG_OFFSET, 988 PCIC_CB_CONTROL_REG_LENGTH, 989 &attr, 990 &pcic->handle) != DDI_SUCCESS) { 991 cmn_err(CE_CONT, 992 "pcic%d: unable to map " 993 "PCI regs\n", 994 ddi_get_instance(dip)); 995 ddi_regs_map_free(&pcic->cfg_handle); 996 kmem_free(pcic, sizeof (pcicdev_t)); 997 return (DDI_FAILURE); 998 } /* ddi_regs_map_setup */ 999 break; 1000 default: 1001 break; 1002 } /* switch (pcic->pc_type) */ 1003 break; 1004 } /* switch (class_code) */ 1005 } else { 1006 /* 1007 * We're not on a PCI bus, so assume an ISA bus type 1008 * register property. Get access to the adapter IO 1009 * registers on a non-PCI bus. 1010 */ 1011 attr.devacc_attr_version = DDI_DEVICE_ATTR_V0; 1012 attr.devacc_attr_endian_flags = DDI_NEVERSWAP_ACC; 1013 attr.devacc_attr_dataorder = DDI_STRICTORDER_ACC; 1014 pcic->mem_reg_num = PCIC_ISA_MEM_REG_NUM; 1015 pcic->io_reg_num = PCIC_ISA_IO_REG_NUM; 1016 1017 if (ddi_regs_map_setup(dip, PCIC_ISA_CONTROL_REG_NUM, 1018 (caddr_t *)&pcic->ioaddr, 1019 PCIC_ISA_CONTROL_REG_OFFSET, 1020 PCIC_ISA_CONTROL_REG_LENGTH, 1021 &attr, 1022 &pcic->handle) != DDI_SUCCESS) { 1023 cmn_err(CE_CONT, 1024 "pcic%d: unable to map ISA registers\n", 1025 ddi_get_instance(dip)); 1026 1027 kmem_free(pcic, sizeof (pcicdev_t)); 1028 return (DDI_FAILURE); 1029 } /* ddi_regs_map_setup */ 1030 1031 /* ISA bus is limited to 24-bits, but not first 640K */ 1032 pcic->pc_base = 0xd0000; 1033 pcic->pc_bound = (uint32_t)~0; 1034 pcic->pc_iobase = 0x1000; 1035 pcic->pc_iobound = 0xefff; 1036 } /* !PCF_PCIBUS */ 1037 1038 #ifdef PCIC_DEBUG 1039 if (pcic_debug) { 1040 cmn_err(CE_CONT, "pcic_attach pc_flags=%x pc_type=%x\n", 1041 pcic->pc_flags, pcic->pc_type); 1042 } 1043 #endif 1044 1045 /* 1046 * Setup various adapter registers for the PCI case. For the 1047 * non-PCI case, find out the chip type. 1048 */ 1049 if (pcic->pc_flags & PCF_PCIBUS) { 1050 int iline; 1051 #if defined(__sparc) 1052 iline = 0; 1053 #else 1054 iline = cardbus_validate_iline(dip, pcic->cfg_handle); 1055 #endif 1056 1057 /* set flags and socket counts based on chip type */ 1058 switch (pcic->pc_type) { 1059 uint32_t cfg; 1060 case PCIC_INTEL_i82092: 1061 cfg = ddi_get8(pcic->cfg_handle, 1062 pcic->cfgaddr + PCIC_82092_PCICON); 1063 /* we can only support 4 Socket version */ 1064 if (cfg & PCIC_82092_4_SOCKETS) { 1065 pcic->pc_numsockets = 4; 1066 pcic->pc_type = PCIC_INTEL_i82092; 1067 if (iline != 0xFF) 1068 pcic->pc_intr_mode = PCIC_INTR_MODE_PCI_1; 1069 else 1070 pcic->pc_intr_mode = PCIC_INTR_MODE_ISA; 1071 } else { 1072 cmn_err(CE_CONT, 1073 "pcic%d: Intel 82092 adapter " 1074 "in unsupported configuration: 0x%x", 1075 ddi_get_instance(pcic->dip), cfg); 1076 pcic->pc_numsockets = 0; 1077 } /* PCIC_82092_4_SOCKETS */ 1078 break; 1079 case PCIC_CL_PD6730: 1080 case PCIC_CL_PD6729: 1081 pcic->pc_intr_mode = PCIC_INTR_MODE_PCI_1; 1082 cfg = ddi_getprop(DDI_DEV_T_ANY, dip, 1083 DDI_PROP_CANSLEEP, 1084 "interrupts", 0); 1085 /* if not interrupt pin then must use ISA style IRQs */ 1086 if (cfg == 0 || iline == 0xFF) 1087 pcic->pc_intr_mode = PCIC_INTR_MODE_ISA; 1088 else { 1089 /* 1090 * we have the option to use PCI interrupts. 1091 * this might not be optimal but in some cases 1092 * is the only thing possible (sparc case). 1093 * we now deterine what is possible. 1094 */ 1095 pcic->pc_intr_mode = PCIC_INTR_MODE_PCI_1; 1096 } 1097 pcic->pc_numsockets = 2; 1098 pcic->pc_flags |= PCF_IO_REMAP; 1099 break; 1100 case PCIC_TI_PCI1031: 1101 /* this chip doesn't do CardBus but looks like one */ 1102 pcic->pc_flags &= ~PCF_CARDBUS; 1103 /* FALLTHROUGH */ 1104 default: 1105 pcic->pc_flags |= PCF_IO_REMAP; 1106 /* FALLTHROUGH */ 1107 /* indicate feature even if not supported */ 1108 pcic->pc_flags |= PCF_DMA | PCF_ZV; 1109 /* Not sure if these apply to all these chips */ 1110 pcic->pc_flags |= (PCF_VPPX|PCF_33VCAP); 1111 pcic->pc_flags |= pcic_use_cbpwrctl; 1112 1113 pcic->pc_numsockets = 1; /* one per function */ 1114 if (iline != 0xFF) { 1115 uint8_t cfg; 1116 pcic->pc_intr_mode = PCIC_INTR_MODE_PCI_1; 1117 1118 cfg = ddi_get8(pcic->cfg_handle, 1119 (pcic->cfgaddr + PCIC_BRIDGE_CTL_REG)); 1120 cfg &= (~PCIC_FUN_INT_MOD_ISA); 1121 ddi_put8(pcic->cfg_handle, (pcic->cfgaddr + 1122 PCIC_BRIDGE_CTL_REG), cfg); 1123 } 1124 else 1125 pcic->pc_intr_mode = PCIC_INTR_MODE_ISA; 1126 pcic->pc_io_type = PCIC_IOTYPE_YENTA; 1127 break; 1128 } 1129 } else { 1130 /* 1131 * We're not on a PCI bus so do some more 1132 * checking for adapter type here. 1133 * For the non-PCI bus case: 1134 * It could be any one of a number of different chips 1135 * If we can't determine anything else, it is assumed 1136 * to be an Intel 82365SL. The Cirrus Logic PD6710 1137 * has an extension register that provides unique 1138 * identification. Toshiba chip isn't detailed as yet. 1139 */ 1140 1141 /* Init the CL id mode */ 1142 pcic_putb(pcic, 0, PCIC_CHIP_INFO, 0); 1143 value = pcic_getb(pcic, 0, PCIC_CHIP_INFO); 1144 1145 /* default to Intel i82365SL and then refine */ 1146 pcic->pc_type = PCIC_I82365SL; 1147 pcic->pc_chipname = PCIC_TYPE_I82365SL; 1148 for (value = 0; pcic_ci_funcs[value] != NULL; value++) { 1149 /* go until one succeeds or none left */ 1150 if (pcic_ci_funcs[value](pcic)) 1151 break; 1152 } 1153 1154 /* any chip specific flags get set here */ 1155 switch (pcic->pc_type) { 1156 case PCIC_CL_PD6722: 1157 pcic->pc_flags |= PCF_DMA; 1158 } 1159 1160 for (i = 0; i < PCIC_MAX_SOCKETS; i++) { 1161 /* 1162 * look for total number of sockets. 1163 * basically check each possible socket for 1164 * presence like in probe 1165 */ 1166 1167 /* turn all windows off */ 1168 pcic_putb(pcic, i, PCIC_MAPPING_ENABLE, 0); 1169 value = pcic_getb(pcic, i, PCIC_MAPPING_ENABLE); 1170 1171 /* 1172 * if a zero is read back, then this socket 1173 * might be present. It would be except for 1174 * some systems that map the secondary PCIC 1175 * chip space back to the first. 1176 */ 1177 if (value != 0) { 1178 /* definitely not so skip */ 1179 /* note: this is for Compaq support */ 1180 continue; 1181 } 1182 1183 /* further tests */ 1184 value = pcic_getb(pcic, i, PCIC_CHIP_REVISION) & 1185 PCIC_REV_MASK; 1186 if (!(value >= PCIC_REV_LEVEL_LOW && 1187 value <= PCIC_REV_LEVEL_HI)) 1188 break; 1189 1190 pcic_putb(pcic, i, PCIC_SYSMEM_0_STARTLOW, 0xaa); 1191 pcic_putb(pcic, i, PCIC_SYSMEM_1_STARTLOW, 0x55); 1192 value = pcic_getb(pcic, i, PCIC_SYSMEM_0_STARTLOW); 1193 1194 j = pcic_getb(pcic, i, PCIC_SYSMEM_1_STARTLOW); 1195 if (value != 0xaa || j != 0x55) 1196 break; 1197 1198 /* 1199 * at this point we know if we have hardware 1200 * of some type and not just the bus holding 1201 * a pattern for us. We still have to determine 1202 * the case where more than 2 sockets are 1203 * really the same due to peculiar mappings of 1204 * hardware. 1205 */ 1206 j = pcic->pc_numsockets++; 1207 pcic->pc_sockets[j].pcs_flags = 0; 1208 pcic->pc_sockets[j].pcs_io = pcic->ioaddr; 1209 pcic->pc_sockets[j].pcs_socket = i; 1210 1211 /* put PC Card into RESET, just in case */ 1212 value = pcic_getb(pcic, i, PCIC_INTERRUPT); 1213 pcic_putb(pcic, i, PCIC_INTERRUPT, 1214 value & ~PCIC_RESET); 1215 } 1216 1217 #if defined(PCIC_DEBUG) 1218 if (pcic_debug) 1219 cmn_err(CE_CONT, "num sockets = %d\n", 1220 pcic->pc_numsockets); 1221 #endif 1222 if (pcic->pc_numsockets == 0) { 1223 ddi_regs_map_free(&pcic->handle); 1224 kmem_free(pcic, sizeof (pcicdev_t)); 1225 return (DDI_FAILURE); 1226 } 1227 1228 /* 1229 * need to think this through again in light of 1230 * Compaq not following the model that all the 1231 * chip vendors recommend. IBM 755 seems to be 1232 * afflicted as well. Basically, if the vendor 1233 * wired things wrong, socket 0 responds for socket 2 1234 * accesses, etc. 1235 */ 1236 if (pcic->pc_numsockets > 2) { 1237 int count = pcic->pc_numsockets / 4; 1238 for (i = 0; i < count; i++) { 1239 /* put pattern into socket 0 */ 1240 pcic_putb(pcic, i, 1241 PCIC_SYSMEM_0_STARTLOW, 0x11); 1242 1243 /* put pattern into socket 2 */ 1244 pcic_putb(pcic, i + 2, 1245 PCIC_SYSMEM_0_STARTLOW, 0x33); 1246 1247 /* read back socket 0 */ 1248 value = pcic_getb(pcic, i, 1249 PCIC_SYSMEM_0_STARTLOW); 1250 1251 /* read back chip 1 socket 0 */ 1252 j = pcic_getb(pcic, i + 2, 1253 PCIC_SYSMEM_0_STARTLOW); 1254 if (j == value) { 1255 pcic->pc_numsockets -= 2; 1256 } 1257 } 1258 } 1259 1260 smi = 0xff; /* no more override */ 1261 1262 if (ddi_getprop(DDI_DEV_T_NONE, dip, 1263 DDI_PROP_DONTPASS, "need-mult-irq", 1264 0xffff) != 0xffff) 1265 pcic->pc_flags |= PCF_MULT_IRQ; 1266 1267 } /* !PCF_PCIBUS */ 1268 1269 /* 1270 * some platforms/busses need to have resources setup 1271 * this is temporary until a real resource allocator is 1272 * implemented. 1273 */ 1274 1275 pcic_init_assigned(dip); 1276 1277 typename = pcic->pc_chipname; 1278 1279 #ifdef PCIC_DEBUG 1280 if (pcic_debug) { 1281 int nregs, nintrs; 1282 1283 if (ddi_dev_nregs(dip, &nregs) != DDI_SUCCESS) 1284 nregs = 0; 1285 1286 if (ddi_dev_nintrs(dip, &nintrs) != DDI_SUCCESS) 1287 nintrs = 0; 1288 1289 cmn_err(CE_CONT, 1290 "pcic%d: %d register sets, %d interrupts\n", 1291 ddi_get_instance(dip), nregs, nintrs); 1292 1293 nintrs = 0; 1294 while (nregs--) { 1295 off_t size; 1296 1297 if (ddi_dev_regsize(dip, nintrs, &size) == 1298 DDI_SUCCESS) { 1299 cmn_err(CE_CONT, 1300 "\tregnum %d size %ld (0x%lx)" 1301 "bytes", 1302 nintrs, size, size); 1303 if (nintrs == 1304 (pcic->pc_io_type == PCIC_IO_TYPE_82365SL ? 1305 PCIC_ISA_CONTROL_REG_NUM : 1306 PCIC_PCI_CONTROL_REG_NUM)) 1307 cmn_err(CE_CONT, 1308 " mapped at: 0x%p\n", 1309 (void *)pcic->ioaddr); 1310 else 1311 cmn_err(CE_CONT, "\n"); 1312 } else { 1313 cmn_err(CE_CONT, 1314 "\tddi_dev_regsize(rnumber" 1315 "= %d) returns DDI_FAILURE\n", 1316 nintrs); 1317 } 1318 nintrs++; 1319 } /* while */ 1320 } /* if (pcic_debug) */ 1321 #endif 1322 1323 cv_init(&pcic->pm_cv, NULL, CV_DRIVER, NULL); 1324 1325 if (!ddi_getprop(DDI_DEV_T_NONE, dip, DDI_PROP_DONTPASS, 1326 "disable-audio", 0)) 1327 pcic->pc_flags |= PCF_AUDIO; 1328 1329 if (ddi_getprop(DDI_DEV_T_ANY, dip, DDI_PROP_CANSLEEP, 1330 "disable-cardbus", 0)) 1331 pcic->pc_flags &= ~PCF_CARDBUS; 1332 1333 (void) ddi_prop_update_string(DDI_DEV_T_NONE, dip, PCICPROP_CTL, 1334 typename); 1335 1336 /* 1337 * Init all socket SMI levels to 0 (no SMI) 1338 */ 1339 for (i = 0; i < PCIC_MAX_SOCKETS; i++) { 1340 pcic->pc_sockets[i].pcs_smi = 0; 1341 pcic->pc_sockets[i].pcs_debounce_id = 0; 1342 pcic->pc_sockets[i].pcs_pcic = pcic; 1343 } 1344 pcic->pc_lastreg = -1; /* just to make sure we are in sync */ 1345 1346 /* 1347 * Setup the IRQ handler(s) 1348 */ 1349 switch (pcic->pc_intr_mode) { 1350 int xx; 1351 case PCIC_INTR_MODE_ISA: 1352 /* 1353 * On a non-PCI bus, we just use whatever SMI IRQ level was 1354 * specified above, and the IO IRQ levels are allocated 1355 * dynamically. 1356 */ 1357 for (xx = 15, smi = 0; xx >= 0; xx--) { 1358 if (PCIC_IRQ(xx) & 1359 PCIC_AVAIL_IRQS) { 1360 smi = pcmcia_get_intr(dip, xx); 1361 if (smi >= 0) 1362 break; 1363 } 1364 } 1365 #if defined(PCIC_DEBUG) 1366 if (pcic_debug) 1367 cmn_err(CE_NOTE, "\tselected IRQ %d as SMI\n", smi); 1368 #endif 1369 /* init to same so share is easy */ 1370 for (i = 0; i < pcic->pc_numsockets; i++) 1371 pcic->pc_sockets[i].pcs_smi = smi; 1372 /* any special handling of IRQ levels */ 1373 if (pcic->pc_flags & PCF_MULT_IRQ) { 1374 for (i = 2; i < pcic->pc_numsockets; i++) { 1375 if ((i & 1) == 0) { 1376 int xx; 1377 for (xx = 15, smi = 0; xx >= 0; xx--) { 1378 if (PCIC_IRQ(xx) & 1379 PCIC_AVAIL_IRQS) { 1380 smi = 1381 pcmcia_get_intr(dip, 1382 xx); 1383 if (smi >= 0) 1384 break; 1385 } 1386 } 1387 } 1388 if (smi >= 0) 1389 pcic->pc_sockets[i].pcs_smi = smi; 1390 } 1391 } 1392 pcic->pc_intr_htblp = kmem_alloc(pcic->pc_numsockets * 1393 sizeof (ddi_intr_handle_t), KM_SLEEP); 1394 for (i = 0, irqlevel = -1; i < pcic->pc_numsockets; i++) { 1395 struct intrspec *ispecp; 1396 struct ddi_parent_private_data *pdp; 1397 1398 if (irqlevel == pcic->pc_sockets[i].pcs_smi) 1399 continue; 1400 else { 1401 irqlevel = pcic->pc_sockets[i].pcs_smi; 1402 } 1403 /* 1404 * now convert the allocated IRQ into an intrspec 1405 * and ask our parent to add it. Don't use 1406 * the ddi_add_intr since we don't have a 1407 * default intrspec in all cases. 1408 * 1409 * note: this sort of violates DDI but we don't 1410 * get hardware intrspecs for many of the devices. 1411 * at the same time, we know how to allocate them 1412 * so we do the right thing. 1413 */ 1414 if (ddi_intr_alloc(dip, &pcic->pc_intr_htblp[i], 1415 DDI_INTR_TYPE_FIXED, 0, 1, &actual, 1416 DDI_INTR_ALLOC_NORMAL) != DDI_SUCCESS) { 1417 cmn_err(CE_WARN, "%s: ddi_intr_alloc failed", 1418 ddi_get_name(dip)); 1419 goto isa_exit1; 1420 } 1421 1422 /* 1423 * See earlier note: 1424 * Since some devices don't have 'intrspec' 1425 * we make one up in rootnex. 1426 * 1427 * However, it is not properly initialized as 1428 * the data it needs is present in this driver 1429 * and there is no interface to pass that up. 1430 * Specially 'irqlevel' is very important and 1431 * it is part of pcic struct. 1432 * 1433 * Set 'intrspec' up here; otherwise adding the 1434 * interrupt will fail. 1435 */ 1436 pdp = ddi_get_parent_data(dip); 1437 ispecp = (struct intrspec *)&pdp->par_intr[0]; 1438 ispecp->intrspec_vec = irqlevel; 1439 ispecp->intrspec_pri = pcic->pc_irq; 1440 1441 /* Stay compatible w/ PCMCIA */ 1442 pcic->pc_pri = (ddi_iblock_cookie_t) 1443 (uintptr_t)pcic->pc_irq; 1444 pcic->pc_dcookie.idev_priority = 1445 (uintptr_t)pcic->pc_pri; 1446 pcic->pc_dcookie.idev_vector = (ushort_t)irqlevel; 1447 1448 (void) ddi_intr_set_pri(pcic->pc_intr_htblp[i], 1449 pcic->pc_irq); 1450 1451 if (i == 0) { 1452 mutex_init(&pcic->intr_lock, NULL, MUTEX_DRIVER, 1453 DDI_INTR_PRI(pcic->pc_irq)); 1454 mutex_init(&pcic->pc_lock, NULL, MUTEX_DRIVER, 1455 NULL); 1456 } 1457 1458 if (ddi_intr_add_handler(pcic->pc_intr_htblp[i], 1459 pcic_intr, (caddr_t)pcic, NULL)) { 1460 cmn_err(CE_WARN, 1461 "%s: ddi_intr_add_handler failed", 1462 ddi_get_name(dip)); 1463 goto isa_exit2; 1464 } 1465 1466 if (ddi_intr_enable(pcic->pc_intr_htblp[i])) { 1467 cmn_err(CE_WARN, "%s: ddi_intr_enable failed", 1468 ddi_get_name(dip)); 1469 for (j = i; j < 0; j--) 1470 (void) ddi_intr_remove_handler( 1471 pcic->pc_intr_htblp[j]); 1472 goto isa_exit2; 1473 } 1474 } 1475 break; 1476 case PCIC_INTR_MODE_PCI_1: 1477 case PCIC_INTR_MODE_PCI: 1478 /* 1479 * If we're on a PCI bus, we route all interrupts, both SMI 1480 * and IO interrupts, through a single interrupt line. 1481 * Assign the SMI IRQ level to the IO IRQ level here. 1482 */ 1483 pcic->pc_pci_intr_hdlp = kmem_alloc(sizeof (ddi_intr_handle_t), 1484 KM_SLEEP); 1485 if (ddi_intr_alloc(dip, pcic->pc_pci_intr_hdlp, 1486 DDI_INTR_TYPE_FIXED, 0, 1, &actual, 1487 DDI_INTR_ALLOC_NORMAL) != DDI_SUCCESS) 1488 goto pci_exit1; 1489 1490 if (ddi_intr_get_pri(pcic->pc_pci_intr_hdlp[0], 1491 &pri) != DDI_SUCCESS) { 1492 (void) ddi_intr_free(pcic->pc_pci_intr_hdlp[0]); 1493 goto pci_exit1; 1494 } 1495 1496 pcic->pc_pri = (void *)(uintptr_t)pri; 1497 mutex_init(&pcic->intr_lock, NULL, MUTEX_DRIVER, pcic->pc_pri); 1498 mutex_init(&pcic->pc_lock, NULL, MUTEX_DRIVER, NULL); 1499 1500 if (ddi_intr_add_handler(pcic->pc_pci_intr_hdlp[0], 1501 pcic_intr, (caddr_t)pcic, NULL)) 1502 goto pci_exit2; 1503 1504 if (ddi_intr_enable(pcic->pc_pci_intr_hdlp[0])) { 1505 (void) ddi_intr_remove_handler( 1506 pcic->pc_pci_intr_hdlp[0]); 1507 goto pci_exit2; 1508 } 1509 1510 /* Stay compatible w/ PCMCIA */ 1511 pcic->pc_dcookie.idev_priority = (ushort_t)pri; 1512 1513 /* init to same (PCI) so share is easy */ 1514 for (i = 0; i < pcic->pc_numsockets; i++) 1515 pcic->pc_sockets[i].pcs_smi = 0xF; /* any valid */ 1516 break; 1517 } 1518 1519 /* 1520 * Setup the adapter hardware to some reasonable defaults. 1521 */ 1522 mutex_enter(&pcic->pc_lock); 1523 /* mark the driver state as attached */ 1524 pcic->pc_flags |= PCF_ATTACHED; 1525 pcic_setup_adapter(pcic); 1526 1527 for (j = 0; j < pcic->pc_numsockets; j++) 1528 if (ddi_intr_add_softint(dip, 1529 &pcic->pc_sockets[j].pcs_cd_softint_hdl, 1530 PCIC_SOFTINT_PRI_VAL, pcic_cd_softint, 1531 (caddr_t)&pcic->pc_sockets[j]) != DDI_SUCCESS) 1532 goto pci_exit2; 1533 1534 #if defined(PCIC_DEBUG) 1535 if (pcic_debug) 1536 cmn_err(CE_CONT, "type = %s sockets = %d\n", typename, 1537 pcic->pc_numsockets); 1538 #endif 1539 1540 pcic_nexus->an_iblock = &pcic->pc_pri; 1541 pcic_nexus->an_idev = &pcic->pc_dcookie; 1542 1543 mutex_exit(&pcic->pc_lock); 1544 1545 #ifdef CARDBUS 1546 (void) cardbus_enable_cd_intr(dip); 1547 if (pcic_debug) { 1548 1549 cardbus_dump_pci_config(dip); 1550 cardbus_dump_socket(dip); 1551 } 1552 1553 /* 1554 * Give the Cardbus misc module a chance to do it's per-adapter 1555 * instance setup. Note that there is no corresponding detach() 1556 * call. 1557 */ 1558 if (pcic->pc_flags & PCF_CARDBUS) 1559 if (cardbus_attach(dip, &pcic_cbnexus_ops) != DDI_SUCCESS) { 1560 cmn_err(CE_CONT, 1561 "pcic_attach: cardbus_attach failed\n"); 1562 goto pci_exit2; 1563 } 1564 #endif 1565 1566 /* 1567 * Give the PCMCIA misc module a chance to do it's per-adapter 1568 * instance setup. 1569 */ 1570 if ((i = pcmcia_attach(dip, pcic_nexus)) != DDI_SUCCESS) 1571 goto pci_exit2; 1572 1573 if (pcic_maxinst == -1) { 1574 /* This assumes that all instances run at the same IPL. */ 1575 mutex_init(&pcic_deb_mtx, NULL, MUTEX_DRIVER, NULL); 1576 cv_init(&pcic_deb_cv, NULL, CV_DRIVER, NULL); 1577 pcic_deb_threadid = thread_create((caddr_t)NULL, 0, 1578 pcic_deb_thread, (caddr_t)NULL, 0, &p0, TS_RUN, 1579 v.v_maxsyspri - 2); 1580 } 1581 pcic_maxinst = max(pcic_maxinst, ddi_get_instance(dip)); 1582 /* 1583 * Setup a debounce timeout to do an initial card detect 1584 * and enable interrupts. 1585 */ 1586 for (j = 0; j < pcic->pc_numsockets; j++) { 1587 pcic->pc_sockets[j].pcs_debounce_id = 1588 pcic_add_debqueue(&pcic->pc_sockets[j], 1589 drv_usectohz(pcic_debounce_time)); 1590 } 1591 1592 return (i); 1593 1594 isa_exit2: 1595 mutex_destroy(&pcic->intr_lock); 1596 mutex_destroy(&pcic->pc_lock); 1597 for (j = i; j < 0; j--) 1598 (void) ddi_intr_free(pcic->pc_intr_htblp[j]); 1599 isa_exit1: 1600 (void) pcmcia_return_intr(dip, pcic->pc_sockets[i].pcs_smi); 1601 ddi_regs_map_free(&pcic->handle); 1602 if (pcic->pc_flags & PCF_PCIBUS) 1603 ddi_regs_map_free(&pcic->cfg_handle); 1604 kmem_free(pcic->pc_intr_htblp, pcic->pc_numsockets * 1605 sizeof (ddi_intr_handle_t)); 1606 kmem_free(pcic, sizeof (pcicdev_t)); 1607 return (DDI_FAILURE); 1608 1609 pci_exit2: 1610 mutex_destroy(&pcic->intr_lock); 1611 mutex_destroy(&pcic->pc_lock); 1612 (void) ddi_intr_free(pcic->pc_pci_intr_hdlp[0]); 1613 pci_exit1: 1614 ddi_regs_map_free(&pcic->handle); 1615 if (pcic->pc_flags & PCF_PCIBUS) 1616 ddi_regs_map_free(&pcic->cfg_handle); 1617 kmem_free(pcic->pc_pci_intr_hdlp, sizeof (ddi_intr_handle_t)); 1618 kmem_free(pcic, sizeof (pcicdev_t)); 1619 return (DDI_FAILURE); 1620 } 1621 1622 /* 1623 * pcic_detach() 1624 * request to detach from the system 1625 */ 1626 static int 1627 pcic_detach(dev_info_t *dip, ddi_detach_cmd_t cmd) 1628 { 1629 anp_t *anp = ddi_get_driver_private(dip); 1630 pcicdev_t *pcic = anp->an_private; 1631 int i; 1632 1633 switch (cmd) { 1634 case DDI_DETACH: 1635 /* don't detach if the nexus still talks to us */ 1636 if (pcic->pc_callback != NULL) 1637 return (DDI_FAILURE); 1638 1639 /* kill off the pm simulation */ 1640 if (pcic->pc_pmtimer) 1641 (void) untimeout(pcic->pc_pmtimer); 1642 1643 /* turn everything off for all sockets and chips */ 1644 for (i = 0; i < pcic->pc_numsockets; i++) { 1645 if (pcic->pc_sockets[i].pcs_debounce_id) 1646 pcic_rm_debqueue( 1647 pcic->pc_sockets[i].pcs_debounce_id); 1648 pcic->pc_sockets[i].pcs_debounce_id = 0; 1649 1650 pcic_putb(pcic, i, PCIC_MANAGEMENT_INT, 0); 1651 pcic_putb(pcic, i, PCIC_CARD_DETECT, 0); 1652 pcic_putb(pcic, i, PCIC_MAPPING_ENABLE, 0); 1653 /* disable interrupts and put card into RESET */ 1654 pcic_putb(pcic, i, PCIC_INTERRUPT, 0); 1655 } 1656 (void) ddi_intr_disable(pcic->pc_pci_intr_hdlp[0]); 1657 (void) ddi_intr_remove_handler(pcic->pc_pci_intr_hdlp[0]); 1658 (void) ddi_intr_free(pcic->pc_pci_intr_hdlp[0]); 1659 kmem_free(pcic->pc_pci_intr_hdlp, sizeof (ddi_intr_handle_t)); 1660 pcic->pc_flags = 0; 1661 mutex_destroy(&pcic->pc_lock); 1662 mutex_destroy(&pcic->intr_lock); 1663 cv_destroy(&pcic->pm_cv); 1664 if (pcic->pc_flags & PCF_PCIBUS) 1665 ddi_regs_map_free(&pcic->cfg_handle); 1666 if (pcic->handle) 1667 ddi_regs_map_free(&pcic->handle); 1668 kmem_free(pcic, sizeof (pcicdev_t)); 1669 ddi_soft_state_free(pcic_soft_state_p, ddi_get_instance(dip)); 1670 return (DDI_SUCCESS); 1671 1672 case DDI_SUSPEND: 1673 case DDI_PM_SUSPEND: 1674 /* 1675 * we got a suspend event (either real or imagined) 1676 * so notify the nexus proper that all existing cards 1677 * should go away. 1678 */ 1679 mutex_enter(&pcic->pc_lock); 1680 #ifdef CARDBUS 1681 if (pcic->pc_flags & PCF_CARDBUS) 1682 for (i = 0; i < pcic->pc_numsockets; i++) 1683 if ((pcic->pc_sockets[i].pcs_flags & 1684 (PCS_CARD_PRESENT|PCS_CARD_ISCARDBUS)) == 1685 (PCS_CARD_PRESENT|PCS_CARD_ISCARDBUS)) 1686 if (!cardbus_can_suspend(dip)) { 1687 mutex_exit(&pcic->pc_lock); 1688 cmn_err(CE_WARN, 1689 "Please unconfigure all " 1690 "CardBus devices before " 1691 "attempting to suspend\n"); 1692 return (DDI_FAILURE); 1693 } 1694 #endif 1695 /* turn everything off for all sockets and chips */ 1696 for (i = 0; i < pcic->pc_numsockets; i++) { 1697 if (pcic->pc_sockets[i].pcs_debounce_id) 1698 pcic_rm_debqueue( 1699 pcic->pc_sockets[i].pcs_debounce_id); 1700 pcic->pc_sockets[i].pcs_debounce_id = 0; 1701 1702 pcic_putb(pcic, i, PCIC_MANAGEMENT_INT, 0); 1703 pcic_putb(pcic, i, PCIC_CARD_DETECT, 0); 1704 pcic_putb(pcic, i, PCIC_MAPPING_ENABLE, 0); 1705 /* disable interrupts and put card into RESET */ 1706 pcic_putb(pcic, i, PCIC_INTERRUPT, 0); 1707 pcic_putb(pcic, i, PCIC_POWER_CONTROL, 0); 1708 if (pcic->pc_flags & PCF_CBPWRCTL) 1709 pcic_putcb(pcic, CB_CONTROL, 0); 1710 1711 if (pcic->pc_sockets[i].pcs_flags & PCS_CARD_PRESENT) { 1712 pcic->pc_sockets[i].pcs_flags = PCS_STARTING; 1713 /* 1714 * Because we are half way through a save 1715 * all this does is schedule a removal event 1716 * to cs for when the system comes back. 1717 * This doesn't actually matter. 1718 */ 1719 if (!pcic_do_pcmcia_sr && pcic_do_removal && 1720 pcic->pc_callback) { 1721 PC_CALLBACK(pcic->dip, pcic->pc_cb_arg, 1722 PCE_CARD_REMOVAL, 1723 pcic->pc_sockets[i].pcs_socket); 1724 } 1725 } 1726 } 1727 1728 pcic->pc_flags |= PCF_SUSPENDED; 1729 mutex_exit(&pcic->pc_lock); 1730 pcic_delayed_resume_toid = 0; 1731 1732 /* 1733 * when true power management exists, save the adapter 1734 * state here to enable a recovery. For the emulation 1735 * condition, the state is gone 1736 */ 1737 return (DDI_SUCCESS); 1738 1739 default: 1740 return (EINVAL); 1741 } 1742 } 1743 1744 static uint32_t pcic_tisysctl_onbits = ((1<<27) | (1<<15) | (1<<14)); 1745 static uint32_t pcic_tisysctl_offbits = 0; 1746 static uint32_t pcic_default_latency = 0x40; 1747 1748 static void 1749 pcic_setup_adapter(pcicdev_t *pcic) 1750 { 1751 int i; 1752 int value, flags; 1753 1754 if (pcic->pc_flags & PCF_PCIBUS) { 1755 /* 1756 * all PCI-to-PCMCIA bus bridges need memory and I/O enabled 1757 */ 1758 flags = (PCIC_ENABLE_IO | PCIC_ENABLE_MEM); 1759 pcic_iomem_pci_ctl(pcic->cfg_handle, pcic->cfgaddr, flags); 1760 } 1761 /* enable each socket */ 1762 for (i = 0; i < pcic->pc_numsockets; i++) { 1763 pcic->pc_sockets[i].pcs_flags = 0; 1764 /* find out the socket capabilities (I/O vs memory) */ 1765 value = pcic_getb(pcic, i, 1766 PCIC_CHIP_REVISION) & PCIC_REV_ID_MASK; 1767 if (value == PCIC_REV_ID_IO || value == PCIC_REV_ID_BOTH) 1768 pcic->pc_sockets[i].pcs_flags |= PCS_SOCKET_IO; 1769 1770 /* disable all windows just in case */ 1771 pcic_putb(pcic, i, PCIC_MAPPING_ENABLE, 0); 1772 1773 switch (pcic->pc_type) { 1774 uint32_t cfg32; 1775 uint16_t cfg16; 1776 uint8_t cfg; 1777 1778 /* enable extended registers for Vadem */ 1779 case PCIC_VADEM_VG469: 1780 case PCIC_VADEM: 1781 1782 /* enable card status change interrupt for socket */ 1783 break; 1784 1785 case PCIC_I82365SL: 1786 break; 1787 1788 case PCIC_CL_PD6710: 1789 pcic_putb(pcic, 0, PCIC_MISC_CTL_2, PCIC_LED_ENABLE); 1790 break; 1791 1792 /* 1793 * On the CL_6730, we need to set up the interrupt 1794 * signalling mode (PCI mode) and set the SMI and 1795 * IRQ interrupt lines to PCI/level-mode. 1796 */ 1797 case PCIC_CL_PD6730: 1798 switch (pcic->pc_intr_mode) { 1799 case PCIC_INTR_MODE_PCI_1: 1800 clext_reg_write(pcic, i, PCIC_CLEXT_MISC_CTL_3, 1801 ((clext_reg_read(pcic, i, 1802 PCIC_CLEXT_MISC_CTL_3) & 1803 ~PCIC_CLEXT_INT_PCI) | 1804 PCIC_CLEXT_INT_PCI)); 1805 clext_reg_write(pcic, i, PCIC_CLEXT_EXT_CTL_1, 1806 (PCIC_CLEXT_IRQ_LVL_MODE | 1807 PCIC_CLEXT_SMI_LVL_MODE)); 1808 cfg = PCIC_CL_LP_DYN_MODE; 1809 pcic_putb(pcic, i, PCIC_MISC_CTL_2, cfg); 1810 break; 1811 case PCIC_INTR_MODE_ISA: 1812 break; 1813 } 1814 break; 1815 /* 1816 * On the CL_6729, we set the SMI and IRQ interrupt 1817 * lines to PCI/level-mode. as well as program the 1818 * correct clock speed divider bit. 1819 */ 1820 case PCIC_CL_PD6729: 1821 switch (pcic->pc_intr_mode) { 1822 case PCIC_INTR_MODE_PCI_1: 1823 clext_reg_write(pcic, i, PCIC_CLEXT_EXT_CTL_1, 1824 (PCIC_CLEXT_IRQ_LVL_MODE | 1825 PCIC_CLEXT_SMI_LVL_MODE)); 1826 1827 break; 1828 case PCIC_INTR_MODE_ISA: 1829 break; 1830 } 1831 if (pcic->bus_speed > PCIC_PCI_25MHZ && i == 0) { 1832 cfg = 0; 1833 cfg |= PCIC_CL_TIMER_CLK_DIV; 1834 pcic_putb(pcic, i, PCIC_MISC_CTL_2, cfg); 1835 } 1836 break; 1837 case PCIC_INTEL_i82092: 1838 cfg = PCIC_82092_EN_TIMING; 1839 if (pcic->bus_speed < PCIC_SYSCLK_33MHZ) 1840 cfg |= PCIC_82092_PCICLK_25MHZ; 1841 ddi_put8(pcic->cfg_handle, pcic->cfgaddr + 1842 PCIC_82092_PCICON, cfg); 1843 break; 1844 case PCIC_TI_PCI1130: 1845 case PCIC_TI_PCI1131: 1846 case PCIC_TI_PCI1250: 1847 case PCIC_TI_PCI1031: 1848 cfg = ddi_get8(pcic->cfg_handle, 1849 pcic->cfgaddr + PCIC_DEVCTL_REG); 1850 cfg &= ~PCIC_DEVCTL_INTR_MASK; 1851 switch (pcic->pc_intr_mode) { 1852 case PCIC_INTR_MODE_ISA: 1853 cfg |= PCIC_DEVCTL_INTR_ISA; 1854 break; 1855 } 1856 #ifdef PCIC_DEBUG 1857 if (pcic_debug) { 1858 cmn_err(CE_CONT, "pcic_setup_adapter: " 1859 "write reg 0x%x=%x \n", 1860 PCIC_DEVCTL_REG, cfg); 1861 } 1862 #endif 1863 ddi_put8(pcic->cfg_handle, 1864 pcic->cfgaddr + PCIC_DEVCTL_REG, 1865 cfg); 1866 1867 cfg = ddi_get8(pcic->cfg_handle, 1868 pcic->cfgaddr + PCIC_CRDCTL_REG); 1869 cfg &= ~(PCIC_CRDCTL_PCIINTR|PCIC_CRDCTL_PCICSC| 1870 PCIC_CRDCTL_PCIFUNC); 1871 switch (pcic->pc_intr_mode) { 1872 case PCIC_INTR_MODE_PCI_1: 1873 cfg |= PCIC_CRDCTL_PCIINTR | 1874 PCIC_CRDCTL_PCICSC | 1875 PCIC_CRDCTL_PCIFUNC; 1876 pcic->pc_flags |= PCF_USE_SMI; 1877 break; 1878 } 1879 #ifdef PCIC_DEBUG 1880 if (pcic_debug) { 1881 cmn_err(CE_CONT, "pcic_setup_adapter: " 1882 " write reg 0x%x=%x \n", 1883 PCIC_CRDCTL_REG, cfg); 1884 } 1885 #endif 1886 ddi_put8(pcic->cfg_handle, 1887 pcic->cfgaddr + PCIC_CRDCTL_REG, 1888 cfg); 1889 break; 1890 case PCIC_TI_PCI1221: 1891 case PCIC_TI_PCI1225: 1892 cfg = ddi_get8(pcic->cfg_handle, 1893 pcic->cfgaddr + PCIC_DEVCTL_REG); 1894 cfg |= (PCIC_DEVCTL_INTR_DFLT | PCIC_DEVCTL_3VCAPABLE); 1895 #ifdef PCIC_DEBUG 1896 if (pcic_debug) { 1897 cmn_err(CE_CONT, "pcic_setup_adapter: " 1898 " write reg 0x%x=%x \n", 1899 PCIC_DEVCTL_REG, cfg); 1900 } 1901 #endif 1902 ddi_put8(pcic->cfg_handle, 1903 pcic->cfgaddr + PCIC_DEVCTL_REG, cfg); 1904 1905 cfg = ddi_get8(pcic->cfg_handle, 1906 pcic->cfgaddr + PCIC_DIAG_REG); 1907 if (pcic->pc_type == PCIC_TI_PCI1225) { 1908 cfg |= (PCIC_DIAG_CSC | PCIC_DIAG_ASYNC); 1909 } else { 1910 cfg |= PCIC_DIAG_ASYNC; 1911 } 1912 pcic->pc_flags |= PCF_USE_SMI; 1913 #ifdef PCIC_DEBUG 1914 if (pcic_debug) { 1915 cmn_err(CE_CONT, "pcic_setup_adapter: " 1916 " write reg 0x%x=%x \n", 1917 PCIC_DIAG_REG, cfg); 1918 } 1919 #endif 1920 ddi_put8(pcic->cfg_handle, 1921 pcic->cfgaddr + PCIC_DIAG_REG, cfg); 1922 break; 1923 case PCIC_TI_PCI1520: 1924 case PCIC_TI_PCI1510: 1925 case PCIC_TI_VENDOR: 1926 if (pcic->pc_intr_mode == PCIC_INTR_MODE_ISA) { 1927 cfg = ddi_get8(pcic->cfg_handle, 1928 pcic->cfgaddr + PCIC_BRIDGE_CTL_REG); 1929 cfg |= PCIC_FUN_INT_MOD_ISA; 1930 ddi_put8(pcic->cfg_handle, 1931 pcic->cfgaddr + PCIC_BRIDGE_CTL_REG, 1932 cfg); 1933 } 1934 cfg = ddi_get8(pcic->cfg_handle, 1935 pcic->cfgaddr + PCIC_DEVCTL_REG); 1936 cfg &= ~PCIC_DEVCTL_INTR_MASK; 1937 if (pcic->pc_intr_mode == PCIC_INTR_MODE_ISA) 1938 cfg |= PCIC_DEVCTL_INTR_ISA; 1939 ddi_put8(pcic->cfg_handle, 1940 pcic->cfgaddr + PCIC_DEVCTL_REG, 1941 cfg); 1942 1943 /* tie INTA and INTB together */ 1944 cfg = ddi_get8(pcic->cfg_handle, 1945 (pcic->cfgaddr + PCIC_SYSCTL_REG + 3)); 1946 cfg |= PCIC_SYSCTL_INTRTIE; 1947 ddi_put8(pcic->cfg_handle, (pcic->cfgaddr + 1948 PCIC_SYSCTL_REG + 3), cfg); 1949 cfg = ddi_get8(pcic->cfg_handle, 1950 pcic->cfgaddr + PCIC_DIAG_REG); 1951 cfg |= (PCIC_DIAG_CSC | PCIC_DIAG_ASYNC); 1952 ddi_put8(pcic->cfg_handle, 1953 pcic->cfgaddr + PCIC_DIAG_REG, cfg); 1954 break; 1955 case PCIC_TI_PCI1410: 1956 cfg = ddi_get8(pcic->cfg_handle, 1957 pcic->cfgaddr + PCIC_DIAG_REG); 1958 cfg |= (PCIC_DIAG_CSC | PCIC_DIAG_ASYNC); 1959 ddi_put8(pcic->cfg_handle, 1960 pcic->cfgaddr + PCIC_DIAG_REG, cfg); 1961 break; 1962 case PCIC_TOSHIBA_TOPIC100: 1963 case PCIC_TOSHIBA_TOPIC95: 1964 case PCIC_TOSHIBA_VENDOR: 1965 cfg = ddi_get8(pcic->cfg_handle, pcic->cfgaddr + 1966 PCIC_TOSHIBA_SLOT_CTL_REG); 1967 cfg |= (PCIC_TOSHIBA_SCR_SLOTON | 1968 PCIC_TOSHIBA_SCR_SLOTEN); 1969 cfg &= (~PCIC_TOSHIBA_SCR_PRT_MASK); 1970 cfg |= PCIC_TOSHIBA_SCR_PRT_3E2; 1971 ddi_put8(pcic->cfg_handle, pcic->cfgaddr + 1972 PCIC_TOSHIBA_SLOT_CTL_REG, cfg); 1973 cfg = ddi_get8(pcic->cfg_handle, pcic->cfgaddr + 1974 PCIC_TOSHIBA_INTR_CTL_REG); 1975 switch (pcic->pc_intr_mode) { 1976 case PCIC_INTR_MODE_ISA: 1977 cfg &= ~PCIC_TOSHIBA_ICR_SRC; 1978 ddi_put8(pcic->cfg_handle, 1979 pcic->cfgaddr + 1980 PCIC_TOSHIBA_INTR_CTL_REG, cfg); 1981 1982 cfg = ddi_get8(pcic->cfg_handle, 1983 pcic->cfgaddr + PCIC_BRIDGE_CTL_REG); 1984 cfg |= PCIC_FUN_INT_MOD_ISA; 1985 ddi_put8(pcic->cfg_handle, 1986 pcic->cfgaddr + PCIC_BRIDGE_CTL_REG, 1987 cfg); 1988 break; 1989 case PCIC_INTR_MODE_PCI_1: 1990 cfg |= PCIC_TOSHIBA_ICR_SRC; 1991 cfg &= (~PCIC_TOSHIBA_ICR_PIN_MASK); 1992 cfg |= PCIC_TOSHIBA_ICR_PIN_INTA; 1993 ddi_put8(pcic->cfg_handle, 1994 pcic->cfgaddr + 1995 PCIC_TOSHIBA_INTR_CTL_REG, cfg); 1996 break; 1997 } 1998 break; 1999 case PCIC_O2MICRO_VENDOR: 2000 cfg32 = ddi_get32(pcic->cfg_handle, 2001 (uint32_t *)(pcic->cfgaddr + 2002 PCIC_O2MICRO_MISC_CTL)); 2003 switch (pcic->pc_intr_mode) { 2004 case PCIC_INTR_MODE_ISA: 2005 cfg32 |= (PCIC_O2MICRO_ISA_LEGACY | 2006 PCIC_O2MICRO_INT_MOD_PCI); 2007 ddi_put32(pcic->cfg_handle, 2008 (uint32_t *)(pcic->cfgaddr + 2009 PCIC_O2MICRO_MISC_CTL), 2010 cfg32); 2011 cfg = ddi_get8(pcic->cfg_handle, 2012 pcic->cfgaddr + PCIC_BRIDGE_CTL_REG); 2013 cfg |= PCIC_FUN_INT_MOD_ISA; 2014 ddi_put8(pcic->cfg_handle, 2015 pcic->cfgaddr + PCIC_BRIDGE_CTL_REG, 2016 cfg); 2017 break; 2018 case PCIC_INTR_MODE_PCI_1: 2019 cfg32 &= ~PCIC_O2MICRO_ISA_LEGACY; 2020 cfg32 |= PCIC_O2MICRO_INT_MOD_PCI; 2021 ddi_put32(pcic->cfg_handle, 2022 (uint32_t *)(pcic->cfgaddr + 2023 PCIC_O2MICRO_MISC_CTL), 2024 cfg32); 2025 break; 2026 } 2027 break; 2028 case PCIC_RICOH_VENDOR: 2029 if (pcic->pc_intr_mode == PCIC_INTR_MODE_ISA) { 2030 cfg16 = ddi_get16(pcic->cfg_handle, 2031 (uint16_t *)(pcic->cfgaddr + 2032 PCIC_RICOH_MISC_CTL_2)); 2033 cfg16 |= (PCIC_RICOH_CSC_INT_MOD | 2034 PCIC_RICOH_FUN_INT_MOD); 2035 ddi_put16(pcic->cfg_handle, 2036 (uint16_t *)(pcic->cfgaddr + 2037 PCIC_RICOH_MISC_CTL_2), 2038 cfg16); 2039 2040 cfg16 = ddi_get16(pcic->cfg_handle, 2041 (uint16_t *)(pcic->cfgaddr + 2042 PCIC_RICOH_MISC_CTL)); 2043 cfg16 |= PCIC_RICOH_SIRQ_EN; 2044 ddi_put16(pcic->cfg_handle, 2045 (uint16_t *)(pcic->cfgaddr + 2046 PCIC_RICOH_MISC_CTL), 2047 cfg16); 2048 2049 cfg = ddi_get8(pcic->cfg_handle, 2050 pcic->cfgaddr + PCIC_BRIDGE_CTL_REG); 2051 cfg |= PCIC_FUN_INT_MOD_ISA; 2052 ddi_put8(pcic->cfg_handle, 2053 pcic->cfgaddr + PCIC_BRIDGE_CTL_REG, 2054 cfg); 2055 } 2056 break; 2057 default: 2058 break; 2059 } /* switch */ 2060 2061 /* 2062 * The default value in the EEPROM (loaded on reset) for 2063 * MFUNC0/MFUNC1 may be incorrect. Here we make sure that 2064 * MFUNC0 is connected to INTA, and MFUNC1 is connected to 2065 * INTB. This applies to all TI CardBus controllers. 2066 */ 2067 if ((pcic->pc_type >> 16) == PCIC_TI_VENDORID && 2068 pcic->pc_intr_mode == PCIC_INTR_MODE_PCI_1) { 2069 value = ddi_get32(pcic->cfg_handle, 2070 (uint32_t *)(pcic->cfgaddr + PCIC_MFROUTE_REG)); 2071 value &= ~0xff; 2072 ddi_put32(pcic->cfg_handle, (uint32_t *)(pcic->cfgaddr + 2073 PCIC_MFROUTE_REG), value|PCIC_TI_MFUNC_SEL); 2074 } 2075 2076 /* setup general card status change interrupt */ 2077 switch (pcic->pc_type) { 2078 case PCIC_TI_PCI1225: 2079 case PCIC_TI_PCI1221: 2080 case PCIC_TI_PCI1031: 2081 case PCIC_TI_PCI1520: 2082 case PCIC_TI_PCI1410: 2083 pcic_putb(pcic, i, PCIC_MANAGEMENT_INT, 2084 PCIC_CHANGE_DEFAULT); 2085 break; 2086 default: 2087 if (pcic->pc_intr_mode == 2088 PCIC_INTR_MODE_PCI_1) { 2089 pcic_putb(pcic, i, PCIC_MANAGEMENT_INT, 2090 PCIC_CHANGE_DEFAULT); 2091 break; 2092 } else { 2093 pcic_putb(pcic, i, PCIC_MANAGEMENT_INT, 2094 PCIC_CHANGE_DEFAULT | 2095 (pcic->pc_sockets[i].pcs_smi << 4)); 2096 break; 2097 } 2098 } 2099 2100 pcic->pc_flags |= PCF_INTRENAB; 2101 2102 /* take card out of RESET */ 2103 pcic_putb(pcic, i, PCIC_INTERRUPT, PCIC_RESET); 2104 /* turn power off and let CS do this */ 2105 pcic_putb(pcic, i, PCIC_POWER_CONTROL, 0); 2106 2107 /* final chip specific initialization */ 2108 switch (pcic->pc_type) { 2109 case PCIC_VADEM: 2110 pcic_putb(pcic, i, PCIC_VG_CONTROL, 2111 PCIC_VC_DELAYENABLE); 2112 pcic->pc_flags |= PCF_DEBOUNCE; 2113 /* FALLTHROUGH */ 2114 case PCIC_I82365SL: 2115 pcic_putb(pcic, i, PCIC_GLOBAL_CONTROL, 2116 PCIC_GC_CSC_WRITE); 2117 /* clear any pending interrupts */ 2118 value = pcic_getb(pcic, i, PCIC_CARD_STATUS_CHANGE); 2119 pcic_putb(pcic, i, PCIC_CARD_STATUS_CHANGE, value); 2120 break; 2121 /* The 82092 uses PCI config space to enable interrupts */ 2122 case PCIC_INTEL_i82092: 2123 pcic_82092_smiirq_ctl(pcic, i, PCIC_82092_CTL_SMI, 2124 PCIC_82092_INT_ENABLE); 2125 break; 2126 case PCIC_CL_PD6729: 2127 if (pcic->bus_speed >= PCIC_PCI_DEF_SYSCLK && i == 0) { 2128 value = pcic_getb(pcic, i, PCIC_MISC_CTL_2); 2129 pcic_putb(pcic, i, PCIC_MISC_CTL_2, 2130 value | PCIC_CL_TIMER_CLK_DIV); 2131 } 2132 break; 2133 } /* switch */ 2134 2135 #if defined(PCIC_DEBUG) 2136 if (pcic_debug) 2137 cmn_err(CE_CONT, 2138 "socket %d value=%x, flags = %x (%s)\n", 2139 i, value, pcic->pc_sockets[i].pcs_flags, 2140 (pcic->pc_sockets[i].pcs_flags & 2141 PCS_CARD_PRESENT) ? 2142 "card present" : "no card"); 2143 #endif 2144 } 2145 } 2146 2147 /* 2148 * pcic_intr(caddr_t, caddr_t) 2149 * interrupt handler for the PCIC style adapter 2150 * handles all basic interrupts and also checks 2151 * for status changes and notifies the nexus if 2152 * necessary 2153 * 2154 * On PCI bus adapters, also handles all card 2155 * IO interrupts. 2156 */ 2157 /*ARGSUSED*/ 2158 uint32_t 2159 pcic_intr(caddr_t arg1, caddr_t arg2) 2160 { 2161 pcicdev_t *pcic = (pcicdev_t *)arg1; 2162 int value = 0, i, ret = DDI_INTR_UNCLAIMED; 2163 uint8_t status; 2164 uint_t io_ints; 2165 2166 #if defined(PCIC_DEBUG) 2167 pcic_err(pcic->dip, 0xf, 2168 "pcic_intr: enter pc_flags=0x%x PCF_ATTACHED=0x%x" 2169 " pc_numsockets=%d \n", 2170 pcic->pc_flags, PCF_ATTACHED, pcic->pc_numsockets); 2171 #endif 2172 2173 if (!(pcic->pc_flags & PCF_ATTACHED)) 2174 return (DDI_INTR_UNCLAIMED); 2175 2176 mutex_enter(&pcic->intr_lock); 2177 2178 if (pcic->pc_flags & PCF_SUSPENDED) { 2179 mutex_exit(&pcic->intr_lock); 2180 return (ret); 2181 } 2182 2183 /* 2184 * need to change to only ACK and touch the slot that 2185 * actually caused the interrupt. Currently everything 2186 * is acked 2187 * 2188 * we need to look at all known sockets to determine 2189 * what might have happened, so step through the list 2190 * of them 2191 */ 2192 2193 /* 2194 * Set the bitmask for IO interrupts to initially include all sockets 2195 */ 2196 io_ints = (1 << pcic->pc_numsockets) - 1; 2197 2198 for (i = 0; i < pcic->pc_numsockets; i++) { 2199 int card_type; 2200 pcic_socket_t *sockp; 2201 int value_cb = 0; 2202 2203 sockp = &pcic->pc_sockets[i]; 2204 /* get the socket's I/O addresses */ 2205 2206 if (sockp->pcs_flags & PCS_WAITING) { 2207 io_ints &= ~(1 << i); 2208 continue; 2209 } 2210 2211 if (sockp->pcs_flags & PCS_CARD_IO) 2212 card_type = IF_IO; 2213 else 2214 card_type = IF_MEMORY; 2215 2216 if (pcic->pc_io_type == PCIC_IO_TYPE_YENTA) 2217 value_cb = pcic_getcb(pcic, CB_STATUS_EVENT); 2218 2219 value = pcic_change(pcic, i); 2220 2221 if ((value != 0) || (value_cb != 0)) { 2222 int x = pcic->pc_cb_arg; 2223 2224 ret = DDI_INTR_CLAIMED; 2225 2226 #if defined(PCIC_DEBUG) 2227 pcic_err(pcic->dip, 0x9, 2228 "card_type = %d, value_cb = 0x%x\n", 2229 card_type, 2230 value_cb ? value_cb : 2231 pcic_getcb(pcic, CB_STATUS_EVENT)); 2232 if (pcic_debug) 2233 cmn_err(CE_CONT, 2234 "\tchange on socket %d (%x)\n", i, 2235 value); 2236 #endif 2237 /* find out what happened */ 2238 status = pcic_getb(pcic, i, PCIC_INTERFACE_STATUS); 2239 2240 /* acknowledge the interrupt */ 2241 if (value_cb) 2242 pcic_putcb(pcic, CB_STATUS_EVENT, value_cb); 2243 2244 if (value) 2245 pcic_putb(pcic, i, PCIC_CARD_STATUS_CHANGE, 2246 value); 2247 2248 if (pcic->pc_callback == NULL) { 2249 /* if not callback handler, nothing to do */ 2250 continue; 2251 } 2252 2253 /* Card Detect */ 2254 if (value & PCIC_CD_DETECT || 2255 value_cb & CB_PS_CCDMASK) { 2256 uint8_t irq; 2257 #if defined(PCIC_DEBUG) 2258 if (pcic_debug) 2259 cmn_err(CE_CONT, 2260 "\tcd_detect: status=%x," 2261 " flags=%x\n", 2262 status, sockp->pcs_flags); 2263 #else 2264 #ifdef lint 2265 if (status == 0) 2266 status++; 2267 #endif 2268 #endif 2269 /* 2270 * Turn off all interrupts for this socket here. 2271 */ 2272 irq = pcic_getb(pcic, sockp->pcs_socket, 2273 PCIC_MANAGEMENT_INT); 2274 irq &= ~PCIC_CHANGE_MASK; 2275 pcic_putb(pcic, sockp->pcs_socket, 2276 PCIC_MANAGEMENT_INT, irq); 2277 2278 pcic_putcb(pcic, CB_STATUS_MASK, 0x0); 2279 2280 /* 2281 * Put the socket in debouncing state so that 2282 * the leaf driver won't receive interrupts. 2283 * Crucial for handling surprise-removal. 2284 */ 2285 sockp->pcs_flags |= PCS_DEBOUNCING; 2286 2287 if (!sockp->pcs_cd_softint_flg) { 2288 sockp->pcs_cd_softint_flg = 1; 2289 (void) ddi_intr_trigger_softint( 2290 sockp->pcs_cd_softint_hdl, NULL); 2291 } 2292 2293 io_ints &= ~(1 << i); 2294 } /* PCIC_CD_DETECT */ 2295 2296 /* Ready/Change Detect */ 2297 sockp->pcs_state ^= SBM_RDYBSY; 2298 if (card_type == IF_MEMORY && value & PCIC_RD_DETECT) { 2299 sockp->pcs_flags |= PCS_READY; 2300 PC_CALLBACK(pcic->dip, x, PCE_CARD_READY, i); 2301 } 2302 2303 /* Battery Warn Detect */ 2304 if (card_type == IF_MEMORY && 2305 value & PCIC_BW_DETECT && 2306 !(sockp->pcs_state & SBM_BVD2)) { 2307 sockp->pcs_state |= SBM_BVD2; 2308 PC_CALLBACK(pcic->dip, x, 2309 PCE_CARD_BATTERY_WARN, i); 2310 } 2311 2312 /* Battery Dead Detect */ 2313 if (value & PCIC_BD_DETECT) { 2314 /* 2315 * need to work out event if RI not enabled 2316 * and card_type == IF_IO 2317 */ 2318 if (card_type == IF_MEMORY && 2319 !(sockp->pcs_state & SBM_BVD1)) { 2320 sockp->pcs_state |= SBM_BVD1; 2321 PC_CALLBACK(pcic->dip, x, 2322 PCE_CARD_BATTERY_DEAD, 2323 i); 2324 } else { 2325 /* 2326 * information in pin replacement 2327 * register if one is available 2328 */ 2329 PC_CALLBACK(pcic->dip, x, 2330 PCE_CARD_STATUS_CHANGE, 2331 i); 2332 } /* IF_MEMORY */ 2333 } /* PCIC_BD_DETECT */ 2334 } /* if pcic_change */ 2335 /* 2336 * for any controllers that we can detect whether a socket 2337 * had an interrupt for the PC Card, we should sort that out 2338 * here. 2339 */ 2340 } /* for pc_numsockets */ 2341 2342 /* 2343 * If we're on a PCI bus, we may need to cycle through each IO 2344 * interrupt handler that is registered since they all 2345 * share the same interrupt line. 2346 */ 2347 2348 2349 #if defined(PCIC_DEBUG) 2350 pcic_err(pcic->dip, 0xf, 2351 "pcic_intr: pc_intr_mode=%d pc_type=%x io_ints=0x%x\n", 2352 pcic->pc_intr_mode, pcic->pc_type, io_ints); 2353 #endif 2354 2355 if (io_ints) { 2356 if (pcic_do_io_intr(pcic, io_ints) == DDI_INTR_CLAIMED) 2357 ret = DDI_INTR_CLAIMED; 2358 } 2359 2360 mutex_exit(&pcic->intr_lock); 2361 2362 #if defined(PCIC_DEBUG) 2363 pcic_err(pcic->dip, 0xf, 2364 "pcic_intr: ret=%d value=%d DDI_INTR_CLAIMED=%d\n", 2365 ret, value, DDI_INTR_CLAIMED); 2366 #endif 2367 2368 return (ret); 2369 } 2370 2371 /* 2372 * pcic_change() 2373 * check to see if this socket had a change in state 2374 * by checking the status change register 2375 */ 2376 static int 2377 pcic_change(pcicdev_t *pcic, int socket) 2378 { 2379 return (pcic_getb(pcic, socket, PCIC_CARD_STATUS_CHANGE)); 2380 } 2381 2382 /* 2383 * pcic_do_io_intr - calls client interrupt handlers 2384 */ 2385 static int 2386 pcic_do_io_intr(pcicdev_t *pcic, uint32_t sockets) 2387 { 2388 inthandler_t *tmp; 2389 int ret = DDI_INTR_UNCLAIMED; 2390 2391 #if defined(PCIC_DEBUG) 2392 pcic_err(pcic->dip, 0xf, 2393 "pcic_do_io_intr: pcic=%p sockets=%d irq_top=%p\n", 2394 (void *)pcic, (int)sockets, (void *)pcic->irq_top); 2395 #endif 2396 2397 if (pcic->irq_top != NULL) { 2398 tmp = pcic->irq_current; 2399 2400 do { 2401 int cur = pcic->irq_current->socket; 2402 pcic_socket_t *sockp = 2403 &pcic->pc_sockets[cur]; 2404 2405 #if defined(PCIC_DEBUG) 2406 pcic_err(pcic->dip, 0xf, 2407 "\t pcs_flags=0x%x PCS_CARD_PRESENT=0x%x\n", 2408 sockp->pcs_flags, PCS_CARD_PRESENT); 2409 pcic_err(pcic->dip, 0xf, 2410 "\t sockets=%d cur=%d intr=%p arg1=%p " 2411 "arg2=%p\n", 2412 sockets, cur, (void *)pcic->irq_current->intr, 2413 pcic->irq_current->arg1, 2414 pcic->irq_current->arg2); 2415 #endif 2416 if ((sockp->pcs_flags & PCS_CARD_PRESENT) && 2417 !(sockp->pcs_flags & PCS_DEBOUNCING) && 2418 (sockets & (1 << cur))) { 2419 2420 if ((*pcic->irq_current->intr)(pcic->irq_current->arg1, 2421 pcic->irq_current->arg2) == DDI_INTR_CLAIMED) 2422 ret = DDI_INTR_CLAIMED; 2423 2424 #if defined(PCIC_DEBUG) 2425 pcic_err(pcic->dip, 0xf, 2426 "\t ret=%d DDI_INTR_CLAIMED=%d\n", 2427 ret, DDI_INTR_CLAIMED); 2428 #endif 2429 } 2430 2431 2432 if ((pcic->irq_current = pcic->irq_current->next) == NULL) 2433 pcic->irq_current = pcic->irq_top; 2434 2435 } while (pcic->irq_current != tmp); 2436 2437 if ((pcic->irq_current = pcic->irq_current->next) == NULL) 2438 pcic->irq_current = pcic->irq_top; 2439 2440 } else { 2441 ret = DDI_INTR_UNCLAIMED; 2442 } 2443 2444 #if defined(PCIC_DEBUG) 2445 pcic_err(pcic->dip, 0xf, 2446 "pcic_do_io_intr: exit ret=%d DDI_INTR_CLAIMED=%d\n", 2447 ret, DDI_INTR_CLAIMED); 2448 #endif 2449 2450 return (ret); 2451 2452 } 2453 2454 /* 2455 * pcic_inquire_adapter() 2456 * SocketServices InquireAdapter function 2457 * get characteristics of the physical adapter 2458 */ 2459 /*ARGSUSED*/ 2460 static int 2461 pcic_inquire_adapter(dev_info_t *dip, inquire_adapter_t *config) 2462 { 2463 anp_t *anp = ddi_get_driver_private(dip); 2464 pcicdev_t *pcic = anp->an_private; 2465 2466 config->NumSockets = pcic->pc_numsockets; 2467 config->NumWindows = pcic->pc_numsockets * PCIC_NUMWINSOCK; 2468 config->NumEDCs = 0; 2469 config->AdpCaps = 0; 2470 config->ActiveHigh = 0; 2471 config->ActiveLow = PCIC_AVAIL_IRQS; 2472 config->NumPower = pcic->pc_numpower; 2473 config->power_entry = pcic->pc_power; /* until we resolve this */ 2474 #if defined(PCIC_DEBUG) 2475 if (pcic_debug) { 2476 cmn_err(CE_CONT, "pcic_inquire_adapter:\n"); 2477 cmn_err(CE_CONT, "\tNumSockets=%d\n", config->NumSockets); 2478 cmn_err(CE_CONT, "\tNumWindows=%d\n", config->NumWindows); 2479 } 2480 #endif 2481 config->ResourceFlags = 0; 2482 switch (pcic->pc_intr_mode) { 2483 case PCIC_INTR_MODE_PCI_1: 2484 config->ResourceFlags |= RES_OWN_IRQ | RES_IRQ_NEXUS | 2485 RES_IRQ_SHAREABLE; 2486 break; 2487 } 2488 return (SUCCESS); 2489 } 2490 2491 /* 2492 * pcic_callback() 2493 * The PCMCIA nexus calls us via this function 2494 * in order to set the callback function we are 2495 * to call the nexus with 2496 */ 2497 /*ARGSUSED*/ 2498 static int 2499 pcic_callback(dev_info_t *dip, int (*handler)(), int arg) 2500 { 2501 anp_t *anp = ddi_get_driver_private(dip); 2502 pcicdev_t *pcic = anp->an_private; 2503 2504 if (handler != NULL) { 2505 pcic->pc_callback = handler; 2506 pcic->pc_cb_arg = arg; 2507 pcic->pc_flags |= PCF_CALLBACK; 2508 } else { 2509 pcic->pc_callback = NULL; 2510 pcic->pc_cb_arg = 0; 2511 pcic->pc_flags &= ~PCF_CALLBACK; 2512 } 2513 /* 2514 * we're now registered with the nexus 2515 * it is acceptable to do callbacks at this point. 2516 * don't call back from here though since it could block 2517 */ 2518 return (PC_SUCCESS); 2519 } 2520 2521 /* 2522 * pcic_calc_speed (pcicdev_t *pcic, uint32_t speed) 2523 * calculate the speed bits from the specified memory speed 2524 * there may be more to do here 2525 */ 2526 2527 static int 2528 pcic_calc_speed(pcicdev_t *pcic, uint32_t speed) 2529 { 2530 uint32_t wspeed = 1; /* assume 1 wait state when unknown */ 2531 uint32_t bspeed = PCIC_ISA_DEF_SYSCLK; 2532 2533 switch (pcic->pc_type) { 2534 case PCIC_I82365SL: 2535 case PCIC_VADEM: 2536 case PCIC_VADEM_VG469: 2537 default: 2538 /* Intel chip wants it in waitstates */ 2539 wspeed = mhztons(PCIC_ISA_DEF_SYSCLK) * 3; 2540 if (speed <= wspeed) 2541 wspeed = 0; 2542 else if (speed <= (wspeed += mhztons(bspeed))) 2543 wspeed = 1; 2544 else if (speed <= (wspeed += mhztons(bspeed))) 2545 wspeed = 2; 2546 else 2547 wspeed = 3; 2548 wspeed <<= 6; /* put in right bit positions */ 2549 break; 2550 2551 case PCIC_INTEL_i82092: 2552 wspeed = SYSMEM_82092_80NS; 2553 if (speed > 80) 2554 wspeed = SYSMEM_82092_100NS; 2555 if (speed > 100) 2556 wspeed = SYSMEM_82092_150NS; 2557 if (speed > 150) 2558 wspeed = SYSMEM_82092_200NS; 2559 if (speed > 200) 2560 wspeed = SYSMEM_82092_250NS; 2561 if (speed > 250) 2562 wspeed = SYSMEM_82092_600NS; 2563 wspeed <<= 5; /* put in right bit positions */ 2564 break; 2565 2566 } /* switch */ 2567 2568 return (wspeed); 2569 } 2570 2571 /* 2572 * These values are taken from the PC Card Standard Electrical Specification. 2573 * Generally the larger value is taken if 2 are possible. 2574 */ 2575 static struct pcic_card_times { 2576 uint16_t cycle; /* Speed as found in the atribute space of he card. */ 2577 uint16_t setup; /* Corresponding address setup time. */ 2578 uint16_t width; /* Corresponding width, OE or WE. */ 2579 uint16_t hold; /* Corresponding data or address hold time. */ 2580 } pcic_card_times[] = { 2581 2582 /* 2583 * Note: The rounded up times for 250, 200 & 150 have been increased 2584 * due to problems with the 3-Com ethernet cards (pcelx) on UBIIi. 2585 * See BugID 00663. 2586 */ 2587 2588 /* 2589 * Rounded up times Original times from 2590 * that add up to the the PCMCIA Spec. 2591 * cycle time. 2592 */ 2593 {600, 180, 370, 140}, /* 100, 300, 70 */ 2594 {400, 120, 300, 90}, /* Made this one up */ 2595 {250, 100, 190, 70}, /* 30, 150, 30 */ 2596 {200, 80, 170, 70}, /* 20, 120, 30 */ 2597 {150, 50, 110, 40}, /* 20, 80, 20 */ 2598 {100, 40, 80, 40}, /* 10, 60, 15 */ 2599 {0, 10, 60, 15} /* 10, 60, 15 */ 2600 }; 2601 2602 /* 2603 * pcic_set_cdtimers 2604 * This is specific to several Cirrus Logic chips 2605 */ 2606 static void 2607 pcic_set_cdtimers(pcicdev_t *pcic, int socket, uint32_t speed, int tset) 2608 { 2609 int cmd, set, rec, offset, clk_pulse; 2610 struct pcic_card_times *ctp; 2611 2612 if ((tset == IOMEM_CLTIMER_SET_1) || (tset == SYSMEM_CLTIMER_SET_1)) 2613 offset = 3; 2614 else 2615 offset = 0; 2616 2617 clk_pulse = mhztons(pcic->bus_speed); 2618 for (ctp = pcic_card_times; speed < ctp->cycle; ctp++); 2619 2620 /* 2621 * Add (clk_pulse/2) and an extra 1 to account for rounding errors. 2622 */ 2623 set = ((ctp->setup + 10 + 1 + (clk_pulse/2))/clk_pulse) - 1; 2624 if (set < 0) 2625 set = 0; 2626 2627 cmd = ((ctp->width + 10 + 1 + (clk_pulse/2))/clk_pulse) - 1; 2628 if (cmd < 0) 2629 cmd = 0; 2630 2631 rec = ((ctp->hold + 10 + 1 + (clk_pulse/2))/clk_pulse) - 2; 2632 if (rec < 0) 2633 rec = 0; 2634 2635 #if defined(PCIC_DEBUG) 2636 pcic_err(pcic->dip, 8, "pcic_set_cdtimers(%d, Timer Set %d)\n" 2637 "ct=%d, cp=%d, cmd=0x%x, setup=0x%x, rec=0x%x\n", 2638 (unsigned)speed, offset == 3 ? 1 : 0, 2639 ctp->cycle, clk_pulse, cmd, set, rec); 2640 #endif 2641 2642 pcic_putb(pcic, socket, PCIC_TIME_COMMAND_0 + offset, cmd); 2643 pcic_putb(pcic, socket, PCIC_TIME_SETUP_0 + offset, set); 2644 pcic_putb(pcic, socket, PCIC_TIME_RECOVER_0 + offset, rec); 2645 } 2646 2647 /* 2648 * pcic_set_window 2649 * essentially the same as the Socket Services specification 2650 * We use socket and not adapter since they are identifiable 2651 * but the rest is the same 2652 * 2653 * dip pcic driver's device information 2654 * window parameters for the request 2655 */ 2656 static int 2657 pcic_set_window(dev_info_t *dip, set_window_t *window) 2658 { 2659 anp_t *anp = ddi_get_driver_private(dip); 2660 pcicdev_t *pcic = anp->an_private; 2661 int select; 2662 int socket, pages, which, ret; 2663 pcic_socket_t *sockp = &pcic->pc_sockets[window->socket]; 2664 ra_return_t res; 2665 ndi_ra_request_t req; 2666 uint32_t base = window->base; 2667 2668 #if defined(PCIC_DEBUG) 2669 if (pcic_debug) { 2670 cmn_err(CE_CONT, "pcic_set_window: entered\n"); 2671 cmn_err(CE_CONT, 2672 "\twindow=%d, socket=%d, WindowSize=%d, speed=%d\n", 2673 window->window, window->socket, window->WindowSize, 2674 window->speed); 2675 cmn_err(CE_CONT, 2676 "\tbase=%x, state=%x\n", (unsigned)window->base, 2677 (unsigned)window->state); 2678 } 2679 #endif 2680 2681 /* 2682 * do some basic sanity checking on what we support 2683 * we don't do paged mode 2684 */ 2685 if (window->state & WS_PAGED) { 2686 cmn_err(CE_WARN, "pcic_set_window: BAD_ATTRIBUTE\n"); 2687 return (BAD_ATTRIBUTE); 2688 } 2689 2690 /* 2691 * we don't care about previous mappings. 2692 * Card Services will deal with that so don't 2693 * even check 2694 */ 2695 2696 socket = window->socket; 2697 2698 if (!(window->state & WS_IO)) { 2699 int win, tmp; 2700 pcs_memwin_t *memp; 2701 #if defined(PCIC_DEBUG) 2702 if (pcic_debug) 2703 cmn_err(CE_CONT, "\twindow type is memory\n"); 2704 #endif 2705 /* this is memory window mapping */ 2706 win = window->window % PCIC_NUMWINSOCK; 2707 tmp = window->window / PCIC_NUMWINSOCK; 2708 2709 /* only windows 2-6 can do memory mapping */ 2710 if (tmp != window->socket || win < PCIC_IOWINDOWS) { 2711 cmn_err(CE_CONT, 2712 "\tattempt to map to non-mem window\n"); 2713 return (BAD_WINDOW); 2714 } 2715 2716 if (window->WindowSize == 0) 2717 window->WindowSize = MEM_MIN; 2718 else if ((window->WindowSize & (PCIC_PAGE-1)) != 0) { 2719 cmn_err(CE_WARN, "pcic_set_window: BAD_SIZE\n"); 2720 return (BAD_SIZE); 2721 } 2722 2723 mutex_enter(&pcic->pc_lock); /* protect the registers */ 2724 2725 memp = &sockp->pcs_windows[win].mem; 2726 memp->pcw_speed = window->speed; 2727 2728 win -= PCIC_IOWINDOWS; /* put in right range */ 2729 2730 if (window->WindowSize != memp->pcw_len) 2731 which = memp->pcw_len; 2732 else 2733 which = 0; 2734 2735 if (window->state & WS_ENABLED) { 2736 uint32_t wspeed; 2737 #if defined(PCIC_DEBUG) 2738 if (pcic_debug) { 2739 cmn_err(CE_CONT, 2740 "\tbase=%x, win=%d\n", (unsigned)base, 2741 win); 2742 if (which) 2743 cmn_err(CE_CONT, 2744 "\tneed to remap window\n"); 2745 } 2746 #endif 2747 2748 if (which && (memp->pcw_status & PCW_MAPPED)) { 2749 ddi_regs_map_free(&memp->pcw_handle); 2750 res.ra_addr_lo = memp->pcw_base; 2751 res.ra_len = memp->pcw_len; 2752 (void) pcmcia_free_mem(memp->res_dip, &res); 2753 memp->pcw_status &= ~(PCW_MAPPED|PCW_ENABLED); 2754 memp->pcw_hostmem = NULL; 2755 memp->pcw_base = NULL; 2756 memp->pcw_len = 0; 2757 } 2758 2759 which = window->WindowSize >> PAGE_SHIFT; 2760 2761 if (!(memp->pcw_status & PCW_MAPPED)) { 2762 ret = 0; 2763 2764 memp->pcw_base = base; 2765 bzero(&req, sizeof (req)); 2766 req.ra_len = which << PAGE_SHIFT; 2767 req.ra_addr = (uint64_t)memp->pcw_base; 2768 req.ra_boundbase = pcic->pc_base; 2769 req.ra_boundlen = pcic->pc_bound; 2770 req.ra_flags = (memp->pcw_base ? 2771 NDI_RA_ALLOC_SPECIFIED : 0) | 2772 NDI_RA_ALLOC_BOUNDED; 2773 req.ra_align_mask = 2774 (PAGESIZE - 1) | (PCIC_PAGE - 1); 2775 #if defined(PCIC_DEBUG) 2776 pcic_err(dip, 8, 2777 "\tlen 0x%"PRIx64 2778 "addr 0x%"PRIx64"bbase 0x%"PRIx64 2779 " blen 0x%"PRIx64" flags 0x%x" 2780 " algn 0x%"PRIx64"\n", 2781 req.ra_len, req.ra_addr, 2782 req.ra_boundbase, 2783 req.ra_boundlen, req.ra_flags, 2784 req.ra_align_mask); 2785 #endif 2786 2787 ret = pcmcia_alloc_mem(dip, &req, &res, 2788 &memp->res_dip); 2789 if (ret == DDI_FAILURE) { 2790 mutex_exit(&pcic->pc_lock); 2791 cmn_err(CE_WARN, 2792 "\tpcmcia_alloc_mem() failed\n"); 2793 return (BAD_SIZE); 2794 } 2795 memp->pcw_base = res.ra_addr_lo; 2796 base = memp->pcw_base; 2797 2798 #if defined(PCIC_DEBUG) 2799 if (pcic_debug) 2800 cmn_err(CE_CONT, 2801 "\tsetwindow: new base=%x\n", 2802 (unsigned)memp->pcw_base); 2803 #endif 2804 memp->pcw_len = window->WindowSize; 2805 2806 which = pcmcia_map_reg(pcic->dip, 2807 window->child, 2808 &res, 2809 (uint32_t)(window->state & 2810 0xffff) | 2811 (window->socket << 16), 2812 (caddr_t *)&memp->pcw_hostmem, 2813 &memp->pcw_handle, 2814 &window->attr, NULL); 2815 2816 if (which != DDI_SUCCESS) { 2817 2818 cmn_err(CE_WARN, "\tpcmcia_map_reg() " 2819 "failed\n"); 2820 2821 res.ra_addr_lo = memp->pcw_base; 2822 res.ra_len = memp->pcw_len; 2823 (void) pcmcia_free_mem(memp->res_dip, &res); 2824 2825 mutex_exit(&pcic->pc_lock); 2826 2827 return (BAD_WINDOW); 2828 } 2829 memp->pcw_status |= PCW_MAPPED; 2830 #if defined(PCIC_DEBUG) 2831 if (pcic_debug) 2832 cmn_err(CE_CONT, 2833 "\tmap=%x, hostmem=%p\n", 2834 which, 2835 (void *)memp->pcw_hostmem); 2836 #endif 2837 } else { 2838 base = memp->pcw_base; 2839 } 2840 2841 /* report the handle back to caller */ 2842 window->handle = memp->pcw_handle; 2843 2844 #if defined(PCIC_DEBUG) 2845 if (pcic_debug) { 2846 cmn_err(CE_CONT, 2847 "\twindow mapped to %x@%x len=%d\n", 2848 (unsigned)window->base, 2849 (unsigned)memp->pcw_base, 2850 memp->pcw_len); 2851 } 2852 #endif 2853 2854 /* find the register set offset */ 2855 select = win * PCIC_MEM_1_OFFSET; 2856 #if defined(PCIC_DEBUG) 2857 if (pcic_debug) 2858 cmn_err(CE_CONT, "\tselect=%x\n", select); 2859 #endif 2860 2861 /* 2862 * at this point, the register window indicator has 2863 * been converted to be an offset from the first 2864 * set of registers that are used for programming 2865 * the window mapping and the offset used to select 2866 * the correct set of registers to access the 2867 * specified socket. This allows basing everything 2868 * off the _0 window 2869 */ 2870 2871 /* map the physical page base address */ 2872 which = (window->state & WS_16BIT) ? SYSMEM_DATA_16 : 0; 2873 which |= (window->speed <= MEM_SPEED_MIN) ? 2874 SYSMEM_ZERO_WAIT : 0; 2875 2876 /* need to select register set */ 2877 select = PCIC_MEM_1_OFFSET * win; 2878 2879 pcic_putb(pcic, socket, 2880 PCIC_SYSMEM_0_STARTLOW + select, 2881 SYSMEM_LOW(base)); 2882 pcic_putb(pcic, socket, 2883 PCIC_SYSMEM_0_STARTHI + select, 2884 SYSMEM_HIGH(base) | which); 2885 2886 /* 2887 * Some adapters can decode window addresses greater 2888 * than 16-bits worth, so handle them here. 2889 */ 2890 switch (pcic->pc_type) { 2891 case PCIC_INTEL_i82092: 2892 pcic_putb(pcic, socket, 2893 PCIC_82092_CPAGE, 2894 SYSMEM_EXT(base)); 2895 break; 2896 case PCIC_CL_PD6729: 2897 case PCIC_CL_PD6730: 2898 clext_reg_write(pcic, socket, 2899 PCIC_CLEXT_MMAP0_UA + win, 2900 SYSMEM_EXT(base)); 2901 break; 2902 case PCIC_TI_PCI1130: 2903 /* 2904 * Note that the TI chip has one upper byte 2905 * per socket so all windows get bound to a 2906 * 16MB segment. This must be detected and 2907 * handled appropriately. We can detect that 2908 * it is done by seeing if the pc_base has 2909 * changed and changing when the register 2910 * is first set. This will force the bounds 2911 * to be correct. 2912 */ 2913 if (pcic->pc_bound == 0xffffffff) { 2914 pcic_putb(pcic, socket, 2915 PCIC_TI_WINDOW_PAGE_PCI, 2916 SYSMEM_EXT(base)); 2917 pcic->pc_base = SYSMEM_EXT(base) << 24; 2918 pcic->pc_bound = 0x1000000; 2919 } 2920 break; 2921 case PCIC_TI_PCI1031: 2922 case PCIC_TI_PCI1131: 2923 case PCIC_TI_PCI1250: 2924 case PCIC_TI_PCI1225: 2925 case PCIC_TI_PCI1221: 2926 case PCIC_SMC_34C90: 2927 case PCIC_CL_PD6832: 2928 case PCIC_RICOH_RL5C466: 2929 case PCIC_TI_PCI1410: 2930 case PCIC_ENE_1410: 2931 case PCIC_TI_PCI1510: 2932 case PCIC_TI_PCI1520: 2933 case PCIC_O2_OZ6912: 2934 case PCIC_TI_PCI1420: 2935 case PCIC_ENE_1420: 2936 case PCIC_TI_VENDOR: 2937 case PCIC_TOSHIBA_TOPIC100: 2938 case PCIC_TOSHIBA_TOPIC95: 2939 case PCIC_TOSHIBA_VENDOR: 2940 case PCIC_RICOH_VENDOR: 2941 case PCIC_O2MICRO_VENDOR: 2942 pcic_putb(pcic, socket, 2943 PCIC_YENTA_MEM_PAGE + win, 2944 SYSMEM_EXT(base)); 2945 break; 2946 default: 2947 cmn_err(CE_NOTE, "pcic_set_window: unknown " 2948 "cardbus vendor:0x%X\n", 2949 pcic->pc_type); 2950 pcic_putb(pcic, socket, 2951 PCIC_YENTA_MEM_PAGE + win, 2952 SYSMEM_EXT(base)); 2953 2954 break; 2955 } /* switch */ 2956 2957 /* 2958 * specify the length of the mapped range 2959 * we convert to pages (rounding up) so that 2960 * the hardware gets the right thing 2961 */ 2962 pages = (window->WindowSize+PCIC_PAGE-1)/PCIC_PAGE; 2963 2964 /* 2965 * Setup this window's timing. 2966 */ 2967 switch (pcic->pc_type) { 2968 case PCIC_CL_PD6729: 2969 case PCIC_CL_PD6730: 2970 case PCIC_CL_PD6710: 2971 case PCIC_CL_PD6722: 2972 wspeed = SYSMEM_CLTIMER_SET_0; 2973 pcic_set_cdtimers(pcic, socket, 2974 window->speed, 2975 wspeed); 2976 break; 2977 2978 case PCIC_INTEL_i82092: 2979 default: 2980 wspeed = pcic_calc_speed(pcic, window->speed); 2981 break; 2982 } /* switch */ 2983 2984 #if defined(PCIC_DEBUG) 2985 if (pcic_debug) 2986 cmn_err(CE_CONT, 2987 "\twindow %d speed bits = %x for " 2988 "%dns\n", 2989 win, (unsigned)wspeed, window->speed); 2990 #endif 2991 2992 pcic_putb(pcic, socket, PCIC_SYSMEM_0_STOPLOW + select, 2993 SYSMEM_LOW(base + 2994 (pages * PCIC_PAGE)-1)); 2995 2996 wspeed |= SYSMEM_HIGH(base + (pages * PCIC_PAGE)-1); 2997 pcic_putb(pcic, socket, PCIC_SYSMEM_0_STOPHI + select, 2998 wspeed); 2999 3000 /* 3001 * now map the card's memory pages - we start with page 3002 * 0 3003 * we also default to AM -- set page might change it 3004 */ 3005 base = memp->pcw_base; 3006 pcic_putb(pcic, socket, 3007 PCIC_CARDMEM_0_LOW + select, 3008 CARDMEM_LOW(0 - (uint32_t)base)); 3009 3010 pcic_putb(pcic, socket, 3011 PCIC_CARDMEM_0_HI + select, 3012 CARDMEM_HIGH(0 - (uint32_t)base) | 3013 CARDMEM_REG_ACTIVE); 3014 3015 /* 3016 * enable the window even though redundant 3017 * and SetPage may do it again. 3018 */ 3019 select = pcic_getb(pcic, socket, 3020 PCIC_MAPPING_ENABLE); 3021 select |= SYSMEM_WINDOW(win); 3022 pcic_putb(pcic, socket, PCIC_MAPPING_ENABLE, select); 3023 memp->pcw_offset = 0; 3024 memp->pcw_status |= PCW_ENABLED; 3025 } else { 3026 /* 3027 * not only do we unmap the memory, the 3028 * window has been turned off. 3029 */ 3030 if (which && memp->pcw_status & PCW_MAPPED) { 3031 ddi_regs_map_free(&memp->pcw_handle); 3032 res.ra_addr_lo = memp->pcw_base; 3033 res.ra_len = memp->pcw_len; 3034 (void) pcmcia_free_mem(memp->res_dip, &res); 3035 memp->pcw_hostmem = NULL; 3036 memp->pcw_status &= ~PCW_MAPPED; 3037 } 3038 3039 /* disable current mapping */ 3040 select = pcic_getb(pcic, socket, PCIC_MAPPING_ENABLE); 3041 select &= ~SYSMEM_WINDOW(win); 3042 pcic_putb(pcic, socket, PCIC_MAPPING_ENABLE, select); 3043 memp->pcw_status &= ~PCW_ENABLED; 3044 } 3045 memp->pcw_len = window->WindowSize; 3046 window->handle = memp->pcw_handle; 3047 #if defined(PCIC_DEBUG) 3048 if (pcic_debug) 3049 xxdmp_all_regs(pcic, window->socket, -1); 3050 #endif 3051 } else { 3052 /* 3053 * This is a request for an IO window 3054 */ 3055 int win, tmp; 3056 pcs_iowin_t *winp; 3057 /* I/O windows */ 3058 #if defined(PCIC_DEBUG) 3059 if (pcic_debug) 3060 cmn_err(CE_CONT, "\twindow type is I/O\n"); 3061 #endif 3062 3063 /* only windows 0 and 1 can do I/O */ 3064 win = window->window % PCIC_NUMWINSOCK; 3065 tmp = window->window / PCIC_NUMWINSOCK; 3066 3067 if (win >= PCIC_IOWINDOWS || tmp != window->socket) { 3068 cmn_err(CE_WARN, 3069 "\twindow is out of range (%d)\n", 3070 window->window); 3071 return (BAD_WINDOW); 3072 } 3073 3074 mutex_enter(&pcic->pc_lock); /* protect the registers */ 3075 3076 winp = &sockp->pcs_windows[win].io; 3077 winp->pcw_speed = window->speed; 3078 if (window->WindowSize != 1 && window->WindowSize & 1) { 3079 /* we don't want an odd-size window */ 3080 window->WindowSize++; 3081 } 3082 winp->pcw_len = window->WindowSize; 3083 3084 if (window->state & WS_ENABLED) { 3085 if (winp->pcw_status & PCW_MAPPED) { 3086 ddi_regs_map_free(&winp->pcw_handle); 3087 res.ra_addr_lo = winp->pcw_base; 3088 res.ra_len = winp->pcw_len; 3089 (void) pcmcia_free_io(winp->res_dip, &res); 3090 winp->pcw_status &= ~(PCW_MAPPED|PCW_ENABLED); 3091 } 3092 3093 /* 3094 * if the I/O address wasn't allocated, allocate 3095 * it now. If it was allocated, it better 3096 * be free to use. 3097 * The winp->pcw_offset value is set and used 3098 * later on if the particular adapter 3099 * that we're running on has the ability 3100 * to translate IO accesses to the card 3101 * (such as some adapters in the Cirrus 3102 * Logic family). 3103 */ 3104 winp->pcw_offset = 0; 3105 3106 /* 3107 * Setup the request parameters for the 3108 * requested base and length. If 3109 * we're on an adapter that has 3110 * IO window offset registers, then 3111 * we don't need a specific base 3112 * address, just a length, and then 3113 * we'll cause the correct IO address 3114 * to be generated on the socket by 3115 * setting up the IO window offset 3116 * registers. 3117 * For adapters that support this capability, we 3118 * always use the IO window offset registers, 3119 * even if the passed base/length would be in 3120 * range. 3121 */ 3122 base = window->base; 3123 bzero(&req, sizeof (req)); 3124 req.ra_len = window->WindowSize; 3125 3126 req.ra_addr = (uint64_t) 3127 ((pcic->pc_flags & PCF_IO_REMAP) ? 0 : base); 3128 req.ra_flags = (req.ra_addr) ? 3129 NDI_RA_ALLOC_SPECIFIED : 0; 3130 3131 req.ra_flags |= NDI_RA_ALIGN_SIZE; 3132 /* need to rethink this */ 3133 req.ra_boundbase = pcic->pc_iobase; 3134 req.ra_boundlen = pcic->pc_iobound; 3135 req.ra_flags |= NDI_RA_ALLOC_BOUNDED; 3136 3137 #if defined(PCIC_DEBUG) 3138 pcic_err(dip, 8, 3139 "\tlen 0x%"PRIx64" addr 0x%"PRIx64 3140 "bbase 0x%"PRIx64 3141 "blen 0x%"PRIx64" flags 0x%x algn 0x%" 3142 PRIx64"\n", 3143 req.ra_len, (uint64_t)req.ra_addr, 3144 req.ra_boundbase, 3145 req.ra_boundlen, req.ra_flags, 3146 req.ra_align_mask); 3147 #endif 3148 3149 /* 3150 * Try to allocate the space. If we fail this, 3151 * return the appropriate error depending 3152 * on whether the caller specified a 3153 * specific base address or not. 3154 */ 3155 if (pcmcia_alloc_io(dip, &req, &res, 3156 &winp->res_dip) == DDI_FAILURE) { 3157 winp->pcw_status &= ~PCW_ENABLED; 3158 mutex_exit(&pcic->pc_lock); 3159 cmn_err(CE_WARN, "Failed to alloc I/O:\n" 3160 "\tlen 0x%" PRIx64 " addr 0x%" PRIx64 3161 "bbase 0x%" PRIx64 3162 "blen 0x%" PRIx64 "flags 0x%x" 3163 "algn 0x%" PRIx64 "\n", 3164 req.ra_len, req.ra_addr, 3165 req.ra_boundbase, 3166 req.ra_boundlen, req.ra_flags, 3167 req.ra_align_mask); 3168 3169 return (base?BAD_BASE:BAD_SIZE); 3170 } /* pcmcia_alloc_io */ 3171 3172 /* 3173 * Don't change the original base. Either we use 3174 * the offset registers below (PCF_IO_REMAP is set) 3175 * or it was allocated correctly anyway. 3176 */ 3177 winp->pcw_base = res.ra_addr_lo; 3178 3179 #if defined(PCIC_DEBUG) 3180 pcic_err(dip, 8, 3181 "\tsetwindow: new base=%x orig base 0x%x\n", 3182 (unsigned)winp->pcw_base, base); 3183 #endif 3184 3185 if ((which = pcmcia_map_reg(pcic->dip, 3186 window->child, 3187 &res, 3188 (uint32_t)(window->state & 3189 0xffff) | 3190 (window->socket << 16), 3191 (caddr_t *)&winp->pcw_hostmem, 3192 &winp->pcw_handle, 3193 &window->attr, 3194 base)) != DDI_SUCCESS) { 3195 3196 cmn_err(CE_WARN, "pcmcia_map_reg()" 3197 "failed\n"); 3198 3199 res.ra_addr_lo = winp->pcw_base; 3200 res.ra_len = winp->pcw_len; 3201 (void) pcmcia_free_io(winp->res_dip, &res); 3202 3203 mutex_exit(&pcic->pc_lock); 3204 return (BAD_WINDOW); 3205 } 3206 3207 window->handle = winp->pcw_handle; 3208 winp->pcw_status |= PCW_MAPPED; 3209 3210 /* find the register set offset */ 3211 select = win * PCIC_IO_OFFSET; 3212 3213 #if defined(PCIC_DEBUG) 3214 if (pcic_debug) { 3215 cmn_err(CE_CONT, 3216 "\tenable: window=%d, select=%x, " 3217 "base=%x, handle=%p\n", 3218 win, select, 3219 (unsigned)window->base, 3220 (void *)window->handle); 3221 } 3222 #endif 3223 /* 3224 * at this point, the register window indicator has 3225 * been converted to be an offset from the first 3226 * set of registers that are used for programming 3227 * the window mapping and the offset used to select 3228 * the correct set of registers to access the 3229 * specified socket. This allows basing everything 3230 * off the _0 window 3231 */ 3232 3233 /* map the I/O base in */ 3234 pcic_putb(pcic, socket, 3235 PCIC_IO_ADDR_0_STARTLOW + select, 3236 LOW_BYTE((uint32_t)winp->pcw_base)); 3237 pcic_putb(pcic, socket, 3238 PCIC_IO_ADDR_0_STARTHI + select, 3239 HIGH_BYTE((uint32_t)winp->pcw_base)); 3240 3241 pcic_putb(pcic, socket, 3242 PCIC_IO_ADDR_0_STOPLOW + select, 3243 LOW_BYTE((uint32_t)winp->pcw_base + 3244 window->WindowSize - 1)); 3245 pcic_putb(pcic, socket, 3246 PCIC_IO_ADDR_0_STOPHI + select, 3247 HIGH_BYTE((uint32_t)winp->pcw_base + 3248 window->WindowSize - 1)); 3249 3250 /* 3251 * We've got the requested IO space, now see if we 3252 * need to adjust the IO window offset registers 3253 * so that the correct IO address is generated 3254 * at the socket. If this window doesn't have 3255 * this capability, then we're all done setting 3256 * up the IO resources. 3257 */ 3258 if (pcic->pc_flags & PCF_IO_REMAP) { 3259 3260 3261 /* 3262 * Note that only 16 bits are used to program 3263 * the registers but leave 32 bits on pcw_offset 3264 * so that we can generate the original base 3265 * in get_window() 3266 */ 3267 winp->pcw_offset = (base - winp->pcw_base); 3268 3269 pcic_putb(pcic, socket, 3270 PCIC_IO_OFFSET_LOW + 3271 (win * PCIC_IO_OFFSET_OFFSET), 3272 winp->pcw_offset & 0x0ff); 3273 pcic_putb(pcic, socket, 3274 PCIC_IO_OFFSET_HI + 3275 (win * PCIC_IO_OFFSET_OFFSET), 3276 (winp->pcw_offset >> 8) & 0x0ff); 3277 3278 } /* PCF_IO_REMAP */ 3279 3280 /* now get the other details (size, etc) right */ 3281 3282 /* 3283 * Set the data size control bits here. Most of the 3284 * adapters will ignore IOMEM_16BIT when 3285 * IOMEM_IOCS16 is set, except for the Intel 3286 * 82092, which only pays attention to the 3287 * IOMEM_16BIT bit. Sigh... Intel can't even 3288 * make a proper clone of their own chip. 3289 * The 82092 also apparently can't set the timing 3290 * of I/O windows. 3291 */ 3292 which = (window->state & WS_16BIT) ? 3293 (IOMEM_16BIT | IOMEM_IOCS16) : 0; 3294 3295 switch (pcic->pc_type) { 3296 case PCIC_CL_PD6729: 3297 case PCIC_CL_PD6730: 3298 case PCIC_CL_PD6710: 3299 case PCIC_CL_PD6722: 3300 case PCIC_CL_PD6832: 3301 /* 3302 * Select Timer Set 1 - this will take 3303 * effect when the PCIC_IO_CONTROL 3304 * register is written to later on; 3305 * the call to pcic_set_cdtimers 3306 * just sets up the timer itself. 3307 */ 3308 which |= IOMEM_CLTIMER_SET_1; 3309 pcic_set_cdtimers(pcic, socket, 3310 window->speed, 3311 IOMEM_CLTIMER_SET_1); 3312 which |= IOMEM_IOCS16; 3313 break; 3314 case PCIC_TI_PCI1031: 3315 3316 if (window->state & WS_16BIT) 3317 which |= IOMEM_WAIT16; 3318 3319 break; 3320 case PCIC_TI_PCI1130: 3321 3322 if (window->state & WS_16BIT) 3323 which |= IOMEM_WAIT16; 3324 3325 break; 3326 case PCIC_INTEL_i82092: 3327 break; 3328 default: 3329 if (window->speed > 3330 mhztons(pcic->bus_speed) * 3) 3331 which |= IOMEM_WAIT16; 3332 #ifdef notdef 3333 if (window->speed < 3334 mhztons(pcic->bus_speed) * 6) 3335 which |= IOMEM_ZERO_WAIT; 3336 #endif 3337 break; 3338 } /* switch (pc_type) */ 3339 3340 /* 3341 * Setup the data width and timing 3342 */ 3343 select = pcic_getb(pcic, socket, PCIC_IO_CONTROL); 3344 select &= ~(PCIC_IO_WIN_MASK << (win * 4)); 3345 select |= IOMEM_SETWIN(win, which); 3346 pcic_putb(pcic, socket, PCIC_IO_CONTROL, select); 3347 3348 /* 3349 * Enable the IO window 3350 */ 3351 select = pcic_getb(pcic, socket, PCIC_MAPPING_ENABLE); 3352 pcic_putb(pcic, socket, PCIC_MAPPING_ENABLE, 3353 select | IOMEM_WINDOW(win)); 3354 3355 winp->pcw_status |= PCW_ENABLED; 3356 3357 #if defined(PCIC_DEBUG) 3358 if (pcic_debug) { 3359 cmn_err(CE_CONT, 3360 "\twhich = %x, select = %x (%x)\n", 3361 which, select, 3362 IOMEM_SETWIN(win, which)); 3363 xxdmp_all_regs(pcic, window->socket * 0x40, 24); 3364 } 3365 #endif 3366 } else { 3367 /* 3368 * not only do we unmap the IO space, the 3369 * window has been turned off. 3370 */ 3371 if (winp->pcw_status & PCW_MAPPED) { 3372 ddi_regs_map_free(&winp->pcw_handle); 3373 res.ra_addr_lo = winp->pcw_base; 3374 res.ra_len = winp->pcw_len; 3375 (void) pcmcia_free_io(winp->res_dip, &res); 3376 winp->pcw_status &= ~PCW_MAPPED; 3377 } 3378 3379 /* disable current mapping */ 3380 select = pcic_getb(pcic, socket, 3381 PCIC_MAPPING_ENABLE); 3382 pcic_putb(pcic, socket, PCIC_MAPPING_ENABLE, 3383 select &= ~IOMEM_WINDOW(win)); 3384 winp->pcw_status &= ~PCW_ENABLED; 3385 3386 winp->pcw_base = 0; 3387 winp->pcw_len = 0; 3388 winp->pcw_offset = 0; 3389 window->base = 0; 3390 /* now make sure we don't accidentally re-enable */ 3391 /* find the register set offset */ 3392 select = win * PCIC_IO_OFFSET; 3393 pcic_putb(pcic, socket, 3394 PCIC_IO_ADDR_0_STARTLOW + select, 0); 3395 pcic_putb(pcic, socket, 3396 PCIC_IO_ADDR_0_STARTHI + select, 0); 3397 pcic_putb(pcic, socket, 3398 PCIC_IO_ADDR_0_STOPLOW + select, 0); 3399 pcic_putb(pcic, socket, 3400 PCIC_IO_ADDR_0_STOPHI + select, 0); 3401 } 3402 } 3403 mutex_exit(&pcic->pc_lock); 3404 3405 return (SUCCESS); 3406 } 3407 3408 /* 3409 * pcic_card_state() 3410 * compute the instantaneous Card State information 3411 */ 3412 static int 3413 pcic_card_state(pcicdev_t *pcic, pcic_socket_t *sockp) 3414 { 3415 int value, result; 3416 #if defined(PCIC_DEBUG) 3417 int orig_value; 3418 #endif 3419 3420 mutex_enter(&pcic->pc_lock); /* protect the registers */ 3421 3422 value = pcic_getb(pcic, sockp->pcs_socket, PCIC_INTERFACE_STATUS); 3423 3424 #if defined(PCIC_DEBUG) 3425 orig_value = value; 3426 if (pcic_debug >= 8) 3427 cmn_err(CE_CONT, "pcic_card_state(%p) if status = %b for %d\n", 3428 (void *)sockp, 3429 value, 3430 "\020\1BVD1\2BVD2\3CD1\4CD2\5WP\6RDY\7PWR\10~GPI", 3431 sockp->pcs_socket); 3432 #endif 3433 /* 3434 * Lie to socket services if we are not ready. 3435 * This is when we are starting up or during debounce timeouts 3436 * or if the card is a cardbus card. 3437 */ 3438 if (!(sockp->pcs_flags & (PCS_STARTING|PCS_CARD_ISCARDBUS)) && 3439 !sockp->pcs_debounce_id && 3440 (value & PCIC_ISTAT_CD_MASK) == PCIC_CD_PRESENT_OK) { 3441 result = SBM_CD; 3442 3443 if (value & PCIC_WRITE_PROTECT || !(value & PCIC_POWER_ON)) 3444 result |= SBM_WP; 3445 if (value & PCIC_POWER_ON) { 3446 if (value & PCIC_READY) 3447 result |= SBM_RDYBSY; 3448 value = (~value) & (PCIC_BVD1 | PCIC_BVD2); 3449 if (value & PCIC_BVD1) 3450 result |= SBM_BVD1; 3451 if (value & PCIC_BVD2) 3452 result |= SBM_BVD2; 3453 } 3454 } else 3455 result = 0; 3456 3457 mutex_exit(&pcic->pc_lock); 3458 3459 #if defined(PCIC_DEBUG) 3460 pcic_err(pcic->dip, 8, 3461 "pcic_card_state(%p) if status = %b for %d (rval=0x%x)\n", 3462 (void *) sockp, orig_value, 3463 "\020\1BVD1\2BVD2\3CD1\4CD2\5WP\6RDY\7PWR\10~GPI", 3464 sockp->pcs_socket, result); 3465 #endif 3466 3467 return (result); 3468 } 3469 3470 /* 3471 * pcic_set_page() 3472 * SocketServices SetPage function 3473 * set the page of PC Card memory that should be in the mapped 3474 * window 3475 */ 3476 /*ARGSUSED*/ 3477 static int 3478 pcic_set_page(dev_info_t *dip, set_page_t *page) 3479 { 3480 anp_t *anp = ddi_get_driver_private(dip); 3481 pcicdev_t *pcic = anp->an_private; 3482 int select; 3483 int which, socket, window; 3484 uint32_t base; 3485 pcs_memwin_t *memp; 3486 3487 /* get real socket/window numbers */ 3488 window = page->window % PCIC_NUMWINSOCK; 3489 socket = page->window / PCIC_NUMWINSOCK; 3490 3491 #if defined(PCIC_DEBUG) 3492 if (pcic_debug) { 3493 cmn_err(CE_CONT, 3494 "pcic_set_page: window=%d, socket=%d, page=%d\n", 3495 window, socket, page->page); 3496 } 3497 #endif 3498 /* only windows 2-6 work on memory */ 3499 if (window < PCIC_IOWINDOWS) 3500 return (BAD_WINDOW); 3501 3502 /* only one page supported (but any size) */ 3503 if (page->page != 0) 3504 return (BAD_PAGE); 3505 3506 mutex_enter(&pcic->pc_lock); /* protect the registers */ 3507 3508 memp = &pcic->pc_sockets[socket].pcs_windows[window].mem; 3509 window -= PCIC_IOWINDOWS; 3510 3511 #if defined(PCIC_DEBUG) 3512 if (pcic_debug) 3513 cmn_err(CE_CONT, "\tpcw_base=%x, pcw_hostmem=%p, pcw_len=%x\n", 3514 (uint32_t)memp->pcw_base, 3515 (void *)memp->pcw_hostmem, memp->pcw_len); 3516 #endif 3517 3518 /* window must be enabled */ 3519 if (!(memp->pcw_status & PCW_ENABLED)) 3520 return (BAD_ATTRIBUTE); 3521 3522 /* find the register set offset */ 3523 select = window * PCIC_MEM_1_OFFSET; 3524 #if defined(PCIC_DEBUG) 3525 if (pcic_debug) 3526 cmn_err(CE_CONT, "\tselect=%x\n", select); 3527 #endif 3528 3529 /* 3530 * now map the card's memory pages - we start with page 0 3531 */ 3532 3533 which = 0; /* assume simple case */ 3534 if (page->state & PS_ATTRIBUTE) { 3535 which |= CARDMEM_REG_ACTIVE; 3536 memp->pcw_status |= PCW_ATTRIBUTE; 3537 } else { 3538 memp->pcw_status &= ~PCW_ATTRIBUTE; 3539 } 3540 3541 /* 3542 * if caller says Write Protect, enforce it. 3543 */ 3544 if (page->state & PS_WP) { 3545 which |= CARDMEM_WRITE_PROTECT; 3546 memp->pcw_status |= PCW_WP; 3547 } else { 3548 memp->pcw_status &= ~PCW_WP; 3549 } 3550 #if defined(PCIC_DEBUG) 3551 if (pcic_debug) { 3552 cmn_err(CE_CONT, "\tmemory type = %s\n", 3553 (which & CARDMEM_REG_ACTIVE) ? "attribute" : "common"); 3554 if (which & CARDMEM_WRITE_PROTECT) 3555 cmn_err(CE_CONT, "\twrite protect\n"); 3556 cmn_err(CE_CONT, "\tpage offset=%x pcw_base=%x (%x)\n", 3557 (unsigned)page->offset, 3558 (unsigned)memp->pcw_base, 3559 (int)page->offset - (int)memp->pcw_base & 0xffffff); 3560 } 3561 #endif 3562 /* address computation based on 64MB range and not larger */ 3563 base = (uint32_t)memp->pcw_base & 0x3ffffff; 3564 pcic_putb(pcic, socket, PCIC_CARDMEM_0_LOW + select, 3565 CARDMEM_LOW((int)page->offset - (int)base)); 3566 (void) pcic_getb(pcic, socket, PCIC_CARDMEM_0_LOW + select); 3567 pcic_putb(pcic, socket, PCIC_CARDMEM_0_HI + select, 3568 CARDMEM_HIGH((int)page->offset - base) | which); 3569 (void) pcic_getb(pcic, socket, PCIC_CARDMEM_0_HI + select); 3570 3571 /* 3572 * while not really necessary, this just makes sure 3573 * nothing turned the window off behind our backs 3574 */ 3575 which = pcic_getb(pcic, socket, PCIC_MAPPING_ENABLE); 3576 which |= SYSMEM_WINDOW(window); 3577 pcic_putb(pcic, socket, PCIC_MAPPING_ENABLE, which); 3578 (void) pcic_getb(pcic, socket, PCIC_MAPPING_ENABLE); 3579 3580 memp->pcw_offset = (off_t)page->offset; 3581 3582 #if defined(PCIC_DEBUG) 3583 if (pcic_debug) { 3584 cmn_err(CE_CONT, "\tbase=%p, *base=%x\n", 3585 (void *)memp->pcw_hostmem, 3586 (uint32_t)*memp->pcw_hostmem); 3587 3588 xxdmp_all_regs(pcic, socket, -1); 3589 3590 cmn_err(CE_CONT, "\tbase=%p, *base=%x\n", 3591 (void *)memp->pcw_hostmem, 3592 (uint32_t)*memp->pcw_hostmem); 3593 } 3594 #endif 3595 3596 if (which & PCW_ATTRIBUTE) 3597 pcic_mswait(pcic, socket, 2); 3598 3599 mutex_exit(&pcic->pc_lock); 3600 3601 return (SUCCESS); 3602 } 3603 3604 /* 3605 * pcic_set_vcc_level() 3606 * 3607 * set voltage based on adapter information 3608 * 3609 * this routine implements a limited solution for support of 3.3v cards. 3610 * the general solution, which would fully support the pcmcia spec 3611 * as far as allowing client drivers to request which voltage levels 3612 * to be set, requires more framework support and driver changes - ess 3613 */ 3614 static int 3615 pcic_set_vcc_level(pcicdev_t *pcic, set_socket_t *socket) 3616 { 3617 uint32_t socket_present_state; 3618 3619 #if defined(PCIC_DEBUG) 3620 if (pcic_debug) { 3621 cmn_err(CE_CONT, 3622 "pcic_set_vcc_level(pcic=%p, VccLevel=%d)\n", 3623 (void *)pcic, socket->VccLevel); 3624 } 3625 #endif 3626 3627 /* 3628 * check VccLevel 3629 * if this is zero, power is being turned off 3630 * if it is non-zero, power is being turned on. 3631 */ 3632 if (socket->VccLevel == 0) { 3633 return (0); 3634 } 3635 3636 /* 3637 * range checking for sanity's sake 3638 */ 3639 if (socket->VccLevel >= pcic->pc_numpower) { 3640 return (BAD_VCC); 3641 } 3642 3643 switch (pcic->pc_io_type) { 3644 /* 3645 * Yenta-compliant adapters have vcc info in the extended registers 3646 * Other adapters can be added as needed, but the 'default' case 3647 * has been left as it was previously so as not to break existing 3648 * adapters. 3649 */ 3650 case PCIC_IO_TYPE_YENTA: 3651 /* 3652 * Here we ignore the VccLevel passed in and read the 3653 * card type from the adapter socket present state register 3654 */ 3655 socket_present_state = 3656 ddi_get32(pcic->handle, (uint32_t *)(pcic->ioaddr + 3657 PCIC_PRESENT_STATE_REG)); 3658 #if defined(PCIC_DEBUG) 3659 if (pcic_debug) { 3660 cmn_err(CE_CONT, 3661 "socket present state = 0x%x\n", 3662 socket_present_state); 3663 } 3664 #endif 3665 switch (socket_present_state & PCIC_VCC_MASK) { 3666 case PCIC_VCC_3VCARD: 3667 /* fall through */ 3668 case PCIC_VCC_3VCARD|PCIC_VCC_5VCARD: 3669 socket->VccLevel = PCIC_VCC_3VLEVEL; 3670 return 3671 (POWER_3VCARD_ENABLE|POWER_OUTPUT_ENABLE); 3672 case PCIC_VCC_5VCARD: 3673 socket->VccLevel = PCIC_VCC_5VLEVEL; 3674 return 3675 (POWER_CARD_ENABLE|POWER_OUTPUT_ENABLE); 3676 default: 3677 /* 3678 * if no card is present, this can be the 3679 * case of a client making a SetSocket call 3680 * after card removal. In this case we return 3681 * the current power level 3682 */ 3683 return ((unsigned)ddi_get8(pcic->handle, 3684 pcic->ioaddr + CB_R2_OFFSET + 3685 PCIC_POWER_CONTROL)); 3686 } 3687 3688 default: 3689 3690 switch (socket->VccLevel) { 3691 case PCIC_VCC_3VLEVEL: 3692 return (BAD_VCC); 3693 case PCIC_VCC_5VLEVEL: 3694 /* enable Vcc */ 3695 return (POWER_CARD_ENABLE|POWER_OUTPUT_ENABLE); 3696 default: 3697 return (BAD_VCC); 3698 } 3699 } 3700 } 3701 3702 3703 /* 3704 * pcic_set_socket() 3705 * Socket Services SetSocket call 3706 * sets basic socket configuration 3707 */ 3708 static int 3709 pcic_set_socket(dev_info_t *dip, set_socket_t *socket) 3710 { 3711 anp_t *anp = ddi_get_driver_private(dip); 3712 pcicdev_t *pcic = anp->an_private; 3713 pcic_socket_t *sockp = &pcic->pc_sockets[socket->socket]; 3714 int irq, interrupt, mirq; 3715 int powerlevel = 0; 3716 int ind, value, orig_pwrctl; 3717 3718 #if defined(PCIC_DEBUG) 3719 if (pcic_debug) { 3720 cmn_err(CE_CONT, 3721 "pcic_set_socket(dip=%p, socket=%d)" 3722 " Vcc=%d Vpp1=%d Vpp2=%d\n", (void *)dip, 3723 socket->socket, socket->VccLevel, socket->Vpp1Level, 3724 socket->Vpp2Level); 3725 } 3726 #endif 3727 /* 3728 * check VccLevel, etc. before setting mutex 3729 * if this is zero, power is being turned off 3730 * if it is non-zero, power is being turned on. 3731 * the default case is to assume Vcc only. 3732 */ 3733 3734 /* this appears to be very implementation specific */ 3735 3736 if (socket->Vpp1Level != socket->Vpp2Level) 3737 return (BAD_VPP); 3738 3739 if (socket->VccLevel == 0 || !(sockp->pcs_flags & PCS_CARD_PRESENT)) { 3740 powerlevel = 0; 3741 sockp->pcs_vcc = 0; 3742 sockp->pcs_vpp1 = 0; 3743 sockp->pcs_vpp2 = 0; 3744 } else { 3745 #if defined(PCIC_DEBUG) 3746 pcic_err(dip, 9, "\tVcc=%d Vpp1Level=%d, Vpp2Level=%d\n", 3747 socket->VccLevel, socket->Vpp1Level, socket->Vpp2Level); 3748 #endif 3749 /* valid Vcc power level? */ 3750 if (socket->VccLevel >= pcic->pc_numpower) 3751 return (BAD_VCC); 3752 3753 switch (pcic_power[socket->VccLevel].PowerLevel) { 3754 case 33: /* 3.3V */ 3755 case 60: /* for bad CIS in Option GPRS card */ 3756 if (!(pcic->pc_flags & PCF_33VCAP)) { 3757 cmn_err(CE_WARN, 3758 "%s%d: Bad Request for 3.3V " 3759 "(Controller incapable)\n", 3760 ddi_get_name(pcic->dip), 3761 ddi_get_instance(pcic->dip)); 3762 return (BAD_VCC); 3763 } 3764 /* FALLTHROUGH */ 3765 case 50: /* 5V */ 3766 if ((pcic->pc_io_type == PCIC_IO_TYPE_YENTA) && 3767 pcic_getcb(pcic, CB_PRESENT_STATE) & 3768 CB_PS_33VCARD) { 3769 /* 3770 * This is actually a 3.3V card. 3771 * Solaris Card Services 3772 * doesn't understand 3.3V 3773 * so we cheat and change 3774 * the setting to the one appropriate to 3.3V. 3775 * Note that this is the entry number 3776 * in the pcic_power[] array. 3777 */ 3778 sockp->pcs_vcc = PCIC_VCC_3VLEVEL; 3779 } else 3780 sockp->pcs_vcc = socket->VccLevel; 3781 break; 3782 default: 3783 return (BAD_VCC); 3784 } 3785 3786 /* enable Vcc */ 3787 powerlevel = POWER_CARD_ENABLE; 3788 3789 #if defined(PCIC_DEBUG) 3790 if (pcic_debug) { 3791 cmn_err(CE_CONT, "\tVcc=%d powerlevel=%x\n", 3792 socket->VccLevel, powerlevel); 3793 } 3794 #endif 3795 ind = 0; /* default index to 0 power */ 3796 if ((int)socket->Vpp1Level >= 0 && 3797 socket->Vpp1Level < pcic->pc_numpower) { 3798 if (!(pcic_power[socket->Vpp1Level].ValidSignals 3799 & VPP1)) { 3800 return (BAD_VPP); 3801 } 3802 ind = pcic_power[socket->Vpp1Level].PowerLevel/10; 3803 powerlevel |= pcic_vpp_levels[ind]; 3804 sockp->pcs_vpp1 = socket->Vpp1Level; 3805 } 3806 if ((int)socket->Vpp2Level >= 0 && 3807 socket->Vpp2Level < pcic->pc_numpower) { 3808 if (!(pcic_power[socket->Vpp2Level].ValidSignals 3809 & VPP2)) { 3810 return (BAD_VPP); 3811 } 3812 ind = pcic_power[socket->Vpp2Level].PowerLevel/10; 3813 powerlevel |= (pcic_vpp_levels[ind] << 2); 3814 sockp->pcs_vpp2 = socket->Vpp2Level; 3815 } 3816 3817 if (pcic->pc_flags & PCF_VPPX) { 3818 /* 3819 * this adapter doesn't allow separate Vpp1/Vpp2 3820 * if one is turned on, both are turned on and only 3821 * the Vpp1 bits should be set 3822 */ 3823 if (sockp->pcs_vpp2 != sockp->pcs_vpp1) { 3824 /* must be the same if one not zero */ 3825 if (sockp->pcs_vpp1 != 0 && 3826 sockp->pcs_vpp2 != 0) { 3827 cmn_err(CE_WARN, 3828 "%s%d: Bad Power Request " 3829 "(Vpp1/2 not the same)\n", 3830 ddi_get_name(pcic->dip), 3831 ddi_get_instance(pcic->dip)); 3832 return (BAD_VPP); 3833 } 3834 } 3835 powerlevel &= ~(3<<2); 3836 } 3837 3838 #if defined(PCIC_DEBUG) 3839 if (pcic_debug) { 3840 cmn_err(CE_CONT, "\tpowerlevel=%x, ind=%x\n", 3841 powerlevel, ind); 3842 } 3843 #endif 3844 } 3845 mutex_enter(&pcic->pc_lock); /* protect the registers */ 3846 3847 /* turn socket->IREQRouting off while programming */ 3848 interrupt = pcic_getb(pcic, socket->socket, PCIC_INTERRUPT); 3849 interrupt &= ~PCIC_INTR_MASK; 3850 if (pcic->pc_flags & PCF_USE_SMI) 3851 interrupt |= PCIC_INTR_ENABLE; 3852 pcic_putb(pcic, socket->socket, PCIC_INTERRUPT, interrupt); 3853 3854 switch (pcic->pc_type) { 3855 case PCIC_INTEL_i82092: 3856 pcic_82092_smiirq_ctl(pcic, socket->socket, PCIC_82092_CTL_IRQ, 3857 PCIC_82092_INT_DISABLE); 3858 break; 3859 default: 3860 break; 3861 } /* switch */ 3862 3863 /* the SCIntMask specifies events to detect */ 3864 mirq = pcic_getb(pcic, socket->socket, PCIC_MANAGEMENT_INT); 3865 3866 #if defined(PCIC_DEBUG) 3867 if (pcic_debug) 3868 cmn_err(CE_CONT, 3869 "\tSCIntMask=%x, interrupt=%x, mirq=%x\n", 3870 socket->SCIntMask, interrupt, mirq); 3871 #endif 3872 mirq &= ~(PCIC_BD_DETECT|PCIC_BW_DETECT|PCIC_RD_DETECT); 3873 pcic_putb(pcic, socket->socket, PCIC_MANAGEMENT_INT, 3874 mirq & ~PCIC_CHANGE_MASK); 3875 3876 /* save the mask we want to use */ 3877 sockp->pcs_intmask = socket->SCIntMask; 3878 3879 /* 3880 * Until there is a card present it's not worth enabling 3881 * any interrupts except "Card detect". This is done 3882 * elsewhere in the driver so don't change things if 3883 * there is no card! 3884 */ 3885 if (sockp->pcs_flags & PCS_CARD_PRESENT) { 3886 3887 /* now update the hardware to reflect events desired */ 3888 if (sockp->pcs_intmask & SBM_BVD1 || socket->IFType == IF_IO) 3889 mirq |= PCIC_BD_DETECT; 3890 3891 if (sockp->pcs_intmask & SBM_BVD2) 3892 mirq |= PCIC_BW_DETECT; 3893 3894 if (sockp->pcs_intmask & SBM_RDYBSY) 3895 mirq |= PCIC_RD_DETECT; 3896 3897 if (sockp->pcs_intmask & SBM_CD) 3898 mirq |= PCIC_CD_DETECT; 3899 } 3900 3901 if (sockp->pcs_flags & PCS_READY) { 3902 /* 3903 * card just came ready. 3904 * make sure enough time elapses 3905 * before touching it. 3906 */ 3907 sockp->pcs_flags &= ~PCS_READY; 3908 pcic_mswait(pcic, socket->socket, 10); 3909 } 3910 3911 #if defined(PCIC_DEBUG) 3912 if (pcic_debug) { 3913 cmn_err(CE_CONT, "\tstatus change set to %x\n", mirq); 3914 } 3915 #endif 3916 3917 switch (pcic->pc_type) { 3918 case PCIC_I82365SL: 3919 case PCIC_VADEM: 3920 case PCIC_VADEM_VG469: 3921 /* 3922 * The Intel version has different options. This is a 3923 * special case of GPI which might be used for eject 3924 */ 3925 3926 irq = pcic_getb(pcic, socket->socket, PCIC_CARD_DETECT); 3927 if (sockp->pcs_intmask & (SBM_EJECT|SBM_INSERT) && 3928 pcic->pc_flags & PCF_GPI_EJECT) { 3929 irq |= PCIC_GPI_ENABLE; 3930 } else { 3931 irq &= ~PCIC_GPI_ENABLE; 3932 } 3933 pcic_putb(pcic, socket->socket, PCIC_CARD_DETECT, irq); 3934 break; 3935 case PCIC_CL_PD6710: 3936 case PCIC_CL_PD6722: 3937 if (socket->IFType == IF_IO) { 3938 pcic_putb(pcic, socket->socket, PCIC_MISC_CTL_2, 0x0); 3939 value = pcic_getb(pcic, socket->socket, 3940 PCIC_MISC_CTL_1); 3941 if (pcic->pc_flags & PCF_AUDIO) 3942 value |= PCIC_MC_SPEAKER_ENB; 3943 pcic_putb(pcic, socket->socket, PCIC_MISC_CTL_1, 3944 value); 3945 } else { 3946 value = pcic_getb(pcic, socket->socket, 3947 PCIC_MISC_CTL_1); 3948 value &= ~PCIC_MC_SPEAKER_ENB; 3949 pcic_putb(pcic, socket->socket, PCIC_MISC_CTL_1, 3950 value); 3951 } 3952 break; 3953 case PCIC_CL_PD6729: 3954 case PCIC_CL_PD6730: 3955 case PCIC_CL_PD6832: 3956 value = pcic_getb(pcic, socket->socket, PCIC_MISC_CTL_1); 3957 if ((socket->IFType == IF_IO) && (pcic->pc_flags & PCF_AUDIO)) { 3958 value |= PCIC_MC_SPEAKER_ENB; 3959 } else { 3960 value &= ~PCIC_MC_SPEAKER_ENB; 3961 } 3962 3963 if (pcic_power[sockp->pcs_vcc].PowerLevel == 33) 3964 value |= PCIC_MC_3VCC; 3965 else 3966 value &= ~PCIC_MC_3VCC; 3967 3968 pcic_putb(pcic, socket->socket, PCIC_MISC_CTL_1, value); 3969 break; 3970 3971 case PCIC_O2_OZ6912: 3972 value = pcic_getcb(pcic, CB_MISCCTRL); 3973 if ((socket->IFType == IF_IO) && (pcic->pc_flags & PCF_AUDIO)) 3974 value |= (1<<25); 3975 else 3976 value &= ~(1<<25); 3977 pcic_putcb(pcic, CB_MISCCTRL, value); 3978 if (pcic_power[sockp->pcs_vcc].PowerLevel == 33) 3979 powerlevel |= 0x08; 3980 break; 3981 3982 case PCIC_TI_PCI1250: 3983 case PCIC_TI_PCI1221: 3984 case PCIC_TI_PCI1225: 3985 case PCIC_TI_PCI1410: 3986 case PCIC_ENE_1410: 3987 case PCIC_TI_PCI1510: 3988 case PCIC_TI_PCI1520: 3989 case PCIC_TI_PCI1420: 3990 case PCIC_ENE_1420: 3991 value = ddi_get8(pcic->cfg_handle, 3992 pcic->cfgaddr + PCIC_CRDCTL_REG); 3993 if ((socket->IFType == IF_IO) && (pcic->pc_flags & PCF_AUDIO)) { 3994 value |= PCIC_CRDCTL_SPKR_ENBL; 3995 } else { 3996 value &= ~PCIC_CRDCTL_SPKR_ENBL; 3997 } 3998 ddi_put8(pcic->cfg_handle, 3999 pcic->cfgaddr + PCIC_CRDCTL_REG, value); 4000 if (pcic_power[sockp->pcs_vcc].PowerLevel == 33) 4001 powerlevel |= 0x08; 4002 break; 4003 } 4004 4005 /* 4006 * ctlind processing -- we can ignore this 4007 * there aren't any outputs on the chip for this and 4008 * the GUI will display what it thinks is correct 4009 */ 4010 4011 /* 4012 * If outputs are enabled and the power is going off 4013 * turn off outputs first. 4014 */ 4015 4016 /* power setup -- if necessary */ 4017 orig_pwrctl = pcic_getb(pcic, socket->socket, PCIC_POWER_CONTROL); 4018 if ((orig_pwrctl & POWER_OUTPUT_ENABLE) && sockp->pcs_vcc == 0) { 4019 orig_pwrctl &= ~POWER_OUTPUT_ENABLE; 4020 pcic_putb(pcic, socket->socket, 4021 PCIC_POWER_CONTROL, orig_pwrctl); 4022 (void) pcic_getb(pcic, socket->socket, PCIC_POWER_CONTROL); 4023 } 4024 4025 if (pcic->pc_flags & PCF_CBPWRCTL) { 4026 value = pcic_cbus_powerctl(pcic, socket->socket); 4027 powerlevel = 0; 4028 } else 4029 value = pcic_exca_powerctl(pcic, socket->socket, powerlevel); 4030 4031 if (value != SUCCESS) { 4032 mutex_exit(&pcic->pc_lock); 4033 return (value); 4034 } 4035 4036 /* 4037 * If outputs were disabled and the power is going on 4038 * turn on outputs afterwards. 4039 */ 4040 if (!(orig_pwrctl & POWER_OUTPUT_ENABLE) && sockp->pcs_vcc != 0) { 4041 orig_pwrctl = pcic_getb(pcic, socket->socket, 4042 PCIC_POWER_CONTROL); 4043 orig_pwrctl |= POWER_OUTPUT_ENABLE; 4044 pcic_putb(pcic, socket->socket, 4045 PCIC_POWER_CONTROL, orig_pwrctl); 4046 (void) pcic_getb(pcic, socket->socket, PCIC_POWER_CONTROL); 4047 } 4048 4049 /* 4050 * Once we have done the power stuff can re-enable management 4051 * interrupts. 4052 */ 4053 pcic_putb(pcic, socket->socket, PCIC_MANAGEMENT_INT, mirq); 4054 4055 #if defined(PCIC_DEBUG) 4056 pcic_err(dip, 8, "\tmanagement int set to %x pwrctl to 0x%x " 4057 "cbctl 0x%x\n", 4058 mirq, pcic_getb(pcic, socket->socket, PCIC_POWER_CONTROL), 4059 pcic_getcb(pcic, CB_CONTROL)); 4060 #endif 4061 4062 /* irq processing */ 4063 if (socket->IFType == IF_IO) { 4064 /* IRQ only for I/O */ 4065 irq = socket->IREQRouting & PCIC_INTR_MASK; 4066 value = pcic_getb(pcic, socket->socket, PCIC_INTERRUPT); 4067 value &= ~PCIC_INTR_MASK; 4068 4069 /* to enable I/O operation */ 4070 value |= PCIC_IO_CARD | PCIC_RESET; 4071 sockp->pcs_flags |= PCS_CARD_IO; 4072 if (irq != sockp->pcs_irq) { 4073 if (sockp->pcs_irq != 0) 4074 cmn_err(CE_CONT, 4075 "SetSocket: IRQ mismatch %x != %x!\n", 4076 irq, sockp->pcs_irq); 4077 else 4078 sockp->pcs_irq = irq; 4079 } 4080 irq = sockp->pcs_irq; 4081 4082 pcic_putb(pcic, socket->socket, PCIC_INTERRUPT, value); 4083 if (socket->IREQRouting & IRQ_ENABLE) { 4084 pcic_enable_io_intr(pcic, socket->socket, irq); 4085 sockp->pcs_flags |= PCS_IRQ_ENABLED; 4086 } else { 4087 pcic_disable_io_intr(pcic, socket->socket); 4088 sockp->pcs_flags &= ~PCS_IRQ_ENABLED; 4089 } 4090 #if defined(PCIC_DEBUG) 4091 if (pcic_debug) { 4092 cmn_err(CE_CONT, 4093 "\tsocket type is I/O and irq %x is %s\n", irq, 4094 (socket->IREQRouting & IRQ_ENABLE) ? 4095 "enabled" : "not enabled"); 4096 xxdmp_all_regs(pcic, socket->socket, 20); 4097 } 4098 #endif 4099 } else { 4100 /* make sure I/O mode is off */ 4101 4102 sockp->pcs_irq = 0; 4103 4104 value = pcic_getb(pcic, socket->socket, PCIC_INTERRUPT); 4105 value &= ~PCIC_IO_CARD; 4106 pcic_putb(pcic, socket->socket, PCIC_INTERRUPT, value); 4107 pcic_disable_io_intr(pcic, socket->socket); 4108 sockp->pcs_flags &= ~(PCS_CARD_IO|PCS_IRQ_ENABLED); 4109 } 4110 4111 sockp->pcs_state &= ~socket->State; 4112 4113 mutex_exit(&pcic->pc_lock); 4114 return (SUCCESS); 4115 } 4116 4117 /* 4118 * pcic_inquire_socket() 4119 * SocketServices InquireSocket function 4120 * returns basic characteristics of the socket 4121 */ 4122 /*ARGSUSED*/ 4123 static int 4124 pcic_inquire_socket(dev_info_t *dip, inquire_socket_t *socket) 4125 { 4126 anp_t *anp = ddi_get_driver_private(dip); 4127 pcicdev_t *pcic = anp->an_private; 4128 int value; 4129 4130 socket->SCIntCaps = PCIC_DEFAULT_INT_CAPS; 4131 socket->SCRptCaps = PCIC_DEFAULT_RPT_CAPS; 4132 socket->CtlIndCaps = PCIC_DEFAULT_CTL_CAPS; 4133 value = pcic->pc_sockets[socket->socket].pcs_flags; 4134 socket->SocketCaps = (value & PCS_SOCKET_IO) ? IF_IO : IF_MEMORY; 4135 socket->ActiveHigh = 0; 4136 /* these are the usable IRQs */ 4137 socket->ActiveLow = 0xfff0; 4138 return (SUCCESS); 4139 } 4140 4141 /* 4142 * pcic_inquire_window() 4143 * SocketServices InquireWindow function 4144 * returns detailed characteristics of the window 4145 * this is where windows get tied to sockets 4146 */ 4147 /*ARGSUSED*/ 4148 static int 4149 pcic_inquire_window(dev_info_t *dip, inquire_window_t *window) 4150 { 4151 int type, socket; 4152 4153 type = window->window % PCIC_NUMWINSOCK; 4154 socket = window->window / PCIC_NUMWINSOCK; 4155 4156 #if defined(PCIC_DEBUG) 4157 if (pcic_debug >= 8) 4158 cmn_err(CE_CONT, 4159 "pcic_inquire_window: window = %d/%d socket=%d\n", 4160 window->window, type, socket); 4161 #endif 4162 if (type < PCIC_IOWINDOWS) { 4163 window->WndCaps = WC_IO|WC_WAIT; 4164 type = IF_IO; 4165 } else { 4166 window->WndCaps = WC_COMMON|WC_ATTRIBUTE|WC_WAIT; 4167 type = IF_MEMORY; 4168 } 4169 4170 /* initialize the socket map - one socket per window */ 4171 PR_ZERO(window->Sockets); 4172 PR_SET(window->Sockets, socket); 4173 4174 if (type == IF_IO) { 4175 iowin_char_t *io; 4176 io = &window->iowin_char; 4177 io->IOWndCaps = WC_BASE|WC_SIZE|WC_WENABLE|WC_8BIT| 4178 WC_16BIT; 4179 io->FirstByte = (baseaddr_t)IOMEM_FIRST; 4180 io->LastByte = (baseaddr_t)IOMEM_LAST; 4181 io->MinSize = IOMEM_MIN; 4182 io->MaxSize = IOMEM_MAX; 4183 io->ReqGran = IOMEM_GRAN; 4184 io->AddrLines = IOMEM_DECODE; 4185 io->EISASlot = 0; 4186 } else { 4187 mem_win_char_t *mem; 4188 mem = &window->mem_win_char; 4189 mem->MemWndCaps = WC_BASE|WC_SIZE|WC_WENABLE|WC_8BIT| 4190 WC_16BIT|WC_WP; 4191 4192 mem->FirstByte = (baseaddr_t)MEM_FIRST; 4193 mem->LastByte = (baseaddr_t)MEM_LAST; 4194 4195 mem->MinSize = MEM_MIN; 4196 mem->MaxSize = MEM_MAX; 4197 mem->ReqGran = PCIC_PAGE; 4198 mem->ReqBase = 0; 4199 mem->ReqOffset = PCIC_PAGE; 4200 mem->Slowest = MEM_SPEED_MAX; 4201 mem->Fastest = MEM_SPEED_MIN; 4202 } 4203 return (SUCCESS); 4204 } 4205 4206 /* 4207 * pcic_get_adapter() 4208 * SocketServices GetAdapter function 4209 * this is nearly a no-op. 4210 */ 4211 /*ARGSUSED*/ 4212 static int 4213 pcic_get_adapter(dev_info_t *dip, get_adapter_t *adapt) 4214 { 4215 anp_t *anp = ddi_get_driver_private(dip); 4216 pcicdev_t *pcic = anp->an_private; 4217 4218 if (pcic->pc_flags & PCF_INTRENAB) 4219 adapt->SCRouting = IRQ_ENABLE; 4220 adapt->state = 0; 4221 return (SUCCESS); 4222 } 4223 4224 /* 4225 * pcic_get_page() 4226 * SocketServices GetPage function 4227 * returns info about the window 4228 */ 4229 /*ARGSUSED*/ 4230 static int 4231 pcic_get_page(dev_info_t *dip, get_page_t *page) 4232 { 4233 anp_t *anp = ddi_get_driver_private(dip); 4234 pcicdev_t *pcic = anp->an_private; 4235 int socket, window; 4236 pcs_memwin_t *winp; 4237 4238 socket = page->window / PCIC_NUMWINSOCK; 4239 window = page->window % PCIC_NUMWINSOCK; 4240 4241 /* I/O windows are the first two */ 4242 if (window < PCIC_IOWINDOWS || socket >= pcic->pc_numsockets) { 4243 return (BAD_WINDOW); 4244 } 4245 4246 winp = &pcic->pc_sockets[socket].pcs_windows[window].mem; 4247 4248 if (page->page != 0) 4249 return (BAD_PAGE); 4250 4251 page->state = 0; 4252 if (winp->pcw_status & PCW_ENABLED) 4253 page->state |= PS_ENABLED; 4254 if (winp->pcw_status & PCW_ATTRIBUTE) 4255 page->state |= PS_ATTRIBUTE; 4256 if (winp->pcw_status & PCW_WP) 4257 page->state |= PS_WP; 4258 4259 page->offset = (off_t)winp->pcw_offset; 4260 4261 return (SUCCESS); 4262 } 4263 4264 /* 4265 * pcic_get_socket() 4266 * SocketServices GetSocket 4267 * returns information about the current socket setting 4268 */ 4269 /*ARGSUSED*/ 4270 static int 4271 pcic_get_socket(dev_info_t *dip, get_socket_t *socket) 4272 { 4273 anp_t *anp = ddi_get_driver_private(dip); 4274 pcicdev_t *pcic = anp->an_private; 4275 int socknum, irq_enabled; 4276 pcic_socket_t *sockp; 4277 4278 socknum = socket->socket; 4279 sockp = &pcic->pc_sockets[socknum]; 4280 4281 socket->SCIntMask = sockp->pcs_intmask; 4282 sockp->pcs_state = pcic_card_state(pcic, sockp); 4283 4284 socket->state = sockp->pcs_state; 4285 if (socket->state & SBM_CD) { 4286 socket->VccLevel = sockp->pcs_vcc; 4287 socket->Vpp1Level = sockp->pcs_vpp1; 4288 socket->Vpp2Level = sockp->pcs_vpp2; 4289 irq_enabled = (sockp->pcs_flags & PCS_IRQ_ENABLED) ? 4290 IRQ_ENABLE : 0; 4291 socket->IRQRouting = sockp->pcs_irq | irq_enabled; 4292 socket->IFType = (sockp->pcs_flags & PCS_CARD_IO) ? 4293 IF_IO : IF_MEMORY; 4294 } else { 4295 socket->VccLevel = 0; 4296 socket->Vpp1Level = 0; 4297 socket->Vpp2Level = 0; 4298 socket->IRQRouting = 0; 4299 socket->IFType = IF_MEMORY; 4300 } 4301 socket->CtlInd = 0; /* no indicators */ 4302 4303 return (SUCCESS); 4304 } 4305 4306 /* 4307 * pcic_get_status() 4308 * SocketServices GetStatus 4309 * returns status information about the PC Card in 4310 * the selected socket 4311 */ 4312 /*ARGSUSED*/ 4313 static int 4314 pcic_get_status(dev_info_t *dip, get_ss_status_t *status) 4315 { 4316 anp_t *anp = ddi_get_driver_private(dip); 4317 pcicdev_t *pcic = anp->an_private; 4318 int socknum, irq_enabled; 4319 pcic_socket_t *sockp; 4320 4321 socknum = status->socket; 4322 sockp = &pcic->pc_sockets[socknum]; 4323 4324 status->CardState = pcic_card_state(pcic, sockp); 4325 status->SocketState = sockp->pcs_state; 4326 status->CtlInd = 0; /* no indicators */ 4327 4328 if (sockp->pcs_flags & PCS_CARD_PRESENT) 4329 status->SocketState |= SBM_CD; 4330 if (status->CardState & SBM_CD) { 4331 irq_enabled = (sockp->pcs_flags & PCS_CARD_ENABLED) ? 4332 IRQ_ENABLE : 0; 4333 status->IRQRouting = sockp->pcs_irq | irq_enabled; 4334 status->IFType = (sockp->pcs_flags & PCS_CARD_IO) ? 4335 IF_IO : IF_MEMORY; 4336 } else { 4337 status->IRQRouting = 0; 4338 status->IFType = IF_MEMORY; 4339 } 4340 4341 #if defined(PCIC_DEBUG) 4342 if (pcic_debug >= 8) 4343 cmn_err(CE_CONT, "pcic_get_status: socket=%d, CardState=%x," 4344 "SocketState=%x\n", 4345 socknum, status->CardState, status->SocketState); 4346 #endif 4347 switch (pcic->pc_type) { 4348 uint32_t present_state; 4349 case PCIC_TI_PCI1410: 4350 case PCIC_TI_PCI1520: 4351 case PCIC_TI_PCI1420: 4352 case PCIC_ENE_1420: 4353 case PCIC_TOSHIBA_TOPIC100: 4354 case PCIC_TOSHIBA_TOPIC95: 4355 case PCIC_TOSHIBA_VENDOR: 4356 case PCIC_O2MICRO_VENDOR: 4357 case PCIC_TI_VENDOR: 4358 case PCIC_RICOH_VENDOR: 4359 present_state = pcic_getcb(pcic, CB_PRESENT_STATE); 4360 if (present_state & PCIC_CB_CARD) 4361 status->IFType = IF_CARDBUS; 4362 #if defined(PCIC_DEBUG) 4363 if (pcic_debug >= 8) 4364 cmn_err(CE_CONT, "pcic_get_status: present_state=0x%x\n", 4365 present_state); 4366 #endif 4367 break; 4368 default: 4369 break; 4370 } 4371 4372 return (SUCCESS); 4373 } 4374 4375 /* 4376 * pcic_get_window() 4377 * SocketServices GetWindow function 4378 * returns state information about the specified window 4379 */ 4380 /*ARGSUSED*/ 4381 static int 4382 pcic_get_window(dev_info_t *dip, get_window_t *window) 4383 { 4384 anp_t *anp = ddi_get_driver_private(dip); 4385 pcicdev_t *pcic = anp->an_private; 4386 int socket, win; 4387 pcic_socket_t *sockp; 4388 pcs_memwin_t *winp; 4389 4390 socket = window->window / PCIC_NUMWINSOCK; 4391 win = window->window % PCIC_NUMWINSOCK; 4392 #if defined(PCIC_DEBUG) 4393 if (pcic_debug) { 4394 cmn_err(CE_CONT, "pcic_get_window(socket=%d, window=%d)\n", 4395 socket, win); 4396 } 4397 #endif 4398 4399 if (socket > pcic->pc_numsockets) 4400 return (BAD_WINDOW); 4401 4402 sockp = &pcic->pc_sockets[socket]; 4403 winp = &sockp->pcs_windows[win].mem; 4404 4405 window->socket = socket; 4406 window->size = winp->pcw_len; 4407 window->speed = winp->pcw_speed; 4408 window->handle = (ddi_acc_handle_t)winp->pcw_handle; 4409 window->base = (uint32_t)winp->pcw_base + winp->pcw_offset; 4410 4411 if (win >= PCIC_IOWINDOWS) { 4412 window->state = 0; 4413 } else { 4414 window->state = WS_IO; 4415 } 4416 if (winp->pcw_status & PCW_ENABLED) 4417 window->state |= WS_ENABLED; 4418 4419 if (winp->pcw_status & PCS_CARD_16BIT) 4420 window->state |= WS_16BIT; 4421 #if defined(PCIC_DEBUG) 4422 if (pcic_debug) 4423 cmn_err(CE_CONT, "\tsize=%d, speed=%d, base=%p, state=%x\n", 4424 window->size, (unsigned)window->speed, 4425 (void *)window->handle, window->state); 4426 #endif 4427 4428 return (SUCCESS); 4429 } 4430 4431 /* 4432 * pcic_ll_reset 4433 * low level reset 4434 * separated out so it can be called when already locked 4435 * 4436 * There are two variables that control the RESET timing: 4437 * pcic_prereset_time - time in mS before asserting RESET 4438 * pcic_reset_time - time in mS to assert RESET 4439 * 4440 */ 4441 int pcic_prereset_time = 1; 4442 int pcic_reset_time = 10; 4443 int pcic_postreset_time = 20; 4444 int pcic_vpp_is_vcc_during_reset = 0; 4445 4446 static int 4447 pcic_ll_reset(pcicdev_t *pcic, int socket) 4448 { 4449 int windowbits, iobits; 4450 uint32_t pwr; 4451 4452 /* save windows that were on */ 4453 windowbits = pcic_getb(pcic, socket, PCIC_MAPPING_ENABLE); 4454 if (pcic_reset_time == 0) 4455 return (windowbits); 4456 /* turn all windows off */ 4457 pcic_putb(pcic, socket, PCIC_MAPPING_ENABLE, 0); 4458 4459 #if defined(PCIC_DEBUG) 4460 pcic_err(pcic->dip, 6, 4461 "pcic_ll_reset(socket %d) powerlevel=%x cbctl 0x%x cbps 0x%x\n", 4462 socket, pcic_getb(pcic, socket, PCIC_POWER_CONTROL), 4463 pcic_getcb(pcic, CB_CONTROL), 4464 pcic_getcb(pcic, CB_PRESENT_STATE)); 4465 #endif 4466 4467 if (pcic_vpp_is_vcc_during_reset) { 4468 4469 /* 4470 * Set VPP to VCC for the duration of the reset - for aironet 4471 * card. 4472 */ 4473 if (pcic->pc_flags & PCF_CBPWRCTL) { 4474 pwr = pcic_getcb(pcic, CB_CONTROL); 4475 pcic_putcb(pcic, CB_CONTROL, (pwr&~CB_C_VPPMASK)|CB_C_VPPVCC); 4476 (void) pcic_getcb(pcic, CB_CONTROL); 4477 } else { 4478 pwr = pcic_getb(pcic, socket, PCIC_POWER_CONTROL); 4479 pcic_putb(pcic, socket, PCIC_POWER_CONTROL, 4480 pwr | 1); 4481 (void) pcic_getb(pcic, socket, PCIC_POWER_CONTROL); 4482 } 4483 } 4484 4485 if (pcic_prereset_time > 0) { 4486 pcic_err(pcic->dip, 8, "pcic_ll_reset pre_wait %d mS\n", 4487 pcic_prereset_time); 4488 pcic_mswait(pcic, socket, pcic_prereset_time); 4489 } 4490 4491 /* turn interrupts off and start a reset */ 4492 pcic_err(pcic->dip, 8, 4493 "pcic_ll_reset turn interrupts off and start a reset\n"); 4494 iobits = pcic_getb(pcic, socket, PCIC_INTERRUPT); 4495 iobits &= ~(PCIC_INTR_MASK | PCIC_RESET); 4496 pcic_putb(pcic, socket, PCIC_INTERRUPT, iobits); 4497 (void) pcic_getb(pcic, socket, PCIC_INTERRUPT); 4498 4499 switch (pcic->pc_type) { 4500 case PCIC_INTEL_i82092: 4501 pcic_82092_smiirq_ctl(pcic, socket, PCIC_82092_CTL_IRQ, 4502 PCIC_82092_INT_DISABLE); 4503 break; 4504 default: 4505 break; 4506 } /* switch */ 4507 4508 pcic->pc_sockets[socket].pcs_state = 0; 4509 4510 if (pcic_reset_time > 0) { 4511 pcic_err(pcic->dip, 8, "pcic_ll_reset reset_wait %d mS\n", 4512 pcic_reset_time); 4513 pcic_mswait(pcic, socket, pcic_reset_time); 4514 } 4515 4516 pcic_err(pcic->dip, 8, "pcic_ll_reset take it out of reset now\n"); 4517 4518 /* take it out of RESET now */ 4519 pcic_putb(pcic, socket, PCIC_INTERRUPT, PCIC_RESET | iobits); 4520 (void) pcic_getb(pcic, socket, PCIC_INTERRUPT); 4521 4522 /* 4523 * can't access the card for 20ms, but we really don't 4524 * want to sit around that long. The pcic is still usable. 4525 * memory accesses must wait for RDY to come up. 4526 */ 4527 if (pcic_postreset_time > 0) { 4528 pcic_err(pcic->dip, 8, "pcic_ll_reset post_wait %d mS\n", 4529 pcic_postreset_time); 4530 pcic_mswait(pcic, socket, pcic_postreset_time); 4531 } 4532 4533 if (pcic_vpp_is_vcc_during_reset > 1) { 4534 4535 /* 4536 * Return VPP power to whatever it was before. 4537 */ 4538 if (pcic->pc_flags & PCF_CBPWRCTL) { 4539 pcic_putcb(pcic, CB_CONTROL, pwr); 4540 (void) pcic_getcb(pcic, CB_CONTROL); 4541 } else { 4542 pcic_putb(pcic, socket, PCIC_POWER_CONTROL, pwr); 4543 (void) pcic_getb(pcic, socket, PCIC_POWER_CONTROL); 4544 } 4545 } 4546 4547 pcic_err(pcic->dip, 7, "pcic_ll_reset returning 0x%x\n", windowbits); 4548 4549 return (windowbits); 4550 } 4551 4552 /* 4553 * pcic_reset_socket() 4554 * SocketServices ResetSocket function 4555 * puts the PC Card in the socket into the RESET state 4556 * and then takes it out after the the cycle time 4557 * The socket is back to initial state when done 4558 */ 4559 static int 4560 pcic_reset_socket(dev_info_t *dip, int socket, int mode) 4561 { 4562 anp_t *anp = ddi_get_driver_private(dip); 4563 pcicdev_t *pcic = anp->an_private; 4564 int value; 4565 int i, mint; 4566 pcic_socket_t *sockp; 4567 4568 #if defined(PCIC_DEBUG) 4569 if (pcic_debug >= 8) 4570 cmn_err(CE_CONT, "pcic_reset_socket(%p, %d, %d/%s)\n", 4571 (void *)dip, socket, mode, 4572 mode == RESET_MODE_FULL ? "full" : "partial"); 4573 #endif 4574 4575 mutex_enter(&pcic->pc_lock); /* protect the registers */ 4576 4577 /* Turn off management interupts. */ 4578 mint = pcic_getb(pcic, socket, PCIC_MANAGEMENT_INT); 4579 pcic_putb(pcic, socket, PCIC_MANAGEMENT_INT, mint & ~PCIC_CHANGE_MASK); 4580 4581 sockp = &pcic->pc_sockets[socket]; 4582 4583 value = pcic_ll_reset(pcic, socket); 4584 if (mode == RESET_MODE_FULL) { 4585 /* disable and unmap all mapped windows */ 4586 for (i = 0; i < PCIC_NUMWINSOCK; i++) { 4587 if (i < PCIC_IOWINDOWS) { 4588 if (sockp->pcs_windows[i].io.pcw_status & 4589 PCW_MAPPED) { 4590 pcs_iowin_t *io; 4591 io = &sockp->pcs_windows[i].io; 4592 io->pcw_status &= ~PCW_ENABLED; 4593 } 4594 } else { 4595 if (sockp->pcs_windows[i].mem.pcw_status & 4596 PCW_MAPPED) { 4597 pcs_memwin_t *mem; 4598 mem = &sockp->pcs_windows[i].mem; 4599 mem->pcw_status &= ~PCW_ENABLED; 4600 } 4601 } 4602 } 4603 } else { 4604 /* turn windows back on */ 4605 pcic_putb(pcic, socket, PCIC_MAPPING_ENABLE, value); 4606 /* wait the rest of the time here */ 4607 pcic_mswait(pcic, socket, 10); 4608 } 4609 pcic_putb(pcic, socket, PCIC_MANAGEMENT_INT, mint); 4610 mutex_exit(&pcic->pc_lock); 4611 return (SUCCESS); 4612 } 4613 4614 /* 4615 * pcic_set_interrupt() 4616 * SocketServices SetInterrupt function 4617 */ 4618 static int 4619 pcic_set_interrupt(dev_info_t *dip, set_irq_handler_t *handler) 4620 { 4621 anp_t *anp = ddi_get_driver_private(dip); 4622 pcicdev_t *pcic = anp->an_private; 4623 int value = DDI_SUCCESS; 4624 inthandler_t *intr; 4625 4626 #if defined(PCIC_DEBUG) 4627 if (pcic_debug) { 4628 cmn_err(CE_CONT, 4629 "pcic_set_interrupt: entered pc_intr_mode=0x%x\n", 4630 pcic->pc_intr_mode); 4631 cmn_err(CE_CONT, 4632 "\t irq_top=%p handler=%p handler_id=%x\n", 4633 (void *)pcic->irq_top, (void *)handler->handler, 4634 handler->handler_id); 4635 } 4636 #endif 4637 4638 /* 4639 * If we're on a PCI bus, we route all IO IRQs through a single 4640 * PCI interrupt (typically INT A#) so we don't have to do 4641 * much other than add the caller to general interrupt handler 4642 * and set some state. 4643 */ 4644 4645 intr = kmem_zalloc(sizeof (inthandler_t), KM_NOSLEEP); 4646 if (intr == NULL) 4647 return (NO_RESOURCE); 4648 4649 switch (pcic->pc_intr_mode) { 4650 case PCIC_INTR_MODE_PCI_1: 4651 /* 4652 * We only allow above-lock-level IO IRQ handlers 4653 * in the PCI bus case. 4654 */ 4655 4656 mutex_enter(&pcic->intr_lock); 4657 4658 if (pcic->irq_top == NULL) { 4659 pcic->irq_top = intr; 4660 pcic->irq_current = pcic->irq_top; 4661 } else { 4662 while (pcic->irq_current->next != NULL) 4663 pcic->irq_current = pcic->irq_current->next; 4664 pcic->irq_current->next = intr; 4665 pcic->irq_current = pcic->irq_current->next; 4666 } 4667 4668 pcic->irq_current->intr = 4669 (ddi_intr_handler_t *)handler->handler; 4670 pcic->irq_current->handler_id = handler->handler_id; 4671 pcic->irq_current->arg1 = handler->arg1; 4672 pcic->irq_current->arg2 = handler->arg2; 4673 pcic->irq_current->socket = handler->socket; 4674 4675 mutex_exit(&pcic->intr_lock); 4676 4677 handler->iblk_cookie = &pcic->pc_pri; 4678 handler->idev_cookie = &pcic->pc_dcookie; 4679 break; 4680 4681 default: 4682 intr->intr = (ddi_intr_handler_t *)handler->handler; 4683 intr->handler_id = handler->handler_id; 4684 intr->arg1 = handler->arg1; 4685 intr->arg2 = handler->arg2; 4686 intr->socket = handler->socket; 4687 intr->irq = handler->irq; 4688 4689 /* 4690 * need to revisit this to see if interrupts can be 4691 * shared someday. Note that IRQ is set in the common 4692 * code. 4693 */ 4694 mutex_enter(&pcic->pc_lock); 4695 if (pcic->pc_handlers == NULL) { 4696 pcic->pc_handlers = intr; 4697 intr->next = intr->prev = intr; 4698 } else { 4699 insque(intr, pcic->pc_handlers); 4700 } 4701 mutex_exit(&pcic->pc_lock); 4702 4703 break; 4704 } 4705 4706 /* 4707 * need to fill in cookies in event of multiple high priority 4708 * interrupt handlers on same IRQ 4709 */ 4710 4711 #if defined(PCIC_DEBUG) 4712 if (pcic_debug) { 4713 cmn_err(CE_CONT, 4714 "pcic_set_interrupt: exit irq_top=%p value=%d\n", 4715 (void *)pcic->irq_top, value); 4716 } 4717 #endif 4718 4719 if (value == DDI_SUCCESS) { 4720 return (SUCCESS); 4721 } else { 4722 return (BAD_IRQ); 4723 } 4724 } 4725 4726 /* 4727 * pcic_clear_interrupt() 4728 * SocketServices ClearInterrupt function 4729 * 4730 * Interrupts for PCIC are complicated by the fact that we must 4731 * follow several different models for interrupts. 4732 * ISA: there is an interrupt per adapter and per socket and 4733 * they can't be shared. 4734 * PCI: some adapters have one PCI interrupt available while others 4735 * have up to 4. Solaris may or may not allow us to use more 4736 * than 1 so we essentially share them all at this point. 4737 * Hybrid: PCI bridge but interrupts wired to host interrupt controller. 4738 * This is like ISA but we have to fudge and create an intrspec 4739 * that PCI's parent understands and bypass the PCI nexus. 4740 * multifunction: this requires sharing the interrupts on a per-socket 4741 * basis. 4742 */ 4743 static int 4744 pcic_clear_interrupt(dev_info_t *dip, clear_irq_handler_t *handler) 4745 { 4746 anp_t *anp = ddi_get_driver_private(dip); 4747 pcicdev_t *pcic = anp->an_private; 4748 inthandler_t *intr, *prev, *current; 4749 int i; 4750 4751 /* 4752 * If we're on a PCI bus, we route all IO IRQs through a single 4753 * PCI interrupt (typically INT A#) so we don't have to do 4754 * much other than remove the caller from the general 4755 * interrupt handler callout list. 4756 */ 4757 4758 #if defined(PCIC_DEBUG) 4759 if (pcic_debug) { 4760 cmn_err(CE_CONT, 4761 "pcic_clear_interrupt: entered pc_intr_mode=0x%x\n", 4762 pcic->pc_intr_mode); 4763 cmn_err(CE_CONT, 4764 "\t irq_top=%p handler=%p handler_id=%x\n", 4765 (void *)pcic->irq_top, (void *)handler->handler, 4766 handler->handler_id); 4767 } 4768 #endif 4769 4770 switch (pcic->pc_intr_mode) { 4771 case PCIC_INTR_MODE_PCI_1: 4772 4773 mutex_enter(&pcic->intr_lock); 4774 if (pcic->irq_top == NULL) { 4775 mutex_exit(&pcic->intr_lock); 4776 return (BAD_IRQ); 4777 } 4778 4779 intr = NULL; 4780 pcic->irq_current = pcic->irq_top; 4781 4782 while ((pcic->irq_current != NULL) && 4783 (pcic->irq_current->handler_id != 4784 handler->handler_id)) { 4785 intr = pcic->irq_current; 4786 pcic->irq_current = pcic->irq_current->next; 4787 } 4788 4789 if (pcic->irq_current == NULL) { 4790 mutex_exit(&pcic->intr_lock); 4791 return (BAD_IRQ); 4792 } 4793 4794 if (intr != NULL) { 4795 intr->next = pcic->irq_current->next; 4796 } else { 4797 pcic->irq_top = pcic->irq_current->next; 4798 } 4799 4800 current = pcic->irq_current; 4801 pcic->irq_current = pcic->irq_top; 4802 mutex_exit(&pcic->intr_lock); 4803 kmem_free(current, sizeof (inthandler_t)); 4804 4805 break; 4806 4807 default: 4808 4809 mutex_enter(&pcic->pc_lock); 4810 intr = pcic_handlers; 4811 prev = (inthandler_t *)&pcic_handlers; 4812 4813 while (intr != NULL) { 4814 if (intr->handler_id == handler->handler_id) { 4815 i = intr->irq & PCIC_INTR_MASK; 4816 if (--pcic_irq_map[i].count == 0) { 4817 /* multi-handler form */ 4818 (void) ddi_intr_disable(pcic->pc_intr_htblp[i]); 4819 (void) ddi_intr_remove_handler( 4820 pcic->pc_intr_htblp[i]); 4821 (void) ddi_intr_free(pcic->pc_intr_htblp[i]); 4822 (void) pcmcia_return_intr(pcic->dip, i); 4823 #if defined(PCIC_DEBUG) 4824 if (pcic_debug) { 4825 cmn_err(CE_CONT, 4826 "removing interrupt %d at %s " 4827 "priority\n", i, "high"); 4828 cmn_err(CE_CONT, 4829 "ddi_remove_intr(%p, %x, %p)\n", 4830 (void *)dip, 4831 0, 4832 (void *)intr->iblk_cookie); 4833 } 4834 #endif 4835 } 4836 prev->next = intr->next; 4837 kmem_free(intr, sizeof (inthandler_t)); 4838 intr = prev->next; 4839 } else { 4840 prev = intr; 4841 intr = intr->next; 4842 } /* if (handler_id) */ 4843 } /* while */ 4844 4845 mutex_exit(&pcic->pc_lock); 4846 } 4847 4848 #if defined(PCIC_DEBUG) 4849 if (pcic_debug) { 4850 cmn_err(CE_CONT, 4851 "pcic_clear_interrupt: exit irq_top=%p\n", 4852 (void *)pcic->irq_top); 4853 } 4854 #endif 4855 4856 4857 return (SUCCESS); 4858 } 4859 4860 struct intel_regs { 4861 char *name; 4862 int off; 4863 char *fmt; 4864 } iregs[] = { 4865 {"ident ", 0}, 4866 {"if-status ", 1, "\020\1BVD1\2BVD2\3CD1\4CD2\5WP\6RDY\7PWR\10~GPI"}, 4867 {"power ", 2, "\020\1Vpp1c0\2Vpp1c1\3Vpp2c0\4Vpp2c1\5PE\6AUTO" 4868 "\7DRD\10OE"}, 4869 {"cardstatus", 4, "\020\1BD\2BW\3RC\4CD\5GPI\6R1\7R2\010R3"}, 4870 {"enable ", 6, "\020\1MW0\2MW1\3MW2\4MW3\5MW4\6MEM16\7IO0\10IO1"}, 4871 {"cd-gcr ", 0x16, "\020\1MDI16\2CRE\3GPIE\4GPIT\5CDR\6S/W"}, 4872 {"GCR ", 0x1e, "\020\1PD\2LEVEL\3WCSC\4PLS14"}, 4873 {"int-gcr ", 3, "\020\5INTR\6IO\7~RST\10RI"}, 4874 {"management", 5, "\020\1BDE\2BWE\3RE\4CDE"}, 4875 {"volt-sense", 0x1f, "\020\1A_VS1\2A_VS2\3B_VS1\4B_VS2"}, 4876 {"volt-sel ", 0x2f, "\020\5EXTCONF\6BUSSELECT\7MIXEDV\10ISAV"}, 4877 {"VG ext A ", 0x3c, "\20\3IVS\4CABLE\5CSTEP\6TEST\7RIO"}, 4878 {"io-ctrl ", 7, "\020\1DS0\2IOCS0\3ZWS0\4WS0\5DS1\6IOS1\7ZWS1\10WS1"}, 4879 {"io0-slow ", 8}, 4880 {"io0-shi ", 9}, 4881 {"io0-elow ", 0xa}, 4882 {"io0-ehi ", 0xb}, 4883 {"io1-slow ", 0xc}, 4884 {"io1-shi ", 0xd}, 4885 {"io1-elow ", 0xe}, 4886 {"io1-ehi ", 0xf}, 4887 {"mem0-slow ", 0x10}, 4888 {"mem0-shi ", 0x11, "\020\7ZW\10DS"}, 4889 {"mem0-elow ", 0x12}, 4890 {"mem0-ehi ", 0x13, "\020\7WS0\10WS1"}, 4891 {"card0-low ", 0x14}, 4892 {"card0-hi ", 0x15, "\020\7AM\10WP"}, 4893 {"mem1-slow ", 0x18}, 4894 {"mem1-shi ", 0x19, "\020\7ZW\10DS"}, 4895 {"mem1-elow ", 0x1a}, 4896 {"mem1-ehi ", 0x1b, "\020\7WS0\10WS1"}, 4897 {"card1-low ", 0x1c}, 4898 {"card1-hi ", 0x1d, "\020\7AM\10WP"}, 4899 {"mem2-slow ", 0x20}, 4900 {"mem2-shi ", 0x21, "\020\7ZW\10DS"}, 4901 {"mem2-elow ", 0x22}, 4902 {"mem2-ehi ", 0x23, "\020\7WS0\10WS1"}, 4903 {"card2-low ", 0x24}, 4904 {"card2-hi ", 0x25, "\020\7AM\10WP"}, 4905 {"mem3-slow ", 0x28}, 4906 {"mem3-shi ", 0x29, "\020\7ZW\10DS"}, 4907 {"mem3-elow ", 0x2a}, 4908 {"mem3-ehi ", 0x2b, "\020\7WS0\10WS1"}, 4909 {"card3-low ", 0x2c}, 4910 {"card3-hi ", 0x2d, "\020\7AM\10WP"}, 4911 4912 {"mem4-slow ", 0x30}, 4913 {"mem4-shi ", 0x31, "\020\7ZW\10DS"}, 4914 {"mem4-elow ", 0x32}, 4915 {"mem4-ehi ", 0x33, "\020\7WS0\10WS1"}, 4916 {"card4-low ", 0x34}, 4917 {"card4-hi ", 0x35, "\020\7AM\10WP"}, 4918 {"mpage0 ", 0x40}, 4919 {"mpage1 ", 0x41}, 4920 {"mpage2 ", 0x42}, 4921 {"mpage3 ", 0x43}, 4922 {"mpage4 ", 0x44}, 4923 {NULL}, 4924 }; 4925 4926 static struct intel_regs cregs[] = { 4927 {"misc-ctl1 ", 0x16, "\20\2VCC3\3PMI\4PSI\5SPKR\10INPACK"}, 4928 {"fifo ", 0x17, "\20\6DIOP\7DMEMP\10EMPTY"}, 4929 {"misc-ctl2 ", 0x1e, "\20\1XCLK\2LOW\3SUSP\4CORE5V\5TCD\10RIOUT"}, 4930 {"chip-info ", 0x1f, "\20\6DUAL"}, 4931 {"IO-offlow0", 0x36}, 4932 {"IO-offhi0 ", 0x37}, 4933 {"IO-offlow1", 0x38}, 4934 {"IO-offhi1 ", 0x39}, 4935 NULL, 4936 }; 4937 4938 static struct intel_regs cxregs[] = { 4939 {"ext-ctl-1 ", 0x03, 4940 "\20\1VCCLCK\2AUTOCLR\3LED\4INVIRQC\5INVIRQM\6PUC"}, 4941 {"misc-ctl3 ", 0x25, "\20\5HWSUSP"}, 4942 {"mem0-up ", 0x05}, 4943 {"mem1-up ", 0x06}, 4944 {"mem2-up ", 0x07}, 4945 {"mem3-up ", 0x08}, 4946 {"mem4-up ", 0x09}, 4947 {NULL} 4948 }; 4949 4950 void 4951 xxdmp_cl_regs(pcicdev_t *pcic, int socket, uint32_t len) 4952 { 4953 int i, value, j; 4954 char buff[256]; 4955 char *fmt; 4956 4957 cmn_err(CE_CONT, "--------- Cirrus Logic Registers --------\n"); 4958 for (buff[0] = '\0', i = 0; cregs[i].name != NULL && len-- != 0; i++) { 4959 int sval; 4960 if (cregs[i].off == PCIC_MISC_CTL_2) 4961 sval = 0; 4962 else 4963 sval = socket; 4964 value = pcic_getb(pcic, sval, cregs[i].off); 4965 if (i & 1) { 4966 if (cregs[i].fmt) 4967 fmt = "%s\t%s\t%b\n"; 4968 else 4969 fmt = "%s\t%s\t%x\n"; 4970 cmn_err(CE_CONT, fmt, buff, 4971 cregs[i].name, value, cregs[i].fmt); 4972 buff[0] = '\0'; 4973 } else { 4974 if (cregs[i].fmt) 4975 fmt = "\t%s\t%b"; 4976 else 4977 fmt = "\t%s\t%x"; 4978 (void) sprintf(buff, fmt, 4979 cregs[i].name, value, cregs[i].fmt); 4980 for (j = strlen(buff); j < 40; j++) 4981 buff[j] = ' '; 4982 buff[40] = '\0'; 4983 } 4984 } 4985 cmn_err(CE_CONT, "%s\n", buff); 4986 4987 i = pcic_getb(pcic, socket, PCIC_TIME_SETUP_0); 4988 j = pcic_getb(pcic, socket, PCIC_TIME_SETUP_1); 4989 cmn_err(CE_CONT, "\tsetup-tim0\t%x\tsetup-tim1\t%x\n", i, j); 4990 4991 i = pcic_getb(pcic, socket, PCIC_TIME_COMMAND_0); 4992 j = pcic_getb(pcic, socket, PCIC_TIME_COMMAND_1); 4993 cmn_err(CE_CONT, "\tcmd-tim0 \t%x\tcmd-tim1 \t%x\n", i, j); 4994 4995 i = pcic_getb(pcic, socket, PCIC_TIME_RECOVER_0); 4996 j = pcic_getb(pcic, socket, PCIC_TIME_RECOVER_1); 4997 cmn_err(CE_CONT, "\trcvr-tim0 \t%x\trcvr-tim1 \t%x\n", i, j); 4998 4999 cmn_err(CE_CONT, "--------- Extended Registers --------\n"); 5000 5001 for (buff[0] = '\0', i = 0; cxregs[i].name != NULL && len-- != 0; i++) { 5002 value = clext_reg_read(pcic, socket, cxregs[i].off); 5003 if (i & 1) { 5004 if (cxregs[i].fmt) 5005 fmt = "%s\t%s\t%b\n"; 5006 else 5007 fmt = "%s\t%s\t%x\n"; 5008 cmn_err(CE_CONT, fmt, buff, 5009 cxregs[i].name, value, cxregs[i].fmt); 5010 buff[0] = '\0'; 5011 } else { 5012 if (cxregs[i].fmt) 5013 fmt = "\t%s\t%b"; 5014 else 5015 fmt = "\t%s\t%x"; 5016 (void) sprintf(buff, fmt, 5017 cxregs[i].name, value, cxregs[i].fmt); 5018 for (j = strlen(buff); j < 40; j++) 5019 buff[j] = ' '; 5020 buff[40] = '\0'; 5021 } 5022 } 5023 } 5024 5025 #if defined(PCIC_DEBUG) 5026 static void 5027 xxdmp_all_regs(pcicdev_t *pcic, int socket, uint32_t len) 5028 { 5029 int i, value, j; 5030 char buff[256]; 5031 char *fmt; 5032 5033 #if defined(PCIC_DEBUG) 5034 if (pcic_debug < 2) 5035 return; 5036 #endif 5037 cmn_err(CE_CONT, 5038 "----------- PCIC Registers for socket %d---------\n", 5039 socket); 5040 cmn_err(CE_CONT, 5041 "\tname value name value\n"); 5042 5043 for (buff[0] = '\0', i = 0; iregs[i].name != NULL && len-- != 0; i++) { 5044 value = pcic_getb(pcic, socket, iregs[i].off); 5045 if (i & 1) { 5046 if (iregs[i].fmt) 5047 fmt = "%s\t%s\t%b\n"; 5048 else 5049 fmt = "%s\t%s\t%x\n"; 5050 cmn_err(CE_CONT, fmt, buff, 5051 iregs[i].name, value, iregs[i].fmt); 5052 buff[0] = '\0'; 5053 } else { 5054 if (iregs[i].fmt) 5055 fmt = "\t%s\t%b"; 5056 else 5057 fmt = "\t%s\t%x"; 5058 (void) sprintf(buff, fmt, 5059 iregs[i].name, value, iregs[i].fmt); 5060 for (j = strlen(buff); j < 40; j++) 5061 buff[j] = ' '; 5062 buff[40] = '\0'; 5063 } 5064 } 5065 switch (pcic->pc_type) { 5066 case PCIC_CL_PD6710: 5067 case PCIC_CL_PD6722: 5068 case PCIC_CL_PD6729: 5069 case PCIC_CL_PD6832: 5070 (void) xxdmp_cl_regs(pcic, socket, 0xFFFF); 5071 break; 5072 } 5073 cmn_err(CE_CONT, "%s\n", buff); 5074 } 5075 #endif 5076 5077 /* 5078 * pcic_mswait(ms) 5079 * sleep ms milliseconds 5080 * call drv_usecwait once for each ms 5081 */ 5082 static void 5083 pcic_mswait(pcicdev_t *pcic, int socket, int ms) 5084 { 5085 if (ms) { 5086 pcic->pc_sockets[socket].pcs_flags |= PCS_WAITING; 5087 pcic_mutex_exit(&pcic->pc_lock); 5088 delay(drv_usectohz(ms*1000)); 5089 pcic_mutex_enter(&pcic->pc_lock); 5090 pcic->pc_sockets[socket].pcs_flags &= ~PCS_WAITING; 5091 } 5092 } 5093 5094 /* 5095 * pcic_check_ready(pcic, index, off) 5096 * Wait for card to come ready 5097 * We only wait if the card is NOT in RESET 5098 * and power is on. 5099 */ 5100 static boolean_t 5101 pcic_check_ready(pcicdev_t *pcic, int socket) 5102 { 5103 int ifstate, intstate; 5104 5105 intstate = pcic_getb(pcic, socket, PCIC_INTERRUPT); 5106 ifstate = pcic_getb(pcic, socket, PCIC_INTERFACE_STATUS); 5107 5108 if ((intstate & PCIC_RESET) && 5109 ((ifstate & (PCIC_READY|PCIC_POWER_ON|PCIC_ISTAT_CD_MASK)) == 5110 (PCIC_READY|PCIC_POWER_ON|PCIC_CD_PRESENT_OK))) 5111 return (B_TRUE); 5112 5113 #ifdef PCIC_DEBUG 5114 pcic_err(NULL, 5, "pcic_check_read: Card not ready, intstate = 0x%x, " 5115 "ifstate = 0x%x\n", intstate, ifstate); 5116 if (pcic_debug) { 5117 pcic_debug += 4; 5118 xxdmp_all_regs(pcic, socket, -1); 5119 pcic_debug -= 4; 5120 } 5121 #endif 5122 return (B_FALSE); 5123 } 5124 5125 /* 5126 * Cirrus Logic extended register read/write routines 5127 */ 5128 static int 5129 clext_reg_read(pcicdev_t *pcic, int sn, uchar_t ext_reg) 5130 { 5131 int val; 5132 5133 switch (pcic->pc_io_type) { 5134 case PCIC_IO_TYPE_YENTA: 5135 val = ddi_get8(pcic->handle, 5136 pcic->ioaddr + CB_CLEXT_OFFSET + ext_reg); 5137 break; 5138 default: 5139 pcic_putb(pcic, sn, PCIC_CL_EXINDEX, ext_reg); 5140 val = pcic_getb(pcic, sn, PCIC_CL_EXINDEX + 1); 5141 break; 5142 } 5143 5144 return (val); 5145 } 5146 5147 static void 5148 clext_reg_write(pcicdev_t *pcic, int sn, uchar_t ext_reg, uchar_t value) 5149 { 5150 switch (pcic->pc_io_type) { 5151 case PCIC_IO_TYPE_YENTA: 5152 ddi_put8(pcic->handle, 5153 pcic->ioaddr + CB_CLEXT_OFFSET + ext_reg, value); 5154 break; 5155 default: 5156 pcic_putb(pcic, sn, PCIC_CL_EXINDEX, ext_reg); 5157 pcic_putb(pcic, sn, PCIC_CL_EXINDEX + 1, value); 5158 break; 5159 } 5160 } 5161 5162 /* 5163 * Misc PCI functions 5164 */ 5165 static void 5166 pcic_iomem_pci_ctl(ddi_acc_handle_t handle, uchar_t *cfgaddr, unsigned flags) 5167 { 5168 unsigned cmd; 5169 5170 if (flags & (PCIC_ENABLE_IO | PCIC_ENABLE_MEM)) { 5171 cmd = ddi_get16(handle, (ushort_t *)(cfgaddr + 4)); 5172 if ((cmd & (PCI_COMM_IO|PCI_COMM_MAE)) == 5173 (PCI_COMM_IO|PCI_COMM_MAE)) 5174 return; 5175 5176 if (flags & PCIC_ENABLE_IO) 5177 cmd |= PCI_COMM_IO; 5178 5179 if (flags & PCIC_ENABLE_MEM) 5180 cmd |= PCI_COMM_MAE; 5181 5182 ddi_put16(handle, (ushort_t *)(cfgaddr + 4), cmd); 5183 } /* if (PCIC_ENABLE_IO | PCIC_ENABLE_MEM) */ 5184 } 5185 5186 /* 5187 * pcic_find_pci_type - Find and return PCI-PCMCIA adapter type 5188 */ 5189 static int 5190 pcic_find_pci_type(pcicdev_t *pcic) 5191 { 5192 uint32_t vend, device; 5193 5194 vend = ddi_getprop(DDI_DEV_T_ANY, pcic->dip, 5195 DDI_PROP_CANSLEEP|DDI_PROP_DONTPASS, 5196 "vendor-id", -1); 5197 device = ddi_getprop(DDI_DEV_T_ANY, pcic->dip, 5198 DDI_PROP_CANSLEEP|DDI_PROP_DONTPASS, 5199 "device-id", -1); 5200 5201 device = PCI_ID(vend, device); 5202 pcic->pc_type = device; 5203 pcic->pc_chipname = "PCI:unknown"; 5204 5205 switch (device) { 5206 case PCIC_INTEL_i82092: 5207 pcic->pc_chipname = PCIC_TYPE_i82092; 5208 break; 5209 case PCIC_CL_PD6729: 5210 pcic->pc_chipname = PCIC_TYPE_PD6729; 5211 /* 5212 * Some 6730's incorrectly identify themselves 5213 * as a 6729, so we need to do some more tests 5214 * here to see if the device that's claiming 5215 * to be a 6729 is really a 6730. 5216 */ 5217 if ((clext_reg_read(pcic, 0, PCIC_CLEXT_MISC_CTL_3) & 5218 PCIC_CLEXT_MISC_CTL_3_REV_MASK) == 5219 0) { 5220 pcic->pc_chipname = PCIC_TYPE_PD6730; 5221 pcic->pc_type = PCIC_CL_PD6730; 5222 } 5223 break; 5224 case PCIC_CL_PD6730: 5225 pcic->pc_chipname = PCIC_TYPE_PD6730; 5226 break; 5227 case PCIC_CL_PD6832: 5228 pcic->pc_chipname = PCIC_TYPE_PD6832; 5229 break; 5230 case PCIC_SMC_34C90: 5231 pcic->pc_chipname = PCIC_TYPE_34C90; 5232 break; 5233 case PCIC_TOSHIBA_TOPIC95: 5234 pcic->pc_chipname = PCIC_TYPE_TOPIC95; 5235 break; 5236 case PCIC_TOSHIBA_TOPIC100: 5237 pcic->pc_chipname = PCIC_TYPE_TOPIC100; 5238 break; 5239 case PCIC_TI_PCI1031: 5240 pcic->pc_chipname = PCIC_TYPE_PCI1031; 5241 break; 5242 case PCIC_TI_PCI1130: 5243 pcic->pc_chipname = PCIC_TYPE_PCI1130; 5244 break; 5245 case PCIC_TI_PCI1131: 5246 pcic->pc_chipname = PCIC_TYPE_PCI1131; 5247 break; 5248 case PCIC_TI_PCI1250: 5249 pcic->pc_chipname = PCIC_TYPE_PCI1250; 5250 break; 5251 case PCIC_TI_PCI1225: 5252 pcic->pc_chipname = PCIC_TYPE_PCI1225; 5253 break; 5254 case PCIC_TI_PCI1410: 5255 pcic->pc_chipname = PCIC_TYPE_PCI1410; 5256 break; 5257 case PCIC_TI_PCI1510: 5258 pcic->pc_chipname = PCIC_TYPE_PCI1510; 5259 break; 5260 case PCIC_TI_PCI1520: 5261 pcic->pc_chipname = PCIC_TYPE_PCI1520; 5262 break; 5263 case PCIC_TI_PCI1221: 5264 pcic->pc_chipname = PCIC_TYPE_PCI1221; 5265 break; 5266 case PCIC_TI_PCI1050: 5267 pcic->pc_chipname = PCIC_TYPE_PCI1050; 5268 break; 5269 case PCIC_ENE_1410: 5270 pcic->pc_chipname = PCIC_TYPE_1410; 5271 break; 5272 case PCIC_O2_OZ6912: 5273 pcic->pc_chipname = PCIC_TYPE_OZ6912; 5274 break; 5275 case PCIC_RICOH_RL5C466: 5276 pcic->pc_chipname = PCIC_TYPE_RL5C466; 5277 break; 5278 case PCIC_TI_PCI1420: 5279 pcic->pc_chipname = PCIC_TYPE_PCI1420; 5280 break; 5281 case PCIC_ENE_1420: 5282 pcic->pc_chipname = PCIC_TYPE_1420; 5283 break; 5284 default: 5285 switch (PCI_ID(vend, (uint32_t)0)) { 5286 case PCIC_TOSHIBA_VENDOR: 5287 pcic->pc_chipname = PCIC_TYPE_TOSHIBA; 5288 pcic->pc_type = PCIC_TOSHIBA_VENDOR; 5289 break; 5290 case PCIC_TI_VENDOR: 5291 pcic->pc_chipname = PCIC_TYPE_TI; 5292 pcic->pc_type = PCIC_TI_VENDOR; 5293 break; 5294 case PCIC_O2MICRO_VENDOR: 5295 pcic->pc_chipname = PCIC_TYPE_O2MICRO; 5296 pcic->pc_type = PCIC_O2MICRO_VENDOR; 5297 break; 5298 case PCIC_RICOH_VENDOR: 5299 pcic->pc_chipname = PCIC_TYPE_RICOH; 5300 pcic->pc_type = PCIC_RICOH_VENDOR; 5301 break; 5302 default: 5303 if (!(pcic->pc_flags & PCF_CARDBUS)) 5304 return (DDI_FAILURE); 5305 pcic->pc_chipname = PCIC_TYPE_YENTA; 5306 break; 5307 } 5308 } 5309 return (DDI_SUCCESS); 5310 } 5311 5312 static void 5313 pcic_82092_smiirq_ctl(pcicdev_t *pcic, int socket, int intr, int state) 5314 { 5315 uchar_t ppirr = ddi_get8(pcic->cfg_handle, 5316 pcic->cfgaddr + PCIC_82092_PPIRR); 5317 uchar_t val; 5318 5319 if (intr == PCIC_82092_CTL_SMI) { 5320 val = PCIC_82092_SMI_CTL(socket, 5321 PCIC_82092_INT_DISABLE); 5322 ppirr &= ~val; 5323 val = PCIC_82092_SMI_CTL(socket, state); 5324 ppirr |= val; 5325 } else { 5326 val = PCIC_82092_IRQ_CTL(socket, 5327 PCIC_82092_INT_DISABLE); 5328 ppirr &= ~val; 5329 val = PCIC_82092_IRQ_CTL(socket, state); 5330 ppirr |= val; 5331 } 5332 ddi_put8(pcic->cfg_handle, pcic->cfgaddr + PCIC_82092_PPIRR, 5333 ppirr); 5334 } 5335 5336 static uint_t 5337 pcic_cd_softint(caddr_t arg1, caddr_t arg2) 5338 { 5339 pcic_socket_t *sockp = (pcic_socket_t *)arg1; 5340 uint_t rc = DDI_INTR_UNCLAIMED; 5341 5342 _NOTE(ARGUNUSED(arg2)) 5343 5344 mutex_enter(&sockp->pcs_pcic->pc_lock); 5345 if (sockp->pcs_cd_softint_flg) { 5346 uint8_t status; 5347 sockp->pcs_cd_softint_flg = 0; 5348 rc = DDI_INTR_CLAIMED; 5349 status = pcic_getb(sockp->pcs_pcic, sockp->pcs_socket, 5350 PCIC_INTERFACE_STATUS); 5351 pcic_handle_cd_change(sockp->pcs_pcic, sockp, status); 5352 } 5353 mutex_exit(&sockp->pcs_pcic->pc_lock); 5354 return (rc); 5355 } 5356 5357 int pcic_debounce_cnt = PCIC_REM_DEBOUNCE_CNT; 5358 int pcic_debounce_intr_time = PCIC_REM_DEBOUNCE_TIME; 5359 int pcic_debounce_cnt_ok = PCIC_DEBOUNCE_OK_CNT; 5360 5361 #ifdef CARDBUS 5362 static uint32_t pcic_cbps_on = 0; 5363 static uint32_t pcic_cbps_off = CB_PS_NOTACARD | CB_PS_CCDMASK | 5364 CB_PS_XVCARD | CB_PS_YVCARD; 5365 #else 5366 static uint32_t pcic_cbps_on = CB_PS_16BITCARD; 5367 static uint32_t pcic_cbps_off = CB_PS_NOTACARD | CB_PS_CCDMASK | 5368 CB_PS_CBCARD | 5369 CB_PS_XVCARD | CB_PS_YVCARD; 5370 #endif 5371 static void 5372 pcic_handle_cd_change(pcicdev_t *pcic, pcic_socket_t *sockp, uint8_t status) 5373 { 5374 boolean_t do_debounce = B_FALSE; 5375 int debounce_time = drv_usectohz(pcic_debounce_time); 5376 uint8_t irq; 5377 timeout_id_t debounce; 5378 5379 /* 5380 * Always reset debounce but may need to check original state later. 5381 */ 5382 debounce = sockp->pcs_debounce_id; 5383 sockp->pcs_debounce_id = 0; 5384 5385 /* 5386 * Check to see whether a card is present or not. There are 5387 * only two states that we are concerned with - the state 5388 * where both CD pins are asserted, which means that the 5389 * card is fully seated, and the state where neither CD 5390 * pin is asserted, which means that the card is not 5391 * present. 5392 * The CD signals are generally very noisy and cause a lot of 5393 * contact bounce as the card is being inserted and 5394 * removed, so we need to do some software debouncing. 5395 */ 5396 5397 #ifdef PCIC_DEBUG 5398 pcic_err(pcic->dip, 6, 5399 "pcic%d handle_cd_change: socket %d card status 0x%x" 5400 " deb 0x%p\n", ddi_get_instance(pcic->dip), 5401 sockp->pcs_socket, status, debounce); 5402 #endif 5403 switch (status & PCIC_ISTAT_CD_MASK) { 5404 case PCIC_CD_PRESENT_OK: 5405 sockp->pcs_flags &= ~(PCS_CARD_REMOVED|PCS_CARD_CBREM); 5406 if (!(sockp->pcs_flags & PCS_CARD_PRESENT)) { 5407 uint32_t cbps; 5408 #ifdef PCIC_DEBUG 5409 pcic_err(pcic->dip, 8, "New card (0x%x)\n", sockp->pcs_flags); 5410 #endif 5411 cbps = pcic_getcb(pcic, CB_PRESENT_STATE); 5412 #ifdef PCIC_DEBUG 5413 pcic_err(pcic->dip, 8, "CBus PS (0x%x)\n", cbps); 5414 #endif 5415 /* 5416 * Check the CB bits are sane. 5417 */ 5418 if ((cbps & pcic_cbps_on) != pcic_cbps_on || 5419 cbps & pcic_cbps_off) { 5420 cmn_err(CE_WARN, 5421 "%s%d: Odd Cardbus Present State 0x%x\n", 5422 ddi_get_name(pcic->dip), 5423 ddi_get_instance(pcic->dip), 5424 cbps); 5425 pcic_putcb(pcic, CB_EVENT_FORCE, CB_EF_CVTEST); 5426 debounce = 0; 5427 debounce_time = drv_usectohz(1000000); 5428 } 5429 if (debounce) { 5430 sockp->pcs_flags |= PCS_CARD_PRESENT; 5431 if (pcic_do_insertion) { 5432 5433 cbps = pcic_getcb(pcic, CB_PRESENT_STATE); 5434 5435 if (cbps & CB_PS_16BITCARD) { 5436 pcic_err(pcic->dip, 8, "16 bit card inserted\n"); 5437 sockp->pcs_flags |= PCS_CARD_IS16BIT; 5438 /* calls pcm_adapter_callback() */ 5439 if (pcic->pc_callback) { 5440 5441 (void) ddi_prop_update_string(DDI_DEV_T_NONE, 5442 pcic->dip, PCM_DEVICETYPE, 5443 "pccard"); 5444 PC_CALLBACK(pcic->dip, pcic->pc_cb_arg, 5445 PCE_CARD_INSERT, 5446 sockp->pcs_socket); 5447 } 5448 } else if (cbps & CB_PS_CBCARD) { 5449 pcic_err(pcic->dip, 8, "32 bit card inserted\n"); 5450 5451 if (pcic->pc_flags & PCF_CARDBUS) { 5452 sockp->pcs_flags |= PCS_CARD_ISCARDBUS; 5453 #ifdef CARDBUS 5454 if (!pcic_load_cardbus(pcic, sockp)) { 5455 pcic_unload_cardbus(pcic, sockp); 5456 } 5457 5458 #else 5459 cmn_err(CE_NOTE, 5460 "32 bit Cardbus not supported in" 5461 " this device driver\n"); 5462 #endif 5463 } else { 5464 /* 5465 * Ignore the card 5466 */ 5467 cmn_err(CE_NOTE, 5468 "32 bit Cardbus not supported on this" 5469 " device\n"); 5470 } 5471 } else { 5472 cmn_err(CE_NOTE, 5473 "Unsupported PCMCIA card inserted\n"); 5474 } 5475 } 5476 } else { 5477 do_debounce = B_TRUE; 5478 } 5479 } else { 5480 /* 5481 * It is possible to come through here if the system 5482 * starts up with cards already inserted. Do nothing 5483 * and don't worry about it. 5484 */ 5485 #ifdef PCIC_DEBUG 5486 pcic_err(pcic->dip, 5, 5487 "pcic%d: Odd card insertion indication on socket %d\n", 5488 ddi_get_instance(pcic->dip), 5489 sockp->pcs_socket); 5490 #endif 5491 } 5492 break; 5493 5494 default: 5495 if (!(sockp->pcs_flags & PCS_CARD_PRESENT)) { 5496 /* 5497 * Someone has started to insert a card so delay a while. 5498 */ 5499 do_debounce = B_TRUE; 5500 break; 5501 } 5502 /* 5503 * Otherwise this is basically the same as not present 5504 * so fall through. 5505 */ 5506 5507 /* FALLTHRU */ 5508 case 0: 5509 if (sockp->pcs_flags & PCS_CARD_PRESENT) { 5510 if (pcic->pc_flags & PCF_CBPWRCTL) { 5511 pcic_putcb(pcic, CB_CONTROL, 0); 5512 } else { 5513 pcic_putb(pcic, sockp->pcs_socket, PCIC_POWER_CONTROL, 0); 5514 (void) pcic_getb(pcic, sockp->pcs_socket, 5515 PCIC_POWER_CONTROL); 5516 } 5517 #ifdef PCIC_DEBUG 5518 pcic_err(pcic->dip, 8, "Card removed\n"); 5519 #endif 5520 sockp->pcs_flags &= ~PCS_CARD_PRESENT; 5521 5522 if (sockp->pcs_flags & PCS_CARD_IS16BIT) { 5523 sockp->pcs_flags &= ~PCS_CARD_IS16BIT; 5524 if (pcic_do_removal && pcic->pc_callback) { 5525 PC_CALLBACK(pcic->dip, pcic->pc_cb_arg, 5526 PCE_CARD_REMOVAL, sockp->pcs_socket); 5527 } 5528 } 5529 if (sockp->pcs_flags & PCS_CARD_ISCARDBUS) { 5530 sockp->pcs_flags &= ~PCS_CARD_ISCARDBUS; 5531 sockp->pcs_flags |= PCS_CARD_CBREM; 5532 } 5533 sockp->pcs_flags |= PCS_CARD_REMOVED; 5534 5535 do_debounce = B_TRUE; 5536 } 5537 if (debounce && (sockp->pcs_flags & PCS_CARD_REMOVED)) { 5538 if (sockp->pcs_flags & PCS_CARD_CBREM) { 5539 /* 5540 * Ensure that we do the unloading in the 5541 * debounce handler, that way we're not doing 5542 * nasty things in an interrupt handler. e.g. 5543 * a USB device will wait for data which will 5544 * obviously never come because we've 5545 * unplugged the device, but the wait will 5546 * wait forever because no interrupts can 5547 * come in... 5548 */ 5549 #ifdef CARDBUS 5550 pcic_unload_cardbus(pcic, sockp); 5551 /* pcic_dump_all(pcic); */ 5552 #endif 5553 sockp->pcs_flags &= ~PCS_CARD_CBREM; 5554 } 5555 sockp->pcs_flags &= ~PCS_CARD_REMOVED; 5556 } 5557 break; 5558 } /* switch */ 5559 5560 if (do_debounce) { 5561 /* 5562 * Delay doing 5563 * anything for a while so that things can settle 5564 * down a little. Interrupts are already disabled. 5565 * Reset the state and we'll reevaluate the 5566 * whole kit 'n kaboodle when the timeout fires 5567 */ 5568 #ifdef PCIC_DEBUG 5569 pcic_err(pcic->dip, 8, "Queueing up debounce timeout for " 5570 "socket %d.%d\n", 5571 ddi_get_instance(pcic->dip), 5572 sockp->pcs_socket); 5573 #endif 5574 sockp->pcs_debounce_id = pcic_add_debqueue(sockp, debounce_time); 5575 5576 /* 5577 * We bug out here without re-enabling interrupts. They will 5578 * be re-enabled when the debounce timeout swings through 5579 * here. 5580 */ 5581 return; 5582 } 5583 5584 /* 5585 * Turn on Card detect interrupts. Other interrupts will be 5586 * enabled during set_socket calls. 5587 * 5588 * Note that set_socket only changes interrupt settings when there 5589 * is a card present. 5590 */ 5591 irq = pcic_getb(pcic, sockp->pcs_socket, PCIC_MANAGEMENT_INT); 5592 irq |= PCIC_CD_DETECT; 5593 pcic_putb(pcic, sockp->pcs_socket, PCIC_MANAGEMENT_INT, irq); 5594 pcic_putcb(pcic, CB_STATUS_MASK, CB_SE_CCDMASK); 5595 5596 /* Out from debouncing state */ 5597 sockp->pcs_flags &= ~PCS_DEBOUNCING; 5598 5599 pcic_err(pcic->dip, 7, "Leaving pcic_handle_cd_change\n"); 5600 } 5601 5602 /* 5603 * pcic_getb() 5604 * get an I/O byte based on the yardware decode method 5605 */ 5606 static uint8_t 5607 pcic_getb(pcicdev_t *pcic, int socket, int reg) 5608 { 5609 int work; 5610 5611 #if defined(PCIC_DEBUG) 5612 if (pcic_debug == 0x7fff) { 5613 cmn_err(CE_CONT, "pcic_getb0: pcic=%p socket=%d reg=%d\n", 5614 (void *)pcic, socket, reg); 5615 cmn_err(CE_CONT, "pcic_getb1: type=%d handle=%p ioaddr=%p \n", 5616 pcic->pc_io_type, (void *)pcic->handle, 5617 (void *)pcic->ioaddr); 5618 } 5619 #endif 5620 5621 switch (pcic->pc_io_type) { 5622 case PCIC_IO_TYPE_YENTA: 5623 return (ddi_get8(pcic->handle, 5624 pcic->ioaddr + CB_R2_OFFSET + reg)); 5625 default: 5626 work = (socket * PCIC_SOCKET_1) | reg; 5627 ddi_put8(pcic->handle, pcic->ioaddr, work); 5628 return (ddi_get8(pcic->handle, pcic->ioaddr + 1)); 5629 } 5630 } 5631 5632 static void 5633 pcic_putb(pcicdev_t *pcic, int socket, int reg, int8_t value) 5634 { 5635 int work; 5636 5637 #if defined(PCIC_DEBUG) 5638 if (pcic_debug == 0x7fff) { 5639 cmn_err(CE_CONT, 5640 "pcic_putb0: pcic=%p socket=%d reg=%d value=%x \n", 5641 (void *)pcic, socket, reg, value); 5642 cmn_err(CE_CONT, 5643 "pcic_putb1: type=%d handle=%p ioaddr=%p \n", 5644 pcic->pc_io_type, (void *)pcic->handle, 5645 (void *)pcic->ioaddr); 5646 } 5647 #endif 5648 5649 5650 switch (pcic->pc_io_type) { 5651 case PCIC_IO_TYPE_YENTA: 5652 ddi_put8(pcic->handle, pcic->ioaddr + CB_R2_OFFSET + reg, 5653 value); 5654 break; 5655 default: 5656 work = (socket * PCIC_SOCKET_1) | reg; 5657 ddi_put8(pcic->handle, pcic->ioaddr, work); 5658 ddi_put8(pcic->handle, pcic->ioaddr + 1, value); 5659 break; 5660 } 5661 } 5662 5663 /* 5664 * chip identification functions 5665 */ 5666 5667 /* 5668 * chip identification: Cirrus Logic PD6710/6720/6722 5669 */ 5670 static int 5671 pcic_ci_cirrus(pcicdev_t *pcic) 5672 { 5673 int value1, value2; 5674 5675 /* Init the CL id mode */ 5676 value1 = pcic_getb(pcic, 0, PCIC_CHIP_INFO); 5677 pcic_putb(pcic, 0, PCIC_CHIP_INFO, 0); 5678 value1 = pcic_getb(pcic, 0, PCIC_CHIP_INFO); 5679 value2 = pcic_getb(pcic, 0, PCIC_CHIP_INFO); 5680 5681 if ((value1 & PCIC_CI_ID) == PCIC_CI_ID && 5682 (value2 & PCIC_CI_ID) == 0) { 5683 /* chip is a Cirrus Logic and not Intel */ 5684 pcic->pc_type = PCIC_CL_PD6710; 5685 if (value1 & PCIC_CI_SLOTS) 5686 pcic->pc_chipname = PCIC_TYPE_PD6720; 5687 else 5688 pcic->pc_chipname = PCIC_TYPE_PD6710; 5689 /* now fine tune things just in case a 6722 */ 5690 value1 = clext_reg_read(pcic, 0, PCIC_CLEXT_DMASK_0); 5691 if (value1 == 0) { 5692 clext_reg_write(pcic, 0, PCIC_CLEXT_SCRATCH, 0x55); 5693 value1 = clext_reg_read(pcic, 0, PCIC_CLEXT_SCRATCH); 5694 if (value1 == 0x55) { 5695 pcic->pc_chipname = PCIC_TYPE_PD6722; 5696 pcic->pc_type = PCIC_CL_PD6722; 5697 clext_reg_write(pcic, 0, PCIC_CLEXT_SCRATCH, 0); 5698 } 5699 } 5700 return (1); 5701 } 5702 return (0); 5703 } 5704 5705 /* 5706 * chip identification: Vadem (VG365/465/468/469) 5707 */ 5708 5709 static void 5710 pcic_vadem_enable(pcicdev_t *pcic) 5711 { 5712 ddi_put8(pcic->handle, pcic->ioaddr, PCIC_VADEM_P1); 5713 ddi_put8(pcic->handle, pcic->ioaddr, PCIC_VADEM_P2); 5714 ddi_put8(pcic->handle, pcic->ioaddr, pcic->pc_lastreg); 5715 } 5716 5717 static int 5718 pcic_ci_vadem(pcicdev_t *pcic) 5719 { 5720 int value; 5721 5722 pcic_vadem_enable(pcic); 5723 value = pcic_getb(pcic, 0, PCIC_CHIP_REVISION); 5724 pcic_putb(pcic, 0, PCIC_CHIP_REVISION, 0xFF); 5725 if (pcic_getb(pcic, 0, PCIC_CHIP_REVISION) == 5726 (value | PCIC_VADEM_D3) || 5727 (pcic_getb(pcic, 0, PCIC_CHIP_REVISION) & PCIC_REV_MASK) == 5728 PCIC_VADEM_469) { 5729 int vadem, new; 5730 pcic_vadem_enable(pcic); 5731 vadem = pcic_getb(pcic, 0, PCIC_VG_DMA) & 5732 ~(PCIC_V_UNLOCK | PCIC_V_VADEMREV); 5733 new = vadem | (PCIC_V_VADEMREV|PCIC_V_UNLOCK); 5734 pcic_putb(pcic, 0, PCIC_VG_DMA, new); 5735 value = pcic_getb(pcic, 0, PCIC_CHIP_REVISION); 5736 5737 /* want to lock but leave mouse or other on */ 5738 pcic_putb(pcic, 0, PCIC_VG_DMA, vadem); 5739 switch (value & PCIC_REV_MASK) { 5740 case PCIC_VADEM_365: 5741 pcic->pc_chipname = PCIC_VG_365; 5742 pcic->pc_type = PCIC_VADEM; 5743 break; 5744 case PCIC_VADEM_465: 5745 pcic->pc_chipname = PCIC_VG_465; 5746 pcic->pc_type = PCIC_VADEM; 5747 pcic->pc_flags |= PCF_1SOCKET; 5748 break; 5749 case PCIC_VADEM_468: 5750 pcic->pc_chipname = PCIC_VG_468; 5751 pcic->pc_type = PCIC_VADEM; 5752 break; 5753 case PCIC_VADEM_469: 5754 pcic->pc_chipname = PCIC_VG_469; 5755 pcic->pc_type = PCIC_VADEM_VG469; 5756 break; 5757 } 5758 return (1); 5759 } 5760 return (0); 5761 } 5762 5763 /* 5764 * chip identification: Ricoh 5765 */ 5766 static int 5767 pcic_ci_ricoh(pcicdev_t *pcic) 5768 { 5769 int value; 5770 5771 value = pcic_getb(pcic, 0, PCIC_RF_CHIP_IDENT); 5772 switch (value) { 5773 case PCIC_RF_296: 5774 pcic->pc_type = PCIC_RICOH; 5775 pcic->pc_chipname = PCIC_TYPE_RF5C296; 5776 return (1); 5777 case PCIC_RF_396: 5778 pcic->pc_type = PCIC_RICOH; 5779 pcic->pc_chipname = PCIC_TYPE_RF5C396; 5780 return (1); 5781 } 5782 return (0); 5783 } 5784 5785 5786 /* 5787 * set up available address spaces in busra 5788 */ 5789 static void 5790 pcic_init_assigned(dev_info_t *dip) 5791 { 5792 pcm_regs_t *pcic_avail_p; 5793 pci_regspec_t *pci_avail_p, *regs; 5794 int len, entries, rlen; 5795 dev_info_t *pdip; 5796 5797 if (ddi_getlongprop(DDI_DEV_T_ANY, dip, DDI_PROP_DONTPASS, 5798 "available", (caddr_t)&pcic_avail_p, &len) == DDI_PROP_SUCCESS) { 5799 /* 5800 * found "available" property at the cardbus/pcmcia node 5801 * need to translate address space entries from pcmcia 5802 * format to pci format 5803 */ 5804 entries = len / sizeof (pcm_regs_t); 5805 pci_avail_p = kmem_alloc(sizeof (pci_regspec_t) * entries, 5806 KM_SLEEP); 5807 if (pcic_apply_avail_ranges(dip, pcic_avail_p, pci_avail_p, 5808 entries) == DDI_SUCCESS) 5809 (void) pci_resource_setup_avail(dip, pci_avail_p, 5810 entries); 5811 kmem_free(pcic_avail_p, len); 5812 kmem_free(pci_avail_p, entries * sizeof (pci_regspec_t)); 5813 return; 5814 } 5815 5816 /* 5817 * "legacy" platforms will have "available" property in pci node 5818 */ 5819 for (pdip = ddi_get_parent(dip); pdip; pdip = ddi_get_parent(pdip)) { 5820 if (ddi_getlongprop(DDI_DEV_T_ANY, pdip, DDI_PROP_DONTPASS, 5821 "available", (caddr_t)&pci_avail_p, &len) == 5822 DDI_PROP_SUCCESS) { 5823 /* (void) pci_resource_setup(pdip); */ 5824 kmem_free(pci_avail_p, len); 5825 break; 5826 } 5827 } 5828 5829 if (pdip == NULL) { 5830 int len; 5831 char bus_type[16] = "(unknown)"; 5832 dev_info_t *par; 5833 5834 cmn_err(CE_CONT, 5835 "?pcic_init_assigned: no available property for pcmcia\n"); 5836 5837 /* 5838 * This code is taken from pci_resource_setup() but does 5839 * not attempt to use the "available" property to populate 5840 * the ndi maps that are created. 5841 * The fact that we will actually 5842 * free some resource below (that was allocated by OBP) 5843 * should be enough to be going on with. 5844 */ 5845 for (par = dip; par != NULL; par = ddi_get_parent(par)) { 5846 len = sizeof (bus_type); 5847 5848 if ((ddi_prop_op(DDI_DEV_T_ANY, par, 5849 PROP_LEN_AND_VAL_BUF, 5850 DDI_PROP_CANSLEEP | DDI_PROP_DONTPASS, 5851 "device_type", 5852 (caddr_t)&bus_type, &len) == DDI_SUCCESS) && 5853 (strcmp(bus_type, DEVI_PCI_NEXNAME) == 0 || 5854 strcmp(bus_type, DEVI_PCIEX_NEXNAME) == 0)) 5855 break; 5856 } 5857 if (par != NULL && 5858 (ndi_ra_map_setup(par, NDI_RA_TYPE_MEM) != NDI_SUCCESS || 5859 ndi_ra_map_setup(par, NDI_RA_TYPE_IO) != NDI_SUCCESS)) 5860 par = NULL; 5861 } else { 5862 #ifdef CARDBUS 5863 cardbus_bus_range_t *bus_range; 5864 int k; 5865 5866 if (ddi_getlongprop(DDI_DEV_T_ANY, pdip, 0, "bus-range", 5867 (caddr_t)&bus_range, &k) == DDI_PROP_SUCCESS) { 5868 if (bus_range->lo != bus_range->hi) 5869 pcic_err(pdip, 9, "allowable bus range is " 5870 "%u->%u\n", bus_range->lo, bus_range->hi); 5871 else { 5872 pcic_err(pdip, 0, 5873 "!No spare PCI bus numbers, range is " 5874 "%u->%u, cardbus isn't usable\n", 5875 bus_range->lo, bus_range->hi); 5876 } 5877 kmem_free(bus_range, k); 5878 } else 5879 pcic_err(pdip, 0, "!No bus-range property seems to " 5880 "have been set up\n"); 5881 #endif 5882 /* 5883 * Have a valid parent with the "available" property 5884 */ 5885 (void) pci_resource_setup(pdip); 5886 } 5887 5888 if ((strcmp(ddi_get_name(dip), "pcma") == 0) && 5889 ddi_getlongprop(DDI_DEV_T_NONE, dip, DDI_PROP_DONTPASS, 5890 "assigned-addresses", 5891 (caddr_t)®s, &rlen) == DDI_SUCCESS) { 5892 ra_return_t ra; 5893 5894 /* 5895 * On the UltraBook IIi the ranges are assigned under 5896 * openboot. If we don't free them here the first I/O 5897 * space that can be used is up above 0x10000 which 5898 * doesn't work for this driver due to restrictions 5899 * on the PCI I/O addresses the controllers can cope with. 5900 * They are never going to be used by anything else 5901 * so free them up to the general pool. AG. 5902 */ 5903 pcic_err(dip, 1, "Free assigned addresses\n"); 5904 5905 if ((PCI_REG_ADDR_G(regs[0].pci_phys_hi) == 5906 PCI_REG_ADDR_G(PCI_ADDR_MEM32)) && 5907 regs[0].pci_size_low == 0x1000000) { 5908 ra.ra_addr_lo = regs[0].pci_phys_low; 5909 ra.ra_len = regs[0].pci_size_low; 5910 (void) pcmcia_free_mem(dip, &ra); 5911 } 5912 if ((PCI_REG_ADDR_G(regs[1].pci_phys_hi) == 5913 PCI_REG_ADDR_G(PCI_ADDR_IO)) && 5914 (regs[1].pci_size_low == 0x8000 || 5915 regs[1].pci_size_low == 0x4000)) /* UB-IIi || UB-I */ 5916 { 5917 ra.ra_addr_lo = regs[1].pci_phys_low; 5918 ra.ra_len = regs[1].pci_size_low; 5919 (void) pcmcia_free_io(dip, &ra); 5920 } 5921 kmem_free((caddr_t)regs, rlen); 5922 } 5923 } 5924 5925 /* 5926 * translate "available" from pcmcia format to pci format 5927 */ 5928 static int 5929 pcic_apply_avail_ranges(dev_info_t *dip, pcm_regs_t *pcic_p, 5930 pci_regspec_t *pci_p, int entries) 5931 { 5932 int i, range_len, range_entries; 5933 pcic_ranges_t *pcic_range_p; 5934 5935 if (ddi_getlongprop(DDI_DEV_T_ANY, dip, DDI_PROP_DONTPASS, "ranges", 5936 (caddr_t)&pcic_range_p, &range_len) != DDI_PROP_SUCCESS) { 5937 cmn_err(CE_CONT, "?pcic_apply_avail_ranges: " 5938 "no ranges property for pcmcia\n"); 5939 return (DDI_FAILURE); 5940 } 5941 5942 range_entries = range_len / sizeof (pcic_ranges_t); 5943 5944 /* for each "available" entry to be translated */ 5945 for (i = 0; i < entries; i++, pcic_p++, pci_p++) { 5946 int j; 5947 pcic_ranges_t *range_p = pcic_range_p; 5948 pci_p->pci_phys_hi = -1u; /* default invalid value */ 5949 5950 /* for each "ranges" entry to be searched */ 5951 for (j = 0; j < range_entries; j++, range_p++) { 5952 uint64_t range_end = range_p->pcic_range_caddrlo + 5953 range_p->pcic_range_size; 5954 uint64_t avail_end = pcic_p->phys_lo + pcic_p->phys_len; 5955 5956 if ((range_p->pcic_range_caddrhi != pcic_p->phys_hi) || 5957 (range_p->pcic_range_caddrlo > pcic_p->phys_lo) || 5958 (range_end < avail_end)) 5959 continue; 5960 5961 pci_p->pci_phys_hi = range_p->pcic_range_paddrhi; 5962 pci_p->pci_phys_mid = range_p->pcic_range_paddrmid; 5963 pci_p->pci_phys_low = range_p->pcic_range_paddrlo 5964 + (pcic_p->phys_lo - range_p->pcic_range_caddrlo); 5965 pci_p->pci_size_hi = 0; 5966 pci_p->pci_size_low = pcic_p->phys_len; 5967 } 5968 } 5969 kmem_free(pcic_range_p, range_len); 5970 return (DDI_SUCCESS); 5971 } 5972 5973 static int 5974 pcic_open(dev_t *dev, int flag, int otyp, cred_t *cred) 5975 { 5976 #ifdef CARDBUS 5977 if (cardbus_is_cb_minor(*dev)) 5978 return (cardbus_open(dev, flag, otyp, cred)); 5979 #endif 5980 return (EINVAL); 5981 } 5982 5983 static int 5984 pcic_close(dev_t dev, int flag, int otyp, cred_t *cred) 5985 { 5986 #ifdef CARDBUS 5987 if (cardbus_is_cb_minor(dev)) 5988 return (cardbus_close(dev, flag, otyp, cred)); 5989 #endif 5990 return (EINVAL); 5991 } 5992 5993 static int 5994 pcic_ioctl(dev_t dev, int cmd, intptr_t arg, int mode, cred_t *cred, 5995 int *rval) 5996 { 5997 #ifdef CARDBUS 5998 if (cardbus_is_cb_minor(dev)) 5999 return (cardbus_ioctl(dev, cmd, arg, mode, cred, rval)); 6000 #endif 6001 return (EINVAL); 6002 } 6003 6004 6005 static boolean_t 6006 pcic_load_cardbus(pcicdev_t *pcic, const pcic_socket_t *sockp) 6007 { 6008 uint32_t present_state; 6009 dev_info_t *dip = pcic->dip; 6010 set_socket_t s; 6011 get_socket_t g; 6012 boolean_t retval; 6013 unsigned vccLevel; 6014 6015 pcic_err(dip, 8, "entering pcic_load_cardbus\n"); 6016 6017 pcic_mutex_exit(&pcic->pc_lock); 6018 6019 bzero(&s, sizeof (set_socket_t)); 6020 s.socket = sockp->pcs_socket; 6021 s.SCIntMask = SBM_CD|SBM_RDYBSY; 6022 s.IFType = IF_CARDBUS; 6023 s.State = (unsigned)~0; 6024 6025 present_state = pcic_getcb(pcic, CB_PRESENT_STATE); 6026 if (present_state & PCIC_VCC_3VCARD) 6027 s.VccLevel = PCIC_VCC_3VLEVEL; 6028 else if (present_state & PCIC_VCC_5VCARD) 6029 s.VccLevel = PCIC_VCC_5VLEVEL; 6030 else { 6031 cmn_err(CE_CONT, 6032 "pcic_load_cardbus: unsupported card voltage\n"); 6033 goto failure; 6034 } 6035 vccLevel = s.VccLevel; 6036 s.Vpp1Level = s.Vpp2Level = 0; 6037 6038 if (pcic_set_socket(dip, &s) != SUCCESS) 6039 goto failure; 6040 6041 if (pcic_reset_socket(dip, sockp->pcs_socket, 6042 RESET_MODE_CARD_ONLY) != SUCCESS) 6043 goto failure; 6044 6045 bzero(&g, sizeof (get_socket_t)); 6046 g.socket = sockp->pcs_socket; 6047 if (pcic_get_socket(dip, &g) != SUCCESS) 6048 goto failure; 6049 6050 bzero(&s, sizeof (set_socket_t)); 6051 s.socket = sockp->pcs_socket; 6052 s.SCIntMask = SBM_CD; 6053 s.IREQRouting = g.IRQRouting; 6054 s.IFType = g.IFType; 6055 s.CtlInd = g.CtlInd; 6056 s.State = (unsigned)~0; 6057 s.VccLevel = vccLevel; 6058 s.Vpp1Level = s.Vpp2Level = 0; 6059 6060 if (pcic_set_socket(dip, &s) != SUCCESS) 6061 goto failure; 6062 6063 retval = cardbus_load_cardbus(dip, sockp->pcs_socket, pcic->pc_base); 6064 goto exit; 6065 6066 failure: 6067 retval = B_FALSE; 6068 6069 exit: 6070 pcic_mutex_enter(&pcic->pc_lock); 6071 pcic_err(dip, 8, "exit pcic_load_cardbus (%s)\n", 6072 retval ? "success" : "failure"); 6073 return (retval); 6074 } 6075 6076 static void 6077 pcic_unload_cardbus(pcicdev_t *pcic, const pcic_socket_t *sockp) 6078 { 6079 dev_info_t *dip = pcic->dip; 6080 set_socket_t s; 6081 6082 pcic_mutex_exit(&pcic->pc_lock); 6083 6084 cardbus_unload_cardbus(dip); 6085 6086 bzero(&s, sizeof (set_socket_t)); 6087 s.socket = sockp->pcs_socket; 6088 s.SCIntMask = SBM_CD|SBM_RDYBSY; 6089 s.IREQRouting = 0; 6090 s.IFType = IF_MEMORY; 6091 s.CtlInd = 0; 6092 s.State = 0; 6093 s.VccLevel = s.Vpp1Level = s.Vpp2Level = 0; 6094 6095 (void) pcic_set_socket(dip, &s); 6096 6097 pcic_mutex_enter(&pcic->pc_lock); 6098 } 6099 6100 static uint32_t 6101 pcic_getcb(pcicdev_t *pcic, int reg) 6102 { 6103 ASSERT(pcic->pc_io_type == PCIC_IO_TYPE_YENTA); 6104 6105 return (ddi_get32(pcic->handle, 6106 (uint32_t *)(pcic->ioaddr + CB_CB_OFFSET + reg))); 6107 } 6108 6109 static void 6110 pcic_putcb(pcicdev_t *pcic, int reg, uint32_t value) 6111 { 6112 ASSERT(pcic->pc_io_type == PCIC_IO_TYPE_YENTA); 6113 6114 ddi_put32(pcic->handle, 6115 (uint32_t *)(pcic->ioaddr + CB_CB_OFFSET + reg), value); 6116 } 6117 6118 static void 6119 pcic_enable_io_intr(pcicdev_t *pcic, int socket, int irq) 6120 { 6121 uint8_t value; 6122 uint16_t brdgctl; 6123 6124 value = pcic_getb(pcic, socket, PCIC_INTERRUPT) & ~PCIC_INTR_MASK; 6125 pcic_putb(pcic, socket, PCIC_INTERRUPT, value | irq); 6126 6127 switch (pcic->pc_type) { 6128 case PCIC_INTEL_i82092: 6129 pcic_82092_smiirq_ctl(pcic, socket, PCIC_82092_CTL_IRQ, 6130 PCIC_82092_INT_ENABLE); 6131 break; 6132 case PCIC_O2_OZ6912: 6133 value = pcic_getb(pcic, 0, PCIC_CENTDMA); 6134 value |= 0x8; 6135 pcic_putb(pcic, 0, PCIC_CENTDMA, value); 6136 break; 6137 case PCIC_CL_PD6832: 6138 case PCIC_TI_PCI1250: 6139 case PCIC_TI_PCI1221: 6140 case PCIC_TI_PCI1225: 6141 case PCIC_TI_PCI1410: 6142 case PCIC_ENE_1410: 6143 case PCIC_TI_PCI1510: 6144 case PCIC_TI_PCI1520: 6145 case PCIC_TI_PCI1420: 6146 case PCIC_ENE_1420: 6147 /* route card functional interrupts to PCI interrupts */ 6148 brdgctl = ddi_get16(pcic->cfg_handle, 6149 (uint16_t *)(pcic->cfgaddr + PCI_CBUS_BRIDGE_CTRL)); 6150 pcic_err(NULL, 1, 6151 "pcic_enable_io_intr brdgctl(0x%x) was: 0x%x\n", 6152 PCI_CBUS_BRIDGE_CTRL, brdgctl); 6153 brdgctl &= ~PCIC_BRDGCTL_INTR_MASK; 6154 ddi_put16(pcic->cfg_handle, 6155 (uint16_t *)(pcic->cfgaddr + PCI_CBUS_BRIDGE_CTRL), 6156 brdgctl); 6157 /* Flush the write */ 6158 (void) ddi_get16(pcic->cfg_handle, 6159 (uint16_t *)(pcic->cfgaddr + PCI_CBUS_BRIDGE_CTRL)); 6160 break; 6161 default: 6162 break; 6163 } 6164 } 6165 6166 static void 6167 pcic_disable_io_intr(pcicdev_t *pcic, int socket) 6168 { 6169 uint8_t value; 6170 uint16_t brdgctl; 6171 6172 value = pcic_getb(pcic, socket, PCIC_INTERRUPT) & ~PCIC_INTR_MASK; 6173 pcic_putb(pcic, socket, PCIC_INTERRUPT, value); 6174 6175 switch (pcic->pc_type) { 6176 case PCIC_INTEL_i82092: 6177 pcic_82092_smiirq_ctl(pcic, socket, PCIC_82092_CTL_IRQ, 6178 PCIC_82092_INT_DISABLE); 6179 break; 6180 case PCIC_O2_OZ6912: 6181 value = pcic_getb(pcic, 0, PCIC_CENTDMA); 6182 value &= ~0x8; 6183 pcic_putb(pcic, 0, PCIC_CENTDMA, value); 6184 /* Flush the write */ 6185 (void) pcic_getb(pcic, 0, PCIC_CENTDMA); 6186 break; 6187 case PCIC_CL_PD6832: 6188 case PCIC_TI_PCI1250: 6189 case PCIC_TI_PCI1221: 6190 case PCIC_TI_PCI1225: 6191 case PCIC_TI_PCI1410: 6192 case PCIC_ENE_1410: 6193 case PCIC_TI_PCI1510: 6194 case PCIC_TI_PCI1520: 6195 case PCIC_TI_PCI1420: 6196 case PCIC_ENE_1420: 6197 /* 6198 * This maps I/O interrupts to ExCA which 6199 * have been turned off by the write to 6200 * PCIC_INTERRUPT above. It would appear to 6201 * be the only way to actually turn I/O Ints off 6202 * while retaining CS Ints. 6203 */ 6204 brdgctl = ddi_get16(pcic->cfg_handle, 6205 (uint16_t *)(pcic->cfgaddr + PCI_CBUS_BRIDGE_CTRL)); 6206 pcic_err(NULL, 1, 6207 "pcic_disable_io_intr brdgctl(0x%x) was: 0x%x\n", 6208 PCI_CBUS_BRIDGE_CTRL, brdgctl); 6209 brdgctl |= PCIC_BRDGCTL_INTR_MASK; 6210 ddi_put16(pcic->cfg_handle, 6211 (uint16_t *)(pcic->cfgaddr + PCI_CBUS_BRIDGE_CTRL), 6212 brdgctl); 6213 /* Flush the write */ 6214 (void) ddi_get16(pcic->cfg_handle, 6215 (uint16_t *)(pcic->cfgaddr + PCI_CBUS_BRIDGE_CTRL)); 6216 break; 6217 default: 6218 break; 6219 } 6220 } 6221 6222 static void 6223 pcic_cb_enable_intr(dev_info_t *dip) 6224 { 6225 anp_t *anp = ddi_get_driver_private(dip); 6226 pcicdev_t *pcic = anp->an_private; 6227 6228 mutex_enter(&pcic->pc_lock); 6229 pcic_enable_io_intr(pcic, 0, pcic->pc_sockets[0].pcs_irq); 6230 mutex_exit(&pcic->pc_lock); 6231 } 6232 6233 static void 6234 pcic_cb_disable_intr(dev_info_t *dip) 6235 { 6236 anp_t *anp = ddi_get_driver_private(dip); 6237 pcicdev_t *pcic = anp->an_private; 6238 6239 mutex_enter(&pcic->pc_lock); 6240 pcic_disable_io_intr(pcic, 0); 6241 mutex_exit(&pcic->pc_lock); 6242 } 6243 6244 static int 6245 log_pci_cfg_err(ushort_t e, int bridge_secondary) 6246 { 6247 int nerr = 0; 6248 if (e & PCI_STAT_PERROR) { 6249 nerr++; 6250 cmn_err(CE_CONT, "detected parity error.\n"); 6251 } 6252 if (e & PCI_STAT_S_SYSERR) { 6253 nerr++; 6254 if (bridge_secondary) 6255 cmn_err(CE_CONT, "received system error.\n"); 6256 else 6257 cmn_err(CE_CONT, "signalled system error.\n"); 6258 } 6259 if (e & PCI_STAT_R_MAST_AB) { 6260 nerr++; 6261 cmn_err(CE_CONT, "received master abort.\n"); 6262 } 6263 if (e & PCI_STAT_R_TARG_AB) 6264 cmn_err(CE_CONT, "received target abort.\n"); 6265 if (e & PCI_STAT_S_TARG_AB) 6266 cmn_err(CE_CONT, "signalled target abort\n"); 6267 if (e & PCI_STAT_S_PERROR) { 6268 nerr++; 6269 cmn_err(CE_CONT, "signalled parity error\n"); 6270 } 6271 return (nerr); 6272 } 6273 6274 #if defined(__sparc) 6275 static int 6276 pcic_fault(enum pci_fault_ops op, void *arg) 6277 { 6278 pcicdev_t *pcic = (pcicdev_t *)arg; 6279 ushort_t pci_cfg_stat = 6280 pci_config_get16(pcic->cfg_handle, PCI_CONF_STAT); 6281 ushort_t pci_cfg_sec_stat = 6282 pci_config_get16(pcic->cfg_handle, 0x16); 6283 char nm[24]; 6284 int nerr = 0; 6285 6286 cardbus_dump_pci_config(pcic->dip); 6287 6288 switch (op) { 6289 case FAULT_LOG: 6290 (void) sprintf(nm, "%s-%d", ddi_driver_name(pcic->dip), 6291 ddi_get_instance(pcic->dip)); 6292 6293 cmn_err(CE_WARN, "%s: PCIC fault log start:\n", nm); 6294 cmn_err(CE_WARN, "%s: primary err (%x):\n", nm, pci_cfg_stat); 6295 nerr += log_pci_cfg_err(pci_cfg_stat, 0); 6296 cmn_err(CE_WARN, "%s: sec err (%x):\n", nm, pci_cfg_sec_stat); 6297 nerr += log_pci_cfg_err(pci_cfg_sec_stat, 1); 6298 cmn_err(CE_CONT, "%s: PCI fault log end.\n", nm); 6299 return (nerr); 6300 case FAULT_POKEFINI: 6301 case FAULT_RESET: 6302 pci_config_put16(pcic->cfg_handle, 6303 PCI_CONF_STAT, pci_cfg_stat); 6304 pci_config_put16(pcic->cfg_handle, 0x16, pci_cfg_sec_stat); 6305 break; 6306 case FAULT_POKEFLT: 6307 if (!(pci_cfg_stat & PCI_STAT_S_SYSERR)) 6308 return (1); 6309 if (!(pci_cfg_sec_stat & PCI_STAT_R_MAST_AB)) 6310 return (1); 6311 break; 6312 default: 6313 break; 6314 } 6315 return (DDI_SUCCESS); 6316 } 6317 #endif 6318 6319 static void 6320 pcic_delayed_resume(void *arg) 6321 { 6322 int i, j, interrupt; 6323 anp_t *pcic_nexus; 6324 pcicdev_t *pcic; 6325 6326 _NOTE(ARGUNUSED(arg)) 6327 6328 #if defined(PCIC_DEBUG) 6329 pcic_err(NULL, 6, "pcic_delayed_resume(): entered\n"); 6330 #endif 6331 for (j = 0; j <= pcic_maxinst; j++) { 6332 6333 pcic_nexus = ddi_get_soft_state(pcic_soft_state_p, j); 6334 if (!pcic_nexus) 6335 continue; 6336 pcic = (pcicdev_t *)pcic_nexus->an_private; 6337 if (!pcic) 6338 continue; 6339 6340 pcic_mutex_enter(&pcic->pc_lock); /* protect the registers */ 6341 for (i = 0; i < pcic->pc_numsockets; i++) { 6342 /* Enable interrupts on PCI if needs be */ 6343 interrupt = pcic_getb(pcic, i, PCIC_INTERRUPT); 6344 if (pcic->pc_flags & PCF_USE_SMI) 6345 interrupt |= PCIC_INTR_ENABLE; 6346 pcic_putb(pcic, i, PCIC_INTERRUPT, 6347 PCIC_RESET | interrupt); 6348 pcic->pc_sockets[i].pcs_debounce_id = 6349 pcic_add_debqueue(&pcic->pc_sockets[i], 6350 drv_usectohz(pcic_debounce_time)); 6351 } 6352 pcic_mutex_exit(&pcic->pc_lock); /* protect the registers */ 6353 if (pcic_do_pcmcia_sr) 6354 (void) pcmcia_wait_insert(pcic->dip); 6355 } 6356 } 6357 6358 static void 6359 pcic_debounce(pcic_socket_t *pcs) 6360 { 6361 uint8_t status, stschng; 6362 6363 pcic_mutex_enter(&pcs->pcs_pcic->pc_lock); 6364 pcs->pcs_flags &= ~PCS_STARTING; 6365 stschng = pcic_getb(pcs->pcs_pcic, pcs->pcs_socket, 6366 PCIC_CARD_STATUS_CHANGE); 6367 status = pcic_getb(pcs->pcs_pcic, pcs->pcs_socket, 6368 PCIC_INTERFACE_STATUS); 6369 #ifdef PCIC_DEBUG 6370 pcic_err(pcs->pcs_pcic->dip, 8, 6371 "pcic_debounce(0x%p, dip=0x%p) socket %d st 0x%x " 6372 "chg 0x%x flg 0x%x\n", 6373 (void *)pcs, (void *) pcs->pcs_pcic->dip, pcs->pcs_socket, 6374 status, stschng, pcs->pcs_flags); 6375 #endif 6376 6377 pcic_putb(pcs->pcs_pcic, pcs->pcs_socket, PCIC_CARD_STATUS_CHANGE, 6378 PCIC_CD_DETECT); 6379 pcic_handle_cd_change(pcs->pcs_pcic, pcs, status); 6380 pcic_mutex_exit(&pcs->pcs_pcic->pc_lock); 6381 } 6382 6383 static void 6384 pcic_deb_thread() 6385 { 6386 callb_cpr_t cprinfo; 6387 struct debounce *debp; 6388 clock_t lastt; 6389 6390 CALLB_CPR_INIT(&cprinfo, &pcic_deb_mtx, 6391 callb_generic_cpr, "pcic debounce thread"); 6392 mutex_enter(&pcic_deb_mtx); 6393 while (pcic_deb_threadid) { 6394 while (pcic_deb_queue) { 6395 #ifdef PCIC_DEBUG 6396 pcic_dump_debqueue("Thread"); 6397 #endif 6398 debp = pcic_deb_queue; 6399 (void) drv_getparm(LBOLT, &lastt); 6400 if (lastt >= debp->expire) { 6401 pcic_deb_queue = debp->next; 6402 mutex_exit(&pcic_deb_mtx); 6403 pcic_debounce(debp->pcs); 6404 mutex_enter(&pcic_deb_mtx); 6405 kmem_free(debp, sizeof (*debp)); 6406 } else { 6407 (void) cv_timedwait(&pcic_deb_cv, 6408 &pcic_deb_mtx, debp->expire); 6409 } 6410 } 6411 CALLB_CPR_SAFE_BEGIN(&cprinfo); 6412 cv_wait(&pcic_deb_cv, &pcic_deb_mtx); 6413 CALLB_CPR_SAFE_END(&cprinfo, &pcic_deb_mtx); 6414 } 6415 pcic_deb_threadid = (kthread_t *)1; 6416 cv_signal(&pcic_deb_cv); 6417 CALLB_CPR_EXIT(&cprinfo); /* Also exits the mutex */ 6418 thread_exit(); 6419 } 6420 6421 static void * 6422 pcic_add_debqueue(pcic_socket_t *pcs, int clocks) 6423 { 6424 clock_t lbolt; 6425 struct debounce *dbp, **dbpp = &pcic_deb_queue; 6426 6427 (void) drv_getparm(LBOLT, &lbolt); 6428 dbp = kmem_alloc(sizeof (struct debounce), KM_SLEEP); 6429 6430 dbp->expire = lbolt + clocks; 6431 dbp->pcs = pcs; 6432 mutex_enter(&pcic_deb_mtx); 6433 while (*dbpp) { 6434 if (dbp->expire > (*dbpp)->expire) 6435 dbpp = &((*dbpp)->next); 6436 else 6437 break; 6438 } 6439 dbp->next = *dbpp; 6440 *dbpp = dbp; 6441 #ifdef PCIC_DEBUG 6442 pcic_dump_debqueue("Add"); 6443 #endif 6444 cv_signal(&pcic_deb_cv); 6445 mutex_exit(&pcic_deb_mtx); 6446 return (dbp); 6447 } 6448 6449 static void 6450 pcic_rm_debqueue(void *id) 6451 { 6452 struct debounce *dbp, **dbpp = &pcic_deb_queue; 6453 6454 dbp = (struct debounce *)id; 6455 mutex_enter(&pcic_deb_mtx); 6456 while (*dbpp) { 6457 if (*dbpp == dbp) { 6458 *dbpp = dbp->next; 6459 kmem_free(dbp, sizeof (*dbp)); 6460 #ifdef PCIC_DEBUG 6461 pcic_dump_debqueue("Remove"); 6462 #endif 6463 cv_signal(&pcic_deb_cv); 6464 mutex_exit(&pcic_deb_mtx); 6465 return; 6466 } 6467 dbpp = &((*dbpp)->next); 6468 } 6469 pcic_err(NULL, 6, "pcic: Failed to find debounce id 0x%p\n", id); 6470 mutex_exit(&pcic_deb_mtx); 6471 } 6472 6473 6474 static int pcic_powerdelay = 0; 6475 6476 static int 6477 pcic_exca_powerctl(pcicdev_t *pcic, int socket, int powerlevel) 6478 { 6479 int ind, value, orig_pwrctl; 6480 6481 /* power setup -- if necessary */ 6482 orig_pwrctl = pcic_getb(pcic, socket, PCIC_POWER_CONTROL); 6483 6484 #if defined(PCIC_DEBUG) 6485 pcic_err(pcic->dip, 6, 6486 "pcic_exca_powerctl(socket %d) powerlevel=%x orig 0x%x\n", 6487 socket, powerlevel, orig_pwrctl); 6488 #endif 6489 /* Preserve the PCIC_OUTPUT_ENABLE (control lines output enable) bit. */ 6490 powerlevel = (powerlevel & ~POWER_OUTPUT_ENABLE) | 6491 (orig_pwrctl & POWER_OUTPUT_ENABLE); 6492 if (powerlevel != orig_pwrctl) { 6493 if (powerlevel & ~POWER_OUTPUT_ENABLE) { 6494 int ifs; 6495 /* 6496 * set power to socket 6497 * note that the powerlevel was calculated earlier 6498 */ 6499 pcic_putb(pcic, socket, PCIC_POWER_CONTROL, powerlevel); 6500 (void) pcic_getb(pcic, socket, PCIC_POWER_CONTROL); 6501 6502 /* 6503 * this second write to the power control register 6504 * is needed to resolve a problem on 6505 * the IBM ThinkPad 750 6506 * where the first write doesn't latch. 6507 * The second write appears to always work and 6508 * doesn't hurt the operation of other chips 6509 * so we can just use it -- this is good since we can't 6510 * determine what chip the 750 actually uses 6511 * (I suspect an early Ricoh). 6512 */ 6513 pcic_putb(pcic, socket, PCIC_POWER_CONTROL, powerlevel); 6514 6515 value = pcic_getb(pcic, socket, PCIC_POWER_CONTROL); 6516 pcic_mswait(pcic, socket, pcic_powerdelay); 6517 #if defined(PCIC_DEBUG) 6518 pcic_err(pcic->dip, 8, 6519 "\tpowerlevel reg = %x (ifs %x)\n", 6520 value, pcic_getb(pcic, socket, 6521 PCIC_INTERFACE_STATUS)); 6522 pcic_err(pcic->dip, 8, 6523 "CBus regs: PS 0x%x, Control 0x%x\n", 6524 pcic_getcb(pcic, CB_PRESENT_STATE), 6525 pcic_getcb(pcic, CB_CONTROL)); 6526 #endif 6527 /* 6528 * since power was touched, make sure it says it 6529 * is on. This lets it become stable. 6530 */ 6531 for (ind = 0; ind < 20; ind++) { 6532 ifs = pcic_getb(pcic, socket, 6533 PCIC_INTERFACE_STATUS); 6534 if (ifs & PCIC_POWER_ON) 6535 break; 6536 else { 6537 pcic_putb(pcic, socket, 6538 PCIC_POWER_CONTROL, 0); 6539 (void) pcic_getb(pcic, socket, 6540 PCIC_POWER_CONTROL); 6541 pcic_mswait(pcic, socket, 40); 6542 if (ind == 10) { 6543 pcic_putcb(pcic, CB_EVENT_FORCE, 6544 CB_EF_CVTEST); 6545 pcic_mswait(pcic, socket, 100); 6546 } 6547 pcic_putb(pcic, socket, 6548 PCIC_POWER_CONTROL, 6549 powerlevel & ~POWER_OUTPUT_ENABLE); 6550 (void) pcic_getb(pcic, socket, 6551 PCIC_POWER_CONTROL); 6552 pcic_mswait(pcic, socket, 6553 pcic_powerdelay); 6554 pcic_putb(pcic, socket, 6555 PCIC_POWER_CONTROL, powerlevel); 6556 (void) pcic_getb(pcic, socket, 6557 PCIC_POWER_CONTROL); 6558 pcic_mswait(pcic, socket, 6559 pcic_powerdelay); 6560 } 6561 } 6562 6563 if (!(ifs & PCIC_POWER_ON)) { 6564 cmn_err(CE_WARN, 6565 "pcic socket %d: Power didn't get turned" 6566 "on!\nif status 0x%x pwrc 0x%x(x%x) " 6567 "misc1 0x%x igc 0x%x ind %d\n", 6568 socket, ifs, 6569 pcic_getb(pcic, socket, PCIC_POWER_CONTROL), 6570 orig_pwrctl, 6571 pcic_getb(pcic, socket, PCIC_MISC_CTL_1), 6572 pcic_getb(pcic, socket, PCIC_INTERRUPT), 6573 ind); 6574 return (BAD_VCC); 6575 } 6576 #if defined(PCIC_DEBUG) 6577 pcic_err(pcic->dip, 8, 6578 "\tind = %d, if status %x pwrc 0x%x " 6579 "misc1 0x%x igc 0x%x\n", 6580 ind, ifs, 6581 pcic_getb(pcic, socket, PCIC_POWER_CONTROL), 6582 pcic_getb(pcic, socket, PCIC_MISC_CTL_1), 6583 pcic_getb(pcic, socket, PCIC_INTERRUPT)); 6584 #endif 6585 } else { 6586 /* explicitly turned off the power */ 6587 pcic_putb(pcic, socket, PCIC_POWER_CONTROL, powerlevel); 6588 (void) pcic_getb(pcic, socket, PCIC_POWER_CONTROL); 6589 } 6590 } 6591 return (SUCCESS); 6592 } 6593 6594 static int pcic_cbdoreset_during_poweron = 1; 6595 static int 6596 pcic_cbus_powerctl(pcicdev_t *pcic, int socket) 6597 { 6598 uint32_t cbctl = 0, orig_cbctl, cbstev, cbps; 6599 int ind, iobits; 6600 pcic_socket_t *sockp = &pcic->pc_sockets[socket]; 6601 6602 pcic_putcb(pcic, CB_STATUS_EVENT, CB_SE_POWER_CYCLE); 6603 6604 ind = pcic_power[sockp->pcs_vpp1].PowerLevel/10; 6605 cbctl |= pcic_cbv_levels[ind]; 6606 6607 ind = pcic_power[sockp->pcs_vcc].PowerLevel/10; 6608 cbctl |= (pcic_cbv_levels[ind]<<4); 6609 6610 orig_cbctl = pcic_getcb(pcic, CB_CONTROL); 6611 6612 #if defined(PCIC_DEBUG) 6613 pcic_err(pcic->dip, 6, 6614 "pcic_cbus_powerctl(socket %d) vcc %d vpp1 %d " 6615 "cbctl 0x%x->0x%x\n", 6616 socket, sockp->pcs_vcc, sockp->pcs_vpp1, orig_cbctl, cbctl); 6617 #endif 6618 if (cbctl != orig_cbctl) { 6619 if (pcic_cbdoreset_during_poweron && 6620 (orig_cbctl & (CB_C_VCCMASK|CB_C_VPPMASK)) == 0) { 6621 iobits = pcic_getb(pcic, socket, PCIC_INTERRUPT); 6622 pcic_putb(pcic, socket, PCIC_INTERRUPT, iobits & ~PCIC_RESET); 6623 } 6624 pcic_putcb(pcic, CB_CONTROL, cbctl); 6625 6626 if ((cbctl & CB_C_VCCMASK) == (orig_cbctl & CB_C_VCCMASK)) { 6627 pcic_mswait(pcic, socket, pcic_powerdelay); 6628 return (SUCCESS); 6629 } 6630 for (ind = 0; ind < 20; ind++) { 6631 cbstev = pcic_getcb(pcic, CB_STATUS_EVENT); 6632 6633 if (cbstev & CB_SE_POWER_CYCLE) { 6634 6635 /* 6636 * delay 400 ms: though the standard defines that the Vcc 6637 * set-up time is 20 ms, some PC-Card bridge requires longer 6638 * duration. 6639 * Note: We should check the status AFTER the delay to give time 6640 * for things to stabilize. 6641 */ 6642 pcic_mswait(pcic, socket, 400); 6643 6644 cbps = pcic_getcb(pcic, CB_PRESENT_STATE); 6645 if (cbctl && !(cbps & CB_PS_POWER_CYCLE)) { 6646 /* break; */ 6647 cmn_err(CE_WARN, "cbus_powerctl: power off??\n"); 6648 } 6649 if (cbctl & CB_PS_BADVCC) { 6650 cmn_err(CE_WARN, "cbus_powerctl: bad power request\n"); 6651 break; 6652 } 6653 6654 #if defined(PCIC_DEBUG) 6655 pcic_err(pcic->dip, 8, 6656 "cbstev = 0x%x cbps = 0x%x cbctl 0x%x(0x%x)", 6657 cbstev, pcic_getcb(pcic, CB_PRESENT_STATE), 6658 cbctl, orig_cbctl); 6659 #endif 6660 if (pcic_cbdoreset_during_poweron && 6661 (orig_cbctl & (CB_C_VCCMASK|CB_C_VPPMASK)) == 0) { 6662 pcic_putb(pcic, socket, PCIC_INTERRUPT, iobits); 6663 } 6664 return (SUCCESS); 6665 } 6666 pcic_mswait(pcic, socket, 40); 6667 } 6668 if (pcic_cbdoreset_during_poweron && 6669 (orig_cbctl & (CB_C_VCCMASK|CB_C_VPPMASK)) == 0) { 6670 pcic_putb(pcic, socket, PCIC_INTERRUPT, iobits); 6671 } 6672 cmn_err(CE_WARN, 6673 "pcic socket %d: Power didn't get turned on/off!\n" 6674 "cbstev = 0x%x cbps = 0x%x cbctl 0x%x(0x%x) " 6675 "vcc %d vpp1 %d", socket, cbstev, 6676 pcic_getcb(pcic, CB_PRESENT_STATE), 6677 cbctl, orig_cbctl, sockp->pcs_vcc, sockp->pcs_vpp1); 6678 return (BAD_VCC); 6679 } 6680 return (SUCCESS); 6681 } 6682 6683 static int pcic_do_pprintf = 0; 6684 6685 static void 6686 pcic_dump_debqueue(char *msg) 6687 { 6688 struct debounce *debp = pcic_deb_queue; 6689 clock_t lbolt; 6690 6691 (void) drv_getparm(LBOLT, &lbolt); 6692 pcic_err(NULL, 6, debp ? "pcic debounce list (%s) lbolt 0x%x:\n" : 6693 "pcic debounce_list (%s) EMPTY lbolt 0x%x\n", msg, lbolt); 6694 while (debp) { 6695 pcic_err(NULL, 6, "%p: exp 0x%x next 0x%p id 0x%p\n", 6696 (void *) debp, (int)debp->expire, (void *) debp->next, 6697 debp->pcs->pcs_debounce_id); 6698 debp = debp->next; 6699 } 6700 } 6701 6702 6703 /* PRINTFLIKE3 */ 6704 static void 6705 pcic_err(dev_info_t *dip, int level, const char *fmt, ...) 6706 { 6707 if (pcic_debug && (level <= pcic_debug)) { 6708 va_list adx; 6709 int instance; 6710 char buf[256]; 6711 const char *name; 6712 #if !defined(PCIC_DEBUG) 6713 int ce; 6714 char qmark = 0; 6715 6716 if (level <= 3) 6717 ce = CE_WARN; 6718 else 6719 ce = CE_CONT; 6720 if (level == 4) 6721 qmark = 1; 6722 #endif 6723 6724 if (dip) { 6725 instance = ddi_get_instance(dip); 6726 /* name = ddi_binding_name(dip); */ 6727 name = ddi_driver_name(dip); 6728 } else { 6729 instance = 0; 6730 name = ""; 6731 } 6732 6733 va_start(adx, fmt); 6734 (void) vsprintf(buf, fmt, adx); 6735 va_end(adx); 6736 6737 #if defined(PCIC_DEBUG) 6738 if (pcic_do_pprintf) { 6739 if (dip) { 6740 if (instance >= 0) 6741 prom_printf("%s(%d),0x%p: %s", name, 6742 instance, dip, buf); 6743 else 6744 prom_printf("%s,0x%p: %s", 6745 name, dip, buf); 6746 } else 6747 prom_printf(buf); 6748 } else { 6749 if (dip) { 6750 if (instance >= 0) 6751 cmn_err(CE_CONT, "%s(%d),0x%p: %s", 6752 name, instance, (void *) dip, buf); 6753 else 6754 cmn_err(CE_CONT, "%s,0x%p: %s", 6755 name, (void *) dip, buf); 6756 } else 6757 cmn_err(CE_CONT, buf); 6758 } 6759 #else 6760 if (dip) 6761 cmn_err(ce, qmark ? "?%s%d: %s" : "%s%d: %s", name, 6762 instance, buf); 6763 else 6764 cmn_err(ce, qmark ? "?%s" : buf, buf); 6765 #endif 6766 } 6767 } 6768